Corrected the mess caused by introducing default_nettype none into the design
verification netlists. Also cleaned up the broken power-on-reset signaling,
and added connections from the user space to the I/O pad direct-to-pad analog
signal pins.
diff --git a/verilog/rtl/ring_osc2x13.v b/verilog/rtl/ring_osc2x13.v
index 719da6e..324c2c7 100644
--- a/verilog/rtl/ring_osc2x13.v
+++ b/verilog/rtl/ring_osc2x13.v
@@ -9,7 +9,7 @@
input [1:0] trim;
output out;
- wire d0, d1, d2;
+ wire d0, d1, d2, ts;
sky130_fd_sc_hd__clkbuf_2 delaybuf0 (
.A(in),
@@ -232,3 +232,4 @@
`endif // !FUNCTIONAL
endmodule
+`default_nettype wire
