Corrected the mess caused by introducing default_nettype none into the design
verification netlists. Also cleaned up the broken power-on-reset signaling,
and added connections from the user space to the I/O pad direct-to-pad analog
signal pins.
diff --git a/verilog/rtl/mgmt_soc.v b/verilog/rtl/mgmt_soc.v
index 8d3e1f7..17a73f4 100644
--- a/verilog/rtl/mgmt_soc.v
+++ b/verilog/rtl/mgmt_soc.v
@@ -321,6 +321,10 @@
wire irq_spi_master;
wire irq_counter_timer0;
wire irq_counter_timer1;
+ wire ser_tx;
+
+ wire wb_clk_i;
+ wire wb_rst_i;
assign irq_stall = 0;
assign irq_7 = (irq_7_inputsrc == 1'b1) ? mgmt_in_data[7] : 1'b0;
@@ -352,6 +356,7 @@
wire cpu_stb_o;
wire [31:0] cpu_dat_o;
wire cpu_ack_i;
+ wire mem_instr;
picorv32_wb #(
.STACKADDR(STACKADDR),
@@ -845,3 +850,4 @@
assign rdata1 = regs[raddr1[4:0]];
assign rdata2 = regs[raddr2[4:0]];
endmodule
+`default_nettype wire
