Corrected the mess caused by introducing default_nettype none into the design
verification netlists. Also cleaned up the broken power-on-reset signaling,
and added connections from the user space to the I/O pad direct-to-pad analog
signal pins.
diff --git a/verilog/rtl/clock_div.v b/verilog/rtl/clock_div.v
index 54bf194..4b698a4 100644
--- a/verilog/rtl/clock_div.v
+++ b/verilog/rtl/clock_div.v
@@ -1,5 +1,5 @@
-`default_nettype none
/* Integer-N clock divider */
+`default_nettype none
module clock_div #(
parameter SIZE = 3 // Number of bits for the divider value
@@ -194,3 +194,4 @@
end
endmodule //even
+`default_nettype wire
