Added two additional features: (1) Timer chaining, which allows one
timer to be clocked from the output of the other, forming a 64-bit
timer, and (2) User power-good signal, memory-mapped so that the state
of the user's 1.8V power domain can be assessed (should have the same
for the 3.3V domains). Also: The routing of the PLL output and trap
and IRQ inputs was moved from the single gpio pin to additional bits
in the user space, and an additional output routing was made for the
secondary clock.
diff --git a/verilog/dv/caravel/defs.h b/verilog/dv/caravel/defs.h
index 96630f1..abfcd44 100644
--- a/verilog/dv/caravel/defs.h
+++ b/verilog/dv/caravel/defs.h
@@ -106,9 +106,11 @@
#define reg_spimaster_data (*(volatile uint32_t*)0x24000004)
// System Area (0x2F00_0000)
-#define reg_pll_out_dest (*(volatile uint32_t*)0x2F00000c)
-#define reg_trap_out_dest (*(volatile uint32_t*)0x2F000010)
-#define reg_irq7_source (*(volatile uint32_t*)0x2F000014)
+#define reg_clk1_out_dest (*(volatile uint32_t*)0x2F000000)
+#define reg_clk2_out_dest (*(volatile uint32_t*)0x2F000004)
+#define reg_trap_out_dest (*(volatile uint32_t*)0x2F000008)
+#define reg_irq7_source (*(volatile uint32_t*)0x2F00000C)
+#define reg_irq8_source (*(volatile uint32_t*)0x2F000010)
// Crossbar Slave Addresses (0x8000_0000 - 0xB000_0000)
#define qspi_ctrl_slave (*(volatile uint32_t*)0x80000000)
diff --git a/verilog/dv/wb_utests/sysctrl_wb/sysctrl_wb_tb.v b/verilog/dv/wb_utests/sysctrl_wb/sysctrl_wb_tb.v
index b4fc6a5..0086016 100644
--- a/verilog/dv/wb_utests/sysctrl_wb/sysctrl_wb_tb.v
+++ b/verilog/dv/wb_utests/sysctrl_wb/sysctrl_wb_tb.v
@@ -46,13 +46,17 @@
integer i;
// System Control Default Register Addresses
- wire [31:0] pll_out_adr = uut.BASE_ADR | uut.PLL_OUT;
+ wire [31:0] clk1_out_adr = uut.BASE_ADR | uut.CLK1_OUT;
+ wire [31:0] clk2_out_adr = uut.BASE_ADR | uut.CLK2_OUT;
wire [31:0] trap_out_adr = uut.BASE_ADR | uut.TRAP_OUT;
wire [31:0] irq7_src_adr = uut.BASE_ADR | uut.IRQ7_SRC;
+ wire [31:0] irq8_src_adr = uut.BASE_ADR | uut.IRQ8_SRC;
- reg pll_output_dest;
+ reg clk1_output_dest;
+ reg clk2_output_dest;
reg trap_output_dest;
reg irq_7_inputsrc;
+ reg irq_8_inputsrc;
initial begin
// Reset Operation
@@ -61,18 +65,28 @@
wb_rst_i = 0;
#2;
- pll_output_dest = 1'b1;
+ clk1_output_dest = 1'b1;
+ clk2_output_dest = 1'b1;
trap_output_dest = 1'b1;
irq_7_inputsrc = 1'b1;
+ irq_8_inputsrc = 1'b1;
// Write to System Control Registers
- write(pll_out_adr, pll_output_dest);
+ write(clk1_out_adr, clk1_output_dest);
+ write(clk2_out_adr, clk2_output_dest);
write(trap_out_adr, trap_output_dest);
write(irq7_src_adr, irq_7_inputsrc);
+ write(irq8_src_adr, irq_8_inputsrc);
#2;
- read(pll_out_adr);
- if (wb_dat_o !== pll_output_dest) begin
- $display("Error reading PLL output destination register.");
+ read(clk1_out_adr);
+ if (wb_dat_o !== clk1_output_dest) begin
+ $display("Error reading CLK1 output destination register.");
+ $finish;
+ end
+
+ read(clk2_out_adr);
+ if (wb_dat_o !== clk2_output_dest) begin
+ $display("Error reading CLK2 output destination register.");
$finish;
end
@@ -88,6 +102,12 @@
$finish;
end
+ read(irq8_src_adr);
+ if (wb_dat_o !== irq_8_inputsrc) begin
+ $display("Error reading IRQ8 input source register.");
+ $finish;
+ end
+
$display("Success!");
$finish;
end
