commit 27200e957abe57219655ca559a260bd43b6e2990
author Ahmed Ghazy <ax3ghazy@aucegypt.edu> Wed Nov 25 22:07:02 2020 +0200
committer Ahmed Ghazy <ax3ghazy@aucegypt.edu> Wed Nov 25 22:07:02 2020 +0200
tree 2faf4fd70a5b0b9f90fab48fa81d454aa666fffd
parent 365f5d7971bf26680fc4cf64d52e4de44bd3eb19

Add more missing USE_POWER_PINS

- in user_id_programming and simple_por

verilog/rtl/simple_por.v

diff --git a/verilog/rtl/simple_por.v b/verilog/rtl/simple_por.v
index f04fa5c..7fef90d 100644
--- a/verilog/rtl/simple_por.v
+++ b/verilog/rtl/simple_por.v
@@ -2,9 +2,11 @@
 `timescale 1 ns / 1 ps
 
 module simple_por(
+`ifdef USE_POWER_PINS
     inout vdd3v3,
     inout vdd1v8,
     inout vss,
+`endif
     output porb_h,
     output porb_l,
     output por_l