Finished implementation of the simple_por Power-on-reset circuit. Completed DRC and LVS,
and testbench simulation in ngspice.
diff --git a/ngspice/.simple_por.spice.swp b/ngspice/.simple_por.spice.swp
new file mode 100644
index 0000000..d42a22f
--- /dev/null
+++ b/ngspice/.simple_por.spice.swp
Binary files differ
diff --git a/ngspice/simple_por.spice b/ngspice/simple_por.spice
index 91dc66f..18065b8 100644
--- a/ngspice/simple_por.spice
+++ b/ngspice/simple_por.spice
@@ -24,49 +24,49 @@
* Actual response of this circuit by ngspice simulation is 15ms.
*-------------------------------------------------------------------
-.subckt simple_por vdda vccd vss por_h por_l porb_l
+.subckt simple_por vdd3v3 vdd1v8 vss porb_h por_l porb_l
Xcap1 vcap vss sky130_fd_pr__cap_mim_m3_1 l=30 w=30
-Xcap2 vcap vss sky130_fd_pr__cap_mim_m3_2 l=30 w=30
+Xcap2 vss vcap sky130_fd_pr__cap_mim_m3_2 l=30 w=30
* Note: 20 resistors of length 25um connected in series
-Xres1 vdda vin vss sky130_fd_pr__res_xhigh_po_0p69 l=500
+Xres1 vdd3v3 vin vss sky130_fd_pr__res_xhigh_po_0p69 l=500
* Note: 6 resistors of length 25um connected in series
Xres2 vin vss vss sky130_fd_pr__res_xhigh_po_0p69 l=150
* Note: 2 dummy resistors of length 25um
Xres3 vss vss vss sky130_fd_pr__res_xhigh_po_0p69 l=50
* Triple current mirror, ratios 8:1, 7:1, and 7:1, with p-cascodes
-* D G S B
-Xm1 casc1 vin vss vss sky130_fd_pr__nfet_g5v0d10v5 w=2 l=0.8 m=1
-Xc1 mir1 casc1 casc1 vdda sky130_fd_pr__pfet_g5v0d10v5 w=2 l=0.8 m=1
-Xm2 mir1 mir1 vdda vdda sky130_fd_pr__pfet_g5v0d10v5 w=2 l=0.8 m=8
-Xm3 mir2 mir1 vdda vdda sky130_fd_pr__pfet_g5v0d10v5 w=2 l=0.8 m=1
-Xc2 casc2 casc1 mir2 vdda sky130_fd_pr__pfet_g5v0d10v5 w=2 l=0.8 m=1
-Xm4 casc2 casc2 vss vss sky130_fd_pr__nfet_g5v0d10v5 w=2 l=0.8 m=7
-Xm5 casc3 casc2 vss vss sky130_fd_pr__nfet_g5v0d10v5 w=2 l=0.8 m=1
-Xc3 mir3 casc3 casc3 vdda sky130_fd_pr__pfet_g5v0d10v5 w=2 l=0.8 m=1
-Xm6 mir3 mir3 vdda vdda sky130_fd_pr__pfet_g5v0d10v5 w=2 l=0.8 m=7
-Xm7 mir4 mir3 vdda vdda sky130_fd_pr__pfet_g5v0d10v5 w=2 l=0.8 m=1
-Xc4 vcap casc3 mir4 vdda sky130_fd_pr__pfet_g5v0d10v5 w=2 l=0.8 m=1
+* D G S B
+Xm1 casc1 vin vss vss sky130_fd_pr__nfet_g5v0d10v5 w=2 l=0.8 m=1
+Xc1 mir1 casc1 casc1 vdd3v3 sky130_fd_pr__pfet_g5v0d10v5 w=2 l=0.8 m=1
+Xm2 mir1 mir1 vdd3v3 vdd3v3 sky130_fd_pr__pfet_g5v0d10v5 w=2 l=0.8 m=8
+Xm3 mir2 mir1 vdd3v3 vdd3v3 sky130_fd_pr__pfet_g5v0d10v5 w=2 l=0.8 m=1
+Xc2 casc2 casc1 mir2 vdd3v3 sky130_fd_pr__pfet_g5v0d10v5 w=2 l=0.8 m=1
+Xm4 casc2 casc2 vss vss sky130_fd_pr__nfet_g5v0d10v5 w=2 l=0.8 m=7
+Xm5 casc3 casc2 vss vss sky130_fd_pr__nfet_g5v0d10v5 w=2 l=0.8 m=1
+Xc3 mir3 casc3 casc3 vdd3v3 sky130_fd_pr__pfet_g5v0d10v5 w=2 l=0.8 m=1
+Xm6 mir3 mir3 vdd3v3 vdd3v3 sky130_fd_pr__pfet_g5v0d10v5 w=2 l=0.8 m=7
+Xm7 mir4 mir3 vdd3v3 vdd3v3 sky130_fd_pr__pfet_g5v0d10v5 w=2 l=0.8 m=1
+Xc4 vcap casc3 mir4 vdd3v3 sky130_fd_pr__pfet_g5v0d10v5 w=2 l=0.8 m=1
* Buffered with schmitt trigger buffer
-Xtrig vcap vss vss vdda vdda out sky130_fd_sc_hvl__schmittbuf_1
+Xtrig vcap vss vss vdd3v3 vdd3v3 out sky130_fd_sc_hvl__schmittbuf_1
* High voltage output (buffer)
-Xbuf out vss vss vdda vdda por_h sky130_fd_sc_hvl__buf_8
+Xbuf out vss vss vdd3v3 vdd3v3 porb_h sky130_fd_sc_hvl__buf_8
* Level shift down (buffer)
-Xlv1 out vss vss vccd vccd por_l sky130_fd_sc_hvl__buf_8
+Xlv1 out vss vss vdd1v8 vdd1v8 porb_l sky130_fd_sc_hvl__buf_8
* Level shift down (inverter)
-Xlv2 out vss vss vccd vccd porb_l sky130_fd_sc_hvl__inv_8
+Xlv2 out vss vss vdd1v8 vdd1v8 por_l sky130_fd_sc_hvl__inv_8
* Fill cell
-Xfill vss vss vccd vccd sky130_fd_sc_hvl__fill_4
+Xfill vss vss vdd3v3 vdd3v3 sky130_fd_sc_hvl__fill_4
* No tap cell in library?
-* Xtap vdda vss sky130_fd_sc_hvl__tapvpwrvgnd_1
+* Xtap vdd3v3 vss sky130_fd_sc_hvl__tapvpwrvgnd_1
.ends
diff --git a/ngspice/simple_por_tb.spice b/ngspice/simple_por_tb.spice
index 815f4fa..f982387 100644
--- a/ngspice/simple_por_tb.spice
+++ b/ngspice/simple_por_tb.spice
@@ -16,10 +16,10 @@
Vpwr vdda vss DC=0 PWL(0.0 0 100u 0 5m 3.3)
Vdig vccd vss DC=0 PWL(0.0 0 300u 0 5.3m 1.8)
Rgnd vss 0 0.01
-Cload1 por_h vss 1E-12
+Cload1 porb_h vss 1E-12
Cload2 por_l vss 1E-12
Cload3 porb_l vss 1E-12
-Xpor vdda vccd vss por_h por_l porb_l simple_por
+Xpor vdda vccd vss porb_h por_l porb_l simple_por
*----------------------------
*----------------------------
@@ -27,7 +27,7 @@
*----------------------------
.control
tran 10u 20m
-plot por_h
+plot porb_h
plot por_l
plot porb_l
.endc
