commit 1070832c14176089d6b180922ec44a24f28d00cd
author Tim Edwards <tim@opencircuitdesign.com> Fri Nov 20 13:55:57 2020 -0500
committer Tim Edwards <tim@opencircuitdesign.com> Fri Nov 20 13:55:57 2020 -0500
tree 027a7e49b61278abf94dc61664edc39aafa59922
parent 4518c6205769f591ea2743b4b175a40e3a684d79

Added ngspice netlist and testbenches for the power-on-reset circuit.

verilog/rtl/simple_por.v

diff --git a/verilog/rtl/simple_por.v b/verilog/rtl/simple_por.v
index 6307e79..f04fa5c 100644
--- a/verilog/rtl/simple_por.v
+++ b/verilog/rtl/simple_por.v
@@ -22,7 +22,8 @@
     end 
 
     // Emulate current source on capacitor as a 500ns delay either up or
-    // down.
+    // down.  Note that this is sped way up for verilog simulation;  the
+    // actual circuit is set to a 15ms delay.
 
     always @(posedge vdd3v3) begin
 	#500 inode <= 1'b1;