Made a few testbench corrections and added the missing OEB lines from the user project. All existing testbench tests are now passing.
diff --git a/verilog/dv/caravel/mgmt_soc/hkspi/hkspi_tb.v b/verilog/dv/caravel/mgmt_soc/hkspi/hkspi_tb.v index 1922c63..c08aa6f 100644 --- a/verilog/dv/caravel/mgmt_soc/hkspi/hkspi_tb.v +++ b/verilog/dv/caravel/mgmt_soc/hkspi/hkspi_tb.v
@@ -177,8 +177,8 @@ $display("Read register 7 = 0x%02x (should be 0x00)", tbdata); if(tbdata !== 8'h00) begin $display("Monitor: Test HK SPI (RTL) Failed"); $finish; end read_byte(tbdata); - $display("Read register 8 = 0x%02x (should be 0x01)", tbdata); - if(tbdata !== 8'h01) begin $display("Monitor: Test HK SPI (RTL) Failed"); $finish; end + $display("Read register 8 = 0x%02x (should be 0x02)", tbdata); + if(tbdata !== 8'h02) begin $display("Monitor: Test HK SPI (RTL) Failed"); $finish; end read_byte(tbdata); $display("Read register 9 = 0x%02x (should be 0x01)", tbdata); if(tbdata !== 8'h01) begin $display("Monitor: Test HK SPI (RTL) Failed"); $finish; end @@ -204,8 +204,8 @@ $display("Read register 16 = 0x%02x (should be 0x03)", tbdata); if(tbdata !== 8'h03) begin $display("Monitor: Test HK SPI (RTL) Failed"); $finish; end read_byte(tbdata); - $display("Read register 17 = 0x%02x (should be 0x00)", tbdata); - if(tbdata !== 8'h00) begin $display("Monitor: Test HK SPI (RTL) Failed"); $finish; end + $display("Read register 17 = 0x%02x (should be 0x02)", tbdata); + if(tbdata !== 8'h02) begin $display("Monitor: Test HK SPI (RTL) Failed"); $finish; end read_byte(tbdata); $display("Read register 18 = 0x%02x (should be 0x04)", tbdata); if(tbdata !== 8'h04) begin $display("Monitor: Test HK SPI (RTL) Failed"); $finish; end
diff --git a/verilog/dv/caravel/mgmt_soc/mprj_ctrl/mprj_ctrl.c b/verilog/dv/caravel/mgmt_soc/mprj_ctrl/mprj_ctrl.c index 4413573..a48759f 100644 --- a/verilog/dv/caravel/mgmt_soc/mprj_ctrl/mprj_ctrl.c +++ b/verilog/dv/caravel/mgmt_soc/mprj_ctrl/mprj_ctrl.c
@@ -58,34 +58,34 @@ reg_mprj_datal = 0; // start test - reg_mprj_datal = 0xA040; + reg_mprj_datal = 0x50000000; // Write to IO Control reg_mprj_io_0 = 0x004F; if (reg_mprj_io_0 != 0x004F) - reg_mprj_datal = 0xAB400000; + reg_mprj_datal = 0x60000000; else - reg_mprj_datal = 0xAB410000; + reg_mprj_datal = 0x70000000; // Write to IO Control reg_mprj_io_1 = 0x005F; if (reg_mprj_io_1 != 0x005F) - reg_mprj_datal = 0xAB500000; + reg_mprj_datal = 0x80000000; else - reg_mprj_datal = 0xAB510000; + reg_mprj_datal = 0x90000000; // Write to IO Control reg_mprj_io_2 = 0x006F; if (reg_mprj_io_2 != 0x006F) - reg_mprj_datal = 0xAB600000; + reg_mprj_datal = 0xA0000000; else - reg_mprj_datal = 0xAB610000; + reg_mprj_datal = 0xb0000000; - // Write to IO Control + // Write to IO Control (NOTE: Only 13 bits are valid) reg_mprj_io_3 = 0xF0F5; - if (reg_mprj_io_3 != 0xF0F5) - reg_mprj_datal = 0xAB700000; + if (reg_mprj_io_3 != 0x10F5) + reg_mprj_datal = 0xc0000000; else - reg_mprj_datal = 0xAB710000; + reg_mprj_datal = 0xd0000000; }
diff --git a/verilog/dv/caravel/mgmt_soc/mprj_ctrl/mprj_ctrl_tb.v b/verilog/dv/caravel/mgmt_soc/mprj_ctrl/mprj_ctrl_tb.v index ef30bcd..c248521 100644 --- a/verilog/dv/caravel/mgmt_soc/mprj_ctrl/mprj_ctrl_tb.v +++ b/verilog/dv/caravel/mgmt_soc/mprj_ctrl/mprj_ctrl_tb.v
@@ -16,7 +16,9 @@ wire [36:0] user_io; wire SDO; - wire [15:0] checkbits; + wire [3:0] checkbits; + + assign checkbits = user_io[31:28]; // External clock is used by default. Make this artificially fast for the // simulation. Normally this would be a slow clock and the digital PLL @@ -29,7 +31,7 @@ end initial begin - $dumpfile("mprj_ctrl_tb.vcd"); + $dumpfile("mprj_ctrl.vcd"); $dumpvars(0, mprj_ctrl_tb); repeat (25) begin repeat (1000) @(posedge clock); @@ -42,28 +44,39 @@ end always @(checkbits) begin - if(checkbits == 16'hA040) begin + if(checkbits == 4'h5) begin $display("Mega-Project control Test started"); - end - else if(checkbits == 16'hAB40) begin + end else if(checkbits == 4'h6) begin $display("%c[1;31m",27); $display("Monitor: IO control R/W failed"); $display("%c[0m",27); $finish; - end - else if(checkbits == 16'hAB41) begin + end else if(checkbits == 4'h7) begin $display("Monitor: IO control R/W passed"); - end - else if(checkbits == 16'hAB50) begin - $display("%c[1;31m",27); + end else if(checkbits == 4'h8) begin + $display("%c[1;31m",27); $display("Monitor: power control R/W failed"); $display("%c[0m",27); $finish; - end else if(checkbits == 16'hAB51) begin + end else if(checkbits == 4'h9) begin $display("Monitor: power control R/W passed"); - $display("Monitor: Mega-Project control (RTL) test passed."); - $finish; - end + end else if(checkbits == 4'ha) begin + $display("%c[1;31m",27); + $display("Monitor: power control R/W failed"); + $display("%c[0m",27); + $finish; + end else if(checkbits == 4'hb) begin + $display("Monitor: power control R/W passed"); + end else if(checkbits == 4'hc) begin + $display("%c[1;31m",27); + $display("Monitor: power control R/W failed"); + $display("%c[0m",27); + $finish; + end else if(checkbits == 4'hd) begin + $display("Monitor: power control R/W passed"); + $display("Monitor: Mega-Project control (RTL) test passed."); + $finish; + end end initial begin
diff --git a/verilog/dv/caravel/mgmt_soc/pass_thru/pass_thru_tb.v b/verilog/dv/caravel/mgmt_soc/pass_thru/pass_thru_tb.v index e00c85f..dbe5322 100644 --- a/verilog/dv/caravel/mgmt_soc/pass_thru/pass_thru_tb.v +++ b/verilog/dv/caravel/mgmt_soc/pass_thru/pass_thru_tb.v
@@ -185,7 +185,7 @@ $display("Read data = 0x%02x (should be 0x10)", tbdata); if(tbdata !== 8'h10) begin $display("Monitor: Test HK SPI Pass-thru (RTL) Failed"); $finish; end - $display("Monitor: Test HK SPI (RTL) Passed"); + $display("Monitor: Test HK SPI Pass-thru (RTL) Passed"); #10000; $finish;
diff --git a/verilog/dv/caravel/mgmt_soc/pll/pll_tb.v b/verilog/dv/caravel/mgmt_soc/pll/pll_tb.v index ef684c5..5921a03 100644 --- a/verilog/dv/caravel/mgmt_soc/pll/pll_tb.v +++ b/verilog/dv/caravel/mgmt_soc/pll/pll_tb.v
@@ -32,14 +32,14 @@ end initial begin - $dumpfile("pll_tb.vcd"); + $dumpfile("pll.vcd"); $dumpvars(0, pll_tb); repeat (25) begin repeat (1000) @(posedge clock); $display("+1000 cycles"); end $display("%c[1;31m",27); - $display ("Monitor: Timeout, Test GPIO (RTL) Failed"); + $display ("Monitor: Timeout, Test PLL (RTL) Failed"); $display("%c[0m",27); $finish; end
diff --git a/verilog/dv/caravel/mgmt_soc/sysctrl/sysctrl_tb.v b/verilog/dv/caravel/mgmt_soc/sysctrl/sysctrl_tb.v index adcbb48..06362c8 100644 --- a/verilog/dv/caravel/mgmt_soc/sysctrl/sysctrl_tb.v +++ b/verilog/dv/caravel/mgmt_soc/sysctrl/sysctrl_tb.v
@@ -32,7 +32,7 @@ end initial begin - $dumpfile("sysctrl_tb.vcd"); + $dumpfile("sysctrl.vcd"); $dumpvars(0, sysctrl_tb); repeat (25) begin repeat (1000) @(posedge clock); @@ -68,8 +68,8 @@ $finish; end wait(checkbits == 16'hA044); - $display(" SPI value = 0x%x (should be 0x01)", spivalue); - if(spivalue !== 32'h01) begin + $display(" SPI value = 0x%x (should be 0x02)", spivalue); + if(spivalue !== 32'h02) begin $display("Monitor: Test Sysctrl (RTL) Failed"); $finish; end @@ -104,8 +104,8 @@ $finish; end wait(checkbits == 16'hA04a); - $display(" SPI value = 0x%x (should be 0x00)", spivalue); - if(spivalue !== 32'h00) begin + $display(" SPI value = 0x%x (should be 0x02)", spivalue); + if(spivalue !== 32'h02) begin $display("Monitor: Test Sysctrl (RTL) Failed"); $finish; end
diff --git a/verilog/dv/caravel/mgmt_soc/timer2/timer2_tb.v b/verilog/dv/caravel/mgmt_soc/timer2/timer2_tb.v index 9c599a5..4baea92 100644 --- a/verilog/dv/caravel/mgmt_soc/timer2/timer2_tb.v +++ b/verilog/dv/caravel/mgmt_soc/timer2/timer2_tb.v
@@ -67,19 +67,19 @@ // Monitor initial begin wait(checkbits == 5'h0a); - $display("Monitor: Test Timer (RTL) Started"); + $display("Monitor: Test Timer2 (RTL) Started"); /* Add checks here */ wait(checkbits == 5'h01); $display(" countbits = 0x%x (should be 0xdcba7eb0)", countbits); if(countbits !== 32'hdcba7eb0) begin - $display("Monitor: Test Timer (RTL) Failed"); + $display("Monitor: Test Timer2 (RTL) Failed"); $finish; end wait(checkbits == 5'h02); $display(" countbits = 0x%x (should be 0x10)", countbits); if(countbits !== 32'h10) begin - $display("Monitor: Test Timer (RTL) Failed"); + $display("Monitor: Test Timer2 (RTL) Failed"); $finish; end wait(checkbits == 5'h03); @@ -91,17 +91,17 @@ wait(checkbits == 5'h04); $display(" countbits = %x (should be 0x0c)", countbits); if(countbits !== 32'h0c) begin - $display("Monitor: Test Timer (RTL) Failed"); + $display("Monitor: Test Timer2 (RTL) Failed"); $finish; end wait(checkbits == 5'h05); $display(" countbits = %x (should be 0x117c)", countbits); if(countbits !== 32'h117c) begin - $display("Monitor: Test Timer (RTL) Failed"); + $display("Monitor: Test Timer2 (RTL) Failed"); $finish; end - $display("Monitor: Test Timer (RTL) Passed"); + $display("Monitor: Test Timer2 (RTL) Passed"); $finish; end
diff --git a/verilog/dv/caravel/mgmt_soc/uart/uart.c b/verilog/dv/caravel/mgmt_soc/uart/uart.c index d89741f..3f8d4c9 100644 --- a/verilog/dv/caravel/mgmt_soc/uart/uart.c +++ b/verilog/dv/caravel/mgmt_soc/uart/uart.c
@@ -5,6 +5,8 @@ void main() { + int j; + // Configure I/O: High 16 bits of user area used for a 16-bit // word to write and be detected by the testbench verilog. // Only serial Tx line is used in this testbench. It connects @@ -32,21 +34,26 @@ reg_mprj_io_6 = GPIO_MODE_MGMT_STD_OUTPUT; - // Apply configuration - reg_mprj_xfer = 1; - while (reg_mprj_xfer == 1); + // Set clock to 64 kbaud and enable the UART. It is important to do this + // before applying the configuration, or else the Tx line initializes as + // zero, which indicates the start of a byte to the receiver. - // Set clock to 64 kbaud and enable the UART reg_uart_clkdiv = 625; reg_uart_enable = 1; + // Now, apply the configuration + reg_mprj_xfer = 1; + while (reg_mprj_xfer == 1); + // Start test reg_mprj_datal = 0xa0000000; // This should appear at the output, received by the testbench UART. - print("\n"); - // print("Monitor: Test UART (RTL) passed\n\n"); - print("X\n\n"); + // (Makes simulation time long.) + print("Monitor: Test UART (RTL) passed\n"); + // Allow transmission to complete before signalling that the program + // has ended. + for (j = 0; j < 20; j++); reg_mprj_datal = 0xab000000; }
diff --git a/verilog/dv/caravel/mgmt_soc/uart/uart_tb.v b/verilog/dv/caravel/mgmt_soc/uart/uart_tb.v index aa1a91b..b3f8bd3 100644 --- a/verilog/dv/caravel/mgmt_soc/uart/uart_tb.v +++ b/verilog/dv/caravel/mgmt_soc/uart/uart_tb.v
@@ -71,7 +71,6 @@ $display("UART Test started"); end else if(checkbits == 16'hAB00) begin - #20000; // Allow time for last transmission $display("UART Test passed"); $finish; end
diff --git a/verilog/dv/caravel/user_proj_example/la_test1/la_test1.c b/verilog/dv/caravel/user_proj_example/la_test1/la_test1.c index d3b08d7..a564a9f 100644 --- a/verilog/dv/caravel/user_proj_example/la_test1/la_test1.c +++ b/verilog/dv/caravel/user_proj_example/la_test1/la_test1.c
@@ -58,14 +58,14 @@ reg_mprj_io_6 = GPIO_MODE_MGMT_STD_OUTPUT; + // Set UART clock to 64 kbaud (enable before I/O configuration) + reg_uart_clkdiv = 625; + reg_uart_enable = 1; + /* Apply configuration */ reg_mprj_xfer = 1; while (reg_mprj_xfer == 1); - // Set UART clock to 64 kbaud - reg_uart_clkdiv = 625; - reg_uart_enable = 1; - // Configure LA probes [31:0], [127:64] as inputs to the cpu // Configure LA probes [63:32] as outputs from the cpu reg_la0_ena = 0xFFFFFFFF; // [31:0] @@ -89,7 +89,7 @@ } } print("\n"); - print("Monitor: Test 2 Passed\n\n"); + print("Monitor: Test 2 Passed\n\n"); // Makes simulation very long! reg_mprj_datal = 0xAB510000; }
diff --git a/verilog/dv/caravel/user_proj_example/la_test2/la_test2_tb.v b/verilog/dv/caravel/user_proj_example/la_test2/la_test2_tb.v index 7494ddc..fff6e2e 100644 --- a/verilog/dv/caravel/user_proj_example/la_test2/la_test2_tb.v +++ b/verilog/dv/caravel/user_proj_example/la_test2/la_test2_tb.v
@@ -13,7 +13,7 @@ wire [36:0] mprj_io; wire [15:0] checkbits; - assign checkbits = mprj_io[15:8]; + assign checkbits = mprj_io[31:16]; always #12.5 clock <= (clock === 1'b0);
diff --git a/verilog/rtl/caravel.v b/verilog/rtl/caravel.v index 3c711fd..463f127 100644 --- a/verilog/rtl/caravel.v +++ b/verilog/rtl/caravel.v
@@ -413,7 +413,8 @@ .la_oen (la_oen), // IO Pads .io_in (user_io_in), - .io_out(user_io_out) + .io_out(user_io_out), + .io_oeb(user_io_oeb) ); /*--------------------------------------*/
diff --git a/verilog/rtl/housekeeping_spi.v b/verilog/rtl/housekeeping_spi.v index 879aff8..10ea1b3 100644 --- a/verilog/rtl/housekeeping_spi.v +++ b/verilog/rtl/housekeeping_spi.v
@@ -177,7 +177,7 @@ (iaddr == 8'h06) ? mask_rev[15:8] : // Mask rev (metal programmed) (iaddr == 8'h07) ? mask_rev[7:0] : // Mask rev (metal programmed) - (iaddr == 8'h08) ? {6'b0000000, pll_dco_ena, pll_ena} : + (iaddr == 8'h08) ? {6'b000000, pll_dco_ena, pll_ena} : (iaddr == 8'h09) ? {7'b0000000, pll_bypass} : (iaddr == 8'h0a) ? {7'b0000000, irq} : (iaddr == 8'h0b) ? {7'b0000000, reset} :
diff --git a/verilog/rtl/user_proj_example.v b/verilog/rtl/user_proj_example.v index 742977c..4c2a6b9 100644 --- a/verilog/rtl/user_proj_example.v +++ b/verilog/rtl/user_proj_example.v
@@ -54,11 +54,16 @@ // IOs input [IO_PADS-1:0] io_in, - output [IO_PADS-1:0] io_out + output [IO_PADS-1:0] io_out, + output [IO_PADS-1:0] io_oeb ); wire clk; wire rst; + wire [IO_PADS-1:0] io_in; + wire [IO_PADS-1:0] io_out; + wire [IO_PADS-1:0] io_oeb; + wire [31:0] rdata; wire [31:0] wdata; wire [BITS-1:0] count; @@ -75,6 +80,7 @@ // IO assign io_out = count; + assign io_oeb = {(IO_PADS-1){rst}}; // LA assign la_data_out = {{(127-BITS){1'b0}}, count};