commit b6dd152556ce2581f06758efc45c9b387bc4c4ab
author Tim Edwards <tim@opencircuitdesign.com> Mon Oct 19 15:58:25 2020 -0400
committer Tim Edwards <tim@opencircuitdesign.com> Mon Oct 19 15:58:25 2020 -0400
tree 77f58827c6d18bbb87dff16e4cffc8ad415fa1c1
parent 268a90bd2da91eba601fe9f9e6de573bbe272951

Updated testbenches to declare 38 bits for the user project GPIO pins.

verilog/rtl/user_proj_example.v

diff --git a/verilog/rtl/user_proj_example.v b/verilog/rtl/user_proj_example.v
index 1edc2dc..d010e77 100644
--- a/verilog/rtl/user_proj_example.v
+++ b/verilog/rtl/user_proj_example.v
@@ -20,7 +20,7 @@
  */
 
 module user_proj_example #(
-    parameter IO_PADS = 37,
+    parameter IO_PADS = 38,
     parameter PWR_PADS = 4,
     parameter BITS = 32
 )(