| commit | 3a1e3537904c34612db08fdfcf89c3ecbdb9a55a | [log] [tgz] |
|---|---|---|
| author | Ahmed Ghazy <ax3ghazy@aucegypt.edu> | Wed Oct 28 03:35:34 2020 +0200 |
| committer | Ahmed Ghazy <ax3ghazy@aucegypt.edu> | Wed Oct 28 22:58:29 2020 +0200 |
| tree | 4a9dec59be7e155ccf8499925baf18deb4b9428a | |
| parent | cfe765325711bbb060668c2ed9950436416c9098 [diff] |
Fix another 36->37 typo in mem_tb.v
diff --git a/verilog/dv/caravel/mgmt_soc/mem/mem_tb.v b/verilog/dv/caravel/mgmt_soc/mem/mem_tb.v index f0fbcae..eac5e68 100644 --- a/verilog/dv/caravel/mgmt_soc/mem/mem_tb.v +++ b/verilog/dv/caravel/mgmt_soc/mem/mem_tb.v
@@ -30,7 +30,7 @@ wire gpio; wire [15:0] checkbits; - wire [36:0] mprj_io; + wire [37:0] mprj_io; wire flash_csb; wire flash_clk; wire flash_io0;