Added cargo readme
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-# Spectrometer on Caravel
+# Spectravel - Spectrometer on Caravel
-![Interface of the Spectrometer](./doc/Spectrometer.png)
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+Block diagram of the Spectravel is given below and detailed explanation of the each block is given inside submodules `spectrometer` and `wb2axip`.
+
+![Global block scheme of the Spectravel](./doc/SpectrometerTest.svg)
+
+This directory contains following submodules and directories:
+
+* Submodule `spectrometer` - contains digital spectrometer generator with built in test structures designed in [Chisel](http://www.chisel-lang.org) HDL
+* Submodule `wb2axip` - contains wishbone to AXI4 bridge. Current submodule is forked version of the [ZipCPU/wb2axip](https://github.com/ZipCPU/wb2axip)
+* `doc` - contains global block scheme of the `Spectravel` block in svg and png format.
+* `top/dv/SpectrometerTest` - contains verilog testbenches for Spectravel integrated with Caravel
+* `top/rtl/SpectrometerTest` - contains `user_proj_example.v` which is the top level verilog file for Spectravel
+* Makefile - have targets for verilog and test generation
+
+## Useful commands
+Before running make commands, we could set the size of FFT inside spectrometer. Default size is 128. For example, we could set the size of the FFT inside spectrometer to be equal to 256 with the command:
+```sh
+$ export SIZE=256
+```
+In order to generate verilog file SpectrometerTest.v which contains verilog code for digital spectrometer, run command:
+```sh
+$ make verilog_spectrometer
+```
+To run chisel tests for digital spectrometer, run command:
+```sh
+$ make test_spectrometer
+```
+In order to run verilog tests for Spectravel connected to Caravel, PDK_ROOT and RISCV32 paths must be set. RISCV32 is path to RV32I Toolchain. For RV32I toolchain installation click [here](https://github.com/cliffordwolf/picorv32#building-a-pure-rv32i-toolchain). To check if paths are set, run command:
+```sh
+$ make check-env
+```
+In order to test Spectravel added to the Caravel, run command:
+```sh
+$ make test_top
+```
+To clean data generated by verilog testbenches, run:
+```sh
+$ make clean_top
+```
+
+## Address space for Spectravel
+```
+User address space 0x3000_0000
+ ├── in_split: 0x3000_0000
+ ├── plfg_ram: 0x3000_1000
+ ├── plfg: 0x3000_2100
+ ├── plfg_split: 0x3000_2200
+ ├── plfg_mux_0: 0x3000_2210
+ ├── plfg_mux_1: 0x3000_2220
+ ├── nco: 0x3000_3000
+ ├── nco_split: 0x3000_3100
+ ├── nco_mux_0: 0x3000_3110
+ ├── nco_mux_1: 0x3000_3120
+ ├── fft: 0x3000_4000
+ ├── fft_split: 0x3000_4100
+ ├── fft_mux_0 0x3000_4110
+ ├── fft_mux_1: 0x3000_4120
+ ├── mag: 0x3000_5000
+ ├── mag_split: 0x3000_5100
+ ├── mag_mux_0: 0x3000_5110
+ ├── mag_mux_1: 0x3000_5120
+ ├── acc_queue: 0x3000_6000
+ ├── acc: 0x3000_7000
+ ├── out_mux: 0x3000_8000
+ ├── out_split: 0x3000_8010
+ ├── uart: 0x3000_9000
+ └── uart_split: 0x3000_9100
+```
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