Eliminate the two inverters at the top level
- Also fix some missing sizes ('_1') in cell names
- Also add USE_POWER_PINS guards in the modified files
diff --git a/verilog/rtl/caravel.v b/verilog/rtl/caravel.v
index 784fdae..42ecf45 100644
--- a/verilog/rtl/caravel.v
+++ b/verilog/rtl/caravel.v
@@ -251,7 +251,7 @@
.flash_io1_do_core(flash_io1_do_core),
.flash_io0_di_core(flash_io0_di_core),
.flash_io1_di_core(flash_io1_di_core),
- .por(~porb_l),
+ .por(por_l),
.mprj_io_in(mprj_io_in),
.mprj_io_out(mprj_io_out),
.mprj_io_oeb(mprj_io_oeb),
@@ -308,6 +308,7 @@
wire mprj_clock;
wire mprj_clock2;
wire mprj_resetn;
+ wire mprj_reset;
wire mprj_cyc_o_user;
wire mprj_stb_o_user;
wire mprj_we_o_user;
@@ -440,6 +441,7 @@
.user_clock(mprj_clock),
.user_clock2(mprj_clock2),
.user_resetn(mprj_resetn),
+ .user_reset(mprj_reset),
.mprj_cyc_o_user(mprj_cyc_o_user),
.mprj_stb_o_user(mprj_stb_o_user),
.mprj_we_o_user(mprj_we_o_user),
@@ -469,7 +471,7 @@
.vssd2(vssd2), // User area 2 digital ground
.wb_clk_i(mprj_clock),
- .wb_rst_i(!mprj_resetn),
+ .wb_rst_i(mprj_reset),
// MGMT SoC Wishbone Slave
.wbs_cyc_i(mprj_cyc_o_user),
.wbs_stb_i(mprj_stb_o_user),
@@ -594,16 +596,6 @@
.pad_gpio_in(mprj_io_in[(`MPRJ_IO_PADS-1):2])
);
- sky130_fd_sc_hvl__lsbufhv2lv porb_level (
- .VPWR(vddio),
- .VPB(vddio),
- .LVPWR(vccd),
- .VNB(vssio),
- .VGND(vssio),
- .A(porb_h),
- .X(porb_l)
- );
-
user_id_programming #(
.USER_PROJECT_ID(USER_PROJECT_ID)
) user_id_value (
@@ -620,12 +612,14 @@
);
// XRES (chip input pin reset) reset level converter
- sky130_fd_sc_hvl__lsbufhv2lv rstb_level (
+ sky130_fd_sc_hvl__lsbufhv2lv_1 rstb_level (
+`ifdef USE_POWER_PINS
.VPWR(vddio),
.VPB(vddio),
.LVPWR(vccd),
.VNB(vssio),
.VGND(vssio),
+`endif
.A(rstb_h),
.X(rstb_l)
);
diff --git a/verilog/rtl/mgmt_protect.v b/verilog/rtl/mgmt_protect.v
index f8fe7fb..c5c79f3 100644
--- a/verilog/rtl/mgmt_protect.v
+++ b/verilog/rtl/mgmt_protect.v
@@ -41,6 +41,7 @@
output user_clock,
output user_clock2,
output user_resetn,
+ output user_reset,
output mprj_cyc_o_user,
output mprj_stb_o_user,
output mprj_we_o_user,
@@ -68,19 +69,23 @@
wire user2_vdd_powergood;
sky130_fd_sc_hd__conb_1 mprj_logic_high [74:0] (
+`ifdef USE_POWER_PINS
.VPWR(vccd1),
.VGND(vssd1),
.VPB(vccd1),
.VNB(vssd1),
+`endif
.HI(mprj_logic1),
.LO()
);
sky130_fd_sc_hd__conb_1 mprj2_logic_high (
+`ifdef USE_POWER_PINS
.VPWR(vccd2),
.VGND(vssd2),
.VPB(vccd2),
.VNB(vssd2),
+`endif
.HI(mprj2_logic1),
.LO()
);
@@ -88,130 +93,158 @@
// Logic high in the VDDA (3.3V) domains
sky130_fd_sc_hvl__conb_1 mprj_logic_high_hvl (
+`ifdef USE_POWER_PINS
.VPWR(vdda1),
.VGND(vssa1),
.VPB(vdda1),
.VNB(vssa1),
+`endif
.HI(mprj_vdd_logic1_h),
.LO()
);
sky130_fd_sc_hvl__conb_1 mprj2_logic_high_hvl (
+`ifdef USE_POWER_PINS
.VPWR(vdda2),
.VGND(vssa2),
.VPB(vdda2),
.VNB(vssa2),
+`endif
.HI(mprj2_vdd_logic1_h),
.LO()
);
// Level shift the logic high signals into the 1.8V domain
- sky130_fd_sc_hvl__lsbufhv2lv mprj_logic_high_lv (
+ sky130_fd_sc_hvl__lsbufhv2lv_1 mprj_logic_high_lv (
+`ifdef USE_POWER_PINS
.VPWR(vdda1),
.VGND(vssd),
.LVPWR(vccd),
.VPB(vdda1),
.VNB(vssd),
+`endif
.X(mprj_vdd_logic1),
.A(mprj_vdd_logic1_h)
);
- sky130_fd_sc_hvl__lsbufhv2lv mprj2_logic_high_lv (
+ sky130_fd_sc_hvl__lsbufhv2lv_1 mprj2_logic_high_lv (
+`ifdef USE_POWER_PINS
.VPWR(vdda2),
.VGND(vssd),
.LVPWR(vccd),
.VPB(vdda2),
.VNB(vssd),
+`endif
.X(mprj2_vdd_logic1),
.A(mprj2_vdd_logic1_h)
);
sky130_fd_sc_hd__einvp_8 mprj_rstn_buf (
+`ifdef USE_POWER_PINS
.VPWR(vccd),
.VGND(vssd),
.VPB(vccd),
.VNB(vssd),
+`endif
.Z(user_resetn),
.A(~caravel_rstn),
.TE(mprj_logic1[0])
);
+ assign user_reset = ~user_resetn;
+
sky130_fd_sc_hd__einvp_8 mprj_clk_buf (
+`ifdef USE_POWER_PINS
.VPWR(vccd),
.VGND(vssd),
.VPB(vccd),
.VNB(vssd),
+`endif
.Z(user_clock),
.A(~caravel_clk),
.TE(mprj_logic1[1])
);
sky130_fd_sc_hd__einvp_8 mprj_clk2_buf (
+`ifdef USE_POWER_PINS
.VPWR(vccd),
.VGND(vssd),
.VPB(vccd),
.VNB(vssd),
+`endif
.Z(user_clock2),
.A(~caravel_clk2),
.TE(mprj_logic1[2])
);
sky130_fd_sc_hd__einvp_8 mprj_cyc_buf (
+`ifdef USE_POWER_PINS
.VPWR(vccd),
.VGND(vssd),
.VPB(vccd),
.VNB(vssd),
+`endif
.Z(mprj_cyc_o_user),
.A(~mprj_cyc_o_core),
.TE(mprj_logic1[3])
);
sky130_fd_sc_hd__einvp_8 mprj_stb_buf (
+`ifdef USE_POWER_PINS
.VPWR(vccd),
.VGND(vssd),
.VPB(vccd),
.VNB(vssd),
+`endif
.Z(mprj_stb_o_user),
.A(~mprj_stb_o_core),
.TE(mprj_logic1[4])
);
sky130_fd_sc_hd__einvp_8 mprj_we_buf (
+`ifdef USE_POWER_PINS
.VPWR(vccd),
.VGND(vssd),
.VPB(vccd),
.VNB(vssd),
+`endif
.Z(mprj_we_o_user),
.A(~mprj_we_o_core),
.TE(mprj_logic1[5])
);
sky130_fd_sc_hd__einvp_8 mprj_sel_buf [3:0] (
+`ifdef USE_POWER_PINS
.VPWR(vccd),
.VGND(vssd),
.VPB(vccd),
.VNB(vssd),
+`endif
.Z(mprj_sel_o_user),
.A(~mprj_sel_o_core),
.TE(mprj_logic1[9:6])
);
sky130_fd_sc_hd__einvp_8 mprj_adr_buf [31:0] (
+`ifdef USE_POWER_PINS
.VPWR(vccd),
.VGND(vssd),
.VPB(vccd),
.VNB(vssd),
+`endif
.Z(mprj_adr_o_user),
.A(~mprj_adr_o_core),
.TE(mprj_logic1[41:10])
);
sky130_fd_sc_hd__einvp_8 mprj_dat_buf [31:0] (
+`ifdef USE_POWER_PINS
.VPWR(vccd),
.VGND(vssd),
.VPB(vccd),
.VNB(vssd),
+`endif
.Z(mprj_dat_o_user),
.A(~mprj_dat_o_core),
.TE(mprj_logic1[73:42])
@@ -224,10 +257,12 @@
/* power-down of vccd1. */
sky130_fd_sc_hd__einvp_8 la_buf [127:0] (
+`ifdef USE_POWER_PINS
.VPWR(vccd),
.VGND(vssd),
.VPB(vccd),
.VNB(vssd),
+`endif
.Z(la_data_in_mprj),
.A(~la_output_core),
.TE(~la_oen)
@@ -238,37 +273,45 @@
/* signal, make sure that it is buffered properly. */
sky130_fd_sc_hd__buf_8 mprj_pwrgood (
+`ifdef USE_POWER_PINS
.VPWR(vccd),
.VGND(vssd),
.VPB(vccd),
.VNB(vssd),
+`endif
.A(mprj_logic1[74]),
.X(user1_vcc_powergood)
);
sky130_fd_sc_hd__buf_8 mprj2_pwrgood (
+`ifdef USE_POWER_PINS
.VPWR(vccd),
.VGND(vssd),
.VPB(vccd),
.VNB(vssd),
+`endif
.A(mprj2_logic1),
.X(user2_vcc_powergood)
);
sky130_fd_sc_hd__buf_8 mprj_vdd_pwrgood (
+`ifdef USE_POWER_PINS
.VPWR(vccd),
.VGND(vssd),
.VPB(vccd),
.VNB(vssd),
+`endif
.A(mprj_vdd_logic1),
.X(user_vdd_powergood)
);
sky130_fd_sc_hd__buf_8 mprj2_vdd_pwrgood (
+`ifdef USE_POWER_PINS
.VPWR(vccd),
.VGND(vssd),
.VPB(vccd),
.VNB(vssd),
+`endif
.A(mprj2_vdd_logic1),
.X(user2_vdd_powergood)
);
diff --git a/verilog/rtl/simple_por.v b/verilog/rtl/simple_por.v
index 2c51e9a..f6bda39 100644
--- a/verilog/rtl/simple_por.v
+++ b/verilog/rtl/simple_por.v
@@ -2,9 +2,12 @@
`timescale 1 ns / 1 ps
module simple_por(
- input vdd3v3,
- input vss,
- output porb_h
+ inout vdd3v3,
+ inout vdd1v8,
+ inout vss,
+ output porb_h,
+ output porb_l,
+ output por_l
);
wire mid, porb_h;
@@ -30,22 +33,41 @@
// Instantiate two shmitt trigger buffers in series
- sky130_fd_sc_hvl__schmittbuf hystbuf1 (
+ sky130_fd_sc_hvl__schmittbuf_1 hystbuf1 (
+`ifdef USE_POWER_PINS
.VPWR(vdd3v3),
.VGND(vss),
.VPB(vdd3v3),
.VNB(vss),
+`endif
.A(inode),
.X(mid)
);
- sky130_fd_sc_hvl__schmittbuf hystbuf2 (
+ sky130_fd_sc_hvl__schmittbuf_1 hystbuf2 (
+`ifdef USE_POWER_PINS
.VPWR(vdd3v3),
.VGND(vss),
.VPB(vdd3v3),
.VNB(vss),
+`endif
.A(mid),
.X(porb_h)
);
+ sky130_fd_sc_hvl__lsbufhv2lv_1 porb_level (
+`ifdef USE_POWER_PINS
+ .VPWR(vdd3v3),
+ .VPB(vdd3v3),
+ .LVPWR(vdd1v8),
+ .VNB(vss),
+ .VGND(vss),
+`endif
+ .A(porb_h),
+ .X(porb_l)
+ );
+
+ // since this is behavioral anyway, but this should be
+ // replaced by a proper inverter
+ assign por_l = porb_l;
endmodule
