| commit | 5844bfbd4678f0ec9212e193c949883c01b614c8 | [log] [tgz] |
|---|---|---|
| author | iamanintrovert <mhasan14@vols.utk.edu> | Tue Dec 08 01:49:58 2020 -0500 |
| committer | GitHub <noreply@github.com> | Tue Dec 08 01:49:58 2020 -0500 |
| tree | 79979acae8e093144d101ab6ed9feb6c45e452fc | |
| parent | 277df388a794e6cd7bfe59e9c01558a4f1dee9a2 [diff] |
added sample simulation image
This is the Google/EFabless/Skywater Caravel submission of an Analog Spiking Neuron Circuit. The submission also includes a SONOS transistor array.
The circuit in the original paper is in 130nm technology and has a vdd of 300mV. Skywater pdk is hybrid 180nm/130nm node where the minimum transistor length is 150nm. As a result vdd needs to be higher in order to get the circuit to work properly. In simulation 700mV seems to work well.
| node | pad | node | pad |
|---|---|---|---|
| i_bias | mprj_io[13] | v_buff | mprj_io[22] |
| vad | mprj_io[14] | u_buff | mprj_io[23] |
| vr | mprj_io[15] | a_buff | mprj_io[24] |
| vk | mprj_io[16] | axon_buff | mprj_io[25] |
| vth | mprj_io[17] | sel | mprj_io[26] |
| vw | mprj_io[18] | v_syn | mprj_io[27] |
| vau | mprj_io[19] | u_syn | mprj_io[28] |
| vsyn0 | mprj_io[20] | a_syn | mprj_io[29] |
| vsyn1 | mprj_io[21] | axon_syn | mprj_io[30] |
| i_in | mprj_io[31] |
A 2x2 array of nfet sonos cells with transistor sizing 420nmx150nm.
| node | pad |
|---|---|
| WL0 | mprj_io[7] |
| WL1 | mprj_io[8] |
| BL0 | mprj_io[9] |
| SL0 | mprj_io[10] |
| BL1 | mprj_io[11] |
| SL1 | mprj_io[12] |
To setup and install the repo for development:
export PDK_ROOT=(where pdks will be installed) cd $PDK_ROOT git clone https://github.com/efabless/openlane.git -b mpw-one-a cd openlane export OPENLANE_ROOT=$(pwd) make
2. Clone and uncompress the repo
git clone https://github.com/Bryce-Readyhough/caravel_UNCC_MPW_1.git make uncompress -j$nproc
