Added a simple power-on-reset circuit with schmitt trigger output, and
decoupled the reset pin from the porb/porb_h. The reset for the
housekeeping SPI remains connected to porb and not the reset pin, so
that the processor can be put in reset but the housekeeping SPI can
be accessed in that state. That prevents the user from bricking the
system by having a program override the housekeeping SPI and then get
into an erroneous state.
diff --git a/verilog/rtl/chip_io.v b/verilog/rtl/chip_io.v
index dc46ebf..d34cfec 100644
--- a/verilog/rtl/chip_io.v
+++ b/verilog/rtl/chip_io.v
@@ -11,7 +11,8 @@
inout flash_io0,
inout flash_io1,
// Chip Core Interface
- output porb_h,
+ input porb_h,
+ output resetb_core_h,
output clock_core,
input gpio_out_core,
output gpio_in_core,
@@ -169,7 +170,7 @@
.tie_hi_esd(),
.tie_lo_esd(),
.pad_a_esd_h(xresloop),
- .xres_h_n(porb_h),
+ .xres_h_n(resetb_core_h),
.disable_pullup_h(vss), // 0 = enable pull-up on reset pad
.enable_h(vdd3v3), // Power-on-reset to the power-on-reset input??
.en_vddio_sig_h(vss), // No idea.
