Minor RTL fixes, switching to wrapped GPIOV2
- use USER2_ABUTMENT_PINS for the second of the vssio and vddio pads
- do core-facing power-to-signal connections using the auto-router
- fix corner pad power connections and keep them for LVS purposes
- add a bunch of missing USE_POWER_PINS guards
diff --git a/verilog/rtl/pads.v b/verilog/rtl/pads.v
index d56999a..0e914b6 100644
--- a/verilog/rtl/pads.v
+++ b/verilog/rtl/pads.v
@@ -60,7 +60,7 @@
`define INPUT_PAD(X,Y) \
wire loop_``X; \
- sky130_ef_io__gpiov2_pad X``_pad ( \
+ sky130_ef_io__gpiov2_pad_wrapped X``_pad ( \
`MGMT_ABUTMENT_PINS \
`ifndef TOP_ROUTING \
.PAD(X), \
@@ -92,7 +92,7 @@
`define OUTPUT_PAD(X,Y,INPUT_DIS,OUT_EN_N) \
wire loop_``X; \
- sky130_ef_io__gpiov2_pad X``_pad ( \
+ sky130_ef_io__gpiov2_pad_wrapped X``_pad ( \
`MGMT_ABUTMENT_PINS \
`ifndef TOP_ROUTING \
.PAD(X), \
@@ -123,7 +123,8 @@
.TIE_LO_ESD(loop_``X))
`define INOUT_PAD(X,Y,Y_OUT,INPUT_DIS,OUT_EN_N,MODE) \
- sky130_ef_io__gpiov2_pad X``_pad ( \
+ wire loop_``X; \
+ sky130_ef_io__gpiov2_pad_wrapped X``_pad ( \
`MGMT_ABUTMENT_PINS \
`ifndef TOP_ROUTING \
.PAD(X),\
