Add run reports for user macro.
diff --git a/openlane/user_proj_example/final_summary_report.csv b/openlane/user_proj_example/final_summary_report.csv
new file mode 120000
index 0000000..e33526d
--- /dev/null
+++ b/openlane/user_proj_example/final_summary_report.csv
@@ -0,0 +1 @@
+results/reports/final_summary_report.csv
\ No newline at end of file
diff --git a/openlane/user_proj_example/results/cmds.log b/openlane/user_proj_example/results/cmds.log
new file mode 100644
index 0000000..65a94da
--- /dev/null
+++ b/openlane/user_proj_example/results/cmds.log
@@ -0,0 +1,100 @@
+Wed Dec 16 10:43:49 UTC 2020 - Executing "/openLANE_flow/scripts/mergeLef.py -i /mnt/data/workspace/pdk/sky130A/libs.ref/sky130_fd_sc_hd/techlef/sky130_fd_sc_hd.tlef {/mnt/data/workspace/pdk/sky130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef /mnt/data/workspace/pdk/sky130A/libs.ref/sky130_fd_sc_hd/lef/sky130_ef_sc_hd__fakediode_2.lef} -o /project/openlane/user_proj_example/runs/16-12_10-43/tmp/merged_unpadded.lef |& tee >&@stdout"
+
+Wed Dec 16 10:43:49 UTC 2020 - Executing "/openLANE_flow/scripts/libtrim.pl /mnt/data/workspace/pdk/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib /mnt/data/workspace/pdk/sky130A/libs.tech/openlane/sky130_fd_sc_hd/no_synth.cells > /project/openlane/user_proj_example/runs/16-12_10-43/tmp/trimmed.lib"
+
+Wed Dec 16 10:43:50 UTC 2020 - Executing "yosys -c /openLANE_flow/scripts/synth.tcl -l /project/openlane/user_proj_example/runs/16-12_10-43/logs/synthesis/yosys.log |& tee >&@stdout"
+
+Wed Dec 16 10:52:34 UTC 2020 - Executing "sed -i -e {s/\(set ::env(CURRENT_NETLIST)\).*/\1 \/project\/openlane\/user_proj_example\/runs\/16-12_10-43\/results\/synthesis\/user_proj_example.synthesis.v/} /project/openlane/user_proj_example/runs/16-12_10-43/config.tcl"
+
+Wed Dec 16 10:52:34 UTC 2020 - Executing "sed -i -e {s/\(set ::env(PREV_NETLIST)\).*/\1 0/} /project/openlane/user_proj_example/runs/16-12_10-43/config.tcl"
+
+Wed Dec 16 10:52:34 UTC 2020 - Executing "sed -ie /defparam/d /project/openlane/user_proj_example/runs/16-12_10-43/results/synthesis/user_proj_example.synthesis.v"
+
+Wed Dec 16 10:52:36 UTC 2020 - Executing "sta /openLANE_flow/scripts/sta.tcl |& tee >&@stdout /project/openlane/user_proj_example/runs/16-12_10-43/logs/synthesis/opensta.log"
+
+Wed Dec 16 10:52:47 UTC 2020 - Executing "openroad -exit /openLANE_flow/scripts/openroad/or_floorplan.tcl |& tee >&@stdout /project/openlane/user_proj_example/runs/16-12_10-43/logs/floorplan/verilog2def.openroad.log"
+
+Wed Dec 16 10:52:54 UTC 2020 - Executing "python3 /openLANE_flow/scripts/io_place.py --input-lef /project/openlane/user_proj_example/runs/16-12_10-43/tmp/merged.lef --input-def /project/openlane/user_proj_example/runs/16-12_10-43/tmp/floorplan/verilog2def_openroad.def --config /project/openlane/user_proj_example/pin_order.cfg --hor-layer 4 --ver-layer 3 --ver-width-mult 2 --hor-width-mult 2 --hor-extension -1 --ver-extension -1 --length 4 -o /project/openlane/user_proj_example/runs/16-12_10-43/tmp/floorplan/ioPlacer.def |& tee /project/openlane/user_proj_example/runs/16-12_10-43/logs/floorplan/place_io_ol.log >&@stdout"
+
+Wed Dec 16 10:53:02 UTC 2020 - Executing "openroad -exit /openLANE_flow/scripts/openroad/or_tapcell.tcl |& tee >&@stdout /project/openlane/user_proj_example/runs/16-12_10-43/logs/floorplan/tapcell.log"
+
+Wed Dec 16 10:53:25 UTC 2020 - Executing "openroad -exit /openLANE_flow/scripts/new_pdn.tcl |& tee >&@stdout /project/openlane/user_proj_example/runs/16-12_10-43/logs/floorplan/pdn.log"
+
+Wed Dec 16 10:53:53 UTC 2020 - Executing "openroad -exit /openLANE_flow/scripts/openroad/or_replace.tcl |& tee >&@stdout /project/openlane/user_proj_example/runs/16-12_10-43/logs/placement/replace.log"
+
+Wed Dec 16 10:57:01 UTC 2020 - Executing "/openLANE_flow/scripts/libtrim.pl /mnt/data/workspace/pdk/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_100C_1v60.lib /mnt/data/workspace/pdk/sky130A/libs.tech/openlane/sky130_fd_sc_hd/no_synth.cells > /project/openlane/user_proj_example/runs/16-12_10-43/tmp/opt.lib"
+
+Wed Dec 16 10:57:01 UTC 2020 - Executing "Psn /openLANE_flow/scripts/openPhySyn.tcl |& tee >&@stdout /project/openlane/user_proj_example/runs/16-12_10-43/logs/placement/openphysyn.log"
+
+Wed Dec 16 11:00:15 UTC 2020 - Executing "openroad -exit /openLANE_flow/scripts/openroad/or_write_verilog.tcl |& tee >&@stdout /project/openlane/user_proj_example/runs/16-12_10-43/logs/write_verilog.log"
+
+Wed Dec 16 11:00:21 UTC 2020 - Executing "sed -i -e {s/\(set ::env(CURRENT_NETLIST)\).*/\1 \/project\/openlane\/user_proj_example\/runs\/16-12_10-43\/results\/synthesis\/user_proj_example.synthesis_optimized.v/} /project/openlane/user_proj_example/runs/16-12_10-43/config.tcl"
+
+Wed Dec 16 11:00:21 UTC 2020 - Executing "sed -i -e {s/\(set ::env(PREV_NETLIST)\).*/\1 \/project\/openlane\/user_proj_example\/runs\/16-12_10-43\/results\/synthesis\/user_proj_example.synthesis.v/} /project/openlane/user_proj_example/runs/16-12_10-43/config.tcl"
+
+Wed Dec 16 11:00:21 UTC 2020 - Executing "sta /openLANE_flow/scripts/sta.tcl |& tee >&@stdout /project/openlane/user_proj_example/runs/16-12_10-43/logs/synthesis/opensta_post_openphysyn.log"
+
+Wed Dec 16 11:00:32 UTC 2020 - Executing "openroad -exit /openLANE_flow/scripts/openroad/or_opendp.tcl |& tee >&@stdout /project/openlane/user_proj_example/runs/16-12_10-43/logs/placement/opendp.log"
+
+Wed Dec 16 11:00:41 UTC 2020 - Executing "openroad -exit /openLANE_flow/scripts/openroad/or_cts.tcl |& tee >&@stdout /project/openlane/user_proj_example/runs/16-12_10-43/logs/cts/cts.log"
+
+Wed Dec 16 11:02:43 UTC 2020 - Executing "openroad -exit /openLANE_flow/scripts/openroad/or_write_verilog.tcl |& tee >&@stdout /project/openlane/user_proj_example/runs/16-12_10-43/logs/write_verilog.log"
+
+Wed Dec 16 11:02:49 UTC 2020 - Executing "sed -i -e {s/\(set ::env(CURRENT_NETLIST)\).*/\1 \/project\/openlane\/user_proj_example\/runs\/16-12_10-43\/results\/synthesis\/user_proj_example.synthesis_cts.v/} /project/openlane/user_proj_example/runs/16-12_10-43/config.tcl"
+
+Wed Dec 16 11:02:49 UTC 2020 - Executing "sed -i -e {s/\(set ::env(PREV_NETLIST)\).*/\1 \/project\/openlane\/user_proj_example\/runs\/16-12_10-43\/results\/synthesis\/user_proj_example.synthesis_optimized.v/} /project/openlane/user_proj_example/runs/16-12_10-43/config.tcl"
+
+Wed Dec 16 11:02:49 UTC 2020 - Executing "python3 /project/openlane/user_proj_example/scripts/place_diodes.py -l /project/openlane/user_proj_example/runs/16-12_10-43/tmp/merged.lef -id /project/openlane/user_proj_example/runs/16-12_10-43/results/cts/user_proj_example.cts.def -o /project/openlane/user_proj_example/runs/16-12_10-43/tmp/placement/user_proj_example.diodes.def |& tee >&@stdout /project/openlane/user_proj_example/runs/16-12_10-43/logs/diodes.log"
+
+Wed Dec 16 11:03:20 UTC 2020 - Executing "opendp -lef /project/openlane/user_proj_example/runs/16-12_10-43/tmp/merged.lef -def /project/openlane/user_proj_example/runs/16-12_10-43/tmp/placement/user_proj_example.diodes.def -output_def /project/openlane/user_proj_example/runs/16-12_10-43/results/placement/user_proj_example.placement.def |& tee >&@stdout /project/openlane/user_proj_example/runs/16-12_10-43/logs/placement/opendp.log"
+
+Wed Dec 16 11:03:36 UTC 2020 - Executing "openroad -exit /openLANE_flow/scripts/openroad/or_route.tcl |& tee >&@stdout /project/openlane/user_proj_example/runs/16-12_10-43/logs/routing/fastroute.log"
+
+Wed Dec 16 11:05:00 UTC 2020 - Executing "openroad -exit /openLANE_flow/scripts/openroad/or_fill.tcl |& tee >&@stdout /project/openlane/user_proj_example/runs/16-12_10-43/logs/routing/addspacers.log"
+
+Wed Dec 16 11:05:10 UTC 2020 - Executing "openroad -exit /openLANE_flow/scripts/openroad/or_write_verilog.tcl |& tee >&@stdout /project/openlane/user_proj_example/runs/16-12_10-43/logs/write_verilog.log"
+
+Wed Dec 16 11:05:22 UTC 2020 - Executing "sed -i -e {s/\(set ::env(CURRENT_NETLIST)\).*/\1 \/project\/openlane\/user_proj_example\/runs\/16-12_10-43\/results\/synthesis\/user_proj_example.synthesis_preroute.v/} /project/openlane/user_proj_example/runs/16-12_10-43/config.tcl"
+
+Wed Dec 16 11:05:22 UTC 2020 - Executing "sed -i -e {s/\(set ::env(PREV_NETLIST)\).*/\1 \/project\/openlane\/user_proj_example\/runs\/16-12_10-43\/results\/synthesis\/user_proj_example.synthesis_cts.v/} /project/openlane/user_proj_example/runs/16-12_10-43/config.tcl"
+
+Wed Dec 16 11:05:22 UTC 2020 - Executing "python3 /openLANE_flow/scripts/addObstruction.py -d /project/openlane/user_proj_example/runs/16-12_10-43/tmp/routing/addspacers.def -l /project/openlane/user_proj_example/runs/16-12_10-43/tmp/merged_unpadded.lef -obs core_obs_0 -ln met5 -px 0 -py 0 -sw 2500 -sh 3100 -db 1000 -f"
+
+Wed Dec 16 11:05:23 UTC 2020 - Executing "envsubst < /openLANE_flow/scripts/tritonRoute.param > /project/openlane/user_proj_example/runs/16-12_10-43/tmp/routing/tritonRoute.param"
+
+Wed Dec 16 11:05:23 UTC 2020 - Executing "TritonRoute /project/openlane/user_proj_example/runs/16-12_10-43/tmp/routing/tritonRoute.param |& tee >&@stdout /project/openlane/user_proj_example/runs/16-12_10-43/logs/routing/tritonRoute.log"
+
+Wed Dec 16 13:32:50 UTC 2020 - Executing "python3 /openLANE_flow/scripts/tr2klayout.py -i /project/openlane/user_proj_example/runs/16-12_10-43/reports/routing/tritonRoute.drc -o /project/openlane/user_proj_example/runs/16-12_10-43/reports/routing/tritonRoute.klayout.xml --design-name user_proj_example"
+
+Wed Dec 16 13:32:50 UTC 2020 - Executing "python3 /openLANE_flow/scripts/spef_extractor/main.py -l /project/openlane/user_proj_example/runs/16-12_10-43/tmp/merged_unpadded.lef -d /project/openlane/user_proj_example/runs/16-12_10-43/results/routing/user_proj_example.def -mw L -ec 1 |& tee >&@stdout /project/openlane/user_proj_example/runs/16-12_10-43/logs/routing/spef_extraction.log"
+
+Wed Dec 16 13:35:43 UTC 2020 - Executing "sta /openLANE_flow/scripts/sta.tcl |& tee >&@stdout /project/openlane/user_proj_example/runs/16-12_10-43/logs/synthesis/opensta_spef.log"
+
+Wed Dec 16 13:36:21 UTC 2020 - Executing "python3 /openLANE_flow/scripts/write_powered_def.py -d /project/openlane/user_proj_example/runs/16-12_10-43/results/routing/user_proj_example.def -l /project/openlane/user_proj_example/runs/16-12_10-43/tmp/merged.lef -v VPWR -g VGND -o /project/openlane/user_proj_example/runs/16-12_10-43/tmp/routing/user_proj_example.powered.def |& tee >&@stdout /project/openlane/user_proj_example/runs/16-12_10-43/logs/lvs/write_powered_verilog.log"
+
+Wed Dec 16 13:37:11 UTC 2020 - Executing "openroad -exit /openLANE_flow/scripts/openroad/or_write_verilog.tcl |& tee >&@stdout /project/openlane/user_proj_example/runs/16-12_10-43/logs/write_verilog.log"
+
+Wed Dec 16 13:37:34 UTC 2020 - Executing "yosys -c /openLANE_flow/scripts/yosys_rewrite_verilog.tcl -l /project/openlane/user_proj_example/runs/16-12_10-43/logs/synthesis/yosys_rewrite_verilog.log"
+
+Wed Dec 16 14:50:14 UTC 2020 - Executing "sed -i -e {s/\(set ::env(CURRENT_NETLIST)\).*/\1 \/project\/openlane\/user_proj_example\/runs\/16-12_10-43\/results\/lvs\/user_proj_example.lvs.powered.v/} /project/openlane/user_proj_example/runs/16-12_10-43/config.tcl"
+
+Wed Dec 16 14:50:14 UTC 2020 - Executing "sed -i -e {s/\(set ::env(PREV_NETLIST)\).*/\1 \/project\/openlane\/user_proj_example\/runs\/16-12_10-43\/results\/synthesis\/user_proj_example.synthesis_preroute.v/} /project/openlane/user_proj_example/runs/16-12_10-43/config.tcl"
+
+Wed Dec 16 14:50:14 UTC 2020 - Executing "magic -noconsole -dnull -rcfile /mnt/data/workspace/pdk/sky130A/libs.tech/magic/sky130A.magicrc /openLANE_flow/scripts/magic/mag_lef_gds.tcl </dev/null |& tee >&@stdout /project/openlane/user_proj_example/runs/16-12_10-43/logs/magic/magic.log"
+
+Wed Dec 16 15:07:52 UTC 2020 - Executing "magic -noconsole -dnull -rcfile /mnt/data/workspace/pdk/sky130A/libs.tech/magic/sky130A.magicrc /openLANE_flow/scripts/magic/maglef.tcl </dev/null |& tee >&@stdout /project/openlane/user_proj_example/runs/16-12_10-43/logs/magic/magic.maglef.log"
+
+Wed Dec 16 15:07:52 UTC 2020 - Executing "magic -noconsole -dnull -rcfile /mnt/data/workspace/pdk/sky130A/libs.tech/magic/sky130A.magicrc /project/openlane/user_proj_example/runs/16-12_10-43/tmp/magic_spice.tcl </dev/null |& tee >&@stdout /project/openlane/user_proj_example/runs/16-12_10-43/logs/magic/magic_spice.log"
+
+Wed Dec 16 17:05:32 UTC 2020 - Executing "magic -noconsole -dnull -rcfile /mnt/data/workspace/pdk/sky130A/libs.tech/magic/sky130A.magicrc /openLANE_flow/scripts/magic/drc.tcl </dev/null |& tee >&@stdout /project/openlane/user_proj_example/runs/16-12_10-43/logs/magic/magic.drc.log"
+
+Wed Dec 16 18:04:09 UTC 2020 - Executing "netgen -batch lvs {/project/openlane/user_proj_example/runs/16-12_10-43/results/magic/user_proj_example.spice user_proj_example} {/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v user_proj_example} /mnt/data/workspace/pdk/sky130A/libs.tech/netgen/sky130A_setup.tcl /project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.log -json |& tee >&@stdout /project/openlane/user_proj_example/runs/16-12_10-43/logs/lvs/lvs.log"
+
+Wed Dec 16 20:46:34 UTC 2020 - Executing "openroad -exit /openLANE_flow/scripts/openroad/or_antenna_check.tcl |& tee >&@stdout /project/openlane/user_proj_example/runs/16-12_10-43/logs/routing/or_antenna.log"
+
+Wed Dec 16 20:47:17 UTC 2020 - Executing "python3 /openLANE_flow/report_generation_wrapper.py -d /project/openlane/user_proj_example -dn user_proj_example -t 16-12_10-43 -o /project/openlane/user_proj_example/runs/16-12_10-43/reports/final_summary_report.csv -r /project/openlane/user_proj_example/runs/16-12_10-43"
+
+Wed Dec 16 20:47:17 UTC 2020 - Executing "magic -noconsole -dnull -rcfile /mnt/data/workspace/pdk/sky130A/libs.tech/magic/sky130A.magicrc /project/openlane/user_proj_example/runs/16-12_10-43/tmp/magic_antenna.tcl </dev/null |& tee >&@stdout /project/openlane/user_proj_example/runs/16-12_10-43/logs/magic/magic_antenna.log"
+
+Thu Dec 17 02:04:34 UTC 2020 - Executing "awk {/Cell:/ {print $2}} /project/openlane/user_proj_example/runs/16-12_10-43/logs/magic/magic_antenna.log > /project/openlane/user_proj_example/runs/16-12_10-43/reports/magic/magic.antenna_violators.rpt"
+
diff --git a/openlane/user_proj_example/results/config.tcl b/openlane/user_proj_example/results/config.tcl
new file mode 100644
index 0000000..bcc68b8
--- /dev/null
+++ b/openlane/user_proj_example/results/config.tcl
@@ -0,0 +1,89 @@
+# General config
+set ::env(PDK) "sky130A"
+set ::env(STD_CELL_LIBRARY) "sky130_fd_sc_hd"
+set ::env(PDK_ROOT) "/mnt/data/workspace/pdk"
+set ::env(CELL_PAD) "8"
+set ::env(MERGED_LEF) "/project/openlane/user_proj_example/runs/16-12_10-43/tmp/merged.lef"
+set ::env(MERGED_LEF_UNPADDED) "/project/openlane/user_proj_example/runs/16-12_10-43/tmp/merged_unpadded.lef"
+set ::env(TRACKS_INFO_FILE) "/project/openlane/user_proj_example/runs/16-12_10-43/tmp/tracks_copy.info"
+set ::env(TECH_LEF) "/mnt/data/workspace/pdk/sky130A/libs.ref/sky130_fd_sc_hd/techlef/sky130_fd_sc_hd.tlef"
+# Design config
+set ::env(CLOCK_PERIOD) "20"
+set ::env(DESIGN_NAME) "user_proj_example"
+set ::env(DESIGN_DIR) "/project/openlane/user_proj_example"
+set ::env(CLOCK_PORT) "wb_clk_i"
+# Synthesis config
+set ::env(LIB_SYNTH) "/project/openlane/user_proj_example/runs/16-12_10-43/tmp/trimmed.lib"
+set ::env(LIB_SYNTH_COMPLETE) "/mnt/data/workspace/pdk/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib"
+set ::env(SYNTH_DRIVING_CELL) "sky130_fd_sc_hd__inv_8"
+set ::env(SYNTH_CAP_LOAD) "17.65"
+set ::env(SYNTH_MAX_FANOUT) "5"
+set ::env(SYNTH_NO_FLAT) "0"
+set ::env(SYNTH_MAX_TRAN) "[expr {0.1*20}]"
+set ::env(LIB_FASTEST) "/mnt/data/workspace/pdk/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_n40C_1v95.lib"
+set ::env(LIB_SLOWEST) "/mnt/data/workspace/pdk/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_100C_1v60.lib"
+set ::env(LIB_TYPICAL) "/mnt/data/workspace/pdk/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib"
+set ::env(SYNTH_SCRIPT) "/openLANE_flow/scripts/synth.tcl"
+set ::env(SYNTH_STRATEGY) "2"
+set ::env(CLOCK_BUFFER_FANOUT) "16"
+set ::env(BASE_SDC_FILE) "/openLANE_flow/scripts/base.sdc"
+# Floorplan config
+set ::env(FP_CORE_UTIL) "50"
+set ::env(FP_ASPECT_RATIO) "1"
+set ::env(FP_CORE_MARGIN) "0"
+set ::env(FP_IO_HMETAL) "4"
+set ::env(FP_IO_VMETAL) "3"
+set ::env(FP_WELLTAP_CELL) "sky130_fd_sc_hd__tapvpwrvgnd_1"
+set ::env(FP_ENDCAP_CELL) "sky130_fd_sc_hd__decap_3"
+set ::env(FP_PDN_VOFFSET) "16.32"
+set ::env(FP_PDN_VPITCH) "153.6"
+set ::env(FP_PDN_HOFFSET) "16.65"
+set ::env(FP_PDN_HPITCH) "153.18"
+set ::env(FP_TAPCELL_DIST) "14"
+set ::env(CELL_PAD_EXCLUDE) "sky130_fd_sc_hd__tap* sky130_fd_sc_hd__decap* sky130_fd_sc_hd__fill*"
+# Placement config
+set ::env(PL_TARGET_DENSITY) "0.38"
+set ::env(PL_TIME_DRIVEN) "0"
+set ::env(PL_LIB) "/mnt/data/workspace/pdk/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib"
+set ::env(PL_BASIC_PLACEMENT) "0"
+set ::env(PL_SKIP_INITIAL_PLACEMENT) "0"
+set ::env(PL_RANDOM_GLB_PLACEMENT) "0"
+set ::env(PL_OPENPHYSYN_OPTIMIZATIONS) "1"
+set ::env(PSN_ENABLE_RESIZING) "1"
+set ::env(PSN_ENABLE_PIN_SWAP) "1"
+set ::env(PL_RESIZER_OVERBUFFER) "0"
+# CTS config
+set ::env(CTS_TARGET_SKEW) "200"
+set ::env(CTS_ROOT_BUFFER) "sky130_fd_sc_hd__clkbuf_16"
+set ::env(CTS_TECH_DIR) "N/A"
+set ::env(CTS_TOLERANCE) "100"
+# Routing config
+set ::env(GLB_RT_MAXLAYER) "5"
+set ::env(GLB_RT_ADJUSTMENT) "0"
+set ::env(GLB_RT_L1_ADJUSTMENT) "0.99"
+set ::env(GLB_RT_L2_ADJUSTMENT) "0"
+set ::env(GLB_RT_MINLAYER) "1"
+set ::env(GLB_RT_MAXLAYER) "5"
+set ::env(GLB_RT_UNIDIRECTIONAL) "1"
+set ::env(GLB_RT_ALLOW_CONGESTION) "0"
+set ::env(GLB_RT_OVERFLOW_ITERS) "50"
+set ::env(GLB_RT_TILES) "15"
+set ::env(GLB_RT_ESTIMATE_PARASITICS) "1"
+set ::env(GLB_RT_MAX_DIODE_INS_ITERS) "1"
+set ::env(DIODE_PADDING) "2"
+set ::env(SPEF_WIRE_MODEL) "L"
+set ::env(SPEF_EDGE_CAP_FACTOR) "1"
+# Flow control config
+set ::env(RUN_SIMPLE_CTS) "0"
+set ::env(RUN_ROUTING_DETAILED) "1"
+set ::env(CLOCK_TREE_SYNTH) "1"
+set ::env(LEC_ENABLE) "0"
+set ::env(FILL_INSERTION) "1"
+set ::env(DIODE_INSERTION_STRATEGY) "0"
+set ::env(CHECK_ASSIGN_STATEMENTS) "0"
+set ::env(CHECK_UNMAPPED_CELLS) "1"
+set ::env(USE_ARC_ANTENNA_CHECK) "1"
+set ::env(RUN_SPEF_EXTRACTION) "1"
+set ::env(CURRENT_DEF) /project/openlane/user_proj_example/runs/16-12_10-43/results/routing/user_proj_example.def
+set ::env(CURRENT_NETLIST) /project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v
+set ::env(PREV_NETLIST) /project/openlane/user_proj_example/runs/16-12_10-43/results/synthesis/user_proj_example.synthesis_preroute.v
diff --git a/openlane/user_proj_example/results/logs/cts/cts.log b/openlane/user_proj_example/results/logs/cts/cts.log
new file mode 100644
index 0000000..7d8d8eb
--- /dev/null
+++ b/openlane/user_proj_example/results/logs/cts/cts.log
@@ -0,0 +1,205 @@
+OpenROAD 0.9.0 d03ebfc244
+This program is licensed under the BSD-3 license. See the LICENSE file for details.
+Components of this program may be licensed under more restrictive licenses which must be honored.
+Error: cannot open '/.openroad'.
+Notice 0: Reading LEF file: /project/openlane/user_proj_example/runs/16-12_10-43/tmp/merged_unpadded.lef
+Notice 0: Created 13 technology layers
+Notice 0: Created 25 technology vias
+Notice 0: Created 438 library cells
+Notice 0: Finished LEF file: /project/openlane/user_proj_example/runs/16-12_10-43/tmp/merged_unpadded.lef
+Warning: /mnt/data/workspace/pdk/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib, line 31 default_operating_condition tt_025C_1v80 not found.
+Notice 0:
+Reading DEF file: /project/openlane/user_proj_example/runs/16-12_10-43/results/placement/user_proj_example.placement.def
+Notice 0: Design: user_proj_example
+Notice 0: Created 100000 Insts
+Notice 0: Created 200000 Insts
+Notice 0: Created 100000 Nets
+Notice 0: Created 606 pins.
+Notice 0: Created 289992 components and 1555826 component-terminals.
+Notice 0: Created 2 special nets and 0 connections.
+Notice 0: Created 187833 nets and 596309 connections.
+Notice 0: Finished DEF file: /project/openlane/user_proj_example/runs/16-12_10-43/results/placement/user_proj_example.placement.def
+[INFO]: Setting output delay to: 4.0
+[INFO]: Setting input delay to: 4.0
+[INFO]: Setting load to: 0.01765
+[INFO]: Configuring cts characterization...
+[INFO]: Performing clock tree synthesis...
+[INFO]: Looking for the following net(s): wb_clk_i
+ *****************
+ * TritonCTS 2.0 *
+ *****************
+ *****************************
+ * Create characterization *
+ *****************************
+Number of created patterns = 50000.
+Number of created patterns = 100000.
+Number of created patterns = 150000.
+Number of created patterns = 200000.
+Number of created patterns = 250000.
+Number of created patterns = 300000.
+Number of created patterns = 313632.
+ Compiling LUT
+ Min. len Max. len Min. cap Max. cap Min. slew Max. slew
+ 2 8 1 39 1 318
+ [WARNING] 6336 wires are pure wire and no slew degration.
+ TritonCTS forced slew degradation on these wires.
+ Num wire segments: 313632
+ Num keys in characterization LUT: 2039
+ Actual min input cap: 2
+ **********************
+ * Find clock roots *
+ **********************
+ Running TritonCTS with user-specified clock roots: wb_clk_i
+ ************************
+ * Populate TritonCTS *
+ ************************
+ Initializing clock nets
+ Looking for clock nets in the design
+ Net "wb_clk_i" found
+ Initializing clock net for : "wb_clk_i"
+ Clock net "wb_clk_i" has 26773 sinks
+ TritonCTS found 1 clock nets.
+ ****************************
+ * Check characterization *
+ ****************************
+ The chacterization used 4 buffer(s) types. All of them are in the loaded DB.
+ ***********************
+ * Build clock trees *
+ ***********************
+ Generating H-Tree topology for net wb_clk_i...
+ Tot. number of sinks: 26773
+ Number of static layers: 0
+ Wire segment unit: 13000 dbu (13 um)
+ Original sink region: [(55925, 88460), (2459425, 2928140)]
+ Normalized sink region: [(4.30192, 6.80462), (189.187, 225.242)]
+ Width: 184.885
+ Height: 218.437
+ Level 1
+ Direction: Vertical
+ # sinks per sub-region: 13387
+ Sub-region size: 184.885 X 109.218
+ Segment length (rounded): 54
+ Key: 9408 outSlew: 34 load: 1 length: 8 isBuffered: 1
+ Key: 7971 outSlew: 11 load: 1 length: 8 isBuffered: 1
+ Key: 9417 outSlew: 34 load: 1 length: 8 isBuffered: 1
+ Key: 7971 outSlew: 11 load: 1 length: 8 isBuffered: 1
+ Key: 9417 outSlew: 34 load: 1 length: 8 isBuffered: 1
+ Key: 7971 outSlew: 11 load: 1 length: 8 isBuffered: 1
+ Key: 1881 outSlew: 23 load: 1 length: 6 isBuffered: 1
+ Level 2
+ Direction: Horizontal
+ # sinks per sub-region: 6694
+ Sub-region size: 92.4423 X 109.218
+ Segment length (rounded): 46
+ Key: 7971 outSlew: 11 load: 1 length: 8 isBuffered: 1
+ Key: 9417 outSlew: 34 load: 1 length: 8 isBuffered: 1
+ Key: 7971 outSlew: 11 load: 1 length: 8 isBuffered: 1
+ Key: 9417 outSlew: 34 load: 1 length: 8 isBuffered: 1
+ Key: 7971 outSlew: 11 load: 1 length: 8 isBuffered: 1
+ Key: 1881 outSlew: 23 load: 1 length: 6 isBuffered: 1
+ Level 3
+ Direction: Vertical
+ # sinks per sub-region: 3347
+ Sub-region size: 92.4423 X 54.6092
+ Segment length (rounded): 28
+ Key: 7971 outSlew: 11 load: 1 length: 8 isBuffered: 1
+ Key: 9417 outSlew: 34 load: 1 length: 8 isBuffered: 1
+ Key: 7971 outSlew: 11 load: 1 length: 8 isBuffered: 1
+ Key: 337 outSlew: 11 load: 1 length: 4 isBuffered: 1
+ Level 4
+ Direction: Horizontal
+ # sinks per sub-region: 1674
+ Sub-region size: 46.2212 X 54.6092
+ Segment length (rounded): 24
+ Key: 9417 outSlew: 34 load: 1 length: 8 isBuffered: 1
+ Key: 7971 outSlew: 11 load: 1 length: 8 isBuffered: 1
+ Key: 9417 outSlew: 34 load: 1 length: 8 isBuffered: 1
+ Level 5
+ Direction: Vertical
+ # sinks per sub-region: 837
+ Sub-region size: 46.2212 X 27.3046
+ Segment length (rounded): 14
+ Key: 7971 outSlew: 11 load: 1 length: 8 isBuffered: 1
+ Key: 1881 outSlew: 23 load: 1 length: 6 isBuffered: 1
+ Level 6
+ Direction: Horizontal
+ # sinks per sub-region: 419
+ Sub-region size: 23.1106 X 27.3046
+ Segment length (rounded): 12
+ Key: 7971 outSlew: 11 load: 1 length: 8 isBuffered: 1
+ Key: 337 outSlew: 11 load: 1 length: 4 isBuffered: 1
+ Level 7
+ Direction: Vertical
+ # sinks per sub-region: 210
+ Sub-region size: 23.1106 X 13.6523
+ Segment length (rounded): 6
+ Key: 1881 outSlew: 23 load: 1 length: 6 isBuffered: 1
+ Level 8
+ Direction: Horizontal
+ # sinks per sub-region: 105
+ Sub-region size: 11.5553 X 13.6523
+ Segment length (rounded): 6
+ Key: 1639 outSlew: 11 load: 1 length: 6 isBuffered: 1
+ Level 9
+ Direction: Vertical
+ # sinks per sub-region: 53
+ Sub-region size: 11.5553 X 6.82615
+ Segment length (rounded): 4
+ Key: 337 outSlew: 11 load: 1 length: 4 isBuffered: 1
+ Level 10
+ Direction: Horizontal
+ # sinks per sub-region: 27
+ Sub-region size: 5.77764 X 6.82615
+ Segment length (rounded): 2
+ Key: 53 outSlew: 11 load: 1 length: 2 isBuffered: 1
+ [WARNING] Creating fake entries in the LUT.
+ Level 11
+ Direction: Vertical
+ # sinks per sub-region: 14
+ Sub-region size: 5.77764 X 3.41308
+ Segment length (rounded): 1
+ Key: 313873 outSlew: 11 load: 1 length: 1 isBuffered: 1
+ Stop criterion found. Max number of sinks is (15)
+ Building clock sub nets...
+ Number of sinks covered: 26773
+ Clock topology of net "wb_clk_i" done.
+ ****************
+ * Post CTS opt *
+ ****************
+ Avg. source sink dist: 36909.2 dbu.
+ Num outlier sinks: 27
+ ********************
+ * Write data to DB *
+ ********************
+ Writing clock net "wb_clk_i" to DB
+ Created 4306 clock buffers.
+ Minimum number of buffers in the clock path: 30.
+ Maximum number of buffers in the clock path: 31.
+ Created 4306 clock nets.
+ Fanout distribution for the current clock = 3:1, 4:8, 5:26, 6:45, 7:69, 8:110, 9:138, 10:164, 11:164, 12:219, 13:199, 14:200, 15:197, 16:171, 17:107, 18:81, 19:50, 20:23, 21:18, 22:14, 23:7, 24:7, 25:3, 26:6, 27:5, 28:4, 29:2, 30:3, 31:1, 33:1, 34:2, 39:2, 45:1.
+ Max level of the clock tree: 11.
+ ... End of TritonCTS execution.
+[INFO]: Legalizing...
+Design Stats
+--------------------------------
+total instances 294298
+multi row instances 0
+fixed instances 102526
+nets 192141
+design area 7655730.0 u^2
+fixed area 133941.0 u^2
+movable area 2233269.4 u^2
+utilization 30 %
+utilization padded 30 %
+rows 1131
+row height 2.7 u
+
+Placement Analysis
+--------------------------------
+total displacement 16727.1 u
+average displacement 0.1 u
+max displacement 20.2 u
+original HPWL 12512726.0 u
+legalized HPWL 12515668.9 u
+delta HPWL 0 %
+
diff --git a/openlane/user_proj_example/results/logs/cts/cts_runtime.txt b/openlane/user_proj_example/results/logs/cts/cts_runtime.txt
new file mode 100644
index 0000000..ac243af
--- /dev/null
+++ b/openlane/user_proj_example/results/logs/cts/cts_runtime.txt
@@ -0,0 +1 @@
+0h2m2s145ms
diff --git a/openlane/user_proj_example/results/logs/diodes.log b/openlane/user_proj_example/results/logs/diodes.log
new file mode 100644
index 0000000..9ceaa90
--- /dev/null
+++ b/openlane/user_proj_example/results/logs/diodes.log
@@ -0,0 +1,17 @@
+Notice 0: Reading LEF file: /project/openlane/user_proj_example/runs/16-12_10-43/tmp/merged.lef
+Notice 0: Created 13 technology layers
+Notice 0: Created 25 technology vias
+Notice 0: Created 438 library cells
+Notice 0: Finished LEF file: /project/openlane/user_proj_example/runs/16-12_10-43/tmp/merged.lef
+Notice 0:
+Reading DEF file: /project/openlane/user_proj_example/runs/16-12_10-43/results/cts/user_proj_example.cts.def
+Notice 0: Design: user_proj_example
+Notice 0: Created 100000 Insts
+Notice 0: Created 200000 Insts
+Notice 0: Created 100000 Nets
+Notice 0: Created 606 pins.
+Notice 0: Created 294298 components and 1581662 component-terminals.
+Notice 0: Created 2 special nets and 0 connections.
+Notice 0: Created 192139 nets and 604921 connections.
+Notice 0: Finished DEF file: /project/openlane/user_proj_example/runs/16-12_10-43/results/cts/user_proj_example.cts.def
+Design name: user_proj_example
diff --git a/openlane/user_proj_example/results/logs/floorplan/pdn.log b/openlane/user_proj_example/results/logs/floorplan/pdn.log
new file mode 100644
index 0000000..9df4d8d
--- /dev/null
+++ b/openlane/user_proj_example/results/logs/floorplan/pdn.log
@@ -0,0 +1,37 @@
+OpenROAD 0.9.0 d03ebfc244
+This program is licensed under the BSD-3 license. See the LICENSE file for details.
+Components of this program may be licensed under more restrictive licenses which must be honored.
+Error: cannot open '/.openroad'.
+Notice 0: Reading LEF file: /project/openlane/user_proj_example/runs/16-12_10-43/tmp/merged_unpadded.lef
+Notice 0: Created 13 technology layers
+Notice 0: Created 25 technology vias
+Notice 0: Created 438 library cells
+Notice 0: Finished LEF file: /project/openlane/user_proj_example/runs/16-12_10-43/tmp/merged_unpadded.lef
+Notice 0:
+Reading DEF file: /project/openlane/user_proj_example/runs/16-12_10-43/results/floorplan/user_proj_example.floorplan.def
+Notice 0: Design: user_proj_example
+Notice 0: Created 100000 Insts
+Notice 0: Created 200000 Insts
+Notice 0: Created 100000 Nets
+Notice 0: Created 604 pins.
+Notice 0: Created 289855 components and 1555004 component-terminals.
+Notice 0: Created 187696 nets and 596035 connections.
+Notice 0: Finished DEF file: /project/openlane/user_proj_example/runs/16-12_10-43/results/floorplan/user_proj_example.floorplan.def
+[INFO] [PDNG-0016] Power Delivery Network Generator: Generating PDN
+[INFO] [PDNG-0016] config: /mnt/data/workspace/pdk/sky130A/libs.tech/openlane/common_pdn.tcl
+[INFO] [PDNG-0008] Design Name is user_proj_example
+[INFO] [PDNG-0009] Reading technology data
+[INFO] [PDNG-0011] ****** INFO ******
+Type: stdcell, grid
+ Stdcell Rails
+ Layer: met1 - width: 0.480 pitch: 2.720 offset: 0.000
+ Straps
+ Layer: met4 - width: 1.600 pitch: 153.600 offset: 16.320
+ Connect: {met1 met4}
+Type: macro, macro_1
+ Macro orientation: R0 R180 MX MY R90 R270 MXR90 MYR90
+ Straps
+ Connect: {met4_PIN_ver met5}
+[INFO] [PDNG-0012] **** END INFO ****
+[INFO] [PDNG-0013] Inserting stdcell grid - grid
+[INFO] [PDNG-0015] Writing to database
diff --git a/openlane/user_proj_example/results/logs/floorplan/pdn_runtime.txt b/openlane/user_proj_example/results/logs/floorplan/pdn_runtime.txt
new file mode 100644
index 0000000..31036f6
--- /dev/null
+++ b/openlane/user_proj_example/results/logs/floorplan/pdn_runtime.txt
@@ -0,0 +1 @@
+0h0m27s794ms
diff --git a/openlane/user_proj_example/results/logs/floorplan/place_io_ol.log b/openlane/user_proj_example/results/logs/floorplan/place_io_ol.log
new file mode 100644
index 0000000..4e4d815
--- /dev/null
+++ b/openlane/user_proj_example/results/logs/floorplan/place_io_ol.log
@@ -0,0 +1,17 @@
+Notice 0: Reading LEF file: /project/openlane/user_proj_example/runs/16-12_10-43/tmp/merged.lef
+Notice 0: Created 13 technology layers
+Notice 0: Created 25 technology vias
+Notice 0: Created 438 library cells
+Notice 0: Finished LEF file: /project/openlane/user_proj_example/runs/16-12_10-43/tmp/merged.lef
+Notice 0:
+Reading DEF file: /project/openlane/user_proj_example/runs/16-12_10-43/tmp/floorplan/verilog2def_openroad.def
+Notice 0: Design: user_proj_example
+Notice 0: Created 100000 Insts
+Notice 0: Created 100000 Nets
+Notice 0: Created 604 pins.
+Notice 0: Created 187329 components and 1345428 component-terminals.
+Notice 0: Created 187696 nets and 596035 connections.
+Notice 0: Finished DEF file: /project/openlane/user_proj_example/runs/16-12_10-43/tmp/floorplan/verilog2def_openroad.def
+Top-level design name: user_proj_example
+Block boundaries: 0 0 2500000 3100000
+Writing /project/openlane/user_proj_example/runs/16-12_10-43/tmp/floorplan/ioPlacer.def
diff --git a/openlane/user_proj_example/results/logs/floorplan/tapcell.log b/openlane/user_proj_example/results/logs/floorplan/tapcell.log
new file mode 100644
index 0000000..7577ebf
--- /dev/null
+++ b/openlane/user_proj_example/results/logs/floorplan/tapcell.log
@@ -0,0 +1,28 @@
+OpenROAD 0.9.0 d03ebfc244
+This program is licensed under the BSD-3 license. See the LICENSE file for details.
+Components of this program may be licensed under more restrictive licenses which must be honored.
+Error: cannot open '/.openroad'.
+Notice 0: Reading LEF file: /project/openlane/user_proj_example/runs/16-12_10-43/tmp/merged_unpadded.lef
+Notice 0: Created 13 technology layers
+Notice 0: Created 25 technology vias
+Notice 0: Created 438 library cells
+Notice 0: Finished LEF file: /project/openlane/user_proj_example/runs/16-12_10-43/tmp/merged_unpadded.lef
+Notice 0:
+Reading DEF file: /project/openlane/user_proj_example/runs/16-12_10-43/tmp/floorplan/ioPlacer.def
+Notice 0: Design: user_proj_example
+Notice 0: Created 100000 Insts
+Notice 0: Created 100000 Nets
+Notice 0: Created 604 pins.
+Notice 0: Created 187329 components and 1345428 component-terminals.
+Notice 0: Created 187696 nets and 596035 connections.
+Notice 0: Finished DEF file: /project/openlane/user_proj_example/runs/16-12_10-43/tmp/floorplan/ioPlacer.def
+Running tapcell...
+Step 1: Cut rows...
+[INFO] Macro blocks found: 0
+[INFO] #Original rows: 1131
+[INFO] #Cut rows: 0
+Step 2: Insert endcaps...
+[INFO] #Endcaps inserted: 2262
+Step 3: Insert tapcells...
+[INFO] #Tapcells inserted: 100264
+Running tapcell... Done!
diff --git a/openlane/user_proj_example/results/logs/floorplan/tapcell_runtime.txt b/openlane/user_proj_example/results/logs/floorplan/tapcell_runtime.txt
new file mode 100644
index 0000000..db8799b
--- /dev/null
+++ b/openlane/user_proj_example/results/logs/floorplan/tapcell_runtime.txt
@@ -0,0 +1 @@
+0h0m23s329ms
diff --git a/openlane/user_proj_example/results/logs/floorplan/verilog2def.openroad.log b/openlane/user_proj_example/results/logs/floorplan/verilog2def.openroad.log
new file mode 100644
index 0000000..caef158
--- /dev/null
+++ b/openlane/user_proj_example/results/logs/floorplan/verilog2def.openroad.log
@@ -0,0 +1,11 @@
+OpenROAD 0.9.0 d03ebfc244
+This program is licensed under the BSD-3 license. See the LICENSE file for details.
+Components of this program may be licensed under more restrictive licenses which must be honored.
+Error: cannot open '/.openroad'.
+Warning: /mnt/data/workspace/pdk/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib, line 31 default_operating_condition tt_025C_1v80 not found.
+Notice 0: Reading LEF file: /project/openlane/user_proj_example/runs/16-12_10-43/tmp/merged_unpadded.lef
+Notice 0: Created 13 technology layers
+Notice 0: Created 25 technology vias
+Notice 0: Created 438 library cells
+Notice 0: Finished LEF file: /project/openlane/user_proj_example/runs/16-12_10-43/tmp/merged_unpadded.lef
+Info: Added 1131 rows of 5410 sites.
diff --git a/openlane/user_proj_example/results/logs/floorplan/verilog2def_openroad_runtime.txt b/openlane/user_proj_example/results/logs/floorplan/verilog2def_openroad_runtime.txt
new file mode 100644
index 0000000..3e036a5
--- /dev/null
+++ b/openlane/user_proj_example/results/logs/floorplan/verilog2def_openroad_runtime.txt
@@ -0,0 +1 @@
+0h0m6s742ms
diff --git a/openlane/user_proj_example/results/logs/lvs/lvs.log b/openlane/user_proj_example/results/logs/lvs/lvs.log
new file mode 100644
index 0000000..a5ee12d
--- /dev/null
+++ b/openlane/user_proj_example/results/logs/lvs/lvs.log
@@ -0,0 +1,503 @@
+Netgen 1.5.158 compiled on Sat Dec 5 19:50:01 UTC 2020
+Warning: netgen command 'format' use fully-qualified name '::netgen::format'
+Warning: netgen command 'global' use fully-qualified name '::netgen::global'
+Generating JSON file result
+Reading netlist file /project/openlane/user_proj_example/runs/16-12_10-43/results/magic/user_proj_example.spice
+Reading netlist file /project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v
+Warning: A case-insensitive file has been read and so the verilog file must be treated case-insensitive to match.
+Creating placeholder cell definition for module sky130_fd_sc_hd__diode_2.
+Creating placeholder cell definition for module sky130_fd_sc_hd__decap_12.
+Creating placeholder cell definition for module sky130_fd_sc_hd__decap_6.
+Creating placeholder cell definition for module sky130_fd_sc_hd__decap_3.
+Creating placeholder cell definition for module sky130_fd_sc_hd__decap_4.
+Creating placeholder cell definition for module sky130_fd_sc_hd__fill_1.
+Creating placeholder cell definition for module sky130_fd_sc_hd__decap_8.
+Creating placeholder cell definition for module sky130_fd_sc_hd__fill_2.
+Creating placeholder cell definition for module sky130_fd_sc_hd__tapvpwrvgnd_1.
+Creating placeholder cell definition for module sky130_fd_sc_hd__buf_2.
+Creating placeholder cell definition for module sky130_fd_sc_hd__inv_2.
+Creating placeholder cell definition for module sky130_fd_sc_hd__and2_4.
+Creating placeholder cell definition for module sky130_fd_sc_hd__a2bb2o_4.
+Creating placeholder cell definition for module sky130_fd_sc_hd__o22a_4.
+Creating placeholder cell definition for module sky130_fd_sc_hd__or4_4.
+Creating placeholder cell definition for module sky130_fd_sc_hd__or2_4.
+Creating placeholder cell definition for module sky130_fd_sc_hd__a21o_4.
+Creating placeholder cell definition for module sky130_fd_sc_hd__o21a_4.
+Creating placeholder cell definition for module sky130_fd_sc_hd__and4_4.
+Creating placeholder cell definition for module sky130_fd_sc_hd__or3_4.
+Creating placeholder cell definition for module sky130_fd_sc_hd__a32o_4.
+Creating placeholder cell definition for module sky130_fd_sc_hd__a21oi_4.
+Creating placeholder cell definition for module sky130_fd_sc_hd__o21ai_4.
+Creating placeholder cell definition for module sky130_fd_sc_hd__nor2_4.
+Creating placeholder cell definition for module sky130_fd_sc_hd__and3_4.
+Creating placeholder cell definition for module sky130_fd_sc_hd__a22oi_4.
+Creating placeholder cell definition for module sky130_fd_sc_hd__nand2_4.
+Creating placeholder cell definition for module sky130_fd_sc_hd__a211o_4.
+Creating placeholder cell definition for module sky130_fd_sc_hd__buf_4.
+Creating placeholder cell definition for module sky130_fd_sc_hd__inv_4.
+Creating placeholder cell definition for module sky130_fd_sc_hd__a21bo_4.
+Creating placeholder cell definition for module sky130_fd_sc_hd__o32a_4.
+Creating placeholder cell definition for module sky130_fd_sc_hd__a41o_4.
+Creating placeholder cell definition for module sky130_fd_sc_hd__o41a_4.
+Creating placeholder cell definition for module sky130_fd_sc_hd__a2111o_4.
+Creating placeholder cell definition for module sky130_fd_sc_hd__inv_8.
+Creating placeholder cell definition for module sky130_fd_sc_hd__conb_1.
+Note: Implicit pin HI
+Note: Implicit pin HI
+Note: Implicit pin HI
+Note: Implicit pin HI
+Note: Implicit pin HI
+Note: Implicit pin HI
+Note: Implicit pin HI
+Note: Implicit pin HI
+Note: Implicit pin HI
+Note: Implicit pin HI
+Note: Implicit pin HI
+Note: Implicit pin HI
+Note: Implicit pin HI
+Note: Implicit pin HI
+Note: Implicit pin HI
+Note: Implicit pin HI
+Note: Implicit pin HI
+Note: Implicit pin HI
+Note: Implicit pin HI
+Note: Implicit pin HI
+Note: Implicit pin HI
+Note: Implicit pin HI
+Note: Implicit pin HI
+Note: Implicit pin HI
+Note: Implicit pin HI
+Note: Implicit pin HI
+Note: Implicit pin HI
+Note: Implicit pin HI
+Note: Implicit pin HI
+Note: Implicit pin HI
+Note: Implicit pin HI
+Note: Implicit pin HI
+Note: Implicit pin HI
+Note: Implicit pin HI
+Note: Implicit pin HI
+Note: Implicit pin HI
+Note: Implicit pin HI
+Note: Implicit pin HI
+Note: Implicit pin HI
+Note: Implicit pin HI
+Note: Implicit pin HI
+Note: Implicit pin HI
+Note: Implicit pin HI
+Note: Implicit pin HI
+Note: Implicit pin HI
+Note: Implicit pin HI
+Note: Implicit pin HI
+Note: Implicit pin HI
+Note: Implicit pin HI
+Note: Implicit pin HI
+Note: Implicit pin HI
+Note: Implicit pin HI
+Note: Implicit pin HI
+Note: Implicit pin HI
+Note: Implicit pin HI
+Note: Implicit pin HI
+Note: Implicit pin HI
+Note: Implicit pin HI
+Note: Implicit pin HI
+Note: Implicit pin HI
+Note: Implicit pin HI
+Note: Implicit pin HI
+Note: Implicit pin HI
+Note: Implicit pin HI
+Note: Implicit pin HI
+Note: Implicit pin HI
+Note: Implicit pin HI
+Note: Implicit pin HI
+Note: Implicit pin HI
+Note: Implicit pin HI
+Note: Implicit pin HI
+Creating placeholder cell definition for module sky130_fd_sc_hd__dfxtp_4.
+Creating placeholder cell definition for module sky130_fd_sc_hd__dfrtp_4.
+Creating placeholder cell definition for module sky130_fd_sc_hd__dfstp_4.
+Creating placeholder cell definition for module sky130_fd_sc_hd__clkbuf_16.
+Creating placeholder cell definition for module sky130_fd_sc_hd__clkbuf_1.
+Creating placeholder cell definition for module sky130_fd_sc_hd__buf_8.
+Reading setup file /mnt/data/workspace/pdk/sky130A/libs.tech/netgen/sky130A_setup.tcl
+Comparison output logged to file /project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.log
+Logging to file "/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.log" enabled
+Contents of circuit 1: Circuit: 'sky130_fd_sc_hd__or2_4'
+Circuit sky130_fd_sc_hd__or2_4 contains 0 device instances.
+Circuit contains 0 nets, and 7 disconnected pins.
+Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__or2_4'
+Circuit sky130_fd_sc_hd__or2_4 contains 0 device instances.
+Circuit contains 0 nets.
+
+Circuit sky130_fd_sc_hd__or2_4 contains no devices.
+Contents of circuit 1: Circuit: 'sky130_fd_sc_hd__dfxtp_4'
+Circuit sky130_fd_sc_hd__dfxtp_4 contains 0 device instances.
+Circuit contains 0 nets, and 7 disconnected pins.
+Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__dfxtp_4'
+Circuit sky130_fd_sc_hd__dfxtp_4 contains 0 device instances.
+Circuit contains 0 nets.
+
+Circuit sky130_fd_sc_hd__dfxtp_4 contains no devices.
+Contents of circuit 1: Circuit: 'sky130_fd_sc_hd__diode_2'
+Circuit sky130_fd_sc_hd__diode_2 contains 0 device instances.
+Circuit contains 0 nets, and 5 disconnected pins.
+Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__diode_2'
+Circuit sky130_fd_sc_hd__diode_2 contains 0 device instances.
+Circuit contains 0 nets.
+
+Circuit sky130_fd_sc_hd__diode_2 contains no devices.
+Contents of circuit 1: Circuit: 'sky130_fd_sc_hd__buf_2'
+Circuit sky130_fd_sc_hd__buf_2 contains 0 device instances.
+Circuit contains 0 nets, and 6 disconnected pins.
+Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__buf_2'
+Circuit sky130_fd_sc_hd__buf_2 contains 0 device instances.
+Circuit contains 0 nets.
+
+Circuit sky130_fd_sc_hd__buf_2 contains no devices.
+Contents of circuit 1: Circuit: 'sky130_fd_sc_hd__or3_4'
+Circuit sky130_fd_sc_hd__or3_4 contains 0 device instances.
+Circuit contains 0 nets, and 8 disconnected pins.
+Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__or3_4'
+Circuit sky130_fd_sc_hd__or3_4 contains 0 device instances.
+Circuit contains 0 nets.
+
+Circuit sky130_fd_sc_hd__or3_4 contains no devices.
+Contents of circuit 1: Circuit: 'sky130_fd_sc_hd__tapvpwrvgnd_1'
+Circuit sky130_fd_sc_hd__tapvpwrvgnd_1 contains 0 device instances.
+Circuit contains 0 nets, and 2 disconnected pins.
+Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__tapvpwrvgnd_1'
+Circuit sky130_fd_sc_hd__tapvpwrvgnd_1 contains 0 device instances.
+Circuit contains 0 nets.
+
+Circuit sky130_fd_sc_hd__tapvpwrvgnd_1 contains no devices.
+Contents of circuit 1: Circuit: 'sky130_fd_sc_hd__and2_4'
+Circuit sky130_fd_sc_hd__and2_4 contains 0 device instances.
+Circuit contains 0 nets, and 7 disconnected pins.
+Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__and2_4'
+Circuit sky130_fd_sc_hd__and2_4 contains 0 device instances.
+Circuit contains 0 nets.
+
+Circuit sky130_fd_sc_hd__and2_4 contains no devices.
+Contents of circuit 1: Circuit: 'sky130_fd_sc_hd__and3_4'
+Circuit sky130_fd_sc_hd__and3_4 contains 0 device instances.
+Circuit contains 0 nets, and 8 disconnected pins.
+Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__and3_4'
+Circuit sky130_fd_sc_hd__and3_4 contains 0 device instances.
+Circuit contains 0 nets.
+
+Circuit sky130_fd_sc_hd__and3_4 contains no devices.
+Contents of circuit 1: Circuit: 'sky130_fd_sc_hd__inv_2'
+Circuit sky130_fd_sc_hd__inv_2 contains 0 device instances.
+Circuit contains 0 nets, and 6 disconnected pins.
+Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__inv_2'
+Circuit sky130_fd_sc_hd__inv_2 contains 0 device instances.
+Circuit contains 0 nets.
+
+Circuit sky130_fd_sc_hd__inv_2 contains no devices.
+Contents of circuit 1: Circuit: 'sky130_fd_sc_hd__a2bb2o_4'
+Circuit sky130_fd_sc_hd__a2bb2o_4 contains 0 device instances.
+Circuit contains 0 nets, and 9 disconnected pins.
+Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__a2bb2o_4'
+Circuit sky130_fd_sc_hd__a2bb2o_4 contains 0 device instances.
+Circuit contains 0 nets.
+
+Circuit sky130_fd_sc_hd__a2bb2o_4 contains no devices.
+Contents of circuit 1: Circuit: 'sky130_fd_sc_hd__a32o_4'
+Circuit sky130_fd_sc_hd__a32o_4 contains 0 device instances.
+Circuit contains 0 nets, and 10 disconnected pins.
+Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__a32o_4'
+Circuit sky130_fd_sc_hd__a32o_4 contains 0 device instances.
+Circuit contains 0 nets.
+
+Circuit sky130_fd_sc_hd__a32o_4 contains no devices.
+Contents of circuit 1: Circuit: 'sky130_fd_sc_hd__dfrtp_4'
+Circuit sky130_fd_sc_hd__dfrtp_4 contains 0 device instances.
+Circuit contains 0 nets, and 8 disconnected pins.
+Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__dfrtp_4'
+Circuit sky130_fd_sc_hd__dfrtp_4 contains 0 device instances.
+Circuit contains 0 nets.
+
+Circuit sky130_fd_sc_hd__dfrtp_4 contains no devices.
+Contents of circuit 1: Circuit: 'sky130_fd_sc_hd__clkbuf_1'
+Circuit sky130_fd_sc_hd__clkbuf_1 contains 0 device instances.
+Circuit contains 0 nets, and 6 disconnected pins.
+Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__clkbuf_1'
+Circuit sky130_fd_sc_hd__clkbuf_1 contains 0 device instances.
+Circuit contains 0 nets.
+
+Circuit sky130_fd_sc_hd__clkbuf_1 contains no devices.
+Contents of circuit 1: Circuit: 'sky130_fd_sc_hd__or4_4'
+Circuit sky130_fd_sc_hd__or4_4 contains 0 device instances.
+Circuit contains 0 nets, and 9 disconnected pins.
+Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__or4_4'
+Circuit sky130_fd_sc_hd__or4_4 contains 0 device instances.
+Circuit contains 0 nets.
+
+Circuit sky130_fd_sc_hd__or4_4 contains no devices.
+Contents of circuit 1: Circuit: 'sky130_fd_sc_hd__o22a_4'
+Circuit sky130_fd_sc_hd__o22a_4 contains 0 device instances.
+Circuit contains 0 nets, and 9 disconnected pins.
+Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__o22a_4'
+Circuit sky130_fd_sc_hd__o22a_4 contains 0 device instances.
+Circuit contains 0 nets.
+
+Circuit sky130_fd_sc_hd__o22a_4 contains no devices.
+Contents of circuit 1: Circuit: 'sky130_fd_sc_hd__nor2_4'
+Circuit sky130_fd_sc_hd__nor2_4 contains 0 device instances.
+Circuit contains 0 nets, and 7 disconnected pins.
+Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__nor2_4'
+Circuit sky130_fd_sc_hd__nor2_4 contains 0 device instances.
+Circuit contains 0 nets.
+
+Circuit sky130_fd_sc_hd__nor2_4 contains no devices.
+Contents of circuit 1: Circuit: 'sky130_fd_sc_hd__o21a_4'
+Circuit sky130_fd_sc_hd__o21a_4 contains 0 device instances.
+Circuit contains 0 nets, and 8 disconnected pins.
+Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__o21a_4'
+Circuit sky130_fd_sc_hd__o21a_4 contains 0 device instances.
+Circuit contains 0 nets.
+
+Circuit sky130_fd_sc_hd__o21a_4 contains no devices.
+Contents of circuit 1: Circuit: 'sky130_fd_sc_hd__a211o_4'
+Circuit sky130_fd_sc_hd__a211o_4 contains 0 device instances.
+Circuit contains 0 nets, and 9 disconnected pins.
+Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__a211o_4'
+Circuit sky130_fd_sc_hd__a211o_4 contains 0 device instances.
+Circuit contains 0 nets.
+
+Circuit sky130_fd_sc_hd__a211o_4 contains no devices.
+Contents of circuit 1: Circuit: 'sky130_fd_sc_hd__a22oi_4'
+Circuit sky130_fd_sc_hd__a22oi_4 contains 0 device instances.
+Circuit contains 0 nets, and 9 disconnected pins.
+Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__a22oi_4'
+Circuit sky130_fd_sc_hd__a22oi_4 contains 0 device instances.
+Circuit contains 0 nets.
+
+Circuit sky130_fd_sc_hd__a22oi_4 contains no devices.
+Contents of circuit 1: Circuit: 'sky130_fd_sc_hd__nand2_4'
+Circuit sky130_fd_sc_hd__nand2_4 contains 0 device instances.
+Circuit contains 0 nets, and 7 disconnected pins.
+Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__nand2_4'
+Circuit sky130_fd_sc_hd__nand2_4 contains 0 device instances.
+Circuit contains 0 nets.
+
+Circuit sky130_fd_sc_hd__nand2_4 contains no devices.
+Contents of circuit 1: Circuit: 'sky130_fd_sc_hd__o21ai_4'
+Circuit sky130_fd_sc_hd__o21ai_4 contains 0 device instances.
+Circuit contains 0 nets, and 8 disconnected pins.
+Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__o21ai_4'
+Circuit sky130_fd_sc_hd__o21ai_4 contains 0 device instances.
+Circuit contains 0 nets.
+
+Circuit sky130_fd_sc_hd__o21ai_4 contains no devices.
+Contents of circuit 1: Circuit: 'sky130_fd_sc_hd__o32a_4'
+Circuit sky130_fd_sc_hd__o32a_4 contains 0 device instances.
+Circuit contains 0 nets, and 10 disconnected pins.
+Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__o32a_4'
+Circuit sky130_fd_sc_hd__o32a_4 contains 0 device instances.
+Circuit contains 0 nets.
+
+Circuit sky130_fd_sc_hd__o32a_4 contains no devices.
+Contents of circuit 1: Circuit: 'sky130_fd_sc_hd__a21bo_4'
+Circuit sky130_fd_sc_hd__a21bo_4 contains 0 device instances.
+Circuit contains 0 nets, and 8 disconnected pins.
+Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__a21bo_4'
+Circuit sky130_fd_sc_hd__a21bo_4 contains 0 device instances.
+Circuit contains 0 nets.
+
+Circuit sky130_fd_sc_hd__a21bo_4 contains no devices.
+Contents of circuit 1: Circuit: 'sky130_fd_sc_hd__and4_4'
+Circuit sky130_fd_sc_hd__and4_4 contains 0 device instances.
+Circuit contains 0 nets, and 9 disconnected pins.
+Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__and4_4'
+Circuit sky130_fd_sc_hd__and4_4 contains 0 device instances.
+Circuit contains 0 nets.
+
+Circuit sky130_fd_sc_hd__and4_4 contains no devices.
+Contents of circuit 1: Circuit: 'sky130_fd_sc_hd__conb_1'
+Circuit sky130_fd_sc_hd__conb_1 contains 0 device instances.
+Circuit contains 0 nets, and 6 disconnected pins.
+Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__conb_1'
+Circuit sky130_fd_sc_hd__conb_1 contains 0 device instances.
+Circuit contains 0 nets.
+
+Circuit sky130_fd_sc_hd__conb_1 contains no devices.
+Contents of circuit 1: Circuit: 'sky130_fd_sc_hd__a21o_4'
+Circuit sky130_fd_sc_hd__a21o_4 contains 0 device instances.
+Circuit contains 0 nets, and 8 disconnected pins.
+Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__a21o_4'
+Circuit sky130_fd_sc_hd__a21o_4 contains 0 device instances.
+Circuit contains 0 nets.
+
+Circuit sky130_fd_sc_hd__a21o_4 contains no devices.
+Contents of circuit 1: Circuit: 'sky130_fd_sc_hd__a21oi_4'
+Circuit sky130_fd_sc_hd__a21oi_4 contains 0 device instances.
+Circuit contains 0 nets, and 8 disconnected pins.
+Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__a21oi_4'
+Circuit sky130_fd_sc_hd__a21oi_4 contains 0 device instances.
+Circuit contains 0 nets.
+
+Circuit sky130_fd_sc_hd__a21oi_4 contains no devices.
+Contents of circuit 1: Circuit: 'sky130_fd_sc_hd__buf_4'
+Circuit sky130_fd_sc_hd__buf_4 contains 0 device instances.
+Circuit contains 0 nets, and 6 disconnected pins.
+Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__buf_4'
+Circuit sky130_fd_sc_hd__buf_4 contains 0 device instances.
+Circuit contains 0 nets.
+
+Circuit sky130_fd_sc_hd__buf_4 contains no devices.
+Contents of circuit 1: Circuit: 'sky130_fd_sc_hd__buf_8'
+Circuit sky130_fd_sc_hd__buf_8 contains 0 device instances.
+Circuit contains 0 nets, and 6 disconnected pins.
+Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__buf_8'
+Circuit sky130_fd_sc_hd__buf_8 contains 0 device instances.
+Circuit contains 0 nets.
+
+Circuit sky130_fd_sc_hd__buf_8 contains no devices.
+Contents of circuit 1: Circuit: 'sky130_fd_sc_hd__o41a_4'
+Circuit sky130_fd_sc_hd__o41a_4 contains 0 device instances.
+Circuit contains 0 nets, and 10 disconnected pins.
+Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__o41a_4'
+Circuit sky130_fd_sc_hd__o41a_4 contains 0 device instances.
+Circuit contains 0 nets.
+
+Circuit sky130_fd_sc_hd__o41a_4 contains no devices.
+Contents of circuit 1: Circuit: 'sky130_fd_sc_hd__clkbuf_16'
+Circuit sky130_fd_sc_hd__clkbuf_16 contains 0 device instances.
+Circuit contains 0 nets, and 6 disconnected pins.
+Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__clkbuf_16'
+Circuit sky130_fd_sc_hd__clkbuf_16 contains 0 device instances.
+Circuit contains 0 nets.
+
+Circuit sky130_fd_sc_hd__clkbuf_16 contains no devices.
+Contents of circuit 1: Circuit: 'sky130_fd_sc_hd__inv_8'
+Circuit sky130_fd_sc_hd__inv_8 contains 0 device instances.
+Circuit contains 0 nets, and 6 disconnected pins.
+Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__inv_8'
+Circuit sky130_fd_sc_hd__inv_8 contains 0 device instances.
+Circuit contains 0 nets.
+
+Circuit sky130_fd_sc_hd__inv_8 contains no devices.
+Contents of circuit 1: Circuit: 'sky130_fd_sc_hd__a2111o_4'
+Circuit sky130_fd_sc_hd__a2111o_4 contains 0 device instances.
+Circuit contains 0 nets, and 10 disconnected pins.
+Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__a2111o_4'
+Circuit sky130_fd_sc_hd__a2111o_4 contains 0 device instances.
+Circuit contains 0 nets.
+
+Circuit sky130_fd_sc_hd__a2111o_4 contains no devices.
+Contents of circuit 1: Circuit: 'sky130_fd_sc_hd__dfstp_4'
+Circuit sky130_fd_sc_hd__dfstp_4 contains 0 device instances.
+Circuit contains 0 nets, and 8 disconnected pins.
+Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__dfstp_4'
+Circuit sky130_fd_sc_hd__dfstp_4 contains 0 device instances.
+Circuit contains 0 nets.
+
+Circuit sky130_fd_sc_hd__dfstp_4 contains no devices.
+Contents of circuit 1: Circuit: 'sky130_fd_sc_hd__inv_4'
+Circuit sky130_fd_sc_hd__inv_4 contains 0 device instances.
+Circuit contains 0 nets, and 6 disconnected pins.
+Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__inv_4'
+Circuit sky130_fd_sc_hd__inv_4 contains 0 device instances.
+Circuit contains 0 nets.
+
+Circuit sky130_fd_sc_hd__inv_4 contains no devices.
+Contents of circuit 1: Circuit: 'sky130_fd_sc_hd__a41o_4'
+Circuit sky130_fd_sc_hd__a41o_4 contains 0 device instances.
+Circuit contains 0 nets, and 10 disconnected pins.
+Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__a41o_4'
+Circuit sky130_fd_sc_hd__a41o_4 contains 0 device instances.
+Circuit contains 0 nets.
+
+Circuit sky130_fd_sc_hd__a41o_4 contains no devices.
+Contents of circuit 1: Circuit: 'user_proj_example'
+Circuit user_proj_example contains 418458 device instances.
+ Class: sky130_fd_sc_hd__a41o_4 instances: 2
+ Class: sky130_fd_sc_hd__a21o_4 instances: 203
+ Class: sky130_fd_sc_hd__clkbuf_16 instances: 28
+ Class: sky130_fd_sc_hd__dfxtp_4 instances: 26132
+ Class: sky130_fd_sc_hd__or4_4 instances: 1116
+ Class: sky130_fd_sc_hd__buf_2 instances: 35952
+ Class: sky130_fd_sc_hd__buf_4 instances: 167
+ Class: sky130_fd_sc_hd__buf_8 instances: 102
+ Class: sky130_fd_sc_hd__a2bb2o_4 instances: 24546
+ Class: sky130_fd_sc_hd__dfstp_4 instances: 18
+ Class: sky130_fd_sc_hd__dfrtp_4 instances: 626
+ Class: sky130_fd_sc_hd__and4_4 instances: 265
+ Class: sky130_fd_sc_hd__inv_2 instances: 25672
+ Class: sky130_fd_sc_hd__inv_4 instances: 2
+ Class: sky130_fd_sc_hd__inv_8 instances: 5
+ Class: sky130_fd_sc_hd__clkbuf_1 instances: 4278
+ Class: sky130_fd_sc_hd__or3_4 instances: 8866
+ Class: sky130_fd_sc_hd__conb_1 instances: 77
+ Class: sky130_fd_sc_hd__a21bo_4 instances: 68
+ Class: sky130_fd_sc_hd__and3_4 instances: 18762
+ Class: sky130_fd_sc_hd__a2111o_4 instances: 35
+ Class: sky130_fd_sc_hd__or2_4 instances: 30981
+ Class: sky130_fd_sc_hd__nand2_4 instances: 558
+ Class: sky130_fd_sc_hd__and2_4 instances: 2003
+ Class: sky130_fd_sc_hd__o32a_4 instances: 231
+ Class: sky130_fd_sc_hd__o22a_4 instances: 2992
+ Class: sky130_fd_sc_hd__diode_2 instances: 126422
+ Class: sky130_fd_sc_hd__a211o_4 instances: 1593
+ Class: sky130_fd_sc_hd__a32o_4 instances: 1198
+ Class: sky130_fd_sc_hd__o41a_4 instances: 6
+ Class: sky130_fd_sc_hd__o21a_4 instances: 1178
+ Class: sky130_fd_sc_hd__a22oi_4 instances: 163
+ Class: sky130_fd_sc_hd__tapvpwrvgnd_1 instances: 100264
+ Class: sky130_fd_sc_hd__o21ai_4 instances: 305
+ Class: sky130_fd_sc_hd__a21oi_4 instances: 173
+ Class: sky130_fd_sc_hd__nor2_4 instances: 3469
+Circuit contains 191960 nets, and 258 disconnected pins.
+Contents of circuit 2: Circuit: 'user_proj_example'
+Circuit user_proj_example contains 418458 device instances.
+ Class: sky130_fd_sc_hd__a41o_4 instances: 2
+ Class: sky130_fd_sc_hd__a21o_4 instances: 203
+ Class: sky130_fd_sc_hd__clkbuf_16 instances: 28
+ Class: sky130_fd_sc_hd__dfxtp_4 instances: 26132
+ Class: sky130_fd_sc_hd__or4_4 instances: 1116
+ Class: sky130_fd_sc_hd__buf_2 instances: 35952
+ Class: sky130_fd_sc_hd__buf_4 instances: 167
+ Class: sky130_fd_sc_hd__buf_8 instances: 102
+ Class: sky130_fd_sc_hd__a2bb2o_4 instances: 24546
+ Class: sky130_fd_sc_hd__dfstp_4 instances: 18
+ Class: sky130_fd_sc_hd__dfrtp_4 instances: 626
+ Class: sky130_fd_sc_hd__and4_4 instances: 265
+ Class: sky130_fd_sc_hd__inv_2 instances: 25672
+ Class: sky130_fd_sc_hd__inv_4 instances: 2
+ Class: sky130_fd_sc_hd__inv_8 instances: 5
+ Class: sky130_fd_sc_hd__clkbuf_1 instances: 4278
+ Class: sky130_fd_sc_hd__or3_4 instances: 8866
+ Class: sky130_fd_sc_hd__conb_1 instances: 77
+ Class: sky130_fd_sc_hd__a21bo_4 instances: 68
+ Class: sky130_fd_sc_hd__and3_4 instances: 18762
+ Class: sky130_fd_sc_hd__a2111o_4 instances: 35
+ Class: sky130_fd_sc_hd__or2_4 instances: 30981
+ Class: sky130_fd_sc_hd__nand2_4 instances: 558
+ Class: sky130_fd_sc_hd__and2_4 instances: 2003
+ Class: sky130_fd_sc_hd__o32a_4 instances: 231
+ Class: sky130_fd_sc_hd__o22a_4 instances: 2992
+ Class: sky130_fd_sc_hd__diode_2 instances: 126422
+ Class: sky130_fd_sc_hd__a211o_4 instances: 1593
+ Class: sky130_fd_sc_hd__a32o_4 instances: 1198
+ Class: sky130_fd_sc_hd__o41a_4 instances: 6
+ Class: sky130_fd_sc_hd__o21a_4 instances: 1178
+ Class: sky130_fd_sc_hd__a22oi_4 instances: 163
+ Class: sky130_fd_sc_hd__tapvpwrvgnd_1 instances: 100264
+ Class: sky130_fd_sc_hd__o21ai_4 instances: 305
+ Class: sky130_fd_sc_hd__a21oi_4 instances: 173
+ Class: sky130_fd_sc_hd__nor2_4 instances: 3469
+Circuit contains 191884 nets, and 328 disconnected pins.
+
+Circuit 1 contains 418458 devices, Circuit 2 contains 418458 devices.
+Circuit 1 contains 191884 nets, Circuit 2 contains 191884 nets.
+
+Circuits match with 24127 symmetries.
+Resolving automorphisms by property value.
+Resolving automorphisms by pin name.
+Netlists match with 24127 symmetries.
+Circuits match correctly.
+Result: The top level cell failed pin matching.
+
+Logging to file "/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.log" disabled
+LVS Done.
diff --git a/openlane/user_proj_example/results/logs/lvs/write_powered_verilog.log b/openlane/user_proj_example/results/logs/lvs/write_powered_verilog.log
new file mode 100644
index 0000000..0766efe
--- /dev/null
+++ b/openlane/user_proj_example/results/logs/lvs/write_powered_verilog.log
@@ -0,0 +1,30 @@
+Notice 0: Reading LEF file: /project/openlane/user_proj_example/runs/16-12_10-43/tmp/merged.lef
+Notice 0: Created 13 technology layers
+Notice 0: Created 25 technology vias
+Notice 0: Created 438 library cells
+Notice 0: Finished LEF file: /project/openlane/user_proj_example/runs/16-12_10-43/tmp/merged.lef
+Notice 0:
+Reading DEF file: /project/openlane/user_proj_example/runs/16-12_10-43/results/routing/user_proj_example.def
+Notice 0: Design: user_proj_example
+Notice 0: error: unknown library cell referenced (obs_core_obs_0) for instance (obs_core_obs_0)
+Notice 0: Created 100000 Insts
+Notice 0: Created 200000 Insts
+Notice 0: Created 300000 Insts
+Notice 0: Created 400000 Insts
+Notice 0: Created 500000 Insts
+Notice 0: Created 600000 Insts
+Notice 0: Created 700000 Insts
+Notice 0: Created 800000 Insts
+Notice 0: Created 900000 Insts
+Notice 0: Created 100000 Nets
+Notice 0: Created 606 pins.
+Notice 0: Created 927490 components and 4240852 component-terminals.
+Notice 0: Created 2 special nets and 0 connections.
+Notice 0: Created 192139 nets and 731343 connections.
+Notice 0: Finished DEF file: /project/openlane/user_proj_example/runs/16-12_10-43/results/routing/user_proj_example.def
+Top-level design name: user_proj_example
+Found port VPWR of type SIGNAL
+Found port VGND of type SIGNAL
+Power net: VPWR
+Ground net: VGND
+Modified power connections of 927490 cells (Remaining: 0 ).
diff --git a/openlane/user_proj_example/results/logs/magic/magic.drc b/openlane/user_proj_example/results/logs/magic/magic.drc
new file mode 100644
index 0000000..b25b903
--- /dev/null
+++ b/openlane/user_proj_example/results/logs/magic/magic.drc
@@ -0,0 +1,5 @@
+user_proj_example
+----------------------------------------
+[INFO]: COUNT: 0
+[INFO]: Should be divided by 3 or 4
+
diff --git a/openlane/user_proj_example/results/logs/magic/magic.drc.log b/openlane/user_proj_example/results/logs/magic/magic.drc.log
new file mode 100644
index 0000000..2ff1b6a
--- /dev/null
+++ b/openlane/user_proj_example/results/logs/magic/magic.drc.log
@@ -0,0 +1,9383 @@
+
+Magic 8.3 revision 92 - Compiled on Sat Dec 5 17:44:54 UTC 2020.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+Processing system .magicrc file
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130: scaleFactor=2, multiplier=2
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/openLANE_flow/scripts/magic/drc.tcl" from command line.
+Warning: Calma reading is not undoable! I hope that's OK.
+Library written using GDS-II Release 3.0
+Library name: user_proj_example
+Reading "sky130_fd_sc_hd__decap_12".
+Error while reading cell "sky130_fd_sc_hd__decap_12" (byte position 150): Unknown layer/datatype in boundary, layer=236 type=0
+Reading "sky130_fd_sc_hd__decap_3".
+Error while reading cell "sky130_fd_sc_hd__decap_3" (byte position 4284): Unknown layer/datatype in boundary, layer=236 type=0
+Reading "sky130_fd_sc_hd__decap_4".
+Error while reading cell "sky130_fd_sc_hd__decap_4" (byte position 6946): Unknown layer/datatype in boundary, layer=236 type=0
+Reading "sky130_fd_sc_hd__tapvpwrvgnd_1".
+Reading "sky130_fd_sc_hd__fill_2".
+Reading "sky130_fd_sc_hd__decap_8".
+Error while reading cell "sky130_fd_sc_hd__decap_8" (byte position 12830): Unknown layer/datatype in boundary, layer=236 type=0
+Reading "sky130_fd_sc_hd__decap_6".
+Error while reading cell "sky130_fd_sc_hd__decap_6" (byte position 16356): Unknown layer/datatype in boundary, layer=236 type=0
+Reading "sky130_fd_sc_hd__diode_2".
+Error while reading cell "sky130_fd_sc_hd__diode_2" (byte position 19498): Unknown layer/datatype in boundary, layer=236 type=0
+Reading "sky130_fd_sc_hd__inv_2".
+Error while reading cell "sky130_fd_sc_hd__inv_2" (byte position 22982): Unknown layer/datatype in boundary, layer=236 type=0
+Reading "sky130_fd_sc_hd__fill_1".
+Reading "sky130_fd_sc_hd__a2bb2o_4".
+Error while reading cell "sky130_fd_sc_hd__a2bb2o_4" (byte position 28072): Unknown layer/datatype in boundary, layer=236 type=0
+Reading "sky130_fd_sc_hd__buf_2".
+Error while reading cell "sky130_fd_sc_hd__buf_2" (byte position 39530): Unknown layer/datatype in boundary, layer=236 type=0
+Reading "sky130_fd_sc_hd__conb_1".
+Error while reading cell "sky130_fd_sc_hd__conb_1" (byte position 44022): Unknown layer/datatype in boundary, layer=236 type=0
+Reading "sky130_fd_sc_hd__or4_4".
+Error while reading cell "sky130_fd_sc_hd__or4_4" (byte position 47380): Unknown layer/datatype in boundary, layer=236 type=0
+Reading "sky130_fd_sc_hd__nor2_4".
+Error while reading cell "sky130_fd_sc_hd__nor2_4" (byte position 54682): Unknown layer/datatype in boundary, layer=236 type=0
+Reading "sky130_fd_sc_hd__or2_4".
+Error while reading cell "sky130_fd_sc_hd__or2_4" (byte position 61782): Unknown layer/datatype in boundary, layer=236 type=0
+Reading "sky130_fd_sc_hd__dfxtp_4".
+Error while reading cell "sky130_fd_sc_hd__dfxtp_4" (byte position 67540): Unknown layer/datatype in boundary, layer=236 type=0
+Reading "sky130_fd_sc_hd__dfstp_4".
+Error while reading cell "sky130_fd_sc_hd__dfstp_4" (byte position 81696): Unknown layer/datatype in boundary, layer=236 type=0
+Reading "sky130_fd_sc_hd__and3_4".
+Error while reading cell "sky130_fd_sc_hd__and3_4" (byte position 99426): Unknown layer/datatype in boundary, layer=236 type=0
+Reading "sky130_fd_sc_hd__or3_4".
+Error while reading cell "sky130_fd_sc_hd__or3_4" (byte position 106316): Unknown layer/datatype in boundary, layer=236 type=0
+Reading "sky130_fd_sc_hd__a211o_4".
+Error while reading cell "sky130_fd_sc_hd__a211o_4" (byte position 113430): Unknown layer/datatype in boundary, layer=236 type=0
+Reading "sky130_fd_sc_hd__a21o_4".
+Error while reading cell "sky130_fd_sc_hd__a21o_4" (byte position 122546): Unknown layer/datatype in boundary, layer=236 type=0
+Reading "sky130_fd_sc_hd__o21a_4".
+Error while reading cell "sky130_fd_sc_hd__o21a_4" (byte position 130766): Unknown layer/datatype in boundary, layer=236 type=0
+Reading "sky130_fd_sc_hd__and2_4".
+Error while reading cell "sky130_fd_sc_hd__and2_4" (byte position 138746): Unknown layer/datatype in boundary, layer=236 type=0
+Reading "sky130_fd_sc_hd__o22a_4".
+Error while reading cell "sky130_fd_sc_hd__o22a_4" (byte position 144488): Unknown layer/datatype in boundary, layer=236 type=0
+Reading "sky130_fd_sc_hd__o21ai_4".
+Error while reading cell "sky130_fd_sc_hd__o21ai_4" (byte position 154170): Unknown layer/datatype in boundary, layer=236 type=0
+Reading "sky130_fd_sc_hd__and4_4".
+Error while reading cell "sky130_fd_sc_hd__and4_4" (byte position 162280): Unknown layer/datatype in boundary, layer=236 type=0
+Reading "sky130_fd_sc_hd__a32o_4".
+Error while reading cell "sky130_fd_sc_hd__a32o_4" (byte position 169726): Unknown layer/datatype in boundary, layer=236 type=0
+Reading "sky130_fd_sc_hd__a21bo_4".
+Error while reading cell "sky130_fd_sc_hd__a21bo_4" (byte position 181918): Unknown layer/datatype in boundary, layer=236 type=0
+Reading "sky130_fd_sc_hd__nand2_4".
+Error while reading cell "sky130_fd_sc_hd__nand2_4" (byte position 190222): Unknown layer/datatype in boundary, layer=236 type=0
+Reading "sky130_fd_sc_hd__clkbuf_1".
+Error while reading cell "sky130_fd_sc_hd__clkbuf_1" (byte position 197862): Unknown layer/datatype in boundary, layer=236 type=0
+Reading "sky130_fd_sc_hd__a21oi_4".
+Error while reading cell "sky130_fd_sc_hd__a21oi_4" (byte position 201668): Unknown layer/datatype in boundary, layer=236 type=0
+Reading "sky130_fd_sc_hd__a22oi_4".
+Error while reading cell "sky130_fd_sc_hd__a22oi_4" (byte position 210258): Unknown layer/datatype in boundary, layer=236 type=0
+Reading "sky130_fd_sc_hd__o32a_4".
+Error while reading cell "sky130_fd_sc_hd__o32a_4" (byte position 222306): Unknown layer/datatype in boundary, layer=236 type=0
+Reading "sky130_fd_sc_hd__a2111o_4".
+Error while reading cell "sky130_fd_sc_hd__a2111o_4" (byte position 234612): Unknown layer/datatype in boundary, layer=236 type=0
+Reading "sky130_fd_sc_hd__buf_4".
+Error while reading cell "sky130_fd_sc_hd__buf_4" (byte position 247020): Unknown layer/datatype in boundary, layer=236 type=0
+Reading "sky130_fd_sc_hd__dfrtp_4".
+Error while reading cell "sky130_fd_sc_hd__dfrtp_4" (byte position 252424): Unknown layer/datatype in boundary, layer=236 type=0
+Reading "sky130_fd_sc_hd__o41a_4".
+Error while reading cell "sky130_fd_sc_hd__o41a_4" (byte position 270272): Unknown layer/datatype in boundary, layer=236 type=0
+Reading "sky130_fd_sc_hd__a41o_4".
+Error while reading cell "sky130_fd_sc_hd__a41o_4" (byte position 283432): Unknown layer/datatype in boundary, layer=236 type=0
+Reading "sky130_fd_sc_hd__buf_8".
+Error while reading cell "sky130_fd_sc_hd__buf_8" (byte position 295952): Unknown layer/datatype in boundary, layer=236 type=0
+Reading "sky130_fd_sc_hd__clkbuf_16".
+Error while reading cell "sky130_fd_sc_hd__clkbuf_16" (byte position 304842): Unknown layer/datatype in boundary, layer=236 type=0
+Reading "sky130_fd_sc_hd__inv_4".
+Error while reading cell "sky130_fd_sc_hd__inv_4" (byte position 317568): Unknown layer/datatype in boundary, layer=236 type=0
+Reading "sky130_fd_sc_hd__inv_8".
+Error while reading cell "sky130_fd_sc_hd__inv_8" (byte position 322612): Unknown layer/datatype in boundary, layer=236 type=0
+Reading "user_proj_example".
+ 100 uses
+ 200 uses
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+[INFO]: Loading user_proj_example
+
+DRC style is now "drc(full)"
+Loading DRC CIF style.
+No errors found.
+[INFO]: COUNT: 0
+[INFO]: Should be divided by 3 or 4
+[INFO]: DRC Checking DONE (/project/openlane/user_proj_example/runs/16-12_10-43/logs/magic/magic.drc)
+[INFO]: Saving mag view with DRC errors(/project/openlane/user_proj_example/runs/16-12_10-43/results/magic/user_proj_example.drc.mag)
+[INFO]: Saved
diff --git a/openlane/user_proj_example/results/logs/magic/magic.log b/openlane/user_proj_example/results/logs/magic/magic.log
new file mode 100644
index 0000000..9469803
--- /dev/null
+++ b/openlane/user_proj_example/results/logs/magic/magic.log
@@ -0,0 +1,103 @@
+
+Magic 8.3 revision 92 - Compiled on Sat Dec 5 17:44:54 UTC 2020.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+Processing system .magicrc file
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130: scaleFactor=2, multiplier=2
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/openLANE_flow/scripts/magic/mag_lef_gds.tcl" from command line.
+Reading LEF data from file /mnt/data/workspace/pdk/sky130A/libs.ref/sky130_fd_sc_hd/techlef/sky130_fd_sc_hd.tlef.
+This action cannot be undone.
+LEF read, Line 77 (Message): Unknown keyword "ANTENNAMODEL" in LEF file; ignoring.
+LEF read, Line 78 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring.
+LEF read, Line 111 (Message): Unknown keyword "ANTENNAMODEL" in LEF file; ignoring.
+LEF read, Line 112 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring.
+LEF read, Line 118 (Message): Unknown keyword "MAXIMUMDENSITY" in LEF file; ignoring.
+LEF read, Line 119 (Message): Unknown keyword "DENSITYCHECKWINDOW" in LEF file; ignoring.
+LEF read, Line 120 (Message): Unknown keyword "DENSITYCHECKSTEP" in LEF file; ignoring.
+LEF read, Line 159 (Message): Unknown keyword "ANTENNAMODEL" in LEF file; ignoring.
+LEF read, Line 160 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring.
+LEF read, Line 162 (Message): Unknown keyword "MAXIMUMDENSITY" in LEF file; ignoring.
+LEF read, Line 163 (Message): Unknown keyword "DENSITYCHECKWINDOW" in LEF file; ignoring.
+LEF read, Line 164 (Message): Unknown keyword "DENSITYCHECKSTEP" in LEF file; ignoring.
+LEF read, Line 200 (Message): Unknown keyword "ANTENNAMODEL" in LEF file; ignoring.
+LEF read, Line 201 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring.
+LEF read, Line 203 (Message): Unknown keyword "MAXIMUMDENSITY" in LEF file; ignoring.
+LEF read, Line 204 (Message): Unknown keyword "DENSITYCHECKWINDOW" in LEF file; ignoring.
+LEF read, Line 205 (Message): Unknown keyword "DENSITYCHECKSTEP" in LEF file; ignoring.
+LEF read, Line 241 (Message): Unknown keyword "ANTENNAMODEL" in LEF file; ignoring.
+LEF read, Line 242 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring.
+LEF read, Line 244 (Message): Unknown keyword "MAXIMUMDENSITY" in LEF file; ignoring.
+LEF read, Line 245 (Message): Unknown keyword "DENSITYCHECKWINDOW" in LEF file; ignoring.
+LEF read, Line 246 (Message): Unknown keyword "DENSITYCHECKSTEP" in LEF file; ignoring.
+LEF read, Line 282 (Message): Unknown keyword "ANTENNAMODEL" in LEF file; ignoring.
+LEF read, Line 283 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring.
+LEF read: Processed 789 lines.
+Reading DEF data from file /project/openlane/user_proj_example/runs/16-12_10-43/results/routing/user_proj_example.def.
+This action cannot be undone.
+ Processed 5 vias total.
+Cell obs_core_obs_0 couldn't be read
+DEF read, Line 2327 (Error): Cell obs_core_obs_0 is not defined. Maybe you have not read the corresponding LEF file?
+ Processed 927491 subcell instances total.
+ Processed 606 pins total.
+ Processed 2 special nets total.
+ Processed 192139 nets total.
+DEF read: Processed 5039852 lines.
+DEF Read: encountered 1 error total.
+[INFO]: Zeroizing Origin
+[INFO]: Current Box Values: 1 0 498978 620000
+[INFO]: Writing abstract LEF
+Generating LEF output /project/openlane/user_proj_example/runs/16-12_10-43/results/magic/user_proj_example.lef for cell user_proj_example:
+Diagnostic: Write LEF header for cell user_proj_example
+Diagnostic: Writing LEF output for cell user_proj_example
+Diagnostic: Scale value is 0.005000
+[INFO]: LEF Write Complete
+ Writing cell user_proj_example
+ Writing cell sky130_fd_sc_hd__decap_12
+ Writing cell sky130_fd_sc_hd__decap_3
+ Writing cell sky130_fd_sc_hd__decap_4
+ Writing cell sky130_fd_sc_hd__tapvpwrvgnd_1
+ Writing cell sky130_fd_sc_hd__fill_2
+ Writing cell sky130_fd_sc_hd__decap_8
+ Writing cell sky130_fd_sc_hd__decap_6
+ Writing cell sky130_fd_sc_hd__diode_2
+ Writing cell sky130_fd_sc_hd__inv_2
+ Writing cell sky130_fd_sc_hd__fill_1
+ Writing cell sky130_fd_sc_hd__a2bb2o_4
+ Writing cell sky130_fd_sc_hd__buf_2
+ Writing cell sky130_fd_sc_hd__conb_1
+ Writing cell sky130_fd_sc_hd__or4_4
+ Writing cell sky130_fd_sc_hd__nor2_4
+ Writing cell sky130_fd_sc_hd__or2_4
+ Writing cell sky130_fd_sc_hd__dfxtp_4
+ Writing cell sky130_fd_sc_hd__dfstp_4
+ Writing cell sky130_fd_sc_hd__and3_4
+ Writing cell sky130_fd_sc_hd__or3_4
+ Writing cell sky130_fd_sc_hd__a211o_4
+ Writing cell sky130_fd_sc_hd__a21o_4
+ Writing cell sky130_fd_sc_hd__o21a_4
+ Writing cell sky130_fd_sc_hd__and2_4
+ Writing cell sky130_fd_sc_hd__o22a_4
+ Writing cell sky130_fd_sc_hd__o21ai_4
+ Writing cell sky130_fd_sc_hd__and4_4
+ Writing cell sky130_fd_sc_hd__a32o_4
+ Writing cell sky130_fd_sc_hd__a21bo_4
+ Writing cell sky130_fd_sc_hd__nand2_4
+ Writing cell sky130_fd_sc_hd__clkbuf_1
+ Writing cell sky130_fd_sc_hd__a21oi_4
+ Writing cell sky130_fd_sc_hd__a22oi_4
+ Writing cell sky130_fd_sc_hd__o32a_4
+ Writing cell sky130_fd_sc_hd__a2111o_4
+ Writing cell sky130_fd_sc_hd__buf_4
+ Writing cell sky130_fd_sc_hd__dfrtp_4
+ Writing cell sky130_fd_sc_hd__o41a_4
+ Writing cell sky130_fd_sc_hd__a41o_4
+ Writing cell sky130_fd_sc_hd__buf_8
+ Writing cell sky130_fd_sc_hd__clkbuf_16
+ Writing cell sky130_fd_sc_hd__inv_4
+ Writing cell sky130_fd_sc_hd__inv_8
+[INFO]: GDS Write Complete
diff --git a/openlane/user_proj_example/results/logs/magic/magic.maglef.log b/openlane/user_proj_example/results/logs/magic/magic.maglef.log
new file mode 100644
index 0000000..dcf9061
--- /dev/null
+++ b/openlane/user_proj_example/results/logs/magic/magic.maglef.log
@@ -0,0 +1,16 @@
+
+Magic 8.3 revision 92 - Compiled on Sat Dec 5 17:44:54 UTC 2020.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+Processing system .magicrc file
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130: scaleFactor=2, multiplier=2
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/openLANE_flow/scripts/magic/maglef.tcl" from command line.
+Reading LEF data from file /project/openlane/user_proj_example/runs/16-12_10-43/results/magic/user_proj_example.lef.
+This action cannot be undone.
+LEF read: Processed 4871 lines.
+[INFO]: DONE GENERATING MAGLEF VIEW
diff --git a/openlane/user_proj_example/results/logs/magic/magic_antenna.log b/openlane/user_proj_example/results/logs/magic/magic_antenna.log
new file mode 100644
index 0000000..8ca9124
--- /dev/null
+++ b/openlane/user_proj_example/results/logs/magic/magic_antenna.log
@@ -0,0 +1,5331 @@
+
+Magic 8.3 revision 92 - Compiled on Sat Dec 5 17:44:54 UTC 2020.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+Processing system .magicrc file
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130: scaleFactor=2, multiplier=2
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/project/openlane/user_proj_example/runs/16-12_10-43/tmp/magic_antenna.tcl" from command line.
+Reading LEF data from file /mnt/data/workspace/pdk/sky130A/libs.ref/sky130_fd_sc_hd/techlef/sky130_fd_sc_hd.tlef.
+This action cannot be undone.
+LEF read, Line 77 (Message): Unknown keyword "ANTENNAMODEL" in LEF file; ignoring.
+LEF read, Line 78 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring.
+LEF read, Line 111 (Message): Unknown keyword "ANTENNAMODEL" in LEF file; ignoring.
+LEF read, Line 112 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring.
+LEF read, Line 118 (Message): Unknown keyword "MAXIMUMDENSITY" in LEF file; ignoring.
+LEF read, Line 119 (Message): Unknown keyword "DENSITYCHECKWINDOW" in LEF file; ignoring.
+LEF read, Line 120 (Message): Unknown keyword "DENSITYCHECKSTEP" in LEF file; ignoring.
+LEF read, Line 159 (Message): Unknown keyword "ANTENNAMODEL" in LEF file; ignoring.
+LEF read, Line 160 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring.
+LEF read, Line 162 (Message): Unknown keyword "MAXIMUMDENSITY" in LEF file; ignoring.
+LEF read, Line 163 (Message): Unknown keyword "DENSITYCHECKWINDOW" in LEF file; ignoring.
+LEF read, Line 164 (Message): Unknown keyword "DENSITYCHECKSTEP" in LEF file; ignoring.
+LEF read, Line 200 (Message): Unknown keyword "ANTENNAMODEL" in LEF file; ignoring.
+LEF read, Line 201 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring.
+LEF read, Line 203 (Message): Unknown keyword "MAXIMUMDENSITY" in LEF file; ignoring.
+LEF read, Line 204 (Message): Unknown keyword "DENSITYCHECKWINDOW" in LEF file; ignoring.
+LEF read, Line 205 (Message): Unknown keyword "DENSITYCHECKSTEP" in LEF file; ignoring.
+LEF read, Line 241 (Message): Unknown keyword "ANTENNAMODEL" in LEF file; ignoring.
+LEF read, Line 242 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring.
+LEF read, Line 244 (Message): Unknown keyword "MAXIMUMDENSITY" in LEF file; ignoring.
+LEF read, Line 245 (Message): Unknown keyword "DENSITYCHECKWINDOW" in LEF file; ignoring.
+LEF read, Line 246 (Message): Unknown keyword "DENSITYCHECKSTEP" in LEF file; ignoring.
+LEF read, Line 282 (Message): Unknown keyword "ANTENNAMODEL" in LEF file; ignoring.
+LEF read, Line 283 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring.
+LEF read: Processed 789 lines.
+Reading DEF data from file /project/openlane/user_proj_example/runs/16-12_10-43/results/routing/user_proj_example.def.
+This action cannot be undone.
+ Processed 5 vias total.
+Cell obs_core_obs_0 couldn't be read
+DEF read, Line 2327 (Error): Cell obs_core_obs_0 is not defined. Maybe you have not read the corresponding LEF file?
+File </mnt/data/workspace/pdk/sky130A//libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__buf_2.mag> is already locked by another process. Opening read-only.
+File </mnt/data/workspace/pdk/sky130A//libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__inv_2.mag> is already locked by another process. Opening read-only.
+File </mnt/data/workspace/pdk/sky130A//libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__and2_4.mag> is already locked by another process. Opening read-only.
+File </mnt/data/workspace/pdk/sky130A//libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__a2bb2o_4.mag> is already locked by another process. Opening read-only.
+File </mnt/data/workspace/pdk/sky130A//libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__o22a_4.mag> is already locked by another process. Opening read-only.
+File </mnt/data/workspace/pdk/sky130A//libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__or4_4.mag> is already locked by another process. Opening read-only.
+File </mnt/data/workspace/pdk/sky130A//libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__or2_4.mag> is already locked by another process. Opening read-only.
+File </mnt/data/workspace/pdk/sky130A//libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__a21o_4.mag> is already locked by another process. Opening read-only.
+File </mnt/data/workspace/pdk/sky130A//libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__o21a_4.mag> is already locked by another process. Opening read-only.
+File </mnt/data/workspace/pdk/sky130A//libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__and4_4.mag> is already locked by another process. Opening read-only.
+File </mnt/data/workspace/pdk/sky130A//libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__or3_4.mag> is already locked by another process. Opening read-only.
+File </mnt/data/workspace/pdk/sky130A//libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__a32o_4.mag> is already locked by another process. Opening read-only.
+File </mnt/data/workspace/pdk/sky130A//libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__a21oi_4.mag> is already locked by another process. Opening read-only.
+File </mnt/data/workspace/pdk/sky130A//libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__o21ai_4.mag> is already locked by another process. Opening read-only.
+File </mnt/data/workspace/pdk/sky130A//libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__nor2_4.mag> is already locked by another process. Opening read-only.
+File </mnt/data/workspace/pdk/sky130A//libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__and3_4.mag> is already locked by another process. Opening read-only.
+File </mnt/data/workspace/pdk/sky130A//libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__a22oi_4.mag> is already locked by another process. Opening read-only.
+File </mnt/data/workspace/pdk/sky130A//libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__nand2_4.mag> is already locked by another process. Opening read-only.
+File </mnt/data/workspace/pdk/sky130A//libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__a211o_4.mag> is already locked by another process. Opening read-only.
+File </mnt/data/workspace/pdk/sky130A//libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__buf_4.mag> is already locked by another process. Opening read-only.
+File </mnt/data/workspace/pdk/sky130A//libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__inv_4.mag> is already locked by another process. Opening read-only.
+File </mnt/data/workspace/pdk/sky130A//libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__a21bo_4.mag> is already locked by another process. Opening read-only.
+File </mnt/data/workspace/pdk/sky130A//libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__o32a_4.mag> is already locked by another process. Opening read-only.
+File </mnt/data/workspace/pdk/sky130A//libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__a41o_4.mag> is already locked by another process. Opening read-only.
+File </mnt/data/workspace/pdk/sky130A//libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__o41a_4.mag> is already locked by another process. Opening read-only.
+File </mnt/data/workspace/pdk/sky130A//libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__a2111o_4.mag> is already locked by another process. Opening read-only.
+File </mnt/data/workspace/pdk/sky130A//libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__inv_8.mag> is already locked by another process. Opening read-only.
+File </mnt/data/workspace/pdk/sky130A//libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__conb_1.mag> is already locked by another process. Opening read-only.
+File </mnt/data/workspace/pdk/sky130A//libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__dfxtp_4.mag> is already locked by another process. Opening read-only.
+File </mnt/data/workspace/pdk/sky130A//libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__dfrtp_4.mag> is already locked by another process. Opening read-only.
+File </mnt/data/workspace/pdk/sky130A//libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__dfstp_4.mag> is already locked by another process. Opening read-only.
+File </mnt/data/workspace/pdk/sky130A//libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__decap_3.mag> is already locked by another process. Opening read-only.
+File </mnt/data/workspace/pdk/sky130A//libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__tapvpwrvgnd_1.mag> is already locked by another process. Opening read-only.
+File </mnt/data/workspace/pdk/sky130A//libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__buf_8.mag> is already locked by another process. Opening read-only.
+File </mnt/data/workspace/pdk/sky130A//libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__clkbuf_16.mag> is already locked by another process. Opening read-only.
+File </mnt/data/workspace/pdk/sky130A//libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__clkbuf_1.mag> is already locked by another process. Opening read-only.
+File </mnt/data/workspace/pdk/sky130A//libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__diode_2.mag> is already locked by another process. Opening read-only.
+File </mnt/data/workspace/pdk/sky130A//libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__decap_12.mag> is already locked by another process. Opening read-only.
+File </mnt/data/workspace/pdk/sky130A//libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__decap_4.mag> is already locked by another process. Opening read-only.
+File </mnt/data/workspace/pdk/sky130A//libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__decap_6.mag> is already locked by another process. Opening read-only.
+File </mnt/data/workspace/pdk/sky130A//libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__decap_8.mag> is already locked by another process. Opening read-only.
+File </mnt/data/workspace/pdk/sky130A//libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__fill_2.mag> is already locked by another process. Opening read-only.
+File </mnt/data/workspace/pdk/sky130A//libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__fill_1.mag> is already locked by another process. Opening read-only.
+ Processed 927491 subcell instances total.
+ Processed 606 pins total.
+ Processed 2 special nets total.
+ Processed 192139 nets total.
+DEF read: Processed 5039852 lines.
+DEF Read: encountered 1 error total.
+Extracting sky130_fd_sc_hd__inv_8 into sky130_fd_sc_hd__inv_8.ext:
+Extracting sky130_fd_sc_hd__inv_4 into sky130_fd_sc_hd__inv_4.ext:
+Extracting sky130_fd_sc_hd__clkbuf_16 into sky130_fd_sc_hd__clkbuf_16.ext:
+Extracting sky130_fd_sc_hd__buf_8 into sky130_fd_sc_hd__buf_8.ext:
+Extracting sky130_fd_sc_hd__a41o_4 into sky130_fd_sc_hd__a41o_4.ext:
+Extracting sky130_fd_sc_hd__o41a_4 into sky130_fd_sc_hd__o41a_4.ext:
+Extracting sky130_fd_sc_hd__dfrtp_4 into sky130_fd_sc_hd__dfrtp_4.ext:
+Extracting sky130_fd_sc_hd__buf_4 into sky130_fd_sc_hd__buf_4.ext:
+Extracting sky130_fd_sc_hd__a2111o_4 into sky130_fd_sc_hd__a2111o_4.ext:
+Extracting sky130_fd_sc_hd__o32a_4 into sky130_fd_sc_hd__o32a_4.ext:
+Extracting sky130_fd_sc_hd__a22oi_4 into sky130_fd_sc_hd__a22oi_4.ext:
+Extracting sky130_fd_sc_hd__a21oi_4 into sky130_fd_sc_hd__a21oi_4.ext:
+Extracting sky130_fd_sc_hd__clkbuf_1 into sky130_fd_sc_hd__clkbuf_1.ext:
+Extracting sky130_fd_sc_hd__nand2_4 into sky130_fd_sc_hd__nand2_4.ext:
+Extracting sky130_fd_sc_hd__a21bo_4 into sky130_fd_sc_hd__a21bo_4.ext:
+Extracting sky130_fd_sc_hd__a32o_4 into sky130_fd_sc_hd__a32o_4.ext:
+Extracting sky130_fd_sc_hd__and4_4 into sky130_fd_sc_hd__and4_4.ext:
+Extracting sky130_fd_sc_hd__o21ai_4 into sky130_fd_sc_hd__o21ai_4.ext:
+Extracting sky130_fd_sc_hd__o22a_4 into sky130_fd_sc_hd__o22a_4.ext:
+Extracting sky130_fd_sc_hd__and2_4 into sky130_fd_sc_hd__and2_4.ext:
+Extracting sky130_fd_sc_hd__a21o_4 into sky130_fd_sc_hd__a21o_4.ext:
+Extracting sky130_fd_sc_hd__o21a_4 into sky130_fd_sc_hd__o21a_4.ext:
+Extracting sky130_fd_sc_hd__a211o_4 into sky130_fd_sc_hd__a211o_4.ext:
+Extracting sky130_fd_sc_hd__or3_4 into sky130_fd_sc_hd__or3_4.ext:
+Extracting sky130_fd_sc_hd__and3_4 into sky130_fd_sc_hd__and3_4.ext:
+Extracting sky130_fd_sc_hd__dfstp_4 into sky130_fd_sc_hd__dfstp_4.ext:
+Extracting sky130_fd_sc_hd__dfxtp_4 into sky130_fd_sc_hd__dfxtp_4.ext:
+Extracting sky130_fd_sc_hd__or2_4 into sky130_fd_sc_hd__or2_4.ext:
+Extracting sky130_fd_sc_hd__nor2_4 into sky130_fd_sc_hd__nor2_4.ext:
+Extracting sky130_fd_sc_hd__or4_4 into sky130_fd_sc_hd__or4_4.ext:
+Extracting sky130_fd_sc_hd__conb_1 into sky130_fd_sc_hd__conb_1.ext:
+sky130_fd_sc_hd__conb_1: 4 warnings
+Extracting sky130_fd_sc_hd__buf_2 into sky130_fd_sc_hd__buf_2.ext:
+Extracting sky130_fd_sc_hd__a2bb2o_4 into sky130_fd_sc_hd__a2bb2o_4.ext:
+Extracting sky130_fd_sc_hd__fill_1 into sky130_fd_sc_hd__fill_1.ext:
+Extracting sky130_fd_sc_hd__diode_2 into sky130_fd_sc_hd__diode_2.ext:
+Device has multiple lengths: scaling all widths to length 34
+Extracting sky130_fd_sc_hd__inv_2 into sky130_fd_sc_hd__inv_2.ext:
+Extracting sky130_fd_sc_hd__fill_2 into sky130_fd_sc_hd__fill_2.ext:
+Extracting sky130_fd_sc_hd__decap_8 into sky130_fd_sc_hd__decap_8.ext:
+sky130_fd_sc_hd__decap_8: 2 warnings
+Extracting sky130_fd_sc_hd__decap_6 into sky130_fd_sc_hd__decap_6.ext:
+sky130_fd_sc_hd__decap_6: 2 warnings
+Extracting sky130_fd_sc_hd__decap_4 into sky130_fd_sc_hd__decap_4.ext:
+sky130_fd_sc_hd__decap_4: 2 warnings
+Extracting sky130_fd_sc_hd__tapvpwrvgnd_1 into sky130_fd_sc_hd__tapvpwrvgnd_1.ext:
+Extracting sky130_fd_sc_hd__decap_12 into sky130_fd_sc_hd__decap_12.ext:
+sky130_fd_sc_hd__decap_12: 2 warnings
+Extracting sky130_fd_sc_hd__decap_3 into sky130_fd_sc_hd__decap_3.ext:
+sky130_fd_sc_hd__decap_3: 2 warnings
+Extracting user_proj_example into user_proj_example.ext:
+Created database crash recovery file /tmp//MAG917.eibPMA
+Total of 14 warnings.
+Reading extract file.
+Building flattened netlist.
+Running antenna checks.
+ 100 gates analyzed.
+ 200 gates analyzed.
+ 300 gates analyzed.
+ 400 gates analyzed.
+ 500 gates analyzed.
+ 600 gates analyzed.
+ 700 gates analyzed.
+ 800 gates analyzed.
+ 900 gates analyzed.
+ 1000 gates analyzed.
+ 1100 gates analyzed.
+ 1200 gates analyzed.
+ 1300 gates analyzed.
+ 1400 gates analyzed.
+ 1500 gates analyzed.
+ 1600 gates analyzed.
+ 1700 gates analyzed.
+ 1800 gates analyzed.
+ 1900 gates analyzed.
+ 2000 gates analyzed.
+ 2100 gates analyzed.
+ 2200 gates analyzed.
+ 2300 gates analyzed.
+ 2400 gates analyzed.
+ 2500 gates analyzed.
+ 2600 gates analyzed.
+ 2700 gates analyzed.
+ 2800 gates analyzed.
+ 2900 gates analyzed.
+ 3000 gates analyzed.
+ 3100 gates analyzed.
+ 3200 gates analyzed.
+ 3300 gates analyzed.
+ 3400 gates analyzed.
+ 3500 gates analyzed.
+ 3600 gates analyzed.
+ 3700 gates analyzed.
+ 3800 gates analyzed.
+ 3900 gates analyzed.
+ 4000 gates analyzed.
+ 4100 gates analyzed.
+ 4200 gates analyzed.
+ 4300 gates analyzed.
+ 4400 gates analyzed.
+ 4500 gates analyzed.
+ 4600 gates analyzed.
+ 4700 gates analyzed.
+ 4800 gates analyzed.
+ 4900 gates analyzed.
+ 5000 gates analyzed.
+ 5100 gates analyzed.
+ 5200 gates analyzed.
+ 5300 gates analyzed.
+ 5400 gates analyzed.
+ 5500 gates analyzed.
+ 5600 gates analyzed.
+ 5700 gates analyzed.
+ 5800 gates analyzed.
+ 5900 gates analyzed.
+ 6000 gates analyzed.
+ 6100 gates analyzed.
+ 6200 gates analyzed.
+ 6300 gates analyzed.
+ 6400 gates analyzed.
+ 6500 gates analyzed.
+ 6600 gates analyzed.
+ 6700 gates analyzed.
+ 6800 gates analyzed.
+ 6900 gates analyzed.
+ 7000 gates analyzed.
+ 7100 gates analyzed.
+ 7200 gates analyzed.
+ 7300 gates analyzed.
+ 7400 gates analyzed.
+ 7500 gates analyzed.
+ 7600 gates analyzed.
+ 7700 gates analyzed.
+ 7800 gates analyzed.
+ 7900 gates analyzed.
+ 8000 gates analyzed.
+ 8100 gates analyzed.
+ 8200 gates analyzed.
+ 8300 gates analyzed.
+ 8400 gates analyzed.
+ 8500 gates analyzed.
+ 8600 gates analyzed.
+ 8700 gates analyzed.
+ 8800 gates analyzed.
+ 8900 gates analyzed.
+ 9000 gates analyzed.
+ 9100 gates analyzed.
+ 9200 gates analyzed.
+ 9300 gates analyzed.
+ 9400 gates analyzed.
+ 9500 gates analyzed.
+ 9600 gates analyzed.
+ 9700 gates analyzed.
+ 9800 gates analyzed.
+ 9900 gates analyzed.
+ 10000 gates analyzed.
+ 10100 gates analyzed.
+ 10200 gates analyzed.
+ 10300 gates analyzed.
+ 10400 gates analyzed.
+ 10500 gates analyzed.
+ 10600 gates analyzed.
+ 10700 gates analyzed.
+ 10800 gates analyzed.
+ 10900 gates analyzed.
+ 11000 gates analyzed.
+ 11100 gates analyzed.
+ 11200 gates analyzed.
+ 11300 gates analyzed.
+ 11400 gates analyzed.
+ 11500 gates analyzed.
+ 11600 gates analyzed.
+ 11700 gates analyzed.
+ 11800 gates analyzed.
+ 11900 gates analyzed.
+ 12000 gates analyzed.
+ 12100 gates analyzed.
+ 12200 gates analyzed.
+ 12300 gates analyzed.
+ 12400 gates analyzed.
+ 12500 gates analyzed.
+ 12600 gates analyzed.
+ 12700 gates analyzed.
+ 12800 gates analyzed.
+ 12900 gates analyzed.
+ 13000 gates analyzed.
+ 13100 gates analyzed.
+ 13200 gates analyzed.
+ 13300 gates analyzed.
+ 13400 gates analyzed.
+ 13500 gates analyzed.
+ 13600 gates analyzed.
+ 13700 gates analyzed.
+ 13800 gates analyzed.
+ 13900 gates analyzed.
+ 14000 gates analyzed.
+ 14100 gates analyzed.
+ 14200 gates analyzed.
+ 14300 gates analyzed.
+ 14400 gates analyzed.
+ 14500 gates analyzed.
+ 14600 gates analyzed.
+ 14700 gates analyzed.
+ 14800 gates analyzed.
+ 14900 gates analyzed.
+ 15000 gates analyzed.
+ 15100 gates analyzed.
+ 15200 gates analyzed.
+ 15300 gates analyzed.
+ 15400 gates analyzed.
+ 15500 gates analyzed.
+ 15600 gates analyzed.
+ 15700 gates analyzed.
+ 15800 gates analyzed.
+ 15900 gates analyzed.
+ 16000 gates analyzed.
+ 16100 gates analyzed.
+ 16200 gates analyzed.
+ 16300 gates analyzed.
+ 16400 gates analyzed.
+ 16500 gates analyzed.
+ 16600 gates analyzed.
+ 16700 gates analyzed.
+ 16800 gates analyzed.
+ 16900 gates analyzed.
+ 17000 gates analyzed.
+ 17100 gates analyzed.
+ 17200 gates analyzed.
+ 17300 gates analyzed.
+ 17400 gates analyzed.
+ 17500 gates analyzed.
+ 17600 gates analyzed.
+ 17700 gates analyzed.
+ 17800 gates analyzed.
+ 17900 gates analyzed.
+ 18000 gates analyzed.
+ 18100 gates analyzed.
+ 18200 gates analyzed.
+ 18300 gates analyzed.
+ 18400 gates analyzed.
+ 18500 gates analyzed.
+ 18600 gates analyzed.
+ 18700 gates analyzed.
+ 18800 gates analyzed.
+ 18900 gates analyzed.
+ 19000 gates analyzed.
+ 19100 gates analyzed.
+ 19200 gates analyzed.
+ 19300 gates analyzed.
+ 19400 gates analyzed.
+ 19500 gates analyzed.
+ 19600 gates analyzed.
+ 19700 gates analyzed.
+ 19800 gates analyzed.
+ 19900 gates analyzed.
+ 20000 gates analyzed.
+ 20100 gates analyzed.
+ 20200 gates analyzed.
+ 20300 gates analyzed.
+ 20400 gates analyzed.
+ 20500 gates analyzed.
+ 20600 gates analyzed.
+ 20700 gates analyzed.
+ 20800 gates analyzed.
+ 20900 gates analyzed.
+ 21000 gates analyzed.
+ 21100 gates analyzed.
+ 21200 gates analyzed.
+ 21300 gates analyzed.
+ 21400 gates analyzed.
+ 21500 gates analyzed.
+ 21600 gates analyzed.
+ 21700 gates analyzed.
+ 21800 gates analyzed.
+ 21900 gates analyzed.
+ 22000 gates analyzed.
+ 22100 gates analyzed.
+ 22200 gates analyzed.
+ 22300 gates analyzed.
+ 22400 gates analyzed.
+ 22500 gates analyzed.
+ 22600 gates analyzed.
+ 22700 gates analyzed.
+ 22800 gates analyzed.
+ 22900 gates analyzed.
+ 23000 gates analyzed.
+ 23100 gates analyzed.
+ 23200 gates analyzed.
+ 23300 gates analyzed.
+ 23400 gates analyzed.
+ 23500 gates analyzed.
+ 23600 gates analyzed.
+ 23700 gates analyzed.
+ 23800 gates analyzed.
+ 23900 gates analyzed.
+ 24000 gates analyzed.
+ 24100 gates analyzed.
+ 24200 gates analyzed.
+ 24300 gates analyzed.
+ 24400 gates analyzed.
+ 24500 gates analyzed.
+ 24600 gates analyzed.
+ 24700 gates analyzed.
+ 24800 gates analyzed.
+ 24900 gates analyzed.
+ 25000 gates analyzed.
+ 25100 gates analyzed.
+ 25200 gates analyzed.
+ 25300 gates analyzed.
+ 25400 gates analyzed.
+ 25500 gates analyzed.
+ 25600 gates analyzed.
+ 25700 gates analyzed.
+ 25800 gates analyzed.
+ 25900 gates analyzed.
+ 26000 gates analyzed.
+ 26100 gates analyzed.
+ 26200 gates analyzed.
+ 26300 gates analyzed.
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+ 504500 gates analyzed.
+ 504600 gates analyzed.
+ 504700 gates analyzed.
+ 504800 gates analyzed.
+ 504900 gates analyzed.
+ 505000 gates analyzed.
+ 505100 gates analyzed.
+ 505200 gates analyzed.
+ 505300 gates analyzed.
+ 505400 gates analyzed.
+ 505500 gates analyzed.
+ 505600 gates analyzed.
+ 505700 gates analyzed.
+ 505800 gates analyzed.
+ 505900 gates analyzed.
+ 506000 gates analyzed.
+ 506100 gates analyzed.
+ 506200 gates analyzed.
+ 506300 gates analyzed.
+ 506400 gates analyzed.
+ 506500 gates analyzed.
+ 506600 gates analyzed.
+ 506700 gates analyzed.
+ 506800 gates analyzed.
+ 506900 gates analyzed.
+ 507000 gates analyzed.
+ 507100 gates analyzed.
+ 507200 gates analyzed.
+ 507300 gates analyzed.
+ 507400 gates analyzed.
+ 507500 gates analyzed.
+ 507600 gates analyzed.
+ 507700 gates analyzed.
+ 507800 gates analyzed.
+ 507900 gates analyzed.
+ 508000 gates analyzed.
+ 508100 gates analyzed.
+ 508200 gates analyzed.
+ 508300 gates analyzed.
+ 508400 gates analyzed.
+ 508500 gates analyzed.
+ 508600 gates analyzed.
+ 508700 gates analyzed.
+ 508800 gates analyzed.
+ 508900 gates analyzed.
+ 509000 gates analyzed.
+ 509100 gates analyzed.
+ 509200 gates analyzed.
+ 509300 gates analyzed.
+ 509400 gates analyzed.
+ 509500 gates analyzed.
+ 509600 gates analyzed.
+ 509700 gates analyzed.
+ 509800 gates analyzed.
+ 509900 gates analyzed.
+ 510000 gates analyzed.
+ 510100 gates analyzed.
+ 510200 gates analyzed.
+ 510300 gates analyzed.
+ 510400 gates analyzed.
+ 510500 gates analyzed.
+ 510600 gates analyzed.
+ 510700 gates analyzed.
+ 510800 gates analyzed.
+ 510900 gates analyzed.
+ 511000 gates analyzed.
+ 511100 gates analyzed.
+ 511200 gates analyzed.
+ 511300 gates analyzed.
+ 511400 gates analyzed.
+ 511500 gates analyzed.
+antennacheck finished.
+Using technology "sky130A", version 1.0.81-0-gb184e85
diff --git a/openlane/user_proj_example/results/logs/magic/magic_ext2spice.antenna.feedback.txt b/openlane/user_proj_example/results/logs/magic/magic_ext2spice.antenna.feedback.txt
new file mode 100644
index 0000000..1b77a85
--- /dev/null
+++ b/openlane/user_proj_example/results/logs/magic/magic_ext2spice.antenna.feedback.txt
@@ -0,0 +1,38 @@
+box 497342 4065 497344 4067
+feedback add "Label \"no_jumper_check\" attached to more than one unconnected node: c_83_258#" pale
+box 497445 4065 497447 4067
+feedback add "Label \"no_jumper_check\" attached to more than one unconnected node: c_186_258#" pale
+box 497492 4080 497494 4082
+feedback add "Label \"resistive_li1_ok\" attached to more than one unconnected node: c_233_273#" pale
+box 497304 4080 497306 4082
+feedback add "Label \"resistive_li1_ok\" attached to more than one unconnected node: c_45_273#" pale
+box 5875 616399 6453 616509
+feedback add "device missing 1 terminal;
+ connecting remainder to node VGND" pale
+box 5875 616675 6453 616849
+feedback add "device missing 1 terminal;
+ connecting remainder to node VPWR" pale
+box 496879 617283 497273 617393
+feedback add "device missing 1 terminal;
+ connecting remainder to node VGND" pale
+box 496879 616943 497273 617117
+feedback add "device missing 1 terminal;
+ connecting remainder to node VPWR" pale
+box 3667 617283 3877 617393
+feedback add "device missing 1 terminal;
+ connecting remainder to node VGND" pale
+box 3667 616943 3877 617117
+feedback add "device missing 1 terminal;
+ connecting remainder to node VPWR" pale
+box 497523 617283 498469 617393
+feedback add "device missing 1 terminal;
+ connecting remainder to node VGND" pale
+box 497523 616943 498469 617117
+feedback add "device missing 1 terminal;
+ connecting remainder to node VPWR" pale
+box 71931 615311 72049 615421
+feedback add "device missing 1 terminal;
+ connecting remainder to node VGND" pale
+box 71931 615587 72049 615761
+feedback add "device missing 1 terminal;
+ connecting remainder to node VPWR" pale
diff --git a/openlane/user_proj_example/results/logs/magic/magic_ext2spice.feedback.txt b/openlane/user_proj_example/results/logs/magic/magic_ext2spice.feedback.txt
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/openlane/user_proj_example/results/logs/magic/magic_ext2spice.feedback.txt
diff --git a/openlane/user_proj_example/results/logs/magic/magic_spice.log b/openlane/user_proj_example/results/logs/magic/magic_spice.log
new file mode 100644
index 0000000..18e17c0
--- /dev/null
+++ b/openlane/user_proj_example/results/logs/magic/magic_spice.log
@@ -0,0 +1,97 @@
+
+Magic 8.3 revision 92 - Compiled on Sat Dec 5 17:44:54 UTC 2020.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+Processing system .magicrc file
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130: scaleFactor=2, multiplier=2
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/project/openlane/user_proj_example/runs/16-12_10-43/tmp/magic_spice.tcl" from command line.
+Reading LEF data from file /mnt/data/workspace/pdk/sky130A/libs.ref/sky130_fd_sc_hd/techlef/sky130_fd_sc_hd.tlef.
+This action cannot be undone.
+LEF read, Line 77 (Message): Unknown keyword "ANTENNAMODEL" in LEF file; ignoring.
+LEF read, Line 78 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring.
+LEF read, Line 111 (Message): Unknown keyword "ANTENNAMODEL" in LEF file; ignoring.
+LEF read, Line 112 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring.
+LEF read, Line 118 (Message): Unknown keyword "MAXIMUMDENSITY" in LEF file; ignoring.
+LEF read, Line 119 (Message): Unknown keyword "DENSITYCHECKWINDOW" in LEF file; ignoring.
+LEF read, Line 120 (Message): Unknown keyword "DENSITYCHECKSTEP" in LEF file; ignoring.
+LEF read, Line 159 (Message): Unknown keyword "ANTENNAMODEL" in LEF file; ignoring.
+LEF read, Line 160 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring.
+LEF read, Line 162 (Message): Unknown keyword "MAXIMUMDENSITY" in LEF file; ignoring.
+LEF read, Line 163 (Message): Unknown keyword "DENSITYCHECKWINDOW" in LEF file; ignoring.
+LEF read, Line 164 (Message): Unknown keyword "DENSITYCHECKSTEP" in LEF file; ignoring.
+LEF read, Line 200 (Message): Unknown keyword "ANTENNAMODEL" in LEF file; ignoring.
+LEF read, Line 201 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring.
+LEF read, Line 203 (Message): Unknown keyword "MAXIMUMDENSITY" in LEF file; ignoring.
+LEF read, Line 204 (Message): Unknown keyword "DENSITYCHECKWINDOW" in LEF file; ignoring.
+LEF read, Line 205 (Message): Unknown keyword "DENSITYCHECKSTEP" in LEF file; ignoring.
+LEF read, Line 241 (Message): Unknown keyword "ANTENNAMODEL" in LEF file; ignoring.
+LEF read, Line 242 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring.
+LEF read, Line 244 (Message): Unknown keyword "MAXIMUMDENSITY" in LEF file; ignoring.
+LEF read, Line 245 (Message): Unknown keyword "DENSITYCHECKWINDOW" in LEF file; ignoring.
+LEF read, Line 246 (Message): Unknown keyword "DENSITYCHECKSTEP" in LEF file; ignoring.
+LEF read, Line 282 (Message): Unknown keyword "ANTENNAMODEL" in LEF file; ignoring.
+LEF read, Line 283 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring.
+LEF read: Processed 789 lines.
+Reading DEF data from file /project/openlane/user_proj_example/runs/16-12_10-43/results/routing/user_proj_example.def.
+This action cannot be undone.
+ Processed 5 vias total.
+Cell obs_core_obs_0 couldn't be read
+DEF read, Line 2327 (Error): Cell obs_core_obs_0 is not defined. Maybe you have not read the corresponding LEF file?
+ Processed 927491 subcell instances total.
+ Processed 606 pins total.
+ Processed 2 special nets total.
+ Processed 192139 nets total.
+DEF read: Processed 5039852 lines.
+DEF Read: encountered 1 error total.
+Extracting sky130_fd_sc_hd__a41o_4 into sky130_fd_sc_hd__a41o_4.ext:
+Extracting sky130_fd_sc_hd__o41a_4 into sky130_fd_sc_hd__o41a_4.ext:
+Extracting sky130_fd_sc_hd__o32a_4 into sky130_fd_sc_hd__o32a_4.ext:
+Extracting sky130_fd_sc_hd__a21bo_4 into sky130_fd_sc_hd__a21bo_4.ext:
+Extracting sky130_fd_sc_hd__a22oi_4 into sky130_fd_sc_hd__a22oi_4.ext:
+Extracting sky130_fd_sc_hd__a2bb2o_4 into sky130_fd_sc_hd__a2bb2o_4.ext:
+Extracting sky130_fd_sc_hd__a21o_4 into sky130_fd_sc_hd__a21o_4.ext:
+Extracting sky130_fd_sc_hd__nand2_4 into sky130_fd_sc_hd__nand2_4.ext:
+Extracting sky130_fd_sc_hd__inv_4 into sky130_fd_sc_hd__inv_4.ext:
+Extracting sky130_fd_sc_hd__inv_8 into sky130_fd_sc_hd__inv_8.ext:
+Extracting sky130_fd_sc_hd__a2111o_4 into sky130_fd_sc_hd__a2111o_4.ext:
+Extracting sky130_fd_sc_hd__a21oi_4 into sky130_fd_sc_hd__a21oi_4.ext:
+Extracting sky130_fd_sc_hd__o21ai_4 into sky130_fd_sc_hd__o21ai_4.ext:
+Extracting sky130_fd_sc_hd__a32o_4 into sky130_fd_sc_hd__a32o_4.ext:
+Extracting sky130_fd_sc_hd__nor2_4 into sky130_fd_sc_hd__nor2_4.ext:
+Extracting sky130_fd_sc_hd__and2_4 into sky130_fd_sc_hd__and2_4.ext:
+Extracting sky130_fd_sc_hd__a211o_4 into sky130_fd_sc_hd__a211o_4.ext:
+Extracting sky130_fd_sc_hd__o22a_4 into sky130_fd_sc_hd__o22a_4.ext:
+Extracting sky130_fd_sc_hd__and4_4 into sky130_fd_sc_hd__and4_4.ext:
+Extracting sky130_fd_sc_hd__or3_4 into sky130_fd_sc_hd__or3_4.ext:
+Extracting sky130_fd_sc_hd__o21a_4 into sky130_fd_sc_hd__o21a_4.ext:
+Extracting sky130_fd_sc_hd__or2_4 into sky130_fd_sc_hd__or2_4.ext:
+Extracting sky130_fd_sc_hd__and3_4 into sky130_fd_sc_hd__and3_4.ext:
+Extracting sky130_fd_sc_hd__or4_4 into sky130_fd_sc_hd__or4_4.ext:
+Extracting sky130_fd_sc_hd__inv_2 into sky130_fd_sc_hd__inv_2.ext:
+Extracting sky130_fd_sc_hd__conb_1 into sky130_fd_sc_hd__conb_1.ext:
+Extracting sky130_fd_sc_hd__dfstp_4 into sky130_fd_sc_hd__dfstp_4.ext:
+Extracting sky130_fd_sc_hd__dfxtp_4 into sky130_fd_sc_hd__dfxtp_4.ext:
+Extracting sky130_fd_sc_hd__dfrtp_4 into sky130_fd_sc_hd__dfrtp_4.ext:
+Extracting sky130_fd_sc_hd__tapvpwrvgnd_1 into sky130_fd_sc_hd__tapvpwrvgnd_1.ext:
+Extracting sky130_fd_sc_hd__buf_4 into sky130_fd_sc_hd__buf_4.ext:
+Extracting sky130_fd_sc_hd__buf_2 into sky130_fd_sc_hd__buf_2.ext:
+Extracting sky130_fd_sc_hd__buf_8 into sky130_fd_sc_hd__buf_8.ext:
+Extracting sky130_fd_sc_hd__clkbuf_1 into sky130_fd_sc_hd__clkbuf_1.ext:
+Extracting sky130_fd_sc_hd__clkbuf_16 into sky130_fd_sc_hd__clkbuf_16.ext:
+Extracting sky130_fd_sc_hd__diode_2 into sky130_fd_sc_hd__diode_2.ext:
+Extracting sky130_fd_sc_hd__decap_3 into sky130_fd_sc_hd__decap_3.ext:
+Extracting sky130_fd_sc_hd__fill_1 into sky130_fd_sc_hd__fill_1.ext:
+Extracting sky130_fd_sc_hd__decap_8 into sky130_fd_sc_hd__decap_8.ext:
+Extracting sky130_fd_sc_hd__fill_2 into sky130_fd_sc_hd__fill_2.ext:
+Extracting sky130_fd_sc_hd__decap_4 into sky130_fd_sc_hd__decap_4.ext:
+Extracting sky130_fd_sc_hd__decap_6 into sky130_fd_sc_hd__decap_6.ext:
+Extracting sky130_fd_sc_hd__decap_12 into sky130_fd_sc_hd__decap_12.ext:
+Extracting user_proj_example into user_proj_example.ext:
+Created database crash recovery file /tmp//MAG585.JUfUXF
+exttospice finished.
+Using technology "sky130A", version 1.0.81-0-gb184e85
diff --git a/openlane/user_proj_example/results/logs/placement/opendp.log b/openlane/user_proj_example/results/logs/placement/opendp.log
new file mode 100644
index 0000000..80becc9
--- /dev/null
+++ b/openlane/user_proj_example/results/logs/placement/opendp.log
@@ -0,0 +1,136 @@
+===========================================================================
+ Open Source Mixed-Height Standard Cell Detail Placer < OpenDP_v1.0 >
+ Developers : SangGi Do, Mingyu Woo
+===========================================================================
+Parsed 10000 number of lines!!
+Parsed 20000 number of lines!!
+Parsed 30000 number of lines!!
+Parsed 40000 number of lines!!
+Parsed 50000 number of lines!!
+Parsed 60000 number of lines!!
+Reading /project/openlane/user_proj_example/runs/16-12_10-43/tmp/merged.lef is Done
+
+-------------------- INPUT FILES ----------------------------------
+ benchmark name : placement
+ directory : /project/openlane/user_proj_example/runs/16-12_10-43/tmp
+ lef : /project/openlane/user_proj_example/runs/16-12_10-43/tmp/merged.lef
+ def : /project/openlane/user_proj_example/runs/16-12_10-43/tmp/placement/user_proj_example.diodes.def
+-------------------------------------------------------------------
+Parsed 10000 number of lines!!
+Parsed 20000 number of lines!!
+Parsed 30000 number of lines!!
+Parsed 40000 number of lines!!
+Parsed 50000 number of lines!!
+Parsed 60000 number of lines!!
+Parsed 70000 number of lines!!
+Parsed 80000 number of lines!!
+Parsed 90000 number of lines!!
+Parsed 100000 number of lines!!
+Parsed 110000 number of lines!!
+Parsed 120000 number of lines!!
+Parsed 130000 number of lines!!
+Parsed 140000 number of lines!!
+Parsed 150000 number of lines!!
+Parsed 160000 number of lines!!
+Parsed 170000 number of lines!!
+Parsed 180000 number of lines!!
+Parsed 190000 number of lines!!
+Parsed 200000 number of lines!!
+Parsed 210000 number of lines!!
+Parsed 220000 number of lines!!
+Parsed 230000 number of lines!!
+Parsed 240000 number of lines!!
+Parsed 250000 number of lines!!
+Parsed 260000 number of lines!!
+Parsed 270000 number of lines!!
+Parsed 280000 number of lines!!
+Parsed 290000 number of lines!!
+Parsed 300000 number of lines!!
+Parsed 310000 number of lines!!
+Parsed 320000 number of lines!!
+Parsed 330000 number of lines!!
+Parsed 340000 number of lines!!
+Parsed 350000 number of lines!!
+Parsed 360000 number of lines!!
+Parsed 370000 number of lines!!
+Parsed 380000 number of lines!!
+Parsed 390000 number of lines!!
+Parsed 400000 number of lines!!
+Parsed 410000 number of lines!!
+Parsed 420000 number of lines!!
+Parsed 430000 number of lines!!
+Parsed 440000 number of lines!!
+Parsed 450000 number of lines!!
+Parsed 460000 number of lines!!
+Parsed 470000 number of lines!!
+Parsed 480000 number of lines!!
+Parsed 490000 number of lines!!
+Parsed 500000 number of lines!!
+Parsed 510000 number of lines!!
+Parsed 520000 number of lines!!
+Parsed 530000 number of lines!!
+Parsed 540000 number of lines!!
+Parsed 550000 number of lines!!
+Parsed 560000 number of lines!!
+Parsed 570000 number of lines!!
+Parsed 580000 number of lines!!
+Parsed 590000 number of lines!!
+Parsed 600000 number of lines!!
+Parsed 610000 number of lines!!
+Parsed 620000 number of lines!!
+Parsed 630000 number of lines!!
+Parsed 640000 number of lines!!
+Parsed 650000 number of lines!!
+Parsed 660000 number of lines!!
+Parsed 670000 number of lines!!
+Parsed 680000 number of lines!!
+Parsed 690000 number of lines!!
+CoreArea:
+5520.000000 : 10880.000000 - 2494120.000000 : 3087200.000000
+DieArea:
+0.000000 : 0.000000 - 2488600.000000 : 3076320.000000
+Reading /project/openlane/user_proj_example/runs/16-12_10-43/tmp/placement/user_proj_example.diodes.def is Done
+-------------------- DESIGN ANALYSIS ------------------------------
+ total cells : 420720
+ multi cells : 0
+ fixed cells : 102526
+ total nets : 192139
+ design area : 7.65573e+12
+ total f_area : 1.33941e+11
+ total m_area : 2.54963e+12
+ design util : 33.8966
+ num rows : 1131
+ row height : 2720
+-------------------------------------------------------------------
+ non_group_cell_region_assign done ..
+ - - - - - - - - - - - - - - - - - - - - - - - -
+ non_group_cell_placement done ..
+ - - - - - - - - - - - - - - - - - - - - - - - -
+Reading /project/openlane/user_proj_example/runs/16-12_10-43/tmp/placement/user_proj_example.diodes.def is Done
+ DEF file write success !!
+ location : /project/openlane/user_proj_example/runs/16-12_10-43/results/placement/user_proj_example.placement.def
+-------------------------------------------------------------------
+ tasks Wtime Ctime
+ Parser 8.140 8.070
+ resgin assign 8.575 8.500
+ pre-placement 8.575 8.500
+ non Group cell placement 8.916 8.840
+ All 8.964 8.890
+ - - - - - EVALUATION - - - - -
+ AVG_displacement : 54.2436
+ SUM_displacement : 2.28214e+07
+ MAX_displacement : 9200
+ - - - - - - - - - - - - - - - -
+ GP HPWL : 1.25408e+07
+ HPWL : 1.25467e+07
+ avg_Disp_site : 0.117921
+ avg_Disp_row : 0.0199425
+ delta_HPWL : 0.0466474
+ ==== CHECK LEGALITY ====
+ row_check ==>> PASS
+ site_check ==>> PASS
+ power_check ==>> PASS
+ edge_check ==>> PASS
+ placed_check ==>> PASS
+ overlap_check ==>> PASS
+ - - - - - < Program END > - - - - -
diff --git a/openlane/user_proj_example/results/logs/placement/opendp_runtime.txt b/openlane/user_proj_example/results/logs/placement/opendp_runtime.txt
new file mode 100644
index 0000000..0bbf54d
--- /dev/null
+++ b/openlane/user_proj_example/results/logs/placement/opendp_runtime.txt
@@ -0,0 +1,2 @@
+0h0m8s441ms
+0h0m16s529ms
diff --git a/openlane/user_proj_example/results/logs/placement/openphysyn.log b/openlane/user_proj_example/results/logs/placement/openphysyn.log
new file mode 100644
index 0000000..c665b83
--- /dev/null
+++ b/openlane/user_proj_example/results/logs/placement/openphysyn.log
@@ -0,0 +1,1620 @@
+[OpenPhySyn] [2020-12-16 10:57:01.883] [info] Loaded 6 transforms.
+[OpenPhySyn] [2020-12-16 10:57:02.508] [info] OpenPhySyn: 1.8.1
+Warning: /project/openlane/user_proj_example/runs/16-12_10-43/tmp/opt.lib, line 32 default_operating_condition ss_100C_1v60 not found.
+Notice 0: Reading LEF file: /project/openlane/user_proj_example/runs/16-12_10-43/tmp/merged_unpadded.lef
+Notice 0: Created 13 technology layers
+Notice 0: Created 25 technology vias
+Notice 0: Created 438 library cells
+Notice 0: Finished LEF file: /project/openlane/user_proj_example/runs/16-12_10-43/tmp/merged_unpadded.lef
+Notice 0:
+Reading DEF file: /project/openlane/user_proj_example/runs/16-12_10-43/tmp/placement/replace.def
+Notice 0: Design: user_proj_example
+Notice 0: Created 100000 Insts
+Notice 0: Created 200000 Insts
+Notice 0: Created 100000 Nets
+Notice 0: Created 606 pins.
+Notice 0: Created 289855 components and 1555004 component-terminals.
+Notice 0: Created 2 special nets and 0 connections.
+Notice 0: Created 187696 nets and 596035 connections.
+Notice 0: Finished DEF file: /project/openlane/user_proj_example/runs/16-12_10-43/tmp/placement/replace.def
+[INFO]: Setting output delay to: 4.0
+[INFO]: Setting input delay to: 4.0
+[INFO]: Setting load to: 0.01765
+=============== Initial Reports =============
+Startpoint: la_data_in[2] (input port clocked by wb_clk_i)
+Endpoint: _346788_ (recovery check against rising-edge clock wb_clk_i)
+Path Group: **async_default**
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (ideal)
+ 4.00 4.00 v input external delay
+ 0.48 4.48 v la_data_in[2] (in)
+ 0.59 5.07 v _163808_/X (sky130_fd_sc_hd__or2_4)
+ 0.40 5.47 v _163809_/X (sky130_fd_sc_hd__buf_2)
+ 0.39 5.86 v _163810_/X (sky130_fd_sc_hd__buf_2)
+ 0.11 5.97 ^ _163811_/Y (sky130_fd_sc_hd__inv_2)
+ 0.41 6.38 ^ _163812_/X (sky130_fd_sc_hd__buf_2)
+ 0.39 6.77 ^ _163813_/X (sky130_fd_sc_hd__buf_2)
+ 0.57 7.34 ^ _163814_/X (sky130_fd_sc_hd__buf_2)
+ 0.93 8.27 ^ _172814_/X (sky130_fd_sc_hd__buf_2)
+ 0.55 8.82 ^ _172921_/X (sky130_fd_sc_hd__buf_2)
+ 0.20 9.02 ^ _172927_/X (sky130_fd_sc_hd__buf_2)
+ 0.00 9.02 ^ _346788_/SET_B (sky130_fd_sc_hd__dfstp_4)
+ 9.02 data arrival time
+
+ 20.00 20.00 clock wb_clk_i (rise edge)
+ 0.00 20.00 clock network delay (ideal)
+ 0.00 20.00 clock reconvergence pessimism
+ 20.00 ^ _346788_/CLK (sky130_fd_sc_hd__dfstp_4)
+ 0.25 20.25 library recovery time
+ 20.25 data required time
+---------------------------------------------------------
+ 20.25 data required time
+ -9.02 data arrival time
+---------------------------------------------------------
+ 11.22 slack (MET)
+
+
+Startpoint: wbs_adr_i[2] (input port clocked by wb_clk_i)
+Endpoint: wbs_dat_o[7] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (ideal)
+ 4.00 4.00 ^ input external delay
+ 0.27 4.27 ^ wbs_adr_i[2] (in)
+ 0.91 5.18 ^ _160705_/X (sky130_fd_sc_hd__a32o_4)
+ 1.07 6.25 ^ _160712_/X (sky130_fd_sc_hd__buf_2)
+ 0.55 6.80 ^ _162471_/X (sky130_fd_sc_hd__buf_2)
+ 1.19 8.00 ^ _162472_/X (sky130_fd_sc_hd__buf_2)
+ 1.22 9.21 ^ _162473_/X (sky130_fd_sc_hd__buf_2)
+ 0.94 10.15 ^ _162474_/X (sky130_fd_sc_hd__buf_2)
+ 0.84 10.99 ^ _163102_/X (sky130_fd_sc_hd__or4_4)
+ 0.50 11.48 ^ _164092_/X (sky130_fd_sc_hd__or4_4)
+ 0.31 11.79 ^ _164093_/X (sky130_fd_sc_hd__buf_2)
+ 0.11 11.90 v _164094_/Y (sky130_fd_sc_hd__inv_2)
+ 0.41 12.31 v _280957_/X (sky130_fd_sc_hd__or2_4)
+ 0.34 12.65 v _280958_/X (sky130_fd_sc_hd__buf_2)
+ 0.35 13.00 v _281237_/X (sky130_fd_sc_hd__buf_2)
+ 0.46 13.46 v _281238_/X (sky130_fd_sc_hd__or2_4)
+ 0.56 14.02 v _281240_/X (sky130_fd_sc_hd__a32o_4)
+ 2.03 16.05 ^ _281241_/Y (sky130_fd_sc_hd__a22oi_4)
+ 0.94 16.99 v _312746_/Y (sky130_fd_sc_hd__inv_2)
+ 0.00 16.99 v wbs_dat_o[7] (out)
+ 16.99 data arrival time
+
+ 20.00 20.00 clock wb_clk_i (rise edge)
+ 0.00 20.00 clock network delay (ideal)
+ 0.00 20.00 clock reconvergence pessimism
+ -4.00 16.00 output external delay
+ 16.00 data required time
+---------------------------------------------------------
+ 16.00 data required time
+ -16.99 data arrival time
+---------------------------------------------------------
+ -0.99 slack (VIOLATED)
+
+
+max slew
+
+Pin Limit Slew Slack
+------------------------------------------------------------
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+_320792_/A 1.50 5.18 -3.68 (VIOLATED)
+_318740_/Y 1.50 5.17 -3.68 (VIOLATED)
+_320794_/A 1.50 5.17 -3.67 (VIOLATED)
+_318797_/Y 1.50 5.16 -3.66 (VIOLATED)
+_318683_/Y 1.50 5.16 -3.66 (VIOLATED)
+_320791_/A 1.50 5.14 -3.64 (VIOLATED)
+_318627_/Y 1.50 5.12 -3.63 (VIOLATED)
+_320790_/A 1.50 5.07 -3.57 (VIOLATED)
+_318571_/Y 1.50 5.05 -3.56 (VIOLATED)
+_320789_/A 1.50 4.89 -3.39 (VIOLATED)
+_318515_/Y 1.50 4.88 -3.38 (VIOLATED)
+_320788_/A 1.50 4.74 -3.24 (VIOLATED)
+_318445_/Y 1.50 4.73 -3.23 (VIOLATED)
+_320787_/A 1.50 4.66 -3.16 (VIOLATED)
+_318379_/Y 1.50 4.65 -3.15 (VIOLATED)
+_320785_/A 1.50 4.53 -3.03 (VIOLATED)
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+_263271_/A 1.50 1.56 -0.06 (VIOLATED)
+_264363_/A 1.50 1.56 -0.06 (VIOLATED)
+_265447_/A 1.50 1.56 -0.06 (VIOLATED)
+_252244_/X 1.51 1.57 -0.06 (VIOLATED)
+_320735_/A 1.50 1.56 -0.06 (VIOLATED)
+_300997_/A 1.50 1.56 -0.06 (VIOLATED)
+_194811_/A 1.50 1.56 -0.06 (VIOLATED)
+_268011_/A 1.50 1.55 -0.05 (VIOLATED)
+_243237_/A 1.50 1.55 -0.05 (VIOLATED)
+_194886_/A 1.50 1.55 -0.05 (VIOLATED)
+_319269_/X 1.50 1.56 -0.05 (VIOLATED)
+_193475_/A 1.50 1.55 -0.05 (VIOLATED)
+_178853_/X 1.50 1.56 -0.05 (VIOLATED)
+_193222_/A 1.50 1.55 -0.05 (VIOLATED)
+_195194_/A 1.50 1.55 -0.05 (VIOLATED)
+_194775_/X 1.51 1.56 -0.05 (VIOLATED)
+_240282_/A 1.50 1.55 -0.05 (VIOLATED)
+_246473_/A 1.50 1.55 -0.05 (VIOLATED)
+_194571_/A 1.50 1.55 -0.05 (VIOLATED)
+_196651_/A 1.50 1.55 -0.05 (VIOLATED)
+_199197_/A 1.50 1.55 -0.05 (VIOLATED)
+_193561_/X 1.51 1.56 -0.05 (VIOLATED)
+_268230_/A 1.50 1.55 -0.05 (VIOLATED)
+_268120_/A 1.50 1.55 -0.05 (VIOLATED)
+_162524_/X 1.51 1.56 -0.05 (VIOLATED)
+_228652_/A 1.50 1.55 -0.05 (VIOLATED)
+_222428_/A 1.50 1.55 -0.05 (VIOLATED)
+_272771_/X 1.51 1.56 -0.05 (VIOLATED)
+_227786_/A 1.50 1.55 -0.05 (VIOLATED)
+_241589_/A 1.50 1.55 -0.05 (VIOLATED)
+_201600_/A 1.50 1.55 -0.05 (VIOLATED)
+_259094_/A 1.50 1.55 -0.05 (VIOLATED)
+_194174_/A 1.50 1.55 -0.05 (VIOLATED)
+_162301_/A 1.50 1.55 -0.05 (VIOLATED)
+_194767_/X 1.51 1.56 -0.05 (VIOLATED)
+_195682_/A 1.50 1.55 -0.05 (VIOLATED)
+_227602_/A 1.50 1.55 -0.05 (VIOLATED)
+_241402_/A 1.50 1.55 -0.05 (VIOLATED)
+_193438_/A 1.50 1.55 -0.05 (VIOLATED)
+_194323_/X 1.51 1.56 -0.05 (VIOLATED)
+_193726_/X 1.51 1.56 -0.05 (VIOLATED)
+_195435_/A 1.50 1.55 -0.05 (VIOLATED)
+_193101_/A 1.50 1.55 -0.05 (VIOLATED)
+_196027_/A 1.50 1.55 -0.05 (VIOLATED)
+_198582_/A 1.50 1.55 -0.05 (VIOLATED)
+_193111_/A 1.50 1.55 -0.05 (VIOLATED)
+_196887_/A 1.50 1.55 -0.05 (VIOLATED)
+_203268_/A 1.50 1.55 -0.05 (VIOLATED)
+_195156_/A 1.50 1.55 -0.05 (VIOLATED)
+_204824_/A 1.50 1.55 -0.05 (VIOLATED)
+_195813_/A 1.50 1.55 -0.05 (VIOLATED)
+_195938_/A 1.50 1.55 -0.05 (VIOLATED)
+_196687_/A 1.50 1.55 -0.05 (VIOLATED)
+_194660_/A 1.50 1.55 -0.05 (VIOLATED)
+_193166_/A 1.50 1.55 -0.05 (VIOLATED)
+_221384_/A 1.50 1.54 -0.04 (VIOLATED)
+_200526_/A 1.50 1.54 -0.04 (VIOLATED)
+_319091_/X 1.50 1.55 -0.04 (VIOLATED)
+_195385_/A 1.50 1.54 -0.04 (VIOLATED)
+_199454_/A 1.50 1.54 -0.04 (VIOLATED)
+_194570_/X 1.51 1.55 -0.04 (VIOLATED)
+_267791_/X 1.51 1.55 -0.04 (VIOLATED)
+_178875_/A 1.50 1.54 -0.04 (VIOLATED)
+_263461_/A 1.50 1.54 -0.04 (VIOLATED)
+_265629_/A 1.50 1.54 -0.04 (VIOLATED)
+_193100_/X 1.51 1.55 -0.04 (VIOLATED)
+_238872_/A 1.50 1.54 -0.04 (VIOLATED)
+_194600_/A 1.50 1.54 -0.04 (VIOLATED)
+_200476_/A 1.50 1.54 -0.04 (VIOLATED)
+_263152_/A 1.50 1.54 -0.04 (VIOLATED)
+_195155_/X 1.51 1.55 -0.04 (VIOLATED)
+_193907_/A 1.50 1.54 -0.04 (VIOLATED)
+_300749_/B 1.50 1.54 -0.04 (VIOLATED)
+_197045_/A 1.50 1.54 -0.04 (VIOLATED)
+_193624_/A 1.50 1.54 -0.04 (VIOLATED)
+_239722_/A 1.50 1.54 -0.04 (VIOLATED)
+_202629_/A 1.50 1.54 -0.04 (VIOLATED)
+_194059_/A 1.50 1.54 -0.04 (VIOLATED)
+_194659_/X 1.51 1.54 -0.04 (VIOLATED)
+_193582_/A 1.50 1.53 -0.03 (VIOLATED)
+_193221_/X 1.51 1.54 -0.03 (VIOLATED)
+_272789_/A 1.50 1.53 -0.03 (VIOLATED)
+_246999_/A 1.50 1.53 -0.03 (VIOLATED)
+_205468_/B 1.50 1.53 -0.03 (VIOLATED)
+_267522_/A 1.50 1.53 -0.03 (VIOLATED)
+_193006_/A 1.50 1.53 -0.03 (VIOLATED)
+_194677_/A 1.50 1.53 -0.03 (VIOLATED)
+_273345_/A 1.50 1.53 -0.03 (VIOLATED)
+_205822_/A 1.50 1.53 -0.03 (VIOLATED)
+_205951_/A 1.50 1.53 -0.03 (VIOLATED)
+_273900_/A 1.50 1.53 -0.03 (VIOLATED)
+_280589_/A 1.50 1.53 -0.03 (VIOLATED)
+_198430_/A 1.50 1.53 -0.03 (VIOLATED)
+_197159_/A 1.50 1.53 -0.03 (VIOLATED)
+_195771_/A 1.50 1.53 -0.03 (VIOLATED)
+_248787_/A 1.50 1.53 -0.03 (VIOLATED)
+_304128_/B1 1.50 1.53 -0.03 (VIOLATED)
+_251566_/A 1.50 1.53 -0.03 (VIOLATED)
+_194173_/X 1.51 1.54 -0.03 (VIOLATED)
+_164669_/A 1.50 1.53 -0.03 (VIOLATED)
+_272212_/A 1.50 1.53 -0.03 (VIOLATED)
+_206331_/A 1.50 1.53 -0.03 (VIOLATED)
+_275009_/A 1.50 1.53 -0.03 (VIOLATED)
+_271657_/A 1.50 1.53 -0.03 (VIOLATED)
+_274454_/A 1.50 1.53 -0.03 (VIOLATED)
+_194604_/A 1.50 1.53 -0.03 (VIOLATED)
+_194757_/A 1.50 1.53 -0.03 (VIOLATED)
+_193906_/X 1.51 1.54 -0.03 (VIOLATED)
+_244754_/A 1.50 1.53 -0.03 (VIOLATED)
+_238551_/A 1.50 1.53 -0.03 (VIOLATED)
+_262246_/A 1.50 1.53 -0.03 (VIOLATED)
+_193474_/X 1.51 1.54 -0.03 (VIOLATED)
+_224748_/A 1.50 1.53 -0.03 (VIOLATED)
+_194599_/X 1.51 1.54 -0.03 (VIOLATED)
+_206205_/A 1.50 1.53 -0.03 (VIOLATED)
+_206079_/A 1.50 1.53 -0.03 (VIOLATED)
+_190541_/B1 1.50 1.53 -0.03 (VIOLATED)
+_193110_/X 1.51 1.53 -0.03 (VIOLATED)
+_226489_/A 1.50 1.52 -0.02 (VIOLATED)
+_220269_/A 1.50 1.52 -0.02 (VIOLATED)
+_281299_/B1 1.50 1.52 -0.02 (VIOLATED)
+_178843_/X 1.50 1.53 -0.02 (VIOLATED)
+_199381_/A 1.50 1.52 -0.02 (VIOLATED)
+_231380_/B2 1.50 1.52 -0.02 (VIOLATED)
+_271103_/A 1.50 1.52 -0.02 (VIOLATED)
+_205467_/X 1.51 1.53 -0.02 (VIOLATED)
+_206450_/A 1.50 1.52 -0.02 (VIOLATED)
+_162300_/X 1.51 1.53 -0.02 (VIOLATED)
+_268871_/A 1.50 1.52 -0.02 (VIOLATED)
+_219682_/A 1.50 1.52 -0.02 (VIOLATED)
+_225895_/A 1.50 1.52 -0.02 (VIOLATED)
+_269426_/A 1.50 1.52 -0.02 (VIOLATED)
+_290140_/B1 1.50 1.52 -0.02 (VIOLATED)
+_196239_/A 1.50 1.52 -0.02 (VIOLATED)
+_228163_/A 1.50 1.52 -0.02 (VIOLATED)
+_241963_/A 1.50 1.52 -0.02 (VIOLATED)
+_259463_/A 1.50 1.52 -0.02 (VIOLATED)
+_257123_/A 1.50 1.52 -0.02 (VIOLATED)
+_193277_/A 1.50 1.52 -0.02 (VIOLATED)
+_272788_/X 1.51 1.53 -0.02 (VIOLATED)
+_221940_/A 1.50 1.52 -0.02 (VIOLATED)
+_193615_/A 1.50 1.52 -0.02 (VIOLATED)
+_194676_/X 1.51 1.53 -0.02 (VIOLATED)
+_270548_/A 1.50 1.52 -0.02 (VIOLATED)
+_186545_/A 1.50 1.52 -0.02 (VIOLATED)
+_203821_/A 1.50 1.52 -0.02 (VIOLATED)
+_198779_/A 1.50 1.52 -0.02 (VIOLATED)
+_291114_/A 1.50 1.52 -0.02 (VIOLATED)
+_193000_/A 1.50 1.52 -0.02 (VIOLATED)
+_194597_/A 1.50 1.52 -0.02 (VIOLATED)
+_194754_/A 1.50 1.52 -0.02 (VIOLATED)
+_245685_/A 1.50 1.52 -0.02 (VIOLATED)
+_193160_/A 1.50 1.52 -0.02 (VIOLATED)
+_205821_/X 1.51 1.52 -0.02 (VIOLATED)
+_241588_/A 1.50 1.51 -0.01 (VIOLATED)
+_259093_/A 1.50 1.51 -0.01 (VIOLATED)
+_268317_/A 1.50 1.51 -0.01 (VIOLATED)
+_265784_/A 1.50 1.51 -0.01 (VIOLATED)
+_266814_/A 1.50 1.51 -0.01 (VIOLATED)
+_257677_/A 1.50 1.51 -0.01 (VIOLATED)
+_206786_/A 1.50 1.51 -0.01 (VIOLATED)
+_269980_/A 1.50 1.51 -0.01 (VIOLATED)
+_207578_/A 1.50 1.51 -0.01 (VIOLATED)
+_207196_/A 1.50 1.51 -0.01 (VIOLATED)
+_207388_/A 1.50 1.51 -0.01 (VIOLATED)
+_301013_/A 1.50 1.51 -0.01 (VIOLATED)
+_225292_/A 1.50 1.51 -0.01 (VIOLATED)
+_239094_/A 1.50 1.51 -0.01 (VIOLATED)
+_245294_/A 1.50 1.51 -0.01 (VIOLATED)
+_262785_/A 1.50 1.51 -0.01 (VIOLATED)
+_269988_/A 1.50 1.51 -0.01 (VIOLATED)
+_190540_/X 1.51 1.52 -0.01 (VIOLATED)
+_208392_/A 1.50 1.51 -0.01 (VIOLATED)
+_193276_/X 1.51 1.52 -0.01 (VIOLATED)
+_210414_/A 1.50 1.51 -0.01 (VIOLATED)
+_270541_/A 1.50 1.51 -0.01 (VIOLATED)
+_263463_/A 1.50 1.51 -0.01 (VIOLATED)
+_259819_/A 1.50 1.51 -0.01 (VIOLATED)
+_246015_/A 1.50 1.51 -0.01 (VIOLATED)
+_195016_/A 1.50 1.51 -0.01 (VIOLATED)
+_260339_/A 1.50 1.51 -0.01 (VIOLATED)
+_291141_/A 1.50 1.51 -0.01 (VIOLATED)
+_247651_/B1 1.50 1.51 -0.01 (VIOLATED)
+_247631_/B1 1.50 1.51 -0.01 (VIOLATED)
+_291136_/A 1.50 1.51 -0.01 (VIOLATED)
+_194010_/A 1.50 1.51 -0.01 (VIOLATED)
+_247611_/B1 1.50 1.51 -0.01 (VIOLATED)
+_193159_/X 1.51 1.52 -0.01 (VIOLATED)
+_195729_/X 1.51 1.51 -0.01 (VIOLATED)
+_206811_/A 1.50 1.50 -0.00 (VIOLATED)
+_164668_/X 1.51 1.51 -0.00 (VIOLATED)
+_194774_/A 1.50 1.50 -0.00 (VIOLATED)
+_226361_/A 1.50 1.50 -0.00 (VIOLATED)
+_237657_/A 1.50 1.50 -0.00 (VIOLATED)
+_243865_/A 1.50 1.50 -0.00 (VIOLATED)
+_194853_/A 1.50 1.50 -0.00 (VIOLATED)
+_206447_/X 1.51 1.51 -0.00 (VIOLATED)
+_261359_/A 1.50 1.50 -0.00 (VIOLATED)
+_194709_/A 1.50 1.50 -0.00 (VIOLATED)
+_223854_/A 1.50 1.50 -0.00 (VIOLATED)
+_262657_/A 1.50 1.50 -0.00 (VIOLATED)
+_245166_/A 1.50 1.50 -0.00 (VIOLATED)
+_238966_/A 1.50 1.50 -0.00 (VIOLATED)
+_225163_/A 1.50 1.50 -0.00 (VIOLATED)
+_219307_/A 1.50 1.50 -0.00 (VIOLATED)
+_218869_/A 1.50 1.50 -0.00 (VIOLATED)
+_195077_/A 1.50 1.50 -0.00 (VIOLATED)
+_220824_/A 1.50 1.50 -0.00 (VIOLATED)
+_199948_/A 1.50 1.50 -0.00 (VIOLATED)
+_198117_/A 1.50 1.50 -0.00 (VIOLATED)
+_264165_/A 1.50 1.50 -0.00 (VIOLATED)
+_265252_/A 1.50 1.50 -0.00 (VIOLATED)
+_266294_/A 1.50 1.50 -0.00 (VIOLATED)
+_267321_/A 1.50 1.50 -0.00 (VIOLATED)
+_193573_/A 1.50 1.50 -0.00 (VIOLATED)
+_194783_/A 1.50 1.50 -0.00 (VIOLATED)
+_263195_/A 1.50 1.50 -0.00 (VIOLATED)
+_265005_/B 1.50 1.50 -0.00 (VIOLATED)
+_266060_/B 1.50 1.50 -0.00 (VIOLATED)
+_267089_/B 1.50 1.50 -0.00 (VIOLATED)
+_204531_/A 1.50 1.50 -0.00 (VIOLATED)
+_198006_/A 1.50 1.50 -0.00 (VIOLATED)
+_204375_/A 1.50 1.50 -0.00 (VIOLATED)
+
+max capacitance
+
+Pin Limit Cap Slack
+------------------------------------------------------------
+_281241_/Y 0.18 0.25 -0.07 (VIOLATED)
+_281256_/Y 0.18 0.25 -0.07 (VIOLATED)
+_205403_/X 0.20 0.24 -0.04 (VIOLATED)
+_247123_/X 0.20 0.24 -0.04 (VIOLATED)
+_247251_/X 0.20 0.23 -0.04 (VIOLATED)
+_296846_/X 0.20 0.23 -0.03 (VIOLATED)
+_205602_/X 0.20 0.23 -0.03 (VIOLATED)
+_193669_/X 0.20 0.23 -0.03 (VIOLATED)
+_296717_/X 0.20 0.23 -0.03 (VIOLATED)
+_296733_/X 0.20 0.23 -0.03 (VIOLATED)
+_296730_/X 0.20 0.23 -0.03 (VIOLATED)
+_206195_/X 0.20 0.23 -0.03 (VIOLATED)
+_193764_/X 0.20 0.23 -0.03 (VIOLATED)
+_296740_/X 0.20 0.23 -0.03 (VIOLATED)
+_254345_/X 0.20 0.23 -0.03 (VIOLATED)
+_296743_/X 0.20 0.22 -0.03 (VIOLATED)
+_296737_/X 0.20 0.22 -0.03 (VIOLATED)
+_193801_/X 0.20 0.22 -0.02 (VIOLATED)
+_205546_/X 0.20 0.22 -0.02 (VIOLATED)
+_296866_/X 0.20 0.22 -0.02 (VIOLATED)
+_193793_/X 0.20 0.22 -0.02 (VIOLATED)
+_296872_/X 0.20 0.22 -0.02 (VIOLATED)
+_296726_/X 0.20 0.22 -0.02 (VIOLATED)
+_247226_/X 0.20 0.22 -0.02 (VIOLATED)
+_205577_/X 0.20 0.22 -0.02 (VIOLATED)
+_193740_/X 0.20 0.22 -0.02 (VIOLATED)
+_193725_/X 0.20 0.22 -0.02 (VIOLATED)
+_194195_/X 0.20 0.22 -0.02 (VIOLATED)
+_247222_/X 0.20 0.22 -0.02 (VIOLATED)
+_296869_/X 0.20 0.22 -0.02 (VIOLATED)
+_296723_/X 0.20 0.22 -0.02 (VIOLATED)
+_193284_/X 0.20 0.22 -0.02 (VIOLATED)
+_193862_/X 0.20 0.22 -0.02 (VIOLATED)
+_296720_/X 0.20 0.22 -0.02 (VIOLATED)
+_193743_/X 0.20 0.21 -0.02 (VIOLATED)
+_162307_/X 0.20 0.21 -0.02 (VIOLATED)
+_194338_/X 0.20 0.21 -0.01 (VIOLATED)
+_296859_/X 0.20 0.21 -0.01 (VIOLATED)
+_296862_/X 0.20 0.21 -0.01 (VIOLATED)
+_160465_/X 0.20 0.21 -0.01 (VIOLATED)
+_162506_/X 0.20 0.21 -0.01 (VIOLATED)
+_193748_/X 0.20 0.21 -0.01 (VIOLATED)
+_247230_/X 0.20 0.21 -0.01 (VIOLATED)
+_296855_/X 0.20 0.21 -0.01 (VIOLATED)
+_247235_/X 0.20 0.21 -0.01 (VIOLATED)
+_160715_/X 0.20 0.21 -0.01 (VIOLATED)
+_205830_/X 0.20 0.21 -0.01 (VIOLATED)
+_249456_/X 0.20 0.21 -0.01 (VIOLATED)
+_193691_/X 0.20 0.21 -0.01 (VIOLATED)
+_296849_/X 0.20 0.20 -0.01 (VIOLATED)
+_272766_/X 0.20 0.20 -0.01 (VIOLATED)
+_162508_/X 0.20 0.20 -0.00 (VIOLATED)
+_195205_/X 0.20 0.20 -0.00 (VIOLATED)
+_247243_/X 0.20 0.20 -0.00 (VIOLATED)
+_296852_/X 0.20 0.20 -0.00 (VIOLATED)
+_207016_/X 0.20 0.20 -0.00 (VIOLATED)
+_194818_/X 0.20 0.20 -0.00 (VIOLATED)
+_164614_/X 0.20 0.20 -0.00 (VIOLATED)
+_205834_/X 0.20 0.20 -0.00 (VIOLATED)
+_164612_/X 0.20 0.20 -0.00 (VIOLATED)
+_193273_/X 0.20 0.20 -0.00 (VIOLATED)
+
+Capacitance violations: 61
+Transition violations: 1204
+wns -0.99
+tns -5.25
+Initial area: 23602706 um2
+OpenPhySyn timing repair:
+[OpenPhySyn] [2020-12-16 10:57:40.237] [info] Invoking repair_timing transform
+[OpenPhySyn] [2020-12-16 10:57:42.285] [info] Buffer library: sky130_fd_sc_hd__buf_2, sky130_fd_sc_hd__buf_4, sky130_fd_sc_hd__buf_8
+[OpenPhySyn] [2020-12-16 10:57:42.287] [info] Inverter library: None
+[OpenPhySyn] [2020-12-16 10:57:42.288] [info] Buffering: enabled
+[OpenPhySyn] [2020-12-16 10:57:42.288] [info] Driver sizing: enabled
+[OpenPhySyn] [2020-12-16 10:57:42.290] [info] Pin-swapping: enabled
+[OpenPhySyn] [2020-12-16 10:57:42.291] [info] Mode: Timing-Driven
+[OpenPhySyn] [2020-12-16 10:57:42.293] [info] Iteration 1
+[OpenPhySyn] [2020-12-16 11:00:05.393] [info] Runtime: 143s
+[OpenPhySyn] [2020-12-16 11:00:05.393] [info] Buffers: 137
+[OpenPhySyn] [2020-12-16 11:00:05.393] [info] Resize up: 172
+[OpenPhySyn] [2020-12-16 11:00:05.393] [info] Resize down: 0
+[OpenPhySyn] [2020-12-16 11:00:05.393] [info] Pin Swap: 24
+[OpenPhySyn] [2020-12-16 11:00:05.393] [info] Buffered nets: 236
+[OpenPhySyn] [2020-12-16 11:00:05.393] [info] Fanout violations: 0
+[OpenPhySyn] [2020-12-16 11:00:05.393] [info] Transition violations: 1204
+[OpenPhySyn] [2020-12-16 11:00:05.393] [info] Capacitance violations: 61
+[OpenPhySyn] [2020-12-16 11:00:05.393] [info] Slack gain: 6.23824e-08
+[OpenPhySyn] [2020-12-16 11:00:05.393] [info] Initial area: 2360271
+[OpenPhySyn] [2020-12-16 11:00:05.393] [info] New area: 2362439
+[OpenPhySyn] [2020-12-16 11:00:05.393] [info] Finished repair_timing transform (333)
+Added/updated 333 cells
+=============== Final Reports =============
+Startpoint: la_data_in[2] (input port clocked by wb_clk_i)
+Endpoint: _346788_ (recovery check against rising-edge clock wb_clk_i)
+Path Group: **async_default**
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (ideal)
+ 4.00 4.00 v input external delay
+ 0.48 4.48 v la_data_in[2] (in)
+ 0.59 5.07 v _163808_/X (sky130_fd_sc_hd__or2_4)
+ 0.40 5.47 v _163809_/X (sky130_fd_sc_hd__buf_2)
+ 0.39 5.86 v _163810_/X (sky130_fd_sc_hd__buf_2)
+ 0.11 5.97 ^ _163811_/Y (sky130_fd_sc_hd__inv_2)
+ 0.41 6.38 ^ _163812_/X (sky130_fd_sc_hd__buf_2)
+ 0.39 6.77 ^ _163813_/X (sky130_fd_sc_hd__buf_2)
+ 0.57 7.34 ^ _163814_/X (sky130_fd_sc_hd__buf_2)
+ 0.93 8.27 ^ _172814_/X (sky130_fd_sc_hd__buf_2)
+ 0.55 8.82 ^ _172921_/X (sky130_fd_sc_hd__buf_2)
+ 0.20 9.02 ^ _172927_/X (sky130_fd_sc_hd__buf_2)
+ 0.00 9.02 ^ _346788_/SET_B (sky130_fd_sc_hd__dfstp_4)
+ 9.02 data arrival time
+
+ 20.00 20.00 clock wb_clk_i (rise edge)
+ 0.00 20.00 clock network delay (ideal)
+ 0.00 20.00 clock reconvergence pessimism
+ 20.00 ^ _346788_/CLK (sky130_fd_sc_hd__dfstp_4)
+ 0.25 20.25 library recovery time
+ 20.25 data required time
+---------------------------------------------------------
+ 20.25 data required time
+ -9.02 data arrival time
+---------------------------------------------------------
+ 11.22 slack (MET)
+
+
+Startpoint: wbs_adr_i[2] (input port clocked by wb_clk_i)
+Endpoint: _336470_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (ideal)
+ 4.00 4.00 v input external delay
+ 0.16 4.16 v wbs_adr_i[2] (in)
+ 0.81 4.97 v _160705_/X (sky130_fd_sc_hd__a32o_4)
+ 0.45 5.42 ^ _160706_/Y (sky130_fd_sc_hd__inv_2)
+ 0.62 6.04 ^ _162316_/X (sky130_fd_sc_hd__buf_2)
+ 0.73 6.77 ^ _162317_/X (sky130_fd_sc_hd__buf_2)
+ 1.10 7.86 ^ _162318_/X (sky130_fd_sc_hd__buf_2)
+ 1.51 9.38 ^ _162319_/X (sky130_fd_sc_hd__buf_2)
+ 1.35 10.72 ^ _162320_/X (sky130_fd_sc_hd__buf_2)
+ 0.84 11.57 ^ _162321_/X (sky130_fd_sc_hd__buf_2)
+ 0.70 12.27 ^ _162322_/X (sky130_fd_sc_hd__buf_2)
+ 0.38 12.65 ^ _162616_/X (sky130_fd_sc_hd__or4_4)
+ 0.69 13.34 ^ _163118_/X (sky130_fd_sc_hd__buf_2)
+ 1.03 14.38 ^ _205464_/X (sky130_fd_sc_hd__buf_2)
+ 1.17 15.55 ^ _205465_/X (sky130_fd_sc_hd__buf_2)
+ 0.56 16.11 ^ _205892_/X (sky130_fd_sc_hd__or2_4)
+ 0.96 17.07 ^ _205893_/X (sky130_fd_sc_hd__buf_2)
+ 0.56 17.63 v _247364_/Y (sky130_fd_sc_hd__nor2_4)
+ 0.43 18.06 v _247370_/X (sky130_fd_sc_hd__buf_2)
+ 0.38 18.44 v _247373_/X (sky130_fd_sc_hd__a2bb2o_4)
+ 0.00 18.44 v _336470_/D (sky130_fd_sc_hd__dfxtp_4)
+ 18.44 data arrival time
+
+ 20.00 20.00 clock wb_clk_i (rise edge)
+ 0.00 20.00 clock network delay (ideal)
+ 0.00 20.00 clock reconvergence pessimism
+ 20.00 ^ _336470_/CLK (sky130_fd_sc_hd__dfxtp_4)
+ -0.28 19.72 library setup time
+ 19.72 data required time
+---------------------------------------------------------
+ 19.72 data required time
+ -18.44 data arrival time
+---------------------------------------------------------
+ 1.28 slack (MET)
+
+
+max slew
+
+Pin Limit Slew Slack
+------------------------------------------------------------
+_197601_/A 1.50 1.98 -0.48 (VIOLATED)
+_203967_/A 1.50 1.98 -0.48 (VIOLATED)
+_240878_/A 1.50 1.98 -0.48 (VIOLATED)
+_258390_/A 1.50 1.98 -0.48 (VIOLATED)
+_193765_/A 1.50 1.97 -0.47 (VIOLATED)
+_193764_/X 1.51 1.97 -0.46 (VIOLATED)
+_225969_/A 1.50 1.91 -0.41 (VIOLATED)
+_219757_/A 1.50 1.91 -0.41 (VIOLATED)
+_198854_/A 1.50 1.91 -0.41 (VIOLATED)
+_259592_/A 1.50 1.90 -0.40 (VIOLATED)
+_193741_/A 1.50 1.90 -0.40 (VIOLATED)
+_196295_/A 1.50 1.90 -0.40 (VIOLATED)
+_202679_/A 1.50 1.90 -0.40 (VIOLATED)
+_193726_/A 1.50 1.90 -0.40 (VIOLATED)
+_239580_/A 1.50 1.90 -0.40 (VIOLATED)
+_245778_/A 1.50 1.90 -0.40 (VIOLATED)
+_247236_/A 1.50 1.90 -0.40 (VIOLATED)
+_247348_/A 1.50 1.89 -0.39 (VIOLATED)
+_247457_/A 1.50 1.89 -0.39 (VIOLATED)
+_193740_/X 1.51 1.90 -0.39 (VIOLATED)
+_259594_/A 1.50 1.89 -0.39 (VIOLATED)
+_242094_/A 1.50 1.89 -0.39 (VIOLATED)
+_228298_/A 1.50 1.89 -0.39 (VIOLATED)
+_245815_/A 1.50 1.89 -0.39 (VIOLATED)
+_193725_/X 1.51 1.90 -0.39 (VIOLATED)
+_193744_/A 1.50 1.88 -0.38 (VIOLATED)
+_198856_/A 1.50 1.88 -0.38 (VIOLATED)
+_193749_/A 1.50 1.88 -0.38 (VIOLATED)
+_247566_/A 1.50 1.88 -0.38 (VIOLATED)
+_247675_/A 1.50 1.87 -0.37 (VIOLATED)
+_193743_/X 1.51 1.88 -0.37 (VIOLATED)
+_223491_/A 1.50 1.87 -0.37 (VIOLATED)
+_202688_/A 1.50 1.87 -0.37 (VIOLATED)
+_196304_/A 1.50 1.87 -0.37 (VIOLATED)
+_247235_/X 1.51 1.87 -0.36 (VIOLATED)
+_193748_/X 1.51 1.87 -0.36 (VIOLATED)
+_163115_/A 1.50 1.85 -0.35 (VIOLATED)
+_193691_/A 1.50 1.85 -0.35 (VIOLATED)
+_162509_/A 1.50 1.85 -0.35 (VIOLATED)
+_266315_/A 1.50 1.82 -0.32 (VIOLATED)
+_267342_/A 1.50 1.82 -0.32 (VIOLATED)
+_162508_/X 1.51 1.82 -0.31 (VIOLATED)
+_193660_/A 1.50 1.78 -0.28 (VIOLATED)
+_162320_/A 1.50 1.78 -0.28 (VIOLATED)
+_193373_/A 1.50 1.78 -0.28 (VIOLATED)
+_162921_/B 1.50 1.77 -0.27 (VIOLATED)
+_243513_/A 1.50 1.76 -0.26 (VIOLATED)
+_261008_/A 1.50 1.76 -0.26 (VIOLATED)
+_193274_/A 1.50 1.76 -0.26 (VIOLATED)
+_220807_/A 1.50 1.75 -0.25 (VIOLATED)
+_199931_/A 1.50 1.75 -0.25 (VIOLATED)
+_267319_/B 1.50 1.75 -0.25 (VIOLATED)
+_193273_/X 1.51 1.75 -0.24 (VIOLATED)
+_162319_/X 1.51 1.75 -0.24 (VIOLATED)
+_225708_/A 1.50 1.74 -0.24 (VIOLATED)
+_201154_/A 1.50 1.74 -0.24 (VIOLATED)
+_193100_/A 1.50 1.73 -0.23 (VIOLATED)
+_199979_/A 1.50 1.73 -0.23 (VIOLATED)
+_193761_/A 1.50 1.71 -0.21 (VIOLATED)
+_193099_/X 1.51 1.71 -0.20 (VIOLATED)
+_267398_/B 1.50 1.67 -0.17 (VIOLATED)
+_267338_/B 1.50 1.67 -0.17 (VIOLATED)
+_267386_/B 1.50 1.67 -0.17 (VIOLATED)
+_200631_/A 1.50 1.67 -0.17 (VIOLATED)
+_194950_/A 1.50 1.67 -0.17 (VIOLATED)
+_194949_/X 1.51 1.67 -0.16 (VIOLATED)
+_198531_/A 1.50 1.61 -0.11 (VIOLATED)
+_194173_/A 1.50 1.61 -0.11 (VIOLATED)
+_193909_/A 1.50 1.61 -0.11 (VIOLATED)
+_193819_/A 1.50 1.61 -0.11 (VIOLATED)
+_195979_/A 1.50 1.60 -0.10 (VIOLATED)
+_193818_/X 1.51 1.60 -0.09 (VIOLATED)
+_193609_/A 1.50 1.59 -0.09 (VIOLATED)
+_193312_/A 1.50 1.59 -0.09 (VIOLATED)
+_203718_/A 1.50 1.59 -0.09 (VIOLATED)
+_194790_/A 1.50 1.59 -0.09 (VIOLATED)
+_193196_/A 1.50 1.59 -0.09 (VIOLATED)
+_193195_/X 1.51 1.59 -0.08 (VIOLATED)
+_201848_/A 1.50 1.58 -0.08 (VIOLATED)
+_194776_/A 1.50 1.58 -0.08 (VIOLATED)
+_196830_/A 1.50 1.57 -0.07 (VIOLATED)
+_194953_/A 1.50 1.57 -0.07 (VIOLATED)
+_195149_/A 1.50 1.57 -0.07 (VIOLATED)
+_291120_/A 1.50 1.57 -0.07 (VIOLATED)
+_186551_/A 1.50 1.57 -0.07 (VIOLATED)
+_194775_/X 1.51 1.57 -0.06 (VIOLATED)
+_240282_/A 1.50 1.56 -0.06 (VIOLATED)
+_246473_/A 1.50 1.56 -0.06 (VIOLATED)
+_227786_/A 1.50 1.56 -0.06 (VIOLATED)
+_241589_/A 1.50 1.56 -0.06 (VIOLATED)
+_259094_/A 1.50 1.56 -0.06 (VIOLATED)
+_196887_/A 1.50 1.55 -0.05 (VIOLATED)
+_203268_/A 1.50 1.55 -0.05 (VIOLATED)
+_195156_/A 1.50 1.55 -0.05 (VIOLATED)
+_196687_/A 1.50 1.55 -0.05 (VIOLATED)
+_194660_/A 1.50 1.55 -0.05 (VIOLATED)
+_195155_/X 1.51 1.55 -0.04 (VIOLATED)
+_194659_/X 1.51 1.55 -0.04 (VIOLATED)
+_178875_/A 1.50 1.54 -0.04 (VIOLATED)
+_280589_/A 1.50 1.53 -0.03 (VIOLATED)
+_186545_/A 1.50 1.52 -0.02 (VIOLATED)
+_291114_/A 1.50 1.52 -0.02 (VIOLATED)
+_301013_/A 1.50 1.51 -0.01 (VIOLATED)
+_291141_/A 1.50 1.51 -0.01 (VIOLATED)
+_291136_/A 1.50 1.51 -0.01 (VIOLATED)
+_174139_/A 1.50 1.50 -0.00 (VIOLATED)
+_164158_/A 1.50 1.50 -0.00 (VIOLATED)
+
+max capacitance
+
+Pin Limit Cap Slack
+------------------------------------------------------------
+_193764_/X 0.20 0.23 -0.03 (VIOLATED)
+_193740_/X 0.20 0.22 -0.02 (VIOLATED)
+_193725_/X 0.20 0.22 -0.02 (VIOLATED)
+_193743_/X 0.20 0.22 -0.02 (VIOLATED)
+_193748_/X 0.20 0.21 -0.01 (VIOLATED)
+_247235_/X 0.20 0.21 -0.01 (VIOLATED)
+_162508_/X 0.20 0.20 -0.01 (VIOLATED)
+_193273_/X 0.20 0.20 -0.00 (VIOLATED)
+
+Capacitance violations: 8
+Transition violations: 107
+wns 0.00
+tns 0.00
+Final area: 23624386 um2
+Export optimized design
diff --git a/openlane/user_proj_example/results/logs/placement/openphysyn_runtime.txt b/openlane/user_proj_example/results/logs/placement/openphysyn_runtime.txt
new file mode 100644
index 0000000..28aa184
--- /dev/null
+++ b/openlane/user_proj_example/results/logs/placement/openphysyn_runtime.txt
@@ -0,0 +1 @@
+0h3m31s347ms
diff --git a/openlane/user_proj_example/results/logs/placement/replace.log b/openlane/user_proj_example/results/logs/placement/replace.log
new file mode 100644
index 0000000..24946d2
--- /dev/null
+++ b/openlane/user_proj_example/results/logs/placement/replace.log
@@ -0,0 +1,151 @@
+OpenROAD 0.9.0 d03ebfc244
+This program is licensed under the BSD-3 license. See the LICENSE file for details.
+Components of this program may be licensed under more restrictive licenses which must be honored.
+Error: cannot open '/.openroad'.
+Notice 0: Reading LEF file: /project/openlane/user_proj_example/runs/16-12_10-43/tmp/merged_unpadded.lef
+Notice 0: Created 13 technology layers
+Notice 0: Created 25 technology vias
+Notice 0: Created 438 library cells
+Notice 0: Finished LEF file: /project/openlane/user_proj_example/runs/16-12_10-43/tmp/merged_unpadded.lef
+Notice 0:
+Reading DEF file: /project/openlane/user_proj_example/runs/16-12_10-43/tmp/floorplan/pdn.def
+Notice 0: Design: user_proj_example
+Notice 0: Created 100000 Insts
+Notice 0: Created 200000 Insts
+Notice 0: Created 100000 Nets
+Notice 0: Created 606 pins.
+Notice 0: Created 289855 components and 1555004 component-terminals.
+Notice 0: Created 2 special nets and 0 connections.
+Notice 0: Created 187696 nets and 596035 connections.
+Notice 0: Finished DEF file: /project/openlane/user_proj_example/runs/16-12_10-43/tmp/floorplan/pdn.def
+[INFO] DBU = 1000
+[INFO] SiteSize = (460, 2720)
+[INFO] CoreAreaLxLy = (5520, 10880)
+[INFO] CoreAreaUxUy = (2494120, 3087200)
+[INFO] NumInstances = 289855
+[INFO] NumPlaceInstances = 187329
+[INFO] NumFixedInstances = 102526
+[INFO] NumDummyInstances = 0
+[INFO] NumNets = 187696
+[INFO] NumPins = 596639
+[INFO] DieAreaLxLy = (0, 0)
+[INFO] DieAreaUxUy = (2500000, 3100000)
+[INFO] CoreAreaLxLy = (5520, 10880)
+[INFO] CoreAreaUxUy = (2494120, 3087200)
+[INFO] CoreArea = 7655729952000
+[INFO] NonPlaceInstsArea = 133940960000
+[INFO] PlaceInstsArea = 2214343731200
+[INFO] Util(%) = 29.439056
+[INFO] StdInstsArea = 2214343731200
+[INFO] MacroInstsArea = 0
+[InitialPlace] Iter: 1 CG Error: 0.00262755 HPWL: 2398295010
+[InitialPlace] Iter: 2 CG Error: 0.00010348 HPWL: 2453047977
+[InitialPlace] Iter: 3 CG Error: 3.15599e-05 HPWL: 2462446827
+[InitialPlace] Iter: 4 CG Error: 2.97316e-05 HPWL: 2458835582
+[InitialPlace] Iter: 5 CG Error: 0.00124914 HPWL: 2452395171
+[InitialPlace] Iter: 6 CG Error: 4.6744e-05 HPWL: 2461983826
+[InitialPlace] Iter: 7 CG Error: 2.38737e-05 HPWL: 2445668111
+[InitialPlace] Iter: 8 CG Error: 2.85405e-05 HPWL: 2444511420
+[InitialPlace] Iter: 9 CG Error: 4.57619e-05 HPWL: 2444155974
+[InitialPlace] Iter: 10 CG Error: 3.21273e-05 HPWL: 2444307270
+[InitialPlace] Iter: 11 CG Error: 4.00076e-05 HPWL: 2444072878
+[InitialPlace] Iter: 12 CG Error: 5.21517e-05 HPWL: 2444295148
+[InitialPlace] Iter: 13 CG Error: 4.41386e-05 HPWL: 2444196266
+[InitialPlace] Iter: 14 CG Error: 3.60662e-05 HPWL: 2444132323
+[InitialPlace] Iter: 15 CG Error: 3.51615e-05 HPWL: 2444006313
+[InitialPlace] Iter: 16 CG Error: 2.77687e-05 HPWL: 2443993286
+[InitialPlace] Iter: 17 CG Error: 3.05805e-05 HPWL: 2443752700
+[InitialPlace] Iter: 18 CG Error: 3.23555e-05 HPWL: 2443855921
+[InitialPlace] Iter: 19 CG Error: 3.79422e-05 HPWL: 2443557132
+[InitialPlace] Iter: 20 CG Error: 3.38399e-05 HPWL: 2443760645
+[INFO] FillerInit: NumGCells = 242915
+[INFO] FillerInit: NumGNets = 187696
+[INFO] FillerInit: NumGPins = 596639
+[INFO] TargetDensity = 0.380000
+[INFO] AveragePlaceInstArea = 11820613
+[INFO] IdealBinArea = 31106876
+[INFO] IdealBinCnt = 246110
+[INFO] TotalBinArea = 7655729952000
+[INFO] BinCnt = (256, 256)
+[INFO] BinSize = (9722, 12017)
+[INFO] NumBins = 65536
+[NesterovSolve] Iter: 1 overflow: 0.997945 HPWL: 991922369
+[NesterovSolve] Iter: 10 overflow: 0.992548 HPWL: 1395079573
+[NesterovSolve] Iter: 20 overflow: 0.988938 HPWL: 1586827183
+[NesterovSolve] Iter: 30 overflow: 0.987115 HPWL: 1686194197
+[NesterovSolve] Iter: 40 overflow: 0.986603 HPWL: 1720768832
+[NesterovSolve] Iter: 50 overflow: 0.986512 HPWL: 1743489074
+[NesterovSolve] Iter: 60 overflow: 0.986471 HPWL: 1768552415
+[NesterovSolve] Iter: 70 overflow: 0.986426 HPWL: 1790009166
+[NesterovSolve] Iter: 80 overflow: 0.986481 HPWL: 1803076806
+[NesterovSolve] Iter: 90 overflow: 0.986634 HPWL: 1801815667
+[NesterovSolve] Iter: 100 overflow: 0.986787 HPWL: 1791658817
+[NesterovSolve] Iter: 110 overflow: 0.98688 HPWL: 1781923083
+[NesterovSolve] Iter: 120 overflow: 0.9869 HPWL: 1776390835
+[NesterovSolve] Iter: 130 overflow: 0.986929 HPWL: 1775292380
+[NesterovSolve] Iter: 140 overflow: 0.986955 HPWL: 1777722532
+[NesterovSolve] Iter: 150 overflow: 0.986956 HPWL: 1783722936
+[NesterovSolve] Iter: 160 overflow: 0.987013 HPWL: 1796235382
+[NesterovSolve] Iter: 170 overflow: 0.986979 HPWL: 1819307533
+[NesterovSolve] Iter: 180 overflow: 0.986926 HPWL: 1857607273
+[NesterovSolve] Iter: 190 overflow: 0.986688 HPWL: 1916412651
+[NesterovSolve] Iter: 200 overflow: 0.985925 HPWL: 2010232812
+[NesterovSolve] Iter: 210 overflow: 0.984625 HPWL: 2150534515
+[NesterovSolve] Iter: 220 overflow: 0.982036 HPWL: 2335248822
+[NesterovSolve] Iter: 230 overflow: 0.977614 HPWL: 2562690993
+[NesterovSolve] Iter: 240 overflow: 0.971308 HPWL: 2849174467
+[NesterovSolve] Iter: 250 overflow: 0.962997 HPWL: 3230095604
+[NesterovSolve] Iter: 260 overflow: 0.951454 HPWL: 3725385437
+[NesterovSolve] Iter: 270 overflow: 0.938451 HPWL: 4338009810
+[NesterovSolve] Iter: 280 overflow: 0.923247 HPWL: 5077232306
+[NesterovSolve] Iter: 290 overflow: 0.905186 HPWL: 5879216191
+[NesterovSolve] Iter: 300 overflow: 0.885053 HPWL: 6608596786
+[NesterovSolve] Iter: 310 overflow: 0.859596 HPWL: 7301107440
+[NesterovSolve] Iter: 320 overflow: 0.830887 HPWL: 7961130902
+[NesterovSolve] Iter: 330 overflow: 0.800265 HPWL: 8645195415
+[NesterovSolve] Iter: 340 overflow: 0.768785 HPWL: 9487031008
+[NesterovSolve] Iter: 350 overflow: 0.734815 HPWL: 10187154629
+[NesterovSolve] Iter: 360 overflow: 0.695456 HPWL: 10243640748
+[NesterovSolve] Iter: 370 overflow: 0.646592 HPWL: 10700185923
+[NesterovSolve] Iter: 380 overflow: 0.607814 HPWL: 11377701480
+[NesterovSolve] Iter: 390 overflow: 0.568534 HPWL: 11766780460
+[NesterovSolve] Iter: 400 overflow: 0.524274 HPWL: 11558452642
+[NesterovSolve] Iter: 410 overflow: 0.482033 HPWL: 11910191673
+[NesterovSolve] Iter: 420 overflow: 0.44124 HPWL: 11708421973
+[NesterovSolve] Iter: 430 overflow: 0.395478 HPWL: 11977717593
+[NesterovSolve] Iter: 440 overflow: 0.363463 HPWL: 11922575003
+[NesterovSolve] Iter: 450 overflow: 0.327177 HPWL: 11871708564
+[NesterovSolve] Iter: 460 overflow: 0.301419 HPWL: 11704884673
+[NesterovSolve] Iter: 470 overflow: 0.275018 HPWL: 11630862523
+[NesterovSolve] Iter: 480 overflow: 0.248225 HPWL: 11555734408
+[NesterovSolve] Iter: 490 overflow: 0.221669 HPWL: 11521209411
+[NesterovSolve] Iter: 500 overflow: 0.194028 HPWL: 11484567773
+[NesterovSolve] Iter: 510 overflow: 0.169144 HPWL: 11457140232
+[NesterovSolve] Iter: 520 overflow: 0.146261 HPWL: 11440360286
+[NesterovSolve] Iter: 530 overflow: 0.125302 HPWL: 11429437252
+[NesterovSolve] Iter: 540 overflow: 0.106547 HPWL: 11420932923
+[NesterovSolve] Finished with Overflow: 0.0995692
+Warning: /mnt/data/workspace/pdk/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_100C_1v60.lib, line 32 default_operating_condition ss_100C_1v60 not found.
+Warning: /mnt/data/workspace/pdk/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_n40C_1v95.lib, line 31 default_operating_condition ff_n40C_1v95 not found.
+create_clock [get_ports $::env(CLOCK_PORT)] -name $::env(CLOCK_PORT) -period $::env(CLOCK_PERIOD)
+set input_delay_value [expr $::env(CLOCK_PERIOD) * $::env(IO_PCT)]
+set output_delay_value [expr $::env(CLOCK_PERIOD) * $::env(IO_PCT)]
+puts "\[INFO\]: Setting output delay to: $output_delay_value"
+[INFO]: Setting output delay to: 4.0
+puts "\[INFO\]: Setting input delay to: $input_delay_value"
+[INFO]: Setting input delay to: 4.0
+set clk_indx [lsearch [all_inputs] [get_port $::env(CLOCK_PORT)]]
+#set rst_indx [lsearch [all_inputs] [get_port resetn]]
+set all_inputs_wo_clk [lreplace [all_inputs] $clk_indx $clk_indx]
+#set all_inputs_wo_clk_rst [lreplace $all_inputs_wo_clk $rst_indx $rst_indx]
+set all_inputs_wo_clk_rst $all_inputs_wo_clk
+# correct resetn
+set_input_delay $input_delay_value -clock [get_clocks $::env(CLOCK_PORT)] $all_inputs_wo_clk_rst
+#set_input_delay 0.0 -clock [get_clocks $::env(CLOCK_PORT)] {resetn}
+set_output_delay $output_delay_value -clock [get_clocks $::env(CLOCK_PORT)] [all_outputs]
+# TODO set this as parameter
+set_driving_cell -lib_cell $::env(SYNTH_DRIVING_CELL) -pin $::env(SYNTH_DRIVING_CELL_PIN) [all_inputs]
+set cap_load [expr $::env(SYNTH_CAP_LOAD) / 1000.0]
+puts "\[INFO\]: Setting load to: $cap_load"
+[INFO]: Setting load to: 0.01765
+set_load $cap_load [all_outputs]
diff --git a/openlane/user_proj_example/results/logs/placement/replace_runtime.txt b/openlane/user_proj_example/results/logs/placement/replace_runtime.txt
new file mode 100644
index 0000000..84192a4
--- /dev/null
+++ b/openlane/user_proj_example/results/logs/placement/replace_runtime.txt
@@ -0,0 +1 @@
+0h3m7s856ms
diff --git a/openlane/user_proj_example/results/logs/routing/addspacers.log b/openlane/user_proj_example/results/logs/routing/addspacers.log
new file mode 100644
index 0000000..818e16f
--- /dev/null
+++ b/openlane/user_proj_example/results/logs/routing/addspacers.log
@@ -0,0 +1,23 @@
+OpenROAD 0.9.0 d03ebfc244
+This program is licensed under the BSD-3 license. See the LICENSE file for details.
+Components of this program may be licensed under more restrictive licenses which must be honored.
+Error: cannot open '/.openroad'.
+Notice 0: Reading LEF file: /project/openlane/user_proj_example/runs/16-12_10-43/tmp/merged_unpadded.lef
+Notice 0: Created 13 technology layers
+Notice 0: Created 25 technology vias
+Notice 0: Created 438 library cells
+Notice 0: Finished LEF file: /project/openlane/user_proj_example/runs/16-12_10-43/tmp/merged_unpadded.lef
+Notice 0:
+Reading DEF file: /project/openlane/user_proj_example/runs/16-12_10-43/tmp/routing/fastroute.def
+Notice 0: Design: user_proj_example
+Notice 0: Created 100000 Insts
+Notice 0: Created 200000 Insts
+Notice 0: Created 300000 Insts
+Notice 0: Created 400000 Insts
+Notice 0: Created 100000 Nets
+Notice 0: Created 606 pins.
+Notice 0: Created 420720 components and 2213772 component-terminals.
+Notice 0: Created 2 special nets and 0 connections.
+Notice 0: Created 192139 nets and 731343 connections.
+Notice 0: Finished DEF file: /project/openlane/user_proj_example/runs/16-12_10-43/tmp/routing/fastroute.def
+Placed 506770 filler instances.
diff --git a/openlane/user_proj_example/results/logs/routing/addspacers_runtime.txt b/openlane/user_proj_example/results/logs/routing/addspacers_runtime.txt
new file mode 100644
index 0000000..1a9925e
--- /dev/null
+++ b/openlane/user_proj_example/results/logs/routing/addspacers_runtime.txt
@@ -0,0 +1 @@
+0h0m10s138ms
diff --git a/openlane/user_proj_example/results/logs/routing/fastroute.log b/openlane/user_proj_example/results/logs/routing/fastroute.log
new file mode 100644
index 0000000..c2bd93c
--- /dev/null
+++ b/openlane/user_proj_example/results/logs/routing/fastroute.log
@@ -0,0 +1,217 @@
+OpenROAD 0.9.0 d03ebfc244
+This program is licensed under the BSD-3 license. See the LICENSE file for details.
+Components of this program may be licensed under more restrictive licenses which must be honored.
+Error: cannot open '/.openroad'.
+Warning: /mnt/data/workspace/pdk/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib, line 31 default_operating_condition tt_025C_1v80 not found.
+Notice 0: Reading LEF file: /project/openlane/user_proj_example/runs/16-12_10-43/tmp/merged_unpadded.lef
+Notice 0: Created 13 technology layers
+Notice 0: Created 25 technology vias
+Notice 0: Created 438 library cells
+Notice 0: Finished LEF file: /project/openlane/user_proj_example/runs/16-12_10-43/tmp/merged_unpadded.lef
+Notice 0:
+Reading DEF file: /project/openlane/user_proj_example/runs/16-12_10-43/results/placement/user_proj_example.placement.def
+Notice 0: Design: user_proj_example
+Notice 0: Created 100000 Insts
+Notice 0: Created 200000 Insts
+Notice 0: Created 300000 Insts
+Notice 0: Created 400000 Insts
+Notice 0: Created 100000 Nets
+Notice 0: Created 606 pins.
+Notice 0: Created 420720 components and 2213772 component-terminals.
+Notice 0: Created 2 special nets and 0 connections.
+Notice 0: Created 192139 nets and 731343 connections.
+Notice 0: Finished DEF file: /project/openlane/user_proj_example/runs/16-12_10-43/results/placement/user_proj_example.placement.def
+[PARAMS] Min routing layer: 2
+[PARAMS] Max routing layer: 5
+[PARAMS] Global adjustment: 0
+[PARAMS] Unidirectional routing: 1
+[PARAMS] Grid origin: (-1, -1)
+[INFO] #DB Obstructions: 0
+[INFO] #DB Obstacles: 10383302
+[INFO] #DB Macros: 0
+[INFO] Found 0 clock nets
+[INFO] Minimum degree: 2
+[INFO] Maximum degree: 91
+[INFO] Processing 7357819 obstacles on layer 1
+[INFO] Processing 1344048 obstacles on layer 2
+[INFO] Processing 33 obstacles on layer 5
+[INFO] Reducing resources of layer 1 by 99%
+[INFO] WIRELEN : 1950149, WIRELEN1 : 0
+[INFO] NumSeg : 452832
+[INFO] NumShift: 0
+First L Route
+[INFO] WIRELEN : 1954567, WIRELEN1 : 1954567
+[INFO] NumSeg : 451716
+[INFO] NumShift: 13309
+[Overflow Report] Total hCap : 4187241
+[Overflow Report] Total vCap : 3555840
+[Overflow Report] Total Usage : 1954567
+[Overflow Report] Max H Overflow: 0
+[Overflow Report] Max V Overflow: 5
+[Overflow Report] Max Overflow : 5
+[Overflow Report] Num Overflow e: 87
+[Overflow Report] H Overflow : 0
+[Overflow Report] V Overflow : 159
+[Overflow Report] Final Overflow: 159
+
+Second L Route
+[Overflow Report] Total hCap : 4187241
+[Overflow Report] Total vCap : 3555840
+[Overflow Report] Total Usage : 1954567
+[Overflow Report] Max H Overflow: 0
+[Overflow Report] Max V Overflow: 3
+[Overflow Report] Max Overflow : 3
+[Overflow Report] Num Overflow e: 71
+[Overflow Report] H Overflow : 0
+[Overflow Report] V Overflow : 103
+[Overflow Report] Final Overflow: 103
+
+First Z Route
+[Overflow Report] Total hCap : 4187241
+[Overflow Report] Total vCap : 3555840
+[Overflow Report] Total Usage : 1954567
+[Overflow Report] Max H Overflow: 0
+[Overflow Report] Max V Overflow: 3
+[Overflow Report] Max Overflow : 3
+[Overflow Report] Num Overflow e: 56
+[Overflow Report] H Overflow : 0
+[Overflow Report] V Overflow : 80
+[Overflow Report] Final Overflow: 80
+
+[INFO] LV routing round 0, enlarge 10
+[INFO] 10 threshold, 10 expand
+[Overflow Report] total Usage : 1954567
+[Overflow Report] Max H Overflow: 0
+[Overflow Report] Max V Overflow: 3
+[Overflow Report] Max Overflow : 3
+[Overflow Report] Num Overflow e: 52
+[Overflow Report] H Overflow : 0
+[Overflow Report] V Overflow : 76
+[Overflow Report] Final Overflow: 76
+
+[INFO] LV routing round 1, enlarge 15
+[INFO] 5 threshold, 15 expand
+[Overflow Report] total Usage : 1954567
+[Overflow Report] Max H Overflow: 0
+[Overflow Report] Max V Overflow: 3
+[Overflow Report] Max Overflow : 3
+[Overflow Report] Num Overflow e: 48
+[Overflow Report] H Overflow : 0
+[Overflow Report] V Overflow : 70
+[Overflow Report] Final Overflow: 70
+
+[INFO] LV routing round 2, enlarge 20
+[INFO] 1 threshold, 20 expand
+[Overflow Report] total Usage : 1954567
+[Overflow Report] Max H Overflow: 0
+[Overflow Report] Max V Overflow: 3
+[Overflow Report] Max Overflow : 3
+[Overflow Report] Num Overflow e: 46
+[Overflow Report] H Overflow : 0
+[Overflow Report] V Overflow : 66
+[Overflow Report] Final Overflow: 66
+
+Running extra iterations to remove overflow...
+Update congestion history type 1
+[INFO] iteration 1, enlarge 20, costheight 9, threshold 10 via cost 2
+[INFO] log_coef 0.953011, healingTrigger 0 cost_step 5 L 1 cost_type 1 updatetype 1
+[Overflow Report] total Usage : 1954676
+[Overflow Report] Max H Overflow: 0
+[Overflow Report] Max V Overflow: 0
+[Overflow Report] Max Overflow : 0
+[Overflow Report] Num Overflow e: 0
+[Overflow Report] H Overflow : 0
+[Overflow Report] V Overflow : 0
+[Overflow Report] Final Overflow: 0
+
+Usage checked
+Maze routing finished
+[INFO] P3 runtime: 0.160000 sec
+[INFO] Final 2D results:
+[Overflow Report] total Usage : 1954676
+[Overflow Report] Max H Overflow: 0
+[Overflow Report] Max V Overflow: 0
+[Overflow Report] Max Overflow : 0
+[Overflow Report] Num Overflow e: 0
+[Overflow Report] H Overflow : 0
+[Overflow Report] V Overflow : 0
+[Overflow Report] Final Overflow: 0
+
+Layer Assignment Begins
+Layer assignment finished
+[INFO] 2D + Layer Assignment Runtime: 10.170000 sec
+Post Processing Begins
+Post Processsing finished
+ Starting via filling
+[INFO] Via related to pin nodes 889476
+[INFO] Via related stiner nodes 43554
+Via filling finished
+
+Final usage/overflow report:
+[INFO] Usage per layer:
+ Layer 1 usage: 0
+ Layer 2 usage: 767587
+ Layer 3 usage: 1061300
+ Layer 4 usage: 22151
+ Layer 5 usage: 106969
+
+[INFO] Capacity per layer:
+ Layer 1 capacity: 0
+ Layer 2 capacity: 2565990
+ Layer 3 capacity: 2433984
+ Layer 4 capacity: 1621251
+ Layer 5 capacity: 1121856
+
+[INFO] Use percentage per layer:
+ Layer 1 use percentage: 0.0%
+ Layer 2 use percentage: 29.91%
+ Layer 3 use percentage: 43.60%
+ Layer 4 use percentage: 1.37%
+ Layer 5 use percentage: 9.54%
+
+[INFO] Overflow per layer:
+ Layer 1 overflow: 0
+ Layer 2 overflow: 0
+ Layer 3 overflow: 0
+ Layer 4 overflow: 0
+ Layer 5 overflow: 0
+
+[Overflow Report] Total Usage : 1958007
+[Overflow Report] Total Capacity: 7743081
+[Overflow Report] Max H Overflow: 0
+[Overflow Report] Max V Overflow: 0
+[Overflow Report] Max Overflow : 0
+[Overflow Report] H Overflow : 0
+[Overflow Report] V Overflow : 0
+[Overflow Report] Final Overflow: 0
+
+[INFO] Final usage : 1958007
+[INFO] Final number of vias : 1047078
+[INFO] Final usage 3D : 5099241
+[INFO] Total wirelength: 17425763 um
+[INFO] Num routed nets: 191881
+Warning: /mnt/data/workspace/pdk/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_100C_1v60.lib, line 32 default_operating_condition ss_100C_1v60 not found.
+Warning: /mnt/data/workspace/pdk/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_n40C_1v95.lib, line 31 default_operating_condition ff_n40C_1v95 not found.
+create_clock [get_ports $::env(CLOCK_PORT)] -name $::env(CLOCK_PORT) -period $::env(CLOCK_PERIOD)
+set input_delay_value [expr $::env(CLOCK_PERIOD) * $::env(IO_PCT)]
+set output_delay_value [expr $::env(CLOCK_PERIOD) * $::env(IO_PCT)]
+puts "\[INFO\]: Setting output delay to: $output_delay_value"
+[INFO]: Setting output delay to: 4.0
+puts "\[INFO\]: Setting input delay to: $input_delay_value"
+[INFO]: Setting input delay to: 4.0
+set clk_indx [lsearch [all_inputs] [get_port $::env(CLOCK_PORT)]]
+#set rst_indx [lsearch [all_inputs] [get_port resetn]]
+set all_inputs_wo_clk [lreplace [all_inputs] $clk_indx $clk_indx]
+#set all_inputs_wo_clk_rst [lreplace $all_inputs_wo_clk $rst_indx $rst_indx]
+set all_inputs_wo_clk_rst $all_inputs_wo_clk
+# correct resetn
+set_input_delay $input_delay_value -clock [get_clocks $::env(CLOCK_PORT)] $all_inputs_wo_clk_rst
+#set_input_delay 0.0 -clock [get_clocks $::env(CLOCK_PORT)] {resetn}
+set_output_delay $output_delay_value -clock [get_clocks $::env(CLOCK_PORT)] [all_outputs]
+# TODO set this as parameter
+set_driving_cell -lib_cell $::env(SYNTH_DRIVING_CELL) -pin $::env(SYNTH_DRIVING_CELL_PIN) [all_inputs]
+set cap_load [expr $::env(SYNTH_CAP_LOAD) / 1000.0]
+puts "\[INFO\]: Setting load to: $cap_load"
+[INFO]: Setting load to: 0.01765
+set_load $cap_load [all_outputs]
+Warning: missing route to pin _347570_/RESET_B
diff --git a/openlane/user_proj_example/results/logs/routing/fastroute_runtime.txt b/openlane/user_proj_example/results/logs/routing/fastroute_runtime.txt
new file mode 100644
index 0000000..8639eec
--- /dev/null
+++ b/openlane/user_proj_example/results/logs/routing/fastroute_runtime.txt
@@ -0,0 +1 @@
+0h1m23s850ms
diff --git a/openlane/user_proj_example/results/logs/routing/or_antenna.log b/openlane/user_proj_example/results/logs/routing/or_antenna.log
new file mode 100644
index 0000000..7c480fc
--- /dev/null
+++ b/openlane/user_proj_example/results/logs/routing/or_antenna.log
@@ -0,0 +1,31 @@
+OpenROAD 0.9.0 d03ebfc244
+This program is licensed under the BSD-3 license. See the LICENSE file for details.
+Components of this program may be licensed under more restrictive licenses which must be honored.
+Error: cannot open '/.openroad'.
+Notice 0: Reading LEF file: /project/openlane/user_proj_example/runs/16-12_10-43/tmp/merged_unpadded.lef
+Notice 0: Created 13 technology layers
+Notice 0: Created 25 technology vias
+Notice 0: Created 439 library cells
+Notice 0: Finished LEF file: /project/openlane/user_proj_example/runs/16-12_10-43/tmp/merged_unpadded.lef
+Notice 0:
+Reading DEF file: /project/openlane/user_proj_example/runs/16-12_10-43/results/routing/user_proj_example.def
+Notice 0: Design: user_proj_example
+Notice 0: Created 100000 Insts
+Notice 0: Created 200000 Insts
+Notice 0: Created 300000 Insts
+Notice 0: Created 400000 Insts
+Notice 0: Created 500000 Insts
+Notice 0: Created 600000 Insts
+Notice 0: Created 700000 Insts
+Notice 0: Created 800000 Insts
+Notice 0: Created 900000 Insts
+Notice 0: Created 100000 Nets
+Notice 0: Created 606 pins.
+Notice 0: Created 927491 components and 4240852 component-terminals.
+Notice 0: Created 2 special nets and 0 connections.
+Notice 0: Created 192139 nets and 731343 connections.
+Notice 0: Finished DEF file: /project/openlane/user_proj_example/runs/16-12_10-43/results/routing/user_proj_example.def
+Notice 0: Split top of 65162 T shapes.
+Number of pins violated: 17
+Number of nets violated: 12
+Total number of nets: 192139
diff --git a/openlane/user_proj_example/results/logs/routing/spef_extraction.log b/openlane/user_proj_example/results/logs/routing/spef_extraction.log
new file mode 100644
index 0000000..76b87ef
--- /dev/null
+++ b/openlane/user_proj_example/results/logs/routing/spef_extraction.log
@@ -0,0 +1,12 @@
+Start parsing LEF file...
+Parsing LEF file done.
+Start parsing DEF file...
+Parsing DEF file done.
+
+Parameters Used:
+Edge Capacitance Factor: 1.0
+Wire model: L
+
+RC Extraction is done
+Start writing SPEF file
+Writing SPEF is done
diff --git a/openlane/user_proj_example/results/logs/routing/tritonRoute.log b/openlane/user_proj_example/results/logs/routing/tritonRoute.log
new file mode 100644
index 0000000..04ff593
--- /dev/null
+++ b/openlane/user_proj_example/results/logs/routing/tritonRoute.log
@@ -0,0 +1,2745 @@
+
+reading lef ...
+
+units: 1000
+#layers: 13
+#macros: 439
+#vias: 25
+#viarulegen: 25
+
+reading def ...
+defIn read 10000 components
+defIn read 20000 components
+defIn read 30000 components
+defIn read 40000 components
+defIn read 50000 components
+defIn read 60000 components
+defIn read 70000 components
+defIn read 80000 components
+defIn read 90000 components
+defIn read 100000 components
+defIn read 200000 components
+defIn read 300000 components
+defIn read 400000 components
+defIn read 500000 components
+defIn read 600000 components
+defIn read 700000 components
+defIn read 800000 components
+defIn read 900000 components
+defIn read 10000 nets
+defIn read 20000 nets
+defIn read 30000 nets
+defIn read 40000 nets
+defIn read 50000 nets
+defIn read 60000 nets
+defIn read 70000 nets
+defIn read 80000 nets
+defIn read 90000 nets
+defIn read 100000 nets
+
+design: user_proj_example
+die area: ( 0 0 ) ( 2500000 3100000 )
+trackPts: 12
+defvias: 3
+#components: 927491
+#terminals: 606
+#snets: 2
+#nets: 192139
+
+reading guide ...
+guideIn read 100000 guides
+guideIn read 200000 guides
+guideIn read 300000 guides
+guideIn read 400000 guides
+guideIn read 500000 guides
+guideIn read 600000 guides
+guideIn read 700000 guides
+guideIn read 800000 guides
+guideIn read 900000 guides
+guideIn read 1000000 guides
+
+#guides: 1491158
+Warning: met2 does not have viaDef align with layer direction, generating new viaDef via2_FR...
+Warning: met4 does not have viaDef align with layer direction, generating new viaDef via4_FR...
+done initConstraintLayerIdx
+List of default vias:
+ Layer mcon
+ default via: L1M1_PR_MR
+ Layer via
+ default via: M1M2_PR
+ Layer via2
+ default via: via2_FR
+ Layer via3
+ default via: M3M4_PR_M
+ Layer via4
+ default via: via4_FR
+Writing reference output def...
+
+libcell analysis ...
+
+instance analysis ...
+ complete 10000 instances
+ complete 20000 instances
+ complete 30000 instances
+ complete 40000 instances
+ complete 50000 instances
+ complete 60000 instances
+ complete 70000 instances
+ complete 80000 instances
+ complete 90000 instances
+ complete 100000 instances
+ complete 200000 instances
+ complete 300000 instances
+ complete 400000 instances
+ complete 500000 instances
+ complete 600000 instances
+ complete 700000 instances
+ complete 800000 instances
+ complete 900000 instances
+#unique instances = 87
+
+init region query ...
+ complete 10000 insts
+ complete 20000 insts
+ complete 30000 insts
+ complete 40000 insts
+ complete 50000 insts
+ complete 60000 insts
+ complete 70000 insts
+ complete 80000 insts
+ complete 90000 insts
+ complete 100000 insts
+ complete 200000 insts
+ complete 300000 insts
+ complete 400000 insts
+ complete 500000 insts
+ complete 600000 insts
+ complete 700000 insts
+ complete 800000 insts
+ complete 900000 insts
+ complete FR_MASTERSLICE
+ complete FR_VIA
+ complete li1
+ complete mcon
+ complete met1
+ complete via
+ complete met2
+ complete via2
+ complete met3
+ complete via3
+ complete met4
+ complete via4
+ complete met5
+
+FR_MASTERSLICE shape region query size = 0
+FR_VIA shape region query size = 0
+li1 shape region query size = 10049539
+mcon shape region query size = 12449082
+met1 shape region query size = 2376266
+via shape region query size = 74712
+met2 shape region query size = 37960
+via2 shape region query size = 74712
+met3 shape region query size = 37356
+via3 shape region query size = 74712
+met4 shape region query size = 18713
+via4 shape region query size = 0
+met5 shape region query size = 1
+
+
+start pin access
+ complete 100 pins
+ complete 200 pins
+ complete 252 pins
+ complete 80 unique inst patterns
+ complete 1000 groups
+ complete 2000 groups
+ complete 3000 groups
+ complete 4000 groups
+ complete 5000 groups
+ complete 6000 groups
+ complete 7000 groups
+ complete 8000 groups
+ complete 9000 groups
+ complete 10000 groups
+ complete 20000 groups
+ complete 30000 groups
+ complete 40000 groups
+ complete 50000 groups
+ complete 60000 groups
+ complete 70000 groups
+ complete 80000 groups
+ complete 90000 groups
+ complete 100000 groups
+ complete 110000 groups
+ complete 120000 groups
+ complete 130000 groups
+ complete 140000 groups
+ complete 150000 groups
+ complete 160000 groups
+ complete 170000 groups
+ complete 180000 groups
+ complete 190000 groups
+ complete 197612 groups
+Expt1 runtime (pin-level access point gen): 1.22746
+Expt2 runtime (design-level access pattern gen): 8.10979
+#scanned instances = 927491
+#unique instances = 87
+#stdCellGenAp = 1875
+#stdCellValidPlanarAp = 36
+#stdCellValidViaAp = 1164
+#stdCellPinNoAp = 0
+#stdCellPinCnt = 731343
+#instTermValidViaApCnt = 0
+#macroGenAp = 0
+#macroValidPlanarAp = 0
+#macroValidViaAp = 0
+#macroNoAp = 0
+
+complete pin access
+cpu time = 00:00:47, elapsed time = 00:00:10, memory = 1817.29 (MB), peak = 2182.73 (MB)
+
+post process guides ...
+GCELLGRID X -1 DO 449 STEP 6900 ;
+GCELLGRID Y -1 DO 362 STEP 6900 ;
+ complete 10000 orig guides
+ complete 20000 orig guides
+ complete 30000 orig guides
+ complete 40000 orig guides
+ complete 50000 orig guides
+ complete 60000 orig guides
+ complete 70000 orig guides
+ complete 80000 orig guides
+ complete 90000 orig guides
+ complete 100000 orig guides
+ complete 200000 orig guides
+ complete 300000 orig guides
+ complete 400000 orig guides
+ complete 500000 orig guides
+ complete 600000 orig guides
+ complete 700000 orig guides
+ complete 800000 orig guides
+ complete 900000 orig guides
+ complete 1000000 orig guides
+ complete 1100000 orig guides
+ complete 1200000 orig guides
+ complete 1300000 orig guides
+ complete 1400000 orig guides
+ complete FR_MASTERSLICE
+ complete FR_VIA
+ complete li1
+ complete mcon
+ complete met1
+ complete via
+ complete met2
+ complete via2
+ complete met3
+ complete via3
+ complete met4
+ complete via4
+ complete met5
+ complete 10000 nets
+ complete 20000 nets
+ complete 30000 nets
+ complete 40000 nets
+ complete 50000 nets
+ complete 60000 nets
+ complete 70000 nets
+ complete 80000 nets
+ complete 90000 nets
+ complete 100000 nets
+
+building cmap ...
+
+init guide query ...
+ complete 10000 nets (guide)
+ complete 20000 nets (guide)
+ complete 30000 nets (guide)
+ complete 40000 nets (guide)
+ complete 50000 nets (guide)
+ complete 60000 nets (guide)
+ complete 70000 nets (guide)
+ complete 80000 nets (guide)
+ complete 90000 nets (guide)
+ complete 100000 nets (guide)
+ complete FR_MASTERSLICE (guide)
+ complete FR_VIA (guide)
+ complete li1 (guide)
+ complete mcon (guide)
+ complete met1 (guide)
+ complete via (guide)
+ complete met2 (guide)
+ complete via2 (guide)
+ complete met3 (guide)
+ complete via3 (guide)
+ complete met4 (guide)
+ complete via4 (guide)
+ complete met5 (guide)
+
+FR_MASTERSLICE guide region query size = 0
+FR_VIA guide region query size = 0
+li1 guide region query size = 578051
+mcon guide region query size = 0
+met1 guide region query size = 487063
+via guide region query size = 0
+met2 guide region query size = 254774
+via2 guide region query size = 0
+met3 guide region query size = 2831
+via3 guide region query size = 0
+met4 guide region query size = 1345
+via4 guide region query size = 0
+met5 guide region query size = 0
+
+init gr pin query ...
+
+
+start track assignment
+Done with 834170 vertical wires in 8 frboxes and 489894 horizontal wires in 9 frboxes.
+Done with 132167 vertical wires in 8 frboxes and 157988 horizontal wires in 9 frboxes.
+
+complete track assignment
+cpu time = 00:04:45, elapsed time = 00:01:41, memory = 2503.34 (MB), peak = 5582.41 (MB)
+
+post processing ...
+
+start routing data preparation
+initVia2ViaMinLen_minSpc li1 (d2d, d2u, u2d, u2u) = (0, 0, 0, 370)
+initVia2ViaMinLen_minSpc met1 (d2d, d2u, u2d, u2u) = (430, 445, 445, 460)
+initVia2ViaMinLen_minSpc met2 (d2d, d2u, u2d, u2u) = (460, 485, 485, 630)
+initVia2ViaMinLen_minSpc met3 (d2d, d2u, u2d, u2u) = (630, 655, 655, 680)
+initVia2ViaMinLen_minSpc met4 (d2d, d2u, u2d, u2u) = (630, 1055, 1055, 3020)
+initVia2ViaMinLen_minSpc met5 (d2d, d2u, u2d, u2u) = (1480, 0, 0, 0)
+initVia2ViaMinLen_minimumcut li1 (d2d, d2u, u2d, u2u) = (0, 0, 0, 370)
+initVia2ViaMinLen_minimumcut li1 zerolen (b, b, b, b) = (1, 1, 1, 1)
+initVia2ViaMinLen_minimumcut met1 (d2d, d2u, u2d, u2u) = (430, 445, 445, 460)
+initVia2ViaMinLen_minimumcut met1 zerolen (b, b, b, b) = (1, 1, 1, 1)
+initVia2ViaMinLen_minimumcut met2 (d2d, d2u, u2d, u2u) = (460, 485, 485, 630)
+initVia2ViaMinLen_minimumcut met2 zerolen (b, b, b, b) = (1, 1, 1, 1)
+initVia2ViaMinLen_minimumcut met3 (d2d, d2u, u2d, u2u) = (630, 655, 655, 680)
+initVia2ViaMinLen_minimumcut met3 zerolen (b, b, b, b) = (1, 1, 1, 1)
+initVia2ViaMinLen_minimumcut met4 (d2d, d2u, u2d, u2u) = (630, 1055, 1055, 3020)
+initVia2ViaMinLen_minimumcut met4 zerolen (b, b, b, b) = (1, 1, 1, 1)
+initVia2ViaMinLen_minimumcut met5 (d2d, d2u, u2d, u2u) = (1480, 0, 0, 0)
+initVia2ViaMinLen_minimumcut met5 zerolen (b, b, b, b) = (1, 1, 1, 1)
+initVia2ViaMinLenNew_minSpc li1 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (0, 0, 0, 0, 0, 0, 430, 370)
+initVia2ViaMinLenNew_minSpc met1 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (430, 370, 445, 385, 445, 385, 460, 460)
+initVia2ViaMinLenNew_minSpc met2 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (460, 460, 410, 485, 410, 485, 630, 630)
+initVia2ViaMinLenNew_minSpc met3 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (630, 630, 655, 625, 655, 625, 680, 630)
+initVia2ViaMinLenNew_minSpc met4 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (680, 630, 1055, 1055, 1055, 1055, 3020, 3020)
+initVia2ViaMinLenNew_minSpc met5 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (1480, 1480, 0, 0, 0, 0, 0, 0)
+initVia2ViaMinLenNew_minimumcut li1 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (0, 0, 0, 0, 0, 0, 430, 370)
+initVia2ViaMinLenNew_minimumcut met1 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (430, 370, 445, 385, 445, 385, 460, 460)
+initVia2ViaMinLenNew_minimumcut met2 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (460, 460, 410, 485, 410, 485, 630, 630)
+initVia2ViaMinLenNew_minimumcut met3 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (630, 630, 655, 625, 655, 625, 680, 630)
+initVia2ViaMinLenNew_minimumcut met4 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (680, 630, 1055, 1055, 1055, 1055, 3020, 3020)
+initVia2ViaMinLenNew_minimumcut met5 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (1480, 1480, 0, 0, 0, 0, 0, 0)
+initVia2ViaMinLenNew_cutSpc li1 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (0, 0, 0, 0, 0, 0, 430, 370)
+initVia2ViaMinLenNew_cutSpc met1 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (430, 370, 445, 385, 445, 385, 460, 460)
+initVia2ViaMinLenNew_cutSpc met2 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (460, 460, 410, 485, 410, 485, 630, 630)
+initVia2ViaMinLenNew_cutSpc met3 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (630, 630, 655, 625, 655, 625, 680, 630)
+initVia2ViaMinLenNew_cutSpc met4 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (680, 630, 1055, 1055, 1055, 1055, 3020, 3020)
+initVia2ViaMinLenNew_cutSpc met5 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (1600, 1600, 0, 0, 0, 0, 0, 0)
+cpu time = 00:00:02, elapsed time = 00:00:02, memory = 2503.34 (MB), peak = 5582.41 (MB)
+
+start detail routing ...
+start 0th optimization iteration ...
+ completing 10% with 0 violations
+ elapsed time = 00:02:39, memory = 2806.83 (MB)
+ completing 20% with 0 violations
+ elapsed time = 00:05:21, memory = 2962.18 (MB)
+ completing 30% with 161414 violations
+ elapsed time = 00:07:56, memory = 3007.89 (MB)
+ completing 40% with 161414 violations
+ elapsed time = 00:10:33, memory = 3106.07 (MB)
+ completing 50% with 161414 violations
+ elapsed time = 00:13:35, memory = 3255.52 (MB)
+ completing 60% with 218634 violations
+ elapsed time = 00:16:40, memory = 3178.65 (MB)
+ completing 70% with 218634 violations
+ elapsed time = 00:19:52, memory = 3328.68 (MB)
+ completing 80% with 305347 violations
+ elapsed time = 00:22:31, memory = 3287.85 (MB)
+ completing 90% with 305347 violations
+ elapsed time = 00:25:07, memory = 3417.27 (MB)
+ completing 100% with 282726 violations
+ elapsed time = 00:28:19, memory = 3176.97 (MB)
+ number of violations = 309643
+cpu time = 01:50:54, elapsed time = 00:28:36, memory = 3738.74 (MB), peak = 5582.41 (MB)
+total wire length = 13889967 um
+total wire length on LAYER li1 = 5814 um
+total wire length on LAYER met1 = 5494976 um
+total wire length on LAYER met2 = 7371041 um
+total wire length on LAYER met3 = 239770 um
+total wire length on LAYER met4 = 778364 um
+total wire length on LAYER met5 = 0 um
+total number of vias = 1581666
+up-via summary (total 1581666):
+
+--------------------------
+ FR_MASTERSLICE 0
+ li1 742218
+ met1 802803
+ met2 29780
+ met3 6865
+ met4 0
+--------------------------
+ 1581666
+
+
+start 1st optimization iteration ...
+ completing 10% with 309643 violations
+ elapsed time = 00:02:24, memory = 3981.30 (MB)
+ completing 20% with 309643 violations
+ elapsed time = 00:04:43, memory = 4144.67 (MB)
+ completing 30% with 273519 violations
+ elapsed time = 00:06:54, memory = 3928.46 (MB)
+ completing 40% with 273519 violations
+ elapsed time = 00:09:03, memory = 4039.13 (MB)
+ completing 50% with 273519 violations
+ elapsed time = 00:11:10, memory = 4194.89 (MB)
+ completing 60% with 242205 violations
+ elapsed time = 00:13:08, memory = 3987.17 (MB)
+ completing 70% with 242205 violations
+ elapsed time = 00:15:09, memory = 4164.96 (MB)
+ completing 80% with 206482 violations
+ elapsed time = 00:16:52, memory = 3937.68 (MB)
+ completing 90% with 206482 violations
+ elapsed time = 00:18:40, memory = 4036.53 (MB)
+ completing 100% with 174198 violations
+ elapsed time = 00:20:49, memory = 3682.65 (MB)
+ number of violations = 174203
+cpu time = 01:40:44, elapsed time = 00:21:03, memory = 3682.65 (MB), peak = 5582.41 (MB)
+total wire length = 13848719 um
+total wire length on LAYER li1 = 5829 um
+total wire length on LAYER met1 = 5461425 um
+total wire length on LAYER met2 = 7334458 um
+total wire length on LAYER met3 = 259827 um
+total wire length on LAYER met4 = 787177 um
+total wire length on LAYER met5 = 0 um
+total number of vias = 1590089
+up-via summary (total 1590089):
+
+--------------------------
+ FR_MASTERSLICE 0
+ li1 742037
+ met1 804885
+ met2 34826
+ met3 8341
+ met4 0
+--------------------------
+ 1590089
+
+
+start 2nd optimization iteration ...
+ completing 10% with 174203 violations
+ elapsed time = 00:01:50, memory = 3986.30 (MB)
+ completing 20% with 174203 violations
+ elapsed time = 00:03:48, memory = 4146.27 (MB)
+ completing 30% with 187965 violations
+ elapsed time = 00:05:19, memory = 3934.98 (MB)
+ completing 40% with 187965 violations
+ elapsed time = 00:06:56, memory = 4013.48 (MB)
+ completing 50% with 187965 violations
+ elapsed time = 00:09:11, memory = 4175.61 (MB)
+ completing 60% with 187649 violations
+ elapsed time = 00:11:01, memory = 3985.12 (MB)
+ completing 70% with 187649 violations
+ elapsed time = 00:12:56, memory = 4151.56 (MB)
+ completing 80% with 187720 violations
+ elapsed time = 00:14:40, memory = 3936.03 (MB)
+ completing 90% with 187720 violations
+ elapsed time = 00:16:20, memory = 4024.31 (MB)
+ completing 100% with 174655 violations
+ elapsed time = 00:18:33, memory = 3802.54 (MB)
+ number of violations = 174659
+cpu time = 01:39:36, elapsed time = 00:18:47, memory = 3802.54 (MB), peak = 5582.41 (MB)
+total wire length = 13839085 um
+total wire length on LAYER li1 = 5789 um
+total wire length on LAYER met1 = 5455520 um
+total wire length on LAYER met2 = 7323607 um
+total wire length on LAYER met3 = 263894 um
+total wire length on LAYER met4 = 790273 um
+total wire length on LAYER met5 = 0 um
+total number of vias = 1593146
+up-via summary (total 1593146):
+
+--------------------------
+ FR_MASTERSLICE 0
+ li1 741952
+ met1 806954
+ met2 35486
+ met3 8754
+ met4 0
+--------------------------
+ 1593146
+
+
+start 3rd optimization iteration ...
+ completing 10% with 174659 violations
+ elapsed time = 00:01:24, memory = 3981.30 (MB)
+ completing 20% with 174659 violations
+ elapsed time = 00:03:02, memory = 4140.45 (MB)
+ completing 30% with 145204 violations
+ elapsed time = 00:04:20, memory = 3937.63 (MB)
+ completing 40% with 145204 violations
+ elapsed time = 00:05:42, memory = 4017.17 (MB)
+ completing 50% with 145204 violations
+ elapsed time = 00:07:14, memory = 4187.19 (MB)
+ completing 60% with 111765 violations
+ elapsed time = 00:08:33, memory = 3986.08 (MB)
+ completing 70% with 111765 violations
+ elapsed time = 00:09:59, memory = 4126.29 (MB)
+ completing 80% with 75951 violations
+ elapsed time = 00:11:06, memory = 3948.09 (MB)
+ completing 90% with 75951 violations
+ elapsed time = 00:12:16, memory = 3992.76 (MB)
+ completing 100% with 35891 violations
+ elapsed time = 00:13:35, memory = 3738.97 (MB)
+ number of violations = 35891
+cpu time = 01:16:48, elapsed time = 00:13:42, memory = 3738.97 (MB), peak = 5582.41 (MB)
+total wire length = 13812517 um
+total wire length on LAYER li1 = 5421 um
+total wire length on LAYER met1 = 5105294 um
+total wire length on LAYER met2 = 7246047 um
+total wire length on LAYER met3 = 582499 um
+total wire length on LAYER met4 = 873254 um
+total wire length on LAYER met5 = 0 um
+total number of vias = 1639890
+up-via summary (total 1639890):
+
+--------------------------
+ FR_MASTERSLICE 0
+ li1 741629
+ met1 817631
+ met2 66114
+ met3 14516
+ met4 0
+--------------------------
+ 1639890
+
+
+start 4th optimization iteration ...
+ completing 10% with 35891 violations
+ elapsed time = 00:00:45, memory = 3977.20 (MB)
+ completing 20% with 35891 violations
+ elapsed time = 00:01:28, memory = 4111.78 (MB)
+ completing 30% with 30106 violations
+ elapsed time = 00:02:04, memory = 3935.92 (MB)
+ completing 40% with 30106 violations
+ elapsed time = 00:02:49, memory = 4006.20 (MB)
+ completing 50% with 30106 violations
+ elapsed time = 00:03:39, memory = 4160.15 (MB)
+ completing 60% with 23456 violations
+ elapsed time = 00:04:26, memory = 3978.80 (MB)
+ completing 70% with 23456 violations
+ elapsed time = 00:05:12, memory = 4123.14 (MB)
+ completing 80% with 17391 violations
+ elapsed time = 00:05:47, memory = 3937.95 (MB)
+ completing 90% with 17391 violations
+ elapsed time = 00:06:34, memory = 4000.05 (MB)
+ completing 100% with 9744 violations
+ elapsed time = 00:07:20, memory = 3679.18 (MB)
+ number of violations = 9744
+cpu time = 00:43:42, elapsed time = 00:07:24, memory = 3679.18 (MB), peak = 5582.41 (MB)
+total wire length = 13816400 um
+total wire length on LAYER li1 = 5418 um
+total wire length on LAYER met1 = 5059766 um
+total wire length on LAYER met2 = 7209495 um
+total wire length on LAYER met3 = 630536 um
+total wire length on LAYER met4 = 911183 um
+total wire length on LAYER met5 = 0 um
+total number of vias = 1651437
+up-via summary (total 1651437):
+
+--------------------------
+ FR_MASTERSLICE 0
+ li1 741656
+ met1 821170
+ met2 71776
+ met3 16835
+ met4 0
+--------------------------
+ 1651437
+
+
+start 5th optimization iteration ...
+ completing 10% with 9744 violations
+ elapsed time = 00:00:26, memory = 3954.78 (MB)
+ completing 20% with 9744 violations
+ elapsed time = 00:01:08, memory = 4011.82 (MB)
+ completing 30% with 8121 violations
+ elapsed time = 00:01:32, memory = 3898.25 (MB)
+ completing 40% with 8121 violations
+ elapsed time = 00:02:00, memory = 3982.79 (MB)
+ completing 50% with 8121 violations
+ elapsed time = 00:02:35, memory = 4036.77 (MB)
+ completing 60% with 6321 violations
+ elapsed time = 00:02:59, memory = 3942.32 (MB)
+ completing 70% with 6321 violations
+ elapsed time = 00:03:31, memory = 4032.73 (MB)
+ completing 80% with 4676 violations
+ elapsed time = 00:03:50, memory = 3899.44 (MB)
+ completing 90% with 4676 violations
+ elapsed time = 00:04:13, memory = 3975.62 (MB)
+ completing 100% with 2714 violations
+ elapsed time = 00:04:42, memory = 3675.67 (MB)
+ number of violations = 2714
+cpu time = 00:27:58, elapsed time = 00:04:44, memory = 3675.67 (MB), peak = 5582.41 (MB)
+total wire length = 13818626 um
+total wire length on LAYER li1 = 5390 um
+total wire length on LAYER met1 = 5048091 um
+total wire length on LAYER met2 = 7191392 um
+total wire length on LAYER met3 = 644217 um
+total wire length on LAYER met4 = 929534 um
+total wire length on LAYER met5 = 0 um
+total number of vias = 1655671
+up-via summary (total 1655671):
+
+--------------------------
+ FR_MASTERSLICE 0
+ li1 741624
+ met1 822339
+ met2 73643
+ met3 18065
+ met4 0
+--------------------------
+ 1655671
+
+
+start 6th optimization iteration ...
+ completing 10% with 2714 violations
+ elapsed time = 00:00:11, memory = 3910.53 (MB)
+ completing 20% with 2714 violations
+ elapsed time = 00:00:32, memory = 3981.08 (MB)
+ completing 30% with 2128 violations
+ elapsed time = 00:00:42, memory = 3862.67 (MB)
+ completing 40% with 2128 violations
+ elapsed time = 00:00:53, memory = 3901.56 (MB)
+ completing 50% with 2128 violations
+ elapsed time = 00:01:10, memory = 3969.61 (MB)
+ completing 60% with 1635 violations
+ elapsed time = 00:01:20, memory = 3894.86 (MB)
+ completing 70% with 1635 violations
+ elapsed time = 00:01:39, memory = 3967.92 (MB)
+ completing 80% with 1075 violations
+ elapsed time = 00:01:50, memory = 3831.64 (MB)
+ completing 90% with 1075 violations
+ elapsed time = 00:02:02, memory = 3903.47 (MB)
+ completing 100% with 663 violations
+ elapsed time = 00:02:18, memory = 3730.54 (MB)
+ number of violations = 663
+cpu time = 00:13:40, elapsed time = 00:02:19, memory = 3730.54 (MB), peak = 5582.41 (MB)
+total wire length = 13819389 um
+total wire length on LAYER li1 = 5373 um
+total wire length on LAYER met1 = 5044631 um
+total wire length on LAYER met2 = 7185464 um
+total wire length on LAYER met3 = 648427 um
+total wire length on LAYER met4 = 935491 um
+total wire length on LAYER met5 = 0 um
+total number of vias = 1657036
+up-via summary (total 1657036):
+
+--------------------------
+ FR_MASTERSLICE 0
+ li1 741596
+ met1 822647
+ met2 74251
+ met3 18542
+ met4 0
+--------------------------
+ 1657036
+
+
+start 7th optimization iteration ...
+ completing 10% with 663 violations
+ elapsed time = 00:00:07, memory = 3872.08 (MB)
+ completing 20% with 663 violations
+ elapsed time = 00:00:18, memory = 3932.66 (MB)
+ completing 30% with 560 violations
+ elapsed time = 00:00:25, memory = 3891.01 (MB)
+ completing 40% with 560 violations
+ elapsed time = 00:00:31, memory = 3908.63 (MB)
+ completing 50% with 560 violations
+ elapsed time = 00:00:41, memory = 3932.56 (MB)
+ completing 60% with 447 violations
+ elapsed time = 00:00:48, memory = 3901.15 (MB)
+ completing 70% with 447 violations
+ elapsed time = 00:00:57, memory = 3932.16 (MB)
+ completing 80% with 327 violations
+ elapsed time = 00:01:05, memory = 3932.16 (MB)
+ completing 90% with 327 violations
+ elapsed time = 00:01:12, memory = 3932.26 (MB)
+ completing 100% with 197 violations
+ elapsed time = 00:01:21, memory = 3932.66 (MB)
+ number of violations = 197
+cpu time = 00:07:59, elapsed time = 00:01:21, memory = 3932.66 (MB), peak = 5582.41 (MB)
+total wire length = 13819588 um
+total wire length on LAYER li1 = 5375 um
+total wire length on LAYER met1 = 5043949 um
+total wire length on LAYER met2 = 7183876 um
+total wire length on LAYER met3 = 649340 um
+total wire length on LAYER met4 = 937047 um
+total wire length on LAYER met5 = 0 um
+total number of vias = 1657368
+up-via summary (total 1657368):
+
+--------------------------
+ FR_MASTERSLICE 0
+ li1 741600
+ met1 822702
+ met2 74423
+ met3 18643
+ met4 0
+--------------------------
+ 1657368
+
+
+start 8th optimization iteration ...
+ completing 10% with 197 violations
+ elapsed time = 00:00:05, memory = 3932.66 (MB)
+ completing 20% with 197 violations
+ elapsed time = 00:00:13, memory = 3934.98 (MB)
+ completing 30% with 151 violations
+ elapsed time = 00:00:19, memory = 3934.98 (MB)
+ completing 40% with 151 violations
+ elapsed time = 00:00:25, memory = 3935.12 (MB)
+ completing 50% with 151 violations
+ elapsed time = 00:00:32, memory = 3935.14 (MB)
+ completing 60% with 126 violations
+ elapsed time = 00:00:38, memory = 3935.14 (MB)
+ completing 70% with 126 violations
+ elapsed time = 00:00:45, memory = 3935.14 (MB)
+ completing 80% with 87 violations
+ elapsed time = 00:00:51, memory = 3935.14 (MB)
+ completing 90% with 87 violations
+ elapsed time = 00:00:57, memory = 3935.14 (MB)
+ completing 100% with 57 violations
+ elapsed time = 00:01:04, memory = 3935.14 (MB)
+ number of violations = 57
+cpu time = 00:06:20, elapsed time = 00:01:04, memory = 3935.14 (MB), peak = 5582.41 (MB)
+total wire length = 13819727 um
+total wire length on LAYER li1 = 5374 um
+total wire length on LAYER met1 = 5043848 um
+total wire length on LAYER met2 = 7183530 um
+total wire length on LAYER met3 = 649581 um
+total wire length on LAYER met4 = 937393 um
+total wire length on LAYER met5 = 0 um
+total number of vias = 1657518
+up-via summary (total 1657518):
+
+--------------------------
+ FR_MASTERSLICE 0
+ li1 741600
+ met1 822742
+ met2 74483
+ met3 18693
+ met4 0
+--------------------------
+ 1657518
+
+
+start 9th optimization iteration ...
+ completing 10% with 57 violations
+ elapsed time = 00:00:05, memory = 3935.14 (MB)
+ completing 20% with 57 violations
+ elapsed time = 00:00:11, memory = 3935.14 (MB)
+ completing 30% with 52 violations
+ elapsed time = 00:00:17, memory = 3935.14 (MB)
+ completing 40% with 52 violations
+ elapsed time = 00:00:23, memory = 3935.14 (MB)
+ completing 50% with 52 violations
+ elapsed time = 00:00:30, memory = 3935.14 (MB)
+ completing 60% with 41 violations
+ elapsed time = 00:00:35, memory = 3935.30 (MB)
+ completing 70% with 41 violations
+ elapsed time = 00:00:41, memory = 3935.30 (MB)
+ completing 80% with 34 violations
+ elapsed time = 00:00:47, memory = 3935.30 (MB)
+ completing 90% with 34 violations
+ elapsed time = 00:00:53, memory = 3935.30 (MB)
+ completing 100% with 31 violations
+ elapsed time = 00:00:59, memory = 3935.30 (MB)
+ number of violations = 31
+cpu time = 00:05:51, elapsed time = 00:01:00, memory = 3935.30 (MB), peak = 5582.41 (MB)
+total wire length = 13819750 um
+total wire length on LAYER li1 = 5375 um
+total wire length on LAYER met1 = 5043803 um
+total wire length on LAYER met2 = 7183512 um
+total wire length on LAYER met3 = 649629 um
+total wire length on LAYER met4 = 937429 um
+total wire length on LAYER met5 = 0 um
+total number of vias = 1657550
+up-via summary (total 1657550):
+
+--------------------------
+ FR_MASTERSLICE 0
+ li1 741602
+ met1 822746
+ met2 74501
+ met3 18701
+ met4 0
+--------------------------
+ 1657550
+
+
+start 10th optimization iteration ...
+ completing 10% with 31 violations
+ elapsed time = 00:00:05, memory = 3935.30 (MB)
+ completing 20% with 31 violations
+ elapsed time = 00:00:11, memory = 3935.30 (MB)
+ completing 30% with 31 violations
+ elapsed time = 00:00:17, memory = 3935.30 (MB)
+ completing 40% with 31 violations
+ elapsed time = 00:00:23, memory = 3935.30 (MB)
+ completing 50% with 31 violations
+ elapsed time = 00:00:29, memory = 3935.30 (MB)
+ completing 60% with 26 violations
+ elapsed time = 00:00:35, memory = 3935.30 (MB)
+ completing 70% with 26 violations
+ elapsed time = 00:00:41, memory = 3935.30 (MB)
+ completing 80% with 23 violations
+ elapsed time = 00:00:47, memory = 3935.30 (MB)
+ completing 90% with 23 violations
+ elapsed time = 00:00:52, memory = 3935.30 (MB)
+ completing 100% with 20 violations
+ elapsed time = 00:00:58, memory = 3935.30 (MB)
+ number of violations = 20
+cpu time = 00:05:45, elapsed time = 00:00:59, memory = 3935.30 (MB), peak = 5582.41 (MB)
+total wire length = 13819775 um
+total wire length on LAYER li1 = 5373 um
+total wire length on LAYER met1 = 5043805 um
+total wire length on LAYER met2 = 7183529 um
+total wire length on LAYER met3 = 649641 um
+total wire length on LAYER met4 = 937424 um
+total wire length on LAYER met5 = 0 um
+total number of vias = 1657565
+up-via summary (total 1657565):
+
+--------------------------
+ FR_MASTERSLICE 0
+ li1 741598
+ met1 822753
+ met2 74501
+ met3 18713
+ met4 0
+--------------------------
+ 1657565
+
+
+start 11th optimization iteration ...
+ completing 10% with 20 violations
+ elapsed time = 00:00:05, memory = 3935.30 (MB)
+ completing 20% with 20 violations
+ elapsed time = 00:00:11, memory = 3935.30 (MB)
+ completing 30% with 20 violations
+ elapsed time = 00:00:17, memory = 3935.30 (MB)
+ completing 40% with 20 violations
+ elapsed time = 00:00:23, memory = 3935.30 (MB)
+ completing 50% with 20 violations
+ elapsed time = 00:00:29, memory = 3935.30 (MB)
+ completing 60% with 17 violations
+ elapsed time = 00:00:35, memory = 3935.30 (MB)
+ completing 70% with 17 violations
+ elapsed time = 00:00:41, memory = 3935.30 (MB)
+ completing 80% with 17 violations
+ elapsed time = 00:00:47, memory = 3935.30 (MB)
+ completing 90% with 17 violations
+ elapsed time = 00:00:52, memory = 3935.30 (MB)
+ completing 100% with 17 violations
+ elapsed time = 00:00:58, memory = 3935.30 (MB)
+ number of violations = 17
+cpu time = 00:05:45, elapsed time = 00:00:59, memory = 3935.30 (MB), peak = 5582.41 (MB)
+total wire length = 13819776 um
+total wire length on LAYER li1 = 5373 um
+total wire length on LAYER met1 = 5043796 um
+total wire length on LAYER met2 = 7183537 um
+total wire length on LAYER met3 = 649643 um
+total wire length on LAYER met4 = 937424 um
+total wire length on LAYER met5 = 0 um
+total number of vias = 1657566
+up-via summary (total 1657566):
+
+--------------------------
+ FR_MASTERSLICE 0
+ li1 741598
+ met1 822752
+ met2 74503
+ met3 18713
+ met4 0
+--------------------------
+ 1657566
+
+
+start 12th optimization iteration ...
+ completing 10% with 17 violations
+ elapsed time = 00:00:05, memory = 3935.30 (MB)
+ completing 20% with 17 violations
+ elapsed time = 00:00:11, memory = 3935.30 (MB)
+ completing 30% with 17 violations
+ elapsed time = 00:00:17, memory = 3935.30 (MB)
+ completing 40% with 17 violations
+ elapsed time = 00:00:23, memory = 3935.30 (MB)
+ completing 50% with 17 violations
+ elapsed time = 00:00:29, memory = 3935.30 (MB)
+ completing 60% with 17 violations
+ elapsed time = 00:00:34, memory = 3935.30 (MB)
+ completing 70% with 17 violations
+ elapsed time = 00:00:40, memory = 3935.30 (MB)
+ completing 80% with 17 violations
+ elapsed time = 00:00:46, memory = 3935.30 (MB)
+ completing 90% with 17 violations
+ elapsed time = 00:00:52, memory = 3935.30 (MB)
+ completing 100% with 15 violations
+ elapsed time = 00:00:58, memory = 3935.30 (MB)
+ number of violations = 15
+cpu time = 00:05:40, elapsed time = 00:00:58, memory = 3935.30 (MB), peak = 5582.41 (MB)
+total wire length = 13819777 um
+total wire length on LAYER li1 = 5373 um
+total wire length on LAYER met1 = 5043798 um
+total wire length on LAYER met2 = 7183536 um
+total wire length on LAYER met3 = 649643 um
+total wire length on LAYER met4 = 937424 um
+total wire length on LAYER met5 = 0 um
+total number of vias = 1657565
+up-via summary (total 1657565):
+
+--------------------------
+ FR_MASTERSLICE 0
+ li1 741598
+ met1 822751
+ met2 74503
+ met3 18713
+ met4 0
+--------------------------
+ 1657565
+
+
+start 13th optimization iteration ...
+ completing 10% with 15 violations
+ elapsed time = 00:00:05, memory = 3935.30 (MB)
+ completing 20% with 15 violations
+ elapsed time = 00:00:11, memory = 3935.30 (MB)
+ completing 30% with 15 violations
+ elapsed time = 00:00:16, memory = 3935.30 (MB)
+ completing 40% with 15 violations
+ elapsed time = 00:00:22, memory = 3935.30 (MB)
+ completing 50% with 15 violations
+ elapsed time = 00:00:28, memory = 3935.30 (MB)
+ completing 60% with 15 violations
+ elapsed time = 00:00:34, memory = 3935.30 (MB)
+ completing 70% with 15 violations
+ elapsed time = 00:00:39, memory = 3935.30 (MB)
+ completing 80% with 15 violations
+ elapsed time = 00:00:45, memory = 3935.30 (MB)
+ completing 90% with 15 violations
+ elapsed time = 00:00:51, memory = 3935.30 (MB)
+ completing 100% with 15 violations
+ elapsed time = 00:00:57, memory = 3935.30 (MB)
+ number of violations = 15
+cpu time = 00:05:40, elapsed time = 00:00:58, memory = 3935.30 (MB), peak = 5582.41 (MB)
+total wire length = 13819766 um
+total wire length on LAYER li1 = 5373 um
+total wire length on LAYER met1 = 5043793 um
+total wire length on LAYER met2 = 7183530 um
+total wire length on LAYER met3 = 649644 um
+total wire length on LAYER met4 = 937424 um
+total wire length on LAYER met5 = 0 um
+total number of vias = 1657573
+up-via summary (total 1657573):
+
+--------------------------
+ FR_MASTERSLICE 0
+ li1 741598
+ met1 822758
+ met2 74504
+ met3 18713
+ met4 0
+--------------------------
+ 1657573
+
+
+start 14th optimization iteration ...
+ completing 10% with 15 violations
+ elapsed time = 00:00:05, memory = 3935.30 (MB)
+ completing 20% with 15 violations
+ elapsed time = 00:00:11, memory = 3935.30 (MB)
+ completing 30% with 15 violations
+ elapsed time = 00:00:16, memory = 3935.30 (MB)
+ completing 40% with 15 violations
+ elapsed time = 00:00:22, memory = 3935.30 (MB)
+ completing 50% with 15 violations
+ elapsed time = 00:00:28, memory = 3935.30 (MB)
+ completing 60% with 15 violations
+ elapsed time = 00:00:34, memory = 3935.30 (MB)
+ completing 70% with 15 violations
+ elapsed time = 00:00:40, memory = 3935.30 (MB)
+ completing 80% with 15 violations
+ elapsed time = 00:00:45, memory = 3935.30 (MB)
+ completing 90% with 15 violations
+ elapsed time = 00:00:51, memory = 3935.30 (MB)
+ completing 100% with 15 violations
+ elapsed time = 00:00:57, memory = 3935.30 (MB)
+ number of violations = 15
+cpu time = 00:05:37, elapsed time = 00:00:57, memory = 3935.30 (MB), peak = 5582.41 (MB)
+total wire length = 13819774 um
+total wire length on LAYER li1 = 5373 um
+total wire length on LAYER met1 = 5043808 um
+total wire length on LAYER met2 = 7183523 um
+total wire length on LAYER met3 = 649643 um
+total wire length on LAYER met4 = 937424 um
+total wire length on LAYER met5 = 0 um
+total number of vias = 1657568
+up-via summary (total 1657568):
+
+--------------------------
+ FR_MASTERSLICE 0
+ li1 741598
+ met1 822754
+ met2 74503
+ met3 18713
+ met4 0
+--------------------------
+ 1657568
+
+
+start 15th optimization iteration ...
+ completing 10% with 15 violations
+ elapsed time = 00:00:05, memory = 3935.30 (MB)
+ completing 20% with 15 violations
+ elapsed time = 00:00:11, memory = 3935.30 (MB)
+ completing 30% with 15 violations
+ elapsed time = 00:00:16, memory = 3935.30 (MB)
+ completing 40% with 15 violations
+ elapsed time = 00:00:22, memory = 3935.30 (MB)
+ completing 50% with 15 violations
+ elapsed time = 00:00:29, memory = 3935.30 (MB)
+ completing 60% with 14 violations
+ elapsed time = 00:00:34, memory = 3935.30 (MB)
+ completing 70% with 14 violations
+ elapsed time = 00:00:40, memory = 3935.30 (MB)
+ completing 80% with 14 violations
+ elapsed time = 00:00:46, memory = 3935.30 (MB)
+ completing 90% with 14 violations
+ elapsed time = 00:00:52, memory = 3935.30 (MB)
+ completing 100% with 14 violations
+ elapsed time = 00:00:58, memory = 3935.30 (MB)
+ number of violations = 14
+cpu time = 00:05:40, elapsed time = 00:00:58, memory = 3935.30 (MB), peak = 5582.41 (MB)
+total wire length = 13819775 um
+total wire length on LAYER li1 = 5373 um
+total wire length on LAYER met1 = 5043788 um
+total wire length on LAYER met2 = 7183533 um
+total wire length on LAYER met3 = 649654 um
+total wire length on LAYER met4 = 937424 um
+total wire length on LAYER met5 = 0 um
+total number of vias = 1657571
+up-via summary (total 1657571):
+
+--------------------------
+ FR_MASTERSLICE 0
+ li1 741598
+ met1 822755
+ met2 74505
+ met3 18713
+ met4 0
+--------------------------
+ 1657571
+
+
+start 16th optimization iteration ...
+ completing 10% with 14 violations
+ elapsed time = 00:00:05, memory = 3935.30 (MB)
+ completing 20% with 14 violations
+ elapsed time = 00:00:11, memory = 3935.30 (MB)
+ completing 30% with 14 violations
+ elapsed time = 00:00:16, memory = 3935.30 (MB)
+ completing 40% with 14 violations
+ elapsed time = 00:00:22, memory = 3935.30 (MB)
+ completing 50% with 14 violations
+ elapsed time = 00:00:28, memory = 3935.30 (MB)
+ completing 60% with 14 violations
+ elapsed time = 00:00:34, memory = 3935.30 (MB)
+ completing 70% with 14 violations
+ elapsed time = 00:00:40, memory = 3935.30 (MB)
+ completing 80% with 14 violations
+ elapsed time = 00:00:46, memory = 3935.30 (MB)
+ completing 90% with 14 violations
+ elapsed time = 00:00:51, memory = 3935.30 (MB)
+ completing 100% with 14 violations
+ elapsed time = 00:00:57, memory = 3935.30 (MB)
+ number of violations = 14
+cpu time = 00:05:39, elapsed time = 00:00:58, memory = 3935.30 (MB), peak = 5582.41 (MB)
+total wire length = 13819782 um
+total wire length on LAYER li1 = 5373 um
+total wire length on LAYER met1 = 5043800 um
+total wire length on LAYER met2 = 7183526 um
+total wire length on LAYER met3 = 649656 um
+total wire length on LAYER met4 = 937424 um
+total wire length on LAYER met5 = 0 um
+total number of vias = 1657569
+up-via summary (total 1657569):
+
+--------------------------
+ FR_MASTERSLICE 0
+ li1 741598
+ met1 822751
+ met2 74507
+ met3 18713
+ met4 0
+--------------------------
+ 1657569
+
+
+start 17th optimization iteration ...
+ completing 10% with 14 violations
+ elapsed time = 00:00:05, memory = 3935.30 (MB)
+ completing 20% with 14 violations
+ elapsed time = 00:00:12, memory = 3935.30 (MB)
+ completing 30% with 14 violations
+ elapsed time = 00:00:16, memory = 3935.30 (MB)
+ completing 40% with 14 violations
+ elapsed time = 00:00:23, memory = 3935.30 (MB)
+ completing 50% with 14 violations
+ elapsed time = 00:00:29, memory = 3935.30 (MB)
+ completing 60% with 14 violations
+ elapsed time = 00:00:34, memory = 3935.30 (MB)
+ completing 70% with 14 violations
+ elapsed time = 00:00:41, memory = 3935.30 (MB)
+ completing 80% with 14 violations
+ elapsed time = 00:00:47, memory = 3935.30 (MB)
+ completing 90% with 14 violations
+ elapsed time = 00:00:53, memory = 3935.30 (MB)
+ completing 100% with 14 violations
+ elapsed time = 00:01:00, memory = 3935.30 (MB)
+ number of violations = 14
+cpu time = 00:05:57, elapsed time = 00:01:01, memory = 3935.30 (MB), peak = 5582.41 (MB)
+total wire length = 13819782 um
+total wire length on LAYER li1 = 5373 um
+total wire length on LAYER met1 = 5043800 um
+total wire length on LAYER met2 = 7183526 um
+total wire length on LAYER met3 = 649656 um
+total wire length on LAYER met4 = 937424 um
+total wire length on LAYER met5 = 0 um
+total number of vias = 1657569
+up-via summary (total 1657569):
+
+--------------------------
+ FR_MASTERSLICE 0
+ li1 741598
+ met1 822751
+ met2 74507
+ met3 18713
+ met4 0
+--------------------------
+ 1657569
+
+
+start 18th optimization iteration ...
+ completing 10% with 14 violations
+ elapsed time = 00:00:05, memory = 3935.30 (MB)
+ completing 20% with 14 violations
+ elapsed time = 00:00:11, memory = 3935.30 (MB)
+ completing 30% with 14 violations
+ elapsed time = 00:00:17, memory = 3935.30 (MB)
+ completing 40% with 14 violations
+ elapsed time = 00:00:23, memory = 3935.30 (MB)
+ completing 50% with 14 violations
+ elapsed time = 00:00:29, memory = 3935.30 (MB)
+ completing 60% with 14 violations
+ elapsed time = 00:00:35, memory = 3935.30 (MB)
+ completing 70% with 14 violations
+ elapsed time = 00:00:41, memory = 3935.30 (MB)
+ completing 80% with 14 violations
+ elapsed time = 00:00:46, memory = 3935.30 (MB)
+ completing 90% with 14 violations
+ elapsed time = 00:00:52, memory = 3935.30 (MB)
+ completing 100% with 14 violations
+ elapsed time = 00:00:58, memory = 3935.30 (MB)
+ number of violations = 14
+cpu time = 00:05:41, elapsed time = 00:00:58, memory = 3935.30 (MB), peak = 5582.41 (MB)
+total wire length = 13819821 um
+total wire length on LAYER li1 = 5374 um
+total wire length on LAYER met1 = 5043799 um
+total wire length on LAYER met2 = 7183525 um
+total wire length on LAYER met3 = 649688 um
+total wire length on LAYER met4 = 937432 um
+total wire length on LAYER met5 = 0 um
+total number of vias = 1657582
+up-via summary (total 1657582):
+
+--------------------------
+ FR_MASTERSLICE 0
+ li1 741599
+ met1 822755
+ met2 74513
+ met3 18715
+ met4 0
+--------------------------
+ 1657582
+
+
+start 19th optimization iteration ...
+ completing 10% with 14 violations
+ elapsed time = 00:00:05, memory = 3935.30 (MB)
+ completing 20% with 14 violations
+ elapsed time = 00:00:11, memory = 3935.30 (MB)
+ completing 30% with 14 violations
+ elapsed time = 00:00:17, memory = 3935.30 (MB)
+ completing 40% with 14 violations
+ elapsed time = 00:00:22, memory = 3935.30 (MB)
+ completing 50% with 14 violations
+ elapsed time = 00:00:28, memory = 3935.30 (MB)
+ completing 60% with 14 violations
+ elapsed time = 00:00:34, memory = 3935.30 (MB)
+ completing 70% with 14 violations
+ elapsed time = 00:00:40, memory = 3935.30 (MB)
+ completing 80% with 14 violations
+ elapsed time = 00:00:45, memory = 3935.30 (MB)
+ completing 90% with 14 violations
+ elapsed time = 00:00:51, memory = 3935.30 (MB)
+ completing 100% with 14 violations
+ elapsed time = 00:00:57, memory = 3935.30 (MB)
+ number of violations = 14
+cpu time = 00:05:37, elapsed time = 00:00:57, memory = 3935.30 (MB), peak = 5582.41 (MB)
+total wire length = 13819815 um
+total wire length on LAYER li1 = 5374 um
+total wire length on LAYER met1 = 5043787 um
+total wire length on LAYER met2 = 7183528 um
+total wire length on LAYER met3 = 649699 um
+total wire length on LAYER met4 = 937424 um
+total wire length on LAYER met5 = 0 um
+total number of vias = 1657581
+up-via summary (total 1657581):
+
+--------------------------
+ FR_MASTERSLICE 0
+ li1 741599
+ met1 822755
+ met2 74514
+ met3 18713
+ met4 0
+--------------------------
+ 1657581
+
+
+start 20th optimization iteration ...
+ completing 10% with 14 violations
+ elapsed time = 00:00:05, memory = 3935.30 (MB)
+ completing 20% with 14 violations
+ elapsed time = 00:00:11, memory = 3935.30 (MB)
+ completing 30% with 14 violations
+ elapsed time = 00:00:16, memory = 3935.30 (MB)
+ completing 40% with 14 violations
+ elapsed time = 00:00:22, memory = 3935.30 (MB)
+ completing 50% with 14 violations
+ elapsed time = 00:00:28, memory = 3935.30 (MB)
+ completing 60% with 14 violations
+ elapsed time = 00:00:34, memory = 3935.30 (MB)
+ completing 70% with 14 violations
+ elapsed time = 00:00:40, memory = 3935.30 (MB)
+ completing 80% with 14 violations
+ elapsed time = 00:00:46, memory = 3935.30 (MB)
+ completing 90% with 14 violations
+ elapsed time = 00:00:51, memory = 3935.30 (MB)
+ completing 100% with 14 violations
+ elapsed time = 00:00:58, memory = 3935.30 (MB)
+ number of violations = 14
+cpu time = 00:05:39, elapsed time = 00:00:58, memory = 3935.30 (MB), peak = 5582.41 (MB)
+total wire length = 13819821 um
+total wire length on LAYER li1 = 5374 um
+total wire length on LAYER met1 = 5043797 um
+total wire length on LAYER met2 = 7183524 um
+total wire length on LAYER met3 = 649700 um
+total wire length on LAYER met4 = 937424 um
+total wire length on LAYER met5 = 0 um
+total number of vias = 1657574
+up-via summary (total 1657574):
+
+--------------------------
+ FR_MASTERSLICE 0
+ li1 741599
+ met1 822749
+ met2 74513
+ met3 18713
+ met4 0
+--------------------------
+ 1657574
+
+
+start 21st optimization iteration ...
+ completing 10% with 14 violations
+ elapsed time = 00:00:05, memory = 3935.30 (MB)
+ completing 20% with 14 violations
+ elapsed time = 00:00:11, memory = 3935.30 (MB)
+ completing 30% with 14 violations
+ elapsed time = 00:00:16, memory = 3935.30 (MB)
+ completing 40% with 14 violations
+ elapsed time = 00:00:22, memory = 3935.30 (MB)
+ completing 50% with 14 violations
+ elapsed time = 00:00:28, memory = 3935.30 (MB)
+ completing 60% with 14 violations
+ elapsed time = 00:00:34, memory = 3935.30 (MB)
+ completing 70% with 14 violations
+ elapsed time = 00:00:40, memory = 3935.30 (MB)
+ completing 80% with 14 violations
+ elapsed time = 00:00:46, memory = 3935.30 (MB)
+ completing 90% with 14 violations
+ elapsed time = 00:00:52, memory = 3935.30 (MB)
+ completing 100% with 14 violations
+ elapsed time = 00:00:58, memory = 3935.30 (MB)
+ number of violations = 14
+cpu time = 00:05:44, elapsed time = 00:00:58, memory = 3935.30 (MB), peak = 5582.41 (MB)
+total wire length = 13819824 um
+total wire length on LAYER li1 = 5374 um
+total wire length on LAYER met1 = 5043787 um
+total wire length on LAYER met2 = 7183537 um
+total wire length on LAYER met3 = 649701 um
+total wire length on LAYER met4 = 937424 um
+total wire length on LAYER met5 = 0 um
+total number of vias = 1657585
+up-via summary (total 1657585):
+
+--------------------------
+ FR_MASTERSLICE 0
+ li1 741599
+ met1 822759
+ met2 74514
+ met3 18713
+ met4 0
+--------------------------
+ 1657585
+
+
+start 22nd optimization iteration ...
+ completing 10% with 14 violations
+ elapsed time = 00:00:05, memory = 3935.30 (MB)
+ completing 20% with 14 violations
+ elapsed time = 00:00:11, memory = 3935.30 (MB)
+ completing 30% with 14 violations
+ elapsed time = 00:00:16, memory = 3935.30 (MB)
+ completing 40% with 14 violations
+ elapsed time = 00:00:22, memory = 3935.30 (MB)
+ completing 50% with 14 violations
+ elapsed time = 00:00:28, memory = 3935.30 (MB)
+ completing 60% with 14 violations
+ elapsed time = 00:00:33, memory = 3935.30 (MB)
+ completing 70% with 14 violations
+ elapsed time = 00:00:39, memory = 3935.30 (MB)
+ completing 80% with 14 violations
+ elapsed time = 00:00:45, memory = 3935.30 (MB)
+ completing 90% with 14 violations
+ elapsed time = 00:00:51, memory = 3935.30 (MB)
+ completing 100% with 14 violations
+ elapsed time = 00:00:57, memory = 3935.30 (MB)
+ number of violations = 14
+cpu time = 00:05:39, elapsed time = 00:00:58, memory = 3935.30 (MB), peak = 5582.41 (MB)
+total wire length = 13819826 um
+total wire length on LAYER li1 = 5374 um
+total wire length on LAYER met1 = 5043809 um
+total wire length on LAYER met2 = 7183530 um
+total wire length on LAYER met3 = 649687 um
+total wire length on LAYER met4 = 937424 um
+total wire length on LAYER met5 = 0 um
+total number of vias = 1657579
+up-via summary (total 1657579):
+
+--------------------------
+ FR_MASTERSLICE 0
+ li1 741599
+ met1 822756
+ met2 74511
+ met3 18713
+ met4 0
+--------------------------
+ 1657579
+
+
+start 23rd optimization iteration ...
+ completing 10% with 14 violations
+ elapsed time = 00:00:05, memory = 3935.30 (MB)
+ completing 20% with 14 violations
+ elapsed time = 00:00:11, memory = 3935.30 (MB)
+ completing 30% with 14 violations
+ elapsed time = 00:00:16, memory = 3935.30 (MB)
+ completing 40% with 14 violations
+ elapsed time = 00:00:22, memory = 3935.30 (MB)
+ completing 50% with 14 violations
+ elapsed time = 00:00:28, memory = 3935.30 (MB)
+ completing 60% with 14 violations
+ elapsed time = 00:00:33, memory = 3935.30 (MB)
+ completing 70% with 14 violations
+ elapsed time = 00:00:39, memory = 3935.30 (MB)
+ completing 80% with 14 violations
+ elapsed time = 00:00:45, memory = 3935.30 (MB)
+ completing 90% with 14 violations
+ elapsed time = 00:00:51, memory = 3935.30 (MB)
+ completing 100% with 14 violations
+ elapsed time = 00:00:57, memory = 3935.30 (MB)
+ number of violations = 14
+cpu time = 00:05:37, elapsed time = 00:00:57, memory = 3935.30 (MB), peak = 5582.41 (MB)
+total wire length = 13819820 um
+total wire length on LAYER li1 = 5374 um
+total wire length on LAYER met1 = 5043809 um
+total wire length on LAYER met2 = 7183524 um
+total wire length on LAYER met3 = 649687 um
+total wire length on LAYER met4 = 937424 um
+total wire length on LAYER met5 = 0 um
+total number of vias = 1657577
+up-via summary (total 1657577):
+
+--------------------------
+ FR_MASTERSLICE 0
+ li1 741599
+ met1 822754
+ met2 74511
+ met3 18713
+ met4 0
+--------------------------
+ 1657577
+
+
+start 24th optimization iteration ...
+ completing 10% with 14 violations
+ elapsed time = 00:00:05, memory = 3935.30 (MB)
+ completing 20% with 14 violations
+ elapsed time = 00:00:11, memory = 3935.30 (MB)
+ completing 30% with 14 violations
+ elapsed time = 00:00:16, memory = 3935.30 (MB)
+ completing 40% with 14 violations
+ elapsed time = 00:00:22, memory = 3935.30 (MB)
+ completing 50% with 14 violations
+ elapsed time = 00:00:28, memory = 3935.30 (MB)
+ completing 60% with 14 violations
+ elapsed time = 00:00:34, memory = 3935.30 (MB)
+ completing 70% with 14 violations
+ elapsed time = 00:00:40, memory = 3935.30 (MB)
+ completing 80% with 14 violations
+ elapsed time = 00:00:45, memory = 3935.30 (MB)
+ completing 90% with 14 violations
+ elapsed time = 00:00:51, memory = 3935.30 (MB)
+ completing 100% with 14 violations
+ elapsed time = 00:00:58, memory = 3935.30 (MB)
+ number of violations = 14
+cpu time = 00:05:42, elapsed time = 00:00:58, memory = 3935.30 (MB), peak = 5582.41 (MB)
+total wire length = 13819821 um
+total wire length on LAYER li1 = 5374 um
+total wire length on LAYER met1 = 5043812 um
+total wire length on LAYER met2 = 7183523 um
+total wire length on LAYER met3 = 649687 um
+total wire length on LAYER met4 = 937424 um
+total wire length on LAYER met5 = 0 um
+total number of vias = 1657577
+up-via summary (total 1657577):
+
+--------------------------
+ FR_MASTERSLICE 0
+ li1 741599
+ met1 822754
+ met2 74511
+ met3 18713
+ met4 0
+--------------------------
+ 1657577
+
+
+start 25th optimization iteration ...
+ completing 10% with 14 violations
+ elapsed time = 00:00:06, memory = 3935.30 (MB)
+ completing 20% with 14 violations
+ elapsed time = 00:00:12, memory = 3935.30 (MB)
+ completing 30% with 14 violations
+ elapsed time = 00:00:18, memory = 3935.30 (MB)
+ completing 40% with 14 violations
+ elapsed time = 00:00:24, memory = 3935.30 (MB)
+ completing 50% with 14 violations
+ elapsed time = 00:00:31, memory = 3935.30 (MB)
+ completing 60% with 19 violations
+ elapsed time = 00:00:37, memory = 3935.30 (MB)
+ completing 70% with 19 violations
+ elapsed time = 00:00:44, memory = 3935.30 (MB)
+ completing 80% with 19 violations
+ elapsed time = 00:00:50, memory = 3935.30 (MB)
+ completing 90% with 19 violations
+ elapsed time = 00:00:56, memory = 3935.30 (MB)
+ completing 100% with 19 violations
+ elapsed time = 00:01:02, memory = 3935.30 (MB)
+ number of violations = 19
+cpu time = 00:06:07, elapsed time = 00:01:03, memory = 3935.30 (MB), peak = 5582.41 (MB)
+total wire length = 13819821 um
+total wire length on LAYER li1 = 5372 um
+total wire length on LAYER met1 = 5043663 um
+total wire length on LAYER met2 = 7183382 um
+total wire length on LAYER met3 = 649859 um
+total wire length on LAYER met4 = 937543 um
+total wire length on LAYER met5 = 0 um
+total number of vias = 1657562
+up-via summary (total 1657562):
+
+--------------------------
+ FR_MASTERSLICE 0
+ li1 741595
+ met1 822738
+ met2 74506
+ met3 18723
+ met4 0
+--------------------------
+ 1657562
+
+
+start 26th optimization iteration ...
+ completing 10% with 19 violations
+ elapsed time = 00:00:05, memory = 3935.30 (MB)
+ completing 20% with 19 violations
+ elapsed time = 00:00:11, memory = 3938.64 (MB)
+ completing 30% with 19 violations
+ elapsed time = 00:00:17, memory = 3896.51 (MB)
+ completing 40% with 19 violations
+ elapsed time = 00:00:23, memory = 3903.21 (MB)
+ completing 50% with 19 violations
+ elapsed time = 00:00:29, memory = 3920.23 (MB)
+ completing 60% with 19 violations
+ elapsed time = 00:00:35, memory = 3920.23 (MB)
+ completing 70% with 19 violations
+ elapsed time = 00:00:40, memory = 3920.25 (MB)
+ completing 80% with 12 violations
+ elapsed time = 00:00:46, memory = 3920.25 (MB)
+ completing 90% with 12 violations
+ elapsed time = 00:00:52, memory = 3920.25 (MB)
+ completing 100% with 12 violations
+ elapsed time = 00:00:57, memory = 3920.25 (MB)
+ number of violations = 12
+cpu time = 00:05:41, elapsed time = 00:00:58, memory = 3920.25 (MB), peak = 5582.41 (MB)
+total wire length = 13819819 um
+total wire length on LAYER li1 = 5372 um
+total wire length on LAYER met1 = 5043665 um
+total wire length on LAYER met2 = 7183380 um
+total wire length on LAYER met3 = 649858 um
+total wire length on LAYER met4 = 937543 um
+total wire length on LAYER met5 = 0 um
+total number of vias = 1657562
+up-via summary (total 1657562):
+
+--------------------------
+ FR_MASTERSLICE 0
+ li1 741595
+ met1 822738
+ met2 74508
+ met3 18721
+ met4 0
+--------------------------
+ 1657562
+
+
+start 27th optimization iteration ...
+ completing 10% with 12 violations
+ elapsed time = 00:00:05, memory = 3920.25 (MB)
+ completing 20% with 12 violations
+ elapsed time = 00:00:11, memory = 3920.25 (MB)
+ completing 30% with 12 violations
+ elapsed time = 00:00:17, memory = 3920.25 (MB)
+ completing 40% with 12 violations
+ elapsed time = 00:00:23, memory = 3920.25 (MB)
+ completing 50% with 12 violations
+ elapsed time = 00:00:29, memory = 3920.25 (MB)
+ completing 60% with 12 violations
+ elapsed time = 00:00:35, memory = 3920.25 (MB)
+ completing 70% with 12 violations
+ elapsed time = 00:00:40, memory = 3920.25 (MB)
+ completing 80% with 12 violations
+ elapsed time = 00:00:46, memory = 3920.25 (MB)
+ completing 90% with 12 violations
+ elapsed time = 00:00:52, memory = 3920.25 (MB)
+ completing 100% with 12 violations
+ elapsed time = 00:00:58, memory = 3920.25 (MB)
+ number of violations = 12
+cpu time = 00:05:41, elapsed time = 00:00:58, memory = 3920.25 (MB), peak = 5582.41 (MB)
+total wire length = 13819820 um
+total wire length on LAYER li1 = 5372 um
+total wire length on LAYER met1 = 5043654 um
+total wire length on LAYER met2 = 7183399 um
+total wire length on LAYER met3 = 649851 um
+total wire length on LAYER met4 = 937543 um
+total wire length on LAYER met5 = 0 um
+total number of vias = 1657563
+up-via summary (total 1657563):
+
+--------------------------
+ FR_MASTERSLICE 0
+ li1 741595
+ met1 822741
+ met2 74506
+ met3 18721
+ met4 0
+--------------------------
+ 1657563
+
+
+start 28th optimization iteration ...
+ completing 10% with 12 violations
+ elapsed time = 00:00:05, memory = 3920.25 (MB)
+ completing 20% with 12 violations
+ elapsed time = 00:00:11, memory = 3926.43 (MB)
+ completing 30% with 12 violations
+ elapsed time = 00:00:17, memory = 3882.10 (MB)
+ completing 40% with 12 violations
+ elapsed time = 00:00:22, memory = 3882.10 (MB)
+ completing 50% with 12 violations
+ elapsed time = 00:00:28, memory = 3882.36 (MB)
+ completing 60% with 12 violations
+ elapsed time = 00:00:34, memory = 3882.36 (MB)
+ completing 70% with 12 violations
+ elapsed time = 00:00:40, memory = 3882.43 (MB)
+ completing 80% with 12 violations
+ elapsed time = 00:00:46, memory = 3882.43 (MB)
+ completing 90% with 12 violations
+ elapsed time = 00:00:52, memory = 3882.43 (MB)
+ completing 100% with 12 violations
+ elapsed time = 00:00:58, memory = 3904.09 (MB)
+ number of violations = 12
+cpu time = 00:05:42, elapsed time = 00:00:58, memory = 3904.09 (MB), peak = 5582.41 (MB)
+total wire length = 13819823 um
+total wire length on LAYER li1 = 5372 um
+total wire length on LAYER met1 = 5043663 um
+total wire length on LAYER met2 = 7183386 um
+total wire length on LAYER met3 = 649859 um
+total wire length on LAYER met4 = 937543 um
+total wire length on LAYER met5 = 0 um
+total number of vias = 1657560
+up-via summary (total 1657560):
+
+--------------------------
+ FR_MASTERSLICE 0
+ li1 741595
+ met1 822734
+ met2 74510
+ met3 18721
+ met4 0
+--------------------------
+ 1657560
+
+
+start 29th optimization iteration ...
+ completing 10% with 12 violations
+ elapsed time = 00:00:05, memory = 3904.09 (MB)
+ completing 20% with 12 violations
+ elapsed time = 00:00:11, memory = 3904.17 (MB)
+ completing 30% with 12 violations
+ elapsed time = 00:00:16, memory = 3904.17 (MB)
+ completing 40% with 12 violations
+ elapsed time = 00:00:22, memory = 3904.17 (MB)
+ completing 50% with 12 violations
+ elapsed time = 00:00:28, memory = 3904.17 (MB)
+ completing 60% with 12 violations
+ elapsed time = 00:00:33, memory = 3904.17 (MB)
+ completing 70% with 12 violations
+ elapsed time = 00:00:39, memory = 3904.17 (MB)
+ completing 80% with 12 violations
+ elapsed time = 00:00:45, memory = 3904.17 (MB)
+ completing 90% with 12 violations
+ elapsed time = 00:00:51, memory = 3904.17 (MB)
+ completing 100% with 12 violations
+ elapsed time = 00:00:56, memory = 3904.17 (MB)
+ number of violations = 12
+cpu time = 00:05:35, elapsed time = 00:00:57, memory = 3904.17 (MB), peak = 5582.41 (MB)
+total wire length = 13819820 um
+total wire length on LAYER li1 = 5372 um
+total wire length on LAYER met1 = 5043652 um
+total wire length on LAYER met2 = 7183392 um
+total wire length on LAYER met3 = 649859 um
+total wire length on LAYER met4 = 937543 um
+total wire length on LAYER met5 = 0 um
+total number of vias = 1657567
+up-via summary (total 1657567):
+
+--------------------------
+ FR_MASTERSLICE 0
+ li1 741595
+ met1 822740
+ met2 74511
+ met3 18721
+ met4 0
+--------------------------
+ 1657567
+
+
+start 30th optimization iteration ...
+ completing 10% with 12 violations
+ elapsed time = 00:00:05, memory = 3904.17 (MB)
+ completing 20% with 12 violations
+ elapsed time = 00:00:10, memory = 3904.17 (MB)
+ completing 30% with 12 violations
+ elapsed time = 00:00:16, memory = 3904.17 (MB)
+ completing 40% with 12 violations
+ elapsed time = 00:00:22, memory = 3904.17 (MB)
+ completing 50% with 12 violations
+ elapsed time = 00:00:28, memory = 3904.68 (MB)
+ completing 60% with 12 violations
+ elapsed time = 00:00:34, memory = 3904.68 (MB)
+ completing 70% with 12 violations
+ elapsed time = 00:00:39, memory = 3904.68 (MB)
+ completing 80% with 12 violations
+ elapsed time = 00:00:45, memory = 3904.68 (MB)
+ completing 90% with 12 violations
+ elapsed time = 00:00:51, memory = 3904.68 (MB)
+ completing 100% with 12 violations
+ elapsed time = 00:00:57, memory = 3904.68 (MB)
+ number of violations = 12
+cpu time = 00:05:40, elapsed time = 00:00:58, memory = 3904.68 (MB), peak = 5582.41 (MB)
+total wire length = 13819823 um
+total wire length on LAYER li1 = 5372 um
+total wire length on LAYER met1 = 5043662 um
+total wire length on LAYER met2 = 7183385 um
+total wire length on LAYER met3 = 649859 um
+total wire length on LAYER met4 = 937543 um
+total wire length on LAYER met5 = 0 um
+total number of vias = 1657562
+up-via summary (total 1657562):
+
+--------------------------
+ FR_MASTERSLICE 0
+ li1 741595
+ met1 822736
+ met2 74510
+ met3 18721
+ met4 0
+--------------------------
+ 1657562
+
+
+start 31st optimization iteration ...
+ completing 10% with 12 violations
+ elapsed time = 00:00:05, memory = 3904.68 (MB)
+ completing 20% with 12 violations
+ elapsed time = 00:00:11, memory = 3904.76 (MB)
+ completing 30% with 12 violations
+ elapsed time = 00:00:16, memory = 3904.76 (MB)
+ completing 40% with 12 violations
+ elapsed time = 00:00:22, memory = 3904.76 (MB)
+ completing 50% with 12 violations
+ elapsed time = 00:00:28, memory = 3904.76 (MB)
+ completing 60% with 12 violations
+ elapsed time = 00:00:34, memory = 3904.76 (MB)
+ completing 70% with 12 violations
+ elapsed time = 00:00:39, memory = 3905.79 (MB)
+ completing 80% with 12 violations
+ elapsed time = 00:00:45, memory = 3905.79 (MB)
+ completing 90% with 12 violations
+ elapsed time = 00:00:51, memory = 3905.79 (MB)
+ completing 100% with 12 violations
+ elapsed time = 00:00:57, memory = 3905.79 (MB)
+ number of violations = 12
+cpu time = 00:05:39, elapsed time = 00:00:57, memory = 3905.79 (MB), peak = 5582.41 (MB)
+total wire length = 13819817 um
+total wire length on LAYER li1 = 5372 um
+total wire length on LAYER met1 = 5043656 um
+total wire length on LAYER met2 = 7183386 um
+total wire length on LAYER met3 = 649859 um
+total wire length on LAYER met4 = 937543 um
+total wire length on LAYER met5 = 0 um
+total number of vias = 1657561
+up-via summary (total 1657561):
+
+--------------------------
+ FR_MASTERSLICE 0
+ li1 741595
+ met1 822735
+ met2 74510
+ met3 18721
+ met4 0
+--------------------------
+ 1657561
+
+
+start 32nd optimization iteration ...
+ completing 10% with 12 violations
+ elapsed time = 00:00:05, memory = 3905.79 (MB)
+ completing 20% with 12 violations
+ elapsed time = 00:00:11, memory = 3905.79 (MB)
+ completing 30% with 12 violations
+ elapsed time = 00:00:16, memory = 3905.79 (MB)
+ completing 40% with 12 violations
+ elapsed time = 00:00:22, memory = 3905.79 (MB)
+ completing 50% with 12 violations
+ elapsed time = 00:00:28, memory = 3905.79 (MB)
+ completing 60% with 12 violations
+ elapsed time = 00:00:33, memory = 3905.79 (MB)
+ completing 70% with 12 violations
+ elapsed time = 00:00:39, memory = 3905.79 (MB)
+ completing 80% with 12 violations
+ elapsed time = 00:00:45, memory = 3905.91 (MB)
+ completing 90% with 12 violations
+ elapsed time = 00:00:51, memory = 3905.91 (MB)
+ completing 100% with 12 violations
+ elapsed time = 00:00:57, memory = 3905.91 (MB)
+ number of violations = 12
+cpu time = 00:05:37, elapsed time = 00:00:57, memory = 3905.91 (MB), peak = 5582.41 (MB)
+total wire length = 13819810 um
+total wire length on LAYER li1 = 5372 um
+total wire length on LAYER met1 = 5043655 um
+total wire length on LAYER met2 = 7183380 um
+total wire length on LAYER met3 = 649859 um
+total wire length on LAYER met4 = 937543 um
+total wire length on LAYER met5 = 0 um
+total number of vias = 1657559
+up-via summary (total 1657559):
+
+--------------------------
+ FR_MASTERSLICE 0
+ li1 741595
+ met1 822733
+ met2 74510
+ met3 18721
+ met4 0
+--------------------------
+ 1657559
+
+
+start 33rd optimization iteration ...
+ completing 10% with 12 violations
+ elapsed time = 00:00:07, memory = 3905.91 (MB)
+ completing 20% with 12 violations
+ elapsed time = 00:00:14, memory = 3905.91 (MB)
+ completing 30% with 10 violations
+ elapsed time = 00:00:21, memory = 3905.91 (MB)
+ completing 40% with 10 violations
+ elapsed time = 00:00:28, memory = 3905.91 (MB)
+ completing 50% with 8 violations
+ elapsed time = 00:00:35, memory = 3905.91 (MB)
+ completing 60% with 8 violations
+ elapsed time = 00:00:42, memory = 3905.91 (MB)
+ completing 70% with 8 violations
+ elapsed time = 00:00:49, memory = 3905.91 (MB)
+ completing 80% with 8 violations
+ elapsed time = 00:00:57, memory = 3905.91 (MB)
+ completing 90% with 8 violations
+ elapsed time = 00:01:03, memory = 3905.91 (MB)
+ completing 100% with 6 violations
+ elapsed time = 00:01:11, memory = 3905.91 (MB)
+ number of violations = 6
+cpu time = 00:06:55, elapsed time = 00:01:11, memory = 3905.91 (MB), peak = 5582.41 (MB)
+total wire length = 13819832 um
+total wire length on LAYER li1 = 5371 um
+total wire length on LAYER met1 = 5043596 um
+total wire length on LAYER met2 = 7183360 um
+total wire length on LAYER met3 = 649931 um
+total wire length on LAYER met4 = 937573 um
+total wire length on LAYER met5 = 0 um
+total number of vias = 1657602
+up-via summary (total 1657602):
+
+--------------------------
+ FR_MASTERSLICE 0
+ li1 741593
+ met1 822770
+ met2 74519
+ met3 18720
+ met4 0
+--------------------------
+ 1657602
+
+
+start 34th optimization iteration ...
+ completing 10% with 6 violations
+ elapsed time = 00:00:05, memory = 3905.91 (MB)
+ completing 20% with 6 violations
+ elapsed time = 00:00:11, memory = 3905.91 (MB)
+ completing 30% with 6 violations
+ elapsed time = 00:00:18, memory = 3866.21 (MB)
+ completing 40% with 6 violations
+ elapsed time = 00:00:23, memory = 3866.21 (MB)
+ completing 50% with 6 violations
+ elapsed time = 00:00:29, memory = 3866.98 (MB)
+ completing 60% with 6 violations
+ elapsed time = 00:00:35, memory = 3867.24 (MB)
+ completing 70% with 6 violations
+ elapsed time = 00:00:41, memory = 3867.27 (MB)
+ completing 80% with 6 violations
+ elapsed time = 00:00:47, memory = 3867.27 (MB)
+ completing 90% with 6 violations
+ elapsed time = 00:00:52, memory = 3867.27 (MB)
+ completing 100% with 6 violations
+ elapsed time = 00:00:58, memory = 3867.27 (MB)
+ number of violations = 6
+cpu time = 00:05:42, elapsed time = 00:00:58, memory = 3867.27 (MB), peak = 5582.41 (MB)
+total wire length = 13819832 um
+total wire length on LAYER li1 = 5371 um
+total wire length on LAYER met1 = 5043596 um
+total wire length on LAYER met2 = 7183360 um
+total wire length on LAYER met3 = 649931 um
+total wire length on LAYER met4 = 937573 um
+total wire length on LAYER met5 = 0 um
+total number of vias = 1657602
+up-via summary (total 1657602):
+
+--------------------------
+ FR_MASTERSLICE 0
+ li1 741593
+ met1 822770
+ met2 74519
+ met3 18720
+ met4 0
+--------------------------
+ 1657602
+
+
+start 35th optimization iteration ...
+ completing 10% with 6 violations
+ elapsed time = 00:00:05, memory = 3867.27 (MB)
+ completing 20% with 6 violations
+ elapsed time = 00:00:11, memory = 3887.63 (MB)
+ completing 30% with 6 violations
+ elapsed time = 00:00:16, memory = 3887.63 (MB)
+ completing 40% with 6 violations
+ elapsed time = 00:00:22, memory = 3887.71 (MB)
+ completing 50% with 6 violations
+ elapsed time = 00:00:28, memory = 3887.71 (MB)
+ completing 60% with 6 violations
+ elapsed time = 00:00:34, memory = 3887.71 (MB)
+ completing 70% with 6 violations
+ elapsed time = 00:00:39, memory = 3887.79 (MB)
+ completing 80% with 6 violations
+ elapsed time = 00:00:45, memory = 3887.79 (MB)
+ completing 90% with 6 violations
+ elapsed time = 00:00:50, memory = 3887.79 (MB)
+ completing 100% with 6 violations
+ elapsed time = 00:00:56, memory = 3887.79 (MB)
+ number of violations = 6
+cpu time = 00:05:34, elapsed time = 00:00:56, memory = 3887.79 (MB), peak = 5582.41 (MB)
+total wire length = 13819843 um
+total wire length on LAYER li1 = 5371 um
+total wire length on LAYER met1 = 5043597 um
+total wire length on LAYER met2 = 7183360 um
+total wire length on LAYER met3 = 649941 um
+total wire length on LAYER met4 = 937573 um
+total wire length on LAYER met5 = 0 um
+total number of vias = 1657606
+up-via summary (total 1657606):
+
+--------------------------
+ FR_MASTERSLICE 0
+ li1 741593
+ met1 822774
+ met2 74519
+ met3 18720
+ met4 0
+--------------------------
+ 1657606
+
+
+start 36th optimization iteration ...
+ completing 10% with 6 violations
+ elapsed time = 00:00:05, memory = 3887.79 (MB)
+ completing 20% with 6 violations
+ elapsed time = 00:00:11, memory = 3887.79 (MB)
+ completing 30% with 6 violations
+ elapsed time = 00:00:16, memory = 3887.79 (MB)
+ completing 40% with 6 violations
+ elapsed time = 00:00:22, memory = 3887.79 (MB)
+ completing 50% with 6 violations
+ elapsed time = 00:00:28, memory = 3887.79 (MB)
+ completing 60% with 6 violations
+ elapsed time = 00:00:34, memory = 3887.79 (MB)
+ completing 70% with 6 violations
+ elapsed time = 00:00:39, memory = 3887.79 (MB)
+ completing 80% with 6 violations
+ elapsed time = 00:00:45, memory = 3887.79 (MB)
+ completing 90% with 6 violations
+ elapsed time = 00:00:51, memory = 3887.79 (MB)
+ completing 100% with 6 violations
+ elapsed time = 00:00:57, memory = 3887.79 (MB)
+ number of violations = 6
+cpu time = 00:05:36, elapsed time = 00:00:57, memory = 3887.79 (MB), peak = 5582.41 (MB)
+total wire length = 13819841 um
+total wire length on LAYER li1 = 5371 um
+total wire length on LAYER met1 = 5043593 um
+total wire length on LAYER met2 = 7183362 um
+total wire length on LAYER met3 = 649941 um
+total wire length on LAYER met4 = 937573 um
+total wire length on LAYER met5 = 0 um
+total number of vias = 1657604
+up-via summary (total 1657604):
+
+--------------------------
+ FR_MASTERSLICE 0
+ li1 741593
+ met1 822772
+ met2 74519
+ met3 18720
+ met4 0
+--------------------------
+ 1657604
+
+
+start 37th optimization iteration ...
+ completing 10% with 6 violations
+ elapsed time = 00:00:05, memory = 3887.79 (MB)
+ completing 20% with 6 violations
+ elapsed time = 00:00:11, memory = 3887.79 (MB)
+ completing 30% with 6 violations
+ elapsed time = 00:00:16, memory = 3887.97 (MB)
+ completing 40% with 6 violations
+ elapsed time = 00:00:22, memory = 3887.97 (MB)
+ completing 50% with 6 violations
+ elapsed time = 00:00:28, memory = 3887.97 (MB)
+ completing 60% with 6 violations
+ elapsed time = 00:00:33, memory = 3887.97 (MB)
+ completing 70% with 6 violations
+ elapsed time = 00:00:39, memory = 3887.97 (MB)
+ completing 80% with 6 violations
+ elapsed time = 00:00:45, memory = 3887.97 (MB)
+ completing 90% with 6 violations
+ elapsed time = 00:00:51, memory = 3887.97 (MB)
+ completing 100% with 6 violations
+ elapsed time = 00:00:57, memory = 3887.97 (MB)
+ number of violations = 6
+cpu time = 00:05:37, elapsed time = 00:00:57, memory = 3887.97 (MB), peak = 5582.41 (MB)
+total wire length = 13819839 um
+total wire length on LAYER li1 = 5371 um
+total wire length on LAYER met1 = 5043586 um
+total wire length on LAYER met2 = 7183366 um
+total wire length on LAYER met3 = 649942 um
+total wire length on LAYER met4 = 937573 um
+total wire length on LAYER met5 = 0 um
+total number of vias = 1657609
+up-via summary (total 1657609):
+
+--------------------------
+ FR_MASTERSLICE 0
+ li1 741593
+ met1 822776
+ met2 74520
+ met3 18720
+ met4 0
+--------------------------
+ 1657609
+
+
+start 38th optimization iteration ...
+ completing 10% with 6 violations
+ elapsed time = 00:00:05, memory = 3887.97 (MB)
+ completing 20% with 6 violations
+ elapsed time = 00:00:11, memory = 3887.97 (MB)
+ completing 30% with 6 violations
+ elapsed time = 00:00:16, memory = 3887.97 (MB)
+ completing 40% with 6 violations
+ elapsed time = 00:00:22, memory = 3887.97 (MB)
+ completing 50% with 6 violations
+ elapsed time = 00:00:28, memory = 3888.48 (MB)
+ completing 60% with 6 violations
+ elapsed time = 00:00:33, memory = 3888.48 (MB)
+ completing 70% with 6 violations
+ elapsed time = 00:00:39, memory = 3888.48 (MB)
+ completing 80% with 6 violations
+ elapsed time = 00:00:44, memory = 3888.48 (MB)
+ completing 90% with 6 violations
+ elapsed time = 00:00:50, memory = 3888.48 (MB)
+ completing 100% with 6 violations
+ elapsed time = 00:00:56, memory = 3888.48 (MB)
+ number of violations = 6
+cpu time = 00:05:32, elapsed time = 00:00:56, memory = 3888.48 (MB), peak = 5582.41 (MB)
+total wire length = 13819845 um
+total wire length on LAYER li1 = 5371 um
+total wire length on LAYER met1 = 5043598 um
+total wire length on LAYER met2 = 7183361 um
+total wire length on LAYER met3 = 649941 um
+total wire length on LAYER met4 = 937573 um
+total wire length on LAYER met5 = 0 um
+total number of vias = 1657604
+up-via summary (total 1657604):
+
+--------------------------
+ FR_MASTERSLICE 0
+ li1 741593
+ met1 822772
+ met2 74519
+ met3 18720
+ met4 0
+--------------------------
+ 1657604
+
+
+start 39th optimization iteration ...
+ completing 10% with 6 violations
+ elapsed time = 00:00:05, memory = 3888.48 (MB)
+ completing 20% with 6 violations
+ elapsed time = 00:00:11, memory = 3888.70 (MB)
+ completing 30% with 6 violations
+ elapsed time = 00:00:15, memory = 3888.70 (MB)
+ completing 40% with 6 violations
+ elapsed time = 00:00:21, memory = 3888.70 (MB)
+ completing 50% with 6 violations
+ elapsed time = 00:00:28, memory = 3888.70 (MB)
+ completing 60% with 6 violations
+ elapsed time = 00:00:33, memory = 3888.70 (MB)
+ completing 70% with 6 violations
+ elapsed time = 00:00:39, memory = 3891.01 (MB)
+ completing 80% with 6 violations
+ elapsed time = 00:00:44, memory = 3891.01 (MB)
+ completing 90% with 6 violations
+ elapsed time = 00:00:50, memory = 3891.01 (MB)
+ completing 100% with 6 violations
+ elapsed time = 00:00:56, memory = 3891.01 (MB)
+ number of violations = 6
+cpu time = 00:05:32, elapsed time = 00:00:56, memory = 3891.01 (MB), peak = 5582.41 (MB)
+total wire length = 13819840 um
+total wire length on LAYER li1 = 5371 um
+total wire length on LAYER met1 = 5043593 um
+total wire length on LAYER met2 = 7183361 um
+total wire length on LAYER met3 = 649941 um
+total wire length on LAYER met4 = 937573 um
+total wire length on LAYER met5 = 0 um
+total number of vias = 1657603
+up-via summary (total 1657603):
+
+--------------------------
+ FR_MASTERSLICE 0
+ li1 741593
+ met1 822771
+ met2 74519
+ met3 18720
+ met4 0
+--------------------------
+ 1657603
+
+
+start 40th optimization iteration ...
+ completing 10% with 6 violations
+ elapsed time = 00:00:05, memory = 3891.01 (MB)
+ completing 20% with 6 violations
+ elapsed time = 00:00:11, memory = 3891.01 (MB)
+ completing 30% with 6 violations
+ elapsed time = 00:00:16, memory = 3891.01 (MB)
+ completing 40% with 6 violations
+ elapsed time = 00:00:22, memory = 3891.01 (MB)
+ completing 50% with 6 violations
+ elapsed time = 00:00:28, memory = 3891.01 (MB)
+ completing 60% with 6 violations
+ elapsed time = 00:00:33, memory = 3891.01 (MB)
+ completing 70% with 6 violations
+ elapsed time = 00:00:39, memory = 3891.01 (MB)
+ completing 80% with 6 violations
+ elapsed time = 00:00:45, memory = 3891.01 (MB)
+ completing 90% with 6 violations
+ elapsed time = 00:00:51, memory = 3891.01 (MB)
+ completing 100% with 6 violations
+ elapsed time = 00:00:57, memory = 3891.01 (MB)
+ number of violations = 6
+cpu time = 00:05:36, elapsed time = 00:00:57, memory = 3891.01 (MB), peak = 5582.41 (MB)
+total wire length = 13819840 um
+total wire length on LAYER li1 = 5371 um
+total wire length on LAYER met1 = 5043592 um
+total wire length on LAYER met2 = 7183361 um
+total wire length on LAYER met3 = 649942 um
+total wire length on LAYER met4 = 937573 um
+total wire length on LAYER met5 = 0 um
+total number of vias = 1657603
+up-via summary (total 1657603):
+
+--------------------------
+ FR_MASTERSLICE 0
+ li1 741593
+ met1 822769
+ met2 74521
+ met3 18720
+ met4 0
+--------------------------
+ 1657603
+
+
+start 41st optimization iteration ...
+ completing 10% with 6 violations
+ elapsed time = 00:00:06, memory = 3891.01 (MB)
+ completing 20% with 4 violations
+ elapsed time = 00:00:14, memory = 3891.01 (MB)
+ completing 30% with 4 violations
+ elapsed time = 00:00:21, memory = 3891.01 (MB)
+ completing 40% with 4 violations
+ elapsed time = 00:00:28, memory = 3891.01 (MB)
+ completing 50% with 4 violations
+ elapsed time = 00:00:35, memory = 3891.01 (MB)
+ completing 60% with 4 violations
+ elapsed time = 00:00:42, memory = 3891.01 (MB)
+ completing 70% with 4 violations
+ elapsed time = 00:00:50, memory = 3891.01 (MB)
+ completing 80% with 4 violations
+ elapsed time = 00:00:56, memory = 3891.01 (MB)
+ completing 90% with 4 violations
+ elapsed time = 00:01:03, memory = 3891.21 (MB)
+ completing 100% with 4 violations
+ elapsed time = 00:01:11, memory = 3891.21 (MB)
+ number of violations = 4
+cpu time = 00:06:53, elapsed time = 00:01:11, memory = 3891.21 (MB), peak = 5582.41 (MB)
+total wire length = 13819847 um
+total wire length on LAYER li1 = 5371 um
+total wire length on LAYER met1 = 5043585 um
+total wire length on LAYER met2 = 7183337 um
+total wire length on LAYER met3 = 649945 um
+total wire length on LAYER met4 = 937607 um
+total wire length on LAYER met5 = 0 um
+total number of vias = 1657610
+up-via summary (total 1657610):
+
+--------------------------
+ FR_MASTERSLICE 0
+ li1 741593
+ met1 822779
+ met2 74518
+ met3 18720
+ met4 0
+--------------------------
+ 1657610
+
+
+start 42nd optimization iteration ...
+ completing 10% with 4 violations
+ elapsed time = 00:00:05, memory = 3891.21 (MB)
+ completing 20% with 4 violations
+ elapsed time = 00:00:11, memory = 3891.21 (MB)
+ completing 30% with 4 violations
+ elapsed time = 00:00:17, memory = 3891.21 (MB)
+ completing 40% with 4 violations
+ elapsed time = 00:00:23, memory = 3891.21 (MB)
+ completing 50% with 4 violations
+ elapsed time = 00:00:28, memory = 3891.21 (MB)
+ completing 60% with 4 violations
+ elapsed time = 00:00:34, memory = 3891.21 (MB)
+ completing 70% with 4 violations
+ elapsed time = 00:00:40, memory = 3909.77 (MB)
+ completing 80% with 4 violations
+ elapsed time = 00:00:46, memory = 3867.54 (MB)
+ completing 90% with 4 violations
+ elapsed time = 00:00:52, memory = 3867.54 (MB)
+ completing 100% with 4 violations
+ elapsed time = 00:00:57, memory = 3867.54 (MB)
+ number of violations = 4
+cpu time = 00:05:40, elapsed time = 00:00:57, memory = 3867.54 (MB), peak = 5582.41 (MB)
+total wire length = 13819842 um
+total wire length on LAYER li1 = 5371 um
+total wire length on LAYER met1 = 5043555 um
+total wire length on LAYER met2 = 7183353 um
+total wire length on LAYER met3 = 649947 um
+total wire length on LAYER met4 = 937615 um
+total wire length on LAYER met5 = 0 um
+total number of vias = 1657615
+up-via summary (total 1657615):
+
+--------------------------
+ FR_MASTERSLICE 0
+ li1 741593
+ met1 822782
+ met2 74518
+ met3 18722
+ met4 0
+--------------------------
+ 1657615
+
+
+start 43rd optimization iteration ...
+ completing 10% with 4 violations
+ elapsed time = 00:00:05, memory = 3867.54 (MB)
+ completing 20% with 4 violations
+ elapsed time = 00:00:11, memory = 3867.54 (MB)
+ completing 30% with 4 violations
+ elapsed time = 00:00:16, memory = 3867.80 (MB)
+ completing 40% with 4 violations
+ elapsed time = 00:00:22, memory = 3867.80 (MB)
+ completing 50% with 4 violations
+ elapsed time = 00:00:28, memory = 3867.80 (MB)
+ completing 60% with 4 violations
+ elapsed time = 00:00:34, memory = 3867.80 (MB)
+ completing 70% with 4 violations
+ elapsed time = 00:00:39, memory = 3867.80 (MB)
+ completing 80% with 2 violations
+ elapsed time = 00:00:45, memory = 3867.80 (MB)
+ completing 90% with 2 violations
+ elapsed time = 00:00:51, memory = 3867.80 (MB)
+ completing 100% with 2 violations
+ elapsed time = 00:00:56, memory = 3867.80 (MB)
+ number of violations = 2
+cpu time = 00:05:35, elapsed time = 00:00:57, memory = 3867.80 (MB), peak = 5582.41 (MB)
+total wire length = 13819844 um
+total wire length on LAYER li1 = 5371 um
+total wire length on LAYER met1 = 5043553 um
+total wire length on LAYER met2 = 7183353 um
+total wire length on LAYER met3 = 649958 um
+total wire length on LAYER met4 = 937607 um
+total wire length on LAYER met5 = 0 um
+total number of vias = 1657613
+up-via summary (total 1657613):
+
+--------------------------
+ FR_MASTERSLICE 0
+ li1 741593
+ met1 822782
+ met2 74518
+ met3 18720
+ met4 0
+--------------------------
+ 1657613
+
+
+start 44th optimization iteration ...
+ completing 10% with 2 violations
+ elapsed time = 00:00:05, memory = 3867.80 (MB)
+ completing 20% with 2 violations
+ elapsed time = 00:00:11, memory = 3875.53 (MB)
+ completing 30% with 2 violations
+ elapsed time = 00:00:16, memory = 3843.21 (MB)
+ completing 40% with 2 violations
+ elapsed time = 00:00:22, memory = 3843.21 (MB)
+ completing 50% with 2 violations
+ elapsed time = 00:00:28, memory = 3843.21 (MB)
+ completing 60% with 2 violations
+ elapsed time = 00:00:34, memory = 3843.21 (MB)
+ completing 70% with 2 violations
+ elapsed time = 00:00:39, memory = 3843.21 (MB)
+ completing 80% with 2 violations
+ elapsed time = 00:00:45, memory = 3843.21 (MB)
+ completing 90% with 2 violations
+ elapsed time = 00:00:51, memory = 3843.45 (MB)
+ completing 100% with 2 violations
+ elapsed time = 00:00:56, memory = 3843.45 (MB)
+ number of violations = 2
+cpu time = 00:05:35, elapsed time = 00:00:56, memory = 3843.45 (MB), peak = 5582.41 (MB)
+total wire length = 13819844 um
+total wire length on LAYER li1 = 5371 um
+total wire length on LAYER met1 = 5043553 um
+total wire length on LAYER met2 = 7183353 um
+total wire length on LAYER met3 = 649958 um
+total wire length on LAYER met4 = 937607 um
+total wire length on LAYER met5 = 0 um
+total number of vias = 1657613
+up-via summary (total 1657613):
+
+--------------------------
+ FR_MASTERSLICE 0
+ li1 741593
+ met1 822782
+ met2 74518
+ met3 18720
+ met4 0
+--------------------------
+ 1657613
+
+
+start 45th optimization iteration ...
+ completing 10% with 2 violations
+ elapsed time = 00:00:05, memory = 3843.45 (MB)
+ completing 20% with 2 violations
+ elapsed time = 00:00:11, memory = 3843.45 (MB)
+ completing 30% with 2 violations
+ elapsed time = 00:00:16, memory = 3843.45 (MB)
+ completing 40% with 2 violations
+ elapsed time = 00:00:21, memory = 3843.45 (MB)
+ completing 50% with 2 violations
+ elapsed time = 00:00:27, memory = 3843.45 (MB)
+ completing 60% with 2 violations
+ elapsed time = 00:00:33, memory = 3843.58 (MB)
+ completing 70% with 2 violations
+ elapsed time = 00:00:38, memory = 3843.58 (MB)
+ completing 80% with 2 violations
+ elapsed time = 00:00:44, memory = 3843.58 (MB)
+ completing 90% with 2 violations
+ elapsed time = 00:00:50, memory = 3843.58 (MB)
+ completing 100% with 2 violations
+ elapsed time = 00:00:56, memory = 3843.58 (MB)
+ number of violations = 2
+cpu time = 00:05:31, elapsed time = 00:00:56, memory = 3843.58 (MB), peak = 5582.41 (MB)
+total wire length = 13819844 um
+total wire length on LAYER li1 = 5371 um
+total wire length on LAYER met1 = 5043551 um
+total wire length on LAYER met2 = 7183354 um
+total wire length on LAYER met3 = 649958 um
+total wire length on LAYER met4 = 937607 um
+total wire length on LAYER met5 = 0 um
+total number of vias = 1657615
+up-via summary (total 1657615):
+
+--------------------------
+ FR_MASTERSLICE 0
+ li1 741593
+ met1 822784
+ met2 74518
+ met3 18720
+ met4 0
+--------------------------
+ 1657615
+
+
+start 46th optimization iteration ...
+ completing 10% with 2 violations
+ elapsed time = 00:00:05, memory = 3843.58 (MB)
+ completing 20% with 2 violations
+ elapsed time = 00:00:11, memory = 3843.60 (MB)
+ completing 30% with 2 violations
+ elapsed time = 00:00:16, memory = 3843.60 (MB)
+ completing 40% with 2 violations
+ elapsed time = 00:00:21, memory = 3843.60 (MB)
+ completing 50% with 2 violations
+ elapsed time = 00:00:28, memory = 3843.60 (MB)
+ completing 60% with 2 violations
+ elapsed time = 00:00:33, memory = 3843.64 (MB)
+ completing 70% with 2 violations
+ elapsed time = 00:00:39, memory = 3843.64 (MB)
+ completing 80% with 2 violations
+ elapsed time = 00:00:45, memory = 3843.64 (MB)
+ completing 90% with 2 violations
+ elapsed time = 00:00:51, memory = 3843.64 (MB)
+ completing 100% with 2 violations
+ elapsed time = 00:00:56, memory = 3843.64 (MB)
+ number of violations = 2
+cpu time = 00:05:35, elapsed time = 00:00:56, memory = 3843.64 (MB), peak = 5582.41 (MB)
+total wire length = 13819844 um
+total wire length on LAYER li1 = 5371 um
+total wire length on LAYER met1 = 5043551 um
+total wire length on LAYER met2 = 7183354 um
+total wire length on LAYER met3 = 649958 um
+total wire length on LAYER met4 = 937607 um
+total wire length on LAYER met5 = 0 um
+total number of vias = 1657615
+up-via summary (total 1657615):
+
+--------------------------
+ FR_MASTERSLICE 0
+ li1 741593
+ met1 822784
+ met2 74518
+ met3 18720
+ met4 0
+--------------------------
+ 1657615
+
+
+start 47th optimization iteration ...
+ completing 10% with 2 violations
+ elapsed time = 00:00:05, memory = 3843.64 (MB)
+ completing 20% with 2 violations
+ elapsed time = 00:00:10, memory = 3843.64 (MB)
+ completing 30% with 2 violations
+ elapsed time = 00:00:15, memory = 3843.64 (MB)
+ completing 40% with 2 violations
+ elapsed time = 00:00:21, memory = 3843.64 (MB)
+ completing 50% with 2 violations
+ elapsed time = 00:00:27, memory = 3843.64 (MB)
+ completing 60% with 2 violations
+ elapsed time = 00:00:33, memory = 3843.64 (MB)
+ completing 70% with 2 violations
+ elapsed time = 00:00:38, memory = 3843.64 (MB)
+ completing 80% with 2 violations
+ elapsed time = 00:00:44, memory = 3843.64 (MB)
+ completing 90% with 2 violations
+ elapsed time = 00:00:50, memory = 3843.64 (MB)
+ completing 100% with 2 violations
+ elapsed time = 00:00:56, memory = 3843.64 (MB)
+ number of violations = 2
+cpu time = 00:05:30, elapsed time = 00:00:56, memory = 3843.64 (MB), peak = 5582.41 (MB)
+total wire length = 13819841 um
+total wire length on LAYER li1 = 5371 um
+total wire length on LAYER met1 = 5043552 um
+total wire length on LAYER met2 = 7183354 um
+total wire length on LAYER met3 = 649954 um
+total wire length on LAYER met4 = 937607 um
+total wire length on LAYER met5 = 0 um
+total number of vias = 1657616
+up-via summary (total 1657616):
+
+--------------------------
+ FR_MASTERSLICE 0
+ li1 741593
+ met1 822785
+ met2 74518
+ met3 18720
+ met4 0
+--------------------------
+ 1657616
+
+
+start 48th optimization iteration ...
+ completing 10% with 2 violations
+ elapsed time = 00:00:05, memory = 3843.64 (MB)
+ completing 20% with 2 violations
+ elapsed time = 00:00:11, memory = 3843.64 (MB)
+ completing 30% with 2 violations
+ elapsed time = 00:00:16, memory = 3843.64 (MB)
+ completing 40% with 2 violations
+ elapsed time = 00:00:22, memory = 3843.64 (MB)
+ completing 50% with 2 violations
+ elapsed time = 00:00:28, memory = 3843.64 (MB)
+ completing 60% with 2 violations
+ elapsed time = 00:00:33, memory = 3843.64 (MB)
+ completing 70% with 2 violations
+ elapsed time = 00:00:39, memory = 3843.64 (MB)
+ completing 80% with 2 violations
+ elapsed time = 00:00:44, memory = 3843.64 (MB)
+ completing 90% with 2 violations
+ elapsed time = 00:00:50, memory = 3843.64 (MB)
+ completing 100% with 2 violations
+ elapsed time = 00:00:56, memory = 3843.64 (MB)
+ number of violations = 2
+cpu time = 00:05:35, elapsed time = 00:00:57, memory = 3843.64 (MB), peak = 5582.41 (MB)
+total wire length = 13819838 um
+total wire length on LAYER li1 = 5371 um
+total wire length on LAYER met1 = 5043546 um
+total wire length on LAYER met2 = 7183358 um
+total wire length on LAYER met3 = 649954 um
+total wire length on LAYER met4 = 937607 um
+total wire length on LAYER met5 = 0 um
+total number of vias = 1657618
+up-via summary (total 1657618):
+
+--------------------------
+ FR_MASTERSLICE 0
+ li1 741593
+ met1 822787
+ met2 74518
+ met3 18720
+ met4 0
+--------------------------
+ 1657618
+
+
+start 49th optimization iteration ...
+ completing 10% with 2 violations
+ elapsed time = 00:00:07, memory = 3843.64 (MB)
+ completing 20% with 2 violations
+ elapsed time = 00:00:14, memory = 3843.64 (MB)
+ completing 30% with 2 violations
+ elapsed time = 00:00:21, memory = 3843.64 (MB)
+ completing 40% with 2 violations
+ elapsed time = 00:00:28, memory = 3843.64 (MB)
+ completing 50% with 2 violations
+ elapsed time = 00:00:35, memory = 3843.64 (MB)
+ completing 60% with 2 violations
+ elapsed time = 00:00:42, memory = 3843.64 (MB)
+ completing 70% with 2 violations
+ elapsed time = 00:00:50, memory = 3843.68 (MB)
+ completing 80% with 2 violations
+ elapsed time = 00:00:57, memory = 3843.68 (MB)
+ completing 90% with 2 violations
+ elapsed time = 00:01:04, memory = 3843.68 (MB)
+ completing 100% with 2 violations
+ elapsed time = 00:01:12, memory = 3843.68 (MB)
+ number of violations = 2
+cpu time = 00:06:57, elapsed time = 00:01:12, memory = 3843.68 (MB), peak = 5582.41 (MB)
+total wire length = 13819838 um
+total wire length on LAYER li1 = 5371 um
+total wire length on LAYER met1 = 5043546 um
+total wire length on LAYER met2 = 7183358 um
+total wire length on LAYER met3 = 649954 um
+total wire length on LAYER met4 = 937607 um
+total wire length on LAYER met5 = 0 um
+total number of vias = 1657618
+up-via summary (total 1657618):
+
+--------------------------
+ FR_MASTERSLICE 0
+ li1 741593
+ met1 822787
+ met2 74518
+ met3 18720
+ met4 0
+--------------------------
+ 1657618
+
+
+start 50th optimization iteration ...
+ completing 10% with 2 violations
+ elapsed time = 00:00:05, memory = 3843.68 (MB)
+ completing 20% with 2 violations
+ elapsed time = 00:00:11, memory = 3884.93 (MB)
+ completing 30% with 2 violations
+ elapsed time = 00:00:48, memory = 3843.18 (MB)
+ completing 40% with 2 violations
+ elapsed time = 00:00:54, memory = 3843.32 (MB)
+ completing 50% with 2 violations
+ elapsed time = 00:00:59, memory = 3843.32 (MB)
+ completing 60% with 2 violations
+ elapsed time = 00:01:05, memory = 3843.32 (MB)
+ completing 70% with 2 violations
+ elapsed time = 00:01:11, memory = 3843.32 (MB)
+ completing 80% with 2 violations
+ elapsed time = 00:01:16, memory = 3843.32 (MB)
+ completing 90% with 2 violations
+ elapsed time = 00:01:22, memory = 3843.57 (MB)
+ completing 100% with 2 violations
+ elapsed time = 00:01:28, memory = 3843.57 (MB)
+ number of violations = 2
+cpu time = 00:06:12, elapsed time = 00:01:28, memory = 3843.57 (MB), peak = 5582.41 (MB)
+total wire length = 13819838 um
+total wire length on LAYER li1 = 5371 um
+total wire length on LAYER met1 = 5043546 um
+total wire length on LAYER met2 = 7183358 um
+total wire length on LAYER met3 = 649954 um
+total wire length on LAYER met4 = 937607 um
+total wire length on LAYER met5 = 0 um
+total number of vias = 1657618
+up-via summary (total 1657618):
+
+--------------------------
+ FR_MASTERSLICE 0
+ li1 741593
+ met1 822787
+ met2 74518
+ met3 18720
+ met4 0
+--------------------------
+ 1657618
+
+
+start 51st optimization iteration ...
+ completing 10% with 2 violations
+ elapsed time = 00:00:05, memory = 3843.57 (MB)
+ completing 20% with 2 violations
+ elapsed time = 00:00:11, memory = 3843.57 (MB)
+ completing 30% with 2 violations
+ elapsed time = 00:00:17, memory = 3843.58 (MB)
+ completing 40% with 2 violations
+ elapsed time = 00:00:23, memory = 3843.58 (MB)
+ completing 50% with 2 violations
+ elapsed time = 00:00:29, memory = 3843.58 (MB)
+ completing 60% with 2 violations
+ elapsed time = 00:00:35, memory = 3843.58 (MB)
+ completing 70% with 2 violations
+ elapsed time = 00:00:40, memory = 3843.58 (MB)
+ completing 80% with 2 violations
+ elapsed time = 00:00:46, memory = 3843.58 (MB)
+ completing 90% with 2 violations
+ elapsed time = 00:00:51, memory = 3843.58 (MB)
+ completing 100% with 2 violations
+ elapsed time = 00:00:56, memory = 3843.58 (MB)
+ number of violations = 2
+cpu time = 00:05:35, elapsed time = 00:00:57, memory = 3843.58 (MB), peak = 5582.41 (MB)
+total wire length = 13819838 um
+total wire length on LAYER li1 = 5371 um
+total wire length on LAYER met1 = 5043544 um
+total wire length on LAYER met2 = 7183360 um
+total wire length on LAYER met3 = 649954 um
+total wire length on LAYER met4 = 937607 um
+total wire length on LAYER met5 = 0 um
+total number of vias = 1657619
+up-via summary (total 1657619):
+
+--------------------------
+ FR_MASTERSLICE 0
+ li1 741593
+ met1 822788
+ met2 74518
+ met3 18720
+ met4 0
+--------------------------
+ 1657619
+
+
+start 52nd optimization iteration ...
+ completing 10% with 2 violations
+ elapsed time = 00:00:05, memory = 3843.58 (MB)
+ completing 20% with 2 violations
+ elapsed time = 00:00:11, memory = 3847.19 (MB)
+ completing 30% with 0 violations
+ elapsed time = 00:00:17, memory = 3804.57 (MB)
+ completing 40% with 0 violations
+ elapsed time = 00:00:22, memory = 3804.57 (MB)
+ completing 50% with 0 violations
+ elapsed time = 00:00:28, memory = 3804.83 (MB)
+ completing 60% with 0 violations
+ elapsed time = 00:00:34, memory = 3804.83 (MB)
+ completing 70% with 0 violations
+ elapsed time = 00:00:39, memory = 3805.04 (MB)
+ completing 80% with 0 violations
+ elapsed time = 00:00:45, memory = 3805.04 (MB)
+ completing 90% with 0 violations
+ elapsed time = 00:00:51, memory = 3805.04 (MB)
+ completing 100% with 0 violations
+ elapsed time = 00:00:56, memory = 3805.04 (MB)
+ number of violations = 0
+cpu time = 00:05:35, elapsed time = 00:00:57, memory = 3805.04 (MB), peak = 5582.41 (MB)
+total wire length = 13819851 um
+total wire length on LAYER li1 = 5370 um
+total wire length on LAYER met1 = 5043557 um
+total wire length on LAYER met2 = 7183337 um
+total wire length on LAYER met3 = 649978 um
+total wire length on LAYER met4 = 937607 um
+total wire length on LAYER met5 = 0 um
+total number of vias = 1657614
+up-via summary (total 1657614):
+
+--------------------------
+ FR_MASTERSLICE 0
+ li1 741591
+ met1 822783
+ met2 74520
+ met3 18720
+ met4 0
+--------------------------
+ 1657614
+
+
+start 57th optimization iteration ...
+ completing 10% with 0 violations
+ elapsed time = 00:00:07, memory = 3805.04 (MB)
+ completing 20% with 0 violations
+ elapsed time = 00:00:14, memory = 3805.20 (MB)
+ completing 30% with 0 violations
+ elapsed time = 00:00:21, memory = 3805.20 (MB)
+ completing 40% with 0 violations
+ elapsed time = 00:00:28, memory = 3805.20 (MB)
+ completing 50% with 0 violations
+ elapsed time = 00:00:35, memory = 3805.42 (MB)
+ completing 60% with 0 violations
+ elapsed time = 00:00:42, memory = 3805.42 (MB)
+ completing 70% with 0 violations
+ elapsed time = 00:00:50, memory = 3805.42 (MB)
+ completing 80% with 0 violations
+ elapsed time = 00:00:57, memory = 3805.42 (MB)
+ completing 90% with 0 violations
+ elapsed time = 00:01:04, memory = 3805.42 (MB)
+ completing 100% with 0 violations
+ elapsed time = 00:01:11, memory = 3805.42 (MB)
+ number of violations = 0
+cpu time = 00:06:58, elapsed time = 00:01:12, memory = 3805.42 (MB), peak = 5582.41 (MB)
+total wire length = 13819851 um
+total wire length on LAYER li1 = 5370 um
+total wire length on LAYER met1 = 5043557 um
+total wire length on LAYER met2 = 7183337 um
+total wire length on LAYER met3 = 649978 um
+total wire length on LAYER met4 = 937607 um
+total wire length on LAYER met5 = 0 um
+total number of vias = 1657614
+up-via summary (total 1657614):
+
+--------------------------
+ FR_MASTERSLICE 0
+ li1 741591
+ met1 822783
+ met2 74520
+ met3 18720
+ met4 0
+--------------------------
+ 1657614
+
+
+complete detail routing
+total wire length = 13819851 um
+total wire length on LAYER li1 = 5370 um
+total wire length on LAYER met1 = 5043557 um
+total wire length on LAYER met2 = 7183337 um
+total wire length on LAYER met3 = 649978 um
+total wire length on LAYER met4 = 937607 um
+total wire length on LAYER met5 = 0 um
+total number of vias = 1657614
+up-via summary (total 1657614):
+
+--------------------------
+ FR_MASTERSLICE 0
+ li1 741591
+ met1 822783
+ met2 74520
+ met3 18720
+ met4 0
+--------------------------
+ 1657614
+
+cpu time = 12:28:54, elapsed time = 02:24:37, memory = 3805.42 (MB), peak = 5582.41 (MB)
+
+post processing ...
+
+Runtime taken (hrt): 8842.71
diff --git a/openlane/user_proj_example/results/logs/routing/tritonRoute_runtime.txt b/openlane/user_proj_example/results/logs/routing/tritonRoute_runtime.txt
new file mode 100644
index 0000000..b80971b
--- /dev/null
+++ b/openlane/user_proj_example/results/logs/routing/tritonRoute_runtime.txt
@@ -0,0 +1 @@
+2h27m27s341ms
diff --git a/openlane/user_proj_example/results/logs/synthesis/opensta.log b/openlane/user_proj_example/results/logs/synthesis/opensta.log
new file mode 100644
index 0000000..e0721ec
--- /dev/null
+++ b/openlane/user_proj_example/results/logs/synthesis/opensta.log
@@ -0,0 +1,33 @@
+OpenSTA 2.2.0 7662c12482 Copyright (c) 2019, Parallax Software, Inc.
+License GPLv3: GNU GPL version 3 <http://gnu.org/licenses/gpl.html>
+
+This is free software, and you are free to change and redistribute it
+under certain conditions; type `show_copying' for details.
+This program comes with ABSOLUTELY NO WARRANTY; for details type `show_warranty'.
+Error: cannot open '/.sta'.
+Warning: /mnt/data/workspace/pdk/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_n40C_1v95.lib, line 31 default_operating_condition ff_n40C_1v95 not found.
+Warning: /mnt/data/workspace/pdk/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_100C_1v60.lib, line 32 default_operating_condition ss_100C_1v60 not found.
+create_clock [get_ports $::env(CLOCK_PORT)] -name $::env(CLOCK_PORT) -period $::env(CLOCK_PERIOD)
+set input_delay_value [expr $::env(CLOCK_PERIOD) * $::env(IO_PCT)]
+set output_delay_value [expr $::env(CLOCK_PERIOD) * $::env(IO_PCT)]
+puts "\[INFO\]: Setting output delay to: $output_delay_value"
+[INFO]: Setting output delay to: 4.0
+puts "\[INFO\]: Setting input delay to: $input_delay_value"
+[INFO]: Setting input delay to: 4.0
+set clk_indx [lsearch [all_inputs] [get_port $::env(CLOCK_PORT)]]
+#set rst_indx [lsearch [all_inputs] [get_port resetn]]
+set all_inputs_wo_clk [lreplace [all_inputs] $clk_indx $clk_indx]
+#set all_inputs_wo_clk_rst [lreplace $all_inputs_wo_clk $rst_indx $rst_indx]
+set all_inputs_wo_clk_rst $all_inputs_wo_clk
+# correct resetn
+set_input_delay $input_delay_value -clock [get_clocks $::env(CLOCK_PORT)] $all_inputs_wo_clk_rst
+#set_input_delay 0.0 -clock [get_clocks $::env(CLOCK_PORT)] {resetn}
+set_output_delay $output_delay_value -clock [get_clocks $::env(CLOCK_PORT)] [all_outputs]
+# TODO set this as parameter
+set_driving_cell -lib_cell $::env(SYNTH_DRIVING_CELL) -pin $::env(SYNTH_DRIVING_CELL_PIN) [all_inputs]
+set cap_load [expr $::env(SYNTH_CAP_LOAD) / 1000.0]
+puts "\[INFO\]: Setting load to: $cap_load"
+[INFO]: Setting load to: 0.01765
+set_load $cap_load [all_outputs]
+tns 0.00
+wns 0.00
diff --git a/openlane/user_proj_example/results/logs/synthesis/opensta_post_openphysyn.log b/openlane/user_proj_example/results/logs/synthesis/opensta_post_openphysyn.log
new file mode 100644
index 0000000..1cc0dc4
--- /dev/null
+++ b/openlane/user_proj_example/results/logs/synthesis/opensta_post_openphysyn.log
@@ -0,0 +1,34 @@
+OpenSTA 2.2.0 7662c12482 Copyright (c) 2019, Parallax Software, Inc.
+License GPLv3: GNU GPL version 3 <http://gnu.org/licenses/gpl.html>
+
+This is free software, and you are free to change and redistribute it
+under certain conditions; type `show_copying' for details.
+This program comes with ABSOLUTELY NO WARRANTY; for details type `show_warranty'.
+Error: cannot open '/.sta'.
+Warning: /mnt/data/workspace/pdk/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_n40C_1v95.lib, line 31 default_operating_condition ff_n40C_1v95 not found.
+Warning: /mnt/data/workspace/pdk/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_100C_1v60.lib, line 32 default_operating_condition ss_100C_1v60 not found.
+Warning: /project/openlane/user_proj_example/runs/16-12_10-43/results/synthesis/user_proj_example.synthesis_optimized.v, line 598335 module sky130_fd_sc_hd__tapvpwrvgnd_1 not found. Creating black box for PHY_2262.
+create_clock [get_ports $::env(CLOCK_PORT)] -name $::env(CLOCK_PORT) -period $::env(CLOCK_PERIOD)
+set input_delay_value [expr $::env(CLOCK_PERIOD) * $::env(IO_PCT)]
+set output_delay_value [expr $::env(CLOCK_PERIOD) * $::env(IO_PCT)]
+puts "\[INFO\]: Setting output delay to: $output_delay_value"
+[INFO]: Setting output delay to: 4.0
+puts "\[INFO\]: Setting input delay to: $input_delay_value"
+[INFO]: Setting input delay to: 4.0
+set clk_indx [lsearch [all_inputs] [get_port $::env(CLOCK_PORT)]]
+#set rst_indx [lsearch [all_inputs] [get_port resetn]]
+set all_inputs_wo_clk [lreplace [all_inputs] $clk_indx $clk_indx]
+#set all_inputs_wo_clk_rst [lreplace $all_inputs_wo_clk $rst_indx $rst_indx]
+set all_inputs_wo_clk_rst $all_inputs_wo_clk
+# correct resetn
+set_input_delay $input_delay_value -clock [get_clocks $::env(CLOCK_PORT)] $all_inputs_wo_clk_rst
+#set_input_delay 0.0 -clock [get_clocks $::env(CLOCK_PORT)] {resetn}
+set_output_delay $output_delay_value -clock [get_clocks $::env(CLOCK_PORT)] [all_outputs]
+# TODO set this as parameter
+set_driving_cell -lib_cell $::env(SYNTH_DRIVING_CELL) -pin $::env(SYNTH_DRIVING_CELL_PIN) [all_inputs]
+set cap_load [expr $::env(SYNTH_CAP_LOAD) / 1000.0]
+puts "\[INFO\]: Setting load to: $cap_load"
+[INFO]: Setting load to: 0.01765
+set_load $cap_load [all_outputs]
+tns 0.00
+wns 0.00
diff --git a/openlane/user_proj_example/results/logs/synthesis/opensta_spef.log b/openlane/user_proj_example/results/logs/synthesis/opensta_spef.log
new file mode 100644
index 0000000..e0b3a6d
--- /dev/null
+++ b/openlane/user_proj_example/results/logs/synthesis/opensta_spef.log
@@ -0,0 +1,36 @@
+OpenSTA 2.2.0 7662c12482 Copyright (c) 2019, Parallax Software, Inc.
+License GPLv3: GNU GPL version 3 <http://gnu.org/licenses/gpl.html>
+
+This is free software, and you are free to change and redistribute it
+under certain conditions; type `show_copying' for details.
+This program comes with ABSOLUTELY NO WARRANTY; for details type `show_warranty'.
+Error: cannot open '/.sta'.
+Warning: /mnt/data/workspace/pdk/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_n40C_1v95.lib, line 31 default_operating_condition ff_n40C_1v95 not found.
+Warning: /mnt/data/workspace/pdk/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_100C_1v60.lib, line 32 default_operating_condition ss_100C_1v60 not found.
+Warning: /project/openlane/user_proj_example/runs/16-12_10-43/results/synthesis/user_proj_example.synthesis_preroute.v, line 598335 module sky130_fd_sc_hd__tapvpwrvgnd_1 not found. Creating black box for PHY_2262.
+Warning: /project/openlane/user_proj_example/runs/16-12_10-43/results/synthesis/user_proj_example.synthesis_preroute.v, line 834435 module sky130_fd_sc_hd__fill_2 not found. Creating black box for FILLER_1_59.
+Warning: /project/openlane/user_proj_example/runs/16-12_10-43/results/synthesis/user_proj_example.synthesis_preroute.v, line 834522 module sky130_fd_sc_hd__fill_1 not found. Creating black box for FILLER_1_1097.
+create_clock [get_ports $::env(CLOCK_PORT)] -name $::env(CLOCK_PORT) -period $::env(CLOCK_PERIOD)
+set input_delay_value [expr $::env(CLOCK_PERIOD) * $::env(IO_PCT)]
+set output_delay_value [expr $::env(CLOCK_PERIOD) * $::env(IO_PCT)]
+puts "\[INFO\]: Setting output delay to: $output_delay_value"
+[INFO]: Setting output delay to: 4.0
+puts "\[INFO\]: Setting input delay to: $input_delay_value"
+[INFO]: Setting input delay to: 4.0
+set clk_indx [lsearch [all_inputs] [get_port $::env(CLOCK_PORT)]]
+#set rst_indx [lsearch [all_inputs] [get_port resetn]]
+set all_inputs_wo_clk [lreplace [all_inputs] $clk_indx $clk_indx]
+#set all_inputs_wo_clk_rst [lreplace $all_inputs_wo_clk $rst_indx $rst_indx]
+set all_inputs_wo_clk_rst $all_inputs_wo_clk
+# correct resetn
+set_input_delay $input_delay_value -clock [get_clocks $::env(CLOCK_PORT)] $all_inputs_wo_clk_rst
+#set_input_delay 0.0 -clock [get_clocks $::env(CLOCK_PORT)] {resetn}
+set_output_delay $output_delay_value -clock [get_clocks $::env(CLOCK_PORT)] [all_outputs]
+# TODO set this as parameter
+set_driving_cell -lib_cell $::env(SYNTH_DRIVING_CELL) -pin $::env(SYNTH_DRIVING_CELL_PIN) [all_inputs]
+set cap_load [expr $::env(SYNTH_CAP_LOAD) / 1000.0]
+puts "\[INFO\]: Setting load to: $cap_load"
+[INFO]: Setting load to: 0.01765
+set_load $cap_load [all_outputs]
+tns 0.00
+wns 0.00
diff --git a/openlane/user_proj_example/results/logs/synthesis/yosys.log b/openlane/user_proj_example/results/logs/synthesis/yosys.log
new file mode 100644
index 0000000..5e5a513
--- /dev/null
+++ b/openlane/user_proj_example/results/logs/synthesis/yosys.log
@@ -0,0 +1,64008 @@
+
+ /----------------------------------------------------------------------------\
+ | |
+ | yosys -- Yosys Open SYnthesis Suite |
+ | |
+ | Copyright (C) 2012 - 2020 Claire Wolf <claire@symbioticeda.com> |
+ | |
+ | Permission to use, copy, modify, and/or distribute this software for any |
+ | purpose with or without fee is hereby granted, provided that the above |
+ | copyright notice and this permission notice appear in all copies. |
+ | |
+ | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES |
+ | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF |
+ | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR |
+ | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES |
+ | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN |
+ | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF |
+ | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. |
+ | |
+ \----------------------------------------------------------------------------/
+
+ Yosys 0.9+3621 (git sha1 84e9fa7, gcc 8.3.1 -fPIC -Os)
+
+[TCL: yosys -import] Command name collision: found pre-existing command `cd' -> skip.
+[TCL: yosys -import] Command name collision: found pre-existing command `eval' -> skip.
+[TCL: yosys -import] Command name collision: found pre-existing command `exec' -> skip.
+[TCL: yosys -import] Command name collision: found pre-existing command `read' -> skip.
+[TCL: yosys -import] Command name collision: found pre-existing command `trace' -> skip.
+
+1. Executing Verilog-2005 frontend: /project/openlane/user_proj_example/../../verilog/rtl/defines.v
+Parsing SystemVerilog input from `/project/openlane/user_proj_example/../../verilog/rtl/defines.v' to AST representation.
+Successfully finished Verilog frontend.
+
+2. Executing Verilog-2005 frontend: /project/openlane/user_proj_example/../../verilog/rtl/user_proj_example.v
+Parsing SystemVerilog input from `/project/openlane/user_proj_example/../../verilog/rtl/user_proj_example.v' to AST representation.
+Generating RTLIL representation for module `\user_proj_example'.
+Successfully finished Verilog frontend.
+
+3. Executing Verilog-2005 frontend: /project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/softshell_top.v
+Parsing SystemVerilog input from `/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/softshell_top.v' to AST representation.
+Generating RTLIL representation for module `\softshell_top'.
+Successfully finished Verilog frontend.
+
+4. Executing Verilog-2005 frontend: /project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/rv_core.v
+Parsing SystemVerilog input from `/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/rv_core.v' to AST representation.
+Generating RTLIL representation for module `\rv_core'.
+Generating RTLIL representation for module `\mgmt_soc_regs'.
+Successfully finished Verilog frontend.
+
+5. Executing Verilog-2005 frontend: /project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/pinmux.v
+Parsing SystemVerilog input from `/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/pinmux.v' to AST representation.
+Generating RTLIL representation for module `\pinmux'.
+Warning: Replacing memory \reg_mux_out with list of registers. See /project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/pinmux.v:77
+Warning: Replacing memory \reg_mux_in with list of registers. See /project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/pinmux.v:74
+Successfully finished Verilog frontend.
+
+6. Executing Verilog-2005 frontend: /project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/pcpi_flexio.v
+Parsing SystemVerilog input from `/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/pcpi_flexio.v' to AST representation.
+Generating RTLIL representation for module `\pcpi_flexio'.
+Successfully finished Verilog frontend.
+
+7. Executing Verilog-2005 frontend: /project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/verilog-wishbone/rtl/wb_arbiter_3.v
+Parsing SystemVerilog input from `/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/verilog-wishbone/rtl/wb_arbiter_3.v' to AST representation.
+Generating RTLIL representation for module `\wb_arbiter_3'.
+/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/verilog-wishbone/rtl/wb_arbiter_3.v:108: Warning: Identifier `\grant_valid' is implicitly declared.
+Successfully finished Verilog frontend.
+
+8. Executing Verilog-2005 frontend: /project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/verilog-wishbone/rtl/wb_arbiter_4.v
+Parsing SystemVerilog input from `/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/verilog-wishbone/rtl/wb_arbiter_4.v' to AST representation.
+Generating RTLIL representation for module `\wb_arbiter_4'.
+/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/verilog-wishbone/rtl/wb_arbiter_4.v:123: Warning: Identifier `\grant_valid' is implicitly declared.
+Successfully finished Verilog frontend.
+
+9. Executing Verilog-2005 frontend: /project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/verilog-wishbone/rtl/wb_arbiter_5.v
+Parsing SystemVerilog input from `/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/verilog-wishbone/rtl/wb_arbiter_5.v' to AST representation.
+Generating RTLIL representation for module `\wb_arbiter_5'.
+/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/verilog-wishbone/rtl/wb_arbiter_5.v:138: Warning: Identifier `\grant_valid' is implicitly declared.
+Successfully finished Verilog frontend.
+
+10. Executing Verilog-2005 frontend: /project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/verilog-wishbone/rtl/arbiter.v
+Parsing SystemVerilog input from `/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/verilog-wishbone/rtl/arbiter.v' to AST representation.
+Generating RTLIL representation for module `\arbiter'.
+Successfully finished Verilog frontend.
+
+11. Executing Verilog-2005 frontend: /project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/verilog-wishbone/rtl/priority_encoder.v
+Parsing SystemVerilog input from `/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/verilog-wishbone/rtl/priority_encoder.v' to AST representation.
+Generating RTLIL representation for module `\priority_encoder'.
+Successfully finished Verilog frontend.
+
+12. Executing Verilog-2005 frontend: /project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/verilog-wishbone/rtl/wb_mux_3.v
+Parsing SystemVerilog input from `/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/verilog-wishbone/rtl/wb_mux_3.v' to AST representation.
+Generating RTLIL representation for module `\wb_mux_3'.
+Successfully finished Verilog frontend.
+
+13. Executing Verilog-2005 frontend: /project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/verilog-wishbone/rtl/wb_mux_5.v
+Parsing SystemVerilog input from `/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/verilog-wishbone/rtl/wb_mux_5.v' to AST representation.
+Generating RTLIL representation for module `\wb_mux_5'.
+Successfully finished Verilog frontend.
+
+14. Executing Verilog-2005 frontend: /project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v
+Parsing SystemVerilog input from `/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v' to AST representation.
+Generating RTLIL representation for module `\mem_ff_wb'.
+Generating RTLIL representation for module `\ff32_ram'.
+Successfully finished Verilog frontend.
+
+15. Executing Verilog-2005 frontend: /project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/simpleuart.v
+Parsing SystemVerilog input from `/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/simpleuart.v' to AST representation.
+Generating RTLIL representation for module `\simpleuart_wb'.
+Generating RTLIL representation for module `\simpleuart'.
+Successfully finished Verilog frontend.
+
+16. Executing Verilog-2005 frontend: /project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/spimemio.v
+Parsing SystemVerilog input from `/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/spimemio.v' to AST representation.
+Generating RTLIL representation for module `\spimemio_wb'.
+Generating RTLIL representation for module `\spimemio'.
+Generating RTLIL representation for module `\spimemio_xfer'.
+Successfully finished Verilog frontend.
+
+17. Executing Verilog-2005 frontend: /project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/gpio32_wb.v
+Parsing SystemVerilog input from `/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/gpio32_wb.v' to AST representation.
+Generating RTLIL representation for module `\gpio32_wb'.
+Generating RTLIL representation for module `\gpio'.
+Successfully finished Verilog frontend.
+
+18. Executing Verilog-2005 frontend: /project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v
+Parsing SystemVerilog input from `/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v' to AST representation.
+Generating RTLIL representation for module `\picorv32'.
+Generating RTLIL representation for module `\picorv32_regs'.
+Generating RTLIL representation for module `\picorv32_pcpi_mul'.
+Generating RTLIL representation for module `\picorv32_pcpi_fast_mul'.
+Generating RTLIL representation for module `\picorv32_pcpi_div'.
+Generating RTLIL representation for module `\picorv32_axi'.
+Generating RTLIL representation for module `\picorv32_axi_adapter'.
+Generating RTLIL representation for module `\picorv32_wb'.
+Successfully finished Verilog frontend.
+
+19. Executing Verilog-2005 frontend: /project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v
+Parsing SystemVerilog input from `/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v' to AST representation.
+Generating RTLIL representation for module `\afifo'.
+Successfully finished Verilog frontend.
+
+20. Generating Graphviz representation of design.
+Writing dot description to `/project/openlane/user_proj_example/runs/16-12_10-43/tmp/synthesis/hierarchy.dot'.
+Dumping module user_proj_example to page 1.
+
+21. Executing HIERARCHY pass (managing design hierarchy).
+
+21.1. Analyzing design hierarchy..
+Top module: \user_proj_example
+Used module: \softshell_top
+Used module: \rv_core
+Used module: \wb_mux_3
+Used module: \gpio32_wb
+Used module: \gpio
+Used module: \mem_ff_wb
+Used module: \ff32_ram
+Used module: \picorv32_wb
+Used module: \picorv32
+Used module: \mgmt_soc_regs
+Used module: \pcpi_flexio
+Used module: \afifo
+Used module: \wb_mux_5
+Used module: \wb_arbiter_4
+Used module: \arbiter
+Used module: \priority_encoder
+Used module: \spimemio_wb
+Used module: \spimemio
+Used module: \spimemio_xfer
+Used module: \simpleuart_wb
+Used module: \simpleuart
+Used module: \pinmux
+Parameter \MEM_WORDS = 32
+Parameter \PROGADDR_RESET = 809697280
+Parameter \CORE_ID = 2
+
+21.2. Executing AST frontend in derive mode using pre-parsed AST for module `\rv_core'.
+Parameter \MEM_WORDS = 32
+Parameter \PROGADDR_RESET = 809697280
+Parameter \CORE_ID = 2
+Generating RTLIL representation for module `$paramod\rv_core\MEM_WORDS=32\PROGADDR_RESET=809697280\CORE_ID=2'.
+Parameter \MEM_WORDS = 32
+Parameter \PROGADDR_RESET = 809631744
+Parameter \CORE_ID = 1
+
+21.3. Executing AST frontend in derive mode using pre-parsed AST for module `\rv_core'.
+Parameter \MEM_WORDS = 32
+Parameter \PROGADDR_RESET = 809631744
+Parameter \CORE_ID = 1
+Generating RTLIL representation for module `$paramod\rv_core\MEM_WORDS=32\PROGADDR_RESET=809631744\CORE_ID=1'.
+Parameter \MEM_WORDS = 32
+Parameter \PROGADDR_RESET = 809566208
+Parameter \CORE_ID = 0
+
+21.4. Executing AST frontend in derive mode using pre-parsed AST for module `\rv_core'.
+Parameter \MEM_WORDS = 32
+Parameter \PROGADDR_RESET = 809566208
+Parameter \CORE_ID = 0
+Generating RTLIL representation for module `$paramod\rv_core\MEM_WORDS=32\PROGADDR_RESET=809566208\CORE_ID=0'.
+Parameter \ARB_TYPE = 88'0101001001001111010101010100111001000100010111110101001001001111010000100100100101001110
+
+21.5. Executing AST frontend in derive mode using pre-parsed AST for module `\wb_arbiter_4'.
+Parameter \ARB_TYPE = 88'0101001001001111010101010100111001000100010111110101001001001111010000100100100101001110
+Generating RTLIL representation for module `$paramod$dfdc56f61c29f5320a5a986f0ea01fc1dee9752c\wb_arbiter_4'.
+/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/verilog-wishbone/rtl/wb_arbiter_4.v:123: Warning: Identifier `\grant_valid' is implicitly declared.
+Parameter \BASE_ADR = 813826048
+
+21.6. Executing AST frontend in derive mode using pre-parsed AST for module `\simpleuart_wb'.
+Parameter \BASE_ADR = 813826048
+Generating RTLIL representation for module `$paramod\simpleuart_wb\BASE_ADR=813826048'.
+Parameter \NUM_INPUTS = 1
+Parameter \NUM_OUTPUTS = 25
+Parameter \NUM_GPIOS = 32
+
+21.7. Executing AST frontend in derive mode using pre-parsed AST for module `\pinmux'.
+Parameter \NUM_INPUTS = 1
+Parameter \NUM_OUTPUTS = 25
+Parameter \NUM_GPIOS = 32
+Generating RTLIL representation for module `$paramod\pinmux\NUM_INPUTS=1\NUM_OUTPUTS=25\NUM_GPIOS=32'.
+Warning: Replacing memory \reg_mux_out with list of registers. See /project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/pinmux.v:77
+Warning: Replacing memory \reg_mux_in with list of registers. See /project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/pinmux.v:74
+Parameter \MEM_WORDS = 512
+
+21.8. Executing AST frontend in derive mode using pre-parsed AST for module `\mem_ff_wb'.
+Parameter \MEM_WORDS = 512
+Generating RTLIL representation for module `$paramod\mem_ff_wb\MEM_WORDS=512'.
+Parameter \ADDR_WIDTH = 8
+
+21.9. Executing AST frontend in derive mode using pre-parsed AST for module `\ff32_ram'.
+Parameter \ADDR_WIDTH = 8
+Generating RTLIL representation for module `$paramod\ff32_ram\ADDR_WIDTH=8'.
+Parameter \WIDTH = 4
+Parameter \LSB_PRIORITY = 24'010011000100111101010111
+
+21.10. Executing AST frontend in derive mode using pre-parsed AST for module `\priority_encoder'.
+Parameter \WIDTH = 4
+Parameter \LSB_PRIORITY = 24'010011000100111101010111
+Generating RTLIL representation for module `$paramod\priority_encoder\WIDTH=4\LSB_PRIORITY=24'010011000100111101010111'.
+Parameter \WIDTH = 4
+Parameter \LSB_PRIORITY = 24'010011000100111101010111
+Found cached RTLIL representation for module `$paramod\priority_encoder\WIDTH=4\LSB_PRIORITY=24'010011000100111101010111'.
+Parameter \PORTS = 4
+Parameter \TYPE = 64'0101000001010010010010010100111101010010010010010101010001011001
+Parameter \BLOCK = 56'01010010010001010101000101010101010001010101001101010100
+Parameter \LSB_PRIORITY = 1212761928
+
+21.11. Executing AST frontend in derive mode using pre-parsed AST for module `\arbiter'.
+Parameter \PORTS = 4
+Parameter \TYPE = 64'0101000001010010010010010100111101010010010010010101010001011001
+Parameter \BLOCK = 56'01010010010001010101000101010101010001010101001101010100
+Parameter \LSB_PRIORITY = 1212761928
+Generating RTLIL representation for module `$paramod$24c541bd7343cc5f822b4d520bbee160919bc05e\arbiter'.
+Parameter \MEM_WORDS = 256
+
+21.12. Executing AST frontend in derive mode using pre-parsed AST for module `\mem_ff_wb'.
+Parameter \MEM_WORDS = 256
+Generating RTLIL representation for module `$paramod\mem_ff_wb\MEM_WORDS=256'.
+Parameter \ENABLE_COUNTERS64 = 0
+Parameter \BARREL_SHIFTER = 1
+Parameter \COMPRESSED_ISA = 1
+Parameter \ENABLE_PCPI = 1
+Parameter \ENABLE_MUL = 0
+Parameter \ENABLE_DIV = 0
+Parameter \ENABLE_IRQ = 1
+Parameter \ENABLE_IRQ_QREGS = 0
+Parameter \PROGADDR_RESET = 268435456
+Parameter \PROGADDR_IRQ = 0
+Parameter \STACKADDR = 1024
+
+21.13. Executing AST frontend in derive mode using pre-parsed AST for module `\picorv32_wb'.
+Parameter \ENABLE_COUNTERS64 = 0
+Parameter \BARREL_SHIFTER = 1
+Parameter \COMPRESSED_ISA = 1
+Parameter \ENABLE_PCPI = 1
+Parameter \ENABLE_MUL = 0
+Parameter \ENABLE_DIV = 0
+Parameter \ENABLE_IRQ = 1
+Parameter \ENABLE_IRQ_QREGS = 0
+Parameter \PROGADDR_RESET = 268435456
+Parameter \PROGADDR_IRQ = 0
+Parameter \STACKADDR = 1024
+Generating RTLIL representation for module `$paramod$ca87a48608487cb535f5aa73074540d50b96131d\picorv32_wb'.
+Parameter \LGFIFO = 2
+Parameter \WIDTH = 32
+Parameter \OPT_REGISTER_READS = 1'0
+
+21.14. Executing AST frontend in derive mode using pre-parsed AST for module `\afifo'.
+Parameter \LGFIFO = 2
+Parameter \WIDTH = 32
+Parameter \OPT_REGISTER_READS = 1'0
+Generating RTLIL representation for module `$paramod\afifo\LGFIFO=2\WIDTH=32\OPT_REGISTER_READS=1'0'.
+Parameter \ENABLE_COUNTERS = 1'1
+Parameter \ENABLE_COUNTERS64 = 1'1
+Parameter \ENABLE_REGS_16_31 = 1'1
+Parameter \ENABLE_REGS_DUALPORT = 1'1
+Parameter \TWO_STAGE_SHIFT = 1'1
+Parameter \BARREL_SHIFTER = 1'0
+Parameter \TWO_CYCLE_COMPARE = 1'0
+Parameter \TWO_CYCLE_ALU = 1'0
+Parameter \COMPRESSED_ISA = 1'0
+Parameter \CATCH_MISALIGN = 1'1
+Parameter \CATCH_ILLINSN = 1'1
+Parameter \ENABLE_PCPI = 1'0
+Parameter \ENABLE_MUL = 1'0
+Parameter \ENABLE_FAST_MUL = 1'0
+Parameter \ENABLE_DIV = 1'0
+Parameter \ENABLE_IRQ = 1'0
+Parameter \ENABLE_IRQ_QREGS = 1'1
+Parameter \ENABLE_IRQ_TIMER = 1'1
+Parameter \ENABLE_TRACE = 1'0
+Parameter \REGS_INIT_ZERO = 1'0
+Parameter \MASKED_IRQ = 0
+Parameter \LATCHED_IRQ = 32'11111111111111111111111111111111
+Parameter \PROGADDR_RESET = 0
+Parameter \PROGADDR_IRQ = 16
+Parameter \STACKADDR = 32'11111111111111111111111111111111
+
+21.15. Executing AST frontend in derive mode using pre-parsed AST for module `\picorv32'.
+Parameter \ENABLE_COUNTERS = 1'1
+Parameter \ENABLE_COUNTERS64 = 1'1
+Parameter \ENABLE_REGS_16_31 = 1'1
+Parameter \ENABLE_REGS_DUALPORT = 1'1
+Parameter \TWO_STAGE_SHIFT = 1'1
+Parameter \BARREL_SHIFTER = 1'0
+Parameter \TWO_CYCLE_COMPARE = 1'0
+Parameter \TWO_CYCLE_ALU = 1'0
+Parameter \COMPRESSED_ISA = 1'0
+Parameter \CATCH_MISALIGN = 1'1
+Parameter \CATCH_ILLINSN = 1'1
+Parameter \ENABLE_PCPI = 1'0
+Parameter \ENABLE_MUL = 1'0
+Parameter \ENABLE_FAST_MUL = 1'0
+Parameter \ENABLE_DIV = 1'0
+Parameter \ENABLE_IRQ = 1'0
+Parameter \ENABLE_IRQ_QREGS = 1'1
+Parameter \ENABLE_IRQ_TIMER = 1'1
+Parameter \ENABLE_TRACE = 1'0
+Parameter \REGS_INIT_ZERO = 1'0
+Parameter \MASKED_IRQ = 0
+Parameter \LATCHED_IRQ = 32'11111111111111111111111111111111
+Parameter \PROGADDR_RESET = 0
+Parameter \PROGADDR_IRQ = 16
+Parameter \STACKADDR = 32'11111111111111111111111111111111
+Generating RTLIL representation for module `$paramod$4d2dfdcc1db1a7362453fb449ccdda75bb1b39f9\picorv32'.
+Parameter \GPIO_DATA = 8'00000000
+Parameter \GPIO_ENA = 8'00000100
+Parameter \GPIO_PU = 8'00001000
+Parameter \GPIO_PD = 8'00001100
+
+21.16. Executing AST frontend in derive mode using pre-parsed AST for module `\gpio'.
+Parameter \GPIO_DATA = 8'00000000
+Parameter \GPIO_ENA = 8'00000100
+Parameter \GPIO_PU = 8'00001000
+Parameter \GPIO_PD = 8'00001100
+Generating RTLIL representation for module `$paramod$b48b6478f53991418334d339eb44ca404341ca26\gpio'.
+Parameter \WIDTH = 2
+Parameter \LSB_PRIORITY = 24'010011000100111101010111
+
+21.17. Executing AST frontend in derive mode using pre-parsed AST for module `\priority_encoder'.
+Parameter \WIDTH = 2
+Parameter \LSB_PRIORITY = 24'010011000100111101010111
+Generating RTLIL representation for module `$paramod\priority_encoder\WIDTH=2\LSB_PRIORITY=24'010011000100111101010111'.
+Parameter \WIDTH = 2
+Parameter \LSB_PRIORITY = 24'010011000100111101010111
+Found cached RTLIL representation for module `$paramod\priority_encoder\WIDTH=2\LSB_PRIORITY=24'010011000100111101010111'.
+
+21.18. Analyzing design hierarchy..
+Top module: \user_proj_example
+Used module: \softshell_top
+Used module: $paramod\rv_core\MEM_WORDS=32\PROGADDR_RESET=809697280\CORE_ID=2
+Used module: \wb_mux_3
+Used module: \gpio32_wb
+Used module: $paramod$b48b6478f53991418334d339eb44ca404341ca26\gpio
+Used module: \mem_ff_wb
+Used module: $paramod\ff32_ram\ADDR_WIDTH=8
+Used module: \picorv32_wb
+Used module: $paramod$4d2dfdcc1db1a7362453fb449ccdda75bb1b39f9\picorv32
+Used module: \mgmt_soc_regs
+Used module: \pcpi_flexio
+Used module: $paramod\afifo\LGFIFO=2\WIDTH=32\OPT_REGISTER_READS=1'0
+Used module: $paramod\rv_core\MEM_WORDS=32\PROGADDR_RESET=809631744\CORE_ID=1
+Used module: $paramod\rv_core\MEM_WORDS=32\PROGADDR_RESET=809566208\CORE_ID=0
+Used module: \wb_mux_5
+Used module: $paramod$dfdc56f61c29f5320a5a986f0ea01fc1dee9752c\wb_arbiter_4
+Used module: \arbiter
+Used module: $paramod\priority_encoder\WIDTH=4\LSB_PRIORITY=24'010011000100111101010111
+Used module: \priority_encoder
+Used module: $paramod\priority_encoder\WIDTH=2\LSB_PRIORITY=24'010011000100111101010111
+Used module: \spimemio_wb
+Used module: \spimemio
+Used module: \spimemio_xfer
+Used module: $paramod\simpleuart_wb\BASE_ADR=813826048
+Used module: \simpleuart
+Used module: $paramod\pinmux\NUM_INPUTS=1\NUM_OUTPUTS=25\NUM_GPIOS=32
+Used module: $paramod\mem_ff_wb\MEM_WORDS=512
+Used module: \ff32_ram
+Parameter \MEM_WORDS = 32
+
+21.19. Executing AST frontend in derive mode using pre-parsed AST for module `\mem_ff_wb'.
+Parameter \MEM_WORDS = 32
+Generating RTLIL representation for module `$paramod\mem_ff_wb\MEM_WORDS=32'.
+Parameter \ENABLE_COUNTERS64 = 0
+Parameter \BARREL_SHIFTER = 1
+Parameter \COMPRESSED_ISA = 1
+Parameter \ENABLE_PCPI = 1
+Parameter \ENABLE_MUL = 0
+Parameter \ENABLE_DIV = 0
+Parameter \ENABLE_IRQ = 1
+Parameter \ENABLE_IRQ_QREGS = 0
+Parameter \PROGADDR_RESET = 809697280
+Parameter \PROGADDR_IRQ = 0
+Parameter \STACKADDR = 128
+
+21.20. Executing AST frontend in derive mode using pre-parsed AST for module `\picorv32_wb'.
+Parameter \ENABLE_COUNTERS64 = 0
+Parameter \BARREL_SHIFTER = 1
+Parameter \COMPRESSED_ISA = 1
+Parameter \ENABLE_PCPI = 1
+Parameter \ENABLE_MUL = 0
+Parameter \ENABLE_DIV = 0
+Parameter \ENABLE_IRQ = 1
+Parameter \ENABLE_IRQ_QREGS = 0
+Parameter \PROGADDR_RESET = 809697280
+Parameter \PROGADDR_IRQ = 0
+Parameter \STACKADDR = 128
+Generating RTLIL representation for module `$paramod$d7c2e1f9a7f32b8e9c28fc8646c0275848e63526\picorv32_wb'.
+Parameter \MEM_WORDS = 32
+Found cached RTLIL representation for module `$paramod\mem_ff_wb\MEM_WORDS=32'.
+Parameter \ENABLE_COUNTERS64 = 0
+Parameter \BARREL_SHIFTER = 1
+Parameter \COMPRESSED_ISA = 1
+Parameter \ENABLE_PCPI = 1
+Parameter \ENABLE_MUL = 0
+Parameter \ENABLE_DIV = 0
+Parameter \ENABLE_IRQ = 1
+Parameter \ENABLE_IRQ_QREGS = 0
+Parameter \PROGADDR_RESET = 809631744
+Parameter \PROGADDR_IRQ = 0
+Parameter \STACKADDR = 128
+
+21.21. Executing AST frontend in derive mode using pre-parsed AST for module `\picorv32_wb'.
+Parameter \ENABLE_COUNTERS64 = 0
+Parameter \BARREL_SHIFTER = 1
+Parameter \COMPRESSED_ISA = 1
+Parameter \ENABLE_PCPI = 1
+Parameter \ENABLE_MUL = 0
+Parameter \ENABLE_DIV = 0
+Parameter \ENABLE_IRQ = 1
+Parameter \ENABLE_IRQ_QREGS = 0
+Parameter \PROGADDR_RESET = 809631744
+Parameter \PROGADDR_IRQ = 0
+Parameter \STACKADDR = 128
+Generating RTLIL representation for module `$paramod$e50444e694c9a9e823a24aefd7b9b454c7f28d7e\picorv32_wb'.
+Parameter \MEM_WORDS = 32
+Found cached RTLIL representation for module `$paramod\mem_ff_wb\MEM_WORDS=32'.
+Parameter \ENABLE_COUNTERS64 = 0
+Parameter \BARREL_SHIFTER = 1
+Parameter \COMPRESSED_ISA = 1
+Parameter \ENABLE_PCPI = 1
+Parameter \ENABLE_MUL = 0
+Parameter \ENABLE_DIV = 0
+Parameter \ENABLE_IRQ = 1
+Parameter \ENABLE_IRQ_QREGS = 0
+Parameter \PROGADDR_RESET = 809566208
+Parameter \PROGADDR_IRQ = 0
+Parameter \STACKADDR = 128
+
+21.22. Executing AST frontend in derive mode using pre-parsed AST for module `\picorv32_wb'.
+Parameter \ENABLE_COUNTERS64 = 0
+Parameter \BARREL_SHIFTER = 1
+Parameter \COMPRESSED_ISA = 1
+Parameter \ENABLE_PCPI = 1
+Parameter \ENABLE_MUL = 0
+Parameter \ENABLE_DIV = 0
+Parameter \ENABLE_IRQ = 1
+Parameter \ENABLE_IRQ_QREGS = 0
+Parameter \PROGADDR_RESET = 809566208
+Parameter \PROGADDR_IRQ = 0
+Parameter \STACKADDR = 128
+Generating RTLIL representation for module `$paramod$02c0b2a9118806de1d82e68e563b733cce432378\picorv32_wb'.
+Parameter \PORTS = 4
+Parameter \TYPE = 88'0101001001001111010101010100111001000100010111110101001001001111010000100100100101001110
+Parameter \BLOCK = 56'01010010010001010101000101010101010001010101001101010100
+Parameter \LSB_PRIORITY = 1212761928
+
+21.23. Executing AST frontend in derive mode using pre-parsed AST for module `\arbiter'.
+Parameter \PORTS = 4
+Parameter \TYPE = 88'0101001001001111010101010100111001000100010111110101001001001111010000100100100101001110
+Parameter \BLOCK = 56'01010010010001010101000101010101010001010101001101010100
+Parameter \LSB_PRIORITY = 1212761928
+Generating RTLIL representation for module `$paramod$922eeecdf93ea4da89c0f9a13b613ec8c6a19ae5\arbiter'.
+Parameter \ADDR_WIDTH = 9
+
+21.24. Executing AST frontend in derive mode using pre-parsed AST for module `\ff32_ram'.
+Parameter \ADDR_WIDTH = 9
+Generating RTLIL representation for module `$paramod\ff32_ram\ADDR_WIDTH=9'.
+Parameter \WIDTH = 2
+Parameter \LSB_PRIORITY = 24'010011000100111101010111
+Found cached RTLIL representation for module `$paramod\priority_encoder\WIDTH=2\LSB_PRIORITY=24'010011000100111101010111'.
+Parameter \WIDTH = 2
+Parameter \LSB_PRIORITY = 24'010011000100111101010111
+Found cached RTLIL representation for module `$paramod\priority_encoder\WIDTH=2\LSB_PRIORITY=24'010011000100111101010111'.
+
+21.25. Analyzing design hierarchy..
+Top module: \user_proj_example
+Used module: \softshell_top
+Used module: $paramod\rv_core\MEM_WORDS=32\PROGADDR_RESET=809697280\CORE_ID=2
+Used module: \wb_mux_3
+Used module: \gpio32_wb
+Used module: $paramod$b48b6478f53991418334d339eb44ca404341ca26\gpio
+Used module: $paramod\mem_ff_wb\MEM_WORDS=32
+Used module: \ff32_ram
+Used module: $paramod$d7c2e1f9a7f32b8e9c28fc8646c0275848e63526\picorv32_wb
+Used module: \picorv32
+Used module: \mgmt_soc_regs
+Used module: \pcpi_flexio
+Used module: $paramod\afifo\LGFIFO=2\WIDTH=32\OPT_REGISTER_READS=1'0
+Used module: $paramod\rv_core\MEM_WORDS=32\PROGADDR_RESET=809631744\CORE_ID=1
+Used module: $paramod$e50444e694c9a9e823a24aefd7b9b454c7f28d7e\picorv32_wb
+Used module: $paramod\rv_core\MEM_WORDS=32\PROGADDR_RESET=809566208\CORE_ID=0
+Used module: $paramod$02c0b2a9118806de1d82e68e563b733cce432378\picorv32_wb
+Used module: \wb_mux_5
+Used module: $paramod$dfdc56f61c29f5320a5a986f0ea01fc1dee9752c\wb_arbiter_4
+Used module: $paramod$922eeecdf93ea4da89c0f9a13b613ec8c6a19ae5\arbiter
+Used module: \priority_encoder
+Used module: $paramod\priority_encoder\WIDTH=2\LSB_PRIORITY=24'010011000100111101010111
+Used module: \spimemio_wb
+Used module: \spimemio
+Used module: \spimemio_xfer
+Used module: $paramod\simpleuart_wb\BASE_ADR=813826048
+Used module: \simpleuart
+Used module: $paramod\pinmux\NUM_INPUTS=1\NUM_OUTPUTS=25\NUM_GPIOS=32
+Used module: $paramod\mem_ff_wb\MEM_WORDS=512
+Used module: $paramod\ff32_ram\ADDR_WIDTH=9
+Parameter \ADDR_WIDTH = 5
+
+21.26. Executing AST frontend in derive mode using pre-parsed AST for module `\ff32_ram'.
+Parameter \ADDR_WIDTH = 5
+Generating RTLIL representation for module `$paramod\ff32_ram\ADDR_WIDTH=5'.
+Parameter \ENABLE_COUNTERS = 1'1
+Parameter \ENABLE_COUNTERS64 = 1'0
+Parameter \ENABLE_REGS_16_31 = 1'1
+Parameter \ENABLE_REGS_DUALPORT = 1'1
+Parameter \TWO_STAGE_SHIFT = 1'1
+Parameter \BARREL_SHIFTER = 1'1
+Parameter \TWO_CYCLE_COMPARE = 1'0
+Parameter \TWO_CYCLE_ALU = 1'0
+Parameter \COMPRESSED_ISA = 1'1
+Parameter \CATCH_MISALIGN = 1'1
+Parameter \CATCH_ILLINSN = 1'1
+Parameter \ENABLE_PCPI = 1'1
+Parameter \ENABLE_MUL = 1'0
+Parameter \ENABLE_FAST_MUL = 1'0
+Parameter \ENABLE_DIV = 1'0
+Parameter \ENABLE_IRQ = 1'1
+Parameter \ENABLE_IRQ_QREGS = 1'0
+Parameter \ENABLE_IRQ_TIMER = 1'1
+Parameter \ENABLE_TRACE = 1'0
+Parameter \REGS_INIT_ZERO = 1'0
+Parameter \MASKED_IRQ = 0
+Parameter \LATCHED_IRQ = 32'11111111111111111111111111111111
+Parameter \PROGADDR_RESET = 809697280
+Parameter \PROGADDR_IRQ = 0
+Parameter \STACKADDR = 128
+
+21.27. Executing AST frontend in derive mode using pre-parsed AST for module `\picorv32'.
+Parameter \ENABLE_COUNTERS = 1'1
+Parameter \ENABLE_COUNTERS64 = 1'0
+Parameter \ENABLE_REGS_16_31 = 1'1
+Parameter \ENABLE_REGS_DUALPORT = 1'1
+Parameter \TWO_STAGE_SHIFT = 1'1
+Parameter \BARREL_SHIFTER = 1'1
+Parameter \TWO_CYCLE_COMPARE = 1'0
+Parameter \TWO_CYCLE_ALU = 1'0
+Parameter \COMPRESSED_ISA = 1'1
+Parameter \CATCH_MISALIGN = 1'1
+Parameter \CATCH_ILLINSN = 1'1
+Parameter \ENABLE_PCPI = 1'1
+Parameter \ENABLE_MUL = 1'0
+Parameter \ENABLE_FAST_MUL = 1'0
+Parameter \ENABLE_DIV = 1'0
+Parameter \ENABLE_IRQ = 1'1
+Parameter \ENABLE_IRQ_QREGS = 1'0
+Parameter \ENABLE_IRQ_TIMER = 1'1
+Parameter \ENABLE_TRACE = 1'0
+Parameter \REGS_INIT_ZERO = 1'0
+Parameter \MASKED_IRQ = 0
+Parameter \LATCHED_IRQ = 32'11111111111111111111111111111111
+Parameter \PROGADDR_RESET = 809697280
+Parameter \PROGADDR_IRQ = 0
+Parameter \STACKADDR = 128
+Generating RTLIL representation for module `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32'.
+Parameter \ENABLE_COUNTERS = 1'1
+Parameter \ENABLE_COUNTERS64 = 1'0
+Parameter \ENABLE_REGS_16_31 = 1'1
+Parameter \ENABLE_REGS_DUALPORT = 1'1
+Parameter \TWO_STAGE_SHIFT = 1'1
+Parameter \BARREL_SHIFTER = 1'1
+Parameter \TWO_CYCLE_COMPARE = 1'0
+Parameter \TWO_CYCLE_ALU = 1'0
+Parameter \COMPRESSED_ISA = 1'1
+Parameter \CATCH_MISALIGN = 1'1
+Parameter \CATCH_ILLINSN = 1'1
+Parameter \ENABLE_PCPI = 1'1
+Parameter \ENABLE_MUL = 1'0
+Parameter \ENABLE_FAST_MUL = 1'0
+Parameter \ENABLE_DIV = 1'0
+Parameter \ENABLE_IRQ = 1'1
+Parameter \ENABLE_IRQ_QREGS = 1'0
+Parameter \ENABLE_IRQ_TIMER = 1'1
+Parameter \ENABLE_TRACE = 1'0
+Parameter \REGS_INIT_ZERO = 1'0
+Parameter \MASKED_IRQ = 0
+Parameter \LATCHED_IRQ = 32'11111111111111111111111111111111
+Parameter \PROGADDR_RESET = 809631744
+Parameter \PROGADDR_IRQ = 0
+Parameter \STACKADDR = 128
+
+21.28. Executing AST frontend in derive mode using pre-parsed AST for module `\picorv32'.
+Parameter \ENABLE_COUNTERS = 1'1
+Parameter \ENABLE_COUNTERS64 = 1'0
+Parameter \ENABLE_REGS_16_31 = 1'1
+Parameter \ENABLE_REGS_DUALPORT = 1'1
+Parameter \TWO_STAGE_SHIFT = 1'1
+Parameter \BARREL_SHIFTER = 1'1
+Parameter \TWO_CYCLE_COMPARE = 1'0
+Parameter \TWO_CYCLE_ALU = 1'0
+Parameter \COMPRESSED_ISA = 1'1
+Parameter \CATCH_MISALIGN = 1'1
+Parameter \CATCH_ILLINSN = 1'1
+Parameter \ENABLE_PCPI = 1'1
+Parameter \ENABLE_MUL = 1'0
+Parameter \ENABLE_FAST_MUL = 1'0
+Parameter \ENABLE_DIV = 1'0
+Parameter \ENABLE_IRQ = 1'1
+Parameter \ENABLE_IRQ_QREGS = 1'0
+Parameter \ENABLE_IRQ_TIMER = 1'1
+Parameter \ENABLE_TRACE = 1'0
+Parameter \REGS_INIT_ZERO = 1'0
+Parameter \MASKED_IRQ = 0
+Parameter \LATCHED_IRQ = 32'11111111111111111111111111111111
+Parameter \PROGADDR_RESET = 809631744
+Parameter \PROGADDR_IRQ = 0
+Parameter \STACKADDR = 128
+Generating RTLIL representation for module `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32'.
+Parameter \ENABLE_COUNTERS = 1'1
+Parameter \ENABLE_COUNTERS64 = 1'0
+Parameter \ENABLE_REGS_16_31 = 1'1
+Parameter \ENABLE_REGS_DUALPORT = 1'1
+Parameter \TWO_STAGE_SHIFT = 1'1
+Parameter \BARREL_SHIFTER = 1'1
+Parameter \TWO_CYCLE_COMPARE = 1'0
+Parameter \TWO_CYCLE_ALU = 1'0
+Parameter \COMPRESSED_ISA = 1'1
+Parameter \CATCH_MISALIGN = 1'1
+Parameter \CATCH_ILLINSN = 1'1
+Parameter \ENABLE_PCPI = 1'1
+Parameter \ENABLE_MUL = 1'0
+Parameter \ENABLE_FAST_MUL = 1'0
+Parameter \ENABLE_DIV = 1'0
+Parameter \ENABLE_IRQ = 1'1
+Parameter \ENABLE_IRQ_QREGS = 1'0
+Parameter \ENABLE_IRQ_TIMER = 1'1
+Parameter \ENABLE_TRACE = 1'0
+Parameter \REGS_INIT_ZERO = 1'0
+Parameter \MASKED_IRQ = 0
+Parameter \LATCHED_IRQ = 32'11111111111111111111111111111111
+Parameter \PROGADDR_RESET = 809566208
+Parameter \PROGADDR_IRQ = 0
+Parameter \STACKADDR = 128
+
+21.29. Executing AST frontend in derive mode using pre-parsed AST for module `\picorv32'.
+Parameter \ENABLE_COUNTERS = 1'1
+Parameter \ENABLE_COUNTERS64 = 1'0
+Parameter \ENABLE_REGS_16_31 = 1'1
+Parameter \ENABLE_REGS_DUALPORT = 1'1
+Parameter \TWO_STAGE_SHIFT = 1'1
+Parameter \BARREL_SHIFTER = 1'1
+Parameter \TWO_CYCLE_COMPARE = 1'0
+Parameter \TWO_CYCLE_ALU = 1'0
+Parameter \COMPRESSED_ISA = 1'1
+Parameter \CATCH_MISALIGN = 1'1
+Parameter \CATCH_ILLINSN = 1'1
+Parameter \ENABLE_PCPI = 1'1
+Parameter \ENABLE_MUL = 1'0
+Parameter \ENABLE_FAST_MUL = 1'0
+Parameter \ENABLE_DIV = 1'0
+Parameter \ENABLE_IRQ = 1'1
+Parameter \ENABLE_IRQ_QREGS = 1'0
+Parameter \ENABLE_IRQ_TIMER = 1'1
+Parameter \ENABLE_TRACE = 1'0
+Parameter \REGS_INIT_ZERO = 1'0
+Parameter \MASKED_IRQ = 0
+Parameter \LATCHED_IRQ = 32'11111111111111111111111111111111
+Parameter \PROGADDR_RESET = 809566208
+Parameter \PROGADDR_IRQ = 0
+Parameter \STACKADDR = 128
+Generating RTLIL representation for module `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32'.
+Parameter \WIDTH = 4
+Parameter \LSB_PRIORITY = 1212761928
+
+21.30. Executing AST frontend in derive mode using pre-parsed AST for module `\priority_encoder'.
+Parameter \WIDTH = 4
+Parameter \LSB_PRIORITY = 1212761928
+Generating RTLIL representation for module `$paramod\priority_encoder\WIDTH=4\LSB_PRIORITY=1212761928'.
+Parameter \WIDTH = 4
+Parameter \LSB_PRIORITY = 1212761928
+Found cached RTLIL representation for module `$paramod\priority_encoder\WIDTH=4\LSB_PRIORITY=1212761928'.
+
+21.31. Analyzing design hierarchy..
+Top module: \user_proj_example
+Used module: \softshell_top
+Used module: $paramod\rv_core\MEM_WORDS=32\PROGADDR_RESET=809697280\CORE_ID=2
+Used module: \wb_mux_3
+Used module: \gpio32_wb
+Used module: $paramod$b48b6478f53991418334d339eb44ca404341ca26\gpio
+Used module: $paramod\mem_ff_wb\MEM_WORDS=32
+Used module: $paramod\ff32_ram\ADDR_WIDTH=5
+Used module: $paramod$d7c2e1f9a7f32b8e9c28fc8646c0275848e63526\picorv32_wb
+Used module: $paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32
+Used module: \mgmt_soc_regs
+Used module: \pcpi_flexio
+Used module: $paramod\afifo\LGFIFO=2\WIDTH=32\OPT_REGISTER_READS=1'0
+Used module: $paramod\rv_core\MEM_WORDS=32\PROGADDR_RESET=809631744\CORE_ID=1
+Used module: $paramod$e50444e694c9a9e823a24aefd7b9b454c7f28d7e\picorv32_wb
+Used module: $paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32
+Used module: $paramod\rv_core\MEM_WORDS=32\PROGADDR_RESET=809566208\CORE_ID=0
+Used module: $paramod$02c0b2a9118806de1d82e68e563b733cce432378\picorv32_wb
+Used module: $paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32
+Used module: \wb_mux_5
+Used module: $paramod$dfdc56f61c29f5320a5a986f0ea01fc1dee9752c\wb_arbiter_4
+Used module: $paramod$922eeecdf93ea4da89c0f9a13b613ec8c6a19ae5\arbiter
+Used module: $paramod\priority_encoder\WIDTH=4\LSB_PRIORITY=1212761928
+Used module: \priority_encoder
+Used module: $paramod\priority_encoder\WIDTH=2\LSB_PRIORITY=24'010011000100111101010111
+Used module: \spimemio_wb
+Used module: \spimemio
+Used module: \spimemio_xfer
+Used module: $paramod\simpleuart_wb\BASE_ADR=813826048
+Used module: \simpleuart
+Used module: $paramod\pinmux\NUM_INPUTS=1\NUM_OUTPUTS=25\NUM_GPIOS=32
+Used module: $paramod\mem_ff_wb\MEM_WORDS=512
+Used module: $paramod\ff32_ram\ADDR_WIDTH=9
+Parameter \WIDTH = 2
+Parameter \LSB_PRIORITY = 1212761928
+
+21.32. Executing AST frontend in derive mode using pre-parsed AST for module `\priority_encoder'.
+Parameter \WIDTH = 2
+Parameter \LSB_PRIORITY = 1212761928
+Generating RTLIL representation for module `$paramod\priority_encoder\WIDTH=2\LSB_PRIORITY=1212761928'.
+Parameter \WIDTH = 2
+Parameter \LSB_PRIORITY = 1212761928
+Found cached RTLIL representation for module `$paramod\priority_encoder\WIDTH=2\LSB_PRIORITY=1212761928'.
+
+21.33. Analyzing design hierarchy..
+Top module: \user_proj_example
+Used module: \softshell_top
+Used module: $paramod\rv_core\MEM_WORDS=32\PROGADDR_RESET=809697280\CORE_ID=2
+Used module: \wb_mux_3
+Used module: \gpio32_wb
+Used module: $paramod$b48b6478f53991418334d339eb44ca404341ca26\gpio
+Used module: $paramod\mem_ff_wb\MEM_WORDS=32
+Used module: $paramod\ff32_ram\ADDR_WIDTH=5
+Used module: $paramod$d7c2e1f9a7f32b8e9c28fc8646c0275848e63526\picorv32_wb
+Used module: $paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32
+Used module: \mgmt_soc_regs
+Used module: \pcpi_flexio
+Used module: $paramod\afifo\LGFIFO=2\WIDTH=32\OPT_REGISTER_READS=1'0
+Used module: $paramod\rv_core\MEM_WORDS=32\PROGADDR_RESET=809631744\CORE_ID=1
+Used module: $paramod$e50444e694c9a9e823a24aefd7b9b454c7f28d7e\picorv32_wb
+Used module: $paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32
+Used module: $paramod\rv_core\MEM_WORDS=32\PROGADDR_RESET=809566208\CORE_ID=0
+Used module: $paramod$02c0b2a9118806de1d82e68e563b733cce432378\picorv32_wb
+Used module: $paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32
+Used module: \wb_mux_5
+Used module: $paramod$dfdc56f61c29f5320a5a986f0ea01fc1dee9752c\wb_arbiter_4
+Used module: $paramod$922eeecdf93ea4da89c0f9a13b613ec8c6a19ae5\arbiter
+Used module: $paramod\priority_encoder\WIDTH=4\LSB_PRIORITY=1212761928
+Used module: $paramod\priority_encoder\WIDTH=2\LSB_PRIORITY=1212761928
+Used module: \spimemio_wb
+Used module: \spimemio
+Used module: \spimemio_xfer
+Used module: $paramod\simpleuart_wb\BASE_ADR=813826048
+Used module: \simpleuart
+Used module: $paramod\pinmux\NUM_INPUTS=1\NUM_OUTPUTS=25\NUM_GPIOS=32
+Used module: $paramod\mem_ff_wb\MEM_WORDS=512
+Used module: $paramod\ff32_ram\ADDR_WIDTH=9
+
+21.34. Analyzing design hierarchy..
+Top module: \user_proj_example
+Used module: \softshell_top
+Used module: $paramod\rv_core\MEM_WORDS=32\PROGADDR_RESET=809697280\CORE_ID=2
+Used module: \wb_mux_3
+Used module: \gpio32_wb
+Used module: $paramod$b48b6478f53991418334d339eb44ca404341ca26\gpio
+Used module: $paramod\mem_ff_wb\MEM_WORDS=32
+Used module: $paramod\ff32_ram\ADDR_WIDTH=5
+Used module: $paramod$d7c2e1f9a7f32b8e9c28fc8646c0275848e63526\picorv32_wb
+Used module: $paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32
+Used module: \mgmt_soc_regs
+Used module: \pcpi_flexio
+Used module: $paramod\afifo\LGFIFO=2\WIDTH=32\OPT_REGISTER_READS=1'0
+Used module: $paramod\rv_core\MEM_WORDS=32\PROGADDR_RESET=809631744\CORE_ID=1
+Used module: $paramod$e50444e694c9a9e823a24aefd7b9b454c7f28d7e\picorv32_wb
+Used module: $paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32
+Used module: $paramod\rv_core\MEM_WORDS=32\PROGADDR_RESET=809566208\CORE_ID=0
+Used module: $paramod$02c0b2a9118806de1d82e68e563b733cce432378\picorv32_wb
+Used module: $paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32
+Used module: \wb_mux_5
+Used module: $paramod$dfdc56f61c29f5320a5a986f0ea01fc1dee9752c\wb_arbiter_4
+Used module: $paramod$922eeecdf93ea4da89c0f9a13b613ec8c6a19ae5\arbiter
+Used module: $paramod\priority_encoder\WIDTH=4\LSB_PRIORITY=1212761928
+Used module: $paramod\priority_encoder\WIDTH=2\LSB_PRIORITY=1212761928
+Used module: \spimemio_wb
+Used module: \spimemio
+Used module: \spimemio_xfer
+Used module: $paramod\simpleuart_wb\BASE_ADR=813826048
+Used module: \simpleuart
+Used module: $paramod\pinmux\NUM_INPUTS=1\NUM_OUTPUTS=25\NUM_GPIOS=32
+Used module: $paramod\mem_ff_wb\MEM_WORDS=512
+Used module: $paramod\ff32_ram\ADDR_WIDTH=9
+Removing unused module `$paramod\priority_encoder\WIDTH=2\LSB_PRIORITY=24'010011000100111101010111'.
+Removing unused module `$paramod$4d2dfdcc1db1a7362453fb449ccdda75bb1b39f9\picorv32'.
+Removing unused module `$paramod$ca87a48608487cb535f5aa73074540d50b96131d\picorv32_wb'.
+Removing unused module `$paramod\mem_ff_wb\MEM_WORDS=256'.
+Removing unused module `$paramod$24c541bd7343cc5f822b4d520bbee160919bc05e\arbiter'.
+Removing unused module `$paramod\priority_encoder\WIDTH=4\LSB_PRIORITY=24'010011000100111101010111'.
+Removing unused module `$paramod\ff32_ram\ADDR_WIDTH=8'.
+Removing unused module `\afifo'.
+Removing unused module `\picorv32_wb'.
+Removing unused module `\picorv32_axi_adapter'.
+Removing unused module `\picorv32_axi'.
+Removing unused module `\picorv32_pcpi_div'.
+Removing unused module `\picorv32_pcpi_fast_mul'.
+Removing unused module `\picorv32_pcpi_mul'.
+Removing unused module `\picorv32_regs'.
+Removing unused module `\picorv32'.
+Removing unused module `\gpio'.
+Removing unused module `\simpleuart_wb'.
+Removing unused module `\ff32_ram'.
+Removing unused module `\mem_ff_wb'.
+Removing unused module `\priority_encoder'.
+Removing unused module `\arbiter'.
+Removing unused module `\wb_arbiter_5'.
+Removing unused module `\wb_arbiter_4'.
+Removing unused module `\wb_arbiter_3'.
+Removing unused module `\pinmux'.
+Removing unused module `\rv_core'.
+Removed 27 unused modules.
+
+22. Executing TRIBUF pass.
+
+23. Executing SYNTH pass.
+
+23.1. Executing HIERARCHY pass (managing design hierarchy).
+
+23.1.1. Analyzing design hierarchy..
+Top module: \user_proj_example
+Used module: \softshell_top
+Used module: $paramod\rv_core\MEM_WORDS=32\PROGADDR_RESET=809697280\CORE_ID=2
+Used module: \wb_mux_3
+Used module: \gpio32_wb
+Used module: $paramod$b48b6478f53991418334d339eb44ca404341ca26\gpio
+Used module: $paramod\mem_ff_wb\MEM_WORDS=32
+Used module: $paramod\ff32_ram\ADDR_WIDTH=5
+Used module: $paramod$d7c2e1f9a7f32b8e9c28fc8646c0275848e63526\picorv32_wb
+Used module: $paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32
+Used module: \mgmt_soc_regs
+Used module: \pcpi_flexio
+Used module: $paramod\afifo\LGFIFO=2\WIDTH=32\OPT_REGISTER_READS=1'0
+Used module: $paramod\rv_core\MEM_WORDS=32\PROGADDR_RESET=809631744\CORE_ID=1
+Used module: $paramod$e50444e694c9a9e823a24aefd7b9b454c7f28d7e\picorv32_wb
+Used module: $paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32
+Used module: $paramod\rv_core\MEM_WORDS=32\PROGADDR_RESET=809566208\CORE_ID=0
+Used module: $paramod$02c0b2a9118806de1d82e68e563b733cce432378\picorv32_wb
+Used module: $paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32
+Used module: \wb_mux_5
+Used module: $paramod$dfdc56f61c29f5320a5a986f0ea01fc1dee9752c\wb_arbiter_4
+Used module: $paramod$922eeecdf93ea4da89c0f9a13b613ec8c6a19ae5\arbiter
+Used module: $paramod\priority_encoder\WIDTH=4\LSB_PRIORITY=1212761928
+Used module: $paramod\priority_encoder\WIDTH=2\LSB_PRIORITY=1212761928
+Used module: \spimemio_wb
+Used module: \spimemio
+Used module: \spimemio_xfer
+Used module: $paramod\simpleuart_wb\BASE_ADR=813826048
+Used module: \simpleuart
+Used module: $paramod\pinmux\NUM_INPUTS=1\NUM_OUTPUTS=25\NUM_GPIOS=32
+Used module: $paramod\mem_ff_wb\MEM_WORDS=512
+Used module: $paramod\ff32_ram\ADDR_WIDTH=9
+
+23.1.2. Analyzing design hierarchy..
+Top module: \user_proj_example
+Used module: \softshell_top
+Used module: $paramod\rv_core\MEM_WORDS=32\PROGADDR_RESET=809697280\CORE_ID=2
+Used module: \wb_mux_3
+Used module: \gpio32_wb
+Used module: $paramod$b48b6478f53991418334d339eb44ca404341ca26\gpio
+Used module: $paramod\mem_ff_wb\MEM_WORDS=32
+Used module: $paramod\ff32_ram\ADDR_WIDTH=5
+Used module: $paramod$d7c2e1f9a7f32b8e9c28fc8646c0275848e63526\picorv32_wb
+Used module: $paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32
+Used module: \mgmt_soc_regs
+Used module: \pcpi_flexio
+Used module: $paramod\afifo\LGFIFO=2\WIDTH=32\OPT_REGISTER_READS=1'0
+Used module: $paramod\rv_core\MEM_WORDS=32\PROGADDR_RESET=809631744\CORE_ID=1
+Used module: $paramod$e50444e694c9a9e823a24aefd7b9b454c7f28d7e\picorv32_wb
+Used module: $paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32
+Used module: $paramod\rv_core\MEM_WORDS=32\PROGADDR_RESET=809566208\CORE_ID=0
+Used module: $paramod$02c0b2a9118806de1d82e68e563b733cce432378\picorv32_wb
+Used module: $paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32
+Used module: \wb_mux_5
+Used module: $paramod$dfdc56f61c29f5320a5a986f0ea01fc1dee9752c\wb_arbiter_4
+Used module: $paramod$922eeecdf93ea4da89c0f9a13b613ec8c6a19ae5\arbiter
+Used module: $paramod\priority_encoder\WIDTH=4\LSB_PRIORITY=1212761928
+Used module: $paramod\priority_encoder\WIDTH=2\LSB_PRIORITY=1212761928
+Used module: \spimemio_wb
+Used module: \spimemio
+Used module: \spimemio_xfer
+Used module: $paramod\simpleuart_wb\BASE_ADR=813826048
+Used module: \simpleuart
+Used module: $paramod\pinmux\NUM_INPUTS=1\NUM_OUTPUTS=25\NUM_GPIOS=32
+Used module: $paramod\mem_ff_wb\MEM_WORDS=512
+Used module: $paramod\ff32_ram\ADDR_WIDTH=9
+Removed 0 unused modules.
+
+23.2. Executing PROC pass (convert processes to netlists).
+
+23.2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
+Found and cleaned up 4 empty switches in `$paramod$922eeecdf93ea4da89c0f9a13b613ec8c6a19ae5\arbiter.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/verilog-wishbone/rtl/arbiter.v:94$2746'.
+Found and cleaned up 16 empty switches in `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1397$4672'.
+Found and cleaned up 1 empty switch in `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1382$4658'.
+Found and cleaned up 6 empty switches in `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:546$4304'.
+Removing empty process `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:546$4304'.
+Found and cleaned up 16 empty switches in `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1397$3989'.
+Found and cleaned up 1 empty switch in `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1382$3975'.
+Found and cleaned up 6 empty switches in `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:546$3621'.
+Removing empty process `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:546$3621'.
+Found and cleaned up 16 empty switches in `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1397$3306'.
+Found and cleaned up 1 empty switch in `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1382$3292'.
+Found and cleaned up 6 empty switches in `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:546$2938'.
+Removing empty process `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:546$2938'.
+Cleaned up 73 empty switches.
+
+23.2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
+Marked 1 switch rules as full_case in process $proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/verilog-wishbone/rtl/arbiter.v:139$2757 in module $paramod$922eeecdf93ea4da89c0f9a13b613ec8c6a19ae5\arbiter.
+Marked 4 switch rules as full_case in process $proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/verilog-wishbone/rtl/arbiter.v:94$2746 in module $paramod$922eeecdf93ea4da89c0f9a13b613ec8c6a19ae5\arbiter.
+Marked 3 switch rules as full_case in process $proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:2994$2744 in module $paramod$02c0b2a9118806de1d82e68e563b733cce432378\picorv32_wb.
+Marked 3 switch rules as full_case in process $proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:2994$2739 in module $paramod$e50444e694c9a9e823a24aefd7b9b454c7f28d7e\picorv32_wb.
+Marked 3 switch rules as full_case in process $proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:2994$2734 in module $paramod$d7c2e1f9a7f32b8e9c28fc8646c0275848e63526\picorv32_wb.
+Marked 1 switch rules as full_case in process $proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:43$2721 in module $paramod\mem_ff_wb\MEM_WORDS=32.
+Marked 4 switch rules as full_case in process $proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/gpio32_wb.v:102$2710 in module $paramod$b48b6478f53991418334d339eb44ca404341ca26\gpio.
+Marked 1 switch rules as full_case in process $proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:182$2024 in module $paramod\afifo\LGFIFO=2\WIDTH=32\OPT_REGISTER_READS=1'0.
+Marked 1 switch rules as full_case in process $proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:173$2022 in module $paramod\afifo\LGFIFO=2\WIDTH=32\OPT_REGISTER_READS=1'0.
+Marked 1 switch rules as full_case in process $proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:145$2014 in module $paramod\afifo\LGFIFO=2\WIDTH=32\OPT_REGISTER_READS=1'0.
+Marked 1 switch rules as full_case in process $proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:123$2001 in module $paramod\afifo\LGFIFO=2\WIDTH=32\OPT_REGISTER_READS=1'0.
+Marked 41 switch rules as full_case in process $proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1397$4672 in module $paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.
+Marked 2 switch rules as full_case in process $proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1304$4644 in module $paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.
+Marked 2 switch rules as full_case in process $proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1290$4639 in module $paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.
+Marked 8 switch rules as full_case in process $proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1181$4604 in module $paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.
+Marked 3 switch rules as full_case in process $proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$4344 in module $paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.
+Marked 3 switch rules as full_case in process $proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:807$4342 in module $paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.
+Marked 2 switch rules as full_case in process $proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:776$4338 in module $paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.
+Marked 47 switch rules as full_case in process $proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:700$4337 in module $paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.
+Marked 4 switch rules as full_case in process $proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:565$4313 in module $paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.
+Marked 1 switch rules as full_case in process $proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:430$4275 in module $paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.
+Removed 2 dead cases from process $proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:401$4272 in module $paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.
+Marked 2 switch rules as full_case in process $proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:401$4272 in module $paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.
+Marked 1 switch rules as full_case in process $proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:390$4267 in module $paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.
+Marked 1 switch rules as full_case in process $proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:325$4193 in module $paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.
+Marked 2 switch rules as full_case in process $proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/spimemio.v:697$748 in module spimemio_xfer.
+Marked 5 switch rules as full_case in process $proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/spimemio.v:609$724 in module spimemio_xfer.
+Marked 3 switch rules as full_case in process $proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/spimemio.v:369$694 in module spimemio.
+Marked 1 switch rules as full_case in process $proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/spimemio.v:243$626 in module spimemio.
+Marked 3 switch rules as full_case in process $proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/simpleuart.v:194$597 in module simpleuart.
+Marked 2 switch rules as full_case in process $proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/simpleuart.v:151$587 in module simpleuart.
+Marked 1 switch rules as full_case in process $proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/simpleuart.v:138$585 in module simpleuart.
+Marked 41 switch rules as full_case in process $proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1397$3989 in module $paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.
+Marked 2 switch rules as full_case in process $proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1304$3961 in module $paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.
+Marked 2 switch rules as full_case in process $proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1290$3956 in module $paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.
+Marked 8 switch rules as full_case in process $proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1181$3921 in module $paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.
+Marked 3 switch rules as full_case in process $proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$3661 in module $paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.
+Marked 3 switch rules as full_case in process $proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:807$3659 in module $paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.
+Marked 2 switch rules as full_case in process $proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:776$3655 in module $paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.
+Marked 47 switch rules as full_case in process $proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:700$3654 in module $paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.
+Marked 4 switch rules as full_case in process $proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:565$3630 in module $paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.
+Marked 1 switch rules as full_case in process $proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:430$3592 in module $paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.
+Removed 2 dead cases from process $proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:401$3589 in module $paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.
+Marked 2 switch rules as full_case in process $proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:401$3589 in module $paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.
+Marked 1 switch rules as full_case in process $proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:390$3584 in module $paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.
+Marked 1 switch rules as full_case in process $proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:325$3510 in module $paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.
+Marked 41 switch rules as full_case in process $proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1397$3306 in module $paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.
+Marked 2 switch rules as full_case in process $proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1304$3278 in module $paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.
+Marked 2 switch rules as full_case in process $proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1290$3273 in module $paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.
+Marked 8 switch rules as full_case in process $proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1181$3238 in module $paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.
+Marked 3 switch rules as full_case in process $proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$2978 in module $paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.
+Marked 3 switch rules as full_case in process $proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:807$2976 in module $paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.
+Marked 2 switch rules as full_case in process $proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:776$2972 in module $paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.
+Marked 47 switch rules as full_case in process $proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:700$2971 in module $paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.
+Marked 4 switch rules as full_case in process $proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:565$2947 in module $paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.
+Marked 1 switch rules as full_case in process $proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:430$2909 in module $paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.
+Removed 2 dead cases from process $proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:401$2906 in module $paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.
+Marked 2 switch rules as full_case in process $proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:401$2906 in module $paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.
+Marked 1 switch rules as full_case in process $proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:390$2901 in module $paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.
+Marked 1 switch rules as full_case in process $proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:325$2827 in module $paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.
+Marked 1 switch rules as full_case in process $proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:43$1931 in module $paramod\mem_ff_wb\MEM_WORDS=512.
+Removed 1 dead cases from process $proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/pinmux.v:71$1818 in module $paramod\pinmux\NUM_INPUTS=1\NUM_OUTPUTS=25\NUM_GPIOS=32.
+Marked 9 switch rules as full_case in process $proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/pinmux.v:71$1818 in module $paramod\pinmux\NUM_INPUTS=1\NUM_OUTPUTS=25\NUM_GPIOS=32.
+Marked 5 switch rules as full_case in process $proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/pcpi_flexio.v:152$258 in module pcpi_flexio.
+Marked 2 switch rules as full_case in process $proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/pcpi_flexio.v:135$254 in module pcpi_flexio.
+Marked 4 switch rules as full_case in process $proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/pcpi_flexio.v:96$250 in module pcpi_flexio.
+Marked 1 switch rules as full_case in process $proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/softshell_top.v:143$2 in module softshell_top.
+Removed a total of 7 dead cases.
+
+23.2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
+Removed 38 redundant assignments.
+Promoted 209 assignments to connections.
+
+23.2.4. Executing PROC_INIT pass (extract init attributes).
+Found init rule in `$paramod$922eeecdf93ea4da89c0f9a13b613ec8c6a19ae5\arbiter.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/verilog-wishbone/rtl/arbiter.v:77$2761'.
+ Set init value: \mask_reg = 4'0000
+Found init rule in `$paramod$922eeecdf93ea4da89c0f9a13b613ec8c6a19ae5\arbiter.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/verilog-wishbone/rtl/arbiter.v:56$2760'.
+ Set init value: \grant_encoded_reg = 2'00
+Found init rule in `$paramod$922eeecdf93ea4da89c0f9a13b613ec8c6a19ae5\arbiter.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/verilog-wishbone/rtl/arbiter.v:55$2759'.
+ Set init value: \grant_valid_reg = 1'0
+Found init rule in `$paramod$922eeecdf93ea4da89c0f9a13b613ec8c6a19ae5\arbiter.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/verilog-wishbone/rtl/arbiter.v:54$2758'.
+ Set init value: \grant_reg = 4'0000
+
+23.2.5. Executing PROC_ARST pass (detect async resets in processes).
+Found async reset \i_rd_reset_n in `$paramod\afifo\LGFIFO=2\WIDTH=32\OPT_REGISTER_READS=1'0.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:182$2024'.
+Found async reset \i_wr_reset_n in `$paramod\afifo\LGFIFO=2\WIDTH=32\OPT_REGISTER_READS=1'0.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:173$2022'.
+Found async reset \i_rd_reset_n in `$paramod\afifo\LGFIFO=2\WIDTH=32\OPT_REGISTER_READS=1'0.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:145$2014'.
+Found async reset \i_wr_reset_n in `$paramod\afifo\LGFIFO=2\WIDTH=32\OPT_REGISTER_READS=1'0.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:123$2001'.
+Found async reset \wb_rst_i in `$paramod\pinmux\NUM_INPUTS=1\NUM_OUTPUTS=25\NUM_GPIOS=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/pinmux.v:71$1818'.
+Found async reset \flexio_resetb in `\pcpi_flexio.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/pcpi_flexio.v:152$258'.
+Found async reset \flexio_resetb in `\pcpi_flexio.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/pcpi_flexio.v:135$254'.
+Found async reset \resetb in `\pcpi_flexio.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/pcpi_flexio.v:96$250'.
+Found async reset \reset_in in `\softshell_top.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/softshell_top.v:143$2'.
+
+23.2.6. Executing PROC_MUX pass (convert decision trees to multiplexers).
+Creating decoders for process `$paramod$922eeecdf93ea4da89c0f9a13b613ec8c6a19ae5\arbiter.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/verilog-wishbone/rtl/arbiter.v:77$2761'.
+Creating decoders for process `$paramod$922eeecdf93ea4da89c0f9a13b613ec8c6a19ae5\arbiter.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/verilog-wishbone/rtl/arbiter.v:56$2760'.
+Creating decoders for process `$paramod$922eeecdf93ea4da89c0f9a13b613ec8c6a19ae5\arbiter.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/verilog-wishbone/rtl/arbiter.v:55$2759'.
+Creating decoders for process `$paramod$922eeecdf93ea4da89c0f9a13b613ec8c6a19ae5\arbiter.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/verilog-wishbone/rtl/arbiter.v:54$2758'.
+Creating decoders for process `$paramod$922eeecdf93ea4da89c0f9a13b613ec8c6a19ae5\arbiter.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/verilog-wishbone/rtl/arbiter.v:139$2757'.
+ 1/4: $0\mask_reg[3:0]
+ 2/4: $0\grant_encoded_reg[1:0]
+ 3/4: $0\grant_valid_reg[0:0]
+ 4/4: $0\grant_reg[3:0]
+Creating decoders for process `$paramod$922eeecdf93ea4da89c0f9a13b613ec8c6a19ae5\arbiter.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/verilog-wishbone/rtl/arbiter.v:94$2746'.
+ 1/26: $8\mask_next[3:0]
+ 2/26: $7\mask_next[3:0]
+ 3/26: $6\mask_next[3:0]
+ 4/26: $6\grant_encoded_next[1:0]
+ 5/26: $6\grant_next[3:0]
+ 6/26: $6\grant_valid_next[0:0]
+ 7/26: $5\mask_next[3:0]
+ 8/26: $5\grant_encoded_next[1:0]
+ 9/26: $5\grant_valid_next[0:0]
+ 10/26: $5\grant_next[3:0]
+ 11/26: $4\mask_next[3:0]
+ 12/26: $4\grant_encoded_next[1:0]
+ 13/26: $4\grant_valid_next[0:0]
+ 14/26: $4\grant_next[3:0]
+ 15/26: $3\mask_next[3:0]
+ 16/26: $3\grant_encoded_next[1:0]
+ 17/26: $3\grant_valid_next[0:0]
+ 18/26: $3\grant_next[3:0]
+ 19/26: $2\grant_encoded_next[1:0]
+ 20/26: $2\grant_next[3:0]
+ 21/26: $2\grant_valid_next[0:0]
+ 22/26: $2\mask_next[3:0]
+ 23/26: $1\grant_encoded_next[1:0]
+ 24/26: $1\grant_next[3:0]
+ 25/26: $1\grant_valid_next[0:0]
+ 26/26: $1\mask_next[3:0]
+Creating decoders for process `$paramod$02c0b2a9118806de1d82e68e563b733cce432378\picorv32_wb.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:2994$2744'.
+ 1/9: $0\mem_rdata[31:0]
+ 2/9: $0\mem_ready[0:0]
+ 3/9: $0\state[1:0]
+ 4/9: $0\wbm_sel_o[3:0]
+ 5/9: $0\wbm_we_o[0:0]
+ 6/9: $0\wbm_cyc_o[0:0]
+ 7/9: $0\wbm_stb_o[0:0]
+ 8/9: $0\wbm_adr_o[31:0]
+ 9/9: $0\wbm_dat_o[31:0]
+Creating decoders for process `$paramod$e50444e694c9a9e823a24aefd7b9b454c7f28d7e\picorv32_wb.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:2994$2739'.
+ 1/9: $0\mem_rdata[31:0]
+ 2/9: $0\mem_ready[0:0]
+ 3/9: $0\state[1:0]
+ 4/9: $0\wbm_sel_o[3:0]
+ 5/9: $0\wbm_we_o[0:0]
+ 6/9: $0\wbm_cyc_o[0:0]
+ 7/9: $0\wbm_stb_o[0:0]
+ 8/9: $0\wbm_adr_o[31:0]
+ 9/9: $0\wbm_dat_o[31:0]
+Creating decoders for process `$paramod$d7c2e1f9a7f32b8e9c28fc8646c0275848e63526\picorv32_wb.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:2994$2734'.
+ 1/9: $0\mem_rdata[31:0]
+ 2/9: $0\mem_ready[0:0]
+ 3/9: $0\state[1:0]
+ 4/9: $0\wbm_sel_o[3:0]
+ 5/9: $0\wbm_we_o[0:0]
+ 6/9: $0\wbm_cyc_o[0:0]
+ 7/9: $0\wbm_stb_o[0:0]
+ 8/9: $0\wbm_adr_o[31:0]
+ 9/9: $0\wbm_dat_o[31:0]
+Creating decoders for process `$paramod\mem_ff_wb\MEM_WORDS=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:43$2721'.
+ 1/2: $0\wb_ack_o[0:0]
+ 2/2: $0\wb_ack_read[0:0]
+Creating decoders for process `$paramod$b48b6478f53991418334d339eb44ca404341ca26\gpio.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/gpio32_wb.v:102$2710'.
+ 1/6: $0\gpio_pd[31:0]
+ 2/6: $0\gpio_pu[31:0]
+ 3/6: $0\iomem_ready[0:0]
+ 4/6: $0\iomem_rdata[31:0]
+ 5/6: $0\gpio_oeb[31:0]
+ 6/6: $0\gpio_out[31:0]
+Creating decoders for process `$paramod\afifo\LGFIFO=2\WIDTH=32\OPT_REGISTER_READS=1'0.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:230$2033'.
+Creating decoders for process `$paramod\afifo\LGFIFO=2\WIDTH=32\OPT_REGISTER_READS=1'0.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:227$2032'.
+Creating decoders for process `$paramod\afifo\LGFIFO=2\WIDTH=32\OPT_REGISTER_READS=1'0.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:224$2031'.
+Creating decoders for process `$paramod\afifo\LGFIFO=2\WIDTH=32\OPT_REGISTER_READS=1'0.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:201$2029'.
+Creating decoders for process `$paramod\afifo\LGFIFO=2\WIDTH=32\OPT_REGISTER_READS=1'0.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:198$2026'.
+Creating decoders for process `$paramod\afifo\LGFIFO=2\WIDTH=32\OPT_REGISTER_READS=1'0.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:182$2024'.
+ 1/1: { $0\rd_wgray[2:0] $0\wgray_cross[2:0] }
+Creating decoders for process `$paramod\afifo\LGFIFO=2\WIDTH=32\OPT_REGISTER_READS=1'0.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:173$2022'.
+ 1/1: { $0\wr_rgray[2:0] $0\rgray_cross[2:0] }
+Creating decoders for process `$paramod\afifo\LGFIFO=2\WIDTH=32\OPT_REGISTER_READS=1'0.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:159$2020'.
+Creating decoders for process `$paramod\afifo\LGFIFO=2\WIDTH=32\OPT_REGISTER_READS=1'0.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:145$2014'.
+ 1/2: $0\rgray[2:0]
+ 2/2: $0\rd_addr[2:0]
+Creating decoders for process `$paramod\afifo\LGFIFO=2\WIDTH=32\OPT_REGISTER_READS=1'0.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:137$2007'.
+ 1/3: $0$memwr$\mem$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:139$1999_EN[31:0]$2010
+ 2/3: $0$memwr$\mem$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:139$1999_DATA[31:0]$2009
+ 3/3: $0$memwr$\mem$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:139$1999_ADDR[1:0]$2008
+Creating decoders for process `$paramod\afifo\LGFIFO=2\WIDTH=32\OPT_REGISTER_READS=1'0.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:123$2001'.
+ 1/2: $0\wgray[2:0]
+ 2/2: $0\wr_addr[2:0]
+Creating decoders for process `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1397$4672'.
+ 1/88: $23\next_irq_pending[2:2]
+ 2/88: $22\next_irq_pending[2:2]
+ 3/88: $21\next_irq_pending[2:2]
+ 4/88: $20\next_irq_pending[2:2]
+ 5/88: $19\next_irq_pending[2:2]
+ 6/88: $18\next_irq_pending[2:2]
+ 7/88: $17\next_irq_pending[2:2]
+ 8/88: $16\next_irq_pending[0:0]
+ 9/88: $15\next_irq_pending[0:0]
+ 10/88: $14\next_irq_pending[31:0] [0]
+ 11/88: $14\next_irq_pending[31:0] [31:1]
+ 12/88: $2\next_irq_pending[31:0] [31:2]
+ 13/88: $3\set_mem_do_rdata[0:0]
+ 14/88: $2\next_irq_pending[31:0] [1]
+ 15/88: $3\set_mem_do_wdata[0:0]
+ 16/88: $2\next_irq_pending[31:0] [0]
+ 17/88: $4\set_mem_do_rinst[0:0]
+ 18/88: $3\set_mem_do_rinst[0:0]
+ 19/88: $4\set_mem_do_wdata[0:0]
+ 20/88: $12\next_irq_pending[1:1]
+ 21/88: $11\next_irq_pending[1:1]
+ 22/88: $10\next_irq_pending[1:1]
+ 23/88: $4\set_mem_do_rdata[0:0]
+ 24/88: $8\next_irq_pending[1:1]
+ 25/88: $7\next_irq_pending[1:1]
+ 26/88: $6\next_irq_pending[1:1]
+ 27/88: $5\next_irq_pending[1:1]
+ 28/88: $4\next_irq_pending[1:1]
+ 29/88: $13\next_irq_pending[1:1]
+ 30/88: $5\set_mem_do_rinst[0:0]
+ 31/88: $9\next_irq_pending[1:1]
+ 32/88: $0\count_instr[63:0] [31:0]
+ 33/88: $3\next_irq_pending[31:0]
+ 34/88: $0\count_instr[63:0] [63:32]
+ 35/88: $2\current_pc[31:0]
+ 36/88: $2\set_mem_do_wdata[0:0]
+ 37/88: $2\set_mem_do_rdata[0:0]
+ 38/88: $2\set_mem_do_rinst[0:0]
+ 39/88: $1\next_irq_pending[31:0]
+ 40/88: $1\current_pc[31:0]
+ 41/88: $1\set_mem_do_wdata[0:0]
+ 42/88: $1\set_mem_do_rdata[0:0]
+ 43/88: $1\set_mem_do_rinst[0:0]
+ 44/88: $0\trace_data[35:0]
+ 45/88: $0\count_cycle[63:0] [63:32]
+ 46/88: $0\count_cycle[63:0] [31:0]
+ 47/88: $0\pcpi_timeout[0:0]
+ 48/88: $0\trace_valid[0:0]
+ 49/88: $0\do_waitirq[0:0]
+ 50/88: $0\decoder_pseudo_trigger[0:0]
+ 51/88: $0\decoder_trigger[0:0]
+ 52/88: $0\alu_wait_2[0:0]
+ 53/88: $0\alu_wait[0:0]
+ 54/88: $0\reg_out[31:0]
+ 55/88: $0\reg_sh[4:0]
+ 56/88: $0\trap[0:0]
+ 57/88: $0\pcpi_timeout_counter[3:0]
+ 58/88: $0\latched_rd[4:0]
+ 59/88: $0\latched_is_lb[0:0]
+ 60/88: $0\latched_is_lh[0:0]
+ 61/88: $0\latched_is_lu[0:0]
+ 62/88: $0\latched_trace[0:0]
+ 63/88: $0\latched_compr[0:0]
+ 64/88: $0\latched_branch[0:0]
+ 65/88: $0\latched_stalu[0:0]
+ 66/88: $0\latched_store[0:0]
+ 67/88: $0\irq_state[1:0]
+ 68/88: $0\cpu_state[7:0]
+ 69/88: $0\dbg_rs2val_valid[0:0]
+ 70/88: $0\dbg_rs1val_valid[0:0]
+ 71/88: $0\dbg_rs2val[31:0]
+ 72/88: $0\dbg_rs1val[31:0]
+ 73/88: $0\mem_do_wdata[0:0]
+ 74/88: $0\mem_do_rdata[0:0]
+ 75/88: $0\mem_do_rinst[0:0]
+ 76/88: $0\mem_do_prefetch[0:0]
+ 77/88: $0\mem_wordsize[1:0]
+ 78/88: $0\timer[31:0]
+ 79/88: $0\irq_mask[31:0]
+ 80/88: $0\irq_active[0:0]
+ 81/88: $0\irq_delay[0:0]
+ 82/88: $0\reg_op2[31:0]
+ 83/88: $0\reg_op1[31:0]
+ 84/88: $0\reg_next_pc[31:0]
+ 85/88: $0\reg_pc[31:0]
+ 86/88: $3\current_pc[31:0]
+ 87/88: $0\eoi[31:0]
+ 88/88: $0\pcpi_valid[0:0]
+Creating decoders for process `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1382$4658'.
+Creating decoders for process `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1304$4644'.
+ 1/4: $2\cpuregs_write[0:0]
+ 2/4: $2\cpuregs_wrdata[31:0]
+ 3/4: $1\cpuregs_wrdata[31:0]
+ 4/4: $1\cpuregs_write[0:0]
+Creating decoders for process `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1290$4639'.
+ 1/2: $2\clear_prefetched_high_word[0:0]
+ 2/2: $1\clear_prefetched_high_word[0:0]
+Creating decoders for process `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1288$4638'.
+Creating decoders for process `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1244$4616'.
+ 1/2: $1\alu_out[31:0]
+ 2/2: $1\alu_out_0[0:0]
+Creating decoders for process `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1181$4604'.
+ 1/8: $8\dbg_ascii_state[127:0]
+ 2/8: $7\dbg_ascii_state[127:0]
+ 3/8: $6\dbg_ascii_state[127:0]
+ 4/8: $5\dbg_ascii_state[127:0]
+ 5/8: $4\dbg_ascii_state[127:0]
+ 6/8: $3\dbg_ascii_state[127:0]
+ 7/8: $2\dbg_ascii_state[127:0]
+ 8/8: $1\dbg_ascii_state[127:0]
+Creating decoders for process `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$4344'.
+ 1/76: $0\decoded_rs1[4:0] [4]
+ 2/76: $0\decoded_imm_j[31:0] [10]
+ 3/76: $0\decoded_imm_j[31:0] [7]
+ 4/76: $0\decoded_imm_j[31:0] [6]
+ 5/76: $0\decoded_imm_j[31:0] [3:1]
+ 6/76: $0\decoded_imm_j[31:0] [5]
+ 7/76: $0\decoded_imm_j[31:0] [9:8]
+ 8/76: $0\decoded_imm_j[31:0] [31:20]
+ 9/76: $0\decoded_imm_j[31:0] [4]
+ 10/76: $0\decoded_imm_j[31:0] [11]
+ 11/76: $0\decoded_imm_j[31:0] [0]
+ 12/76: $0\decoded_rs1[4:0] [3:0]
+ 13/76: $0\is_lui_auipc_jal_jalr_addi_add_sub[0:0]
+ 14/76: $0\is_alu_reg_reg[0:0]
+ 15/76: $0\is_alu_reg_imm[0:0]
+ 16/76: $0\is_beq_bne_blt_bge_bltu_bgeu[0:0]
+ 17/76: $0\is_sll_srl_sra[0:0]
+ 18/76: $0\is_sb_sh_sw[0:0]
+ 19/76: $0\is_jalr_addi_slti_sltiu_xori_ori_andi[0:0]
+ 20/76: $0\is_slli_srli_srai[0:0]
+ 21/76: $0\is_lb_lh_lw_lbu_lhu[0:0]
+ 22/76: $0\compressed_instr[0:0]
+ 23/76: $0\is_compare[0:0]
+ 24/76: $0\decoded_imm[31:0]
+ 25/76: $0\decoded_rs2[4:0]
+ 26/76: $0\decoded_imm_j[31:0] [19:12]
+ 27/76: $0\decoded_rd[4:0]
+ 28/76: $0\instr_timer[0:0]
+ 29/76: $0\instr_waitirq[0:0]
+ 30/76: $0\instr_maskirq[0:0]
+ 31/76: $0\instr_retirq[0:0]
+ 32/76: $0\instr_setq[0:0]
+ 33/76: $0\instr_getq[0:0]
+ 34/76: $0\instr_ecall_ebreak[0:0]
+ 35/76: $0\instr_rdinstrh[0:0]
+ 36/76: $0\instr_rdinstr[0:0]
+ 37/76: $0\instr_rdcycleh[0:0]
+ 38/76: $0\instr_rdcycle[0:0]
+ 39/76: $0\instr_and[0:0]
+ 40/76: $0\instr_or[0:0]
+ 41/76: $0\instr_sra[0:0]
+ 42/76: $0\instr_srl[0:0]
+ 43/76: $0\instr_xor[0:0]
+ 44/76: $0\instr_sltu[0:0]
+ 45/76: $0\instr_slt[0:0]
+ 46/76: $0\instr_sll[0:0]
+ 47/76: $0\instr_sub[0:0]
+ 48/76: $0\instr_add[0:0]
+ 49/76: $0\instr_srai[0:0]
+ 50/76: $0\instr_srli[0:0]
+ 51/76: $0\instr_slli[0:0]
+ 52/76: $0\instr_andi[0:0]
+ 53/76: $0\instr_ori[0:0]
+ 54/76: $0\instr_xori[0:0]
+ 55/76: $0\instr_sltiu[0:0]
+ 56/76: $0\instr_slti[0:0]
+ 57/76: $0\instr_addi[0:0]
+ 58/76: $0\instr_sw[0:0]
+ 59/76: $0\instr_sh[0:0]
+ 60/76: $0\instr_sb[0:0]
+ 61/76: $0\instr_lhu[0:0]
+ 62/76: $0\instr_lbu[0:0]
+ 63/76: $0\instr_lw[0:0]
+ 64/76: $0\instr_lh[0:0]
+ 65/76: $0\instr_lb[0:0]
+ 66/76: $0\instr_bgeu[0:0]
+ 67/76: $0\instr_bltu[0:0]
+ 68/76: $0\instr_bge[0:0]
+ 69/76: $0\instr_blt[0:0]
+ 70/76: $0\instr_bne[0:0]
+ 71/76: $0\instr_beq[0:0]
+ 72/76: $0\instr_jalr[0:0]
+ 73/76: $0\instr_jal[0:0]
+ 74/76: $0\instr_auipc[0:0]
+ 75/76: $0\instr_lui[0:0]
+ 76/76: $0\pcpi_insn[31:0]
+Creating decoders for process `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:807$4342'.
+ 1/13: $3\dbg_insn_opcode[31:0]
+ 2/13: $2\dbg_insn_rd[4:0]
+ 3/13: $2\dbg_insn_rs2[4:0]
+ 4/13: $2\dbg_insn_rs1[4:0]
+ 5/13: $2\dbg_insn_opcode[31:0]
+ 6/13: $2\dbg_insn_imm[31:0]
+ 7/13: $2\dbg_ascii_instr[63:0]
+ 8/13: $1\dbg_insn_rd[4:0]
+ 9/13: $1\dbg_insn_rs2[4:0]
+ 10/13: $1\dbg_insn_rs1[4:0]
+ 11/13: $1\dbg_insn_imm[31:0]
+ 12/13: $1\dbg_ascii_instr[63:0]
+ 13/13: $1\dbg_insn_opcode[31:0]
+Creating decoders for process `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:776$4338'.
+ 1/8: $0\cached_insn_rd[4:0]
+ 2/8: $0\cached_insn_rs2[4:0]
+ 3/8: $0\cached_insn_rs1[4:0]
+ 4/8: $0\cached_insn_opcode[31:0]
+ 5/8: $0\cached_insn_imm[31:0]
+ 6/8: $0\cached_ascii_instr[63:0]
+ 7/8: $0\dbg_valid_insn[0:0]
+ 8/8: $0\dbg_insn_addr[31:0]
+Creating decoders for process `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:700$4337'.
+ 1/47: $47\new_ascii_instr[63:0]
+ 2/47: $46\new_ascii_instr[63:0]
+ 3/47: $45\new_ascii_instr[63:0]
+ 4/47: $44\new_ascii_instr[63:0]
+ 5/47: $43\new_ascii_instr[63:0]
+ 6/47: $42\new_ascii_instr[63:0]
+ 7/47: $41\new_ascii_instr[63:0]
+ 8/47: $40\new_ascii_instr[63:0]
+ 9/47: $39\new_ascii_instr[63:0]
+ 10/47: $38\new_ascii_instr[63:0]
+ 11/47: $37\new_ascii_instr[63:0]
+ 12/47: $36\new_ascii_instr[63:0]
+ 13/47: $35\new_ascii_instr[63:0]
+ 14/47: $34\new_ascii_instr[63:0]
+ 15/47: $33\new_ascii_instr[63:0]
+ 16/47: $32\new_ascii_instr[63:0]
+ 17/47: $31\new_ascii_instr[63:0]
+ 18/47: $30\new_ascii_instr[63:0]
+ 19/47: $29\new_ascii_instr[63:0]
+ 20/47: $28\new_ascii_instr[63:0]
+ 21/47: $27\new_ascii_instr[63:0]
+ 22/47: $26\new_ascii_instr[63:0]
+ 23/47: $25\new_ascii_instr[63:0]
+ 24/47: $24\new_ascii_instr[63:0]
+ 25/47: $23\new_ascii_instr[63:0]
+ 26/47: $22\new_ascii_instr[63:0]
+ 27/47: $21\new_ascii_instr[63:0]
+ 28/47: $20\new_ascii_instr[63:0]
+ 29/47: $19\new_ascii_instr[63:0]
+ 30/47: $18\new_ascii_instr[63:0]
+ 31/47: $17\new_ascii_instr[63:0]
+ 32/47: $16\new_ascii_instr[63:0]
+ 33/47: $15\new_ascii_instr[63:0]
+ 34/47: $14\new_ascii_instr[63:0]
+ 35/47: $13\new_ascii_instr[63:0]
+ 36/47: $12\new_ascii_instr[63:0]
+ 37/47: $11\new_ascii_instr[63:0]
+ 38/47: $10\new_ascii_instr[63:0]
+ 39/47: $9\new_ascii_instr[63:0]
+ 40/47: $8\new_ascii_instr[63:0]
+ 41/47: $7\new_ascii_instr[63:0]
+ 42/47: $6\new_ascii_instr[63:0]
+ 43/47: $5\new_ascii_instr[63:0]
+ 44/47: $4\new_ascii_instr[63:0]
+ 45/47: $3\new_ascii_instr[63:0]
+ 46/47: $2\new_ascii_instr[63:0]
+ 47/47: $1\new_ascii_instr[63:0]
+Creating decoders for process `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:565$4313'.
+ 1/9: $0\mem_16bit_buffer[15:0]
+ 2/9: $0\prefetched_high_word[0:0]
+ 3/9: $0\mem_la_secondword[0:0]
+ 4/9: $0\mem_state[1:0]
+ 5/9: $0\mem_wstrb[3:0]
+ 6/9: $0\mem_valid[0:0]
+ 7/9: $0\mem_addr[31:0]
+ 8/9: $0\mem_wdata[31:0]
+ 9/9: $0\mem_instr[0:0]
+Creating decoders for process `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1234$4852'.
+Creating decoders for process `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:430$4275'.
+ 1/9: $0\mem_rdata_q[31:0] [31]
+ 2/9: $0\mem_rdata_q[31:0] [7]
+ 3/9: $0\mem_rdata_q[31:0] [24:20]
+ 4/9: $0\mem_rdata_q[31:0] [19:15]
+ 5/9: $0\mem_rdata_q[31:0] [6:0]
+ 6/9: $0\mem_rdata_q[31:0] [14:12]
+ 7/9: $0\mem_rdata_q[31:0] [11:8]
+ 8/9: $0\mem_rdata_q[31:0] [30:25]
+ 9/9: $0\next_insn_opcode[31:0]
+Creating decoders for process `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:401$4272'.
+ 1/5: $3\mem_rdata_word[31:0]
+ 2/5: $2\mem_rdata_word[31:0]
+ 3/5: $1\mem_rdata_word[31:0]
+ 4/5: $1\mem_la_wstrb[3:0]
+ 5/5: $1\mem_la_wdata[31:0]
+Creating decoders for process `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:390$4267'.
+ 1/2: $0\last_mem_valid[0:0]
+ 2/2: $0\mem_la_firstword_reg[0:0]
+Creating decoders for process `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:325$4193'.
+ 1/2: $1\pcpi_int_rd[31:0]
+ 2/2: $1\pcpi_int_wr[0:0]
+Creating decoders for process `\spimemio_xfer.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/spimemio.v:697$748'.
+ 1/14: $0\last_fetch[0:0]
+ 2/14: $0\fetch[0:0]
+ 3/14: $0\xfer_tag[3:0]
+ 4/14: $0\xfer_rd[0:0]
+ 5/14: $0\xfer_qspi[0:0]
+ 6/14: $0\xfer_cont[0:0]
+ 7/14: $0\dummy_count[3:0]
+ 8/14: $0\count[3:0]
+ 9/14: $0\ibuffer[7:0]
+ 10/14: $0\obuffer[7:0]
+ 11/14: $0\xfer_ddr[0:0]
+ 12/14: $0\xfer_dspi[0:0]
+ 13/14: $0\flash_clk[0:0]
+ 14/14: $0\flash_csb[0:0]
+Creating decoders for process `\spimemio_xfer.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/spimemio.v:609$724'.
+ 1/33: $5\next_count[3:0]
+ 2/33: $5\next_obuffer[7:0]
+ 3/33: $5\next_ibuffer[7:0]
+ 4/33: $4\next_count[3:0]
+ 5/33: $4\next_obuffer[7:0]
+ 6/33: $4\next_ibuffer[7:0]
+ 7/33: $3\next_count[3:0]
+ 8/33: $3\next_obuffer[7:0]
+ 9/33: $3\next_ibuffer[7:0]
+ 10/33: $2\next_fetch[0:0]
+ 11/33: $2\next_count[3:0]
+ 12/33: $2\next_ibuffer[7:0]
+ 13/33: $2\next_obuffer[7:0]
+ 14/33: $2\flash_io0_do[0:0]
+ 15/33: $2\flash_io0_oe[0:0]
+ 16/33: $2\flash_io3_oe[0:0]
+ 17/33: $2\flash_io2_oe[0:0]
+ 18/33: $2\flash_io1_oe[0:0]
+ 19/33: $2\flash_io3_do[0:0]
+ 20/33: $2\flash_io2_do[0:0]
+ 21/33: $2\flash_io1_do[0:0]
+ 22/33: $1\next_fetch[0:0]
+ 23/33: $1\next_count[3:0]
+ 24/33: $1\next_ibuffer[7:0]
+ 25/33: $1\next_obuffer[7:0]
+ 26/33: $1\flash_io3_oe[0:0]
+ 27/33: $1\flash_io2_oe[0:0]
+ 28/33: $1\flash_io1_oe[0:0]
+ 29/33: $1\flash_io0_oe[0:0]
+ 30/33: $1\flash_io3_do[0:0]
+ 31/33: $1\flash_io2_do[0:0]
+ 32/33: $1\flash_io1_do[0:0]
+ 33/33: $1\flash_io0_do[0:0]
+Creating decoders for process `\spimemio_xfer.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/spimemio.v:598$715'.
+Creating decoders for process `\spimemio.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/spimemio.v:369$694'.
+ 1/17: $0\buffer[23:0] [23:16]
+ 2/17: $0\buffer[23:0] [15:8]
+ 3/17: $0\buffer[23:0] [7:0]
+ 4/17: $0\xfer_resetn[0:0]
+ 5/17: $0\state[3:0]
+ 6/17: $0\rd_inc[0:0]
+ 7/17: $0\rd_wait[0:0]
+ 8/17: $0\rd_valid[0:0]
+ 9/17: $0\rd_addr[23:0]
+ 10/17: $0\din_valid[0:0]
+ 11/17: $0\din_rd[0:0]
+ 12/17: $0\din_ddr[0:0]
+ 13/17: $0\din_qspi[0:0]
+ 14/17: $0\din_cont[0:0]
+ 15/17: $0\din_tag[3:0]
+ 16/17: $0\din_data[7:0]
+ 17/17: $0\rdata[31:0]
+Creating decoders for process `\spimemio.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/spimemio.v:295$630'.
+Creating decoders for process `\spimemio.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/spimemio.v:243$626'.
+ 1/10: $0\softreset[0:0]
+ 2/10: $0\config_do[3:0]
+ 3/10: $0\config_clk[0:0]
+ 4/10: $0\config_csb[0:0]
+ 5/10: $0\config_oe[3:0]
+ 6/10: $0\config_dummy[3:0]
+ 7/10: $0\config_cont[0:0]
+ 8/10: $0\config_qspi[0:0]
+ 9/10: $0\config_ddr[0:0]
+ 10/10: $0\config_en[0:0]
+Creating decoders for process `\simpleuart.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/simpleuart.v:194$597'.
+ 1/4: $0\send_divcnt[31:0]
+ 2/4: $0\send_dummy[0:0]
+ 3/4: $0\send_bitcnt[3:0]
+ 4/4: $0\send_pattern[9:0]
+Creating decoders for process `\simpleuart.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/simpleuart.v:151$587'.
+ 1/5: $0\recv_divcnt[31:0]
+ 2/5: $0\recv_buf_valid[0:0]
+ 3/5: $0\recv_buf_data[7:0]
+ 4/5: $0\recv_pattern[7:0]
+ 5/5: $0\recv_state[3:0]
+Creating decoders for process `\simpleuart.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/simpleuart.v:138$585'.
+ 1/5: $0\cfg_divider[31:0] [31:24]
+ 2/5: $0\cfg_divider[31:0] [23:16]
+ 3/5: $0\cfg_divider[31:0] [15:8]
+ 4/5: $0\cfg_divider[31:0] [7:0]
+ 5/5: $0\enabled[0:0]
+Creating decoders for process `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1397$3989'.
+ 1/88: $23\next_irq_pending[2:2]
+ 2/88: $22\next_irq_pending[2:2]
+ 3/88: $21\next_irq_pending[2:2]
+ 4/88: $20\next_irq_pending[2:2]
+ 5/88: $19\next_irq_pending[2:2]
+ 6/88: $18\next_irq_pending[2:2]
+ 7/88: $17\next_irq_pending[2:2]
+ 8/88: $16\next_irq_pending[0:0]
+ 9/88: $15\next_irq_pending[0:0]
+ 10/88: $14\next_irq_pending[31:0] [0]
+ 11/88: $14\next_irq_pending[31:0] [31:1]
+ 12/88: $2\next_irq_pending[31:0] [31:2]
+ 13/88: $3\set_mem_do_rdata[0:0]
+ 14/88: $2\next_irq_pending[31:0] [1]
+ 15/88: $3\set_mem_do_wdata[0:0]
+ 16/88: $2\next_irq_pending[31:0] [0]
+ 17/88: $4\set_mem_do_rinst[0:0]
+ 18/88: $3\set_mem_do_rinst[0:0]
+ 19/88: $4\set_mem_do_wdata[0:0]
+ 20/88: $12\next_irq_pending[1:1]
+ 21/88: $11\next_irq_pending[1:1]
+ 22/88: $10\next_irq_pending[1:1]
+ 23/88: $4\set_mem_do_rdata[0:0]
+ 24/88: $8\next_irq_pending[1:1]
+ 25/88: $7\next_irq_pending[1:1]
+ 26/88: $6\next_irq_pending[1:1]
+ 27/88: $5\next_irq_pending[1:1]
+ 28/88: $4\next_irq_pending[1:1]
+ 29/88: $13\next_irq_pending[1:1]
+ 30/88: $5\set_mem_do_rinst[0:0]
+ 31/88: $9\next_irq_pending[1:1]
+ 32/88: $0\count_instr[63:0] [31:0]
+ 33/88: $3\next_irq_pending[31:0]
+ 34/88: $0\count_instr[63:0] [63:32]
+ 35/88: $2\current_pc[31:0]
+ 36/88: $2\set_mem_do_wdata[0:0]
+ 37/88: $2\set_mem_do_rdata[0:0]
+ 38/88: $2\set_mem_do_rinst[0:0]
+ 39/88: $1\next_irq_pending[31:0]
+ 40/88: $1\current_pc[31:0]
+ 41/88: $1\set_mem_do_wdata[0:0]
+ 42/88: $1\set_mem_do_rdata[0:0]
+ 43/88: $1\set_mem_do_rinst[0:0]
+ 44/88: $0\trace_data[35:0]
+ 45/88: $0\count_cycle[63:0] [63:32]
+ 46/88: $0\count_cycle[63:0] [31:0]
+ 47/88: $0\pcpi_timeout[0:0]
+ 48/88: $0\trace_valid[0:0]
+ 49/88: $0\do_waitirq[0:0]
+ 50/88: $0\decoder_pseudo_trigger[0:0]
+ 51/88: $0\decoder_trigger[0:0]
+ 52/88: $0\alu_wait_2[0:0]
+ 53/88: $0\alu_wait[0:0]
+ 54/88: $0\reg_out[31:0]
+ 55/88: $0\reg_sh[4:0]
+ 56/88: $0\trap[0:0]
+ 57/88: $0\pcpi_timeout_counter[3:0]
+ 58/88: $0\latched_rd[4:0]
+ 59/88: $0\latched_is_lb[0:0]
+ 60/88: $0\latched_is_lh[0:0]
+ 61/88: $0\latched_is_lu[0:0]
+ 62/88: $0\latched_trace[0:0]
+ 63/88: $0\latched_compr[0:0]
+ 64/88: $0\latched_branch[0:0]
+ 65/88: $0\latched_stalu[0:0]
+ 66/88: $0\latched_store[0:0]
+ 67/88: $0\irq_state[1:0]
+ 68/88: $0\cpu_state[7:0]
+ 69/88: $0\dbg_rs2val_valid[0:0]
+ 70/88: $0\dbg_rs1val_valid[0:0]
+ 71/88: $0\dbg_rs2val[31:0]
+ 72/88: $0\dbg_rs1val[31:0]
+ 73/88: $0\mem_do_wdata[0:0]
+ 74/88: $0\mem_do_rdata[0:0]
+ 75/88: $0\mem_do_rinst[0:0]
+ 76/88: $0\mem_do_prefetch[0:0]
+ 77/88: $0\mem_wordsize[1:0]
+ 78/88: $0\timer[31:0]
+ 79/88: $0\irq_mask[31:0]
+ 80/88: $0\irq_active[0:0]
+ 81/88: $0\irq_delay[0:0]
+ 82/88: $0\reg_op2[31:0]
+ 83/88: $0\reg_op1[31:0]
+ 84/88: $0\reg_next_pc[31:0]
+ 85/88: $0\reg_pc[31:0]
+ 86/88: $3\current_pc[31:0]
+ 87/88: $0\eoi[31:0]
+ 88/88: $0\pcpi_valid[0:0]
+Creating decoders for process `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1382$3975'.
+Creating decoders for process `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1304$3961'.
+ 1/4: $2\cpuregs_write[0:0]
+ 2/4: $2\cpuregs_wrdata[31:0]
+ 3/4: $1\cpuregs_wrdata[31:0]
+ 4/4: $1\cpuregs_write[0:0]
+Creating decoders for process `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1290$3956'.
+ 1/2: $2\clear_prefetched_high_word[0:0]
+ 2/2: $1\clear_prefetched_high_word[0:0]
+Creating decoders for process `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1288$3955'.
+Creating decoders for process `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1244$3933'.
+ 1/2: $1\alu_out[31:0]
+ 2/2: $1\alu_out_0[0:0]
+Creating decoders for process `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1181$3921'.
+ 1/8: $8\dbg_ascii_state[127:0]
+ 2/8: $7\dbg_ascii_state[127:0]
+ 3/8: $6\dbg_ascii_state[127:0]
+ 4/8: $5\dbg_ascii_state[127:0]
+ 5/8: $4\dbg_ascii_state[127:0]
+ 6/8: $3\dbg_ascii_state[127:0]
+ 7/8: $2\dbg_ascii_state[127:0]
+ 8/8: $1\dbg_ascii_state[127:0]
+Creating decoders for process `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$3661'.
+ 1/76: $0\decoded_rs1[4:0] [4]
+ 2/76: $0\decoded_imm_j[31:0] [10]
+ 3/76: $0\decoded_imm_j[31:0] [7]
+ 4/76: $0\decoded_imm_j[31:0] [6]
+ 5/76: $0\decoded_imm_j[31:0] [3:1]
+ 6/76: $0\decoded_imm_j[31:0] [5]
+ 7/76: $0\decoded_imm_j[31:0] [9:8]
+ 8/76: $0\decoded_imm_j[31:0] [31:20]
+ 9/76: $0\decoded_imm_j[31:0] [4]
+ 10/76: $0\decoded_imm_j[31:0] [11]
+ 11/76: $0\decoded_imm_j[31:0] [0]
+ 12/76: $0\decoded_rs1[4:0] [3:0]
+ 13/76: $0\is_lui_auipc_jal_jalr_addi_add_sub[0:0]
+ 14/76: $0\is_alu_reg_reg[0:0]
+ 15/76: $0\is_alu_reg_imm[0:0]
+ 16/76: $0\is_beq_bne_blt_bge_bltu_bgeu[0:0]
+ 17/76: $0\is_sll_srl_sra[0:0]
+ 18/76: $0\is_sb_sh_sw[0:0]
+ 19/76: $0\is_jalr_addi_slti_sltiu_xori_ori_andi[0:0]
+ 20/76: $0\is_slli_srli_srai[0:0]
+ 21/76: $0\is_lb_lh_lw_lbu_lhu[0:0]
+ 22/76: $0\compressed_instr[0:0]
+ 23/76: $0\is_compare[0:0]
+ 24/76: $0\decoded_imm[31:0]
+ 25/76: $0\decoded_rs2[4:0]
+ 26/76: $0\decoded_imm_j[31:0] [19:12]
+ 27/76: $0\decoded_rd[4:0]
+ 28/76: $0\instr_timer[0:0]
+ 29/76: $0\instr_waitirq[0:0]
+ 30/76: $0\instr_maskirq[0:0]
+ 31/76: $0\instr_retirq[0:0]
+ 32/76: $0\instr_setq[0:0]
+ 33/76: $0\instr_getq[0:0]
+ 34/76: $0\instr_ecall_ebreak[0:0]
+ 35/76: $0\instr_rdinstrh[0:0]
+ 36/76: $0\instr_rdinstr[0:0]
+ 37/76: $0\instr_rdcycleh[0:0]
+ 38/76: $0\instr_rdcycle[0:0]
+ 39/76: $0\instr_and[0:0]
+ 40/76: $0\instr_or[0:0]
+ 41/76: $0\instr_sra[0:0]
+ 42/76: $0\instr_srl[0:0]
+ 43/76: $0\instr_xor[0:0]
+ 44/76: $0\instr_sltu[0:0]
+ 45/76: $0\instr_slt[0:0]
+ 46/76: $0\instr_sll[0:0]
+ 47/76: $0\instr_sub[0:0]
+ 48/76: $0\instr_add[0:0]
+ 49/76: $0\instr_srai[0:0]
+ 50/76: $0\instr_srli[0:0]
+ 51/76: $0\instr_slli[0:0]
+ 52/76: $0\instr_andi[0:0]
+ 53/76: $0\instr_ori[0:0]
+ 54/76: $0\instr_xori[0:0]
+ 55/76: $0\instr_sltiu[0:0]
+ 56/76: $0\instr_slti[0:0]
+ 57/76: $0\instr_addi[0:0]
+ 58/76: $0\instr_sw[0:0]
+ 59/76: $0\instr_sh[0:0]
+ 60/76: $0\instr_sb[0:0]
+ 61/76: $0\instr_lhu[0:0]
+ 62/76: $0\instr_lbu[0:0]
+ 63/76: $0\instr_lw[0:0]
+ 64/76: $0\instr_lh[0:0]
+ 65/76: $0\instr_lb[0:0]
+ 66/76: $0\instr_bgeu[0:0]
+ 67/76: $0\instr_bltu[0:0]
+ 68/76: $0\instr_bge[0:0]
+ 69/76: $0\instr_blt[0:0]
+ 70/76: $0\instr_bne[0:0]
+ 71/76: $0\instr_beq[0:0]
+ 72/76: $0\instr_jalr[0:0]
+ 73/76: $0\instr_jal[0:0]
+ 74/76: $0\instr_auipc[0:0]
+ 75/76: $0\instr_lui[0:0]
+ 76/76: $0\pcpi_insn[31:0]
+Creating decoders for process `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:807$3659'.
+ 1/13: $3\dbg_insn_opcode[31:0]
+ 2/13: $2\dbg_insn_rd[4:0]
+ 3/13: $2\dbg_insn_rs2[4:0]
+ 4/13: $2\dbg_insn_rs1[4:0]
+ 5/13: $2\dbg_insn_opcode[31:0]
+ 6/13: $2\dbg_insn_imm[31:0]
+ 7/13: $2\dbg_ascii_instr[63:0]
+ 8/13: $1\dbg_insn_rd[4:0]
+ 9/13: $1\dbg_insn_rs2[4:0]
+ 10/13: $1\dbg_insn_rs1[4:0]
+ 11/13: $1\dbg_insn_imm[31:0]
+ 12/13: $1\dbg_ascii_instr[63:0]
+ 13/13: $1\dbg_insn_opcode[31:0]
+Creating decoders for process `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:776$3655'.
+ 1/8: $0\cached_insn_rd[4:0]
+ 2/8: $0\cached_insn_rs2[4:0]
+ 3/8: $0\cached_insn_rs1[4:0]
+ 4/8: $0\cached_insn_opcode[31:0]
+ 5/8: $0\cached_insn_imm[31:0]
+ 6/8: $0\cached_ascii_instr[63:0]
+ 7/8: $0\dbg_valid_insn[0:0]
+ 8/8: $0\dbg_insn_addr[31:0]
+Creating decoders for process `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:700$3654'.
+ 1/47: $47\new_ascii_instr[63:0]
+ 2/47: $46\new_ascii_instr[63:0]
+ 3/47: $45\new_ascii_instr[63:0]
+ 4/47: $44\new_ascii_instr[63:0]
+ 5/47: $43\new_ascii_instr[63:0]
+ 6/47: $42\new_ascii_instr[63:0]
+ 7/47: $41\new_ascii_instr[63:0]
+ 8/47: $40\new_ascii_instr[63:0]
+ 9/47: $39\new_ascii_instr[63:0]
+ 10/47: $38\new_ascii_instr[63:0]
+ 11/47: $37\new_ascii_instr[63:0]
+ 12/47: $36\new_ascii_instr[63:0]
+ 13/47: $35\new_ascii_instr[63:0]
+ 14/47: $34\new_ascii_instr[63:0]
+ 15/47: $33\new_ascii_instr[63:0]
+ 16/47: $32\new_ascii_instr[63:0]
+ 17/47: $31\new_ascii_instr[63:0]
+ 18/47: $30\new_ascii_instr[63:0]
+ 19/47: $29\new_ascii_instr[63:0]
+ 20/47: $28\new_ascii_instr[63:0]
+ 21/47: $27\new_ascii_instr[63:0]
+ 22/47: $26\new_ascii_instr[63:0]
+ 23/47: $25\new_ascii_instr[63:0]
+ 24/47: $24\new_ascii_instr[63:0]
+ 25/47: $23\new_ascii_instr[63:0]
+ 26/47: $22\new_ascii_instr[63:0]
+ 27/47: $21\new_ascii_instr[63:0]
+ 28/47: $20\new_ascii_instr[63:0]
+ 29/47: $19\new_ascii_instr[63:0]
+ 30/47: $18\new_ascii_instr[63:0]
+ 31/47: $17\new_ascii_instr[63:0]
+ 32/47: $16\new_ascii_instr[63:0]
+ 33/47: $15\new_ascii_instr[63:0]
+ 34/47: $14\new_ascii_instr[63:0]
+ 35/47: $13\new_ascii_instr[63:0]
+ 36/47: $12\new_ascii_instr[63:0]
+ 37/47: $11\new_ascii_instr[63:0]
+ 38/47: $10\new_ascii_instr[63:0]
+ 39/47: $9\new_ascii_instr[63:0]
+ 40/47: $8\new_ascii_instr[63:0]
+ 41/47: $7\new_ascii_instr[63:0]
+ 42/47: $6\new_ascii_instr[63:0]
+ 43/47: $5\new_ascii_instr[63:0]
+ 44/47: $4\new_ascii_instr[63:0]
+ 45/47: $3\new_ascii_instr[63:0]
+ 46/47: $2\new_ascii_instr[63:0]
+ 47/47: $1\new_ascii_instr[63:0]
+Creating decoders for process `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:565$3630'.
+ 1/9: $0\mem_16bit_buffer[15:0]
+ 2/9: $0\prefetched_high_word[0:0]
+ 3/9: $0\mem_la_secondword[0:0]
+ 4/9: $0\mem_state[1:0]
+ 5/9: $0\mem_wstrb[3:0]
+ 6/9: $0\mem_valid[0:0]
+ 7/9: $0\mem_addr[31:0]
+ 8/9: $0\mem_wdata[31:0]
+ 9/9: $0\mem_instr[0:0]
+Creating decoders for process `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1234$4169'.
+Creating decoders for process `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:430$3592'.
+ 1/9: $0\mem_rdata_q[31:0] [31]
+ 2/9: $0\mem_rdata_q[31:0] [7]
+ 3/9: $0\mem_rdata_q[31:0] [24:20]
+ 4/9: $0\mem_rdata_q[31:0] [19:15]
+ 5/9: $0\mem_rdata_q[31:0] [6:0]
+ 6/9: $0\mem_rdata_q[31:0] [14:12]
+ 7/9: $0\mem_rdata_q[31:0] [11:8]
+ 8/9: $0\mem_rdata_q[31:0] [30:25]
+ 9/9: $0\next_insn_opcode[31:0]
+Creating decoders for process `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:401$3589'.
+ 1/5: $3\mem_rdata_word[31:0]
+ 2/5: $2\mem_rdata_word[31:0]
+ 3/5: $1\mem_rdata_word[31:0]
+ 4/5: $1\mem_la_wstrb[3:0]
+ 5/5: $1\mem_la_wdata[31:0]
+Creating decoders for process `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:390$3584'.
+ 1/2: $0\last_mem_valid[0:0]
+ 2/2: $0\mem_la_firstword_reg[0:0]
+Creating decoders for process `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:325$3510'.
+ 1/2: $1\pcpi_int_rd[31:0]
+ 2/2: $1\pcpi_int_wr[0:0]
+Creating decoders for process `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1397$3306'.
+ 1/88: $23\next_irq_pending[2:2]
+ 2/88: $22\next_irq_pending[2:2]
+ 3/88: $21\next_irq_pending[2:2]
+ 4/88: $20\next_irq_pending[2:2]
+ 5/88: $19\next_irq_pending[2:2]
+ 6/88: $18\next_irq_pending[2:2]
+ 7/88: $17\next_irq_pending[2:2]
+ 8/88: $16\next_irq_pending[0:0]
+ 9/88: $15\next_irq_pending[0:0]
+ 10/88: $14\next_irq_pending[31:0] [0]
+ 11/88: $14\next_irq_pending[31:0] [31:1]
+ 12/88: $2\next_irq_pending[31:0] [31:2]
+ 13/88: $3\set_mem_do_rdata[0:0]
+ 14/88: $2\next_irq_pending[31:0] [1]
+ 15/88: $3\set_mem_do_wdata[0:0]
+ 16/88: $2\next_irq_pending[31:0] [0]
+ 17/88: $4\set_mem_do_rinst[0:0]
+ 18/88: $3\set_mem_do_rinst[0:0]
+ 19/88: $4\set_mem_do_wdata[0:0]
+ 20/88: $12\next_irq_pending[1:1]
+ 21/88: $11\next_irq_pending[1:1]
+ 22/88: $10\next_irq_pending[1:1]
+ 23/88: $4\set_mem_do_rdata[0:0]
+ 24/88: $8\next_irq_pending[1:1]
+ 25/88: $7\next_irq_pending[1:1]
+ 26/88: $6\next_irq_pending[1:1]
+ 27/88: $5\next_irq_pending[1:1]
+ 28/88: $4\next_irq_pending[1:1]
+ 29/88: $13\next_irq_pending[1:1]
+ 30/88: $5\set_mem_do_rinst[0:0]
+ 31/88: $9\next_irq_pending[1:1]
+ 32/88: $0\count_instr[63:0] [31:0]
+ 33/88: $3\next_irq_pending[31:0]
+ 34/88: $0\count_instr[63:0] [63:32]
+ 35/88: $2\current_pc[31:0]
+ 36/88: $2\set_mem_do_wdata[0:0]
+ 37/88: $2\set_mem_do_rdata[0:0]
+ 38/88: $2\set_mem_do_rinst[0:0]
+ 39/88: $1\next_irq_pending[31:0]
+ 40/88: $1\current_pc[31:0]
+ 41/88: $1\set_mem_do_wdata[0:0]
+ 42/88: $1\set_mem_do_rdata[0:0]
+ 43/88: $1\set_mem_do_rinst[0:0]
+ 44/88: $0\trace_data[35:0]
+ 45/88: $0\count_cycle[63:0] [63:32]
+ 46/88: $0\count_cycle[63:0] [31:0]
+ 47/88: $0\pcpi_timeout[0:0]
+ 48/88: $0\trace_valid[0:0]
+ 49/88: $0\do_waitirq[0:0]
+ 50/88: $0\decoder_pseudo_trigger[0:0]
+ 51/88: $0\decoder_trigger[0:0]
+ 52/88: $0\alu_wait_2[0:0]
+ 53/88: $0\alu_wait[0:0]
+ 54/88: $0\reg_out[31:0]
+ 55/88: $0\reg_sh[4:0]
+ 56/88: $0\trap[0:0]
+ 57/88: $0\pcpi_timeout_counter[3:0]
+ 58/88: $0\latched_rd[4:0]
+ 59/88: $0\latched_is_lb[0:0]
+ 60/88: $0\latched_is_lh[0:0]
+ 61/88: $0\latched_is_lu[0:0]
+ 62/88: $0\latched_trace[0:0]
+ 63/88: $0\latched_compr[0:0]
+ 64/88: $0\latched_branch[0:0]
+ 65/88: $0\latched_stalu[0:0]
+ 66/88: $0\latched_store[0:0]
+ 67/88: $0\irq_state[1:0]
+ 68/88: $0\cpu_state[7:0]
+ 69/88: $0\dbg_rs2val_valid[0:0]
+ 70/88: $0\dbg_rs1val_valid[0:0]
+ 71/88: $0\dbg_rs2val[31:0]
+ 72/88: $0\dbg_rs1val[31:0]
+ 73/88: $0\mem_do_wdata[0:0]
+ 74/88: $0\mem_do_rdata[0:0]
+ 75/88: $0\mem_do_rinst[0:0]
+ 76/88: $0\mem_do_prefetch[0:0]
+ 77/88: $0\mem_wordsize[1:0]
+ 78/88: $0\timer[31:0]
+ 79/88: $0\irq_mask[31:0]
+ 80/88: $0\irq_active[0:0]
+ 81/88: $0\irq_delay[0:0]
+ 82/88: $0\reg_op2[31:0]
+ 83/88: $0\reg_op1[31:0]
+ 84/88: $0\reg_next_pc[31:0]
+ 85/88: $0\reg_pc[31:0]
+ 86/88: $3\current_pc[31:0]
+ 87/88: $0\eoi[31:0]
+ 88/88: $0\pcpi_valid[0:0]
+Creating decoders for process `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1382$3292'.
+Creating decoders for process `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1304$3278'.
+ 1/4: $2\cpuregs_write[0:0]
+ 2/4: $2\cpuregs_wrdata[31:0]
+ 3/4: $1\cpuregs_wrdata[31:0]
+ 4/4: $1\cpuregs_write[0:0]
+Creating decoders for process `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1290$3273'.
+ 1/2: $2\clear_prefetched_high_word[0:0]
+ 2/2: $1\clear_prefetched_high_word[0:0]
+Creating decoders for process `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1288$3272'.
+Creating decoders for process `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1244$3250'.
+ 1/2: $1\alu_out[31:0]
+ 2/2: $1\alu_out_0[0:0]
+Creating decoders for process `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1181$3238'.
+ 1/8: $8\dbg_ascii_state[127:0]
+ 2/8: $7\dbg_ascii_state[127:0]
+ 3/8: $6\dbg_ascii_state[127:0]
+ 4/8: $5\dbg_ascii_state[127:0]
+ 5/8: $4\dbg_ascii_state[127:0]
+ 6/8: $3\dbg_ascii_state[127:0]
+ 7/8: $2\dbg_ascii_state[127:0]
+ 8/8: $1\dbg_ascii_state[127:0]
+Creating decoders for process `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$2978'.
+ 1/76: $0\decoded_rs1[4:0] [4]
+ 2/76: $0\decoded_imm_j[31:0] [10]
+ 3/76: $0\decoded_imm_j[31:0] [7]
+ 4/76: $0\decoded_imm_j[31:0] [6]
+ 5/76: $0\decoded_imm_j[31:0] [3:1]
+ 6/76: $0\decoded_imm_j[31:0] [5]
+ 7/76: $0\decoded_imm_j[31:0] [9:8]
+ 8/76: $0\decoded_imm_j[31:0] [31:20]
+ 9/76: $0\decoded_imm_j[31:0] [4]
+ 10/76: $0\decoded_imm_j[31:0] [11]
+ 11/76: $0\decoded_imm_j[31:0] [0]
+ 12/76: $0\decoded_rs1[4:0] [3:0]
+ 13/76: $0\is_lui_auipc_jal_jalr_addi_add_sub[0:0]
+ 14/76: $0\is_alu_reg_reg[0:0]
+ 15/76: $0\is_alu_reg_imm[0:0]
+ 16/76: $0\is_beq_bne_blt_bge_bltu_bgeu[0:0]
+ 17/76: $0\is_sll_srl_sra[0:0]
+ 18/76: $0\is_sb_sh_sw[0:0]
+ 19/76: $0\is_jalr_addi_slti_sltiu_xori_ori_andi[0:0]
+ 20/76: $0\is_slli_srli_srai[0:0]
+ 21/76: $0\is_lb_lh_lw_lbu_lhu[0:0]
+ 22/76: $0\compressed_instr[0:0]
+ 23/76: $0\is_compare[0:0]
+ 24/76: $0\decoded_imm[31:0]
+ 25/76: $0\decoded_rs2[4:0]
+ 26/76: $0\decoded_imm_j[31:0] [19:12]
+ 27/76: $0\decoded_rd[4:0]
+ 28/76: $0\instr_timer[0:0]
+ 29/76: $0\instr_waitirq[0:0]
+ 30/76: $0\instr_maskirq[0:0]
+ 31/76: $0\instr_retirq[0:0]
+ 32/76: $0\instr_setq[0:0]
+ 33/76: $0\instr_getq[0:0]
+ 34/76: $0\instr_ecall_ebreak[0:0]
+ 35/76: $0\instr_rdinstrh[0:0]
+ 36/76: $0\instr_rdinstr[0:0]
+ 37/76: $0\instr_rdcycleh[0:0]
+ 38/76: $0\instr_rdcycle[0:0]
+ 39/76: $0\instr_and[0:0]
+ 40/76: $0\instr_or[0:0]
+ 41/76: $0\instr_sra[0:0]
+ 42/76: $0\instr_srl[0:0]
+ 43/76: $0\instr_xor[0:0]
+ 44/76: $0\instr_sltu[0:0]
+ 45/76: $0\instr_slt[0:0]
+ 46/76: $0\instr_sll[0:0]
+ 47/76: $0\instr_sub[0:0]
+ 48/76: $0\instr_add[0:0]
+ 49/76: $0\instr_srai[0:0]
+ 50/76: $0\instr_srli[0:0]
+ 51/76: $0\instr_slli[0:0]
+ 52/76: $0\instr_andi[0:0]
+ 53/76: $0\instr_ori[0:0]
+ 54/76: $0\instr_xori[0:0]
+ 55/76: $0\instr_sltiu[0:0]
+ 56/76: $0\instr_slti[0:0]
+ 57/76: $0\instr_addi[0:0]
+ 58/76: $0\instr_sw[0:0]
+ 59/76: $0\instr_sh[0:0]
+ 60/76: $0\instr_sb[0:0]
+ 61/76: $0\instr_lhu[0:0]
+ 62/76: $0\instr_lbu[0:0]
+ 63/76: $0\instr_lw[0:0]
+ 64/76: $0\instr_lh[0:0]
+ 65/76: $0\instr_lb[0:0]
+ 66/76: $0\instr_bgeu[0:0]
+ 67/76: $0\instr_bltu[0:0]
+ 68/76: $0\instr_bge[0:0]
+ 69/76: $0\instr_blt[0:0]
+ 70/76: $0\instr_bne[0:0]
+ 71/76: $0\instr_beq[0:0]
+ 72/76: $0\instr_jalr[0:0]
+ 73/76: $0\instr_jal[0:0]
+ 74/76: $0\instr_auipc[0:0]
+ 75/76: $0\instr_lui[0:0]
+ 76/76: $0\pcpi_insn[31:0]
+Creating decoders for process `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:807$2976'.
+ 1/13: $3\dbg_insn_opcode[31:0]
+ 2/13: $2\dbg_insn_rd[4:0]
+ 3/13: $2\dbg_insn_rs2[4:0]
+ 4/13: $2\dbg_insn_rs1[4:0]
+ 5/13: $2\dbg_insn_opcode[31:0]
+ 6/13: $2\dbg_insn_imm[31:0]
+ 7/13: $2\dbg_ascii_instr[63:0]
+ 8/13: $1\dbg_insn_rd[4:0]
+ 9/13: $1\dbg_insn_rs2[4:0]
+ 10/13: $1\dbg_insn_rs1[4:0]
+ 11/13: $1\dbg_insn_imm[31:0]
+ 12/13: $1\dbg_ascii_instr[63:0]
+ 13/13: $1\dbg_insn_opcode[31:0]
+Creating decoders for process `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:776$2972'.
+ 1/8: $0\cached_insn_rd[4:0]
+ 2/8: $0\cached_insn_rs2[4:0]
+ 3/8: $0\cached_insn_rs1[4:0]
+ 4/8: $0\cached_insn_opcode[31:0]
+ 5/8: $0\cached_insn_imm[31:0]
+ 6/8: $0\cached_ascii_instr[63:0]
+ 7/8: $0\dbg_valid_insn[0:0]
+ 8/8: $0\dbg_insn_addr[31:0]
+Creating decoders for process `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:700$2971'.
+ 1/47: $47\new_ascii_instr[63:0]
+ 2/47: $46\new_ascii_instr[63:0]
+ 3/47: $45\new_ascii_instr[63:0]
+ 4/47: $44\new_ascii_instr[63:0]
+ 5/47: $43\new_ascii_instr[63:0]
+ 6/47: $42\new_ascii_instr[63:0]
+ 7/47: $41\new_ascii_instr[63:0]
+ 8/47: $40\new_ascii_instr[63:0]
+ 9/47: $39\new_ascii_instr[63:0]
+ 10/47: $38\new_ascii_instr[63:0]
+ 11/47: $37\new_ascii_instr[63:0]
+ 12/47: $36\new_ascii_instr[63:0]
+ 13/47: $35\new_ascii_instr[63:0]
+ 14/47: $34\new_ascii_instr[63:0]
+ 15/47: $33\new_ascii_instr[63:0]
+ 16/47: $32\new_ascii_instr[63:0]
+ 17/47: $31\new_ascii_instr[63:0]
+ 18/47: $30\new_ascii_instr[63:0]
+ 19/47: $29\new_ascii_instr[63:0]
+ 20/47: $28\new_ascii_instr[63:0]
+ 21/47: $27\new_ascii_instr[63:0]
+ 22/47: $26\new_ascii_instr[63:0]
+ 23/47: $25\new_ascii_instr[63:0]
+ 24/47: $24\new_ascii_instr[63:0]
+ 25/47: $23\new_ascii_instr[63:0]
+ 26/47: $22\new_ascii_instr[63:0]
+ 27/47: $21\new_ascii_instr[63:0]
+ 28/47: $20\new_ascii_instr[63:0]
+ 29/47: $19\new_ascii_instr[63:0]
+ 30/47: $18\new_ascii_instr[63:0]
+ 31/47: $17\new_ascii_instr[63:0]
+ 32/47: $16\new_ascii_instr[63:0]
+ 33/47: $15\new_ascii_instr[63:0]
+ 34/47: $14\new_ascii_instr[63:0]
+ 35/47: $13\new_ascii_instr[63:0]
+ 36/47: $12\new_ascii_instr[63:0]
+ 37/47: $11\new_ascii_instr[63:0]
+ 38/47: $10\new_ascii_instr[63:0]
+ 39/47: $9\new_ascii_instr[63:0]
+ 40/47: $8\new_ascii_instr[63:0]
+ 41/47: $7\new_ascii_instr[63:0]
+ 42/47: $6\new_ascii_instr[63:0]
+ 43/47: $5\new_ascii_instr[63:0]
+ 44/47: $4\new_ascii_instr[63:0]
+ 45/47: $3\new_ascii_instr[63:0]
+ 46/47: $2\new_ascii_instr[63:0]
+ 47/47: $1\new_ascii_instr[63:0]
+Creating decoders for process `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:565$2947'.
+ 1/9: $0\mem_16bit_buffer[15:0]
+ 2/9: $0\prefetched_high_word[0:0]
+ 3/9: $0\mem_la_secondword[0:0]
+ 4/9: $0\mem_state[1:0]
+ 5/9: $0\mem_wstrb[3:0]
+ 6/9: $0\mem_valid[0:0]
+ 7/9: $0\mem_addr[31:0]
+ 8/9: $0\mem_wdata[31:0]
+ 9/9: $0\mem_instr[0:0]
+Creating decoders for process `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1234$3486'.
+Creating decoders for process `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:430$2909'.
+ 1/9: $0\mem_rdata_q[31:0] [31]
+ 2/9: $0\mem_rdata_q[31:0] [7]
+ 3/9: $0\mem_rdata_q[31:0] [24:20]
+ 4/9: $0\mem_rdata_q[31:0] [19:15]
+ 5/9: $0\mem_rdata_q[31:0] [6:0]
+ 6/9: $0\mem_rdata_q[31:0] [14:12]
+ 7/9: $0\mem_rdata_q[31:0] [11:8]
+ 8/9: $0\mem_rdata_q[31:0] [30:25]
+ 9/9: $0\next_insn_opcode[31:0]
+Creating decoders for process `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:401$2906'.
+ 1/5: $3\mem_rdata_word[31:0]
+ 2/5: $2\mem_rdata_word[31:0]
+ 3/5: $1\mem_rdata_word[31:0]
+ 4/5: $1\mem_la_wstrb[3:0]
+ 5/5: $1\mem_la_wdata[31:0]
+Creating decoders for process `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:390$2901'.
+ 1/2: $0\last_mem_valid[0:0]
+ 2/2: $0\mem_la_firstword_reg[0:0]
+Creating decoders for process `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:325$2827'.
+ 1/2: $1\pcpi_int_rd[31:0]
+ 2/2: $1\pcpi_int_wr[0:0]
+Creating decoders for process `$paramod\ff32_ram\ADDR_WIDTH=5.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:114$2805'.
+ 1/4: $0\dout[31:0] [31:24]
+ 2/4: $0\dout[31:0] [23:16]
+ 3/4: $0\dout[31:0] [15:8]
+ 4/4: $0\dout[31:0] [7:0]
+Creating decoders for process `$paramod\ff32_ram\ADDR_WIDTH=5.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:100$2792'.
+ 1/12: $0$memwr$\ram0$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:103$2788_EN[7:0]$2795
+ 2/12: $0$memwr$\ram0$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:103$2788_DATA[7:0]$2794
+ 3/12: $0$memwr$\ram0$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:103$2788_ADDR[4:0]$2793
+ 4/12: $0$memwr$\ram1$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:105$2789_EN[7:0]$2798
+ 5/12: $0$memwr$\ram1$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:105$2789_DATA[7:0]$2797
+ 6/12: $0$memwr$\ram1$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:105$2789_ADDR[4:0]$2796
+ 7/12: $0$memwr$\ram2$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:107$2790_EN[7:0]$2801
+ 8/12: $0$memwr$\ram2$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:107$2790_DATA[7:0]$2800
+ 9/12: $0$memwr$\ram2$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:107$2790_ADDR[4:0]$2799
+ 10/12: $0$memwr$\ram3$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:109$2791_EN[7:0]$2804
+ 11/12: $0$memwr$\ram3$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:109$2791_DATA[7:0]$2803
+ 12/12: $0$memwr$\ram3$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:109$2791_ADDR[4:0]$2802
+Creating decoders for process `$paramod\ff32_ram\ADDR_WIDTH=9.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:114$2779'.
+ 1/4: $0\dout[31:0] [31:24]
+ 2/4: $0\dout[31:0] [23:16]
+ 3/4: $0\dout[31:0] [15:8]
+ 4/4: $0\dout[31:0] [7:0]
+Creating decoders for process `$paramod\ff32_ram\ADDR_WIDTH=9.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:100$2766'.
+ 1/12: $0$memwr$\ram0$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:103$2762_EN[7:0]$2769
+ 2/12: $0$memwr$\ram0$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:103$2762_DATA[7:0]$2768
+ 3/12: $0$memwr$\ram0$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:103$2762_ADDR[8:0]$2767
+ 4/12: $0$memwr$\ram1$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:105$2763_EN[7:0]$2772
+ 5/12: $0$memwr$\ram1$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:105$2763_DATA[7:0]$2771
+ 6/12: $0$memwr$\ram1$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:105$2763_ADDR[8:0]$2770
+ 7/12: $0$memwr$\ram2$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:107$2764_EN[7:0]$2775
+ 8/12: $0$memwr$\ram2$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:107$2764_DATA[7:0]$2774
+ 9/12: $0$memwr$\ram2$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:107$2764_ADDR[8:0]$2773
+ 10/12: $0$memwr$\ram3$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:109$2765_EN[7:0]$2778
+ 11/12: $0$memwr$\ram3$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:109$2765_DATA[7:0]$2777
+ 12/12: $0$memwr$\ram3$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:109$2765_ADDR[8:0]$2776
+Creating decoders for process `$paramod\mem_ff_wb\MEM_WORDS=512.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:43$1931'.
+ 1/2: $0\wb_ack_o[0:0]
+ 2/2: $0\wb_ack_read[0:0]
+Creating decoders for process `$paramod\pinmux\NUM_INPUTS=1\NUM_OUTPUTS=25\NUM_GPIOS=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/pinmux.v:71$1818'.
+ 1/70: $5$mem2reg_wr$\reg_mux_out$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/pinmux.v:96$1810_ADDR[4:0]$1861
+ 2/70: $5$mem2reg_wr$\reg_mux_out$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/pinmux.v:96$1810_DATA[4:0]$1862
+ 3/70: $5$mem2reg_rd$\reg_mux_out$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/pinmux.v:94$1809_DATA[4:0]$1860
+ 4/70: $4$mem2reg_wr$\reg_mux_out$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/pinmux.v:96$1810_DATA[4:0]$1859
+ 5/70: $4$mem2reg_wr$\reg_mux_out$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/pinmux.v:96$1810_ADDR[4:0]$1858
+ 6/70: $4$mem2reg_rd$\reg_mux_out$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/pinmux.v:94$1809_DATA[4:0]$1857
+ 7/70: $4$mem2reg_rd$\reg_mux_out$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/pinmux.v:94$1809_ADDR[4:0]$1856
+ 8/70: $4$mem2reg_wr$\reg_mux_in$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/pinmux.v:90$1808_ADDR[0:0]$1854
+ 9/70: $4$mem2reg_wr$\reg_mux_in$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/pinmux.v:90$1808_DATA[5:0]$1855
+ 10/70: $4$mem2reg_rd$\reg_mux_in$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/pinmux.v:88$1807_DATA[5:0]$1853
+ 11/70: $3$mem2reg_wr$\reg_mux_in$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/pinmux.v:90$1808_DATA[5:0]$1848
+ 12/70: $3$mem2reg_wr$\reg_mux_in$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/pinmux.v:90$1808_ADDR[0:0]$1847
+ 13/70: $3$mem2reg_rd$\reg_mux_in$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/pinmux.v:88$1807_DATA[5:0]$1846
+ 14/70: $3$mem2reg_rd$\reg_mux_in$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/pinmux.v:88$1807_ADDR[0:0]$1845
+ 15/70: $3$mem2reg_wr$\reg_mux_out$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/pinmux.v:96$1810_DATA[4:0]$1852
+ 16/70: $3$mem2reg_wr$\reg_mux_out$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/pinmux.v:96$1810_ADDR[4:0]$1851
+ 17/70: $3$mem2reg_rd$\reg_mux_out$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/pinmux.v:94$1809_DATA[4:0]$1850
+ 18/70: $3$mem2reg_rd$\reg_mux_out$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/pinmux.v:94$1809_ADDR[4:0]$1849
+ 19/70: $2$mem2reg_wr$\reg_mux_out$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/pinmux.v:96$1810_DATA[4:0]$1844
+ 20/70: $2$mem2reg_wr$\reg_mux_out$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/pinmux.v:96$1810_ADDR[4:0]$1843
+ 21/70: $2$mem2reg_rd$\reg_mux_out$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/pinmux.v:94$1809_DATA[4:0]$1842
+ 22/70: $2$mem2reg_rd$\reg_mux_out$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/pinmux.v:94$1809_ADDR[4:0]$1841
+ 23/70: $2$mem2reg_wr$\reg_mux_in$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/pinmux.v:90$1808_DATA[5:0]$1840
+ 24/70: $2$mem2reg_wr$\reg_mux_in$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/pinmux.v:90$1808_ADDR[0:0]$1839
+ 25/70: $2$mem2reg_rd$\reg_mux_in$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/pinmux.v:88$1807_DATA[5:0]$1838
+ 26/70: $2$mem2reg_rd$\reg_mux_in$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/pinmux.v:88$1807_ADDR[0:0]$1837
+ 27/70: $1$mem2reg_wr$\reg_mux_out$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/pinmux.v:96$1810_DATA[4:0]$1834
+ 28/70: $1$mem2reg_wr$\reg_mux_out$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/pinmux.v:96$1810_ADDR[4:0]$1833
+ 29/70: $1$mem2reg_rd$\reg_mux_out$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/pinmux.v:94$1809_DATA[4:0]$1832
+ 30/70: $1$mem2reg_rd$\reg_mux_out$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/pinmux.v:94$1809_ADDR[4:0]$1831
+ 31/70: $1$mem2reg_wr$\reg_mux_in$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/pinmux.v:90$1808_DATA[5:0]$1830
+ 32/70: $1$mem2reg_wr$\reg_mux_in$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/pinmux.v:90$1808_ADDR[0:0]$1829
+ 33/70: $1$mem2reg_rd$\reg_mux_in$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/pinmux.v:88$1807_DATA[5:0]$1828
+ 34/70: $1$mem2reg_rd$\reg_mux_in$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/pinmux.v:88$1807_ADDR[0:0]$1827
+ 35/70: $0\wb_ack_o[0:0]
+ 36/70: $1\i[31:0]
+ 37/70: $0\reg_mux_out[31][4:0]
+ 38/70: $0\reg_mux_out[30][4:0]
+ 39/70: $0\reg_mux_out[29][4:0]
+ 40/70: $0\reg_mux_out[28][4:0]
+ 41/70: $0\reg_mux_out[27][4:0]
+ 42/70: $0\reg_mux_out[26][4:0]
+ 43/70: $0\reg_mux_out[25][4:0]
+ 44/70: $0\reg_mux_out[24][4:0]
+ 45/70: $0\reg_mux_out[23][4:0]
+ 46/70: $0\reg_mux_out[22][4:0]
+ 47/70: $0\reg_mux_out[21][4:0]
+ 48/70: $0\reg_mux_out[20][4:0]
+ 49/70: $0\reg_mux_out[19][4:0]
+ 50/70: $0\reg_mux_out[18][4:0]
+ 51/70: $0\reg_mux_out[17][4:0]
+ 52/70: $0\reg_mux_out[16][4:0]
+ 53/70: $0\reg_mux_out[15][4:0]
+ 54/70: $0\reg_mux_out[14][4:0]
+ 55/70: $0\reg_mux_out[13][4:0]
+ 56/70: $0\reg_mux_out[12][4:0]
+ 57/70: $0\reg_mux_out[11][4:0]
+ 58/70: $0\reg_mux_out[10][4:0]
+ 59/70: $0\reg_mux_out[9][4:0]
+ 60/70: $0\reg_mux_out[8][4:0]
+ 61/70: $0\reg_mux_out[7][4:0]
+ 62/70: $0\reg_mux_out[6][4:0]
+ 63/70: $0\reg_mux_out[5][4:0]
+ 64/70: $0\reg_mux_out[4][4:0]
+ 65/70: $0\reg_mux_out[3][4:0]
+ 66/70: $0\reg_mux_out[2][4:0]
+ 67/70: $0\reg_mux_out[1][4:0]
+ 68/70: $0\reg_mux_out[0][4:0]
+ 69/70: $0\reg_mux_in[0][5:0]
+ 70/70: $0\wb_dat_o[31:0]
+Creating decoders for process `\pcpi_flexio.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/pcpi_flexio.v:152$258'.
+ 1/3: $0\out_rd_en[0:0]
+ 2/3: $0\out_shift_cnt[4:0]
+ 3/3: $0\out_shift_reg[31:0]
+Creating decoders for process `\pcpi_flexio.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/pcpi_flexio.v:135$254'.
+ 1/2: $0\clk_en[0:0]
+ 2/2: $0\clk_div_cnt[23:0]
+Creating decoders for process `\pcpi_flexio.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/pcpi_flexio.v:96$250'.
+ 1/7: $0\out_wr_en[0:0]
+ 2/7: $0\pcpi_wait[0:0]
+ 3/7: $0\pcpi_ready[0:0]
+ 4/7: $0\out_wr_data[31:0]
+ 5/7: $0\cfg_clk_div[23:0]
+ 6/7: $0\cfg_bits_per_clock[3:0]
+ 7/7: $0\cfg_out_bit_mask[7:0]
+Creating decoders for process `\mgmt_soc_regs.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/rv_core.v:285$26'.
+ 1/3: $0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/rv_core.v:286$25_EN[31:0]$29
+ 2/3: $0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/rv_core.v:286$25_DATA[31:0]$28
+ 3/3: $0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/rv_core.v:286$25_ADDR[4:0]$27
+Creating decoders for process `\softshell_top.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/softshell_top.v:0$22'.
+Creating decoders for process `\softshell_top.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/softshell_top.v:143$2'.
+ 1/1: $0\reset_pipe[2:0]
+
+23.2.7. Executing PROC_DLATCH pass (convert process syncs to latches).
+No latch inferred for signal `$paramod$922eeecdf93ea4da89c0f9a13b613ec8c6a19ae5\arbiter.\grant_next' from process `$paramod$922eeecdf93ea4da89c0f9a13b613ec8c6a19ae5\arbiter.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/verilog-wishbone/rtl/arbiter.v:94$2746'.
+No latch inferred for signal `$paramod$922eeecdf93ea4da89c0f9a13b613ec8c6a19ae5\arbiter.\grant_valid_next' from process `$paramod$922eeecdf93ea4da89c0f9a13b613ec8c6a19ae5\arbiter.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/verilog-wishbone/rtl/arbiter.v:94$2746'.
+No latch inferred for signal `$paramod$922eeecdf93ea4da89c0f9a13b613ec8c6a19ae5\arbiter.\grant_encoded_next' from process `$paramod$922eeecdf93ea4da89c0f9a13b613ec8c6a19ae5\arbiter.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/verilog-wishbone/rtl/arbiter.v:94$2746'.
+No latch inferred for signal `$paramod$922eeecdf93ea4da89c0f9a13b613ec8c6a19ae5\arbiter.\mask_next' from process `$paramod$922eeecdf93ea4da89c0f9a13b613ec8c6a19ae5\arbiter.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/verilog-wishbone/rtl/arbiter.v:94$2746'.
+No latch inferred for signal `$paramod\afifo\LGFIFO=2\WIDTH=32\OPT_REGISTER_READS=1'0.\o_rd_data' from process `$paramod\afifo\LGFIFO=2\WIDTH=32\OPT_REGISTER_READS=1'0.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:230$2033'.
+No latch inferred for signal `$paramod\afifo\LGFIFO=2\WIDTH=32\OPT_REGISTER_READS=1'0.\o_rd_empty' from process `$paramod\afifo\LGFIFO=2\WIDTH=32\OPT_REGISTER_READS=1'0.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:227$2032'.
+No latch inferred for signal `$paramod\afifo\LGFIFO=2\WIDTH=32\OPT_REGISTER_READS=1'0.\lcl_read' from process `$paramod\afifo\LGFIFO=2\WIDTH=32\OPT_REGISTER_READS=1'0.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:224$2031'.
+No latch inferred for signal `$paramod\afifo\LGFIFO=2\WIDTH=32\OPT_REGISTER_READS=1'0.\lcl_rd_empty' from process `$paramod\afifo\LGFIFO=2\WIDTH=32\OPT_REGISTER_READS=1'0.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:201$2029'.
+No latch inferred for signal `$paramod\afifo\LGFIFO=2\WIDTH=32\OPT_REGISTER_READS=1'0.\o_wr_full' from process `$paramod\afifo\LGFIFO=2\WIDTH=32\OPT_REGISTER_READS=1'0.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:198$2026'.
+No latch inferred for signal `$paramod\afifo\LGFIFO=2\WIDTH=32\OPT_REGISTER_READS=1'0.\lcl_rd_data' from process `$paramod\afifo\LGFIFO=2\WIDTH=32\OPT_REGISTER_READS=1'0.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:159$2020'.
+No latch inferred for signal `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.\cpuregs_rs1' from process `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1382$4658'.
+No latch inferred for signal `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.\cpuregs_rs2' from process `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1382$4658'.
+No latch inferred for signal `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.\decoded_rs' from process `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1382$4658'.
+No latch inferred for signal `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.\cpuregs_write' from process `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1304$4644'.
+No latch inferred for signal `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.\cpuregs_wrdata' from process `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1304$4644'.
+No latch inferred for signal `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.\clear_prefetched_high_word' from process `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1290$4639'.
+No latch inferred for signal `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.\alu_out' from process `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1244$4616'.
+No latch inferred for signal `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.\alu_out_0' from process `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1244$4616'.
+No latch inferred for signal `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.\dbg_ascii_state' from process `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1181$4604'.
+No latch inferred for signal `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.\dbg_insn_opcode' from process `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:807$4342'.
+No latch inferred for signal `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.\dbg_ascii_instr' from process `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:807$4342'.
+No latch inferred for signal `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.\dbg_insn_imm' from process `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:807$4342'.
+No latch inferred for signal `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.\dbg_insn_rs1' from process `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:807$4342'.
+No latch inferred for signal `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.\dbg_insn_rs2' from process `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:807$4342'.
+No latch inferred for signal `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.\dbg_insn_rd' from process `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:807$4342'.
+No latch inferred for signal `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.\new_ascii_instr' from process `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:700$4337'.
+No latch inferred for signal `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.\alu_add_sub' from process `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1234$4852'.
+No latch inferred for signal `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.\alu_shl' from process `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1234$4852'.
+No latch inferred for signal `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.\alu_shr' from process `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1234$4852'.
+No latch inferred for signal `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.\alu_eq' from process `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1234$4852'.
+No latch inferred for signal `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.\alu_ltu' from process `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1234$4852'.
+No latch inferred for signal `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.\alu_lts' from process `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1234$4852'.
+No latch inferred for signal `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.\mem_la_wdata' from process `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:401$4272'.
+No latch inferred for signal `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.\mem_la_wstrb' from process `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:401$4272'.
+No latch inferred for signal `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.\mem_rdata_word' from process `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:401$4272'.
+No latch inferred for signal `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.\pcpi_int_wr' from process `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:325$4193'.
+No latch inferred for signal `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.\pcpi_int_rd' from process `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:325$4193'.
+No latch inferred for signal `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.\pcpi_int_wait' from process `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:325$4193'.
+No latch inferred for signal `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.\pcpi_int_ready' from process `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:325$4193'.
+No latch inferred for signal `\spimemio_xfer.\flash_io0_do' from process `\spimemio_xfer.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/spimemio.v:609$724'.
+No latch inferred for signal `\spimemio_xfer.\flash_io1_do' from process `\spimemio_xfer.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/spimemio.v:609$724'.
+No latch inferred for signal `\spimemio_xfer.\flash_io2_do' from process `\spimemio_xfer.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/spimemio.v:609$724'.
+No latch inferred for signal `\spimemio_xfer.\flash_io3_do' from process `\spimemio_xfer.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/spimemio.v:609$724'.
+No latch inferred for signal `\spimemio_xfer.\flash_io0_oe' from process `\spimemio_xfer.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/spimemio.v:609$724'.
+No latch inferred for signal `\spimemio_xfer.\flash_io1_oe' from process `\spimemio_xfer.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/spimemio.v:609$724'.
+No latch inferred for signal `\spimemio_xfer.\flash_io2_oe' from process `\spimemio_xfer.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/spimemio.v:609$724'.
+No latch inferred for signal `\spimemio_xfer.\flash_io3_oe' from process `\spimemio_xfer.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/spimemio.v:609$724'.
+No latch inferred for signal `\spimemio_xfer.\next_obuffer' from process `\spimemio_xfer.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/spimemio.v:609$724'.
+No latch inferred for signal `\spimemio_xfer.\next_ibuffer' from process `\spimemio_xfer.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/spimemio.v:609$724'.
+No latch inferred for signal `\spimemio_xfer.\next_count' from process `\spimemio_xfer.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/spimemio.v:609$724'.
+No latch inferred for signal `\spimemio_xfer.\next_fetch' from process `\spimemio_xfer.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/spimemio.v:609$724'.
+No latch inferred for signal `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.\cpuregs_rs1' from process `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1382$3975'.
+No latch inferred for signal `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.\cpuregs_rs2' from process `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1382$3975'.
+No latch inferred for signal `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.\decoded_rs' from process `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1382$3975'.
+No latch inferred for signal `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.\cpuregs_write' from process `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1304$3961'.
+No latch inferred for signal `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.\cpuregs_wrdata' from process `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1304$3961'.
+No latch inferred for signal `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.\clear_prefetched_high_word' from process `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1290$3956'.
+No latch inferred for signal `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.\alu_out' from process `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1244$3933'.
+No latch inferred for signal `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.\alu_out_0' from process `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1244$3933'.
+No latch inferred for signal `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.\dbg_ascii_state' from process `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1181$3921'.
+No latch inferred for signal `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.\dbg_insn_opcode' from process `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:807$3659'.
+No latch inferred for signal `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.\dbg_ascii_instr' from process `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:807$3659'.
+No latch inferred for signal `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.\dbg_insn_imm' from process `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:807$3659'.
+No latch inferred for signal `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.\dbg_insn_rs1' from process `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:807$3659'.
+No latch inferred for signal `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.\dbg_insn_rs2' from process `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:807$3659'.
+No latch inferred for signal `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.\dbg_insn_rd' from process `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:807$3659'.
+No latch inferred for signal `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.\new_ascii_instr' from process `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:700$3654'.
+No latch inferred for signal `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.\alu_add_sub' from process `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1234$4169'.
+No latch inferred for signal `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.\alu_shl' from process `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1234$4169'.
+No latch inferred for signal `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.\alu_shr' from process `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1234$4169'.
+No latch inferred for signal `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.\alu_eq' from process `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1234$4169'.
+No latch inferred for signal `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.\alu_ltu' from process `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1234$4169'.
+No latch inferred for signal `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.\alu_lts' from process `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1234$4169'.
+No latch inferred for signal `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.\mem_la_wdata' from process `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:401$3589'.
+No latch inferred for signal `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.\mem_la_wstrb' from process `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:401$3589'.
+No latch inferred for signal `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.\mem_rdata_word' from process `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:401$3589'.
+No latch inferred for signal `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.\pcpi_int_wr' from process `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:325$3510'.
+No latch inferred for signal `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.\pcpi_int_rd' from process `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:325$3510'.
+No latch inferred for signal `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.\pcpi_int_wait' from process `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:325$3510'.
+No latch inferred for signal `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.\pcpi_int_ready' from process `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:325$3510'.
+No latch inferred for signal `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.\cpuregs_rs1' from process `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1382$3292'.
+No latch inferred for signal `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.\cpuregs_rs2' from process `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1382$3292'.
+No latch inferred for signal `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.\decoded_rs' from process `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1382$3292'.
+No latch inferred for signal `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.\cpuregs_write' from process `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1304$3278'.
+No latch inferred for signal `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.\cpuregs_wrdata' from process `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1304$3278'.
+No latch inferred for signal `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.\clear_prefetched_high_word' from process `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1290$3273'.
+No latch inferred for signal `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.\alu_out' from process `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1244$3250'.
+No latch inferred for signal `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.\alu_out_0' from process `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1244$3250'.
+No latch inferred for signal `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.\dbg_ascii_state' from process `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1181$3238'.
+No latch inferred for signal `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.\dbg_insn_opcode' from process `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:807$2976'.
+No latch inferred for signal `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.\dbg_ascii_instr' from process `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:807$2976'.
+No latch inferred for signal `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.\dbg_insn_imm' from process `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:807$2976'.
+No latch inferred for signal `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.\dbg_insn_rs1' from process `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:807$2976'.
+No latch inferred for signal `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.\dbg_insn_rs2' from process `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:807$2976'.
+No latch inferred for signal `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.\dbg_insn_rd' from process `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:807$2976'.
+No latch inferred for signal `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.\new_ascii_instr' from process `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:700$2971'.
+No latch inferred for signal `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.\alu_add_sub' from process `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1234$3486'.
+No latch inferred for signal `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.\alu_shl' from process `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1234$3486'.
+No latch inferred for signal `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.\alu_shr' from process `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1234$3486'.
+No latch inferred for signal `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.\alu_eq' from process `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1234$3486'.
+No latch inferred for signal `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.\alu_ltu' from process `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1234$3486'.
+No latch inferred for signal `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.\alu_lts' from process `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1234$3486'.
+No latch inferred for signal `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.\mem_la_wdata' from process `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:401$2906'.
+No latch inferred for signal `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.\mem_la_wstrb' from process `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:401$2906'.
+No latch inferred for signal `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.\mem_rdata_word' from process `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:401$2906'.
+No latch inferred for signal `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.\pcpi_int_wr' from process `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:325$2827'.
+No latch inferred for signal `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.\pcpi_int_rd' from process `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:325$2827'.
+No latch inferred for signal `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.\pcpi_int_wait' from process `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:325$2827'.
+No latch inferred for signal `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.\pcpi_int_ready' from process `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:325$2827'.
+No latch inferred for signal `\softshell_top.\gpio_in[0]' from process `\softshell_top.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/softshell_top.v:0$22'.
+No latch inferred for signal `\softshell_top.\gpio_in[1]' from process `\softshell_top.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/softshell_top.v:0$22'.
+No latch inferred for signal `\softshell_top.\gpio_in[2]' from process `\softshell_top.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/softshell_top.v:0$22'.
+No latch inferred for signal `\softshell_top.\cpu_reset[0]' from process `\softshell_top.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/softshell_top.v:0$22'.
+No latch inferred for signal `\softshell_top.\cpu_reset[1]' from process `\softshell_top.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/softshell_top.v:0$22'.
+No latch inferred for signal `\softshell_top.\cpu_reset[2]' from process `\softshell_top.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/softshell_top.v:0$22'.
+
+23.2.8. Executing PROC_DFF pass (convert process syncs to FFs).
+Creating register for signal `$paramod$922eeecdf93ea4da89c0f9a13b613ec8c6a19ae5\arbiter.\grant_reg' using process `$paramod$922eeecdf93ea4da89c0f9a13b613ec8c6a19ae5\arbiter.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/verilog-wishbone/rtl/arbiter.v:139$2757'.
+ created $dff cell `$procdff$16278' with positive edge clock.
+Creating register for signal `$paramod$922eeecdf93ea4da89c0f9a13b613ec8c6a19ae5\arbiter.\grant_valid_reg' using process `$paramod$922eeecdf93ea4da89c0f9a13b613ec8c6a19ae5\arbiter.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/verilog-wishbone/rtl/arbiter.v:139$2757'.
+ created $dff cell `$procdff$16279' with positive edge clock.
+Creating register for signal `$paramod$922eeecdf93ea4da89c0f9a13b613ec8c6a19ae5\arbiter.\grant_encoded_reg' using process `$paramod$922eeecdf93ea4da89c0f9a13b613ec8c6a19ae5\arbiter.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/verilog-wishbone/rtl/arbiter.v:139$2757'.
+ created $dff cell `$procdff$16280' with positive edge clock.
+Creating register for signal `$paramod$922eeecdf93ea4da89c0f9a13b613ec8c6a19ae5\arbiter.\mask_reg' using process `$paramod$922eeecdf93ea4da89c0f9a13b613ec8c6a19ae5\arbiter.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/verilog-wishbone/rtl/arbiter.v:139$2757'.
+ created $dff cell `$procdff$16281' with positive edge clock.
+Creating register for signal `$paramod$02c0b2a9118806de1d82e68e563b733cce432378\picorv32_wb.\wbm_dat_o' using process `$paramod$02c0b2a9118806de1d82e68e563b733cce432378\picorv32_wb.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:2994$2744'.
+ created $dff cell `$procdff$16282' with positive edge clock.
+Creating register for signal `$paramod$02c0b2a9118806de1d82e68e563b733cce432378\picorv32_wb.\wbm_adr_o' using process `$paramod$02c0b2a9118806de1d82e68e563b733cce432378\picorv32_wb.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:2994$2744'.
+ created $dff cell `$procdff$16283' with positive edge clock.
+Creating register for signal `$paramod$02c0b2a9118806de1d82e68e563b733cce432378\picorv32_wb.\wbm_stb_o' using process `$paramod$02c0b2a9118806de1d82e68e563b733cce432378\picorv32_wb.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:2994$2744'.
+ created $dff cell `$procdff$16284' with positive edge clock.
+Creating register for signal `$paramod$02c0b2a9118806de1d82e68e563b733cce432378\picorv32_wb.\wbm_cyc_o' using process `$paramod$02c0b2a9118806de1d82e68e563b733cce432378\picorv32_wb.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:2994$2744'.
+ created $dff cell `$procdff$16285' with positive edge clock.
+Creating register for signal `$paramod$02c0b2a9118806de1d82e68e563b733cce432378\picorv32_wb.\wbm_we_o' using process `$paramod$02c0b2a9118806de1d82e68e563b733cce432378\picorv32_wb.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:2994$2744'.
+ created $dff cell `$procdff$16286' with positive edge clock.
+Creating register for signal `$paramod$02c0b2a9118806de1d82e68e563b733cce432378\picorv32_wb.\wbm_sel_o' using process `$paramod$02c0b2a9118806de1d82e68e563b733cce432378\picorv32_wb.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:2994$2744'.
+ created $dff cell `$procdff$16287' with positive edge clock.
+Creating register for signal `$paramod$02c0b2a9118806de1d82e68e563b733cce432378\picorv32_wb.\state' using process `$paramod$02c0b2a9118806de1d82e68e563b733cce432378\picorv32_wb.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:2994$2744'.
+ created $dff cell `$procdff$16288' with positive edge clock.
+Creating register for signal `$paramod$02c0b2a9118806de1d82e68e563b733cce432378\picorv32_wb.\mem_ready' using process `$paramod$02c0b2a9118806de1d82e68e563b733cce432378\picorv32_wb.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:2994$2744'.
+ created $dff cell `$procdff$16289' with positive edge clock.
+Creating register for signal `$paramod$02c0b2a9118806de1d82e68e563b733cce432378\picorv32_wb.\mem_rdata' using process `$paramod$02c0b2a9118806de1d82e68e563b733cce432378\picorv32_wb.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:2994$2744'.
+ created $dff cell `$procdff$16290' with positive edge clock.
+Creating register for signal `$paramod$e50444e694c9a9e823a24aefd7b9b454c7f28d7e\picorv32_wb.\wbm_dat_o' using process `$paramod$e50444e694c9a9e823a24aefd7b9b454c7f28d7e\picorv32_wb.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:2994$2739'.
+ created $dff cell `$procdff$16291' with positive edge clock.
+Creating register for signal `$paramod$e50444e694c9a9e823a24aefd7b9b454c7f28d7e\picorv32_wb.\wbm_adr_o' using process `$paramod$e50444e694c9a9e823a24aefd7b9b454c7f28d7e\picorv32_wb.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:2994$2739'.
+ created $dff cell `$procdff$16292' with positive edge clock.
+Creating register for signal `$paramod$e50444e694c9a9e823a24aefd7b9b454c7f28d7e\picorv32_wb.\wbm_stb_o' using process `$paramod$e50444e694c9a9e823a24aefd7b9b454c7f28d7e\picorv32_wb.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:2994$2739'.
+ created $dff cell `$procdff$16293' with positive edge clock.
+Creating register for signal `$paramod$e50444e694c9a9e823a24aefd7b9b454c7f28d7e\picorv32_wb.\wbm_cyc_o' using process `$paramod$e50444e694c9a9e823a24aefd7b9b454c7f28d7e\picorv32_wb.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:2994$2739'.
+ created $dff cell `$procdff$16294' with positive edge clock.
+Creating register for signal `$paramod$e50444e694c9a9e823a24aefd7b9b454c7f28d7e\picorv32_wb.\wbm_we_o' using process `$paramod$e50444e694c9a9e823a24aefd7b9b454c7f28d7e\picorv32_wb.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:2994$2739'.
+ created $dff cell `$procdff$16295' with positive edge clock.
+Creating register for signal `$paramod$e50444e694c9a9e823a24aefd7b9b454c7f28d7e\picorv32_wb.\wbm_sel_o' using process `$paramod$e50444e694c9a9e823a24aefd7b9b454c7f28d7e\picorv32_wb.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:2994$2739'.
+ created $dff cell `$procdff$16296' with positive edge clock.
+Creating register for signal `$paramod$e50444e694c9a9e823a24aefd7b9b454c7f28d7e\picorv32_wb.\state' using process `$paramod$e50444e694c9a9e823a24aefd7b9b454c7f28d7e\picorv32_wb.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:2994$2739'.
+ created $dff cell `$procdff$16297' with positive edge clock.
+Creating register for signal `$paramod$e50444e694c9a9e823a24aefd7b9b454c7f28d7e\picorv32_wb.\mem_ready' using process `$paramod$e50444e694c9a9e823a24aefd7b9b454c7f28d7e\picorv32_wb.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:2994$2739'.
+ created $dff cell `$procdff$16298' with positive edge clock.
+Creating register for signal `$paramod$e50444e694c9a9e823a24aefd7b9b454c7f28d7e\picorv32_wb.\mem_rdata' using process `$paramod$e50444e694c9a9e823a24aefd7b9b454c7f28d7e\picorv32_wb.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:2994$2739'.
+ created $dff cell `$procdff$16299' with positive edge clock.
+Creating register for signal `$paramod$d7c2e1f9a7f32b8e9c28fc8646c0275848e63526\picorv32_wb.\wbm_dat_o' using process `$paramod$d7c2e1f9a7f32b8e9c28fc8646c0275848e63526\picorv32_wb.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:2994$2734'.
+ created $dff cell `$procdff$16300' with positive edge clock.
+Creating register for signal `$paramod$d7c2e1f9a7f32b8e9c28fc8646c0275848e63526\picorv32_wb.\wbm_adr_o' using process `$paramod$d7c2e1f9a7f32b8e9c28fc8646c0275848e63526\picorv32_wb.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:2994$2734'.
+ created $dff cell `$procdff$16301' with positive edge clock.
+Creating register for signal `$paramod$d7c2e1f9a7f32b8e9c28fc8646c0275848e63526\picorv32_wb.\wbm_stb_o' using process `$paramod$d7c2e1f9a7f32b8e9c28fc8646c0275848e63526\picorv32_wb.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:2994$2734'.
+ created $dff cell `$procdff$16302' with positive edge clock.
+Creating register for signal `$paramod$d7c2e1f9a7f32b8e9c28fc8646c0275848e63526\picorv32_wb.\wbm_cyc_o' using process `$paramod$d7c2e1f9a7f32b8e9c28fc8646c0275848e63526\picorv32_wb.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:2994$2734'.
+ created $dff cell `$procdff$16303' with positive edge clock.
+Creating register for signal `$paramod$d7c2e1f9a7f32b8e9c28fc8646c0275848e63526\picorv32_wb.\wbm_we_o' using process `$paramod$d7c2e1f9a7f32b8e9c28fc8646c0275848e63526\picorv32_wb.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:2994$2734'.
+ created $dff cell `$procdff$16304' with positive edge clock.
+Creating register for signal `$paramod$d7c2e1f9a7f32b8e9c28fc8646c0275848e63526\picorv32_wb.\wbm_sel_o' using process `$paramod$d7c2e1f9a7f32b8e9c28fc8646c0275848e63526\picorv32_wb.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:2994$2734'.
+ created $dff cell `$procdff$16305' with positive edge clock.
+Creating register for signal `$paramod$d7c2e1f9a7f32b8e9c28fc8646c0275848e63526\picorv32_wb.\state' using process `$paramod$d7c2e1f9a7f32b8e9c28fc8646c0275848e63526\picorv32_wb.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:2994$2734'.
+ created $dff cell `$procdff$16306' with positive edge clock.
+Creating register for signal `$paramod$d7c2e1f9a7f32b8e9c28fc8646c0275848e63526\picorv32_wb.\mem_ready' using process `$paramod$d7c2e1f9a7f32b8e9c28fc8646c0275848e63526\picorv32_wb.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:2994$2734'.
+ created $dff cell `$procdff$16307' with positive edge clock.
+Creating register for signal `$paramod$d7c2e1f9a7f32b8e9c28fc8646c0275848e63526\picorv32_wb.\mem_rdata' using process `$paramod$d7c2e1f9a7f32b8e9c28fc8646c0275848e63526\picorv32_wb.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:2994$2734'.
+ created $dff cell `$procdff$16308' with positive edge clock.
+Creating register for signal `$paramod\mem_ff_wb\MEM_WORDS=32.\wb_ack_o' using process `$paramod\mem_ff_wb\MEM_WORDS=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:43$2721'.
+ created $dff cell `$procdff$16309' with positive edge clock.
+Creating register for signal `$paramod\mem_ff_wb\MEM_WORDS=32.\wb_ack_read' using process `$paramod\mem_ff_wb\MEM_WORDS=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:43$2721'.
+ created $dff cell `$procdff$16310' with positive edge clock.
+Creating register for signal `$paramod$b48b6478f53991418334d339eb44ca404341ca26\gpio.\gpio_out' using process `$paramod$b48b6478f53991418334d339eb44ca404341ca26\gpio.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/gpio32_wb.v:102$2710'.
+ created $dff cell `$procdff$16311' with positive edge clock.
+Creating register for signal `$paramod$b48b6478f53991418334d339eb44ca404341ca26\gpio.\gpio_oeb' using process `$paramod$b48b6478f53991418334d339eb44ca404341ca26\gpio.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/gpio32_wb.v:102$2710'.
+ created $dff cell `$procdff$16312' with positive edge clock.
+Creating register for signal `$paramod$b48b6478f53991418334d339eb44ca404341ca26\gpio.\iomem_rdata' using process `$paramod$b48b6478f53991418334d339eb44ca404341ca26\gpio.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/gpio32_wb.v:102$2710'.
+ created $dff cell `$procdff$16313' with positive edge clock.
+Creating register for signal `$paramod$b48b6478f53991418334d339eb44ca404341ca26\gpio.\iomem_ready' using process `$paramod$b48b6478f53991418334d339eb44ca404341ca26\gpio.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/gpio32_wb.v:102$2710'.
+ created $dff cell `$procdff$16314' with positive edge clock.
+Creating register for signal `$paramod$b48b6478f53991418334d339eb44ca404341ca26\gpio.\gpio_pu' using process `$paramod$b48b6478f53991418334d339eb44ca404341ca26\gpio.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/gpio32_wb.v:102$2710'.
+ created $dff cell `$procdff$16315' with positive edge clock.
+Creating register for signal `$paramod$b48b6478f53991418334d339eb44ca404341ca26\gpio.\gpio_pd' using process `$paramod$b48b6478f53991418334d339eb44ca404341ca26\gpio.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/gpio32_wb.v:102$2710'.
+ created $dff cell `$procdff$16316' with positive edge clock.
+Creating register for signal `$paramod\afifo\LGFIFO=2\WIDTH=32\OPT_REGISTER_READS=1'0.\rd_wgray' using process `$paramod\afifo\LGFIFO=2\WIDTH=32\OPT_REGISTER_READS=1'0.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:182$2024'.
+ created $adff cell `$procdff$16317' with positive edge clock and negative level reset.
+Creating register for signal `$paramod\afifo\LGFIFO=2\WIDTH=32\OPT_REGISTER_READS=1'0.\wgray_cross' using process `$paramod\afifo\LGFIFO=2\WIDTH=32\OPT_REGISTER_READS=1'0.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:182$2024'.
+ created $adff cell `$procdff$16318' with positive edge clock and negative level reset.
+Creating register for signal `$paramod\afifo\LGFIFO=2\WIDTH=32\OPT_REGISTER_READS=1'0.\wr_rgray' using process `$paramod\afifo\LGFIFO=2\WIDTH=32\OPT_REGISTER_READS=1'0.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:173$2022'.
+ created $adff cell `$procdff$16319' with positive edge clock and negative level reset.
+Creating register for signal `$paramod\afifo\LGFIFO=2\WIDTH=32\OPT_REGISTER_READS=1'0.\rgray_cross' using process `$paramod\afifo\LGFIFO=2\WIDTH=32\OPT_REGISTER_READS=1'0.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:173$2022'.
+ created $adff cell `$procdff$16320' with positive edge clock and negative level reset.
+Creating register for signal `$paramod\afifo\LGFIFO=2\WIDTH=32\OPT_REGISTER_READS=1'0.\rd_addr' using process `$paramod\afifo\LGFIFO=2\WIDTH=32\OPT_REGISTER_READS=1'0.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:145$2014'.
+ created $adff cell `$procdff$16321' with positive edge clock and negative level reset.
+Creating register for signal `$paramod\afifo\LGFIFO=2\WIDTH=32\OPT_REGISTER_READS=1'0.\rgray' using process `$paramod\afifo\LGFIFO=2\WIDTH=32\OPT_REGISTER_READS=1'0.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:145$2014'.
+ created $adff cell `$procdff$16322' with positive edge clock and negative level reset.
+Creating register for signal `$paramod\afifo\LGFIFO=2\WIDTH=32\OPT_REGISTER_READS=1'0.$memwr$\mem$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:139$1999_ADDR' using process `$paramod\afifo\LGFIFO=2\WIDTH=32\OPT_REGISTER_READS=1'0.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:137$2007'.
+ created $dff cell `$procdff$16323' with positive edge clock.
+Creating register for signal `$paramod\afifo\LGFIFO=2\WIDTH=32\OPT_REGISTER_READS=1'0.$memwr$\mem$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:139$1999_DATA' using process `$paramod\afifo\LGFIFO=2\WIDTH=32\OPT_REGISTER_READS=1'0.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:137$2007'.
+ created $dff cell `$procdff$16324' with positive edge clock.
+Creating register for signal `$paramod\afifo\LGFIFO=2\WIDTH=32\OPT_REGISTER_READS=1'0.$memwr$\mem$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:139$1999_EN' using process `$paramod\afifo\LGFIFO=2\WIDTH=32\OPT_REGISTER_READS=1'0.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:137$2007'.
+ created $dff cell `$procdff$16325' with positive edge clock.
+Creating register for signal `$paramod\afifo\LGFIFO=2\WIDTH=32\OPT_REGISTER_READS=1'0.\wr_addr' using process `$paramod\afifo\LGFIFO=2\WIDTH=32\OPT_REGISTER_READS=1'0.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:123$2001'.
+ created $adff cell `$procdff$16326' with positive edge clock and negative level reset.
+Creating register for signal `$paramod\afifo\LGFIFO=2\WIDTH=32\OPT_REGISTER_READS=1'0.\wgray' using process `$paramod\afifo\LGFIFO=2\WIDTH=32\OPT_REGISTER_READS=1'0.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:123$2001'.
+ created $adff cell `$procdff$16327' with positive edge clock and negative level reset.
+Creating register for signal `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.\pcpi_valid' using process `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1397$4672'.
+ created $dff cell `$procdff$16328' with positive edge clock.
+Creating register for signal `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.\trap' using process `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1397$4672'.
+ created $dff cell `$procdff$16329' with positive edge clock.
+Creating register for signal `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.\eoi' using process `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1397$4672'.
+ created $dff cell `$procdff$16330' with positive edge clock.
+Creating register for signal `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.\trace_valid' using process `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1397$4672'.
+ created $dff cell `$procdff$16331' with positive edge clock.
+Creating register for signal `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.\trace_data' using process `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1397$4672'.
+ created $dff cell `$procdff$16332' with positive edge clock.
+Creating register for signal `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.\count_cycle' using process `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1397$4672'.
+ created $dff cell `$procdff$16333' with positive edge clock.
+Creating register for signal `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.\count_instr' using process `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1397$4672'.
+ created $dff cell `$procdff$16334' with positive edge clock.
+Creating register for signal `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.\reg_pc' using process `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1397$4672'.
+ created $dff cell `$procdff$16335' with positive edge clock.
+Creating register for signal `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.\reg_next_pc' using process `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1397$4672'.
+ created $dff cell `$procdff$16336' with positive edge clock.
+Creating register for signal `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.\reg_op1' using process `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1397$4672'.
+ created $dff cell `$procdff$16337' with positive edge clock.
+Creating register for signal `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.\reg_op2' using process `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1397$4672'.
+ created $dff cell `$procdff$16338' with positive edge clock.
+Creating register for signal `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.\reg_out' using process `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1397$4672'.
+ created $dff cell `$procdff$16339' with positive edge clock.
+Creating register for signal `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.\reg_sh' using process `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1397$4672'.
+ created $dff cell `$procdff$16340' with positive edge clock.
+Creating register for signal `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.\irq_delay' using process `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1397$4672'.
+ created $dff cell `$procdff$16341' with positive edge clock.
+Creating register for signal `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.\irq_active' using process `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1397$4672'.
+ created $dff cell `$procdff$16342' with positive edge clock.
+Creating register for signal `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.\irq_mask' using process `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1397$4672'.
+ created $dff cell `$procdff$16343' with positive edge clock.
+Creating register for signal `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.\irq_pending' using process `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1397$4672'.
+ created $dff cell `$procdff$16344' with positive edge clock.
+Creating register for signal `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.\timer' using process `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1397$4672'.
+ created $dff cell `$procdff$16345' with positive edge clock.
+Creating register for signal `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.\mem_wordsize' using process `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1397$4672'.
+ created $dff cell `$procdff$16346' with positive edge clock.
+Creating register for signal `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.\mem_do_prefetch' using process `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1397$4672'.
+ created $dff cell `$procdff$16347' with positive edge clock.
+Creating register for signal `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.\mem_do_rinst' using process `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1397$4672'.
+ created $dff cell `$procdff$16348' with positive edge clock.
+Creating register for signal `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.\mem_do_rdata' using process `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1397$4672'.
+ created $dff cell `$procdff$16349' with positive edge clock.
+Creating register for signal `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.\mem_do_wdata' using process `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1397$4672'.
+ created $dff cell `$procdff$16350' with positive edge clock.
+Creating register for signal `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.\decoder_trigger' using process `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1397$4672'.
+ created $dff cell `$procdff$16351' with positive edge clock.
+Creating register for signal `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.\decoder_trigger_q' using process `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1397$4672'.
+ created $dff cell `$procdff$16352' with positive edge clock.
+Creating register for signal `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.\decoder_pseudo_trigger' using process `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1397$4672'.
+ created $dff cell `$procdff$16353' with positive edge clock.
+Creating register for signal `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.\decoder_pseudo_trigger_q' using process `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1397$4672'.
+ created $dff cell `$procdff$16354' with positive edge clock.
+Creating register for signal `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.\dbg_rs1val' using process `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1397$4672'.
+ created $dff cell `$procdff$16355' with positive edge clock.
+Creating register for signal `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.\dbg_rs2val' using process `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1397$4672'.
+ created $dff cell `$procdff$16356' with positive edge clock.
+Creating register for signal `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.\dbg_rs1val_valid' using process `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1397$4672'.
+ created $dff cell `$procdff$16357' with positive edge clock.
+Creating register for signal `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.\dbg_rs2val_valid' using process `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1397$4672'.
+ created $dff cell `$procdff$16358' with positive edge clock.
+Creating register for signal `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.\cpu_state' using process `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1397$4672'.
+ created $dff cell `$procdff$16359' with positive edge clock.
+Creating register for signal `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.\irq_state' using process `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1397$4672'.
+ created $dff cell `$procdff$16360' with positive edge clock.
+Creating register for signal `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.\set_mem_do_rinst' using process `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1397$4672'.
+ created $dff cell `$procdff$16361' with positive edge clock.
+Creating register for signal `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.\set_mem_do_rdata' using process `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1397$4672'.
+ created $dff cell `$procdff$16362' with positive edge clock.
+Creating register for signal `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.\set_mem_do_wdata' using process `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1397$4672'.
+ created $dff cell `$procdff$16363' with positive edge clock.
+Creating register for signal `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.\latched_store' using process `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1397$4672'.
+ created $dff cell `$procdff$16364' with positive edge clock.
+Creating register for signal `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.\latched_stalu' using process `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1397$4672'.
+ created $dff cell `$procdff$16365' with positive edge clock.
+Creating register for signal `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.\latched_branch' using process `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1397$4672'.
+ created $dff cell `$procdff$16366' with positive edge clock.
+Creating register for signal `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.\latched_compr' using process `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1397$4672'.
+ created $dff cell `$procdff$16367' with positive edge clock.
+Creating register for signal `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.\latched_trace' using process `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1397$4672'.
+ created $dff cell `$procdff$16368' with positive edge clock.
+Creating register for signal `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.\latched_is_lu' using process `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1397$4672'.
+ created $dff cell `$procdff$16369' with positive edge clock.
+Creating register for signal `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.\latched_is_lh' using process `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1397$4672'.
+ created $dff cell `$procdff$16370' with positive edge clock.
+Creating register for signal `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.\latched_is_lb' using process `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1397$4672'.
+ created $dff cell `$procdff$16371' with positive edge clock.
+Creating register for signal `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.\latched_rd' using process `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1397$4672'.
+ created $dff cell `$procdff$16372' with positive edge clock.
+Creating register for signal `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.\current_pc' using process `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1397$4672'.
+ created $dff cell `$procdff$16373' with positive edge clock.
+Creating register for signal `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.\pcpi_timeout_counter' using process `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1397$4672'.
+ created $dff cell `$procdff$16374' with positive edge clock.
+Creating register for signal `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.\pcpi_timeout' using process `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1397$4672'.
+ created $dff cell `$procdff$16375' with positive edge clock.
+Creating register for signal `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.\next_irq_pending' using process `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1397$4672'.
+ created $dff cell `$procdff$16376' with positive edge clock.
+Creating register for signal `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.\do_waitirq' using process `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1397$4672'.
+ created $dff cell `$procdff$16377' with positive edge clock.
+Creating register for signal `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.\alu_out_q' using process `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1397$4672'.
+ created $dff cell `$procdff$16378' with positive edge clock.
+Creating register for signal `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.\alu_out_0_q' using process `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1397$4672'.
+ created $dff cell `$procdff$16379' with positive edge clock.
+Creating register for signal `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.\alu_wait' using process `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1397$4672'.
+ created $dff cell `$procdff$16380' with positive edge clock.
+Creating register for signal `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.\alu_wait_2' using process `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1397$4672'.
+ created $dff cell `$procdff$16381' with positive edge clock.
+Creating register for signal `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.\clear_prefetched_high_word_q' using process `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1288$4638'.
+ created $dff cell `$procdff$16382' with positive edge clock.
+Creating register for signal `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.\pcpi_insn' using process `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$4344'.
+ created $dff cell `$procdff$16383' with positive edge clock.
+Creating register for signal `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.\instr_lui' using process `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$4344'.
+ created $dff cell `$procdff$16384' with positive edge clock.
+Creating register for signal `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.\instr_auipc' using process `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$4344'.
+ created $dff cell `$procdff$16385' with positive edge clock.
+Creating register for signal `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.\instr_jal' using process `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$4344'.
+ created $dff cell `$procdff$16386' with positive edge clock.
+Creating register for signal `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.\instr_jalr' using process `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$4344'.
+ created $dff cell `$procdff$16387' with positive edge clock.
+Creating register for signal `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.\instr_beq' using process `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$4344'.
+ created $dff cell `$procdff$16388' with positive edge clock.
+Creating register for signal `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.\instr_bne' using process `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$4344'.
+ created $dff cell `$procdff$16389' with positive edge clock.
+Creating register for signal `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.\instr_blt' using process `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$4344'.
+ created $dff cell `$procdff$16390' with positive edge clock.
+Creating register for signal `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.\instr_bge' using process `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$4344'.
+ created $dff cell `$procdff$16391' with positive edge clock.
+Creating register for signal `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.\instr_bltu' using process `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$4344'.
+ created $dff cell `$procdff$16392' with positive edge clock.
+Creating register for signal `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.\instr_bgeu' using process `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$4344'.
+ created $dff cell `$procdff$16393' with positive edge clock.
+Creating register for signal `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.\instr_lb' using process `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$4344'.
+ created $dff cell `$procdff$16394' with positive edge clock.
+Creating register for signal `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.\instr_lh' using process `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$4344'.
+ created $dff cell `$procdff$16395' with positive edge clock.
+Creating register for signal `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.\instr_lw' using process `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$4344'.
+ created $dff cell `$procdff$16396' with positive edge clock.
+Creating register for signal `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.\instr_lbu' using process `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$4344'.
+ created $dff cell `$procdff$16397' with positive edge clock.
+Creating register for signal `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.\instr_lhu' using process `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$4344'.
+ created $dff cell `$procdff$16398' with positive edge clock.
+Creating register for signal `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.\instr_sb' using process `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$4344'.
+ created $dff cell `$procdff$16399' with positive edge clock.
+Creating register for signal `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.\instr_sh' using process `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$4344'.
+ created $dff cell `$procdff$16400' with positive edge clock.
+Creating register for signal `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.\instr_sw' using process `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$4344'.
+ created $dff cell `$procdff$16401' with positive edge clock.
+Creating register for signal `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.\instr_addi' using process `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$4344'.
+ created $dff cell `$procdff$16402' with positive edge clock.
+Creating register for signal `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.\instr_slti' using process `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$4344'.
+ created $dff cell `$procdff$16403' with positive edge clock.
+Creating register for signal `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.\instr_sltiu' using process `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$4344'.
+ created $dff cell `$procdff$16404' with positive edge clock.
+Creating register for signal `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.\instr_xori' using process `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$4344'.
+ created $dff cell `$procdff$16405' with positive edge clock.
+Creating register for signal `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.\instr_ori' using process `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$4344'.
+ created $dff cell `$procdff$16406' with positive edge clock.
+Creating register for signal `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.\instr_andi' using process `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$4344'.
+ created $dff cell `$procdff$16407' with positive edge clock.
+Creating register for signal `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.\instr_slli' using process `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$4344'.
+ created $dff cell `$procdff$16408' with positive edge clock.
+Creating register for signal `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.\instr_srli' using process `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$4344'.
+ created $dff cell `$procdff$16409' with positive edge clock.
+Creating register for signal `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.\instr_srai' using process `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$4344'.
+ created $dff cell `$procdff$16410' with positive edge clock.
+Creating register for signal `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.\instr_add' using process `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$4344'.
+ created $dff cell `$procdff$16411' with positive edge clock.
+Creating register for signal `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.\instr_sub' using process `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$4344'.
+ created $dff cell `$procdff$16412' with positive edge clock.
+Creating register for signal `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.\instr_sll' using process `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$4344'.
+ created $dff cell `$procdff$16413' with positive edge clock.
+Creating register for signal `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.\instr_slt' using process `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$4344'.
+ created $dff cell `$procdff$16414' with positive edge clock.
+Creating register for signal `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.\instr_sltu' using process `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$4344'.
+ created $dff cell `$procdff$16415' with positive edge clock.
+Creating register for signal `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.\instr_xor' using process `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$4344'.
+ created $dff cell `$procdff$16416' with positive edge clock.
+Creating register for signal `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.\instr_srl' using process `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$4344'.
+ created $dff cell `$procdff$16417' with positive edge clock.
+Creating register for signal `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.\instr_sra' using process `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$4344'.
+ created $dff cell `$procdff$16418' with positive edge clock.
+Creating register for signal `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.\instr_or' using process `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$4344'.
+ created $dff cell `$procdff$16419' with positive edge clock.
+Creating register for signal `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.\instr_and' using process `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$4344'.
+ created $dff cell `$procdff$16420' with positive edge clock.
+Creating register for signal `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.\instr_rdcycle' using process `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$4344'.
+ created $dff cell `$procdff$16421' with positive edge clock.
+Creating register for signal `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.\instr_rdcycleh' using process `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$4344'.
+ created $dff cell `$procdff$16422' with positive edge clock.
+Creating register for signal `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.\instr_rdinstr' using process `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$4344'.
+ created $dff cell `$procdff$16423' with positive edge clock.
+Creating register for signal `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.\instr_rdinstrh' using process `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$4344'.
+ created $dff cell `$procdff$16424' with positive edge clock.
+Creating register for signal `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.\instr_ecall_ebreak' using process `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$4344'.
+ created $dff cell `$procdff$16425' with positive edge clock.
+Creating register for signal `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.\instr_getq' using process `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$4344'.
+ created $dff cell `$procdff$16426' with positive edge clock.
+Creating register for signal `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.\instr_setq' using process `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$4344'.
+ created $dff cell `$procdff$16427' with positive edge clock.
+Creating register for signal `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.\instr_retirq' using process `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$4344'.
+ created $dff cell `$procdff$16428' with positive edge clock.
+Creating register for signal `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.\instr_maskirq' using process `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$4344'.
+ created $dff cell `$procdff$16429' with positive edge clock.
+Creating register for signal `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.\instr_waitirq' using process `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$4344'.
+ created $dff cell `$procdff$16430' with positive edge clock.
+Creating register for signal `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.\instr_timer' using process `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$4344'.
+ created $dff cell `$procdff$16431' with positive edge clock.
+Creating register for signal `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.\decoded_rd' using process `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$4344'.
+ created $dff cell `$procdff$16432' with positive edge clock.
+Creating register for signal `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.\decoded_rs1' using process `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$4344'.
+ created $dff cell `$procdff$16433' with positive edge clock.
+Creating register for signal `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.\decoded_rs2' using process `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$4344'.
+ created $dff cell `$procdff$16434' with positive edge clock.
+Creating register for signal `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.\decoded_imm' using process `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$4344'.
+ created $dff cell `$procdff$16435' with positive edge clock.
+Creating register for signal `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.\decoded_imm_j' using process `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$4344'.
+ created $dff cell `$procdff$16436' with positive edge clock.
+Creating register for signal `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.\compressed_instr' using process `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$4344'.
+ created $dff cell `$procdff$16437' with positive edge clock.
+Creating register for signal `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.\is_lui_auipc_jal' using process `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$4344'.
+ created $dff cell `$procdff$16438' with positive edge clock.
+Creating register for signal `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.\is_lb_lh_lw_lbu_lhu' using process `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$4344'.
+ created $dff cell `$procdff$16439' with positive edge clock.
+Creating register for signal `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.\is_slli_srli_srai' using process `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$4344'.
+ created $dff cell `$procdff$16440' with positive edge clock.
+Creating register for signal `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.\is_jalr_addi_slti_sltiu_xori_ori_andi' using process `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$4344'.
+ created $dff cell `$procdff$16441' with positive edge clock.
+Creating register for signal `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.\is_sb_sh_sw' using process `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$4344'.
+ created $dff cell `$procdff$16442' with positive edge clock.
+Creating register for signal `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.\is_sll_srl_sra' using process `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$4344'.
+ created $dff cell `$procdff$16443' with positive edge clock.
+Creating register for signal `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.\is_lui_auipc_jal_jalr_addi_add_sub' using process `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$4344'.
+ created $dff cell `$procdff$16444' with positive edge clock.
+Creating register for signal `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.\is_slti_blt_slt' using process `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$4344'.
+ created $dff cell `$procdff$16445' with positive edge clock.
+Creating register for signal `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.\is_sltiu_bltu_sltu' using process `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$4344'.
+ created $dff cell `$procdff$16446' with positive edge clock.
+Creating register for signal `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.\is_beq_bne_blt_bge_bltu_bgeu' using process `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$4344'.
+ created $dff cell `$procdff$16447' with positive edge clock.
+Creating register for signal `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.\is_lbu_lhu_lw' using process `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$4344'.
+ created $dff cell `$procdff$16448' with positive edge clock.
+Creating register for signal `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.\is_alu_reg_imm' using process `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$4344'.
+ created $dff cell `$procdff$16449' with positive edge clock.
+Creating register for signal `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.\is_alu_reg_reg' using process `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$4344'.
+ created $dff cell `$procdff$16450' with positive edge clock.
+Creating register for signal `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.\is_compare' using process `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$4344'.
+ created $dff cell `$procdff$16451' with positive edge clock.
+Creating register for signal `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.\dbg_insn_addr' using process `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:776$4338'.
+ created $dff cell `$procdff$16452' with positive edge clock.
+Creating register for signal `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.\q_ascii_instr' using process `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:776$4338'.
+ created $dff cell `$procdff$16453' with positive edge clock.
+Creating register for signal `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.\q_insn_imm' using process `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:776$4338'.
+ created $dff cell `$procdff$16454' with positive edge clock.
+Creating register for signal `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.\q_insn_opcode' using process `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:776$4338'.
+ created $dff cell `$procdff$16455' with positive edge clock.
+Creating register for signal `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.\q_insn_rs1' using process `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:776$4338'.
+ created $dff cell `$procdff$16456' with positive edge clock.
+Creating register for signal `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.\q_insn_rs2' using process `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:776$4338'.
+ created $dff cell `$procdff$16457' with positive edge clock.
+Creating register for signal `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.\q_insn_rd' using process `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:776$4338'.
+ created $dff cell `$procdff$16458' with positive edge clock.
+Creating register for signal `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.\dbg_next' using process `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:776$4338'.
+ created $dff cell `$procdff$16459' with positive edge clock.
+Creating register for signal `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.\dbg_valid_insn' using process `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:776$4338'.
+ created $dff cell `$procdff$16460' with positive edge clock.
+Creating register for signal `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.\cached_ascii_instr' using process `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:776$4338'.
+ created $dff cell `$procdff$16461' with positive edge clock.
+Creating register for signal `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.\cached_insn_imm' using process `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:776$4338'.
+ created $dff cell `$procdff$16462' with positive edge clock.
+Creating register for signal `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.\cached_insn_opcode' using process `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:776$4338'.
+ created $dff cell `$procdff$16463' with positive edge clock.
+Creating register for signal `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.\cached_insn_rs1' using process `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:776$4338'.
+ created $dff cell `$procdff$16464' with positive edge clock.
+Creating register for signal `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.\cached_insn_rs2' using process `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:776$4338'.
+ created $dff cell `$procdff$16465' with positive edge clock.
+Creating register for signal `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.\cached_insn_rd' using process `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:776$4338'.
+ created $dff cell `$procdff$16466' with positive edge clock.
+Creating register for signal `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.\mem_instr' using process `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:565$4313'.
+ created $dff cell `$procdff$16467' with positive edge clock.
+Creating register for signal `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.\mem_wdata' using process `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:565$4313'.
+ created $dff cell `$procdff$16468' with positive edge clock.
+Creating register for signal `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.\mem_addr' using process `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:565$4313'.
+ created $dff cell `$procdff$16469' with positive edge clock.
+Creating register for signal `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.\mem_valid' using process `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:565$4313'.
+ created $dff cell `$procdff$16470' with positive edge clock.
+Creating register for signal `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.\mem_wstrb' using process `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:565$4313'.
+ created $dff cell `$procdff$16471' with positive edge clock.
+Creating register for signal `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.\mem_state' using process `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:565$4313'.
+ created $dff cell `$procdff$16472' with positive edge clock.
+Creating register for signal `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.\mem_la_secondword' using process `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:565$4313'.
+ created $dff cell `$procdff$16473' with positive edge clock.
+Creating register for signal `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.\prefetched_high_word' using process `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:565$4313'.
+ created $dff cell `$procdff$16474' with positive edge clock.
+Creating register for signal `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.\mem_16bit_buffer' using process `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:565$4313'.
+ created $dff cell `$procdff$16475' with positive edge clock.
+Creating register for signal `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.\next_insn_opcode' using process `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:430$4275'.
+ created $dff cell `$procdff$16476' with positive edge clock.
+Creating register for signal `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.\mem_rdata_q' using process `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:430$4275'.
+ created $dff cell `$procdff$16477' with positive edge clock.
+Creating register for signal `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.\mem_la_firstword_reg' using process `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:390$4267'.
+ created $dff cell `$procdff$16478' with positive edge clock.
+Creating register for signal `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.\last_mem_valid' using process `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:390$4267'.
+ created $dff cell `$procdff$16479' with positive edge clock.
+Creating register for signal `\spimemio_xfer.\flash_csb' using process `\spimemio_xfer.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/spimemio.v:697$748'.
+ created $dff cell `$procdff$16480' with positive edge clock.
+Creating register for signal `\spimemio_xfer.\flash_clk' using process `\spimemio_xfer.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/spimemio.v:697$748'.
+ created $dff cell `$procdff$16481' with positive edge clock.
+Creating register for signal `\spimemio_xfer.\xfer_dspi' using process `\spimemio_xfer.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/spimemio.v:697$748'.
+ created $dff cell `$procdff$16482' with positive edge clock.
+Creating register for signal `\spimemio_xfer.\xfer_ddr' using process `\spimemio_xfer.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/spimemio.v:697$748'.
+ created $dff cell `$procdff$16483' with positive edge clock.
+Creating register for signal `\spimemio_xfer.\obuffer' using process `\spimemio_xfer.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/spimemio.v:697$748'.
+ created $dff cell `$procdff$16484' with positive edge clock.
+Creating register for signal `\spimemio_xfer.\ibuffer' using process `\spimemio_xfer.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/spimemio.v:697$748'.
+ created $dff cell `$procdff$16485' with positive edge clock.
+Creating register for signal `\spimemio_xfer.\count' using process `\spimemio_xfer.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/spimemio.v:697$748'.
+ created $dff cell `$procdff$16486' with positive edge clock.
+Creating register for signal `\spimemio_xfer.\dummy_count' using process `\spimemio_xfer.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/spimemio.v:697$748'.
+ created $dff cell `$procdff$16487' with positive edge clock.
+Creating register for signal `\spimemio_xfer.\xfer_cont' using process `\spimemio_xfer.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/spimemio.v:697$748'.
+ created $dff cell `$procdff$16488' with positive edge clock.
+Creating register for signal `\spimemio_xfer.\xfer_qspi' using process `\spimemio_xfer.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/spimemio.v:697$748'.
+ created $dff cell `$procdff$16489' with positive edge clock.
+Creating register for signal `\spimemio_xfer.\xfer_rd' using process `\spimemio_xfer.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/spimemio.v:697$748'.
+ created $dff cell `$procdff$16490' with positive edge clock.
+Creating register for signal `\spimemio_xfer.\xfer_tag' using process `\spimemio_xfer.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/spimemio.v:697$748'.
+ created $dff cell `$procdff$16491' with positive edge clock.
+Creating register for signal `\spimemio_xfer.\fetch' using process `\spimemio_xfer.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/spimemio.v:697$748'.
+ created $dff cell `$procdff$16492' with positive edge clock.
+Creating register for signal `\spimemio_xfer.\last_fetch' using process `\spimemio_xfer.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/spimemio.v:697$748'.
+ created $dff cell `$procdff$16493' with positive edge clock.
+Creating register for signal `\spimemio_xfer.\xfer_ddr_q' using process `\spimemio_xfer.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/spimemio.v:598$715'.
+ created $dff cell `$procdff$16494' with positive edge clock.
+Creating register for signal `\spimemio_xfer.\xfer_tag_q' using process `\spimemio_xfer.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/spimemio.v:598$715'.
+ created $dff cell `$procdff$16495' with positive edge clock.
+Creating register for signal `\spimemio.\rdata' using process `\spimemio.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/spimemio.v:369$694'.
+ created $dff cell `$procdff$16496' with positive edge clock.
+Creating register for signal `\spimemio.\xfer_resetn' using process `\spimemio.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/spimemio.v:369$694'.
+ created $dff cell `$procdff$16497' with positive edge clock.
+Creating register for signal `\spimemio.\din_valid' using process `\spimemio.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/spimemio.v:369$694'.
+ created $dff cell `$procdff$16498' with positive edge clock.
+Creating register for signal `\spimemio.\din_data' using process `\spimemio.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/spimemio.v:369$694'.
+ created $dff cell `$procdff$16499' with positive edge clock.
+Creating register for signal `\spimemio.\din_tag' using process `\spimemio.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/spimemio.v:369$694'.
+ created $dff cell `$procdff$16500' with positive edge clock.
+Creating register for signal `\spimemio.\din_cont' using process `\spimemio.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/spimemio.v:369$694'.
+ created $dff cell `$procdff$16501' with positive edge clock.
+Creating register for signal `\spimemio.\din_qspi' using process `\spimemio.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/spimemio.v:369$694'.
+ created $dff cell `$procdff$16502' with positive edge clock.
+Creating register for signal `\spimemio.\din_ddr' using process `\spimemio.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/spimemio.v:369$694'.
+ created $dff cell `$procdff$16503' with positive edge clock.
+Creating register for signal `\spimemio.\din_rd' using process `\spimemio.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/spimemio.v:369$694'.
+ created $dff cell `$procdff$16504' with positive edge clock.
+Creating register for signal `\spimemio.\buffer' using process `\spimemio.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/spimemio.v:369$694'.
+ created $dff cell `$procdff$16505' with positive edge clock.
+Creating register for signal `\spimemio.\rd_addr' using process `\spimemio.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/spimemio.v:369$694'.
+ created $dff cell `$procdff$16506' with positive edge clock.
+Creating register for signal `\spimemio.\rd_valid' using process `\spimemio.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/spimemio.v:369$694'.
+ created $dff cell `$procdff$16507' with positive edge clock.
+Creating register for signal `\spimemio.\rd_wait' using process `\spimemio.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/spimemio.v:369$694'.
+ created $dff cell `$procdff$16508' with positive edge clock.
+Creating register for signal `\spimemio.\rd_inc' using process `\spimemio.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/spimemio.v:369$694'.
+ created $dff cell `$procdff$16509' with positive edge clock.
+Creating register for signal `\spimemio.\state' using process `\spimemio.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/spimemio.v:369$694'.
+ created $dff cell `$procdff$16510' with positive edge clock.
+Creating register for signal `\spimemio.\xfer_io0_90' using process `\spimemio.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/spimemio.v:295$630'.
+ created $dff cell `$procdff$16511' with negative edge clock.
+Creating register for signal `\spimemio.\xfer_io1_90' using process `\spimemio.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/spimemio.v:295$630'.
+ created $dff cell `$procdff$16512' with negative edge clock.
+Creating register for signal `\spimemio.\xfer_io2_90' using process `\spimemio.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/spimemio.v:295$630'.
+ created $dff cell `$procdff$16513' with negative edge clock.
+Creating register for signal `\spimemio.\xfer_io3_90' using process `\spimemio.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/spimemio.v:295$630'.
+ created $dff cell `$procdff$16514' with negative edge clock.
+Creating register for signal `\spimemio.\softreset' using process `\spimemio.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/spimemio.v:243$626'.
+ created $dff cell `$procdff$16515' with positive edge clock.
+Creating register for signal `\spimemio.\config_en' using process `\spimemio.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/spimemio.v:243$626'.
+ created $dff cell `$procdff$16516' with positive edge clock.
+Creating register for signal `\spimemio.\config_ddr' using process `\spimemio.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/spimemio.v:243$626'.
+ created $dff cell `$procdff$16517' with positive edge clock.
+Creating register for signal `\spimemio.\config_qspi' using process `\spimemio.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/spimemio.v:243$626'.
+ created $dff cell `$procdff$16518' with positive edge clock.
+Creating register for signal `\spimemio.\config_cont' using process `\spimemio.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/spimemio.v:243$626'.
+ created $dff cell `$procdff$16519' with positive edge clock.
+Creating register for signal `\spimemio.\config_dummy' using process `\spimemio.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/spimemio.v:243$626'.
+ created $dff cell `$procdff$16520' with positive edge clock.
+Creating register for signal `\spimemio.\config_oe' using process `\spimemio.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/spimemio.v:243$626'.
+ created $dff cell `$procdff$16521' with positive edge clock.
+Creating register for signal `\spimemio.\config_csb' using process `\spimemio.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/spimemio.v:243$626'.
+ created $dff cell `$procdff$16522' with positive edge clock.
+Creating register for signal `\spimemio.\config_clk' using process `\spimemio.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/spimemio.v:243$626'.
+ created $dff cell `$procdff$16523' with positive edge clock.
+Creating register for signal `\spimemio.\config_do' using process `\spimemio.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/spimemio.v:243$626'.
+ created $dff cell `$procdff$16524' with positive edge clock.
+Creating register for signal `\simpleuart.\send_pattern' using process `\simpleuart.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/simpleuart.v:194$597'.
+ created $dff cell `$procdff$16525' with positive edge clock.
+Creating register for signal `\simpleuart.\send_bitcnt' using process `\simpleuart.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/simpleuart.v:194$597'.
+ created $dff cell `$procdff$16526' with positive edge clock.
+Creating register for signal `\simpleuart.\send_divcnt' using process `\simpleuart.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/simpleuart.v:194$597'.
+ created $dff cell `$procdff$16527' with positive edge clock.
+Creating register for signal `\simpleuart.\send_dummy' using process `\simpleuart.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/simpleuart.v:194$597'.
+ created $dff cell `$procdff$16528' with positive edge clock.
+Creating register for signal `\simpleuart.\recv_state' using process `\simpleuart.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/simpleuart.v:151$587'.
+ created $dff cell `$procdff$16529' with positive edge clock.
+Creating register for signal `\simpleuart.\recv_divcnt' using process `\simpleuart.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/simpleuart.v:151$587'.
+ created $dff cell `$procdff$16530' with positive edge clock.
+Creating register for signal `\simpleuart.\recv_pattern' using process `\simpleuart.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/simpleuart.v:151$587'.
+ created $dff cell `$procdff$16531' with positive edge clock.
+Creating register for signal `\simpleuart.\recv_buf_data' using process `\simpleuart.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/simpleuart.v:151$587'.
+ created $dff cell `$procdff$16532' with positive edge clock.
+Creating register for signal `\simpleuart.\recv_buf_valid' using process `\simpleuart.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/simpleuart.v:151$587'.
+ created $dff cell `$procdff$16533' with positive edge clock.
+Creating register for signal `\simpleuart.\enabled' using process `\simpleuart.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/simpleuart.v:138$585'.
+ created $dff cell `$procdff$16534' with positive edge clock.
+Creating register for signal `\simpleuart.\cfg_divider' using process `\simpleuart.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/simpleuart.v:138$585'.
+ created $dff cell `$procdff$16535' with positive edge clock.
+Creating register for signal `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.\pcpi_valid' using process `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1397$3989'.
+ created $dff cell `$procdff$16536' with positive edge clock.
+Creating register for signal `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.\trap' using process `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1397$3989'.
+ created $dff cell `$procdff$16537' with positive edge clock.
+Creating register for signal `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.\eoi' using process `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1397$3989'.
+ created $dff cell `$procdff$16538' with positive edge clock.
+Creating register for signal `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.\trace_valid' using process `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1397$3989'.
+ created $dff cell `$procdff$16539' with positive edge clock.
+Creating register for signal `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.\trace_data' using process `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1397$3989'.
+ created $dff cell `$procdff$16540' with positive edge clock.
+Creating register for signal `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.\count_cycle' using process `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1397$3989'.
+ created $dff cell `$procdff$16541' with positive edge clock.
+Creating register for signal `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.\count_instr' using process `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1397$3989'.
+ created $dff cell `$procdff$16542' with positive edge clock.
+Creating register for signal `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.\reg_pc' using process `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1397$3989'.
+ created $dff cell `$procdff$16543' with positive edge clock.
+Creating register for signal `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.\reg_next_pc' using process `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1397$3989'.
+ created $dff cell `$procdff$16544' with positive edge clock.
+Creating register for signal `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.\reg_op1' using process `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1397$3989'.
+ created $dff cell `$procdff$16545' with positive edge clock.
+Creating register for signal `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.\reg_op2' using process `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1397$3989'.
+ created $dff cell `$procdff$16546' with positive edge clock.
+Creating register for signal `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.\reg_out' using process `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1397$3989'.
+ created $dff cell `$procdff$16547' with positive edge clock.
+Creating register for signal `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.\reg_sh' using process `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1397$3989'.
+ created $dff cell `$procdff$16548' with positive edge clock.
+Creating register for signal `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.\irq_delay' using process `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1397$3989'.
+ created $dff cell `$procdff$16549' with positive edge clock.
+Creating register for signal `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.\irq_active' using process `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1397$3989'.
+ created $dff cell `$procdff$16550' with positive edge clock.
+Creating register for signal `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.\irq_mask' using process `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1397$3989'.
+ created $dff cell `$procdff$16551' with positive edge clock.
+Creating register for signal `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.\irq_pending' using process `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1397$3989'.
+ created $dff cell `$procdff$16552' with positive edge clock.
+Creating register for signal `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.\timer' using process `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1397$3989'.
+ created $dff cell `$procdff$16553' with positive edge clock.
+Creating register for signal `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.\mem_wordsize' using process `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1397$3989'.
+ created $dff cell `$procdff$16554' with positive edge clock.
+Creating register for signal `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.\mem_do_prefetch' using process `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1397$3989'.
+ created $dff cell `$procdff$16555' with positive edge clock.
+Creating register for signal `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.\mem_do_rinst' using process `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1397$3989'.
+ created $dff cell `$procdff$16556' with positive edge clock.
+Creating register for signal `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.\mem_do_rdata' using process `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1397$3989'.
+ created $dff cell `$procdff$16557' with positive edge clock.
+Creating register for signal `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.\mem_do_wdata' using process `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1397$3989'.
+ created $dff cell `$procdff$16558' with positive edge clock.
+Creating register for signal `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.\decoder_trigger' using process `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1397$3989'.
+ created $dff cell `$procdff$16559' with positive edge clock.
+Creating register for signal `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.\decoder_trigger_q' using process `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1397$3989'.
+ created $dff cell `$procdff$16560' with positive edge clock.
+Creating register for signal `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.\decoder_pseudo_trigger' using process `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1397$3989'.
+ created $dff cell `$procdff$16561' with positive edge clock.
+Creating register for signal `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.\decoder_pseudo_trigger_q' using process `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1397$3989'.
+ created $dff cell `$procdff$16562' with positive edge clock.
+Creating register for signal `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.\dbg_rs1val' using process `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1397$3989'.
+ created $dff cell `$procdff$16563' with positive edge clock.
+Creating register for signal `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.\dbg_rs2val' using process `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1397$3989'.
+ created $dff cell `$procdff$16564' with positive edge clock.
+Creating register for signal `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.\dbg_rs1val_valid' using process `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1397$3989'.
+ created $dff cell `$procdff$16565' with positive edge clock.
+Creating register for signal `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.\dbg_rs2val_valid' using process `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1397$3989'.
+ created $dff cell `$procdff$16566' with positive edge clock.
+Creating register for signal `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.\cpu_state' using process `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1397$3989'.
+ created $dff cell `$procdff$16567' with positive edge clock.
+Creating register for signal `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.\irq_state' using process `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1397$3989'.
+ created $dff cell `$procdff$16568' with positive edge clock.
+Creating register for signal `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.\set_mem_do_rinst' using process `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1397$3989'.
+ created $dff cell `$procdff$16569' with positive edge clock.
+Creating register for signal `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.\set_mem_do_rdata' using process `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1397$3989'.
+ created $dff cell `$procdff$16570' with positive edge clock.
+Creating register for signal `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.\set_mem_do_wdata' using process `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1397$3989'.
+ created $dff cell `$procdff$16571' with positive edge clock.
+Creating register for signal `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.\latched_store' using process `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1397$3989'.
+ created $dff cell `$procdff$16572' with positive edge clock.
+Creating register for signal `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.\latched_stalu' using process `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1397$3989'.
+ created $dff cell `$procdff$16573' with positive edge clock.
+Creating register for signal `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.\latched_branch' using process `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1397$3989'.
+ created $dff cell `$procdff$16574' with positive edge clock.
+Creating register for signal `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.\latched_compr' using process `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1397$3989'.
+ created $dff cell `$procdff$16575' with positive edge clock.
+Creating register for signal `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.\latched_trace' using process `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1397$3989'.
+ created $dff cell `$procdff$16576' with positive edge clock.
+Creating register for signal `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.\latched_is_lu' using process `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1397$3989'.
+ created $dff cell `$procdff$16577' with positive edge clock.
+Creating register for signal `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.\latched_is_lh' using process `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1397$3989'.
+ created $dff cell `$procdff$16578' with positive edge clock.
+Creating register for signal `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.\latched_is_lb' using process `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1397$3989'.
+ created $dff cell `$procdff$16579' with positive edge clock.
+Creating register for signal `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.\latched_rd' using process `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1397$3989'.
+ created $dff cell `$procdff$16580' with positive edge clock.
+Creating register for signal `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.\current_pc' using process `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1397$3989'.
+ created $dff cell `$procdff$16581' with positive edge clock.
+Creating register for signal `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.\pcpi_timeout_counter' using process `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1397$3989'.
+ created $dff cell `$procdff$16582' with positive edge clock.
+Creating register for signal `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.\pcpi_timeout' using process `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1397$3989'.
+ created $dff cell `$procdff$16583' with positive edge clock.
+Creating register for signal `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.\next_irq_pending' using process `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1397$3989'.
+ created $dff cell `$procdff$16584' with positive edge clock.
+Creating register for signal `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.\do_waitirq' using process `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1397$3989'.
+ created $dff cell `$procdff$16585' with positive edge clock.
+Creating register for signal `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.\alu_out_q' using process `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1397$3989'.
+ created $dff cell `$procdff$16586' with positive edge clock.
+Creating register for signal `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.\alu_out_0_q' using process `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1397$3989'.
+ created $dff cell `$procdff$16587' with positive edge clock.
+Creating register for signal `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.\alu_wait' using process `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1397$3989'.
+ created $dff cell `$procdff$16588' with positive edge clock.
+Creating register for signal `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.\alu_wait_2' using process `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1397$3989'.
+ created $dff cell `$procdff$16589' with positive edge clock.
+Creating register for signal `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.\clear_prefetched_high_word_q' using process `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1288$3955'.
+ created $dff cell `$procdff$16590' with positive edge clock.
+Creating register for signal `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.\pcpi_insn' using process `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$3661'.
+ created $dff cell `$procdff$16591' with positive edge clock.
+Creating register for signal `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.\instr_lui' using process `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$3661'.
+ created $dff cell `$procdff$16592' with positive edge clock.
+Creating register for signal `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.\instr_auipc' using process `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$3661'.
+ created $dff cell `$procdff$16593' with positive edge clock.
+Creating register for signal `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.\instr_jal' using process `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$3661'.
+ created $dff cell `$procdff$16594' with positive edge clock.
+Creating register for signal `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.\instr_jalr' using process `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$3661'.
+ created $dff cell `$procdff$16595' with positive edge clock.
+Creating register for signal `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.\instr_beq' using process `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$3661'.
+ created $dff cell `$procdff$16596' with positive edge clock.
+Creating register for signal `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.\instr_bne' using process `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$3661'.
+ created $dff cell `$procdff$16597' with positive edge clock.
+Creating register for signal `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.\instr_blt' using process `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$3661'.
+ created $dff cell `$procdff$16598' with positive edge clock.
+Creating register for signal `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.\instr_bge' using process `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$3661'.
+ created $dff cell `$procdff$16599' with positive edge clock.
+Creating register for signal `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.\instr_bltu' using process `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$3661'.
+ created $dff cell `$procdff$16600' with positive edge clock.
+Creating register for signal `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.\instr_bgeu' using process `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$3661'.
+ created $dff cell `$procdff$16601' with positive edge clock.
+Creating register for signal `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.\instr_lb' using process `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$3661'.
+ created $dff cell `$procdff$16602' with positive edge clock.
+Creating register for signal `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.\instr_lh' using process `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$3661'.
+ created $dff cell `$procdff$16603' with positive edge clock.
+Creating register for signal `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.\instr_lw' using process `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$3661'.
+ created $dff cell `$procdff$16604' with positive edge clock.
+Creating register for signal `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.\instr_lbu' using process `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$3661'.
+ created $dff cell `$procdff$16605' with positive edge clock.
+Creating register for signal `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.\instr_lhu' using process `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$3661'.
+ created $dff cell `$procdff$16606' with positive edge clock.
+Creating register for signal `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.\instr_sb' using process `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$3661'.
+ created $dff cell `$procdff$16607' with positive edge clock.
+Creating register for signal `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.\instr_sh' using process `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$3661'.
+ created $dff cell `$procdff$16608' with positive edge clock.
+Creating register for signal `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.\instr_sw' using process `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$3661'.
+ created $dff cell `$procdff$16609' with positive edge clock.
+Creating register for signal `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.\instr_addi' using process `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$3661'.
+ created $dff cell `$procdff$16610' with positive edge clock.
+Creating register for signal `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.\instr_slti' using process `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$3661'.
+ created $dff cell `$procdff$16611' with positive edge clock.
+Creating register for signal `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.\instr_sltiu' using process `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$3661'.
+ created $dff cell `$procdff$16612' with positive edge clock.
+Creating register for signal `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.\instr_xori' using process `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$3661'.
+ created $dff cell `$procdff$16613' with positive edge clock.
+Creating register for signal `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.\instr_ori' using process `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$3661'.
+ created $dff cell `$procdff$16614' with positive edge clock.
+Creating register for signal `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.\instr_andi' using process `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$3661'.
+ created $dff cell `$procdff$16615' with positive edge clock.
+Creating register for signal `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.\instr_slli' using process `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$3661'.
+ created $dff cell `$procdff$16616' with positive edge clock.
+Creating register for signal `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.\instr_srli' using process `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$3661'.
+ created $dff cell `$procdff$16617' with positive edge clock.
+Creating register for signal `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.\instr_srai' using process `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$3661'.
+ created $dff cell `$procdff$16618' with positive edge clock.
+Creating register for signal `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.\instr_add' using process `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$3661'.
+ created $dff cell `$procdff$16619' with positive edge clock.
+Creating register for signal `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.\instr_sub' using process `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$3661'.
+ created $dff cell `$procdff$16620' with positive edge clock.
+Creating register for signal `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.\instr_sll' using process `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$3661'.
+ created $dff cell `$procdff$16621' with positive edge clock.
+Creating register for signal `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.\instr_slt' using process `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$3661'.
+ created $dff cell `$procdff$16622' with positive edge clock.
+Creating register for signal `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.\instr_sltu' using process `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$3661'.
+ created $dff cell `$procdff$16623' with positive edge clock.
+Creating register for signal `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.\instr_xor' using process `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$3661'.
+ created $dff cell `$procdff$16624' with positive edge clock.
+Creating register for signal `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.\instr_srl' using process `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$3661'.
+ created $dff cell `$procdff$16625' with positive edge clock.
+Creating register for signal `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.\instr_sra' using process `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$3661'.
+ created $dff cell `$procdff$16626' with positive edge clock.
+Creating register for signal `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.\instr_or' using process `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$3661'.
+ created $dff cell `$procdff$16627' with positive edge clock.
+Creating register for signal `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.\instr_and' using process `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$3661'.
+ created $dff cell `$procdff$16628' with positive edge clock.
+Creating register for signal `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.\instr_rdcycle' using process `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$3661'.
+ created $dff cell `$procdff$16629' with positive edge clock.
+Creating register for signal `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.\instr_rdcycleh' using process `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$3661'.
+ created $dff cell `$procdff$16630' with positive edge clock.
+Creating register for signal `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.\instr_rdinstr' using process `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$3661'.
+ created $dff cell `$procdff$16631' with positive edge clock.
+Creating register for signal `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.\instr_rdinstrh' using process `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$3661'.
+ created $dff cell `$procdff$16632' with positive edge clock.
+Creating register for signal `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.\instr_ecall_ebreak' using process `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$3661'.
+ created $dff cell `$procdff$16633' with positive edge clock.
+Creating register for signal `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.\instr_getq' using process `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$3661'.
+ created $dff cell `$procdff$16634' with positive edge clock.
+Creating register for signal `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.\instr_setq' using process `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$3661'.
+ created $dff cell `$procdff$16635' with positive edge clock.
+Creating register for signal `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.\instr_retirq' using process `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$3661'.
+ created $dff cell `$procdff$16636' with positive edge clock.
+Creating register for signal `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.\instr_maskirq' using process `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$3661'.
+ created $dff cell `$procdff$16637' with positive edge clock.
+Creating register for signal `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.\instr_waitirq' using process `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$3661'.
+ created $dff cell `$procdff$16638' with positive edge clock.
+Creating register for signal `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.\instr_timer' using process `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$3661'.
+ created $dff cell `$procdff$16639' with positive edge clock.
+Creating register for signal `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.\decoded_rd' using process `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$3661'.
+ created $dff cell `$procdff$16640' with positive edge clock.
+Creating register for signal `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.\decoded_rs1' using process `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$3661'.
+ created $dff cell `$procdff$16641' with positive edge clock.
+Creating register for signal `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.\decoded_rs2' using process `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$3661'.
+ created $dff cell `$procdff$16642' with positive edge clock.
+Creating register for signal `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.\decoded_imm' using process `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$3661'.
+ created $dff cell `$procdff$16643' with positive edge clock.
+Creating register for signal `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.\decoded_imm_j' using process `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$3661'.
+ created $dff cell `$procdff$16644' with positive edge clock.
+Creating register for signal `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.\compressed_instr' using process `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$3661'.
+ created $dff cell `$procdff$16645' with positive edge clock.
+Creating register for signal `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.\is_lui_auipc_jal' using process `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$3661'.
+ created $dff cell `$procdff$16646' with positive edge clock.
+Creating register for signal `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.\is_lb_lh_lw_lbu_lhu' using process `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$3661'.
+ created $dff cell `$procdff$16647' with positive edge clock.
+Creating register for signal `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.\is_slli_srli_srai' using process `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$3661'.
+ created $dff cell `$procdff$16648' with positive edge clock.
+Creating register for signal `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.\is_jalr_addi_slti_sltiu_xori_ori_andi' using process `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$3661'.
+ created $dff cell `$procdff$16649' with positive edge clock.
+Creating register for signal `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.\is_sb_sh_sw' using process `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$3661'.
+ created $dff cell `$procdff$16650' with positive edge clock.
+Creating register for signal `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.\is_sll_srl_sra' using process `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$3661'.
+ created $dff cell `$procdff$16651' with positive edge clock.
+Creating register for signal `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.\is_lui_auipc_jal_jalr_addi_add_sub' using process `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$3661'.
+ created $dff cell `$procdff$16652' with positive edge clock.
+Creating register for signal `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.\is_slti_blt_slt' using process `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$3661'.
+ created $dff cell `$procdff$16653' with positive edge clock.
+Creating register for signal `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.\is_sltiu_bltu_sltu' using process `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$3661'.
+ created $dff cell `$procdff$16654' with positive edge clock.
+Creating register for signal `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.\is_beq_bne_blt_bge_bltu_bgeu' using process `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$3661'.
+ created $dff cell `$procdff$16655' with positive edge clock.
+Creating register for signal `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.\is_lbu_lhu_lw' using process `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$3661'.
+ created $dff cell `$procdff$16656' with positive edge clock.
+Creating register for signal `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.\is_alu_reg_imm' using process `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$3661'.
+ created $dff cell `$procdff$16657' with positive edge clock.
+Creating register for signal `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.\is_alu_reg_reg' using process `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$3661'.
+ created $dff cell `$procdff$16658' with positive edge clock.
+Creating register for signal `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.\is_compare' using process `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$3661'.
+ created $dff cell `$procdff$16659' with positive edge clock.
+Creating register for signal `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.\dbg_insn_addr' using process `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:776$3655'.
+ created $dff cell `$procdff$16660' with positive edge clock.
+Creating register for signal `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.\q_ascii_instr' using process `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:776$3655'.
+ created $dff cell `$procdff$16661' with positive edge clock.
+Creating register for signal `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.\q_insn_imm' using process `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:776$3655'.
+ created $dff cell `$procdff$16662' with positive edge clock.
+Creating register for signal `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.\q_insn_opcode' using process `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:776$3655'.
+ created $dff cell `$procdff$16663' with positive edge clock.
+Creating register for signal `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.\q_insn_rs1' using process `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:776$3655'.
+ created $dff cell `$procdff$16664' with positive edge clock.
+Creating register for signal `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.\q_insn_rs2' using process `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:776$3655'.
+ created $dff cell `$procdff$16665' with positive edge clock.
+Creating register for signal `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.\q_insn_rd' using process `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:776$3655'.
+ created $dff cell `$procdff$16666' with positive edge clock.
+Creating register for signal `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.\dbg_next' using process `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:776$3655'.
+ created $dff cell `$procdff$16667' with positive edge clock.
+Creating register for signal `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.\dbg_valid_insn' using process `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:776$3655'.
+ created $dff cell `$procdff$16668' with positive edge clock.
+Creating register for signal `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.\cached_ascii_instr' using process `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:776$3655'.
+ created $dff cell `$procdff$16669' with positive edge clock.
+Creating register for signal `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.\cached_insn_imm' using process `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:776$3655'.
+ created $dff cell `$procdff$16670' with positive edge clock.
+Creating register for signal `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.\cached_insn_opcode' using process `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:776$3655'.
+ created $dff cell `$procdff$16671' with positive edge clock.
+Creating register for signal `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.\cached_insn_rs1' using process `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:776$3655'.
+ created $dff cell `$procdff$16672' with positive edge clock.
+Creating register for signal `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.\cached_insn_rs2' using process `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:776$3655'.
+ created $dff cell `$procdff$16673' with positive edge clock.
+Creating register for signal `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.\cached_insn_rd' using process `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:776$3655'.
+ created $dff cell `$procdff$16674' with positive edge clock.
+Creating register for signal `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.\mem_instr' using process `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:565$3630'.
+ created $dff cell `$procdff$16675' with positive edge clock.
+Creating register for signal `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.\mem_wdata' using process `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:565$3630'.
+ created $dff cell `$procdff$16676' with positive edge clock.
+Creating register for signal `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.\mem_addr' using process `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:565$3630'.
+ created $dff cell `$procdff$16677' with positive edge clock.
+Creating register for signal `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.\mem_valid' using process `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:565$3630'.
+ created $dff cell `$procdff$16678' with positive edge clock.
+Creating register for signal `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.\mem_wstrb' using process `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:565$3630'.
+ created $dff cell `$procdff$16679' with positive edge clock.
+Creating register for signal `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.\mem_state' using process `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:565$3630'.
+ created $dff cell `$procdff$16680' with positive edge clock.
+Creating register for signal `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.\mem_la_secondword' using process `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:565$3630'.
+ created $dff cell `$procdff$16681' with positive edge clock.
+Creating register for signal `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.\prefetched_high_word' using process `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:565$3630'.
+ created $dff cell `$procdff$16682' with positive edge clock.
+Creating register for signal `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.\mem_16bit_buffer' using process `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:565$3630'.
+ created $dff cell `$procdff$16683' with positive edge clock.
+Creating register for signal `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.\next_insn_opcode' using process `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:430$3592'.
+ created $dff cell `$procdff$16684' with positive edge clock.
+Creating register for signal `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.\mem_rdata_q' using process `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:430$3592'.
+ created $dff cell `$procdff$16685' with positive edge clock.
+Creating register for signal `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.\mem_la_firstword_reg' using process `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:390$3584'.
+ created $dff cell `$procdff$16686' with positive edge clock.
+Creating register for signal `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.\last_mem_valid' using process `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:390$3584'.
+ created $dff cell `$procdff$16687' with positive edge clock.
+Creating register for signal `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.\pcpi_valid' using process `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1397$3306'.
+ created $dff cell `$procdff$16688' with positive edge clock.
+Creating register for signal `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.\trap' using process `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1397$3306'.
+ created $dff cell `$procdff$16689' with positive edge clock.
+Creating register for signal `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.\eoi' using process `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1397$3306'.
+ created $dff cell `$procdff$16690' with positive edge clock.
+Creating register for signal `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.\trace_valid' using process `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1397$3306'.
+ created $dff cell `$procdff$16691' with positive edge clock.
+Creating register for signal `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.\trace_data' using process `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1397$3306'.
+ created $dff cell `$procdff$16692' with positive edge clock.
+Creating register for signal `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.\count_cycle' using process `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1397$3306'.
+ created $dff cell `$procdff$16693' with positive edge clock.
+Creating register for signal `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.\count_instr' using process `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1397$3306'.
+ created $dff cell `$procdff$16694' with positive edge clock.
+Creating register for signal `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.\reg_pc' using process `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1397$3306'.
+ created $dff cell `$procdff$16695' with positive edge clock.
+Creating register for signal `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.\reg_next_pc' using process `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1397$3306'.
+ created $dff cell `$procdff$16696' with positive edge clock.
+Creating register for signal `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.\reg_op1' using process `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1397$3306'.
+ created $dff cell `$procdff$16697' with positive edge clock.
+Creating register for signal `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.\reg_op2' using process `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1397$3306'.
+ created $dff cell `$procdff$16698' with positive edge clock.
+Creating register for signal `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.\reg_out' using process `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1397$3306'.
+ created $dff cell `$procdff$16699' with positive edge clock.
+Creating register for signal `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.\reg_sh' using process `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1397$3306'.
+ created $dff cell `$procdff$16700' with positive edge clock.
+Creating register for signal `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.\irq_delay' using process `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1397$3306'.
+ created $dff cell `$procdff$16701' with positive edge clock.
+Creating register for signal `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.\irq_active' using process `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1397$3306'.
+ created $dff cell `$procdff$16702' with positive edge clock.
+Creating register for signal `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.\irq_mask' using process `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1397$3306'.
+ created $dff cell `$procdff$16703' with positive edge clock.
+Creating register for signal `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.\irq_pending' using process `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1397$3306'.
+ created $dff cell `$procdff$16704' with positive edge clock.
+Creating register for signal `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.\timer' using process `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1397$3306'.
+ created $dff cell `$procdff$16705' with positive edge clock.
+Creating register for signal `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.\mem_wordsize' using process `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1397$3306'.
+ created $dff cell `$procdff$16706' with positive edge clock.
+Creating register for signal `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.\mem_do_prefetch' using process `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1397$3306'.
+ created $dff cell `$procdff$16707' with positive edge clock.
+Creating register for signal `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.\mem_do_rinst' using process `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1397$3306'.
+ created $dff cell `$procdff$16708' with positive edge clock.
+Creating register for signal `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.\mem_do_rdata' using process `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1397$3306'.
+ created $dff cell `$procdff$16709' with positive edge clock.
+Creating register for signal `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.\mem_do_wdata' using process `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1397$3306'.
+ created $dff cell `$procdff$16710' with positive edge clock.
+Creating register for signal `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.\decoder_trigger' using process `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1397$3306'.
+ created $dff cell `$procdff$16711' with positive edge clock.
+Creating register for signal `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.\decoder_trigger_q' using process `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1397$3306'.
+ created $dff cell `$procdff$16712' with positive edge clock.
+Creating register for signal `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.\decoder_pseudo_trigger' using process `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1397$3306'.
+ created $dff cell `$procdff$16713' with positive edge clock.
+Creating register for signal `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.\decoder_pseudo_trigger_q' using process `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1397$3306'.
+ created $dff cell `$procdff$16714' with positive edge clock.
+Creating register for signal `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.\dbg_rs1val' using process `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1397$3306'.
+ created $dff cell `$procdff$16715' with positive edge clock.
+Creating register for signal `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.\dbg_rs2val' using process `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1397$3306'.
+ created $dff cell `$procdff$16716' with positive edge clock.
+Creating register for signal `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.\dbg_rs1val_valid' using process `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1397$3306'.
+ created $dff cell `$procdff$16717' with positive edge clock.
+Creating register for signal `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.\dbg_rs2val_valid' using process `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1397$3306'.
+ created $dff cell `$procdff$16718' with positive edge clock.
+Creating register for signal `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.\cpu_state' using process `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1397$3306'.
+ created $dff cell `$procdff$16719' with positive edge clock.
+Creating register for signal `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.\irq_state' using process `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1397$3306'.
+ created $dff cell `$procdff$16720' with positive edge clock.
+Creating register for signal `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.\set_mem_do_rinst' using process `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1397$3306'.
+ created $dff cell `$procdff$16721' with positive edge clock.
+Creating register for signal `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.\set_mem_do_rdata' using process `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1397$3306'.
+ created $dff cell `$procdff$16722' with positive edge clock.
+Creating register for signal `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.\set_mem_do_wdata' using process `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1397$3306'.
+ created $dff cell `$procdff$16723' with positive edge clock.
+Creating register for signal `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.\latched_store' using process `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1397$3306'.
+ created $dff cell `$procdff$16724' with positive edge clock.
+Creating register for signal `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.\latched_stalu' using process `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1397$3306'.
+ created $dff cell `$procdff$16725' with positive edge clock.
+Creating register for signal `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.\latched_branch' using process `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1397$3306'.
+ created $dff cell `$procdff$16726' with positive edge clock.
+Creating register for signal `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.\latched_compr' using process `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1397$3306'.
+ created $dff cell `$procdff$16727' with positive edge clock.
+Creating register for signal `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.\latched_trace' using process `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1397$3306'.
+ created $dff cell `$procdff$16728' with positive edge clock.
+Creating register for signal `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.\latched_is_lu' using process `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1397$3306'.
+ created $dff cell `$procdff$16729' with positive edge clock.
+Creating register for signal `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.\latched_is_lh' using process `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1397$3306'.
+ created $dff cell `$procdff$16730' with positive edge clock.
+Creating register for signal `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.\latched_is_lb' using process `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1397$3306'.
+ created $dff cell `$procdff$16731' with positive edge clock.
+Creating register for signal `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.\latched_rd' using process `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1397$3306'.
+ created $dff cell `$procdff$16732' with positive edge clock.
+Creating register for signal `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.\current_pc' using process `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1397$3306'.
+ created $dff cell `$procdff$16733' with positive edge clock.
+Creating register for signal `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.\pcpi_timeout_counter' using process `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1397$3306'.
+ created $dff cell `$procdff$16734' with positive edge clock.
+Creating register for signal `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.\pcpi_timeout' using process `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1397$3306'.
+ created $dff cell `$procdff$16735' with positive edge clock.
+Creating register for signal `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.\next_irq_pending' using process `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1397$3306'.
+ created $dff cell `$procdff$16736' with positive edge clock.
+Creating register for signal `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.\do_waitirq' using process `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1397$3306'.
+ created $dff cell `$procdff$16737' with positive edge clock.
+Creating register for signal `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.\alu_out_q' using process `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1397$3306'.
+ created $dff cell `$procdff$16738' with positive edge clock.
+Creating register for signal `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.\alu_out_0_q' using process `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1397$3306'.
+ created $dff cell `$procdff$16739' with positive edge clock.
+Creating register for signal `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.\alu_wait' using process `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1397$3306'.
+ created $dff cell `$procdff$16740' with positive edge clock.
+Creating register for signal `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.\alu_wait_2' using process `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1397$3306'.
+ created $dff cell `$procdff$16741' with positive edge clock.
+Creating register for signal `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.\clear_prefetched_high_word_q' using process `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1288$3272'.
+ created $dff cell `$procdff$16742' with positive edge clock.
+Creating register for signal `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.\pcpi_insn' using process `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$2978'.
+ created $dff cell `$procdff$16743' with positive edge clock.
+Creating register for signal `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.\instr_lui' using process `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$2978'.
+ created $dff cell `$procdff$16744' with positive edge clock.
+Creating register for signal `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.\instr_auipc' using process `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$2978'.
+ created $dff cell `$procdff$16745' with positive edge clock.
+Creating register for signal `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.\instr_jal' using process `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$2978'.
+ created $dff cell `$procdff$16746' with positive edge clock.
+Creating register for signal `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.\instr_jalr' using process `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$2978'.
+ created $dff cell `$procdff$16747' with positive edge clock.
+Creating register for signal `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.\instr_beq' using process `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$2978'.
+ created $dff cell `$procdff$16748' with positive edge clock.
+Creating register for signal `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.\instr_bne' using process `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$2978'.
+ created $dff cell `$procdff$16749' with positive edge clock.
+Creating register for signal `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.\instr_blt' using process `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$2978'.
+ created $dff cell `$procdff$16750' with positive edge clock.
+Creating register for signal `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.\instr_bge' using process `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$2978'.
+ created $dff cell `$procdff$16751' with positive edge clock.
+Creating register for signal `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.\instr_bltu' using process `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$2978'.
+ created $dff cell `$procdff$16752' with positive edge clock.
+Creating register for signal `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.\instr_bgeu' using process `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$2978'.
+ created $dff cell `$procdff$16753' with positive edge clock.
+Creating register for signal `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.\instr_lb' using process `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$2978'.
+ created $dff cell `$procdff$16754' with positive edge clock.
+Creating register for signal `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.\instr_lh' using process `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$2978'.
+ created $dff cell `$procdff$16755' with positive edge clock.
+Creating register for signal `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.\instr_lw' using process `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$2978'.
+ created $dff cell `$procdff$16756' with positive edge clock.
+Creating register for signal `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.\instr_lbu' using process `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$2978'.
+ created $dff cell `$procdff$16757' with positive edge clock.
+Creating register for signal `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.\instr_lhu' using process `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$2978'.
+ created $dff cell `$procdff$16758' with positive edge clock.
+Creating register for signal `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.\instr_sb' using process `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$2978'.
+ created $dff cell `$procdff$16759' with positive edge clock.
+Creating register for signal `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.\instr_sh' using process `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$2978'.
+ created $dff cell `$procdff$16760' with positive edge clock.
+Creating register for signal `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.\instr_sw' using process `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$2978'.
+ created $dff cell `$procdff$16761' with positive edge clock.
+Creating register for signal `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.\instr_addi' using process `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$2978'.
+ created $dff cell `$procdff$16762' with positive edge clock.
+Creating register for signal `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.\instr_slti' using process `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$2978'.
+ created $dff cell `$procdff$16763' with positive edge clock.
+Creating register for signal `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.\instr_sltiu' using process `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$2978'.
+ created $dff cell `$procdff$16764' with positive edge clock.
+Creating register for signal `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.\instr_xori' using process `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$2978'.
+ created $dff cell `$procdff$16765' with positive edge clock.
+Creating register for signal `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.\instr_ori' using process `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$2978'.
+ created $dff cell `$procdff$16766' with positive edge clock.
+Creating register for signal `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.\instr_andi' using process `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$2978'.
+ created $dff cell `$procdff$16767' with positive edge clock.
+Creating register for signal `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.\instr_slli' using process `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$2978'.
+ created $dff cell `$procdff$16768' with positive edge clock.
+Creating register for signal `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.\instr_srli' using process `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$2978'.
+ created $dff cell `$procdff$16769' with positive edge clock.
+Creating register for signal `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.\instr_srai' using process `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$2978'.
+ created $dff cell `$procdff$16770' with positive edge clock.
+Creating register for signal `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.\instr_add' using process `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$2978'.
+ created $dff cell `$procdff$16771' with positive edge clock.
+Creating register for signal `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.\instr_sub' using process `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$2978'.
+ created $dff cell `$procdff$16772' with positive edge clock.
+Creating register for signal `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.\instr_sll' using process `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$2978'.
+ created $dff cell `$procdff$16773' with positive edge clock.
+Creating register for signal `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.\instr_slt' using process `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$2978'.
+ created $dff cell `$procdff$16774' with positive edge clock.
+Creating register for signal `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.\instr_sltu' using process `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$2978'.
+ created $dff cell `$procdff$16775' with positive edge clock.
+Creating register for signal `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.\instr_xor' using process `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$2978'.
+ created $dff cell `$procdff$16776' with positive edge clock.
+Creating register for signal `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.\instr_srl' using process `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$2978'.
+ created $dff cell `$procdff$16777' with positive edge clock.
+Creating register for signal `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.\instr_sra' using process `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$2978'.
+ created $dff cell `$procdff$16778' with positive edge clock.
+Creating register for signal `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.\instr_or' using process `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$2978'.
+ created $dff cell `$procdff$16779' with positive edge clock.
+Creating register for signal `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.\instr_and' using process `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$2978'.
+ created $dff cell `$procdff$16780' with positive edge clock.
+Creating register for signal `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.\instr_rdcycle' using process `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$2978'.
+ created $dff cell `$procdff$16781' with positive edge clock.
+Creating register for signal `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.\instr_rdcycleh' using process `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$2978'.
+ created $dff cell `$procdff$16782' with positive edge clock.
+Creating register for signal `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.\instr_rdinstr' using process `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$2978'.
+ created $dff cell `$procdff$16783' with positive edge clock.
+Creating register for signal `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.\instr_rdinstrh' using process `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$2978'.
+ created $dff cell `$procdff$16784' with positive edge clock.
+Creating register for signal `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.\instr_ecall_ebreak' using process `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$2978'.
+ created $dff cell `$procdff$16785' with positive edge clock.
+Creating register for signal `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.\instr_getq' using process `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$2978'.
+ created $dff cell `$procdff$16786' with positive edge clock.
+Creating register for signal `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.\instr_setq' using process `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$2978'.
+ created $dff cell `$procdff$16787' with positive edge clock.
+Creating register for signal `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.\instr_retirq' using process `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$2978'.
+ created $dff cell `$procdff$16788' with positive edge clock.
+Creating register for signal `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.\instr_maskirq' using process `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$2978'.
+ created $dff cell `$procdff$16789' with positive edge clock.
+Creating register for signal `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.\instr_waitirq' using process `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$2978'.
+ created $dff cell `$procdff$16790' with positive edge clock.
+Creating register for signal `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.\instr_timer' using process `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$2978'.
+ created $dff cell `$procdff$16791' with positive edge clock.
+Creating register for signal `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.\decoded_rd' using process `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$2978'.
+ created $dff cell `$procdff$16792' with positive edge clock.
+Creating register for signal `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.\decoded_rs1' using process `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$2978'.
+ created $dff cell `$procdff$16793' with positive edge clock.
+Creating register for signal `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.\decoded_rs2' using process `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$2978'.
+ created $dff cell `$procdff$16794' with positive edge clock.
+Creating register for signal `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.\decoded_imm' using process `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$2978'.
+ created $dff cell `$procdff$16795' with positive edge clock.
+Creating register for signal `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.\decoded_imm_j' using process `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$2978'.
+ created $dff cell `$procdff$16796' with positive edge clock.
+Creating register for signal `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.\compressed_instr' using process `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$2978'.
+ created $dff cell `$procdff$16797' with positive edge clock.
+Creating register for signal `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.\is_lui_auipc_jal' using process `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$2978'.
+ created $dff cell `$procdff$16798' with positive edge clock.
+Creating register for signal `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.\is_lb_lh_lw_lbu_lhu' using process `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$2978'.
+ created $dff cell `$procdff$16799' with positive edge clock.
+Creating register for signal `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.\is_slli_srli_srai' using process `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$2978'.
+ created $dff cell `$procdff$16800' with positive edge clock.
+Creating register for signal `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.\is_jalr_addi_slti_sltiu_xori_ori_andi' using process `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$2978'.
+ created $dff cell `$procdff$16801' with positive edge clock.
+Creating register for signal `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.\is_sb_sh_sw' using process `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$2978'.
+ created $dff cell `$procdff$16802' with positive edge clock.
+Creating register for signal `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.\is_sll_srl_sra' using process `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$2978'.
+ created $dff cell `$procdff$16803' with positive edge clock.
+Creating register for signal `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.\is_lui_auipc_jal_jalr_addi_add_sub' using process `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$2978'.
+ created $dff cell `$procdff$16804' with positive edge clock.
+Creating register for signal `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.\is_slti_blt_slt' using process `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$2978'.
+ created $dff cell `$procdff$16805' with positive edge clock.
+Creating register for signal `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.\is_sltiu_bltu_sltu' using process `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$2978'.
+ created $dff cell `$procdff$16806' with positive edge clock.
+Creating register for signal `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.\is_beq_bne_blt_bge_bltu_bgeu' using process `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$2978'.
+ created $dff cell `$procdff$16807' with positive edge clock.
+Creating register for signal `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.\is_lbu_lhu_lw' using process `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$2978'.
+ created $dff cell `$procdff$16808' with positive edge clock.
+Creating register for signal `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.\is_alu_reg_imm' using process `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$2978'.
+ created $dff cell `$procdff$16809' with positive edge clock.
+Creating register for signal `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.\is_alu_reg_reg' using process `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$2978'.
+ created $dff cell `$procdff$16810' with positive edge clock.
+Creating register for signal `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.\is_compare' using process `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$2978'.
+ created $dff cell `$procdff$16811' with positive edge clock.
+Creating register for signal `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.\dbg_insn_addr' using process `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:776$2972'.
+ created $dff cell `$procdff$16812' with positive edge clock.
+Creating register for signal `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.\q_ascii_instr' using process `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:776$2972'.
+ created $dff cell `$procdff$16813' with positive edge clock.
+Creating register for signal `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.\q_insn_imm' using process `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:776$2972'.
+ created $dff cell `$procdff$16814' with positive edge clock.
+Creating register for signal `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.\q_insn_opcode' using process `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:776$2972'.
+ created $dff cell `$procdff$16815' with positive edge clock.
+Creating register for signal `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.\q_insn_rs1' using process `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:776$2972'.
+ created $dff cell `$procdff$16816' with positive edge clock.
+Creating register for signal `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.\q_insn_rs2' using process `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:776$2972'.
+ created $dff cell `$procdff$16817' with positive edge clock.
+Creating register for signal `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.\q_insn_rd' using process `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:776$2972'.
+ created $dff cell `$procdff$16818' with positive edge clock.
+Creating register for signal `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.\dbg_next' using process `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:776$2972'.
+ created $dff cell `$procdff$16819' with positive edge clock.
+Creating register for signal `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.\dbg_valid_insn' using process `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:776$2972'.
+ created $dff cell `$procdff$16820' with positive edge clock.
+Creating register for signal `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.\cached_ascii_instr' using process `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:776$2972'.
+ created $dff cell `$procdff$16821' with positive edge clock.
+Creating register for signal `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.\cached_insn_imm' using process `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:776$2972'.
+ created $dff cell `$procdff$16822' with positive edge clock.
+Creating register for signal `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.\cached_insn_opcode' using process `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:776$2972'.
+ created $dff cell `$procdff$16823' with positive edge clock.
+Creating register for signal `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.\cached_insn_rs1' using process `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:776$2972'.
+ created $dff cell `$procdff$16824' with positive edge clock.
+Creating register for signal `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.\cached_insn_rs2' using process `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:776$2972'.
+ created $dff cell `$procdff$16825' with positive edge clock.
+Creating register for signal `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.\cached_insn_rd' using process `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:776$2972'.
+ created $dff cell `$procdff$16826' with positive edge clock.
+Creating register for signal `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.\mem_instr' using process `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:565$2947'.
+ created $dff cell `$procdff$16827' with positive edge clock.
+Creating register for signal `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.\mem_wdata' using process `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:565$2947'.
+ created $dff cell `$procdff$16828' with positive edge clock.
+Creating register for signal `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.\mem_addr' using process `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:565$2947'.
+ created $dff cell `$procdff$16829' with positive edge clock.
+Creating register for signal `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.\mem_valid' using process `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:565$2947'.
+ created $dff cell `$procdff$16830' with positive edge clock.
+Creating register for signal `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.\mem_wstrb' using process `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:565$2947'.
+ created $dff cell `$procdff$16831' with positive edge clock.
+Creating register for signal `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.\mem_state' using process `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:565$2947'.
+ created $dff cell `$procdff$16832' with positive edge clock.
+Creating register for signal `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.\mem_la_secondword' using process `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:565$2947'.
+ created $dff cell `$procdff$16833' with positive edge clock.
+Creating register for signal `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.\prefetched_high_word' using process `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:565$2947'.
+ created $dff cell `$procdff$16834' with positive edge clock.
+Creating register for signal `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.\mem_16bit_buffer' using process `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:565$2947'.
+ created $dff cell `$procdff$16835' with positive edge clock.
+Creating register for signal `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.\next_insn_opcode' using process `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:430$2909'.
+ created $dff cell `$procdff$16836' with positive edge clock.
+Creating register for signal `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.\mem_rdata_q' using process `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:430$2909'.
+ created $dff cell `$procdff$16837' with positive edge clock.
+Creating register for signal `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.\mem_la_firstword_reg' using process `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:390$2901'.
+ created $dff cell `$procdff$16838' with positive edge clock.
+Creating register for signal `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.\last_mem_valid' using process `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:390$2901'.
+ created $dff cell `$procdff$16839' with positive edge clock.
+Creating register for signal `$paramod\ff32_ram\ADDR_WIDTH=5.\dout' using process `$paramod\ff32_ram\ADDR_WIDTH=5.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:114$2805'.
+ created $dff cell `$procdff$16840' with positive edge clock.
+Creating register for signal `$paramod\ff32_ram\ADDR_WIDTH=5.$memwr$\ram0$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:103$2788_ADDR' using process `$paramod\ff32_ram\ADDR_WIDTH=5.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:100$2792'.
+ created $dff cell `$procdff$16841' with positive edge clock.
+Creating register for signal `$paramod\ff32_ram\ADDR_WIDTH=5.$memwr$\ram0$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:103$2788_DATA' using process `$paramod\ff32_ram\ADDR_WIDTH=5.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:100$2792'.
+ created $dff cell `$procdff$16842' with positive edge clock.
+Creating register for signal `$paramod\ff32_ram\ADDR_WIDTH=5.$memwr$\ram0$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:103$2788_EN' using process `$paramod\ff32_ram\ADDR_WIDTH=5.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:100$2792'.
+ created $dff cell `$procdff$16843' with positive edge clock.
+Creating register for signal `$paramod\ff32_ram\ADDR_WIDTH=5.$memwr$\ram1$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:105$2789_ADDR' using process `$paramod\ff32_ram\ADDR_WIDTH=5.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:100$2792'.
+ created $dff cell `$procdff$16844' with positive edge clock.
+Creating register for signal `$paramod\ff32_ram\ADDR_WIDTH=5.$memwr$\ram1$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:105$2789_DATA' using process `$paramod\ff32_ram\ADDR_WIDTH=5.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:100$2792'.
+ created $dff cell `$procdff$16845' with positive edge clock.
+Creating register for signal `$paramod\ff32_ram\ADDR_WIDTH=5.$memwr$\ram1$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:105$2789_EN' using process `$paramod\ff32_ram\ADDR_WIDTH=5.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:100$2792'.
+ created $dff cell `$procdff$16846' with positive edge clock.
+Creating register for signal `$paramod\ff32_ram\ADDR_WIDTH=5.$memwr$\ram2$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:107$2790_ADDR' using process `$paramod\ff32_ram\ADDR_WIDTH=5.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:100$2792'.
+ created $dff cell `$procdff$16847' with positive edge clock.
+Creating register for signal `$paramod\ff32_ram\ADDR_WIDTH=5.$memwr$\ram2$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:107$2790_DATA' using process `$paramod\ff32_ram\ADDR_WIDTH=5.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:100$2792'.
+ created $dff cell `$procdff$16848' with positive edge clock.
+Creating register for signal `$paramod\ff32_ram\ADDR_WIDTH=5.$memwr$\ram2$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:107$2790_EN' using process `$paramod\ff32_ram\ADDR_WIDTH=5.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:100$2792'.
+ created $dff cell `$procdff$16849' with positive edge clock.
+Creating register for signal `$paramod\ff32_ram\ADDR_WIDTH=5.$memwr$\ram3$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:109$2791_ADDR' using process `$paramod\ff32_ram\ADDR_WIDTH=5.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:100$2792'.
+ created $dff cell `$procdff$16850' with positive edge clock.
+Creating register for signal `$paramod\ff32_ram\ADDR_WIDTH=5.$memwr$\ram3$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:109$2791_DATA' using process `$paramod\ff32_ram\ADDR_WIDTH=5.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:100$2792'.
+ created $dff cell `$procdff$16851' with positive edge clock.
+Creating register for signal `$paramod\ff32_ram\ADDR_WIDTH=5.$memwr$\ram3$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:109$2791_EN' using process `$paramod\ff32_ram\ADDR_WIDTH=5.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:100$2792'.
+ created $dff cell `$procdff$16852' with positive edge clock.
+Creating register for signal `$paramod\ff32_ram\ADDR_WIDTH=9.\dout' using process `$paramod\ff32_ram\ADDR_WIDTH=9.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:114$2779'.
+ created $dff cell `$procdff$16853' with positive edge clock.
+Creating register for signal `$paramod\ff32_ram\ADDR_WIDTH=9.$memwr$\ram0$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:103$2762_ADDR' using process `$paramod\ff32_ram\ADDR_WIDTH=9.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:100$2766'.
+ created $dff cell `$procdff$16854' with positive edge clock.
+Creating register for signal `$paramod\ff32_ram\ADDR_WIDTH=9.$memwr$\ram0$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:103$2762_DATA' using process `$paramod\ff32_ram\ADDR_WIDTH=9.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:100$2766'.
+ created $dff cell `$procdff$16855' with positive edge clock.
+Creating register for signal `$paramod\ff32_ram\ADDR_WIDTH=9.$memwr$\ram0$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:103$2762_EN' using process `$paramod\ff32_ram\ADDR_WIDTH=9.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:100$2766'.
+ created $dff cell `$procdff$16856' with positive edge clock.
+Creating register for signal `$paramod\ff32_ram\ADDR_WIDTH=9.$memwr$\ram1$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:105$2763_ADDR' using process `$paramod\ff32_ram\ADDR_WIDTH=9.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:100$2766'.
+ created $dff cell `$procdff$16857' with positive edge clock.
+Creating register for signal `$paramod\ff32_ram\ADDR_WIDTH=9.$memwr$\ram1$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:105$2763_DATA' using process `$paramod\ff32_ram\ADDR_WIDTH=9.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:100$2766'.
+ created $dff cell `$procdff$16858' with positive edge clock.
+Creating register for signal `$paramod\ff32_ram\ADDR_WIDTH=9.$memwr$\ram1$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:105$2763_EN' using process `$paramod\ff32_ram\ADDR_WIDTH=9.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:100$2766'.
+ created $dff cell `$procdff$16859' with positive edge clock.
+Creating register for signal `$paramod\ff32_ram\ADDR_WIDTH=9.$memwr$\ram2$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:107$2764_ADDR' using process `$paramod\ff32_ram\ADDR_WIDTH=9.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:100$2766'.
+ created $dff cell `$procdff$16860' with positive edge clock.
+Creating register for signal `$paramod\ff32_ram\ADDR_WIDTH=9.$memwr$\ram2$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:107$2764_DATA' using process `$paramod\ff32_ram\ADDR_WIDTH=9.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:100$2766'.
+ created $dff cell `$procdff$16861' with positive edge clock.
+Creating register for signal `$paramod\ff32_ram\ADDR_WIDTH=9.$memwr$\ram2$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:107$2764_EN' using process `$paramod\ff32_ram\ADDR_WIDTH=9.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:100$2766'.
+ created $dff cell `$procdff$16862' with positive edge clock.
+Creating register for signal `$paramod\ff32_ram\ADDR_WIDTH=9.$memwr$\ram3$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:109$2765_ADDR' using process `$paramod\ff32_ram\ADDR_WIDTH=9.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:100$2766'.
+ created $dff cell `$procdff$16863' with positive edge clock.
+Creating register for signal `$paramod\ff32_ram\ADDR_WIDTH=9.$memwr$\ram3$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:109$2765_DATA' using process `$paramod\ff32_ram\ADDR_WIDTH=9.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:100$2766'.
+ created $dff cell `$procdff$16864' with positive edge clock.
+Creating register for signal `$paramod\ff32_ram\ADDR_WIDTH=9.$memwr$\ram3$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:109$2765_EN' using process `$paramod\ff32_ram\ADDR_WIDTH=9.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:100$2766'.
+ created $dff cell `$procdff$16865' with positive edge clock.
+Creating register for signal `$paramod\mem_ff_wb\MEM_WORDS=512.\wb_ack_o' using process `$paramod\mem_ff_wb\MEM_WORDS=512.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:43$1931'.
+ created $dff cell `$procdff$16866' with positive edge clock.
+Creating register for signal `$paramod\mem_ff_wb\MEM_WORDS=512.\wb_ack_read' using process `$paramod\mem_ff_wb\MEM_WORDS=512.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:43$1931'.
+ created $dff cell `$procdff$16867' with positive edge clock.
+Creating register for signal `$paramod\pinmux\NUM_INPUTS=1\NUM_OUTPUTS=25\NUM_GPIOS=32.\wb_ack_o' using process `$paramod\pinmux\NUM_INPUTS=1\NUM_OUTPUTS=25\NUM_GPIOS=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/pinmux.v:71$1818'.
+ created $adff cell `$procdff$16868' with positive edge clock and positive level reset.
+Creating register for signal `$paramod\pinmux\NUM_INPUTS=1\NUM_OUTPUTS=25\NUM_GPIOS=32.\wb_dat_o' using process `$paramod\pinmux\NUM_INPUTS=1\NUM_OUTPUTS=25\NUM_GPIOS=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/pinmux.v:71$1818'.
+ created $adff cell `$procdff$16869' with positive edge clock and positive level reset.
+Creating register for signal `$paramod\pinmux\NUM_INPUTS=1\NUM_OUTPUTS=25\NUM_GPIOS=32.\i' using process `$paramod\pinmux\NUM_INPUTS=1\NUM_OUTPUTS=25\NUM_GPIOS=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/pinmux.v:71$1818'.
+ created $adff cell `$procdff$16870' with positive edge clock and positive level reset.
+Creating register for signal `$paramod\pinmux\NUM_INPUTS=1\NUM_OUTPUTS=25\NUM_GPIOS=32.\reg_mux_in[0]' using process `$paramod\pinmux\NUM_INPUTS=1\NUM_OUTPUTS=25\NUM_GPIOS=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/pinmux.v:71$1818'.
+ created $adff cell `$procdff$16871' with positive edge clock and positive level reset.
+Creating register for signal `$paramod\pinmux\NUM_INPUTS=1\NUM_OUTPUTS=25\NUM_GPIOS=32.\reg_mux_out[0]' using process `$paramod\pinmux\NUM_INPUTS=1\NUM_OUTPUTS=25\NUM_GPIOS=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/pinmux.v:71$1818'.
+ created $adff cell `$procdff$16872' with positive edge clock and positive level reset.
+Creating register for signal `$paramod\pinmux\NUM_INPUTS=1\NUM_OUTPUTS=25\NUM_GPIOS=32.\reg_mux_out[1]' using process `$paramod\pinmux\NUM_INPUTS=1\NUM_OUTPUTS=25\NUM_GPIOS=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/pinmux.v:71$1818'.
+ created $adff cell `$procdff$16873' with positive edge clock and positive level reset.
+Creating register for signal `$paramod\pinmux\NUM_INPUTS=1\NUM_OUTPUTS=25\NUM_GPIOS=32.\reg_mux_out[2]' using process `$paramod\pinmux\NUM_INPUTS=1\NUM_OUTPUTS=25\NUM_GPIOS=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/pinmux.v:71$1818'.
+ created $adff cell `$procdff$16874' with positive edge clock and positive level reset.
+Creating register for signal `$paramod\pinmux\NUM_INPUTS=1\NUM_OUTPUTS=25\NUM_GPIOS=32.\reg_mux_out[3]' using process `$paramod\pinmux\NUM_INPUTS=1\NUM_OUTPUTS=25\NUM_GPIOS=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/pinmux.v:71$1818'.
+ created $adff cell `$procdff$16875' with positive edge clock and positive level reset.
+Creating register for signal `$paramod\pinmux\NUM_INPUTS=1\NUM_OUTPUTS=25\NUM_GPIOS=32.\reg_mux_out[4]' using process `$paramod\pinmux\NUM_INPUTS=1\NUM_OUTPUTS=25\NUM_GPIOS=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/pinmux.v:71$1818'.
+ created $adff cell `$procdff$16876' with positive edge clock and positive level reset.
+Creating register for signal `$paramod\pinmux\NUM_INPUTS=1\NUM_OUTPUTS=25\NUM_GPIOS=32.\reg_mux_out[5]' using process `$paramod\pinmux\NUM_INPUTS=1\NUM_OUTPUTS=25\NUM_GPIOS=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/pinmux.v:71$1818'.
+ created $adff cell `$procdff$16877' with positive edge clock and positive level reset.
+Creating register for signal `$paramod\pinmux\NUM_INPUTS=1\NUM_OUTPUTS=25\NUM_GPIOS=32.\reg_mux_out[6]' using process `$paramod\pinmux\NUM_INPUTS=1\NUM_OUTPUTS=25\NUM_GPIOS=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/pinmux.v:71$1818'.
+ created $adff cell `$procdff$16878' with positive edge clock and positive level reset.
+Creating register for signal `$paramod\pinmux\NUM_INPUTS=1\NUM_OUTPUTS=25\NUM_GPIOS=32.\reg_mux_out[7]' using process `$paramod\pinmux\NUM_INPUTS=1\NUM_OUTPUTS=25\NUM_GPIOS=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/pinmux.v:71$1818'.
+ created $adff cell `$procdff$16879' with positive edge clock and positive level reset.
+Creating register for signal `$paramod\pinmux\NUM_INPUTS=1\NUM_OUTPUTS=25\NUM_GPIOS=32.\reg_mux_out[8]' using process `$paramod\pinmux\NUM_INPUTS=1\NUM_OUTPUTS=25\NUM_GPIOS=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/pinmux.v:71$1818'.
+ created $adff cell `$procdff$16880' with positive edge clock and positive level reset.
+Creating register for signal `$paramod\pinmux\NUM_INPUTS=1\NUM_OUTPUTS=25\NUM_GPIOS=32.\reg_mux_out[9]' using process `$paramod\pinmux\NUM_INPUTS=1\NUM_OUTPUTS=25\NUM_GPIOS=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/pinmux.v:71$1818'.
+ created $adff cell `$procdff$16881' with positive edge clock and positive level reset.
+Creating register for signal `$paramod\pinmux\NUM_INPUTS=1\NUM_OUTPUTS=25\NUM_GPIOS=32.\reg_mux_out[10]' using process `$paramod\pinmux\NUM_INPUTS=1\NUM_OUTPUTS=25\NUM_GPIOS=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/pinmux.v:71$1818'.
+ created $adff cell `$procdff$16882' with positive edge clock and positive level reset.
+Creating register for signal `$paramod\pinmux\NUM_INPUTS=1\NUM_OUTPUTS=25\NUM_GPIOS=32.\reg_mux_out[11]' using process `$paramod\pinmux\NUM_INPUTS=1\NUM_OUTPUTS=25\NUM_GPIOS=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/pinmux.v:71$1818'.
+ created $adff cell `$procdff$16883' with positive edge clock and positive level reset.
+Creating register for signal `$paramod\pinmux\NUM_INPUTS=1\NUM_OUTPUTS=25\NUM_GPIOS=32.\reg_mux_out[12]' using process `$paramod\pinmux\NUM_INPUTS=1\NUM_OUTPUTS=25\NUM_GPIOS=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/pinmux.v:71$1818'.
+ created $adff cell `$procdff$16884' with positive edge clock and positive level reset.
+Creating register for signal `$paramod\pinmux\NUM_INPUTS=1\NUM_OUTPUTS=25\NUM_GPIOS=32.\reg_mux_out[13]' using process `$paramod\pinmux\NUM_INPUTS=1\NUM_OUTPUTS=25\NUM_GPIOS=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/pinmux.v:71$1818'.
+ created $adff cell `$procdff$16885' with positive edge clock and positive level reset.
+Creating register for signal `$paramod\pinmux\NUM_INPUTS=1\NUM_OUTPUTS=25\NUM_GPIOS=32.\reg_mux_out[14]' using process `$paramod\pinmux\NUM_INPUTS=1\NUM_OUTPUTS=25\NUM_GPIOS=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/pinmux.v:71$1818'.
+ created $adff cell `$procdff$16886' with positive edge clock and positive level reset.
+Creating register for signal `$paramod\pinmux\NUM_INPUTS=1\NUM_OUTPUTS=25\NUM_GPIOS=32.\reg_mux_out[15]' using process `$paramod\pinmux\NUM_INPUTS=1\NUM_OUTPUTS=25\NUM_GPIOS=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/pinmux.v:71$1818'.
+ created $adff cell `$procdff$16887' with positive edge clock and positive level reset.
+Creating register for signal `$paramod\pinmux\NUM_INPUTS=1\NUM_OUTPUTS=25\NUM_GPIOS=32.\reg_mux_out[16]' using process `$paramod\pinmux\NUM_INPUTS=1\NUM_OUTPUTS=25\NUM_GPIOS=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/pinmux.v:71$1818'.
+ created $adff cell `$procdff$16888' with positive edge clock and positive level reset.
+Creating register for signal `$paramod\pinmux\NUM_INPUTS=1\NUM_OUTPUTS=25\NUM_GPIOS=32.\reg_mux_out[17]' using process `$paramod\pinmux\NUM_INPUTS=1\NUM_OUTPUTS=25\NUM_GPIOS=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/pinmux.v:71$1818'.
+ created $adff cell `$procdff$16889' with positive edge clock and positive level reset.
+Creating register for signal `$paramod\pinmux\NUM_INPUTS=1\NUM_OUTPUTS=25\NUM_GPIOS=32.\reg_mux_out[18]' using process `$paramod\pinmux\NUM_INPUTS=1\NUM_OUTPUTS=25\NUM_GPIOS=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/pinmux.v:71$1818'.
+ created $adff cell `$procdff$16890' with positive edge clock and positive level reset.
+Creating register for signal `$paramod\pinmux\NUM_INPUTS=1\NUM_OUTPUTS=25\NUM_GPIOS=32.\reg_mux_out[19]' using process `$paramod\pinmux\NUM_INPUTS=1\NUM_OUTPUTS=25\NUM_GPIOS=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/pinmux.v:71$1818'.
+ created $adff cell `$procdff$16891' with positive edge clock and positive level reset.
+Creating register for signal `$paramod\pinmux\NUM_INPUTS=1\NUM_OUTPUTS=25\NUM_GPIOS=32.\reg_mux_out[20]' using process `$paramod\pinmux\NUM_INPUTS=1\NUM_OUTPUTS=25\NUM_GPIOS=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/pinmux.v:71$1818'.
+ created $adff cell `$procdff$16892' with positive edge clock and positive level reset.
+Creating register for signal `$paramod\pinmux\NUM_INPUTS=1\NUM_OUTPUTS=25\NUM_GPIOS=32.\reg_mux_out[21]' using process `$paramod\pinmux\NUM_INPUTS=1\NUM_OUTPUTS=25\NUM_GPIOS=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/pinmux.v:71$1818'.
+ created $adff cell `$procdff$16893' with positive edge clock and positive level reset.
+Creating register for signal `$paramod\pinmux\NUM_INPUTS=1\NUM_OUTPUTS=25\NUM_GPIOS=32.\reg_mux_out[22]' using process `$paramod\pinmux\NUM_INPUTS=1\NUM_OUTPUTS=25\NUM_GPIOS=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/pinmux.v:71$1818'.
+ created $adff cell `$procdff$16894' with positive edge clock and positive level reset.
+Creating register for signal `$paramod\pinmux\NUM_INPUTS=1\NUM_OUTPUTS=25\NUM_GPIOS=32.\reg_mux_out[23]' using process `$paramod\pinmux\NUM_INPUTS=1\NUM_OUTPUTS=25\NUM_GPIOS=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/pinmux.v:71$1818'.
+ created $adff cell `$procdff$16895' with positive edge clock and positive level reset.
+Creating register for signal `$paramod\pinmux\NUM_INPUTS=1\NUM_OUTPUTS=25\NUM_GPIOS=32.\reg_mux_out[24]' using process `$paramod\pinmux\NUM_INPUTS=1\NUM_OUTPUTS=25\NUM_GPIOS=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/pinmux.v:71$1818'.
+ created $adff cell `$procdff$16896' with positive edge clock and positive level reset.
+Creating register for signal `$paramod\pinmux\NUM_INPUTS=1\NUM_OUTPUTS=25\NUM_GPIOS=32.\reg_mux_out[25]' using process `$paramod\pinmux\NUM_INPUTS=1\NUM_OUTPUTS=25\NUM_GPIOS=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/pinmux.v:71$1818'.
+ created $adff cell `$procdff$16897' with positive edge clock and positive level reset.
+Creating register for signal `$paramod\pinmux\NUM_INPUTS=1\NUM_OUTPUTS=25\NUM_GPIOS=32.\reg_mux_out[26]' using process `$paramod\pinmux\NUM_INPUTS=1\NUM_OUTPUTS=25\NUM_GPIOS=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/pinmux.v:71$1818'.
+ created $adff cell `$procdff$16898' with positive edge clock and positive level reset.
+Creating register for signal `$paramod\pinmux\NUM_INPUTS=1\NUM_OUTPUTS=25\NUM_GPIOS=32.\reg_mux_out[27]' using process `$paramod\pinmux\NUM_INPUTS=1\NUM_OUTPUTS=25\NUM_GPIOS=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/pinmux.v:71$1818'.
+ created $adff cell `$procdff$16899' with positive edge clock and positive level reset.
+Creating register for signal `$paramod\pinmux\NUM_INPUTS=1\NUM_OUTPUTS=25\NUM_GPIOS=32.\reg_mux_out[28]' using process `$paramod\pinmux\NUM_INPUTS=1\NUM_OUTPUTS=25\NUM_GPIOS=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/pinmux.v:71$1818'.
+ created $adff cell `$procdff$16900' with positive edge clock and positive level reset.
+Creating register for signal `$paramod\pinmux\NUM_INPUTS=1\NUM_OUTPUTS=25\NUM_GPIOS=32.\reg_mux_out[29]' using process `$paramod\pinmux\NUM_INPUTS=1\NUM_OUTPUTS=25\NUM_GPIOS=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/pinmux.v:71$1818'.
+ created $adff cell `$procdff$16901' with positive edge clock and positive level reset.
+Creating register for signal `$paramod\pinmux\NUM_INPUTS=1\NUM_OUTPUTS=25\NUM_GPIOS=32.\reg_mux_out[30]' using process `$paramod\pinmux\NUM_INPUTS=1\NUM_OUTPUTS=25\NUM_GPIOS=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/pinmux.v:71$1818'.
+ created $adff cell `$procdff$16902' with positive edge clock and positive level reset.
+Creating register for signal `$paramod\pinmux\NUM_INPUTS=1\NUM_OUTPUTS=25\NUM_GPIOS=32.\reg_mux_out[31]' using process `$paramod\pinmux\NUM_INPUTS=1\NUM_OUTPUTS=25\NUM_GPIOS=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/pinmux.v:71$1818'.
+ created $adff cell `$procdff$16903' with positive edge clock and positive level reset.
+Creating register for signal `$paramod\pinmux\NUM_INPUTS=1\NUM_OUTPUTS=25\NUM_GPIOS=32.$mem2reg_rd$\reg_mux_in$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/pinmux.v:88$1807_ADDR' using process `$paramod\pinmux\NUM_INPUTS=1\NUM_OUTPUTS=25\NUM_GPIOS=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/pinmux.v:71$1818'.
+ created $adff cell `$procdff$16904' with positive edge clock and positive level reset.
+Creating register for signal `$paramod\pinmux\NUM_INPUTS=1\NUM_OUTPUTS=25\NUM_GPIOS=32.$mem2reg_rd$\reg_mux_in$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/pinmux.v:88$1807_DATA' using process `$paramod\pinmux\NUM_INPUTS=1\NUM_OUTPUTS=25\NUM_GPIOS=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/pinmux.v:71$1818'.
+ created $adff cell `$procdff$16905' with positive edge clock and positive level reset.
+Creating register for signal `$paramod\pinmux\NUM_INPUTS=1\NUM_OUTPUTS=25\NUM_GPIOS=32.$mem2reg_wr$\reg_mux_in$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/pinmux.v:90$1808_ADDR' using process `$paramod\pinmux\NUM_INPUTS=1\NUM_OUTPUTS=25\NUM_GPIOS=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/pinmux.v:71$1818'.
+ created $adff cell `$procdff$16906' with positive edge clock and positive level reset.
+Creating register for signal `$paramod\pinmux\NUM_INPUTS=1\NUM_OUTPUTS=25\NUM_GPIOS=32.$mem2reg_wr$\reg_mux_in$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/pinmux.v:90$1808_DATA' using process `$paramod\pinmux\NUM_INPUTS=1\NUM_OUTPUTS=25\NUM_GPIOS=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/pinmux.v:71$1818'.
+ created $adff cell `$procdff$16907' with positive edge clock and positive level reset.
+Creating register for signal `$paramod\pinmux\NUM_INPUTS=1\NUM_OUTPUTS=25\NUM_GPIOS=32.$mem2reg_rd$\reg_mux_out$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/pinmux.v:94$1809_ADDR' using process `$paramod\pinmux\NUM_INPUTS=1\NUM_OUTPUTS=25\NUM_GPIOS=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/pinmux.v:71$1818'.
+ created $adff cell `$procdff$16908' with positive edge clock and positive level reset.
+Creating register for signal `$paramod\pinmux\NUM_INPUTS=1\NUM_OUTPUTS=25\NUM_GPIOS=32.$mem2reg_rd$\reg_mux_out$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/pinmux.v:94$1809_DATA' using process `$paramod\pinmux\NUM_INPUTS=1\NUM_OUTPUTS=25\NUM_GPIOS=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/pinmux.v:71$1818'.
+ created $adff cell `$procdff$16909' with positive edge clock and positive level reset.
+Creating register for signal `$paramod\pinmux\NUM_INPUTS=1\NUM_OUTPUTS=25\NUM_GPIOS=32.$mem2reg_wr$\reg_mux_out$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/pinmux.v:96$1810_ADDR' using process `$paramod\pinmux\NUM_INPUTS=1\NUM_OUTPUTS=25\NUM_GPIOS=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/pinmux.v:71$1818'.
+ created $adff cell `$procdff$16910' with positive edge clock and positive level reset.
+Creating register for signal `$paramod\pinmux\NUM_INPUTS=1\NUM_OUTPUTS=25\NUM_GPIOS=32.$mem2reg_wr$\reg_mux_out$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/pinmux.v:96$1810_DATA' using process `$paramod\pinmux\NUM_INPUTS=1\NUM_OUTPUTS=25\NUM_GPIOS=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/pinmux.v:71$1818'.
+ created $adff cell `$procdff$16911' with positive edge clock and positive level reset.
+Creating register for signal `\pcpi_flexio.\out_rd_en' using process `\pcpi_flexio.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/pcpi_flexio.v:152$258'.
+ created $adff cell `$procdff$16912' with positive edge clock and negative level reset.
+Creating register for signal `\pcpi_flexio.\out_shift_reg' using process `\pcpi_flexio.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/pcpi_flexio.v:152$258'.
+ created $adff cell `$procdff$16913' with positive edge clock and negative level reset.
+Creating register for signal `\pcpi_flexio.\out_shift_cnt' using process `\pcpi_flexio.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/pcpi_flexio.v:152$258'.
+ created $adff cell `$procdff$16914' with positive edge clock and negative level reset.
+Creating register for signal `\pcpi_flexio.\clk_div_cnt' using process `\pcpi_flexio.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/pcpi_flexio.v:135$254'.
+ created $adff cell `$procdff$16915' with positive edge clock and negative level reset.
+Creating register for signal `\pcpi_flexio.\clk_en' using process `\pcpi_flexio.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/pcpi_flexio.v:135$254'.
+ created $adff cell `$procdff$16916' with positive edge clock and negative level reset.
+Creating register for signal `\pcpi_flexio.\pcpi_wait' using process `\pcpi_flexio.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/pcpi_flexio.v:96$250'.
+ created $adff cell `$procdff$16917' with positive edge clock and negative level reset.
+Creating register for signal `\pcpi_flexio.\pcpi_ready' using process `\pcpi_flexio.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/pcpi_flexio.v:96$250'.
+ created $adff cell `$procdff$16918' with positive edge clock and negative level reset.
+Creating register for signal `\pcpi_flexio.\cfg_out_bit_mask' using process `\pcpi_flexio.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/pcpi_flexio.v:96$250'.
+ created $adff cell `$procdff$16919' with positive edge clock and negative level reset.
+Creating register for signal `\pcpi_flexio.\cfg_bits_per_clock' using process `\pcpi_flexio.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/pcpi_flexio.v:96$250'.
+ created $adff cell `$procdff$16920' with positive edge clock and negative level reset.
+Creating register for signal `\pcpi_flexio.\cfg_clk_div' using process `\pcpi_flexio.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/pcpi_flexio.v:96$250'.
+ created $adff cell `$procdff$16921' with positive edge clock and negative level reset.
+Creating register for signal `\pcpi_flexio.\out_wr_en' using process `\pcpi_flexio.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/pcpi_flexio.v:96$250'.
+ created $adff cell `$procdff$16922' with positive edge clock and negative level reset.
+Creating register for signal `\pcpi_flexio.\out_wr_data' using process `\pcpi_flexio.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/pcpi_flexio.v:96$250'.
+ created $adff cell `$procdff$16923' with positive edge clock and negative level reset.
+Creating register for signal `\mgmt_soc_regs.$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/rv_core.v:286$25_ADDR' using process `\mgmt_soc_regs.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/rv_core.v:285$26'.
+ created $dff cell `$procdff$16924' with positive edge clock.
+Creating register for signal `\mgmt_soc_regs.$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/rv_core.v:286$25_DATA' using process `\mgmt_soc_regs.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/rv_core.v:285$26'.
+ created $dff cell `$procdff$16925' with positive edge clock.
+Creating register for signal `\mgmt_soc_regs.$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/rv_core.v:286$25_EN' using process `\mgmt_soc_regs.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/rv_core.v:285$26'.
+ created $dff cell `$procdff$16926' with positive edge clock.
+Creating register for signal `\softshell_top.\reset_pipe' using process `\softshell_top.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/softshell_top.v:143$2'.
+ created $adff cell `$procdff$16927' with positive edge clock and positive level reset.
+
+23.2.9. Executing PROC_CLEAN pass (remove empty switches from decision trees).
+Removing empty process `$paramod$922eeecdf93ea4da89c0f9a13b613ec8c6a19ae5\arbiter.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/verilog-wishbone/rtl/arbiter.v:77$2761'.
+Removing empty process `$paramod$922eeecdf93ea4da89c0f9a13b613ec8c6a19ae5\arbiter.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/verilog-wishbone/rtl/arbiter.v:56$2760'.
+Removing empty process `$paramod$922eeecdf93ea4da89c0f9a13b613ec8c6a19ae5\arbiter.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/verilog-wishbone/rtl/arbiter.v:55$2759'.
+Removing empty process `$paramod$922eeecdf93ea4da89c0f9a13b613ec8c6a19ae5\arbiter.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/verilog-wishbone/rtl/arbiter.v:54$2758'.
+Found and cleaned up 1 empty switch in `$paramod$922eeecdf93ea4da89c0f9a13b613ec8c6a19ae5\arbiter.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/verilog-wishbone/rtl/arbiter.v:139$2757'.
+Removing empty process `$paramod$922eeecdf93ea4da89c0f9a13b613ec8c6a19ae5\arbiter.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/verilog-wishbone/rtl/arbiter.v:139$2757'.
+Found and cleaned up 4 empty switches in `$paramod$922eeecdf93ea4da89c0f9a13b613ec8c6a19ae5\arbiter.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/verilog-wishbone/rtl/arbiter.v:94$2746'.
+Removing empty process `$paramod$922eeecdf93ea4da89c0f9a13b613ec8c6a19ae5\arbiter.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/verilog-wishbone/rtl/arbiter.v:94$2746'.
+Found and cleaned up 4 empty switches in `$paramod$02c0b2a9118806de1d82e68e563b733cce432378\picorv32_wb.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:2994$2744'.
+Removing empty process `$paramod$02c0b2a9118806de1d82e68e563b733cce432378\picorv32_wb.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:2994$2744'.
+Found and cleaned up 4 empty switches in `$paramod$e50444e694c9a9e823a24aefd7b9b454c7f28d7e\picorv32_wb.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:2994$2739'.
+Removing empty process `$paramod$e50444e694c9a9e823a24aefd7b9b454c7f28d7e\picorv32_wb.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:2994$2739'.
+Found and cleaned up 4 empty switches in `$paramod$d7c2e1f9a7f32b8e9c28fc8646c0275848e63526\picorv32_wb.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:2994$2734'.
+Removing empty process `$paramod$d7c2e1f9a7f32b8e9c28fc8646c0275848e63526\picorv32_wb.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:2994$2734'.
+Found and cleaned up 1 empty switch in `$paramod\mem_ff_wb\MEM_WORDS=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:43$2721'.
+Removing empty process `$paramod\mem_ff_wb\MEM_WORDS=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:43$2721'.
+Found and cleaned up 10 empty switches in `$paramod$b48b6478f53991418334d339eb44ca404341ca26\gpio.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/gpio32_wb.v:102$2710'.
+Removing empty process `$paramod$b48b6478f53991418334d339eb44ca404341ca26\gpio.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/gpio32_wb.v:102$2710'.
+Removing empty process `$paramod\afifo\LGFIFO=2\WIDTH=32\OPT_REGISTER_READS=1'0.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:230$2033'.
+Removing empty process `$paramod\afifo\LGFIFO=2\WIDTH=32\OPT_REGISTER_READS=1'0.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:227$2032'.
+Removing empty process `$paramod\afifo\LGFIFO=2\WIDTH=32\OPT_REGISTER_READS=1'0.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:224$2031'.
+Removing empty process `$paramod\afifo\LGFIFO=2\WIDTH=32\OPT_REGISTER_READS=1'0.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:201$2029'.
+Removing empty process `$paramod\afifo\LGFIFO=2\WIDTH=32\OPT_REGISTER_READS=1'0.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:198$2026'.
+Removing empty process `$paramod\afifo\LGFIFO=2\WIDTH=32\OPT_REGISTER_READS=1'0.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:182$2024'.
+Removing empty process `$paramod\afifo\LGFIFO=2\WIDTH=32\OPT_REGISTER_READS=1'0.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:173$2022'.
+Removing empty process `$paramod\afifo\LGFIFO=2\WIDTH=32\OPT_REGISTER_READS=1'0.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:159$2020'.
+Found and cleaned up 1 empty switch in `$paramod\afifo\LGFIFO=2\WIDTH=32\OPT_REGISTER_READS=1'0.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:145$2014'.
+Removing empty process `$paramod\afifo\LGFIFO=2\WIDTH=32\OPT_REGISTER_READS=1'0.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:145$2014'.
+Found and cleaned up 1 empty switch in `$paramod\afifo\LGFIFO=2\WIDTH=32\OPT_REGISTER_READS=1'0.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:137$2007'.
+Removing empty process `$paramod\afifo\LGFIFO=2\WIDTH=32\OPT_REGISTER_READS=1'0.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:137$2007'.
+Found and cleaned up 1 empty switch in `$paramod\afifo\LGFIFO=2\WIDTH=32\OPT_REGISTER_READS=1'0.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:123$2001'.
+Removing empty process `$paramod\afifo\LGFIFO=2\WIDTH=32\OPT_REGISTER_READS=1'0.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:123$2001'.
+Found and cleaned up 61 empty switches in `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1397$4672'.
+Removing empty process `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1397$4672'.
+Removing empty process `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1382$4658'.
+Found and cleaned up 2 empty switches in `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1304$4644'.
+Removing empty process `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1304$4644'.
+Found and cleaned up 2 empty switches in `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1290$4639'.
+Removing empty process `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1290$4639'.
+Removing empty process `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1288$4638'.
+Found and cleaned up 2 empty switches in `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1244$4616'.
+Removing empty process `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1244$4616'.
+Found and cleaned up 8 empty switches in `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1181$4604'.
+Removing empty process `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1181$4604'.
+Found and cleaned up 22 empty switches in `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$4344'.
+Removing empty process `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$4344'.
+Found and cleaned up 3 empty switches in `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:807$4342'.
+Removing empty process `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:807$4342'.
+Found and cleaned up 5 empty switches in `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:776$4338'.
+Removing empty process `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:776$4338'.
+Found and cleaned up 47 empty switches in `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:700$4337'.
+Removing empty process `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:700$4337'.
+Found and cleaned up 16 empty switches in `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:565$4313'.
+Removing empty process `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:565$4313'.
+Removing empty process `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1234$4852'.
+Found and cleaned up 19 empty switches in `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:430$4275'.
+Removing empty process `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:430$4275'.
+Found and cleaned up 3 empty switches in `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:401$4272'.
+Removing empty process `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:401$4272'.
+Found and cleaned up 2 empty switches in `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:390$4267'.
+Removing empty process `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:390$4267'.
+Found and cleaned up 1 empty switch in `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:325$4193'.
+Removing empty process `$paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:325$4193'.
+Found and cleaned up 4 empty switches in `\spimemio_xfer.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/spimemio.v:697$748'.
+Removing empty process `spimemio_xfer.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/spimemio.v:697$748'.
+Found and cleaned up 5 empty switches in `\spimemio_xfer.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/spimemio.v:609$724'.
+Removing empty process `spimemio_xfer.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/spimemio.v:609$724'.
+Removing empty process `spimemio_xfer.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/spimemio.v:598$715'.
+Found and cleaned up 25 empty switches in `\spimemio.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/spimemio.v:369$694'.
+Removing empty process `spimemio.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/spimemio.v:369$694'.
+Removing empty process `spimemio.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/spimemio.v:295$630'.
+Found and cleaned up 5 empty switches in `\spimemio.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/spimemio.v:243$626'.
+Removing empty process `spimemio.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/spimemio.v:243$626'.
+Found and cleaned up 5 empty switches in `\simpleuart.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/simpleuart.v:194$597'.
+Removing empty process `simpleuart.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/simpleuart.v:194$597'.
+Found and cleaned up 7 empty switches in `\simpleuart.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/simpleuart.v:151$587'.
+Removing empty process `simpleuart.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/simpleuart.v:151$587'.
+Found and cleaned up 6 empty switches in `\simpleuart.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/simpleuart.v:138$585'.
+Removing empty process `simpleuart.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/simpleuart.v:138$585'.
+Found and cleaned up 61 empty switches in `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1397$3989'.
+Removing empty process `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1397$3989'.
+Removing empty process `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1382$3975'.
+Found and cleaned up 2 empty switches in `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1304$3961'.
+Removing empty process `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1304$3961'.
+Found and cleaned up 2 empty switches in `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1290$3956'.
+Removing empty process `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1290$3956'.
+Removing empty process `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1288$3955'.
+Found and cleaned up 2 empty switches in `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1244$3933'.
+Removing empty process `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1244$3933'.
+Found and cleaned up 8 empty switches in `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1181$3921'.
+Removing empty process `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1181$3921'.
+Found and cleaned up 22 empty switches in `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$3661'.
+Removing empty process `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$3661'.
+Found and cleaned up 3 empty switches in `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:807$3659'.
+Removing empty process `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:807$3659'.
+Found and cleaned up 5 empty switches in `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:776$3655'.
+Removing empty process `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:776$3655'.
+Found and cleaned up 47 empty switches in `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:700$3654'.
+Removing empty process `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:700$3654'.
+Found and cleaned up 16 empty switches in `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:565$3630'.
+Removing empty process `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:565$3630'.
+Removing empty process `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1234$4169'.
+Found and cleaned up 19 empty switches in `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:430$3592'.
+Removing empty process `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:430$3592'.
+Found and cleaned up 3 empty switches in `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:401$3589'.
+Removing empty process `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:401$3589'.
+Found and cleaned up 2 empty switches in `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:390$3584'.
+Removing empty process `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:390$3584'.
+Found and cleaned up 1 empty switch in `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:325$3510'.
+Removing empty process `$paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:325$3510'.
+Found and cleaned up 61 empty switches in `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1397$3306'.
+Removing empty process `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1397$3306'.
+Removing empty process `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1382$3292'.
+Found and cleaned up 2 empty switches in `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1304$3278'.
+Removing empty process `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1304$3278'.
+Found and cleaned up 2 empty switches in `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1290$3273'.
+Removing empty process `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1290$3273'.
+Removing empty process `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1288$3272'.
+Found and cleaned up 2 empty switches in `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1244$3250'.
+Removing empty process `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1244$3250'.
+Found and cleaned up 8 empty switches in `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1181$3238'.
+Removing empty process `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1181$3238'.
+Found and cleaned up 22 empty switches in `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$2978'.
+Removing empty process `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:856$2978'.
+Found and cleaned up 3 empty switches in `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:807$2976'.
+Removing empty process `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:807$2976'.
+Found and cleaned up 5 empty switches in `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:776$2972'.
+Removing empty process `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:776$2972'.
+Found and cleaned up 47 empty switches in `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:700$2971'.
+Removing empty process `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:700$2971'.
+Found and cleaned up 16 empty switches in `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:565$2947'.
+Removing empty process `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:565$2947'.
+Removing empty process `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1234$3486'.
+Found and cleaned up 19 empty switches in `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:430$2909'.
+Removing empty process `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:430$2909'.
+Found and cleaned up 3 empty switches in `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:401$2906'.
+Removing empty process `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:401$2906'.
+Found and cleaned up 2 empty switches in `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:390$2901'.
+Removing empty process `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:390$2901'.
+Found and cleaned up 1 empty switch in `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:325$2827'.
+Removing empty process `$paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:325$2827'.
+Found and cleaned up 1 empty switch in `$paramod\ff32_ram\ADDR_WIDTH=5.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:114$2805'.
+Removing empty process `$paramod\ff32_ram\ADDR_WIDTH=5.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:114$2805'.
+Found and cleaned up 5 empty switches in `$paramod\ff32_ram\ADDR_WIDTH=5.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:100$2792'.
+Removing empty process `$paramod\ff32_ram\ADDR_WIDTH=5.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:100$2792'.
+Found and cleaned up 1 empty switch in `$paramod\ff32_ram\ADDR_WIDTH=9.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:114$2779'.
+Removing empty process `$paramod\ff32_ram\ADDR_WIDTH=9.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:114$2779'.
+Found and cleaned up 5 empty switches in `$paramod\ff32_ram\ADDR_WIDTH=9.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:100$2766'.
+Removing empty process `$paramod\ff32_ram\ADDR_WIDTH=9.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:100$2766'.
+Found and cleaned up 1 empty switch in `$paramod\mem_ff_wb\MEM_WORDS=512.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:43$1931'.
+Removing empty process `$paramod\mem_ff_wb\MEM_WORDS=512.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:43$1931'.
+Found and cleaned up 9 empty switches in `$paramod\pinmux\NUM_INPUTS=1\NUM_OUTPUTS=25\NUM_GPIOS=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/pinmux.v:71$1818'.
+Removing empty process `$paramod\pinmux\NUM_INPUTS=1\NUM_OUTPUTS=25\NUM_GPIOS=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/pinmux.v:71$1818'.
+Found and cleaned up 4 empty switches in `\pcpi_flexio.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/pcpi_flexio.v:152$258'.
+Removing empty process `pcpi_flexio.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/pcpi_flexio.v:152$258'.
+Found and cleaned up 1 empty switch in `\pcpi_flexio.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/pcpi_flexio.v:135$254'.
+Removing empty process `pcpi_flexio.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/pcpi_flexio.v:135$254'.
+Found and cleaned up 4 empty switches in `\pcpi_flexio.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/pcpi_flexio.v:96$250'.
+Removing empty process `pcpi_flexio.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/pcpi_flexio.v:96$250'.
+Found and cleaned up 1 empty switch in `\mgmt_soc_regs.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/rv_core.v:285$26'.
+Removing empty process `mgmt_soc_regs.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/rv_core.v:285$26'.
+Removing empty process `softshell_top.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/softshell_top.v:0$22'.
+Removing empty process `softshell_top.$proc$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/softshell_top.v:143$2'.
+Cleaned up 699 empty switches.
+
+23.3. Executing FLATTEN pass (flatten design).
+Deleting now unused module $paramod\rv_core\MEM_WORDS=32\PROGADDR_RESET=809697280\CORE_ID=2.
+Deleting now unused module $paramod$922eeecdf93ea4da89c0f9a13b613ec8c6a19ae5\arbiter.
+Deleting now unused module $paramod$02c0b2a9118806de1d82e68e563b733cce432378\picorv32_wb.
+Deleting now unused module $paramod$e50444e694c9a9e823a24aefd7b9b454c7f28d7e\picorv32_wb.
+Deleting now unused module $paramod$d7c2e1f9a7f32b8e9c28fc8646c0275848e63526\picorv32_wb.
+Deleting now unused module $paramod\mem_ff_wb\MEM_WORDS=32.
+Deleting now unused module $paramod\priority_encoder\WIDTH=2\LSB_PRIORITY=1212761928.
+Deleting now unused module $paramod$b48b6478f53991418334d339eb44ca404341ca26\gpio.
+Deleting now unused module $paramod\priority_encoder\WIDTH=4\LSB_PRIORITY=1212761928.
+Deleting now unused module $paramod\afifo\LGFIFO=2\WIDTH=32\OPT_REGISTER_READS=1'0.
+Deleting now unused module $paramod$3c3f095f4f58afd05fbda65860ecb89a6c122270\picorv32.
+Deleting now unused module gpio32_wb.
+Deleting now unused module spimemio_xfer.
+Deleting now unused module spimemio.
+Deleting now unused module spimemio_wb.
+Deleting now unused module simpleuart.
+Deleting now unused module $paramod$36d92ab60132cb30ab332fec9d990603dc7a1797\picorv32.
+Deleting now unused module $paramod$635cbf1e6a89400232edb785f79f8237e257777c\picorv32.
+Deleting now unused module $paramod\ff32_ram\ADDR_WIDTH=5.
+Deleting now unused module wb_mux_5.
+Deleting now unused module wb_mux_3.
+Deleting now unused module $paramod\ff32_ram\ADDR_WIDTH=9.
+Deleting now unused module $paramod\mem_ff_wb\MEM_WORDS=512.
+Deleting now unused module $paramod\pinmux\NUM_INPUTS=1\NUM_OUTPUTS=25\NUM_GPIOS=32.
+Deleting now unused module $paramod\simpleuart_wb\BASE_ADR=813826048.
+Deleting now unused module $paramod$dfdc56f61c29f5320a5a986f0ea01fc1dee9752c\wb_arbiter_4.
+Deleting now unused module pcpi_flexio.
+Deleting now unused module $paramod\rv_core\MEM_WORDS=32\PROGADDR_RESET=809566208\CORE_ID=0.
+Deleting now unused module mgmt_soc_regs.
+Deleting now unused module $paramod\rv_core\MEM_WORDS=32\PROGADDR_RESET=809631744\CORE_ID=1.
+Deleting now unused module softshell_top.
+<suppressed ~43 debug messages>
+
+23.4. Executing OPT_EXPR pass (perform const folding).
+Optimizing module user_proj_example.
+<suppressed ~1801 debug messages>
+
+23.5. Executing OPT_CLEAN pass (remove unused cells and wires).
+Finding unused cells or wires in module \user_proj_example..
+Removed 984 unused cells and 6817 unused wires.
+<suppressed ~1229 debug messages>
+
+23.6. Executing CHECK pass (checking for obvious problems).
+checking module user_proj_example..
+Warning: Wire user_proj_example.\softshell.uart0.simpleuart_reg_cfg_do [31] is used but has no driver.
+Warning: Wire user_proj_example.\softshell.uart0.simpleuart_reg_cfg_do [30] is used but has no driver.
+Warning: Wire user_proj_example.\softshell.uart0.simpleuart_reg_cfg_do [29] is used but has no driver.
+Warning: Wire user_proj_example.\softshell.uart0.simpleuart_reg_cfg_do [28] is used but has no driver.
+Warning: Wire user_proj_example.\softshell.uart0.simpleuart_reg_cfg_do [27] is used but has no driver.
+Warning: Wire user_proj_example.\softshell.uart0.simpleuart_reg_cfg_do [26] is used but has no driver.
+Warning: Wire user_proj_example.\softshell.uart0.simpleuart_reg_cfg_do [25] is used but has no driver.
+Warning: Wire user_proj_example.\softshell.uart0.simpleuart_reg_cfg_do [24] is used but has no driver.
+Warning: Wire user_proj_example.\softshell.uart0.simpleuart_reg_cfg_do [23] is used but has no driver.
+Warning: Wire user_proj_example.\softshell.uart0.simpleuart_reg_cfg_do [22] is used but has no driver.
+Warning: Wire user_proj_example.\softshell.uart0.simpleuart_reg_cfg_do [21] is used but has no driver.
+Warning: Wire user_proj_example.\softshell.uart0.simpleuart_reg_cfg_do [20] is used but has no driver.
+Warning: Wire user_proj_example.\softshell.uart0.simpleuart_reg_cfg_do [19] is used but has no driver.
+Warning: Wire user_proj_example.\softshell.uart0.simpleuart_reg_cfg_do [18] is used but has no driver.
+Warning: Wire user_proj_example.\softshell.uart0.simpleuart_reg_cfg_do [17] is used but has no driver.
+Warning: Wire user_proj_example.\softshell.uart0.simpleuart_reg_cfg_do [16] is used but has no driver.
+Warning: Wire user_proj_example.\softshell.uart0.simpleuart_reg_cfg_do [15] is used but has no driver.
+Warning: Wire user_proj_example.\softshell.uart0.simpleuart_reg_cfg_do [14] is used but has no driver.
+Warning: Wire user_proj_example.\softshell.uart0.simpleuart_reg_cfg_do [13] is used but has no driver.
+Warning: Wire user_proj_example.\softshell.uart0.simpleuart_reg_cfg_do [12] is used but has no driver.
+Warning: Wire user_proj_example.\softshell.uart0.simpleuart_reg_cfg_do [11] is used but has no driver.
+Warning: Wire user_proj_example.\softshell.uart0.simpleuart_reg_cfg_do [10] is used but has no driver.
+Warning: Wire user_proj_example.\softshell.uart0.simpleuart_reg_cfg_do [9] is used but has no driver.
+Warning: Wire user_proj_example.\softshell.uart0.simpleuart_reg_cfg_do [8] is used but has no driver.
+Warning: Wire user_proj_example.\softshell.uart0.simpleuart_reg_cfg_do [7] is used but has no driver.
+Warning: Wire user_proj_example.\softshell.uart0.simpleuart_reg_cfg_do [6] is used but has no driver.
+Warning: Wire user_proj_example.\softshell.uart0.simpleuart_reg_cfg_do [5] is used but has no driver.
+Warning: Wire user_proj_example.\softshell.uart0.simpleuart_reg_cfg_do [4] is used but has no driver.
+Warning: Wire user_proj_example.\softshell.uart0.simpleuart_reg_cfg_do [3] is used but has no driver.
+Warning: Wire user_proj_example.\softshell.uart0.simpleuart_reg_cfg_do [2] is used but has no driver.
+Warning: Wire user_proj_example.\softshell.uart0.simpleuart_reg_cfg_do [1] is used but has no driver.
+Warning: Wire user_proj_example.\softshell.uart0.simpleuart_reg_cfg_do [0] is used but has no driver.
+found and reported 32 problems.
+
+23.7. Executing OPT pass (performing simple optimizations).
+
+23.7.1. Executing OPT_EXPR pass (perform const folding).
+Optimizing module user_proj_example.
+
+23.7.2. Executing OPT_MERGE pass (detect identical cells).
+Finding identical cells in module `\user_proj_example'.
+<suppressed ~4452 debug messages>
+Removed a total of 1484 cells.
+
+23.7.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
+Running muxtree optimizer on module \user_proj_example..
+ Creating internal representation of mux trees.
+ Evaluating internal representation of mux trees.
+ Analyzing evaluation results.
+ dead port 1/2 on $mux $flatten\softshell.\arbiter.\arb_inst.$procmux$5031.
+ dead port 1/2 on $mux $flatten\softshell.\arbiter.\arb_inst.$procmux$5049.
+ dead port 2/2 on $mux $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$8338.
+ dead port 2/2 on $mux $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$8345.
+ dead port 1/4 on $pmux $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$8371.
+ dead port 2/4 on $pmux $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$8371.
+ dead port 4/4 on $pmux $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$8371.
+ dead port 1/4 on $pmux $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$8376.
+ dead port 2/4 on $pmux $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$8376.
+ dead port 4/4 on $pmux $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$8376.
+ dead port 1/2 on $mux $flatten\softshell.\arbiter.\arb_inst.$procmux$5058.
+ dead port 1/2 on $mux $flatten\softshell.\arbiter.\arb_inst.$procmux$5070.
+ dead port 1/2 on $mux $flatten\softshell.\arbiter.\arb_inst.$procmux$5076.
+ dead port 1/2 on $mux $flatten\softshell.\arbiter.\arb_inst.$procmux$5082.
+ dead port 4/8 on $pmux $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10170.
+ dead port 5/8 on $pmux $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10170.
+ dead port 1/4 on $pmux $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10238.
+ dead port 1/3 on $pmux $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10253.
+ dead port 2/12 on $pmux $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10257.
+ dead port 7/12 on $pmux $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10257.
+ dead port 8/12 on $pmux $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10257.
+ dead port 1/4 on $pmux $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10441.
+ dead port 1/3 on $pmux $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10453.
+ dead port 2/12 on $pmux $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10457.
+ dead port 7/12 on $pmux $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10457.
+ dead port 8/12 on $pmux $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10457.
+ dead port 2/11 on $pmux $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10641.
+ dead port 7/11 on $pmux $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10641.
+ dead port 8/11 on $pmux $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10641.
+ dead port 4/8 on $pmux $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10691.
+ dead port 5/8 on $pmux $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10691.
+ dead port 2/2 on $mux $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10829.
+ dead port 2/2 on $mux $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10838.
+ dead port 2/2 on $mux $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$5519.
+ dead port 2/2 on $mux $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$5529.
+ dead port 2/2 on $mux $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$5531.
+ dead port 2/2 on $mux $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$5537.
+ dead port 2/2 on $mux $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$5544.
+ dead port 2/2 on $mux $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$5546.
+ dead port 2/2 on $mux $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$5552.
+ dead port 2/2 on $mux $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$5561.
+ dead port 1/2 on $mux $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$5581.
+ dead port 2/2 on $mux $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$5587.
+ dead port 1/2 on $mux $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$5590.
+ dead port 1/2 on $mux $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$5603.
+ dead port 2/2 on $mux $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$5610.
+ dead port 1/2 on $mux $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$5613.
+ dead port 1/2 on $mux $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$5626.
+ dead port 2/2 on $mux $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$5638.
+ dead port 1/2 on $mux $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$5641.
+ dead port 2/2 on $mux $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$5650.
+ dead port 1/2 on $mux $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$5653.
+ dead port 2/2 on $mux $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$5661.
+ dead port 2/2 on $mux $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$5663.
+ dead port 1/2 on $mux $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$5666.
+ dead port 1/2 on $mux $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$5680.
+ dead port 2/2 on $mux $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$5682.
+ dead port 2/2 on $mux $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$5684.
+ dead port 1/2 on $mux $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$5687.
+ dead port 2/2 on $mux $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$5700.
+ dead port 2/2 on $mux $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$5702.
+ dead port 1/2 on $mux $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$5705.
+ dead port 2/2 on $mux $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$5717.
+ dead port 1/2 on $mux $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$5720.
+ dead port 2/2 on $mux $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$5727.
+ dead port 2/2 on $mux $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$5729.
+ dead port 1/2 on $mux $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$5732.
+ dead port 2/2 on $mux $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$11984.
+ dead port 2/2 on $mux $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$11991.
+ dead port 1/2 on $mux $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$5755.
+ dead port 2/2 on $mux $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$5757.
+ dead port 2/2 on $mux $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$5759.
+ dead port 1/2 on $mux $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$5762.
+ dead port 2/2 on $mux $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$5784.
+ dead port 2/2 on $mux $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$5786.
+ dead port 1/4 on $pmux $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$12017.
+ dead port 2/4 on $pmux $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$12017.
+ dead port 4/4 on $pmux $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$12017.
+ dead port 1/4 on $pmux $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$12022.
+ dead port 2/4 on $pmux $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$12022.
+ dead port 4/4 on $pmux $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$12022.
+ dead port 2/2 on $mux $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$9165.
+ dead port 2/2 on $mux $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$9175.
+ dead port 2/2 on $mux $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$9177.
+ dead port 2/2 on $mux $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$9183.
+ dead port 2/2 on $mux $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$9190.
+ dead port 2/2 on $mux $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$9192.
+ dead port 2/2 on $mux $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$9198.
+ dead port 2/2 on $mux $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$9207.
+ dead port 1/2 on $mux $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$5789.
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+ dead port 2/12 on $pmux $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$13322.
+ dead port 7/12 on $pmux $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$13322.
+ dead port 8/12 on $pmux $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$13322.
+ dead port 2/11 on $pmux $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$13506.
+ dead port 7/11 on $pmux $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$13506.
+ dead port 8/11 on $pmux $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$13506.
+ dead port 4/8 on $pmux $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$13556.
+ dead port 5/8 on $pmux $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$13556.
+ dead port 2/2 on $mux $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$7183.
+ dead port 2/2 on $mux $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$13694.
+ dead port 2/2 on $mux $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$13703.
+ dead port 2/2 on $mux $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$7192.
+ dead port 1/2 on $mux $flatten\softshell.\arbiter.\arb_inst.$procmux$4883.
+ dead port 2/2 on $mux $flatten\softshell.\arbiter.\arb_inst.$procmux$4885.
+ dead port 1/2 on $mux $flatten\softshell.\arbiter.\arb_inst.$procmux$4891.
+ dead port 2/2 on $mux $flatten\softshell.\arbiter.\arb_inst.$procmux$4895.
+ dead port 2/2 on $mux $flatten\softshell.\arbiter.\arb_inst.$procmux$4897.
+ dead port 1/2 on $mux $flatten\softshell.\arbiter.\arb_inst.$procmux$4903.
+ dead port 2/2 on $mux $flatten\softshell.\arbiter.\arb_inst.$procmux$4909.
+ dead port 1/2 on $mux $flatten\softshell.\arbiter.\arb_inst.$procmux$4915.
+ dead port 2/2 on $mux $flatten\softshell.\arbiter.\arb_inst.$procmux$4933.
+ dead port 1/2 on $mux $flatten\softshell.\arbiter.\arb_inst.$procmux$4939.
+ dead port 2/2 on $mux $flatten\softshell.\arbiter.\arb_inst.$procmux$4944.
+ dead port 1/2 on $mux $flatten\softshell.\arbiter.\arb_inst.$procmux$4950.
+ dead port 2/2 on $mux $flatten\softshell.\arbiter.\arb_inst.$procmux$4953.
+ dead port 1/2 on $mux $flatten\softshell.\arbiter.\arb_inst.$procmux$4959.
+ dead port 2/2 on $mux $flatten\softshell.\arbiter.\arb_inst.$procmux$4971.
+ dead port 2/2 on $mux $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$14849.
+ dead port 2/2 on $mux $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$14856.
+ dead port 1/2 on $mux $flatten\softshell.\arbiter.\arb_inst.$procmux$4977.
+ dead port 1/4 on $pmux $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$14882.
+ dead port 2/4 on $pmux $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$14882.
+ dead port 4/4 on $pmux $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$14882.
+ dead port 1/4 on $pmux $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$14887.
+ dead port 2/4 on $pmux $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$14887.
+ dead port 4/4 on $pmux $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$14887.
+ dead port 2/2 on $mux $flatten\softshell.\arbiter.\arb_inst.$procmux$4980.
+ dead port 1/2 on $mux $flatten\softshell.\arbiter.\arb_inst.$procmux$4986.
+ dead port 2/2 on $mux $flatten\softshell.\arbiter.\arb_inst.$procmux$4989.
+ dead port 1/2 on $mux $flatten\softshell.\arbiter.\arb_inst.$procmux$4995.
+ dead port 2/2 on $mux $flatten\softshell.\arbiter.\arb_inst.$procmux$5007.
+ dead port 1/2 on $mux $flatten\softshell.\arbiter.\arb_inst.$procmux$5013.
+ dead port 2/2 on $mux $flatten\softshell.\flash.\spimemio.\xfer.$procmux$8485.
+ dead port 1/4 on $pmux $flatten\softshell.\flash.\spimemio.\xfer.$procmux$8487.
+ dead port 2/4 on $pmux $flatten\softshell.\flash.\spimemio.\xfer.$procmux$8487.
+ dead port 3/4 on $pmux $flatten\softshell.\flash.\spimemio.\xfer.$procmux$8487.
+ dead port 2/2 on $mux $flatten\softshell.\flash.\spimemio.\xfer.$procmux$8491.
+ dead port 2/2 on $mux $flatten\softshell.\flash.\spimemio.\xfer.$procmux$8498.
+ dead port 1/4 on $pmux $flatten\softshell.\flash.\spimemio.\xfer.$procmux$8500.
+ dead port 2/4 on $pmux $flatten\softshell.\flash.\spimemio.\xfer.$procmux$8500.
+ dead port 3/4 on $pmux $flatten\softshell.\flash.\spimemio.\xfer.$procmux$8500.
+ dead port 2/2 on $mux $flatten\softshell.\flash.\spimemio.\xfer.$procmux$8504.
+ dead port 2/2 on $mux $flatten\softshell.\flash.\spimemio.\xfer.$procmux$8524.
+ dead port 2/2 on $mux $flatten\softshell.\flash.\spimemio.\xfer.$procmux$8526.
+ dead port 2/2 on $mux $flatten\softshell.\flash.\spimemio.\xfer.$procmux$8535.
+ dead port 2/2 on $mux $flatten\softshell.\flash.\spimemio.\xfer.$procmux$8537.
+ dead port 2/2 on $mux $flatten\softshell.\flash.\spimemio.\xfer.$procmux$8559.
+ dead port 2/2 on $mux $flatten\softshell.\flash.\spimemio.\xfer.$procmux$8561.
+ dead port 2/2 on $mux $flatten\softshell.\flash.\spimemio.\xfer.$procmux$8571.
+ dead port 2/2 on $mux $flatten\softshell.\flash.\spimemio.\xfer.$procmux$8573.
+ dead port 2/2 on $mux $flatten\softshell.\flash.\spimemio.\xfer.$procmux$8583.
+ dead port 2/2 on $mux $flatten\softshell.\flash.\spimemio.\xfer.$procmux$8593.
+ dead port 2/2 on $mux $flatten\softshell.\flash.\spimemio.\xfer.$procmux$8603.
+ dead port 2/2 on $mux $flatten\softshell.\flash.\spimemio.\xfer.$procmux$8613.
+ dead port 2/2 on $mux $flatten\softshell.\flash.\spimemio.\xfer.$procmux$8623.
+ dead port 2/2 on $mux $flatten\softshell.\flash.\spimemio.\xfer.$procmux$8633.
+ dead port 2/2 on $mux $flatten\softshell.\flash.\spimemio.\xfer.$procmux$8641.
+ dead port 2/2 on $mux $flatten\softshell.\flash.\spimemio.\xfer.$procmux$8649.
+ dead port 2/2 on $mux $flatten\softshell.\flash.\spimemio.\xfer.$procmux$8659.
+ dead port 2/2 on $mux $flatten\softshell.\flash.\spimemio.\xfer.$procmux$8667.
+ dead port 2/2 on $mux $flatten\softshell.\flash.\spimemio.\xfer.$procmux$8675.
+ dead port 2/2 on $mux $flatten\softshell.\flash.\spimemio.\xfer.$procmux$8685.
+ dead port 2/2 on $mux $flatten\softshell.\pinmux.$procmux$15068.
+ dead port 1/2 on $mux $flatten\softshell.\pinmux.$procmux$15071.
+ dead port 2/2 on $mux $flatten\softshell.\pinmux.$procmux$15073.
+ dead port 2/2 on $mux $flatten\softshell.\pinmux.$procmux$15134.
+ dead port 2/2 on $mux $flatten\softshell.\pinmux.$procmux$15136.
+ dead port 2/2 on $mux $flatten\softshell.\arbiter.\arb_inst.$procmux$5016.
+ dead port 1/2 on $mux $flatten\softshell.\arbiter.\arb_inst.$procmux$5022.
+Removed 368 multiplexer ports.
+<suppressed ~831 debug messages>
+
+23.7.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
+ Optimizing cells in module \user_proj_example.
+ Consolidated identical input bits for $mux cell $flatten\softshell.\cpus[0].core.\flexio.\out_fifo.$procmux$5505:
+ Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\softshell.\cpus[0].core.\flexio.\out_fifo.$0$memwr$\mem$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:139$1999_EN[31:0]$2010
+ New ports: A=1'0, B=1'1, Y=$flatten\softshell.\cpus[0].core.\flexio.\out_fifo.$0$memwr$\mem$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:139$1999_EN[31:0]$2010 [0]
+ New connections: $flatten\softshell.\cpus[0].core.\flexio.\out_fifo.$0$memwr$\mem$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:139$1999_EN[31:0]$2010 [31:1] = { $flatten\softshell.\cpus[0].core.\flexio.\out_fifo.$0$memwr$\mem$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:139$1999_EN[31:0]$2010 [0] $flatten\softshell.\cpus[0].core.\flexio.\out_fifo.$0$memwr$\mem$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:139$1999_EN[31:0]$2010 [0] $flatten\softshell.\cpus[0].core.\flexio.\out_fifo.$0$memwr$\mem$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:139$1999_EN[31:0]$2010 [0] $flatten\softshell.\cpus[0].core.\flexio.\out_fifo.$0$memwr$\mem$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:139$1999_EN[31:0]$2010 [0] $flatten\softshell.\cpus[0].core.\flexio.\out_fifo.$0$memwr$\mem$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:139$1999_EN[31:0]$2010 [0] $flatten\softshell.\cpus[0].core.\flexio.\out_fifo.$0$memwr$\mem$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:139$1999_EN[31:0]$2010 [0] $flatten\softshell.\cpus[0].core.\flexio.\out_fifo.$0$memwr$\mem$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:139$1999_EN[31:0]$2010 [0] $flatten\softshell.\cpus[0].core.\flexio.\out_fifo.$0$memwr$\mem$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:139$1999_EN[31:0]$2010 [0] $flatten\softshell.\cpus[0].core.\flexio.\out_fifo.$0$memwr$\mem$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:139$1999_EN[31:0]$2010 [0] $flatten\softshell.\cpus[0].core.\flexio.\out_fifo.$0$memwr$\mem$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:139$1999_EN[31:0]$2010 [0] $flatten\softshell.\cpus[0].core.\flexio.\out_fifo.$0$memwr$\mem$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:139$1999_EN[31:0]$2010 [0] $flatten\softshell.\cpus[0].core.\flexio.\out_fifo.$0$memwr$\mem$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:139$1999_EN[31:0]$2010 [0] $flatten\softshell.\cpus[0].core.\flexio.\out_fifo.$0$memwr$\mem$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:139$1999_EN[31:0]$2010 [0] $flatten\softshell.\cpus[0].core.\flexio.\out_fifo.$0$memwr$\mem$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:139$1999_EN[31:0]$2010 [0] $flatten\softshell.\cpus[0].core.\flexio.\out_fifo.$0$memwr$\mem$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:139$1999_EN[31:0]$2010 [0] $flatten\softshell.\cpus[0].core.\flexio.\out_fifo.$0$memwr$\mem$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:139$1999_EN[31:0]$2010 [0] $flatten\softshell.\cpus[0].core.\flexio.\out_fifo.$0$memwr$\mem$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:139$1999_EN[31:0]$2010 [0] $flatten\softshell.\cpus[0].core.\flexio.\out_fifo.$0$memwr$\mem$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:139$1999_EN[31:0]$2010 [0] $flatten\softshell.\cpus[0].core.\flexio.\out_fifo.$0$memwr$\mem$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:139$1999_EN[31:0]$2010 [0] $flatten\softshell.\cpus[0].core.\flexio.\out_fifo.$0$memwr$\mem$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:139$1999_EN[31:0]$2010 [0] $flatten\softshell.\cpus[0].core.\flexio.\out_fifo.$0$memwr$\mem$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:139$1999_EN[31:0]$2010 [0] $flatten\softshell.\cpus[0].core.\flexio.\out_fifo.$0$memwr$\mem$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:139$1999_EN[31:0]$2010 [0] $flatten\softshell.\cpus[0].core.\flexio.\out_fifo.$0$memwr$\mem$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:139$1999_EN[31:0]$2010 [0] $flatten\softshell.\cpus[0].core.\flexio.\out_fifo.$0$memwr$\mem$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:139$1999_EN[31:0]$2010 [0] $flatten\softshell.\cpus[0].core.\flexio.\out_fifo.$0$memwr$\mem$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:139$1999_EN[31:0]$2010 [0] $flatten\softshell.\cpus[0].core.\flexio.\out_fifo.$0$memwr$\mem$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:139$1999_EN[31:0]$2010 [0] $flatten\softshell.\cpus[0].core.\flexio.\out_fifo.$0$memwr$\mem$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:139$1999_EN[31:0]$2010 [0] $flatten\softshell.\cpus[0].core.\flexio.\out_fifo.$0$memwr$\mem$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:139$1999_EN[31:0]$2010 [0] $flatten\softshell.\cpus[0].core.\flexio.\out_fifo.$0$memwr$\mem$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:139$1999_EN[31:0]$2010 [0] $flatten\softshell.\cpus[0].core.\flexio.\out_fifo.$0$memwr$\mem$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:139$1999_EN[31:0]$2010 [0] $flatten\softshell.\cpus[0].core.\flexio.\out_fifo.$0$memwr$\mem$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:139$1999_EN[31:0]$2010 [0] }
+ Consolidated identical input bits for $mux cell $flatten\softshell.\cpus[0].core.\soc_mem.\ram.$procmux$14899:
+ Old ports: A=8'00000000, B=8'11111111, Y=$flatten\softshell.\cpus[0].core.\soc_mem.\ram.$procmux$14899_Y
+ New ports: A=1'0, B=1'1, Y=$flatten\softshell.\cpus[0].core.\soc_mem.\ram.$procmux$14899_Y [0]
+ New connections: $flatten\softshell.\cpus[0].core.\soc_mem.\ram.$procmux$14899_Y [7:1] = { $flatten\softshell.\cpus[0].core.\soc_mem.\ram.$procmux$14899_Y [0] $flatten\softshell.\cpus[0].core.\soc_mem.\ram.$procmux$14899_Y [0] $flatten\softshell.\cpus[0].core.\soc_mem.\ram.$procmux$14899_Y [0] $flatten\softshell.\cpus[0].core.\soc_mem.\ram.$procmux$14899_Y [0] $flatten\softshell.\cpus[0].core.\soc_mem.\ram.$procmux$14899_Y [0] $flatten\softshell.\cpus[0].core.\soc_mem.\ram.$procmux$14899_Y [0] $flatten\softshell.\cpus[0].core.\soc_mem.\ram.$procmux$14899_Y [0] }
+ Consolidated identical input bits for $mux cell $flatten\softshell.\cpus[0].core.\soc_mem.\ram.$procmux$14911:
+ Old ports: A=8'00000000, B=8'11111111, Y=$flatten\softshell.\cpus[0].core.\soc_mem.\ram.$procmux$14911_Y
+ New ports: A=1'0, B=1'1, Y=$flatten\softshell.\cpus[0].core.\soc_mem.\ram.$procmux$14911_Y [0]
+ New connections: $flatten\softshell.\cpus[0].core.\soc_mem.\ram.$procmux$14911_Y [7:1] = { $flatten\softshell.\cpus[0].core.\soc_mem.\ram.$procmux$14911_Y [0] $flatten\softshell.\cpus[0].core.\soc_mem.\ram.$procmux$14911_Y [0] $flatten\softshell.\cpus[0].core.\soc_mem.\ram.$procmux$14911_Y [0] $flatten\softshell.\cpus[0].core.\soc_mem.\ram.$procmux$14911_Y [0] $flatten\softshell.\cpus[0].core.\soc_mem.\ram.$procmux$14911_Y [0] $flatten\softshell.\cpus[0].core.\soc_mem.\ram.$procmux$14911_Y [0] $flatten\softshell.\cpus[0].core.\soc_mem.\ram.$procmux$14911_Y [0] }
+ Consolidated identical input bits for $mux cell $flatten\softshell.\cpus[0].core.\soc_mem.\ram.$procmux$14923:
+ Old ports: A=8'00000000, B=8'11111111, Y=$flatten\softshell.\cpus[0].core.\soc_mem.\ram.$procmux$14923_Y
+ New ports: A=1'0, B=1'1, Y=$flatten\softshell.\cpus[0].core.\soc_mem.\ram.$procmux$14923_Y [0]
+ New connections: $flatten\softshell.\cpus[0].core.\soc_mem.\ram.$procmux$14923_Y [7:1] = { $flatten\softshell.\cpus[0].core.\soc_mem.\ram.$procmux$14923_Y [0] $flatten\softshell.\cpus[0].core.\soc_mem.\ram.$procmux$14923_Y [0] $flatten\softshell.\cpus[0].core.\soc_mem.\ram.$procmux$14923_Y [0] $flatten\softshell.\cpus[0].core.\soc_mem.\ram.$procmux$14923_Y [0] $flatten\softshell.\cpus[0].core.\soc_mem.\ram.$procmux$14923_Y [0] $flatten\softshell.\cpus[0].core.\soc_mem.\ram.$procmux$14923_Y [0] $flatten\softshell.\cpus[0].core.\soc_mem.\ram.$procmux$14923_Y [0] }
+ Consolidated identical input bits for $mux cell $flatten\softshell.\cpus[0].core.\soc_mem.\ram.$procmux$14935:
+ Old ports: A=8'00000000, B=8'11111111, Y=$flatten\softshell.\cpus[0].core.\soc_mem.\ram.$procmux$14935_Y
+ New ports: A=1'0, B=1'1, Y=$flatten\softshell.\cpus[0].core.\soc_mem.\ram.$procmux$14935_Y [0]
+ New connections: $flatten\softshell.\cpus[0].core.\soc_mem.\ram.$procmux$14935_Y [7:1] = { $flatten\softshell.\cpus[0].core.\soc_mem.\ram.$procmux$14935_Y [0] $flatten\softshell.\cpus[0].core.\soc_mem.\ram.$procmux$14935_Y [0] $flatten\softshell.\cpus[0].core.\soc_mem.\ram.$procmux$14935_Y [0] $flatten\softshell.\cpus[0].core.\soc_mem.\ram.$procmux$14935_Y [0] $flatten\softshell.\cpus[0].core.\soc_mem.\ram.$procmux$14935_Y [0] $flatten\softshell.\cpus[0].core.\soc_mem.\ram.$procmux$14935_Y [0] $flatten\softshell.\cpus[0].core.\soc_mem.\ram.$procmux$14935_Y [0] }
+ New ctrl vector for $pmux cell $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10007: { $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$eq$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1308$3962_Y $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10008_CMP }
+ New ctrl vector for $pmux cell $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10147: { $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$eq$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1308$3962_Y $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10018_CMP $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10165_CMP $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10008_CMP $auto$opt_reduce.cc:134:opt_mux$16929 }
+ New ctrl vector for $pmux cell $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10170: { \softshell.cpus[1].core.cpu.picorv32_core.instr_trap $auto$opt_reduce.cc:134:opt_mux$16931 }
+ New ctrl vector for $pmux cell $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10257: { \softshell.cpus[1].core.cpu.picorv32_core.instr_trap $auto$opt_reduce.cc:134:opt_mux$16935 $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1691$4075_Y $auto$opt_reduce.cc:134:opt_mux$16933 }
+ New ctrl vector for $pmux cell $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10431: { $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$eq$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1308$3962_Y $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10018_CMP $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10165_CMP $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10149_CMP }
+ New ctrl vector for $pmux cell $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10457: { \softshell.cpus[1].core.cpu.picorv32_core.instr_trap $auto$opt_reduce.cc:134:opt_mux$16939 $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1691$4075_Y $auto$opt_reduce.cc:134:opt_mux$16937 }
+ New ctrl vector for $pmux cell $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10641: { \softshell.cpus[1].core.cpu.picorv32_core.is_lui_auipc_jal $auto$opt_reduce.cc:134:opt_mux$16941 $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10258_CTRL }
+ New ctrl vector for $pmux cell $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10691: { \softshell.cpus[1].core.cpu.picorv32_core.is_lui_auipc_jal $auto$opt_reduce.cc:134:opt_mux$16943 }
+ New ctrl vector for $pmux cell $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10824: $auto$opt_reduce.cc:134:opt_mux$16945
+ New ctrl vector for $pmux cell $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10914: { $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10911_CMP $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10929_CMP $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10907_CMP $auto$opt_reduce.cc:134:opt_mux$16947 }
+ New ctrl vector for $pmux cell $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10932: $auto$opt_reduce.cc:134:opt_mux$16949
+ New ctrl vector for $pmux cell $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$11000: { $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10911_CMP $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10929_CMP $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10907_CMP $auto$opt_reduce.cc:134:opt_mux$16951 }
+ New ctrl vector for $pmux cell $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$11018: { $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10911_CMP $auto$opt_reduce.cc:134:opt_mux$16953 }
+ New ctrl vector for $pmux cell $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$11066: { $auto$opt_reduce.cc:134:opt_mux$16955 $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10929_CMP $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10907_CMP }
+ New ctrl vector for $pmux cell $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$11087: $auto$opt_reduce.cc:134:opt_mux$16957
+ New ctrl vector for $pmux cell $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$11208: { $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$11216_CMP $auto$opt_reduce.cc:134:opt_mux$16959 $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10929_CMP $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10907_CMP }
+ New ctrl vector for $pmux cell $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$11220: $auto$opt_reduce.cc:134:opt_mux$16961
+ New ctrl vector for $pmux cell $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$11376: $auto$opt_reduce.cc:134:opt_mux$16963
+ New ctrl vector for $pmux cell $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$8132: { $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$7261_CMP $auto$opt_reduce.cc:134:opt_mux$16965 }
+ New ctrl vector for $pmux cell $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$11763: { $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10907_CMP $auto$opt_reduce.cc:134:opt_mux$16967 }
+ New ctrl vector for $pmux cell $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$11778: { $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10907_CMP $auto$opt_reduce.cc:134:opt_mux$16969 }
+ New ctrl vector for $pmux cell $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$5571: { $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$eq$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1308$4645_Y $auto$opt_reduce.cc:134:opt_mux$16971 }
+ New ctrl vector for $pmux cell $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$11796: $auto$opt_reduce.cc:134:opt_mux$16973
+ New ctrl vector for $pmux cell $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$11809: $auto$opt_reduce.cc:134:opt_mux$16975
+ New ctrl vector for $pmux cell $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$5593: { $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$eq$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1308$4645_Y $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$5577_CMP $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$5576_CMP $auto$opt_reduce.cc:134:opt_mux$16977 }
+ New ctrl vector for $pmux cell $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$11834: { $auto$opt_reduce.cc:134:opt_mux$16979 $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10929_CMP $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10907_CMP }
+ New ctrl vector for $pmux cell $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$8150: $auto$opt_reduce.cc:134:opt_mux$16981
+ New ctrl vector for $pmux cell $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$5616: { $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$eq$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1308$4645_Y $auto$opt_reduce.cc:134:opt_mux$16983 }
+ New ctrl vector for $pmux cell $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$11869: { $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10911_CMP $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10907_CMP $auto$opt_reduce.cc:134:opt_mux$16985 }
+ New ctrl vector for $pmux cell $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$11884: { $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10929_CMP $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10907_CMP $auto$opt_reduce.cc:134:opt_mux$16987 $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10915_CMP }
+ New ctrl vector for $pmux cell $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$11911: { $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10911_CMP $auto$opt_reduce.cc:134:opt_mux$16989 }
+ New ctrl vector for $pmux cell $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$11924: $auto$opt_reduce.cc:134:opt_mux$16991
+ New ctrl vector for $pmux cell $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$8163: $auto$opt_reduce.cc:134:opt_mux$16993
+ New ctrl vector for $pmux cell $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$11950: { $auto$opt_reduce.cc:134:opt_mux$16997 $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10929_CMP $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10907_CMP $auto$opt_reduce.cc:134:opt_mux$16995 }
+ New ctrl vector for $pmux cell $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$11969: { $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10911_CMP $auto$opt_reduce.cc:134:opt_mux$16999 }
+ New ctrl vector for $pmux cell $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$8188: { $auto$opt_reduce.cc:134:opt_mux$17001 $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$7283_CMP $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$7261_CMP }
+ New ctrl vector for $pmux cell $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$9217: { $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$eq$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1308$3962_Y $auto$opt_reduce.cc:134:opt_mux$17003 }
+ New ctrl vector for $pmux cell $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$9239: { $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$eq$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1308$3962_Y $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10018_CMP $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10165_CMP $auto$opt_reduce.cc:134:opt_mux$17005 }
+ New ctrl vector for $pmux cell $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$8223: { $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$7265_CMP $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$7261_CMP $auto$opt_reduce.cc:134:opt_mux$17007 }
+ New ctrl vector for $pmux cell $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$9262: { $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$eq$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1308$3962_Y $auto$opt_reduce.cc:134:opt_mux$17009 }
+ New ctrl vector for $pmux cell $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$8238: { $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$7283_CMP $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$7261_CMP $auto$opt_reduce.cc:134:opt_mux$17011 $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$7269_CMP }
+ New ctrl vector for $pmux cell $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$8265: { $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$7265_CMP $auto$opt_reduce.cc:134:opt_mux$17013 }
+ New ctrl vector for $pmux cell $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$8278: $auto$opt_reduce.cc:134:opt_mux$17015
+ New ctrl vector for $pmux cell $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$8304: { $auto$opt_reduce.cc:134:opt_mux$17019 $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$7283_CMP $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$7261_CMP $auto$opt_reduce.cc:134:opt_mux$17017 }
+ New ctrl vector for $pmux cell $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$9653: { $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10223_CMP $auto$opt_reduce.cc:134:opt_mux$17021 }
+ New ctrl vector for $pmux cell $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$6007: { $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$5573_CMP $auto$opt_reduce.cc:134:opt_mux$17023 }
+ New ctrl vector for $pmux cell $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$9666: { $auto$opt_reduce.cc:134:opt_mux$17025 $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10034_CMP }
+ New ctrl vector for $pmux cell $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$6020: { $auto$opt_reduce.cc:134:opt_mux$17027 $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$5572_CMP }
+ New ctrl vector for $pmux cell $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$8323: { $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$7265_CMP $auto$opt_reduce.cc:134:opt_mux$17029 }
+ New ctrl vector for $pmux cell $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$9679: { $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10008_CMP $auto$opt_reduce.cc:134:opt_mux$17031 }
+ New ctrl vector for $pmux cell $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$6033: { $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$5575_CMP $auto$opt_reduce.cc:134:opt_mux$17033 }
+ New ctrl vector for $pmux cell $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$9963: $auto$opt_reduce.cc:134:opt_mux$17035
+ Consolidated identical input bits for $mux cell $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.\cpuregs.$procmux$16272:
+ Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/rv_core.v:286$25_EN[31:0]$29
+ New ports: A=1'0, B=1'1, Y=$flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/rv_core.v:286$25_EN[31:0]$29 [0]
+ New connections: $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/rv_core.v:286$25_EN[31:0]$29 [31:1] = { $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/rv_core.v:286$25_EN[31:0]$29 [0] $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/rv_core.v:286$25_EN[31:0]$29 [0] $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/rv_core.v:286$25_EN[31:0]$29 [0] $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/rv_core.v:286$25_EN[31:0]$29 [0] $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/rv_core.v:286$25_EN[31:0]$29 [0] $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/rv_core.v:286$25_EN[31:0]$29 [0] $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/rv_core.v:286$25_EN[31:0]$29 [0] $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/rv_core.v:286$25_EN[31:0]$29 [0] $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/rv_core.v:286$25_EN[31:0]$29 [0] $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/rv_core.v:286$25_EN[31:0]$29 [0] $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/rv_core.v:286$25_EN[31:0]$29 [0] $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/rv_core.v:286$25_EN[31:0]$29 [0] $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/rv_core.v:286$25_EN[31:0]$29 [0] $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/rv_core.v:286$25_EN[31:0]$29 [0] $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/rv_core.v:286$25_EN[31:0]$29 [0] $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/rv_core.v:286$25_EN[31:0]$29 [0] $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/rv_core.v:286$25_EN[31:0]$29 [0] $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/rv_core.v:286$25_EN[31:0]$29 [0] $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/rv_core.v:286$25_EN[31:0]$29 [0] $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/rv_core.v:286$25_EN[31:0]$29 [0] $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/rv_core.v:286$25_EN[31:0]$29 [0] $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/rv_core.v:286$25_EN[31:0]$29 [0] $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/rv_core.v:286$25_EN[31:0]$29 [0] $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/rv_core.v:286$25_EN[31:0]$29 [0] $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/rv_core.v:286$25_EN[31:0]$29 [0] $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/rv_core.v:286$25_EN[31:0]$29 [0] $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/rv_core.v:286$25_EN[31:0]$29 [0] $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/rv_core.v:286$25_EN[31:0]$29 [0] $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/rv_core.v:286$25_EN[31:0]$29 [0] $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/rv_core.v:286$25_EN[31:0]$29 [0] $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/rv_core.v:286$25_EN[31:0]$29 [0] }
+ Consolidated identical input bits for $mux cell $flatten\softshell.\cpus[1].core.\flexio.\out_fifo.$procmux$5505:
+ Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\softshell.\cpus[1].core.\flexio.\out_fifo.$0$memwr$\mem$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:139$1999_EN[31:0]$2010
+ New ports: A=1'0, B=1'1, Y=$flatten\softshell.\cpus[1].core.\flexio.\out_fifo.$0$memwr$\mem$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:139$1999_EN[31:0]$2010 [0]
+ New connections: $flatten\softshell.\cpus[1].core.\flexio.\out_fifo.$0$memwr$\mem$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:139$1999_EN[31:0]$2010 [31:1] = { $flatten\softshell.\cpus[1].core.\flexio.\out_fifo.$0$memwr$\mem$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:139$1999_EN[31:0]$2010 [0] $flatten\softshell.\cpus[1].core.\flexio.\out_fifo.$0$memwr$\mem$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:139$1999_EN[31:0]$2010 [0] $flatten\softshell.\cpus[1].core.\flexio.\out_fifo.$0$memwr$\mem$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:139$1999_EN[31:0]$2010 [0] $flatten\softshell.\cpus[1].core.\flexio.\out_fifo.$0$memwr$\mem$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:139$1999_EN[31:0]$2010 [0] $flatten\softshell.\cpus[1].core.\flexio.\out_fifo.$0$memwr$\mem$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:139$1999_EN[31:0]$2010 [0] $flatten\softshell.\cpus[1].core.\flexio.\out_fifo.$0$memwr$\mem$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:139$1999_EN[31:0]$2010 [0] $flatten\softshell.\cpus[1].core.\flexio.\out_fifo.$0$memwr$\mem$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:139$1999_EN[31:0]$2010 [0] $flatten\softshell.\cpus[1].core.\flexio.\out_fifo.$0$memwr$\mem$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:139$1999_EN[31:0]$2010 [0] $flatten\softshell.\cpus[1].core.\flexio.\out_fifo.$0$memwr$\mem$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:139$1999_EN[31:0]$2010 [0] $flatten\softshell.\cpus[1].core.\flexio.\out_fifo.$0$memwr$\mem$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:139$1999_EN[31:0]$2010 [0] $flatten\softshell.\cpus[1].core.\flexio.\out_fifo.$0$memwr$\mem$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:139$1999_EN[31:0]$2010 [0] $flatten\softshell.\cpus[1].core.\flexio.\out_fifo.$0$memwr$\mem$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:139$1999_EN[31:0]$2010 [0] $flatten\softshell.\cpus[1].core.\flexio.\out_fifo.$0$memwr$\mem$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:139$1999_EN[31:0]$2010 [0] $flatten\softshell.\cpus[1].core.\flexio.\out_fifo.$0$memwr$\mem$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:139$1999_EN[31:0]$2010 [0] $flatten\softshell.\cpus[1].core.\flexio.\out_fifo.$0$memwr$\mem$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:139$1999_EN[31:0]$2010 [0] $flatten\softshell.\cpus[1].core.\flexio.\out_fifo.$0$memwr$\mem$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:139$1999_EN[31:0]$2010 [0] $flatten\softshell.\cpus[1].core.\flexio.\out_fifo.$0$memwr$\mem$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:139$1999_EN[31:0]$2010 [0] $flatten\softshell.\cpus[1].core.\flexio.\out_fifo.$0$memwr$\mem$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:139$1999_EN[31:0]$2010 [0] $flatten\softshell.\cpus[1].core.\flexio.\out_fifo.$0$memwr$\mem$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:139$1999_EN[31:0]$2010 [0] $flatten\softshell.\cpus[1].core.\flexio.\out_fifo.$0$memwr$\mem$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:139$1999_EN[31:0]$2010 [0] $flatten\softshell.\cpus[1].core.\flexio.\out_fifo.$0$memwr$\mem$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:139$1999_EN[31:0]$2010 [0] $flatten\softshell.\cpus[1].core.\flexio.\out_fifo.$0$memwr$\mem$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:139$1999_EN[31:0]$2010 [0] $flatten\softshell.\cpus[1].core.\flexio.\out_fifo.$0$memwr$\mem$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:139$1999_EN[31:0]$2010 [0] $flatten\softshell.\cpus[1].core.\flexio.\out_fifo.$0$memwr$\mem$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:139$1999_EN[31:0]$2010 [0] $flatten\softshell.\cpus[1].core.\flexio.\out_fifo.$0$memwr$\mem$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:139$1999_EN[31:0]$2010 [0] $flatten\softshell.\cpus[1].core.\flexio.\out_fifo.$0$memwr$\mem$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:139$1999_EN[31:0]$2010 [0] $flatten\softshell.\cpus[1].core.\flexio.\out_fifo.$0$memwr$\mem$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:139$1999_EN[31:0]$2010 [0] $flatten\softshell.\cpus[1].core.\flexio.\out_fifo.$0$memwr$\mem$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:139$1999_EN[31:0]$2010 [0] $flatten\softshell.\cpus[1].core.\flexio.\out_fifo.$0$memwr$\mem$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:139$1999_EN[31:0]$2010 [0] $flatten\softshell.\cpus[1].core.\flexio.\out_fifo.$0$memwr$\mem$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:139$1999_EN[31:0]$2010 [0] $flatten\softshell.\cpus[1].core.\flexio.\out_fifo.$0$memwr$\mem$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:139$1999_EN[31:0]$2010 [0] }
+ Consolidated identical input bits for $mux cell $flatten\softshell.\cpus[1].core.\soc_mem.\ram.$procmux$14899:
+ Old ports: A=8'00000000, B=8'11111111, Y=$flatten\softshell.\cpus[1].core.\soc_mem.\ram.$procmux$14899_Y
+ New ports: A=1'0, B=1'1, Y=$flatten\softshell.\cpus[1].core.\soc_mem.\ram.$procmux$14899_Y [0]
+ New connections: $flatten\softshell.\cpus[1].core.\soc_mem.\ram.$procmux$14899_Y [7:1] = { $flatten\softshell.\cpus[1].core.\soc_mem.\ram.$procmux$14899_Y [0] $flatten\softshell.\cpus[1].core.\soc_mem.\ram.$procmux$14899_Y [0] $flatten\softshell.\cpus[1].core.\soc_mem.\ram.$procmux$14899_Y [0] $flatten\softshell.\cpus[1].core.\soc_mem.\ram.$procmux$14899_Y [0] $flatten\softshell.\cpus[1].core.\soc_mem.\ram.$procmux$14899_Y [0] $flatten\softshell.\cpus[1].core.\soc_mem.\ram.$procmux$14899_Y [0] $flatten\softshell.\cpus[1].core.\soc_mem.\ram.$procmux$14899_Y [0] }
+ Consolidated identical input bits for $mux cell $flatten\softshell.\cpus[1].core.\soc_mem.\ram.$procmux$14911:
+ Old ports: A=8'00000000, B=8'11111111, Y=$flatten\softshell.\cpus[1].core.\soc_mem.\ram.$procmux$14911_Y
+ New ports: A=1'0, B=1'1, Y=$flatten\softshell.\cpus[1].core.\soc_mem.\ram.$procmux$14911_Y [0]
+ New connections: $flatten\softshell.\cpus[1].core.\soc_mem.\ram.$procmux$14911_Y [7:1] = { $flatten\softshell.\cpus[1].core.\soc_mem.\ram.$procmux$14911_Y [0] $flatten\softshell.\cpus[1].core.\soc_mem.\ram.$procmux$14911_Y [0] $flatten\softshell.\cpus[1].core.\soc_mem.\ram.$procmux$14911_Y [0] $flatten\softshell.\cpus[1].core.\soc_mem.\ram.$procmux$14911_Y [0] $flatten\softshell.\cpus[1].core.\soc_mem.\ram.$procmux$14911_Y [0] $flatten\softshell.\cpus[1].core.\soc_mem.\ram.$procmux$14911_Y [0] $flatten\softshell.\cpus[1].core.\soc_mem.\ram.$procmux$14911_Y [0] }
+ Consolidated identical input bits for $mux cell $flatten\softshell.\cpus[1].core.\soc_mem.\ram.$procmux$14923:
+ Old ports: A=8'00000000, B=8'11111111, Y=$flatten\softshell.\cpus[1].core.\soc_mem.\ram.$procmux$14923_Y
+ New ports: A=1'0, B=1'1, Y=$flatten\softshell.\cpus[1].core.\soc_mem.\ram.$procmux$14923_Y [0]
+ New connections: $flatten\softshell.\cpus[1].core.\soc_mem.\ram.$procmux$14923_Y [7:1] = { $flatten\softshell.\cpus[1].core.\soc_mem.\ram.$procmux$14923_Y [0] $flatten\softshell.\cpus[1].core.\soc_mem.\ram.$procmux$14923_Y [0] $flatten\softshell.\cpus[1].core.\soc_mem.\ram.$procmux$14923_Y [0] $flatten\softshell.\cpus[1].core.\soc_mem.\ram.$procmux$14923_Y [0] $flatten\softshell.\cpus[1].core.\soc_mem.\ram.$procmux$14923_Y [0] $flatten\softshell.\cpus[1].core.\soc_mem.\ram.$procmux$14923_Y [0] $flatten\softshell.\cpus[1].core.\soc_mem.\ram.$procmux$14923_Y [0] }
+ Consolidated identical input bits for $mux cell $flatten\softshell.\cpus[1].core.\soc_mem.\ram.$procmux$14935:
+ Old ports: A=8'00000000, B=8'11111111, Y=$flatten\softshell.\cpus[1].core.\soc_mem.\ram.$procmux$14935_Y
+ New ports: A=1'0, B=1'1, Y=$flatten\softshell.\cpus[1].core.\soc_mem.\ram.$procmux$14935_Y [0]
+ New connections: $flatten\softshell.\cpus[1].core.\soc_mem.\ram.$procmux$14935_Y [7:1] = { $flatten\softshell.\cpus[1].core.\soc_mem.\ram.$procmux$14935_Y [0] $flatten\softshell.\cpus[1].core.\soc_mem.\ram.$procmux$14935_Y [0] $flatten\softshell.\cpus[1].core.\soc_mem.\ram.$procmux$14935_Y [0] $flatten\softshell.\cpus[1].core.\soc_mem.\ram.$procmux$14935_Y [0] $flatten\softshell.\cpus[1].core.\soc_mem.\ram.$procmux$14935_Y [0] $flatten\softshell.\cpus[1].core.\soc_mem.\ram.$procmux$14935_Y [0] $flatten\softshell.\cpus[1].core.\soc_mem.\ram.$procmux$14935_Y [0] }
+ New ctrl vector for $pmux cell $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$6317: $auto$opt_reduce.cc:134:opt_mux$17037
+ New ctrl vector for $pmux cell $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$6361: { $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$eq$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1308$4645_Y $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$5575_CMP }
+ New ctrl vector for $pmux cell $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$6501: { $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$eq$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1308$4645_Y $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$5577_CMP $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$5576_CMP $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$5575_CMP $auto$opt_reduce.cc:134:opt_mux$17039 }
+ New ctrl vector for $pmux cell $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$6524: { \softshell.cpus[0].core.cpu.picorv32_core.instr_trap $auto$opt_reduce.cc:134:opt_mux$17041 }
+ New ctrl vector for $pmux cell $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$8117: { $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$7261_CMP $auto$opt_reduce.cc:134:opt_mux$17043 }
+ New ctrl vector for $pmux cell $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$12082: { $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$eq$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1308$3279_Y $auto$opt_reduce.cc:134:opt_mux$17045 }
+ New ctrl vector for $pmux cell $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$6611: { \softshell.cpus[0].core.cpu.picorv32_core.instr_trap $auto$opt_reduce.cc:134:opt_mux$17049 $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1691$4758_Y $auto$opt_reduce.cc:134:opt_mux$17047 }
+ New ctrl vector for $pmux cell $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$12104: { $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$eq$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1308$3279_Y $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$12088_CMP $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$12087_CMP $auto$opt_reduce.cc:134:opt_mux$17051 }
+ New ctrl vector for $pmux cell $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$12127: { $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$eq$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1308$3279_Y $auto$opt_reduce.cc:134:opt_mux$17053 }
+ New ctrl vector for $pmux cell $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$6785: { $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$eq$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1308$4645_Y $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$5577_CMP $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$5576_CMP $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$5574_CMP }
+ New ctrl vector for $pmux cell $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$6811: { \softshell.cpus[0].core.cpu.picorv32_core.instr_trap $auto$opt_reduce.cc:134:opt_mux$17057 $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1691$4758_Y $auto$opt_reduce.cc:134:opt_mux$17055 }
+ New ctrl vector for $pmux cell $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$12518: { $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$12084_CMP $auto$opt_reduce.cc:134:opt_mux$17059 }
+ New ctrl vector for $pmux cell $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$12531: { $auto$opt_reduce.cc:134:opt_mux$17061 $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$12083_CMP }
+ New ctrl vector for $pmux cell $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$12544: { $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$12086_CMP $auto$opt_reduce.cc:134:opt_mux$17063 }
+ New ctrl vector for $pmux cell $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$12828: $auto$opt_reduce.cc:134:opt_mux$17065
+ New ctrl vector for $pmux cell $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$12872: { $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$eq$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1308$3279_Y $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$12086_CMP }
+ New ctrl vector for $pmux cell $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$6995: { \softshell.cpus[0].core.cpu.picorv32_core.is_lui_auipc_jal $auto$opt_reduce.cc:134:opt_mux$17067 $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$6318_CTRL }
+ New ctrl vector for $pmux cell $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$13012: { $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$eq$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1308$3279_Y $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$12088_CMP $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$12087_CMP $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$12086_CMP $auto$opt_reduce.cc:134:opt_mux$17069 }
+ New ctrl vector for $pmux cell $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$13035: { \softshell.cpus[2].core.cpu.picorv32_core.instr_trap $auto$opt_reduce.cc:134:opt_mux$17071 }
+ New ctrl vector for $pmux cell $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$13122: { \softshell.cpus[2].core.cpu.picorv32_core.instr_trap $auto$opt_reduce.cc:134:opt_mux$17075 $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1691$3392_Y $auto$opt_reduce.cc:134:opt_mux$17073 }
+ New ctrl vector for $pmux cell $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$7045: { \softshell.cpus[0].core.cpu.picorv32_core.is_lui_auipc_jal $auto$opt_reduce.cc:134:opt_mux$17077 }
+ New ctrl vector for $pmux cell $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$13296: { $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$eq$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1308$3279_Y $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$12088_CMP $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$12087_CMP $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$12085_CMP }
+ New ctrl vector for $pmux cell $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$13322: { \softshell.cpus[2].core.cpu.picorv32_core.instr_trap $auto$opt_reduce.cc:134:opt_mux$17081 $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1691$3392_Y $auto$opt_reduce.cc:134:opt_mux$17079 }
+ New ctrl vector for $pmux cell $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$13506: { \softshell.cpus[2].core.cpu.picorv32_core.is_lui_auipc_jal $auto$opt_reduce.cc:134:opt_mux$17083 $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$12829_CTRL }
+ New ctrl vector for $pmux cell $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$13556: { \softshell.cpus[2].core.cpu.picorv32_core.is_lui_auipc_jal $auto$opt_reduce.cc:134:opt_mux$17085 }
+ New ctrl vector for $pmux cell $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$7178: $auto$opt_reduce.cc:134:opt_mux$17087
+ New ctrl vector for $pmux cell $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$13689: $auto$opt_reduce.cc:134:opt_mux$17089
+ New ctrl vector for $pmux cell $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$13779: { $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$13776_CMP $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$13794_CMP $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$13772_CMP $auto$opt_reduce.cc:134:opt_mux$17091 }
+ New ctrl vector for $pmux cell $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$13797: $auto$opt_reduce.cc:134:opt_mux$17093
+ New ctrl vector for $pmux cell $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$13865: { $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$13776_CMP $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$13794_CMP $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$13772_CMP $auto$opt_reduce.cc:134:opt_mux$17095 }
+ New ctrl vector for $pmux cell $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$13883: { $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$13776_CMP $auto$opt_reduce.cc:134:opt_mux$17097 }
+ New ctrl vector for $pmux cell $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$7268: { $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$7265_CMP $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$7283_CMP $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$7261_CMP $auto$opt_reduce.cc:134:opt_mux$17099 }
+ New ctrl vector for $pmux cell $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$13931: { $auto$opt_reduce.cc:134:opt_mux$17101 $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$13794_CMP $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$13772_CMP }
+ New ctrl vector for $pmux cell $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$13952: $auto$opt_reduce.cc:134:opt_mux$17103
+ New ctrl vector for $pmux cell $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$7286: $auto$opt_reduce.cc:134:opt_mux$17105
+ New ctrl vector for $pmux cell $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$14073: { $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$14081_CMP $auto$opt_reduce.cc:134:opt_mux$17107 $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$13794_CMP $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$13772_CMP }
+ New ctrl vector for $pmux cell $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$14085: $auto$opt_reduce.cc:134:opt_mux$17109
+ New ctrl vector for $pmux cell $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$14241: $auto$opt_reduce.cc:134:opt_mux$17111
+ New ctrl vector for $pmux cell $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$7354: { $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$7265_CMP $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$7283_CMP $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$7261_CMP $auto$opt_reduce.cc:134:opt_mux$17113 }
+ New ctrl vector for $pmux cell $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$14628: { $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$13772_CMP $auto$opt_reduce.cc:134:opt_mux$17115 }
+ New ctrl vector for $pmux cell $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$14643: { $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$13772_CMP $auto$opt_reduce.cc:134:opt_mux$17117 }
+ New ctrl vector for $pmux cell $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$7372: { $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$7265_CMP $auto$opt_reduce.cc:134:opt_mux$17119 }
+ New ctrl vector for $pmux cell $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$14661: $auto$opt_reduce.cc:134:opt_mux$17121
+ New ctrl vector for $pmux cell $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$14674: $auto$opt_reduce.cc:134:opt_mux$17123
+ New ctrl vector for $pmux cell $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$14699: { $auto$opt_reduce.cc:134:opt_mux$17125 $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$13794_CMP $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$13772_CMP }
+ New ctrl vector for $pmux cell $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$7420: { $auto$opt_reduce.cc:134:opt_mux$17127 $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$7283_CMP $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$7261_CMP }
+ New ctrl vector for $pmux cell $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$14734: { $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$13776_CMP $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$13772_CMP $auto$opt_reduce.cc:134:opt_mux$17129 }
+ New ctrl vector for $pmux cell $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$14749: { $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$13794_CMP $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$13772_CMP $auto$opt_reduce.cc:134:opt_mux$17131 $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$13780_CMP }
+ New ctrl vector for $pmux cell $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$7441: $auto$opt_reduce.cc:134:opt_mux$17133
+ New ctrl vector for $pmux cell $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$14776: { $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$13776_CMP $auto$opt_reduce.cc:134:opt_mux$17135 }
+ New ctrl vector for $pmux cell $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$14789: $auto$opt_reduce.cc:134:opt_mux$17137
+ New ctrl vector for $pmux cell $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$14815: { $auto$opt_reduce.cc:134:opt_mux$17141 $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$13794_CMP $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$13772_CMP $auto$opt_reduce.cc:134:opt_mux$17139 }
+ New ctrl vector for $pmux cell $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$14834: { $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$13776_CMP $auto$opt_reduce.cc:134:opt_mux$17143 }
+ Consolidated identical input bits for $mux cell $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.\cpuregs.$procmux$16272:
+ Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/rv_core.v:286$25_EN[31:0]$29
+ New ports: A=1'0, B=1'1, Y=$flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/rv_core.v:286$25_EN[31:0]$29 [0]
+ New connections: $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/rv_core.v:286$25_EN[31:0]$29 [31:1] = { $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/rv_core.v:286$25_EN[31:0]$29 [0] $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/rv_core.v:286$25_EN[31:0]$29 [0] $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/rv_core.v:286$25_EN[31:0]$29 [0] $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/rv_core.v:286$25_EN[31:0]$29 [0] $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/rv_core.v:286$25_EN[31:0]$29 [0] $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/rv_core.v:286$25_EN[31:0]$29 [0] $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/rv_core.v:286$25_EN[31:0]$29 [0] $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/rv_core.v:286$25_EN[31:0]$29 [0] $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/rv_core.v:286$25_EN[31:0]$29 [0] $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/rv_core.v:286$25_EN[31:0]$29 [0] $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/rv_core.v:286$25_EN[31:0]$29 [0] $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/rv_core.v:286$25_EN[31:0]$29 [0] $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/rv_core.v:286$25_EN[31:0]$29 [0] $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/rv_core.v:286$25_EN[31:0]$29 [0] $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/rv_core.v:286$25_EN[31:0]$29 [0] $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/rv_core.v:286$25_EN[31:0]$29 [0] $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/rv_core.v:286$25_EN[31:0]$29 [0] $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/rv_core.v:286$25_EN[31:0]$29 [0] $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/rv_core.v:286$25_EN[31:0]$29 [0] $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/rv_core.v:286$25_EN[31:0]$29 [0] $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/rv_core.v:286$25_EN[31:0]$29 [0] $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/rv_core.v:286$25_EN[31:0]$29 [0] $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/rv_core.v:286$25_EN[31:0]$29 [0] $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/rv_core.v:286$25_EN[31:0]$29 [0] $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/rv_core.v:286$25_EN[31:0]$29 [0] $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/rv_core.v:286$25_EN[31:0]$29 [0] $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/rv_core.v:286$25_EN[31:0]$29 [0] $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/rv_core.v:286$25_EN[31:0]$29 [0] $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/rv_core.v:286$25_EN[31:0]$29 [0] $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/rv_core.v:286$25_EN[31:0]$29 [0] $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/rv_core.v:286$25_EN[31:0]$29 [0] }
+ Consolidated identical input bits for $mux cell $flatten\softshell.\cpus[2].core.\flexio.\out_fifo.$procmux$5505:
+ Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\softshell.\cpus[2].core.\flexio.\out_fifo.$0$memwr$\mem$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:139$1999_EN[31:0]$2010
+ New ports: A=1'0, B=1'1, Y=$flatten\softshell.\cpus[2].core.\flexio.\out_fifo.$0$memwr$\mem$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:139$1999_EN[31:0]$2010 [0]
+ New connections: $flatten\softshell.\cpus[2].core.\flexio.\out_fifo.$0$memwr$\mem$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:139$1999_EN[31:0]$2010 [31:1] = { $flatten\softshell.\cpus[2].core.\flexio.\out_fifo.$0$memwr$\mem$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:139$1999_EN[31:0]$2010 [0] $flatten\softshell.\cpus[2].core.\flexio.\out_fifo.$0$memwr$\mem$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:139$1999_EN[31:0]$2010 [0] $flatten\softshell.\cpus[2].core.\flexio.\out_fifo.$0$memwr$\mem$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:139$1999_EN[31:0]$2010 [0] $flatten\softshell.\cpus[2].core.\flexio.\out_fifo.$0$memwr$\mem$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:139$1999_EN[31:0]$2010 [0] $flatten\softshell.\cpus[2].core.\flexio.\out_fifo.$0$memwr$\mem$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:139$1999_EN[31:0]$2010 [0] $flatten\softshell.\cpus[2].core.\flexio.\out_fifo.$0$memwr$\mem$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:139$1999_EN[31:0]$2010 [0] $flatten\softshell.\cpus[2].core.\flexio.\out_fifo.$0$memwr$\mem$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:139$1999_EN[31:0]$2010 [0] $flatten\softshell.\cpus[2].core.\flexio.\out_fifo.$0$memwr$\mem$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:139$1999_EN[31:0]$2010 [0] $flatten\softshell.\cpus[2].core.\flexio.\out_fifo.$0$memwr$\mem$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:139$1999_EN[31:0]$2010 [0] $flatten\softshell.\cpus[2].core.\flexio.\out_fifo.$0$memwr$\mem$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:139$1999_EN[31:0]$2010 [0] $flatten\softshell.\cpus[2].core.\flexio.\out_fifo.$0$memwr$\mem$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:139$1999_EN[31:0]$2010 [0] $flatten\softshell.\cpus[2].core.\flexio.\out_fifo.$0$memwr$\mem$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:139$1999_EN[31:0]$2010 [0] $flatten\softshell.\cpus[2].core.\flexio.\out_fifo.$0$memwr$\mem$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:139$1999_EN[31:0]$2010 [0] $flatten\softshell.\cpus[2].core.\flexio.\out_fifo.$0$memwr$\mem$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:139$1999_EN[31:0]$2010 [0] $flatten\softshell.\cpus[2].core.\flexio.\out_fifo.$0$memwr$\mem$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:139$1999_EN[31:0]$2010 [0] $flatten\softshell.\cpus[2].core.\flexio.\out_fifo.$0$memwr$\mem$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:139$1999_EN[31:0]$2010 [0] $flatten\softshell.\cpus[2].core.\flexio.\out_fifo.$0$memwr$\mem$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:139$1999_EN[31:0]$2010 [0] $flatten\softshell.\cpus[2].core.\flexio.\out_fifo.$0$memwr$\mem$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:139$1999_EN[31:0]$2010 [0] $flatten\softshell.\cpus[2].core.\flexio.\out_fifo.$0$memwr$\mem$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:139$1999_EN[31:0]$2010 [0] $flatten\softshell.\cpus[2].core.\flexio.\out_fifo.$0$memwr$\mem$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:139$1999_EN[31:0]$2010 [0] $flatten\softshell.\cpus[2].core.\flexio.\out_fifo.$0$memwr$\mem$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:139$1999_EN[31:0]$2010 [0] $flatten\softshell.\cpus[2].core.\flexio.\out_fifo.$0$memwr$\mem$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:139$1999_EN[31:0]$2010 [0] $flatten\softshell.\cpus[2].core.\flexio.\out_fifo.$0$memwr$\mem$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:139$1999_EN[31:0]$2010 [0] $flatten\softshell.\cpus[2].core.\flexio.\out_fifo.$0$memwr$\mem$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:139$1999_EN[31:0]$2010 [0] $flatten\softshell.\cpus[2].core.\flexio.\out_fifo.$0$memwr$\mem$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:139$1999_EN[31:0]$2010 [0] $flatten\softshell.\cpus[2].core.\flexio.\out_fifo.$0$memwr$\mem$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:139$1999_EN[31:0]$2010 [0] $flatten\softshell.\cpus[2].core.\flexio.\out_fifo.$0$memwr$\mem$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:139$1999_EN[31:0]$2010 [0] $flatten\softshell.\cpus[2].core.\flexio.\out_fifo.$0$memwr$\mem$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:139$1999_EN[31:0]$2010 [0] $flatten\softshell.\cpus[2].core.\flexio.\out_fifo.$0$memwr$\mem$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:139$1999_EN[31:0]$2010 [0] $flatten\softshell.\cpus[2].core.\flexio.\out_fifo.$0$memwr$\mem$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:139$1999_EN[31:0]$2010 [0] $flatten\softshell.\cpus[2].core.\flexio.\out_fifo.$0$memwr$\mem$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:139$1999_EN[31:0]$2010 [0] }
+ Consolidated identical input bits for $mux cell $flatten\softshell.\cpus[2].core.\soc_mem.\ram.$procmux$14899:
+ Old ports: A=8'00000000, B=8'11111111, Y=$flatten\softshell.\cpus[2].core.\soc_mem.\ram.$procmux$14899_Y
+ New ports: A=1'0, B=1'1, Y=$flatten\softshell.\cpus[2].core.\soc_mem.\ram.$procmux$14899_Y [0]
+ New connections: $flatten\softshell.\cpus[2].core.\soc_mem.\ram.$procmux$14899_Y [7:1] = { $flatten\softshell.\cpus[2].core.\soc_mem.\ram.$procmux$14899_Y [0] $flatten\softshell.\cpus[2].core.\soc_mem.\ram.$procmux$14899_Y [0] $flatten\softshell.\cpus[2].core.\soc_mem.\ram.$procmux$14899_Y [0] $flatten\softshell.\cpus[2].core.\soc_mem.\ram.$procmux$14899_Y [0] $flatten\softshell.\cpus[2].core.\soc_mem.\ram.$procmux$14899_Y [0] $flatten\softshell.\cpus[2].core.\soc_mem.\ram.$procmux$14899_Y [0] $flatten\softshell.\cpus[2].core.\soc_mem.\ram.$procmux$14899_Y [0] }
+ Consolidated identical input bits for $mux cell $flatten\softshell.\cpus[2].core.\soc_mem.\ram.$procmux$14911:
+ Old ports: A=8'00000000, B=8'11111111, Y=$flatten\softshell.\cpus[2].core.\soc_mem.\ram.$procmux$14911_Y
+ New ports: A=1'0, B=1'1, Y=$flatten\softshell.\cpus[2].core.\soc_mem.\ram.$procmux$14911_Y [0]
+ New connections: $flatten\softshell.\cpus[2].core.\soc_mem.\ram.$procmux$14911_Y [7:1] = { $flatten\softshell.\cpus[2].core.\soc_mem.\ram.$procmux$14911_Y [0] $flatten\softshell.\cpus[2].core.\soc_mem.\ram.$procmux$14911_Y [0] $flatten\softshell.\cpus[2].core.\soc_mem.\ram.$procmux$14911_Y [0] $flatten\softshell.\cpus[2].core.\soc_mem.\ram.$procmux$14911_Y [0] $flatten\softshell.\cpus[2].core.\soc_mem.\ram.$procmux$14911_Y [0] $flatten\softshell.\cpus[2].core.\soc_mem.\ram.$procmux$14911_Y [0] $flatten\softshell.\cpus[2].core.\soc_mem.\ram.$procmux$14911_Y [0] }
+ Consolidated identical input bits for $mux cell $flatten\softshell.\cpus[2].core.\soc_mem.\ram.$procmux$14923:
+ Old ports: A=8'00000000, B=8'11111111, Y=$flatten\softshell.\cpus[2].core.\soc_mem.\ram.$procmux$14923_Y
+ New ports: A=1'0, B=1'1, Y=$flatten\softshell.\cpus[2].core.\soc_mem.\ram.$procmux$14923_Y [0]
+ New connections: $flatten\softshell.\cpus[2].core.\soc_mem.\ram.$procmux$14923_Y [7:1] = { $flatten\softshell.\cpus[2].core.\soc_mem.\ram.$procmux$14923_Y [0] $flatten\softshell.\cpus[2].core.\soc_mem.\ram.$procmux$14923_Y [0] $flatten\softshell.\cpus[2].core.\soc_mem.\ram.$procmux$14923_Y [0] $flatten\softshell.\cpus[2].core.\soc_mem.\ram.$procmux$14923_Y [0] $flatten\softshell.\cpus[2].core.\soc_mem.\ram.$procmux$14923_Y [0] $flatten\softshell.\cpus[2].core.\soc_mem.\ram.$procmux$14923_Y [0] $flatten\softshell.\cpus[2].core.\soc_mem.\ram.$procmux$14923_Y [0] }
+ Consolidated identical input bits for $mux cell $flatten\softshell.\cpus[2].core.\soc_mem.\ram.$procmux$14935:
+ Old ports: A=8'00000000, B=8'11111111, Y=$flatten\softshell.\cpus[2].core.\soc_mem.\ram.$procmux$14935_Y
+ New ports: A=1'0, B=1'1, Y=$flatten\softshell.\cpus[2].core.\soc_mem.\ram.$procmux$14935_Y [0]
+ New connections: $flatten\softshell.\cpus[2].core.\soc_mem.\ram.$procmux$14935_Y [7:1] = { $flatten\softshell.\cpus[2].core.\soc_mem.\ram.$procmux$14935_Y [0] $flatten\softshell.\cpus[2].core.\soc_mem.\ram.$procmux$14935_Y [0] $flatten\softshell.\cpus[2].core.\soc_mem.\ram.$procmux$14935_Y [0] $flatten\softshell.\cpus[2].core.\soc_mem.\ram.$procmux$14935_Y [0] $flatten\softshell.\cpus[2].core.\soc_mem.\ram.$procmux$14935_Y [0] $flatten\softshell.\cpus[2].core.\soc_mem.\ram.$procmux$14935_Y [0] $flatten\softshell.\cpus[2].core.\soc_mem.\ram.$procmux$14935_Y [0] }
+ New ctrl vector for $pmux cell $flatten\softshell.\flash.\spimemio.$procmux$8944: { $flatten\softshell.\flash.\spimemio.$procmux$8787_CMP $auto$opt_reduce.cc:134:opt_mux$17145 $flatten\softshell.\flash.\spimemio.$procmux$8773_CMP $flatten\softshell.\flash.\spimemio.$procmux$8770_CMP $flatten\softshell.\flash.\spimemio.$procmux$8767_CMP $flatten\softshell.\flash.\spimemio.$procmux$8764_CMP }
+ New ctrl vector for $pmux cell $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$7562: { $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$7570_CMP $auto$opt_reduce.cc:134:opt_mux$17147 $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$7283_CMP $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$7261_CMP }
+ New ctrl vector for $pmux cell $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$7574: $auto$opt_reduce.cc:134:opt_mux$17149
+ Consolidated identical input bits for $mux cell $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.\cpuregs.$procmux$16272:
+ Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/rv_core.v:286$25_EN[31:0]$29
+ New ports: A=1'0, B=1'1, Y=$flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/rv_core.v:286$25_EN[31:0]$29 [0]
+ New connections: $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/rv_core.v:286$25_EN[31:0]$29 [31:1] = { $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/rv_core.v:286$25_EN[31:0]$29 [0] $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/rv_core.v:286$25_EN[31:0]$29 [0] $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/rv_core.v:286$25_EN[31:0]$29 [0] $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/rv_core.v:286$25_EN[31:0]$29 [0] $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/rv_core.v:286$25_EN[31:0]$29 [0] $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/rv_core.v:286$25_EN[31:0]$29 [0] $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/rv_core.v:286$25_EN[31:0]$29 [0] $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/rv_core.v:286$25_EN[31:0]$29 [0] $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/rv_core.v:286$25_EN[31:0]$29 [0] $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/rv_core.v:286$25_EN[31:0]$29 [0] $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/rv_core.v:286$25_EN[31:0]$29 [0] $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/rv_core.v:286$25_EN[31:0]$29 [0] $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/rv_core.v:286$25_EN[31:0]$29 [0] $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/rv_core.v:286$25_EN[31:0]$29 [0] $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/rv_core.v:286$25_EN[31:0]$29 [0] $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/rv_core.v:286$25_EN[31:0]$29 [0] $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/rv_core.v:286$25_EN[31:0]$29 [0] $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/rv_core.v:286$25_EN[31:0]$29 [0] $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/rv_core.v:286$25_EN[31:0]$29 [0] $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/rv_core.v:286$25_EN[31:0]$29 [0] $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/rv_core.v:286$25_EN[31:0]$29 [0] $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/rv_core.v:286$25_EN[31:0]$29 [0] $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/rv_core.v:286$25_EN[31:0]$29 [0] $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/rv_core.v:286$25_EN[31:0]$29 [0] $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/rv_core.v:286$25_EN[31:0]$29 [0] $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/rv_core.v:286$25_EN[31:0]$29 [0] $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/rv_core.v:286$25_EN[31:0]$29 [0] $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/rv_core.v:286$25_EN[31:0]$29 [0] $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/rv_core.v:286$25_EN[31:0]$29 [0] $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/rv_core.v:286$25_EN[31:0]$29 [0] $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/rv_core.v:286$25_EN[31:0]$29 [0] }
+ New ctrl vector for $pmux cell $flatten\softshell.\flash.\spimemio.\xfer.$procmux$8474: $auto$opt_reduce.cc:134:opt_mux$17151
+ New ctrl vector for $pmux cell $flatten\softshell.\flash.\spimemio.\xfer.$procmux$8619: { $flatten\softshell.\flash.\spimemio.\xfer.$procmux$8477_CMP $auto$opt_reduce.cc:134:opt_mux$17153 }
+ New ctrl vector for $pmux cell $flatten\softshell.\flash.\spimemio.\xfer.$procmux$8629: { $flatten\softshell.\flash.\spimemio.\xfer.$procmux$8477_CMP $auto$opt_reduce.cc:134:opt_mux$17155 }
+ New ctrl vector for $pmux cell $flatten\softshell.\flash.\spimemio.\xfer.$procmux$8638: $auto$opt_reduce.cc:134:opt_mux$17157
+ New ctrl vector for $pmux cell $flatten\softshell.\flash.\spimemio.\xfer.$procmux$8646: $auto$opt_reduce.cc:134:opt_mux$17159
+ New ctrl vector for $pmux cell $flatten\softshell.\flash.\spimemio.\xfer.$procmux$8655: { $flatten\softshell.\flash.\spimemio.\xfer.$procmux$8477_CMP $auto$opt_reduce.cc:134:opt_mux$17161 }
+ New ctrl vector for $pmux cell $flatten\softshell.\flash.\spimemio.\xfer.$procmux$8664: $auto$opt_reduce.cc:134:opt_mux$17163
+ New ctrl vector for $pmux cell $flatten\softshell.\flash.\spimemio.\xfer.$procmux$8672: $auto$opt_reduce.cc:134:opt_mux$17165
+ New ctrl vector for $pmux cell $flatten\softshell.\flash.\spimemio.\xfer.$procmux$8681: { $flatten\softshell.\flash.\spimemio.\xfer.$procmux$8477_CMP $auto$opt_reduce.cc:134:opt_mux$17167 }
+ New ctrl vector for $pmux cell $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$7730: $auto$opt_reduce.cc:134:opt_mux$17169
+ Consolidated identical input bits for $mux cell $flatten\softshell.\shared_mem.\ram.$procmux$14955:
+ Old ports: A=8'00000000, B=8'11111111, Y=$flatten\softshell.\shared_mem.\ram.$procmux$14955_Y
+ New ports: A=1'0, B=1'1, Y=$flatten\softshell.\shared_mem.\ram.$procmux$14955_Y [0]
+ New connections: $flatten\softshell.\shared_mem.\ram.$procmux$14955_Y [7:1] = { $flatten\softshell.\shared_mem.\ram.$procmux$14955_Y [0] $flatten\softshell.\shared_mem.\ram.$procmux$14955_Y [0] $flatten\softshell.\shared_mem.\ram.$procmux$14955_Y [0] $flatten\softshell.\shared_mem.\ram.$procmux$14955_Y [0] $flatten\softshell.\shared_mem.\ram.$procmux$14955_Y [0] $flatten\softshell.\shared_mem.\ram.$procmux$14955_Y [0] $flatten\softshell.\shared_mem.\ram.$procmux$14955_Y [0] }
+ Consolidated identical input bits for $mux cell $flatten\softshell.\shared_mem.\ram.$procmux$14967:
+ Old ports: A=8'00000000, B=8'11111111, Y=$flatten\softshell.\shared_mem.\ram.$procmux$14967_Y
+ New ports: A=1'0, B=1'1, Y=$flatten\softshell.\shared_mem.\ram.$procmux$14967_Y [0]
+ New connections: $flatten\softshell.\shared_mem.\ram.$procmux$14967_Y [7:1] = { $flatten\softshell.\shared_mem.\ram.$procmux$14967_Y [0] $flatten\softshell.\shared_mem.\ram.$procmux$14967_Y [0] $flatten\softshell.\shared_mem.\ram.$procmux$14967_Y [0] $flatten\softshell.\shared_mem.\ram.$procmux$14967_Y [0] $flatten\softshell.\shared_mem.\ram.$procmux$14967_Y [0] $flatten\softshell.\shared_mem.\ram.$procmux$14967_Y [0] $flatten\softshell.\shared_mem.\ram.$procmux$14967_Y [0] }
+ Consolidated identical input bits for $mux cell $flatten\softshell.\shared_mem.\ram.$procmux$14979:
+ Old ports: A=8'00000000, B=8'11111111, Y=$flatten\softshell.\shared_mem.\ram.$procmux$14979_Y
+ New ports: A=1'0, B=1'1, Y=$flatten\softshell.\shared_mem.\ram.$procmux$14979_Y [0]
+ New connections: $flatten\softshell.\shared_mem.\ram.$procmux$14979_Y [7:1] = { $flatten\softshell.\shared_mem.\ram.$procmux$14979_Y [0] $flatten\softshell.\shared_mem.\ram.$procmux$14979_Y [0] $flatten\softshell.\shared_mem.\ram.$procmux$14979_Y [0] $flatten\softshell.\shared_mem.\ram.$procmux$14979_Y [0] $flatten\softshell.\shared_mem.\ram.$procmux$14979_Y [0] $flatten\softshell.\shared_mem.\ram.$procmux$14979_Y [0] $flatten\softshell.\shared_mem.\ram.$procmux$14979_Y [0] }
+ Consolidated identical input bits for $mux cell $flatten\softshell.\shared_mem.\ram.$procmux$14991:
+ Old ports: A=8'00000000, B=8'11111111, Y=$flatten\softshell.\shared_mem.\ram.$procmux$14991_Y
+ New ports: A=1'0, B=1'1, Y=$flatten\softshell.\shared_mem.\ram.$procmux$14991_Y [0]
+ New connections: $flatten\softshell.\shared_mem.\ram.$procmux$14991_Y [7:1] = { $flatten\softshell.\shared_mem.\ram.$procmux$14991_Y [0] $flatten\softshell.\shared_mem.\ram.$procmux$14991_Y [0] $flatten\softshell.\shared_mem.\ram.$procmux$14991_Y [0] $flatten\softshell.\shared_mem.\ram.$procmux$14991_Y [0] $flatten\softshell.\shared_mem.\ram.$procmux$14991_Y [0] $flatten\softshell.\shared_mem.\ram.$procmux$14991_Y [0] $flatten\softshell.\shared_mem.\ram.$procmux$14991_Y [0] }
+ New ctrl vector for $pmux cell $flatten\softshell.\uart0.\simpleuart.$procmux$9113: $auto$opt_reduce.cc:134:opt_mux$17171
+ New input vector for $reduce_or cell $auto$opt_reduce.cc:128:opt_mux$16930: { \softshell.cpus[1].core.cpu.picorv32_core.instr_timer \softshell.cpus[1].core.cpu.picorv32_core.instr_maskirq \softshell.cpus[1].core.cpu.picorv32_core.instr_retirq \softshell.cpus[1].core.cpu.picorv32_core.instr_rdinstrh \softshell.cpus[1].core.cpu.picorv32_core.instr_rdinstr \softshell.cpus[1].core.cpu.picorv32_core.instr_rdcycleh \softshell.cpus[1].core.cpu.picorv32_core.instr_rdcycle }
+ New input vector for $reduce_or cell $auto$opt_reduce.cc:128:opt_mux$16932: { \softshell.cpus[1].core.cpu.picorv32_core.is_jalr_addi_slti_sltiu_xori_ori_andi \softshell.cpus[1].core.cpu.picorv32_core.is_slli_srli_srai \softshell.cpus[1].core.cpu.picorv32_core.is_lui_auipc_jal }
+ New input vector for $reduce_or cell $auto$opt_reduce.cc:128:opt_mux$16934: { \softshell.cpus[1].core.cpu.picorv32_core.instr_timer \softshell.cpus[1].core.cpu.picorv32_core.instr_maskirq \softshell.cpus[1].core.cpu.picorv32_core.instr_retirq \softshell.cpus[1].core.cpu.picorv32_core.instr_rdinstrh \softshell.cpus[1].core.cpu.picorv32_core.instr_rdinstr \softshell.cpus[1].core.cpu.picorv32_core.instr_rdcycleh \softshell.cpus[1].core.cpu.picorv32_core.instr_rdcycle }
+ New input vector for $reduce_or cell $auto$opt_reduce.cc:128:opt_mux$16936: { \softshell.cpus[1].core.cpu.picorv32_core.is_jalr_addi_slti_sltiu_xori_ori_andi \softshell.cpus[1].core.cpu.picorv32_core.is_slli_srli_srai \softshell.cpus[1].core.cpu.picorv32_core.is_lui_auipc_jal }
+ New input vector for $reduce_or cell $auto$opt_reduce.cc:128:opt_mux$16938: { \softshell.cpus[1].core.cpu.picorv32_core.instr_timer \softshell.cpus[1].core.cpu.picorv32_core.instr_maskirq \softshell.cpus[1].core.cpu.picorv32_core.instr_retirq \softshell.cpus[1].core.cpu.picorv32_core.instr_rdinstrh \softshell.cpus[1].core.cpu.picorv32_core.instr_rdinstr \softshell.cpus[1].core.cpu.picorv32_core.instr_rdcycleh \softshell.cpus[1].core.cpu.picorv32_core.instr_rdcycle }
+ New input vector for $reduce_or cell $auto$opt_reduce.cc:128:opt_mux$16940: { $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1691$4075_Y \softshell.cpus[1].core.cpu.picorv32_core.instr_timer \softshell.cpus[1].core.cpu.picorv32_core.instr_maskirq \softshell.cpus[1].core.cpu.picorv32_core.instr_retirq \softshell.cpus[1].core.cpu.picorv32_core.instr_rdinstrh \softshell.cpus[1].core.cpu.picorv32_core.instr_rdinstr \softshell.cpus[1].core.cpu.picorv32_core.instr_rdcycleh \softshell.cpus[1].core.cpu.picorv32_core.instr_rdcycle }
+ New input vector for $reduce_or cell $auto$opt_reduce.cc:128:opt_mux$16942: { \softshell.cpus[1].core.cpu.picorv32_core.instr_timer \softshell.cpus[1].core.cpu.picorv32_core.instr_maskirq \softshell.cpus[1].core.cpu.picorv32_core.instr_retirq \softshell.cpus[1].core.cpu.picorv32_core.instr_rdinstrh \softshell.cpus[1].core.cpu.picorv32_core.instr_rdinstr \softshell.cpus[1].core.cpu.picorv32_core.instr_rdcycleh \softshell.cpus[1].core.cpu.picorv32_core.instr_rdcycle }
+ New input vector for $reduce_or cell $auto$opt_reduce.cc:128:opt_mux$17034: { $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1691$4075_Y \softshell.cpus[1].core.cpu.picorv32_core.is_jalr_addi_slti_sltiu_xori_ori_andi \softshell.cpus[1].core.cpu.picorv32_core.is_slli_srli_srai \softshell.cpus[1].core.cpu.picorv32_core.is_lui_auipc_jal \softshell.cpus[1].core.cpu.picorv32_core.instr_timer \softshell.cpus[1].core.cpu.picorv32_core.instr_maskirq \softshell.cpus[1].core.cpu.picorv32_core.instr_retirq \softshell.cpus[1].core.cpu.picorv32_core.instr_rdinstrh \softshell.cpus[1].core.cpu.picorv32_core.instr_rdinstr \softshell.cpus[1].core.cpu.picorv32_core.instr_rdcycleh \softshell.cpus[1].core.cpu.picorv32_core.instr_rdcycle }
+ New input vector for $reduce_or cell $auto$opt_reduce.cc:128:opt_mux$17036: { $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1691$4758_Y \softshell.cpus[0].core.cpu.picorv32_core.is_jalr_addi_slti_sltiu_xori_ori_andi \softshell.cpus[0].core.cpu.picorv32_core.is_slli_srli_srai \softshell.cpus[0].core.cpu.picorv32_core.is_lui_auipc_jal \softshell.cpus[0].core.cpu.picorv32_core.instr_timer \softshell.cpus[0].core.cpu.picorv32_core.instr_maskirq \softshell.cpus[0].core.cpu.picorv32_core.instr_retirq \softshell.cpus[0].core.cpu.picorv32_core.instr_rdinstrh \softshell.cpus[0].core.cpu.picorv32_core.instr_rdinstr \softshell.cpus[0].core.cpu.picorv32_core.instr_rdcycleh \softshell.cpus[0].core.cpu.picorv32_core.instr_rdcycle }
+ New input vector for $reduce_or cell $auto$opt_reduce.cc:128:opt_mux$17040: { \softshell.cpus[0].core.cpu.picorv32_core.instr_timer \softshell.cpus[0].core.cpu.picorv32_core.instr_maskirq \softshell.cpus[0].core.cpu.picorv32_core.instr_retirq \softshell.cpus[0].core.cpu.picorv32_core.instr_rdinstrh \softshell.cpus[0].core.cpu.picorv32_core.instr_rdinstr \softshell.cpus[0].core.cpu.picorv32_core.instr_rdcycleh \softshell.cpus[0].core.cpu.picorv32_core.instr_rdcycle }
+ New input vector for $reduce_or cell $auto$opt_reduce.cc:128:opt_mux$17046: { \softshell.cpus[0].core.cpu.picorv32_core.is_jalr_addi_slti_sltiu_xori_ori_andi \softshell.cpus[0].core.cpu.picorv32_core.is_slli_srli_srai \softshell.cpus[0].core.cpu.picorv32_core.is_lui_auipc_jal }
+ New input vector for $reduce_or cell $auto$opt_reduce.cc:128:opt_mux$17048: { \softshell.cpus[0].core.cpu.picorv32_core.instr_timer \softshell.cpus[0].core.cpu.picorv32_core.instr_maskirq \softshell.cpus[0].core.cpu.picorv32_core.instr_retirq \softshell.cpus[0].core.cpu.picorv32_core.instr_rdinstrh \softshell.cpus[0].core.cpu.picorv32_core.instr_rdinstr \softshell.cpus[0].core.cpu.picorv32_core.instr_rdcycleh \softshell.cpus[0].core.cpu.picorv32_core.instr_rdcycle }
+ New input vector for $reduce_or cell $auto$opt_reduce.cc:128:opt_mux$17054: { \softshell.cpus[0].core.cpu.picorv32_core.is_jalr_addi_slti_sltiu_xori_ori_andi \softshell.cpus[0].core.cpu.picorv32_core.is_slli_srli_srai \softshell.cpus[0].core.cpu.picorv32_core.is_lui_auipc_jal }
+ New input vector for $reduce_or cell $auto$opt_reduce.cc:128:opt_mux$17056: { \softshell.cpus[0].core.cpu.picorv32_core.instr_timer \softshell.cpus[0].core.cpu.picorv32_core.instr_maskirq \softshell.cpus[0].core.cpu.picorv32_core.instr_retirq \softshell.cpus[0].core.cpu.picorv32_core.instr_rdinstrh \softshell.cpus[0].core.cpu.picorv32_core.instr_rdinstr \softshell.cpus[0].core.cpu.picorv32_core.instr_rdcycleh \softshell.cpus[0].core.cpu.picorv32_core.instr_rdcycle }
+ New input vector for $reduce_or cell $auto$opt_reduce.cc:128:opt_mux$17064: { $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1691$3392_Y \softshell.cpus[2].core.cpu.picorv32_core.is_jalr_addi_slti_sltiu_xori_ori_andi \softshell.cpus[2].core.cpu.picorv32_core.is_slli_srli_srai \softshell.cpus[2].core.cpu.picorv32_core.is_lui_auipc_jal \softshell.cpus[2].core.cpu.picorv32_core.instr_timer \softshell.cpus[2].core.cpu.picorv32_core.instr_maskirq \softshell.cpus[2].core.cpu.picorv32_core.instr_retirq \softshell.cpus[2].core.cpu.picorv32_core.instr_rdinstrh \softshell.cpus[2].core.cpu.picorv32_core.instr_rdinstr \softshell.cpus[2].core.cpu.picorv32_core.instr_rdcycleh \softshell.cpus[2].core.cpu.picorv32_core.instr_rdcycle }
+ New input vector for $reduce_or cell $auto$opt_reduce.cc:128:opt_mux$17066: { $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1691$4758_Y \softshell.cpus[0].core.cpu.picorv32_core.instr_timer \softshell.cpus[0].core.cpu.picorv32_core.instr_maskirq \softshell.cpus[0].core.cpu.picorv32_core.instr_retirq \softshell.cpus[0].core.cpu.picorv32_core.instr_rdinstrh \softshell.cpus[0].core.cpu.picorv32_core.instr_rdinstr \softshell.cpus[0].core.cpu.picorv32_core.instr_rdcycleh \softshell.cpus[0].core.cpu.picorv32_core.instr_rdcycle }
+ New input vector for $reduce_or cell $auto$opt_reduce.cc:128:opt_mux$17070: { \softshell.cpus[2].core.cpu.picorv32_core.instr_timer \softshell.cpus[2].core.cpu.picorv32_core.instr_maskirq \softshell.cpus[2].core.cpu.picorv32_core.instr_retirq \softshell.cpus[2].core.cpu.picorv32_core.instr_rdinstrh \softshell.cpus[2].core.cpu.picorv32_core.instr_rdinstr \softshell.cpus[2].core.cpu.picorv32_core.instr_rdcycleh \softshell.cpus[2].core.cpu.picorv32_core.instr_rdcycle }
+ New input vector for $reduce_or cell $auto$opt_reduce.cc:128:opt_mux$17072: { \softshell.cpus[2].core.cpu.picorv32_core.is_jalr_addi_slti_sltiu_xori_ori_andi \softshell.cpus[2].core.cpu.picorv32_core.is_slli_srli_srai \softshell.cpus[2].core.cpu.picorv32_core.is_lui_auipc_jal }
+ New input vector for $reduce_or cell $auto$opt_reduce.cc:128:opt_mux$17074: { \softshell.cpus[2].core.cpu.picorv32_core.instr_timer \softshell.cpus[2].core.cpu.picorv32_core.instr_maskirq \softshell.cpus[2].core.cpu.picorv32_core.instr_retirq \softshell.cpus[2].core.cpu.picorv32_core.instr_rdinstrh \softshell.cpus[2].core.cpu.picorv32_core.instr_rdinstr \softshell.cpus[2].core.cpu.picorv32_core.instr_rdcycleh \softshell.cpus[2].core.cpu.picorv32_core.instr_rdcycle }
+ New input vector for $reduce_or cell $auto$opt_reduce.cc:128:opt_mux$17076: { \softshell.cpus[0].core.cpu.picorv32_core.instr_timer \softshell.cpus[0].core.cpu.picorv32_core.instr_maskirq \softshell.cpus[0].core.cpu.picorv32_core.instr_retirq \softshell.cpus[0].core.cpu.picorv32_core.instr_rdinstrh \softshell.cpus[0].core.cpu.picorv32_core.instr_rdinstr \softshell.cpus[0].core.cpu.picorv32_core.instr_rdcycleh \softshell.cpus[0].core.cpu.picorv32_core.instr_rdcycle }
+ New input vector for $reduce_or cell $auto$opt_reduce.cc:128:opt_mux$17078: { \softshell.cpus[2].core.cpu.picorv32_core.is_jalr_addi_slti_sltiu_xori_ori_andi \softshell.cpus[2].core.cpu.picorv32_core.is_slli_srli_srai \softshell.cpus[2].core.cpu.picorv32_core.is_lui_auipc_jal }
+ New input vector for $reduce_or cell $auto$opt_reduce.cc:128:opt_mux$17080: { \softshell.cpus[2].core.cpu.picorv32_core.instr_timer \softshell.cpus[2].core.cpu.picorv32_core.instr_maskirq \softshell.cpus[2].core.cpu.picorv32_core.instr_retirq \softshell.cpus[2].core.cpu.picorv32_core.instr_rdinstrh \softshell.cpus[2].core.cpu.picorv32_core.instr_rdinstr \softshell.cpus[2].core.cpu.picorv32_core.instr_rdcycleh \softshell.cpus[2].core.cpu.picorv32_core.instr_rdcycle }
+ New input vector for $reduce_or cell $auto$opt_reduce.cc:128:opt_mux$17082: { $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1691$3392_Y \softshell.cpus[2].core.cpu.picorv32_core.instr_timer \softshell.cpus[2].core.cpu.picorv32_core.instr_maskirq \softshell.cpus[2].core.cpu.picorv32_core.instr_retirq \softshell.cpus[2].core.cpu.picorv32_core.instr_rdinstrh \softshell.cpus[2].core.cpu.picorv32_core.instr_rdinstr \softshell.cpus[2].core.cpu.picorv32_core.instr_rdcycleh \softshell.cpus[2].core.cpu.picorv32_core.instr_rdcycle }
+ New input vector for $reduce_or cell $auto$opt_reduce.cc:128:opt_mux$17084: { \softshell.cpus[2].core.cpu.picorv32_core.instr_timer \softshell.cpus[2].core.cpu.picorv32_core.instr_maskirq \softshell.cpus[2].core.cpu.picorv32_core.instr_retirq \softshell.cpus[2].core.cpu.picorv32_core.instr_rdinstrh \softshell.cpus[2].core.cpu.picorv32_core.instr_rdinstr \softshell.cpus[2].core.cpu.picorv32_core.instr_rdcycleh \softshell.cpus[2].core.cpu.picorv32_core.instr_rdcycle }
+ Optimizing cells in module \user_proj_example.
+ Consolidated identical input bits for $mux cell $flatten\softshell.\cpus[0].core.\soc_mem.\ram.$procmux$14901:
+ Old ports: A=8'00000000, B=$flatten\softshell.\cpus[0].core.\soc_mem.\ram.$procmux$14899_Y, Y=$flatten\softshell.\cpus[0].core.\soc_mem.\ram.$0$memwr$\ram0$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:103$2788_EN[7:0]$2795
+ New ports: A=1'0, B=$flatten\softshell.\cpus[0].core.\soc_mem.\ram.$procmux$14899_Y [0], Y=$flatten\softshell.\cpus[0].core.\soc_mem.\ram.$0$memwr$\ram0$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:103$2788_EN[7:0]$2795 [0]
+ New connections: $flatten\softshell.\cpus[0].core.\soc_mem.\ram.$0$memwr$\ram0$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:103$2788_EN[7:0]$2795 [7:1] = { $flatten\softshell.\cpus[0].core.\soc_mem.\ram.$0$memwr$\ram0$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:103$2788_EN[7:0]$2795 [0] $flatten\softshell.\cpus[0].core.\soc_mem.\ram.$0$memwr$\ram0$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:103$2788_EN[7:0]$2795 [0] $flatten\softshell.\cpus[0].core.\soc_mem.\ram.$0$memwr$\ram0$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:103$2788_EN[7:0]$2795 [0] $flatten\softshell.\cpus[0].core.\soc_mem.\ram.$0$memwr$\ram0$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:103$2788_EN[7:0]$2795 [0] $flatten\softshell.\cpus[0].core.\soc_mem.\ram.$0$memwr$\ram0$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:103$2788_EN[7:0]$2795 [0] $flatten\softshell.\cpus[0].core.\soc_mem.\ram.$0$memwr$\ram0$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:103$2788_EN[7:0]$2795 [0] $flatten\softshell.\cpus[0].core.\soc_mem.\ram.$0$memwr$\ram0$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:103$2788_EN[7:0]$2795 [0] }
+ Consolidated identical input bits for $mux cell $flatten\softshell.\cpus[0].core.\soc_mem.\ram.$procmux$14913:
+ Old ports: A=8'00000000, B=$flatten\softshell.\cpus[0].core.\soc_mem.\ram.$procmux$14911_Y, Y=$flatten\softshell.\cpus[0].core.\soc_mem.\ram.$0$memwr$\ram1$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:105$2789_EN[7:0]$2798
+ New ports: A=1'0, B=$flatten\softshell.\cpus[0].core.\soc_mem.\ram.$procmux$14911_Y [0], Y=$flatten\softshell.\cpus[0].core.\soc_mem.\ram.$0$memwr$\ram1$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:105$2789_EN[7:0]$2798 [0]
+ New connections: $flatten\softshell.\cpus[0].core.\soc_mem.\ram.$0$memwr$\ram1$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:105$2789_EN[7:0]$2798 [7:1] = { $flatten\softshell.\cpus[0].core.\soc_mem.\ram.$0$memwr$\ram1$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:105$2789_EN[7:0]$2798 [0] $flatten\softshell.\cpus[0].core.\soc_mem.\ram.$0$memwr$\ram1$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:105$2789_EN[7:0]$2798 [0] $flatten\softshell.\cpus[0].core.\soc_mem.\ram.$0$memwr$\ram1$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:105$2789_EN[7:0]$2798 [0] $flatten\softshell.\cpus[0].core.\soc_mem.\ram.$0$memwr$\ram1$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:105$2789_EN[7:0]$2798 [0] $flatten\softshell.\cpus[0].core.\soc_mem.\ram.$0$memwr$\ram1$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:105$2789_EN[7:0]$2798 [0] $flatten\softshell.\cpus[0].core.\soc_mem.\ram.$0$memwr$\ram1$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:105$2789_EN[7:0]$2798 [0] $flatten\softshell.\cpus[0].core.\soc_mem.\ram.$0$memwr$\ram1$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:105$2789_EN[7:0]$2798 [0] }
+ Consolidated identical input bits for $mux cell $flatten\softshell.\cpus[0].core.\soc_mem.\ram.$procmux$14925:
+ Old ports: A=8'00000000, B=$flatten\softshell.\cpus[0].core.\soc_mem.\ram.$procmux$14923_Y, Y=$flatten\softshell.\cpus[0].core.\soc_mem.\ram.$0$memwr$\ram2$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:107$2790_EN[7:0]$2801
+ New ports: A=1'0, B=$flatten\softshell.\cpus[0].core.\soc_mem.\ram.$procmux$14923_Y [0], Y=$flatten\softshell.\cpus[0].core.\soc_mem.\ram.$0$memwr$\ram2$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:107$2790_EN[7:0]$2801 [0]
+ New connections: $flatten\softshell.\cpus[0].core.\soc_mem.\ram.$0$memwr$\ram2$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:107$2790_EN[7:0]$2801 [7:1] = { $flatten\softshell.\cpus[0].core.\soc_mem.\ram.$0$memwr$\ram2$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:107$2790_EN[7:0]$2801 [0] $flatten\softshell.\cpus[0].core.\soc_mem.\ram.$0$memwr$\ram2$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:107$2790_EN[7:0]$2801 [0] $flatten\softshell.\cpus[0].core.\soc_mem.\ram.$0$memwr$\ram2$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:107$2790_EN[7:0]$2801 [0] $flatten\softshell.\cpus[0].core.\soc_mem.\ram.$0$memwr$\ram2$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:107$2790_EN[7:0]$2801 [0] $flatten\softshell.\cpus[0].core.\soc_mem.\ram.$0$memwr$\ram2$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:107$2790_EN[7:0]$2801 [0] $flatten\softshell.\cpus[0].core.\soc_mem.\ram.$0$memwr$\ram2$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:107$2790_EN[7:0]$2801 [0] $flatten\softshell.\cpus[0].core.\soc_mem.\ram.$0$memwr$\ram2$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:107$2790_EN[7:0]$2801 [0] }
+ Consolidated identical input bits for $mux cell $flatten\softshell.\cpus[0].core.\soc_mem.\ram.$procmux$14937:
+ Old ports: A=8'00000000, B=$flatten\softshell.\cpus[0].core.\soc_mem.\ram.$procmux$14935_Y, Y=$flatten\softshell.\cpus[0].core.\soc_mem.\ram.$0$memwr$\ram3$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:109$2791_EN[7:0]$2804
+ New ports: A=1'0, B=$flatten\softshell.\cpus[0].core.\soc_mem.\ram.$procmux$14935_Y [0], Y=$flatten\softshell.\cpus[0].core.\soc_mem.\ram.$0$memwr$\ram3$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:109$2791_EN[7:0]$2804 [0]
+ New connections: $flatten\softshell.\cpus[0].core.\soc_mem.\ram.$0$memwr$\ram3$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:109$2791_EN[7:0]$2804 [7:1] = { $flatten\softshell.\cpus[0].core.\soc_mem.\ram.$0$memwr$\ram3$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:109$2791_EN[7:0]$2804 [0] $flatten\softshell.\cpus[0].core.\soc_mem.\ram.$0$memwr$\ram3$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:109$2791_EN[7:0]$2804 [0] $flatten\softshell.\cpus[0].core.\soc_mem.\ram.$0$memwr$\ram3$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:109$2791_EN[7:0]$2804 [0] $flatten\softshell.\cpus[0].core.\soc_mem.\ram.$0$memwr$\ram3$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:109$2791_EN[7:0]$2804 [0] $flatten\softshell.\cpus[0].core.\soc_mem.\ram.$0$memwr$\ram3$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:109$2791_EN[7:0]$2804 [0] $flatten\softshell.\cpus[0].core.\soc_mem.\ram.$0$memwr$\ram3$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:109$2791_EN[7:0]$2804 [0] $flatten\softshell.\cpus[0].core.\soc_mem.\ram.$0$memwr$\ram3$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:109$2791_EN[7:0]$2804 [0] }
+ Consolidated identical input bits for $mux cell $flatten\softshell.\cpus[1].core.\soc_mem.\ram.$procmux$14901:
+ Old ports: A=8'00000000, B=$flatten\softshell.\cpus[1].core.\soc_mem.\ram.$procmux$14899_Y, Y=$flatten\softshell.\cpus[1].core.\soc_mem.\ram.$0$memwr$\ram0$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:103$2788_EN[7:0]$2795
+ New ports: A=1'0, B=$flatten\softshell.\cpus[1].core.\soc_mem.\ram.$procmux$14899_Y [0], Y=$flatten\softshell.\cpus[1].core.\soc_mem.\ram.$0$memwr$\ram0$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:103$2788_EN[7:0]$2795 [0]
+ New connections: $flatten\softshell.\cpus[1].core.\soc_mem.\ram.$0$memwr$\ram0$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:103$2788_EN[7:0]$2795 [7:1] = { $flatten\softshell.\cpus[1].core.\soc_mem.\ram.$0$memwr$\ram0$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:103$2788_EN[7:0]$2795 [0] $flatten\softshell.\cpus[1].core.\soc_mem.\ram.$0$memwr$\ram0$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:103$2788_EN[7:0]$2795 [0] $flatten\softshell.\cpus[1].core.\soc_mem.\ram.$0$memwr$\ram0$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:103$2788_EN[7:0]$2795 [0] $flatten\softshell.\cpus[1].core.\soc_mem.\ram.$0$memwr$\ram0$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:103$2788_EN[7:0]$2795 [0] $flatten\softshell.\cpus[1].core.\soc_mem.\ram.$0$memwr$\ram0$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:103$2788_EN[7:0]$2795 [0] $flatten\softshell.\cpus[1].core.\soc_mem.\ram.$0$memwr$\ram0$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:103$2788_EN[7:0]$2795 [0] $flatten\softshell.\cpus[1].core.\soc_mem.\ram.$0$memwr$\ram0$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:103$2788_EN[7:0]$2795 [0] }
+ Consolidated identical input bits for $mux cell $flatten\softshell.\cpus[1].core.\soc_mem.\ram.$procmux$14913:
+ Old ports: A=8'00000000, B=$flatten\softshell.\cpus[1].core.\soc_mem.\ram.$procmux$14911_Y, Y=$flatten\softshell.\cpus[1].core.\soc_mem.\ram.$0$memwr$\ram1$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:105$2789_EN[7:0]$2798
+ New ports: A=1'0, B=$flatten\softshell.\cpus[1].core.\soc_mem.\ram.$procmux$14911_Y [0], Y=$flatten\softshell.\cpus[1].core.\soc_mem.\ram.$0$memwr$\ram1$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:105$2789_EN[7:0]$2798 [0]
+ New connections: $flatten\softshell.\cpus[1].core.\soc_mem.\ram.$0$memwr$\ram1$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:105$2789_EN[7:0]$2798 [7:1] = { $flatten\softshell.\cpus[1].core.\soc_mem.\ram.$0$memwr$\ram1$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:105$2789_EN[7:0]$2798 [0] $flatten\softshell.\cpus[1].core.\soc_mem.\ram.$0$memwr$\ram1$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:105$2789_EN[7:0]$2798 [0] $flatten\softshell.\cpus[1].core.\soc_mem.\ram.$0$memwr$\ram1$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:105$2789_EN[7:0]$2798 [0] $flatten\softshell.\cpus[1].core.\soc_mem.\ram.$0$memwr$\ram1$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:105$2789_EN[7:0]$2798 [0] $flatten\softshell.\cpus[1].core.\soc_mem.\ram.$0$memwr$\ram1$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:105$2789_EN[7:0]$2798 [0] $flatten\softshell.\cpus[1].core.\soc_mem.\ram.$0$memwr$\ram1$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:105$2789_EN[7:0]$2798 [0] $flatten\softshell.\cpus[1].core.\soc_mem.\ram.$0$memwr$\ram1$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:105$2789_EN[7:0]$2798 [0] }
+ Consolidated identical input bits for $mux cell $flatten\softshell.\cpus[1].core.\soc_mem.\ram.$procmux$14925:
+ Old ports: A=8'00000000, B=$flatten\softshell.\cpus[1].core.\soc_mem.\ram.$procmux$14923_Y, Y=$flatten\softshell.\cpus[1].core.\soc_mem.\ram.$0$memwr$\ram2$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:107$2790_EN[7:0]$2801
+ New ports: A=1'0, B=$flatten\softshell.\cpus[1].core.\soc_mem.\ram.$procmux$14923_Y [0], Y=$flatten\softshell.\cpus[1].core.\soc_mem.\ram.$0$memwr$\ram2$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:107$2790_EN[7:0]$2801 [0]
+ New connections: $flatten\softshell.\cpus[1].core.\soc_mem.\ram.$0$memwr$\ram2$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:107$2790_EN[7:0]$2801 [7:1] = { $flatten\softshell.\cpus[1].core.\soc_mem.\ram.$0$memwr$\ram2$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:107$2790_EN[7:0]$2801 [0] $flatten\softshell.\cpus[1].core.\soc_mem.\ram.$0$memwr$\ram2$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:107$2790_EN[7:0]$2801 [0] $flatten\softshell.\cpus[1].core.\soc_mem.\ram.$0$memwr$\ram2$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:107$2790_EN[7:0]$2801 [0] $flatten\softshell.\cpus[1].core.\soc_mem.\ram.$0$memwr$\ram2$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:107$2790_EN[7:0]$2801 [0] $flatten\softshell.\cpus[1].core.\soc_mem.\ram.$0$memwr$\ram2$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:107$2790_EN[7:0]$2801 [0] $flatten\softshell.\cpus[1].core.\soc_mem.\ram.$0$memwr$\ram2$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:107$2790_EN[7:0]$2801 [0] $flatten\softshell.\cpus[1].core.\soc_mem.\ram.$0$memwr$\ram2$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:107$2790_EN[7:0]$2801 [0] }
+ Consolidated identical input bits for $mux cell $flatten\softshell.\cpus[1].core.\soc_mem.\ram.$procmux$14937:
+ Old ports: A=8'00000000, B=$flatten\softshell.\cpus[1].core.\soc_mem.\ram.$procmux$14935_Y, Y=$flatten\softshell.\cpus[1].core.\soc_mem.\ram.$0$memwr$\ram3$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:109$2791_EN[7:0]$2804
+ New ports: A=1'0, B=$flatten\softshell.\cpus[1].core.\soc_mem.\ram.$procmux$14935_Y [0], Y=$flatten\softshell.\cpus[1].core.\soc_mem.\ram.$0$memwr$\ram3$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:109$2791_EN[7:0]$2804 [0]
+ New connections: $flatten\softshell.\cpus[1].core.\soc_mem.\ram.$0$memwr$\ram3$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:109$2791_EN[7:0]$2804 [7:1] = { $flatten\softshell.\cpus[1].core.\soc_mem.\ram.$0$memwr$\ram3$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:109$2791_EN[7:0]$2804 [0] $flatten\softshell.\cpus[1].core.\soc_mem.\ram.$0$memwr$\ram3$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:109$2791_EN[7:0]$2804 [0] $flatten\softshell.\cpus[1].core.\soc_mem.\ram.$0$memwr$\ram3$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:109$2791_EN[7:0]$2804 [0] $flatten\softshell.\cpus[1].core.\soc_mem.\ram.$0$memwr$\ram3$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:109$2791_EN[7:0]$2804 [0] $flatten\softshell.\cpus[1].core.\soc_mem.\ram.$0$memwr$\ram3$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:109$2791_EN[7:0]$2804 [0] $flatten\softshell.\cpus[1].core.\soc_mem.\ram.$0$memwr$\ram3$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:109$2791_EN[7:0]$2804 [0] $flatten\softshell.\cpus[1].core.\soc_mem.\ram.$0$memwr$\ram3$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:109$2791_EN[7:0]$2804 [0] }
+ Consolidated identical input bits for $mux cell $flatten\softshell.\cpus[2].core.\soc_mem.\ram.$procmux$14901:
+ Old ports: A=8'00000000, B=$flatten\softshell.\cpus[2].core.\soc_mem.\ram.$procmux$14899_Y, Y=$flatten\softshell.\cpus[2].core.\soc_mem.\ram.$0$memwr$\ram0$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:103$2788_EN[7:0]$2795
+ New ports: A=1'0, B=$flatten\softshell.\cpus[2].core.\soc_mem.\ram.$procmux$14899_Y [0], Y=$flatten\softshell.\cpus[2].core.\soc_mem.\ram.$0$memwr$\ram0$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:103$2788_EN[7:0]$2795 [0]
+ New connections: $flatten\softshell.\cpus[2].core.\soc_mem.\ram.$0$memwr$\ram0$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:103$2788_EN[7:0]$2795 [7:1] = { $flatten\softshell.\cpus[2].core.\soc_mem.\ram.$0$memwr$\ram0$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:103$2788_EN[7:0]$2795 [0] $flatten\softshell.\cpus[2].core.\soc_mem.\ram.$0$memwr$\ram0$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:103$2788_EN[7:0]$2795 [0] $flatten\softshell.\cpus[2].core.\soc_mem.\ram.$0$memwr$\ram0$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:103$2788_EN[7:0]$2795 [0] $flatten\softshell.\cpus[2].core.\soc_mem.\ram.$0$memwr$\ram0$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:103$2788_EN[7:0]$2795 [0] $flatten\softshell.\cpus[2].core.\soc_mem.\ram.$0$memwr$\ram0$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:103$2788_EN[7:0]$2795 [0] $flatten\softshell.\cpus[2].core.\soc_mem.\ram.$0$memwr$\ram0$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:103$2788_EN[7:0]$2795 [0] $flatten\softshell.\cpus[2].core.\soc_mem.\ram.$0$memwr$\ram0$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:103$2788_EN[7:0]$2795 [0] }
+ Consolidated identical input bits for $mux cell $flatten\softshell.\cpus[2].core.\soc_mem.\ram.$procmux$14913:
+ Old ports: A=8'00000000, B=$flatten\softshell.\cpus[2].core.\soc_mem.\ram.$procmux$14911_Y, Y=$flatten\softshell.\cpus[2].core.\soc_mem.\ram.$0$memwr$\ram1$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:105$2789_EN[7:0]$2798
+ New ports: A=1'0, B=$flatten\softshell.\cpus[2].core.\soc_mem.\ram.$procmux$14911_Y [0], Y=$flatten\softshell.\cpus[2].core.\soc_mem.\ram.$0$memwr$\ram1$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:105$2789_EN[7:0]$2798 [0]
+ New connections: $flatten\softshell.\cpus[2].core.\soc_mem.\ram.$0$memwr$\ram1$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:105$2789_EN[7:0]$2798 [7:1] = { $flatten\softshell.\cpus[2].core.\soc_mem.\ram.$0$memwr$\ram1$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:105$2789_EN[7:0]$2798 [0] $flatten\softshell.\cpus[2].core.\soc_mem.\ram.$0$memwr$\ram1$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:105$2789_EN[7:0]$2798 [0] $flatten\softshell.\cpus[2].core.\soc_mem.\ram.$0$memwr$\ram1$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:105$2789_EN[7:0]$2798 [0] $flatten\softshell.\cpus[2].core.\soc_mem.\ram.$0$memwr$\ram1$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:105$2789_EN[7:0]$2798 [0] $flatten\softshell.\cpus[2].core.\soc_mem.\ram.$0$memwr$\ram1$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:105$2789_EN[7:0]$2798 [0] $flatten\softshell.\cpus[2].core.\soc_mem.\ram.$0$memwr$\ram1$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:105$2789_EN[7:0]$2798 [0] $flatten\softshell.\cpus[2].core.\soc_mem.\ram.$0$memwr$\ram1$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:105$2789_EN[7:0]$2798 [0] }
+ Consolidated identical input bits for $mux cell $flatten\softshell.\cpus[2].core.\soc_mem.\ram.$procmux$14925:
+ Old ports: A=8'00000000, B=$flatten\softshell.\cpus[2].core.\soc_mem.\ram.$procmux$14923_Y, Y=$flatten\softshell.\cpus[2].core.\soc_mem.\ram.$0$memwr$\ram2$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:107$2790_EN[7:0]$2801
+ New ports: A=1'0, B=$flatten\softshell.\cpus[2].core.\soc_mem.\ram.$procmux$14923_Y [0], Y=$flatten\softshell.\cpus[2].core.\soc_mem.\ram.$0$memwr$\ram2$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:107$2790_EN[7:0]$2801 [0]
+ New connections: $flatten\softshell.\cpus[2].core.\soc_mem.\ram.$0$memwr$\ram2$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:107$2790_EN[7:0]$2801 [7:1] = { $flatten\softshell.\cpus[2].core.\soc_mem.\ram.$0$memwr$\ram2$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:107$2790_EN[7:0]$2801 [0] $flatten\softshell.\cpus[2].core.\soc_mem.\ram.$0$memwr$\ram2$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:107$2790_EN[7:0]$2801 [0] $flatten\softshell.\cpus[2].core.\soc_mem.\ram.$0$memwr$\ram2$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:107$2790_EN[7:0]$2801 [0] $flatten\softshell.\cpus[2].core.\soc_mem.\ram.$0$memwr$\ram2$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:107$2790_EN[7:0]$2801 [0] $flatten\softshell.\cpus[2].core.\soc_mem.\ram.$0$memwr$\ram2$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:107$2790_EN[7:0]$2801 [0] $flatten\softshell.\cpus[2].core.\soc_mem.\ram.$0$memwr$\ram2$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:107$2790_EN[7:0]$2801 [0] $flatten\softshell.\cpus[2].core.\soc_mem.\ram.$0$memwr$\ram2$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:107$2790_EN[7:0]$2801 [0] }
+ Consolidated identical input bits for $mux cell $flatten\softshell.\cpus[2].core.\soc_mem.\ram.$procmux$14937:
+ Old ports: A=8'00000000, B=$flatten\softshell.\cpus[2].core.\soc_mem.\ram.$procmux$14935_Y, Y=$flatten\softshell.\cpus[2].core.\soc_mem.\ram.$0$memwr$\ram3$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:109$2791_EN[7:0]$2804
+ New ports: A=1'0, B=$flatten\softshell.\cpus[2].core.\soc_mem.\ram.$procmux$14935_Y [0], Y=$flatten\softshell.\cpus[2].core.\soc_mem.\ram.$0$memwr$\ram3$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:109$2791_EN[7:0]$2804 [0]
+ New connections: $flatten\softshell.\cpus[2].core.\soc_mem.\ram.$0$memwr$\ram3$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:109$2791_EN[7:0]$2804 [7:1] = { $flatten\softshell.\cpus[2].core.\soc_mem.\ram.$0$memwr$\ram3$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:109$2791_EN[7:0]$2804 [0] $flatten\softshell.\cpus[2].core.\soc_mem.\ram.$0$memwr$\ram3$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:109$2791_EN[7:0]$2804 [0] $flatten\softshell.\cpus[2].core.\soc_mem.\ram.$0$memwr$\ram3$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:109$2791_EN[7:0]$2804 [0] $flatten\softshell.\cpus[2].core.\soc_mem.\ram.$0$memwr$\ram3$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:109$2791_EN[7:0]$2804 [0] $flatten\softshell.\cpus[2].core.\soc_mem.\ram.$0$memwr$\ram3$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:109$2791_EN[7:0]$2804 [0] $flatten\softshell.\cpus[2].core.\soc_mem.\ram.$0$memwr$\ram3$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:109$2791_EN[7:0]$2804 [0] $flatten\softshell.\cpus[2].core.\soc_mem.\ram.$0$memwr$\ram3$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:109$2791_EN[7:0]$2804 [0] }
+ Consolidated identical input bits for $mux cell $flatten\softshell.\shared_mem.\ram.$procmux$14957:
+ Old ports: A=8'00000000, B=$flatten\softshell.\shared_mem.\ram.$procmux$14955_Y, Y=$flatten\softshell.\shared_mem.\ram.$0$memwr$\ram0$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:103$2762_EN[7:0]$2769
+ New ports: A=1'0, B=$flatten\softshell.\shared_mem.\ram.$procmux$14955_Y [0], Y=$flatten\softshell.\shared_mem.\ram.$0$memwr$\ram0$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:103$2762_EN[7:0]$2769 [0]
+ New connections: $flatten\softshell.\shared_mem.\ram.$0$memwr$\ram0$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:103$2762_EN[7:0]$2769 [7:1] = { $flatten\softshell.\shared_mem.\ram.$0$memwr$\ram0$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:103$2762_EN[7:0]$2769 [0] $flatten\softshell.\shared_mem.\ram.$0$memwr$\ram0$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:103$2762_EN[7:0]$2769 [0] $flatten\softshell.\shared_mem.\ram.$0$memwr$\ram0$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:103$2762_EN[7:0]$2769 [0] $flatten\softshell.\shared_mem.\ram.$0$memwr$\ram0$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:103$2762_EN[7:0]$2769 [0] $flatten\softshell.\shared_mem.\ram.$0$memwr$\ram0$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:103$2762_EN[7:0]$2769 [0] $flatten\softshell.\shared_mem.\ram.$0$memwr$\ram0$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:103$2762_EN[7:0]$2769 [0] $flatten\softshell.\shared_mem.\ram.$0$memwr$\ram0$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:103$2762_EN[7:0]$2769 [0] }
+ Consolidated identical input bits for $mux cell $flatten\softshell.\shared_mem.\ram.$procmux$14969:
+ Old ports: A=8'00000000, B=$flatten\softshell.\shared_mem.\ram.$procmux$14967_Y, Y=$flatten\softshell.\shared_mem.\ram.$0$memwr$\ram1$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:105$2763_EN[7:0]$2772
+ New ports: A=1'0, B=$flatten\softshell.\shared_mem.\ram.$procmux$14967_Y [0], Y=$flatten\softshell.\shared_mem.\ram.$0$memwr$\ram1$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:105$2763_EN[7:0]$2772 [0]
+ New connections: $flatten\softshell.\shared_mem.\ram.$0$memwr$\ram1$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:105$2763_EN[7:0]$2772 [7:1] = { $flatten\softshell.\shared_mem.\ram.$0$memwr$\ram1$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:105$2763_EN[7:0]$2772 [0] $flatten\softshell.\shared_mem.\ram.$0$memwr$\ram1$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:105$2763_EN[7:0]$2772 [0] $flatten\softshell.\shared_mem.\ram.$0$memwr$\ram1$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:105$2763_EN[7:0]$2772 [0] $flatten\softshell.\shared_mem.\ram.$0$memwr$\ram1$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:105$2763_EN[7:0]$2772 [0] $flatten\softshell.\shared_mem.\ram.$0$memwr$\ram1$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:105$2763_EN[7:0]$2772 [0] $flatten\softshell.\shared_mem.\ram.$0$memwr$\ram1$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:105$2763_EN[7:0]$2772 [0] $flatten\softshell.\shared_mem.\ram.$0$memwr$\ram1$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:105$2763_EN[7:0]$2772 [0] }
+ Consolidated identical input bits for $mux cell $flatten\softshell.\shared_mem.\ram.$procmux$14981:
+ Old ports: A=8'00000000, B=$flatten\softshell.\shared_mem.\ram.$procmux$14979_Y, Y=$flatten\softshell.\shared_mem.\ram.$0$memwr$\ram2$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:107$2764_EN[7:0]$2775
+ New ports: A=1'0, B=$flatten\softshell.\shared_mem.\ram.$procmux$14979_Y [0], Y=$flatten\softshell.\shared_mem.\ram.$0$memwr$\ram2$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:107$2764_EN[7:0]$2775 [0]
+ New connections: $flatten\softshell.\shared_mem.\ram.$0$memwr$\ram2$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:107$2764_EN[7:0]$2775 [7:1] = { $flatten\softshell.\shared_mem.\ram.$0$memwr$\ram2$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:107$2764_EN[7:0]$2775 [0] $flatten\softshell.\shared_mem.\ram.$0$memwr$\ram2$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:107$2764_EN[7:0]$2775 [0] $flatten\softshell.\shared_mem.\ram.$0$memwr$\ram2$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:107$2764_EN[7:0]$2775 [0] $flatten\softshell.\shared_mem.\ram.$0$memwr$\ram2$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:107$2764_EN[7:0]$2775 [0] $flatten\softshell.\shared_mem.\ram.$0$memwr$\ram2$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:107$2764_EN[7:0]$2775 [0] $flatten\softshell.\shared_mem.\ram.$0$memwr$\ram2$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:107$2764_EN[7:0]$2775 [0] $flatten\softshell.\shared_mem.\ram.$0$memwr$\ram2$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:107$2764_EN[7:0]$2775 [0] }
+ Consolidated identical input bits for $mux cell $flatten\softshell.\shared_mem.\ram.$procmux$14993:
+ Old ports: A=8'00000000, B=$flatten\softshell.\shared_mem.\ram.$procmux$14991_Y, Y=$flatten\softshell.\shared_mem.\ram.$0$memwr$\ram3$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:109$2765_EN[7:0]$2778
+ New ports: A=1'0, B=$flatten\softshell.\shared_mem.\ram.$procmux$14991_Y [0], Y=$flatten\softshell.\shared_mem.\ram.$0$memwr$\ram3$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:109$2765_EN[7:0]$2778 [0]
+ New connections: $flatten\softshell.\shared_mem.\ram.$0$memwr$\ram3$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:109$2765_EN[7:0]$2778 [7:1] = { $flatten\softshell.\shared_mem.\ram.$0$memwr$\ram3$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:109$2765_EN[7:0]$2778 [0] $flatten\softshell.\shared_mem.\ram.$0$memwr$\ram3$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:109$2765_EN[7:0]$2778 [0] $flatten\softshell.\shared_mem.\ram.$0$memwr$\ram3$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:109$2765_EN[7:0]$2778 [0] $flatten\softshell.\shared_mem.\ram.$0$memwr$\ram3$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:109$2765_EN[7:0]$2778 [0] $flatten\softshell.\shared_mem.\ram.$0$memwr$\ram3$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:109$2765_EN[7:0]$2778 [0] $flatten\softshell.\shared_mem.\ram.$0$memwr$\ram3$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:109$2765_EN[7:0]$2778 [0] $flatten\softshell.\shared_mem.\ram.$0$memwr$\ram3$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:109$2765_EN[7:0]$2778 [0] }
+ Optimizing cells in module \user_proj_example.
+Performed a total of 181 changes.
+
+23.7.5. Executing OPT_MERGE pass (detect identical cells).
+Finding identical cells in module `\user_proj_example'.
+<suppressed ~531 debug messages>
+Removed a total of 177 cells.
+
+23.7.6. Executing OPT_DFF pass (perform DFF optimizations).
+Setting constant 0-bit at position 32 on $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procdff$16693 ($dff) from module user_proj_example.
+Setting constant 0-bit at position 33 on $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procdff$16693 ($dff) from module user_proj_example.
+Setting constant 0-bit at position 34 on $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procdff$16693 ($dff) from module user_proj_example.
+Setting constant 0-bit at position 35 on $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procdff$16693 ($dff) from module user_proj_example.
+Setting constant 0-bit at position 36 on $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procdff$16693 ($dff) from module user_proj_example.
+Setting constant 0-bit at position 37 on $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procdff$16693 ($dff) from module user_proj_example.
+Setting constant 0-bit at position 38 on $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procdff$16693 ($dff) from module user_proj_example.
+Setting constant 0-bit at position 39 on $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procdff$16693 ($dff) from module user_proj_example.
+Setting constant 0-bit at position 40 on $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procdff$16693 ($dff) from module user_proj_example.
+Setting constant 0-bit at position 41 on $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procdff$16693 ($dff) from module user_proj_example.
+Setting constant 0-bit at position 42 on $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procdff$16693 ($dff) from module user_proj_example.
+Setting constant 0-bit at position 43 on $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procdff$16693 ($dff) from module user_proj_example.
+Setting constant 0-bit at position 44 on $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procdff$16693 ($dff) from module user_proj_example.
+Setting constant 0-bit at position 45 on $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procdff$16693 ($dff) from module user_proj_example.
+Setting constant 0-bit at position 46 on $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procdff$16693 ($dff) from module user_proj_example.
+Setting constant 0-bit at position 47 on $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procdff$16693 ($dff) from module user_proj_example.
+Setting constant 0-bit at position 48 on $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procdff$16693 ($dff) from module user_proj_example.
+Setting constant 0-bit at position 49 on $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procdff$16693 ($dff) from module user_proj_example.
+Setting constant 0-bit at position 50 on $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procdff$16693 ($dff) from module user_proj_example.
+Setting constant 0-bit at position 51 on $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procdff$16693 ($dff) from module user_proj_example.
+Setting constant 0-bit at position 52 on $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procdff$16693 ($dff) from module user_proj_example.
+Setting constant 0-bit at position 53 on $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procdff$16693 ($dff) from module user_proj_example.
+Setting constant 0-bit at position 54 on $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procdff$16693 ($dff) from module user_proj_example.
+Setting constant 0-bit at position 55 on $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procdff$16693 ($dff) from module user_proj_example.
+Setting constant 0-bit at position 56 on $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procdff$16693 ($dff) from module user_proj_example.
+Setting constant 0-bit at position 57 on $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procdff$16693 ($dff) from module user_proj_example.
+Setting constant 0-bit at position 58 on $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procdff$16693 ($dff) from module user_proj_example.
+Setting constant 0-bit at position 59 on $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procdff$16693 ($dff) from module user_proj_example.
+Setting constant 0-bit at position 60 on $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procdff$16693 ($dff) from module user_proj_example.
+Setting constant 0-bit at position 61 on $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procdff$16693 ($dff) from module user_proj_example.
+Setting constant 0-bit at position 62 on $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procdff$16693 ($dff) from module user_proj_example.
+Setting constant 0-bit at position 63 on $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procdff$16693 ($dff) from module user_proj_example.
+Setting constant 0-bit at position 32 on $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procdff$16333 ($dff) from module user_proj_example.
+Setting constant 0-bit at position 33 on $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procdff$16333 ($dff) from module user_proj_example.
+Setting constant 0-bit at position 34 on $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procdff$16333 ($dff) from module user_proj_example.
+Setting constant 0-bit at position 35 on $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procdff$16333 ($dff) from module user_proj_example.
+Setting constant 0-bit at position 36 on $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procdff$16333 ($dff) from module user_proj_example.
+Setting constant 0-bit at position 37 on $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procdff$16333 ($dff) from module user_proj_example.
+Setting constant 0-bit at position 38 on $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procdff$16333 ($dff) from module user_proj_example.
+Setting constant 0-bit at position 39 on $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procdff$16333 ($dff) from module user_proj_example.
+Setting constant 0-bit at position 40 on $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procdff$16333 ($dff) from module user_proj_example.
+Setting constant 0-bit at position 41 on $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procdff$16333 ($dff) from module user_proj_example.
+Setting constant 0-bit at position 42 on $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procdff$16333 ($dff) from module user_proj_example.
+Setting constant 0-bit at position 43 on $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procdff$16333 ($dff) from module user_proj_example.
+Setting constant 0-bit at position 44 on $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procdff$16333 ($dff) from module user_proj_example.
+Setting constant 0-bit at position 45 on $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procdff$16333 ($dff) from module user_proj_example.
+Setting constant 0-bit at position 46 on $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procdff$16333 ($dff) from module user_proj_example.
+Setting constant 0-bit at position 47 on $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procdff$16333 ($dff) from module user_proj_example.
+Setting constant 0-bit at position 48 on $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procdff$16333 ($dff) from module user_proj_example.
+Setting constant 0-bit at position 49 on $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procdff$16333 ($dff) from module user_proj_example.
+Setting constant 0-bit at position 50 on $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procdff$16333 ($dff) from module user_proj_example.
+Setting constant 0-bit at position 51 on $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procdff$16333 ($dff) from module user_proj_example.
+Setting constant 0-bit at position 52 on $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procdff$16333 ($dff) from module user_proj_example.
+Setting constant 0-bit at position 53 on $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procdff$16333 ($dff) from module user_proj_example.
+Setting constant 0-bit at position 54 on $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procdff$16333 ($dff) from module user_proj_example.
+Setting constant 0-bit at position 55 on $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procdff$16333 ($dff) from module user_proj_example.
+Setting constant 0-bit at position 56 on $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procdff$16333 ($dff) from module user_proj_example.
+Setting constant 0-bit at position 57 on $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procdff$16333 ($dff) from module user_proj_example.
+Setting constant 0-bit at position 58 on $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procdff$16333 ($dff) from module user_proj_example.
+Setting constant 0-bit at position 59 on $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procdff$16333 ($dff) from module user_proj_example.
+Setting constant 0-bit at position 60 on $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procdff$16333 ($dff) from module user_proj_example.
+Setting constant 0-bit at position 61 on $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procdff$16333 ($dff) from module user_proj_example.
+Setting constant 0-bit at position 62 on $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procdff$16333 ($dff) from module user_proj_example.
+Setting constant 0-bit at position 63 on $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procdff$16333 ($dff) from module user_proj_example.
+Setting constant 0-bit at position 32 on $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procdff$16541 ($dff) from module user_proj_example.
+Setting constant 0-bit at position 33 on $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procdff$16541 ($dff) from module user_proj_example.
+Setting constant 0-bit at position 34 on $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procdff$16541 ($dff) from module user_proj_example.
+Setting constant 0-bit at position 35 on $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procdff$16541 ($dff) from module user_proj_example.
+Setting constant 0-bit at position 36 on $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procdff$16541 ($dff) from module user_proj_example.
+Setting constant 0-bit at position 37 on $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procdff$16541 ($dff) from module user_proj_example.
+Setting constant 0-bit at position 38 on $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procdff$16541 ($dff) from module user_proj_example.
+Setting constant 0-bit at position 39 on $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procdff$16541 ($dff) from module user_proj_example.
+Setting constant 0-bit at position 40 on $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procdff$16541 ($dff) from module user_proj_example.
+Setting constant 0-bit at position 41 on $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procdff$16541 ($dff) from module user_proj_example.
+Setting constant 0-bit at position 42 on $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procdff$16541 ($dff) from module user_proj_example.
+Setting constant 0-bit at position 43 on $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procdff$16541 ($dff) from module user_proj_example.
+Setting constant 0-bit at position 44 on $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procdff$16541 ($dff) from module user_proj_example.
+Setting constant 0-bit at position 45 on $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procdff$16541 ($dff) from module user_proj_example.
+Setting constant 0-bit at position 46 on $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procdff$16541 ($dff) from module user_proj_example.
+Setting constant 0-bit at position 47 on $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procdff$16541 ($dff) from module user_proj_example.
+Setting constant 0-bit at position 48 on $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procdff$16541 ($dff) from module user_proj_example.
+Setting constant 0-bit at position 49 on $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procdff$16541 ($dff) from module user_proj_example.
+Setting constant 0-bit at position 50 on $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procdff$16541 ($dff) from module user_proj_example.
+Setting constant 0-bit at position 51 on $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procdff$16541 ($dff) from module user_proj_example.
+Setting constant 0-bit at position 52 on $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procdff$16541 ($dff) from module user_proj_example.
+Setting constant 0-bit at position 53 on $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procdff$16541 ($dff) from module user_proj_example.
+Setting constant 0-bit at position 54 on $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procdff$16541 ($dff) from module user_proj_example.
+Setting constant 0-bit at position 55 on $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procdff$16541 ($dff) from module user_proj_example.
+Setting constant 0-bit at position 56 on $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procdff$16541 ($dff) from module user_proj_example.
+Setting constant 0-bit at position 57 on $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procdff$16541 ($dff) from module user_proj_example.
+Setting constant 0-bit at position 58 on $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procdff$16541 ($dff) from module user_proj_example.
+Setting constant 0-bit at position 59 on $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procdff$16541 ($dff) from module user_proj_example.
+Setting constant 0-bit at position 60 on $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procdff$16541 ($dff) from module user_proj_example.
+Setting constant 0-bit at position 61 on $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procdff$16541 ($dff) from module user_proj_example.
+Setting constant 0-bit at position 62 on $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procdff$16541 ($dff) from module user_proj_example.
+Setting constant 0-bit at position 63 on $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procdff$16541 ($dff) from module user_proj_example.
+
+23.7.7. Executing OPT_CLEAN pass (remove unused cells and wires).
+Finding unused cells or wires in module \user_proj_example..
+Removed 0 unused cells and 1958 unused wires.
+<suppressed ~26 debug messages>
+
+23.7.8. Executing OPT_EXPR pass (perform const folding).
+Optimizing module user_proj_example.
+
+23.7.9. Rerunning OPT passes. (Maybe there is more to do..)
+
+23.7.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
+Running muxtree optimizer on module \user_proj_example..
+ Creating internal representation of mux trees.
+ Evaluating internal representation of mux trees.
+ Analyzing evaluation results.
+Removed 0 multiplexer ports.
+<suppressed ~850 debug messages>
+
+23.7.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
+ Optimizing cells in module \user_proj_example.
+ New ctrl vector for $pmux cell $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$5593: { $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$eq$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1308$4645_Y $auto$opt_reduce.cc:134:opt_mux$17173 $auto$opt_reduce.cc:134:opt_mux$16977 }
+ New ctrl vector for $pmux cell $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$6125: $auto$opt_reduce.cc:134:opt_mux$17175
+ New ctrl vector for $pmux cell $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$6142: { $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$5575_CMP $auto$opt_reduce.cc:134:opt_mux$17177 }
+ New ctrl vector for $pmux cell $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$6570: { $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$eq$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1308$4645_Y $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$5577_CMP $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$5576_CMP $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$5575_CMP $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$5574_CMP $auto$opt_reduce.cc:134:opt_mux$17179 }
+ New ctrl vector for $pmux cell $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$7151: $auto$opt_reduce.cc:134:opt_mux$17181
+ New ctrl vector for $pmux cell $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$7456: $auto$opt_reduce.cc:134:opt_mux$17183
+ New ctrl vector for $pmux cell $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$8161: { $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$7285_CMP $auto$opt_reduce.cc:134:opt_mux$17185 }
+ New ctrl vector for $pmux cell $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10216: { $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$eq$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1308$3962_Y $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10018_CMP $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10165_CMP $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10008_CMP $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10149_CMP $auto$opt_reduce.cc:134:opt_mux$17187 }
+ New ctrl vector for $pmux cell $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10797: $auto$opt_reduce.cc:134:opt_mux$17189
+ New ctrl vector for $pmux cell $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$11102: $auto$opt_reduce.cc:134:opt_mux$17191
+ New ctrl vector for $pmux cell $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$11807: { $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10931_CMP $auto$opt_reduce.cc:134:opt_mux$17193 }
+ New ctrl vector for $pmux cell $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$9239: { $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$eq$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1308$3962_Y $auto$opt_reduce.cc:134:opt_mux$17195 $auto$opt_reduce.cc:134:opt_mux$17005 }
+ New ctrl vector for $pmux cell $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$9771: $auto$opt_reduce.cc:134:opt_mux$17197
+ New ctrl vector for $pmux cell $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$9788: { $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10008_CMP $auto$opt_reduce.cc:134:opt_mux$17199 }
+ New ctrl vector for $pmux cell $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$12104: { $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$eq$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1308$3279_Y $auto$opt_reduce.cc:134:opt_mux$17201 $auto$opt_reduce.cc:134:opt_mux$17051 }
+ New ctrl vector for $pmux cell $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$12636: $auto$opt_reduce.cc:134:opt_mux$17203
+ New ctrl vector for $pmux cell $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$12653: { $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$12086_CMP $auto$opt_reduce.cc:134:opt_mux$17205 }
+ New ctrl vector for $pmux cell $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$13081: { $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$eq$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1308$3279_Y $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$12088_CMP $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$12087_CMP $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$12086_CMP $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$12085_CMP $auto$opt_reduce.cc:134:opt_mux$17207 }
+ New ctrl vector for $pmux cell $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$13662: $auto$opt_reduce.cc:134:opt_mux$17209
+ New ctrl vector for $pmux cell $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$13967: $auto$opt_reduce.cc:134:opt_mux$17211
+ New ctrl vector for $pmux cell $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$14672: { $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$13796_CMP $auto$opt_reduce.cc:134:opt_mux$17213 }
+ New ctrl vector for $pmux cell $flatten\softshell.\flash.\spimemio.$procmux$8749: $auto$opt_reduce.cc:134:opt_mux$17215
+ New ctrl vector for $pmux cell $flatten\softshell.\flash.\spimemio.$procmux$8851: { $flatten\softshell.\flash.\spimemio.$procmux$8787_CMP $auto$opt_reduce.cc:134:opt_mux$17217 $flatten\softshell.\flash.\spimemio.$procmux$8764_CMP }
+ Optimizing cells in module \user_proj_example.
+Performed a total of 23 changes.
+
+23.7.12. Executing OPT_MERGE pass (detect identical cells).
+Finding identical cells in module `\user_proj_example'.
+<suppressed ~36 debug messages>
+Removed a total of 12 cells.
+
+23.7.13. Executing OPT_DFF pass (perform DFF optimizations).
+
+23.7.14. Executing OPT_CLEAN pass (remove unused cells and wires).
+Finding unused cells or wires in module \user_proj_example..
+Removed 0 unused cells and 12 unused wires.
+<suppressed ~1 debug messages>
+
+23.7.15. Executing OPT_EXPR pass (perform const folding).
+Optimizing module user_proj_example.
+
+23.7.16. Rerunning OPT passes. (Maybe there is more to do..)
+
+23.7.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
+Running muxtree optimizer on module \user_proj_example..
+ Creating internal representation of mux trees.
+ Evaluating internal representation of mux trees.
+ Analyzing evaluation results.
+Removed 0 multiplexer ports.
+<suppressed ~850 debug messages>
+
+23.7.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
+ Optimizing cells in module \user_proj_example.
+Performed a total of 0 changes.
+
+23.7.19. Executing OPT_MERGE pass (detect identical cells).
+Finding identical cells in module `\user_proj_example'.
+Removed a total of 0 cells.
+
+23.7.20. Executing OPT_DFF pass (perform DFF optimizations).
+
+23.7.21. Executing OPT_CLEAN pass (remove unused cells and wires).
+Finding unused cells or wires in module \user_proj_example..
+
+23.7.22. Executing OPT_EXPR pass (perform const folding).
+Optimizing module user_proj_example.
+
+23.7.23. Finished OPT passes. (There is nothing left to do.)
+
+23.8. Executing FSM pass (extract and optimize FSM).
+
+23.8.1. Executing FSM_DETECT pass (finding FSMs in design).
+Not marking user_proj_example.$flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.\cpuregs.$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/rv_core.v:286$25_EN as FSM state register:
+ Users of register don't seem to benefit from recoding.
+Not marking user_proj_example.$flatten\softshell.\cpus[0].core.\flexio.\out_fifo.$memwr$\mem$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:139$1999_EN as FSM state register:
+ Users of register don't seem to benefit from recoding.
+Not marking user_proj_example.$flatten\softshell.\cpus[0].core.\soc_mem.\ram.$memwr$\ram0$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:103$2788_EN as FSM state register:
+ Users of register don't seem to benefit from recoding.
+Not marking user_proj_example.$flatten\softshell.\cpus[0].core.\soc_mem.\ram.$memwr$\ram1$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:105$2789_EN as FSM state register:
+ Users of register don't seem to benefit from recoding.
+Not marking user_proj_example.$flatten\softshell.\cpus[0].core.\soc_mem.\ram.$memwr$\ram2$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:107$2790_EN as FSM state register:
+ Users of register don't seem to benefit from recoding.
+Not marking user_proj_example.$flatten\softshell.\cpus[0].core.\soc_mem.\ram.$memwr$\ram3$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:109$2791_EN as FSM state register:
+ Users of register don't seem to benefit from recoding.
+Not marking user_proj_example.$flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.\cpuregs.$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/rv_core.v:286$25_EN as FSM state register:
+ Users of register don't seem to benefit from recoding.
+Not marking user_proj_example.$flatten\softshell.\cpus[1].core.\flexio.\out_fifo.$memwr$\mem$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:139$1999_EN as FSM state register:
+ Users of register don't seem to benefit from recoding.
+Not marking user_proj_example.$flatten\softshell.\cpus[1].core.\soc_mem.\ram.$memwr$\ram0$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:103$2788_EN as FSM state register:
+ Users of register don't seem to benefit from recoding.
+Not marking user_proj_example.$flatten\softshell.\cpus[1].core.\soc_mem.\ram.$memwr$\ram1$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:105$2789_EN as FSM state register:
+ Users of register don't seem to benefit from recoding.
+Not marking user_proj_example.$flatten\softshell.\cpus[1].core.\soc_mem.\ram.$memwr$\ram2$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:107$2790_EN as FSM state register:
+ Users of register don't seem to benefit from recoding.
+Not marking user_proj_example.$flatten\softshell.\cpus[1].core.\soc_mem.\ram.$memwr$\ram3$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:109$2791_EN as FSM state register:
+ Users of register don't seem to benefit from recoding.
+Not marking user_proj_example.$flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.\cpuregs.$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/rv_core.v:286$25_EN as FSM state register:
+ Users of register don't seem to benefit from recoding.
+Not marking user_proj_example.$flatten\softshell.\cpus[2].core.\flexio.\out_fifo.$memwr$\mem$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:139$1999_EN as FSM state register:
+ Users of register don't seem to benefit from recoding.
+Not marking user_proj_example.$flatten\softshell.\cpus[2].core.\soc_mem.\ram.$memwr$\ram0$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:103$2788_EN as FSM state register:
+ Users of register don't seem to benefit from recoding.
+Not marking user_proj_example.$flatten\softshell.\cpus[2].core.\soc_mem.\ram.$memwr$\ram1$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:105$2789_EN as FSM state register:
+ Users of register don't seem to benefit from recoding.
+Not marking user_proj_example.$flatten\softshell.\cpus[2].core.\soc_mem.\ram.$memwr$\ram2$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:107$2790_EN as FSM state register:
+ Users of register don't seem to benefit from recoding.
+Not marking user_proj_example.$flatten\softshell.\cpus[2].core.\soc_mem.\ram.$memwr$\ram3$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:109$2791_EN as FSM state register:
+ Users of register don't seem to benefit from recoding.
+Not marking user_proj_example.$flatten\softshell.\shared_mem.\ram.$memwr$\ram0$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:103$2762_EN as FSM state register:
+ Users of register don't seem to benefit from recoding.
+Not marking user_proj_example.$flatten\softshell.\shared_mem.\ram.$memwr$\ram1$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:105$2763_EN as FSM state register:
+ Users of register don't seem to benefit from recoding.
+Not marking user_proj_example.$flatten\softshell.\shared_mem.\ram.$memwr$\ram2$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:107$2764_EN as FSM state register:
+ Users of register don't seem to benefit from recoding.
+Not marking user_proj_example.$flatten\softshell.\shared_mem.\ram.$memwr$\ram3$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:109$2765_EN as FSM state register:
+ Users of register don't seem to benefit from recoding.
+Found FSM state register user_proj_example.softshell.cpus[0].core.cpu.picorv32_core.cpu_state.
+Not marking user_proj_example.softshell.cpus[0].core.cpu.picorv32_core.irq_state as FSM state register:
+ Users of register don't seem to benefit from recoding.
+Not marking user_proj_example.softshell.cpus[0].core.cpu.picorv32_core.mem_state as FSM state register:
+ Users of register don't seem to benefit from recoding.
+Found FSM state register user_proj_example.softshell.cpus[0].core.cpu.picorv32_core.mem_wordsize.
+Found FSM state register user_proj_example.softshell.cpus[0].core.cpu.state.
+Found FSM state register user_proj_example.softshell.cpus[1].core.cpu.picorv32_core.cpu_state.
+Not marking user_proj_example.softshell.cpus[1].core.cpu.picorv32_core.irq_state as FSM state register:
+ Users of register don't seem to benefit from recoding.
+Not marking user_proj_example.softshell.cpus[1].core.cpu.picorv32_core.mem_state as FSM state register:
+ Users of register don't seem to benefit from recoding.
+Found FSM state register user_proj_example.softshell.cpus[1].core.cpu.picorv32_core.mem_wordsize.
+Found FSM state register user_proj_example.softshell.cpus[1].core.cpu.state.
+Found FSM state register user_proj_example.softshell.cpus[2].core.cpu.picorv32_core.cpu_state.
+Not marking user_proj_example.softshell.cpus[2].core.cpu.picorv32_core.irq_state as FSM state register:
+ Users of register don't seem to benefit from recoding.
+Not marking user_proj_example.softshell.cpus[2].core.cpu.picorv32_core.mem_state as FSM state register:
+ Users of register don't seem to benefit from recoding.
+Found FSM state register user_proj_example.softshell.cpus[2].core.cpu.picorv32_core.mem_wordsize.
+Found FSM state register user_proj_example.softshell.cpus[2].core.cpu.state.
+Not marking user_proj_example.softshell.flash.spimemio.din_tag as FSM state register:
+ Users of register don't seem to benefit from recoding.
+Found FSM state register user_proj_example.softshell.flash.spimemio.state.
+
+23.8.2. Executing FSM_EXTRACT pass (extracting FSM from design).
+Extracting FSM `\softshell.cpus[0].core.cpu.picorv32_core.cpu_state' from module `\user_proj_example'.
+ found $dff cell for state register: $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procdff$16359
+ root of input selection tree: $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$0\cpu_state[7:0]
+ found ctrl input: $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1933$4840_Y
+ found ctrl input: $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1917$4823_Y
+ found ctrl input: \softshell.cpus[0].core.cpu.wb_rst_i
+ found ctrl input: $auto$opt_reduce.cc:134:opt_mux$17175
+ found ctrl input: $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$5574_CMP
+ found ctrl input: $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$5575_CMP
+ found ctrl input: $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$5576_CMP
+ found ctrl input: $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$5577_CMP
+ found ctrl input: $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$eq$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1308$4645_Y
+ found ctrl input: $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$logic_or$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1852$4804_Y
+ found ctrl input: $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1867$4808_Y
+ found state code: 8'01000000
+ found ctrl input: $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$eq$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1826$4786_Y
+ found ctrl input: \softshell.cpus[0].core.cpu.picorv32_core.is_beq_bne_blt_bge_bltu_bgeu
+ found ctrl input: \softshell.cpus[0].core.cpu.picorv32_core.mem_done
+ found ctrl input: \softshell.cpus[0].core.cpu.picorv32_core.is_sb_sh_sw
+ found ctrl input: \softshell.cpus[0].core.cpu.picorv32_core.instr_trap
+ found state code: 8'00001000
+ found state code: 8'00000010
+ found ctrl input: \softshell.cpus[0].core.flexio.pcpi_ready
+ found ctrl input: $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1600$4740_Y
+ found ctrl input: $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1603$4744_Y
+ found state code: 8'10000000
+ found ctrl input: $auto$opt_reduce.cc:134:opt_mux$17047
+ found ctrl input: $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1691$4758_Y
+ found ctrl input: $auto$opt_reduce.cc:134:opt_mux$17041
+ found state code: 8'00000001
+ found ctrl input: $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1533$4719_Y
+ found ctrl input: $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1543$4727_Y
+ found ctrl input: \softshell.cpus[0].core.cpu.picorv32_core.decoder_trigger
+ found ctrl input: \softshell.cpus[0].core.cpu.picorv32_core.instr_jal
+ found state code: 8'00100000
+ found ctrl input: $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1925$4833_Y
+ found ctrl input: $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1918$4826_Y
+ found ctrl input: $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1920$4830_Y
+ found ctrl output: $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$eq$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1308$4645_Y
+ found ctrl output: $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$5572_CMP
+ found ctrl output: $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$5573_CMP
+ found ctrl output: $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$5574_CMP
+ found ctrl output: $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$5575_CMP
+ found ctrl output: $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$5576_CMP
+ found ctrl output: $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$5577_CMP
+ found ctrl output: $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$5579_CMP
+ ctrl inputs: { $auto$opt_reduce.cc:134:opt_mux$17041 $auto$opt_reduce.cc:134:opt_mux$17047 \softshell.cpus[0].core.cpu.wb_rst_i $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1933$4840_Y $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1925$4833_Y $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1920$4830_Y $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1918$4826_Y $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1917$4823_Y $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1867$4808_Y $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$logic_or$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1852$4804_Y $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$eq$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1826$4786_Y $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1691$4758_Y $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1603$4744_Y $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1600$4740_Y $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1543$4727_Y $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1533$4719_Y \softshell.cpus[0].core.cpu.picorv32_core.is_beq_bne_blt_bge_bltu_bgeu \softshell.cpus[0].core.cpu.picorv32_core.is_sb_sh_sw \softshell.cpus[0].core.cpu.picorv32_core.decoder_trigger \softshell.cpus[0].core.cpu.picorv32_core.instr_trap \softshell.cpus[0].core.cpu.picorv32_core.instr_jal \softshell.cpus[0].core.cpu.picorv32_core.mem_done \softshell.cpus[0].core.flexio.pcpi_ready $auto$opt_reduce.cc:134:opt_mux$17175 }
+ ctrl outputs: { $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$5579_CMP $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$5577_CMP $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$5576_CMP $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$5575_CMP $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$5574_CMP $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$5573_CMP $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$5572_CMP $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$0\cpu_state[7:0] $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$eq$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1308$4645_Y }
+ transition: 8'10000000 24'--00---0---------------- -> 8'10000000 16'1000000100000000
+ transition: 8'10000000 24'--10---0---------------- -> 8'01000000 16'1000000010000000
+ transition: 8'10000000 24'--000-01---------------- -> 8'10000000 16'1000000100000000
+ transition: 8'10000000 24'--100-01---------------- -> 8'01000000 16'1000000010000000
+ transition: 8'10000000 24'---00011---------------- -> 8'10000000 16'1000000100000000
+ transition: 8'10000000 24'--000111---------------- -> 8'10000000 16'1000000100000000
+ transition: 8'10000000 24'--100111---------------- -> 8'01000000 16'1000000010000000
+ transition: 8'10000000 24'---010-1---------------- -> 8'10000000 16'1000000100000000
+ transition: 8'10000000 24'--001101---------------- -> 8'10000000 16'1000000100000000
+ transition: 8'10000000 24'--101101---------------- -> 8'01000000 16'1000000010000000
+ transition: 8'10000000 24'--001111---------------- -> 8'10000000 16'1000000100000000
+ transition: 8'10000000 24'--101111---------------- -> 8'01000000 16'1000000010000000
+ transition: 8'10000000 24'---1-0------------------ -> 8'10000000 16'1000000100000000
+ transition: 8'10000000 24'--01-1-0---------------- -> 8'10000000 16'1000000100000000
+ transition: 8'10000000 24'--11-1-0---------------- -> 8'01000000 16'1000000010000000
+ transition: 8'10000000 24'--010101---------------- -> 8'10000000 16'1000000100000000
+ transition: 8'10000000 24'--110101---------------- -> 8'01000000 16'1000000010000000
+ transition: 8'10000000 24'--010111---------------- -> 8'10000000 16'1000000100000000
+ transition: 8'10000000 24'--110111---------------- -> 8'01000000 16'1000000010000000
+ transition: 8'10000000 24'--011101---------------- -> 8'10000000 16'1000000100000000
+ transition: 8'10000000 24'--111101---------------- -> 8'01000000 16'1000000010000000
+ transition: 8'10000000 24'--011111---------------- -> 8'10000000 16'1000000100000000
+ transition: 8'10000000 24'--111111---------------- -> 8'01000000 16'1000000010000000
+ transition: 8'01000000 24'--00---0------00--0----- -> 8'01000000 16'0000000010000001
+ transition: 8'01000000 24'--00---0------00--1-0--- -> 8'00100000 16'0000000001000001
+ transition: 8'01000000 24'--00---0------00--1-1--- -> 8'01000000 16'0000000010000001
+ transition: 8'01000000 24'--00---0------10-------- -> 8'01000000 16'0000000010000001
+ transition: 8'01000000 24'--00---0-------1-------- -> 8'01000000 16'0000000010000001
+ transition: 8'01000000 24'--10---0---------------- -> 8'01000000 16'0000000010000001
+ transition: 8'01000000 24'--000-01------00--0----- -> 8'01000000 16'0000000010000001
+ transition: 8'01000000 24'--000-01------00--1-0--- -> 8'00100000 16'0000000001000001
+ transition: 8'01000000 24'--000-01------00--1-1--- -> 8'01000000 16'0000000010000001
+ transition: 8'01000000 24'--000-01------10-------- -> 8'01000000 16'0000000010000001
+ transition: 8'01000000 24'--000-01-------1-------- -> 8'01000000 16'0000000010000001
+ transition: 8'01000000 24'--100-01---------------- -> 8'01000000 16'0000000010000001
+ transition: 8'01000000 24'---00011---------------- -> 8'10000000 16'0000000100000001
+ transition: 8'01000000 24'--000111------00--0----- -> 8'01000000 16'0000000010000001
+ transition: 8'01000000 24'--000111------00--1-0--- -> 8'00100000 16'0000000001000001
+ transition: 8'01000000 24'--000111------00--1-1--- -> 8'01000000 16'0000000010000001
+ transition: 8'01000000 24'--000111------10-------- -> 8'01000000 16'0000000010000001
+ transition: 8'01000000 24'--000111-------1-------- -> 8'01000000 16'0000000010000001
+ transition: 8'01000000 24'--100111---------------- -> 8'01000000 16'0000000010000001
+ transition: 8'01000000 24'---010-1---------------- -> 8'10000000 16'0000000100000001
+ transition: 8'01000000 24'--001101------00--0----- -> 8'01000000 16'0000000010000001
+ transition: 8'01000000 24'--001101------00--1-0--- -> 8'00100000 16'0000000001000001
+ transition: 8'01000000 24'--001101------00--1-1--- -> 8'01000000 16'0000000010000001
+ transition: 8'01000000 24'--001101------10-------- -> 8'01000000 16'0000000010000001
+ transition: 8'01000000 24'--001101-------1-------- -> 8'01000000 16'0000000010000001
+ transition: 8'01000000 24'--101101---------------- -> 8'01000000 16'0000000010000001
+ transition: 8'01000000 24'--001111------00--0----- -> 8'01000000 16'0000000010000001
+ transition: 8'01000000 24'--001111------00--1-0--- -> 8'00100000 16'0000000001000001
+ transition: 8'01000000 24'--001111------00--1-1--- -> 8'01000000 16'0000000010000001
+ transition: 8'01000000 24'--001111------10-------- -> 8'01000000 16'0000000010000001
+ transition: 8'01000000 24'--001111-------1-------- -> 8'01000000 16'0000000010000001
+ transition: 8'01000000 24'--101111---------------- -> 8'01000000 16'0000000010000001
+ transition: 8'01000000 24'---1-0------------------ -> 8'10000000 16'0000000100000001
+ transition: 8'01000000 24'--01-1-0------00--0----- -> 8'01000000 16'0000000010000001
+ transition: 8'01000000 24'--01-1-0------00--1-0--- -> 8'00100000 16'0000000001000001
+ transition: 8'01000000 24'--01-1-0------00--1-1--- -> 8'01000000 16'0000000010000001
+ transition: 8'01000000 24'--01-1-0------10-------- -> 8'01000000 16'0000000010000001
+ transition: 8'01000000 24'--01-1-0-------1-------- -> 8'01000000 16'0000000010000001
+ transition: 8'01000000 24'--11-1-0---------------- -> 8'01000000 16'0000000010000001
+ transition: 8'01000000 24'--010101------00--0----- -> 8'01000000 16'0000000010000001
+ transition: 8'01000000 24'--010101------00--1-0--- -> 8'00100000 16'0000000001000001
+ transition: 8'01000000 24'--010101------00--1-1--- -> 8'01000000 16'0000000010000001
+ transition: 8'01000000 24'--010101------10-------- -> 8'01000000 16'0000000010000001
+ transition: 8'01000000 24'--010101-------1-------- -> 8'01000000 16'0000000010000001
+ transition: 8'01000000 24'--110101---------------- -> 8'01000000 16'0000000010000001
+ transition: 8'01000000 24'--010111------00--0----- -> 8'01000000 16'0000000010000001
+ transition: 8'01000000 24'--010111------00--1-0--- -> 8'00100000 16'0000000001000001
+ transition: 8'01000000 24'--010111------00--1-1--- -> 8'01000000 16'0000000010000001
+ transition: 8'01000000 24'--010111------10-------- -> 8'01000000 16'0000000010000001
+ transition: 8'01000000 24'--010111-------1-------- -> 8'01000000 16'0000000010000001
+ transition: 8'01000000 24'--110111---------------- -> 8'01000000 16'0000000010000001
+ transition: 8'01000000 24'--011101------00--0----- -> 8'01000000 16'0000000010000001
+ transition: 8'01000000 24'--011101------00--1-0--- -> 8'00100000 16'0000000001000001
+ transition: 8'01000000 24'--011101------00--1-1--- -> 8'01000000 16'0000000010000001
+ transition: 8'01000000 24'--011101------10-------- -> 8'01000000 16'0000000010000001
+ transition: 8'01000000 24'--011101-------1-------- -> 8'01000000 16'0000000010000001
+ transition: 8'01000000 24'--111101---------------- -> 8'01000000 16'0000000010000001
+ transition: 8'01000000 24'--011111------00--0----- -> 8'01000000 16'0000000010000001
+ transition: 8'01000000 24'--011111------00--1-0--- -> 8'00100000 16'0000000001000001
+ transition: 8'01000000 24'--011111------00--1-1--- -> 8'01000000 16'0000000010000001
+ transition: 8'01000000 24'--011111------10-------- -> 8'01000000 16'0000000010000001
+ transition: 8'01000000 24'--011111-------1-------- -> 8'01000000 16'0000000010000001
+ transition: 8'01000000 24'--111111---------------- -> 8'01000000 16'0000000010000001
+ transition: 8'00100000 24'0000---0---0-----0-0---- -> 8'00001000 16'0100000000010000
+ transition: 8'00100000 24'0000---0---0-----1------ -> 8'00000010 16'0100000000000100
+ transition: 8'00100000 24'--00---0-----0-----1--0- -> 8'00100000 16'0100000001000000
+ transition: 8'00100000 24'--00---0----01-----1--0- -> 8'10000000 16'0100000100000000
+ transition: 8'00100000 24'--00---0----11-----1--0- -> 8'01000000 16'0100000010000000
+ transition: 8'00100000 24'--00---0-----------1--1- -> 8'01000000 16'0100000010000000
+ transition: 8'00100000 24'1-00---0---------------- -> 8'01000000 16'0100000010000000
+ transition: 8'00100000 24'--00---0---1------------ -> 8'00000001 16'0100000000000010
+ transition: 8'00100000 24'-100---0---------------- -> 8'00001000 16'0100000000010000
+ transition: 8'00100000 24'--10---0---------------- -> 8'01000000 16'0100000010000000
+ transition: 8'00100000 24'00000-01---0-----0-0---- -> 8'00001000 16'0100000000010000
+ transition: 8'00100000 24'00000-01---0-----1------ -> 8'00000010 16'0100000000000100
+ transition: 8'00100000 24'--000-01-----0-----1--0- -> 8'00100000 16'0100000001000000
+ transition: 8'00100000 24'--000-01----01-----1--0- -> 8'10000000 16'0100000100000000
+ transition: 8'00100000 24'--000-01----11-----1--0- -> 8'01000000 16'0100000010000000
+ transition: 8'00100000 24'--000-01-----------1--1- -> 8'01000000 16'0100000010000000
+ transition: 8'00100000 24'1-000-01---------------- -> 8'01000000 16'0100000010000000
+ transition: 8'00100000 24'--000-01---1------------ -> 8'00000001 16'0100000000000010
+ transition: 8'00100000 24'-1000-01---------------- -> 8'00001000 16'0100000000010000
+ transition: 8'00100000 24'--100-01---------------- -> 8'01000000 16'0100000010000000
+ transition: 8'00100000 24'---00011---------------- -> 8'10000000 16'0100000100000000
+ transition: 8'00100000 24'00000111---0-----0-0---- -> 8'00001000 16'0100000000010000
+ transition: 8'00100000 24'00000111---0-----1------ -> 8'00000010 16'0100000000000100
+ transition: 8'00100000 24'--000111-----0-----1--0- -> 8'00100000 16'0100000001000000
+ transition: 8'00100000 24'--000111----01-----1--0- -> 8'10000000 16'0100000100000000
+ transition: 8'00100000 24'--000111----11-----1--0- -> 8'01000000 16'0100000010000000
+ transition: 8'00100000 24'--000111-----------1--1- -> 8'01000000 16'0100000010000000
+ transition: 8'00100000 24'1-000111---------------- -> 8'01000000 16'0100000010000000
+ transition: 8'00100000 24'--000111---1------------ -> 8'00000001 16'0100000000000010
+ transition: 8'00100000 24'-1000111---------------- -> 8'00001000 16'0100000000010000
+ transition: 8'00100000 24'--100111---------------- -> 8'01000000 16'0100000010000000
+ transition: 8'00100000 24'---010-1---------------- -> 8'10000000 16'0100000100000000
+ transition: 8'00100000 24'00001101---0-----0-0---- -> 8'00001000 16'0100000000010000
+ transition: 8'00100000 24'00001101---0-----1------ -> 8'00000010 16'0100000000000100
+ transition: 8'00100000 24'--001101-----0-----1--0- -> 8'00100000 16'0100000001000000
+ transition: 8'00100000 24'--001101----01-----1--0- -> 8'10000000 16'0100000100000000
+ transition: 8'00100000 24'--001101----11-----1--0- -> 8'01000000 16'0100000010000000
+ transition: 8'00100000 24'--001101-----------1--1- -> 8'01000000 16'0100000010000000
+ transition: 8'00100000 24'1-001101---------------- -> 8'01000000 16'0100000010000000
+ transition: 8'00100000 24'--001101---1------------ -> 8'00000001 16'0100000000000010
+ transition: 8'00100000 24'-1001101---------------- -> 8'00001000 16'0100000000010000
+ transition: 8'00100000 24'--101101---------------- -> 8'01000000 16'0100000010000000
+ transition: 8'00100000 24'00001111---0-----0-0---- -> 8'00001000 16'0100000000010000
+ transition: 8'00100000 24'00001111---0-----1------ -> 8'00000010 16'0100000000000100
+ transition: 8'00100000 24'--001111-----0-----1--0- -> 8'00100000 16'0100000001000000
+ transition: 8'00100000 24'--001111----01-----1--0- -> 8'10000000 16'0100000100000000
+ transition: 8'00100000 24'--001111----11-----1--0- -> 8'01000000 16'0100000010000000
+ transition: 8'00100000 24'--001111-----------1--1- -> 8'01000000 16'0100000010000000
+ transition: 8'00100000 24'1-001111---------------- -> 8'01000000 16'0100000010000000
+ transition: 8'00100000 24'--001111---1------------ -> 8'00000001 16'0100000000000010
+ transition: 8'00100000 24'-1001111---------------- -> 8'00001000 16'0100000000010000
+ transition: 8'00100000 24'--101111---------------- -> 8'01000000 16'0100000010000000
+ transition: 8'00100000 24'---1-0------------------ -> 8'10000000 16'0100000100000000
+ transition: 8'00100000 24'0001-1-0---0-----0-0---- -> 8'00001000 16'0100000000010000
+ transition: 8'00100000 24'0001-1-0---0-----1------ -> 8'00000010 16'0100000000000100
+ transition: 8'00100000 24'--01-1-0-----0-----1--0- -> 8'00100000 16'0100000001000000
+ transition: 8'00100000 24'--01-1-0----01-----1--0- -> 8'10000000 16'0100000100000000
+ transition: 8'00100000 24'--01-1-0----11-----1--0- -> 8'01000000 16'0100000010000000
+ transition: 8'00100000 24'--01-1-0-----------1--1- -> 8'01000000 16'0100000010000000
+ transition: 8'00100000 24'1-01-1-0---------------- -> 8'01000000 16'0100000010000000
+ transition: 8'00100000 24'--01-1-0---1------------ -> 8'00000001 16'0100000000000010
+ transition: 8'00100000 24'-101-1-0---------------- -> 8'00001000 16'0100000000010000
+ transition: 8'00100000 24'--11-1-0---------------- -> 8'01000000 16'0100000010000000
+ transition: 8'00100000 24'00010101---0-----0-0---- -> 8'00001000 16'0100000000010000
+ transition: 8'00100000 24'00010101---0-----1------ -> 8'00000010 16'0100000000000100
+ transition: 8'00100000 24'--010101-----0-----1--0- -> 8'00100000 16'0100000001000000
+ transition: 8'00100000 24'--010101----01-----1--0- -> 8'10000000 16'0100000100000000
+ transition: 8'00100000 24'--010101----11-----1--0- -> 8'01000000 16'0100000010000000
+ transition: 8'00100000 24'--010101-----------1--1- -> 8'01000000 16'0100000010000000
+ transition: 8'00100000 24'1-010101---------------- -> 8'01000000 16'0100000010000000
+ transition: 8'00100000 24'--010101---1------------ -> 8'00000001 16'0100000000000010
+ transition: 8'00100000 24'-1010101---------------- -> 8'00001000 16'0100000000010000
+ transition: 8'00100000 24'--110101---------------- -> 8'01000000 16'0100000010000000
+ transition: 8'00100000 24'00010111---0-----0-0---- -> 8'00001000 16'0100000000010000
+ transition: 8'00100000 24'00010111---0-----1------ -> 8'00000010 16'0100000000000100
+ transition: 8'00100000 24'--010111-----0-----1--0- -> 8'00100000 16'0100000001000000
+ transition: 8'00100000 24'--010111----01-----1--0- -> 8'10000000 16'0100000100000000
+ transition: 8'00100000 24'--010111----11-----1--0- -> 8'01000000 16'0100000010000000
+ transition: 8'00100000 24'--010111-----------1--1- -> 8'01000000 16'0100000010000000
+ transition: 8'00100000 24'1-010111---------------- -> 8'01000000 16'0100000010000000
+ transition: 8'00100000 24'--010111---1------------ -> 8'00000001 16'0100000000000010
+ transition: 8'00100000 24'-1010111---------------- -> 8'00001000 16'0100000000010000
+ transition: 8'00100000 24'--110111---------------- -> 8'01000000 16'0100000010000000
+ transition: 8'00100000 24'00011101---0-----0-0---- -> 8'00001000 16'0100000000010000
+ transition: 8'00100000 24'00011101---0-----1------ -> 8'00000010 16'0100000000000100
+ transition: 8'00100000 24'--011101-----0-----1--0- -> 8'00100000 16'0100000001000000
+ transition: 8'00100000 24'--011101----01-----1--0- -> 8'10000000 16'0100000100000000
+ transition: 8'00100000 24'--011101----11-----1--0- -> 8'01000000 16'0100000010000000
+ transition: 8'00100000 24'--011101-----------1--1- -> 8'01000000 16'0100000010000000
+ transition: 8'00100000 24'1-011101---------------- -> 8'01000000 16'0100000010000000
+ transition: 8'00100000 24'--011101---1------------ -> 8'00000001 16'0100000000000010
+ transition: 8'00100000 24'-1011101---------------- -> 8'00001000 16'0100000000010000
+ transition: 8'00100000 24'--111101---------------- -> 8'01000000 16'0100000010000000
+ transition: 8'00100000 24'00011111---0-----0-0---- -> 8'00001000 16'0100000000010000
+ transition: 8'00100000 24'00011111---0-----1------ -> 8'00000010 16'0100000000000100
+ transition: 8'00100000 24'--011111-----0-----1--0- -> 8'00100000 16'0100000001000000
+ transition: 8'00100000 24'--011111----01-----1--0- -> 8'10000000 16'0100000100000000
+ transition: 8'00100000 24'--011111----11-----1--0- -> 8'01000000 16'0100000010000000
+ transition: 8'00100000 24'--011111-----------1--1- -> 8'01000000 16'0100000010000000
+ transition: 8'00100000 24'1-011111---------------- -> 8'01000000 16'0100000010000000
+ transition: 8'00100000 24'--011111---1------------ -> 8'00000001 16'0100000000000010
+ transition: 8'00100000 24'-1011111---------------- -> 8'00001000 16'0100000000010000
+ transition: 8'00100000 24'--111111---------------- -> 8'01000000 16'0100000010000000
+ transition: 8'00001000 24'--00---0--------0------- -> 8'01000000 16'0001000010000000
+ transition: 8'00001000 24'--00---0--------1----0-- -> 8'00001000 16'0001000000010000
+ transition: 8'00001000 24'--00---0--------1----1-- -> 8'01000000 16'0001000010000000
+ transition: 8'00001000 24'--10---0---------------- -> 8'01000000 16'0001000010000000
+ transition: 8'00001000 24'--000-01--------0------- -> 8'01000000 16'0001000010000000
+ transition: 8'00001000 24'--000-01--------1----0-- -> 8'00001000 16'0001000000010000
+ transition: 8'00001000 24'--000-01--------1----1-- -> 8'01000000 16'0001000010000000
+ transition: 8'00001000 24'--100-01---------------- -> 8'01000000 16'0001000010000000
+ transition: 8'00001000 24'---00011---------------- -> 8'10000000 16'0001000100000000
+ transition: 8'00001000 24'--000111--------0------- -> 8'01000000 16'0001000010000000
+ transition: 8'00001000 24'--000111--------1----0-- -> 8'00001000 16'0001000000010000
+ transition: 8'00001000 24'--000111--------1----1-- -> 8'01000000 16'0001000010000000
+ transition: 8'00001000 24'--100111---------------- -> 8'01000000 16'0001000010000000
+ transition: 8'00001000 24'---010-1---------------- -> 8'10000000 16'0001000100000000
+ transition: 8'00001000 24'--001101--------0------- -> 8'01000000 16'0001000010000000
+ transition: 8'00001000 24'--001101--------1----0-- -> 8'00001000 16'0001000000010000
+ transition: 8'00001000 24'--001101--------1----1-- -> 8'01000000 16'0001000010000000
+ transition: 8'00001000 24'--101101---------------- -> 8'01000000 16'0001000010000000
+ transition: 8'00001000 24'--001111--------0------- -> 8'01000000 16'0001000010000000
+ transition: 8'00001000 24'--001111--------1----0-- -> 8'00001000 16'0001000000010000
+ transition: 8'00001000 24'--001111--------1----1-- -> 8'01000000 16'0001000010000000
+ transition: 8'00001000 24'--101111---------------- -> 8'01000000 16'0001000010000000
+ transition: 8'00001000 24'---1-0------------------ -> 8'10000000 16'0001000100000000
+ transition: 8'00001000 24'--01-1-0--------0------- -> 8'01000000 16'0001000010000000
+ transition: 8'00001000 24'--01-1-0--------1----0-- -> 8'00001000 16'0001000000010000
+ transition: 8'00001000 24'--01-1-0--------1----1-- -> 8'01000000 16'0001000010000000
+ transition: 8'00001000 24'--11-1-0---------------- -> 8'01000000 16'0001000010000000
+ transition: 8'00001000 24'--010101--------0------- -> 8'01000000 16'0001000010000000
+ transition: 8'00001000 24'--010101--------1----0-- -> 8'00001000 16'0001000000010000
+ transition: 8'00001000 24'--010101--------1----1-- -> 8'01000000 16'0001000010000000
+ transition: 8'00001000 24'--110101---------------- -> 8'01000000 16'0001000010000000
+ transition: 8'00001000 24'--010111--------0------- -> 8'01000000 16'0001000010000000
+ transition: 8'00001000 24'--010111--------1----0-- -> 8'00001000 16'0001000000010000
+ transition: 8'00001000 24'--010111--------1----1-- -> 8'01000000 16'0001000010000000
+ transition: 8'00001000 24'--110111---------------- -> 8'01000000 16'0001000010000000
+ transition: 8'00001000 24'--011101--------0------- -> 8'01000000 16'0001000010000000
+ transition: 8'00001000 24'--011101--------1----0-- -> 8'00001000 16'0001000000010000
+ transition: 8'00001000 24'--011101--------1----1-- -> 8'01000000 16'0001000010000000
+ transition: 8'00001000 24'--111101---------------- -> 8'01000000 16'0001000010000000
+ transition: 8'00001000 24'--011111--------0------- -> 8'01000000 16'0001000010000000
+ transition: 8'00001000 24'--011111--------1----0-- -> 8'00001000 16'0001000000010000
+ transition: 8'00001000 24'--011111--------1----1-- -> 8'01000000 16'0001000010000000
+ transition: 8'00001000 24'--111111---------------- -> 8'01000000 16'0001000010000000
+ transition: 8'00000010 24'--00---0-0-------------- -> 8'00000010 16'0000010000000100
+ transition: 8'00000010 24'--00---001-------------- -> 8'00000010 16'0000010000000100
+ transition: 8'00000010 24'--00---011-------------- -> 8'01000000 16'0000010010000000
+ transition: 8'00000010 24'--10---0---------------- -> 8'01000000 16'0000010010000000
+ transition: 8'00000010 24'--000-01-0-------------- -> 8'00000010 16'0000010000000100
+ transition: 8'00000010 24'--000-0101-------------- -> 8'00000010 16'0000010000000100
+ transition: 8'00000010 24'--000-0111-------------- -> 8'01000000 16'0000010010000000
+ transition: 8'00000010 24'--100-01---------------- -> 8'01000000 16'0000010010000000
+ transition: 8'00000010 24'---00011---------------- -> 8'10000000 16'0000010100000000
+ transition: 8'00000010 24'--000111-0-------------- -> 8'00000010 16'0000010000000100
+ transition: 8'00000010 24'--00011101-------------- -> 8'00000010 16'0000010000000100
+ transition: 8'00000010 24'--00011111-------------- -> 8'01000000 16'0000010010000000
+ transition: 8'00000010 24'--100111---------------- -> 8'01000000 16'0000010010000000
+ transition: 8'00000010 24'---010-1---------------- -> 8'10000000 16'0000010100000000
+ transition: 8'00000010 24'--001101-0-------------- -> 8'00000010 16'0000010000000100
+ transition: 8'00000010 24'--00110101-------------- -> 8'00000010 16'0000010000000100
+ transition: 8'00000010 24'--00110111-------------- -> 8'01000000 16'0000010010000000
+ transition: 8'00000010 24'--101101---------------- -> 8'01000000 16'0000010010000000
+ transition: 8'00000010 24'--001111-0-------------- -> 8'00000010 16'0000010000000100
+ transition: 8'00000010 24'--00111101-------------- -> 8'00000010 16'0000010000000100
+ transition: 8'00000010 24'--00111111-------------- -> 8'01000000 16'0000010010000000
+ transition: 8'00000010 24'--101111---------------- -> 8'01000000 16'0000010010000000
+ transition: 8'00000010 24'---1-0------------------ -> 8'10000000 16'0000010100000000
+ transition: 8'00000010 24'--01-1-0-0-------------- -> 8'00000010 16'0000010000000100
+ transition: 8'00000010 24'--01-1-001-------------- -> 8'00000010 16'0000010000000100
+ transition: 8'00000010 24'--01-1-011-------------- -> 8'01000000 16'0000010010000000
+ transition: 8'00000010 24'--11-1-0---------------- -> 8'01000000 16'0000010010000000
+ transition: 8'00000010 24'--010101-0-------------- -> 8'00000010 16'0000010000000100
+ transition: 8'00000010 24'--01010101-------------- -> 8'00000010 16'0000010000000100
+ transition: 8'00000010 24'--01010111-------------- -> 8'01000000 16'0000010010000000
+ transition: 8'00000010 24'--110101---------------- -> 8'01000000 16'0000010010000000
+ transition: 8'00000010 24'--010111-0-------------- -> 8'00000010 16'0000010000000100
+ transition: 8'00000010 24'--01011101-------------- -> 8'00000010 16'0000010000000100
+ transition: 8'00000010 24'--01011111-------------- -> 8'01000000 16'0000010010000000
+ transition: 8'00000010 24'--110111---------------- -> 8'01000000 16'0000010010000000
+ transition: 8'00000010 24'--011101-0-------------- -> 8'00000010 16'0000010000000100
+ transition: 8'00000010 24'--01110101-------------- -> 8'00000010 16'0000010000000100
+ transition: 8'00000010 24'--01110111-------------- -> 8'01000000 16'0000010010000000
+ transition: 8'00000010 24'--111101---------------- -> 8'01000000 16'0000010010000000
+ transition: 8'00000010 24'--011111-0-------------- -> 8'00000010 16'0000010000000100
+ transition: 8'00000010 24'--01111101-------------- -> 8'00000010 16'0000010000000100
+ transition: 8'00000010 24'--01111111-------------- -> 8'01000000 16'0000010010000000
+ transition: 8'00000010 24'--111111---------------- -> 8'01000000 16'0000010010000000
+ transition: 8'00000001 24'--00---0-0-------------- -> 8'00000001 16'0000001000000010
+ transition: 8'00000001 24'--00---001-------------- -> 8'00000001 16'0000001000000010
+ transition: 8'00000001 24'--00---011-------------- -> 8'01000000 16'0000001010000000
+ transition: 8'00000001 24'--10---0---------------- -> 8'01000000 16'0000001010000000
+ transition: 8'00000001 24'--000-01-0-------------- -> 8'00000001 16'0000001000000010
+ transition: 8'00000001 24'--000-0101-------------- -> 8'00000001 16'0000001000000010
+ transition: 8'00000001 24'--000-0111-------------- -> 8'01000000 16'0000001010000000
+ transition: 8'00000001 24'--100-01---------------- -> 8'01000000 16'0000001010000000
+ transition: 8'00000001 24'---00011---------------- -> 8'10000000 16'0000001100000000
+ transition: 8'00000001 24'--000111-0-------------- -> 8'00000001 16'0000001000000010
+ transition: 8'00000001 24'--00011101-------------- -> 8'00000001 16'0000001000000010
+ transition: 8'00000001 24'--00011111-------------- -> 8'01000000 16'0000001010000000
+ transition: 8'00000001 24'--100111---------------- -> 8'01000000 16'0000001010000000
+ transition: 8'00000001 24'---010-1---------------- -> 8'10000000 16'0000001100000000
+ transition: 8'00000001 24'--001101-0-------------- -> 8'00000001 16'0000001000000010
+ transition: 8'00000001 24'--00110101-------------- -> 8'00000001 16'0000001000000010
+ transition: 8'00000001 24'--00110111-------------- -> 8'01000000 16'0000001010000000
+ transition: 8'00000001 24'--101101---------------- -> 8'01000000 16'0000001010000000
+ transition: 8'00000001 24'--001111-0-------------- -> 8'00000001 16'0000001000000010
+ transition: 8'00000001 24'--00111101-------------- -> 8'00000001 16'0000001000000010
+ transition: 8'00000001 24'--00111111-------------- -> 8'01000000 16'0000001010000000
+ transition: 8'00000001 24'--101111---------------- -> 8'01000000 16'0000001010000000
+ transition: 8'00000001 24'---1-0------------------ -> 8'10000000 16'0000001100000000
+ transition: 8'00000001 24'--01-1-0-0-------------- -> 8'00000001 16'0000001000000010
+ transition: 8'00000001 24'--01-1-001-------------- -> 8'00000001 16'0000001000000010
+ transition: 8'00000001 24'--01-1-011-------------- -> 8'01000000 16'0000001010000000
+ transition: 8'00000001 24'--11-1-0---------------- -> 8'01000000 16'0000001010000000
+ transition: 8'00000001 24'--010101-0-------------- -> 8'00000001 16'0000001000000010
+ transition: 8'00000001 24'--01010101-------------- -> 8'00000001 16'0000001000000010
+ transition: 8'00000001 24'--01010111-------------- -> 8'01000000 16'0000001010000000
+ transition: 8'00000001 24'--110101---------------- -> 8'01000000 16'0000001010000000
+ transition: 8'00000001 24'--010111-0-------------- -> 8'00000001 16'0000001000000010
+ transition: 8'00000001 24'--01011101-------------- -> 8'00000001 16'0000001000000010
+ transition: 8'00000001 24'--01011111-------------- -> 8'01000000 16'0000001010000000
+ transition: 8'00000001 24'--110111---------------- -> 8'01000000 16'0000001010000000
+ transition: 8'00000001 24'--011101-0-------------- -> 8'00000001 16'0000001000000010
+ transition: 8'00000001 24'--01110101-------------- -> 8'00000001 16'0000001000000010
+ transition: 8'00000001 24'--01110111-------------- -> 8'01000000 16'0000001010000000
+ transition: 8'00000001 24'--111101---------------- -> 8'01000000 16'0000001010000000
+ transition: 8'00000001 24'--011111-0-------------- -> 8'00000001 16'0000001000000010
+ transition: 8'00000001 24'--01111101-------------- -> 8'00000001 16'0000001000000010
+ transition: 8'00000001 24'--01111111-------------- -> 8'01000000 16'0000001010000000
+ transition: 8'00000001 24'--111111---------------- -> 8'01000000 16'0000001010000000
+Extracting FSM `\softshell.cpus[0].core.cpu.picorv32_core.mem_wordsize' from module `\user_proj_example'.
+ found $dff cell for state register: $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procdff$16346
+ root of input selection tree: $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$0\mem_wordsize[1:0]
+ found ctrl input: \softshell.cpus[0].core.cpu.wb_rst_i
+ found ctrl input: $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$5572_CMP
+ found ctrl input: $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$5573_CMP
+ found ctrl input: $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$eq$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1308$4645_Y
+ found ctrl input: $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$logic_or$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1852$4804_Y
+ found ctrl input: \softshell.cpus[0].core.cpu.picorv32_core.mem_do_rdata
+ found ctrl input: \softshell.cpus[0].core.cpu.picorv32_core.instr_lw
+ found ctrl input: $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$logic_or$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1882$4813_Y
+ found ctrl input: $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$logic_or$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1881$4812_Y
+ found state code: 2'00
+ found state code: 2'01
+ found state code: 2'10
+ found ctrl input: \softshell.cpus[0].core.cpu.picorv32_core.mem_do_wdata
+ found ctrl input: \softshell.cpus[0].core.cpu.picorv32_core.instr_sw
+ found ctrl input: \softshell.cpus[0].core.cpu.picorv32_core.instr_sh
+ found ctrl input: \softshell.cpus[0].core.cpu.picorv32_core.instr_sb
+ found ctrl output: $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$eq$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1918$4824_Y
+ found ctrl output: $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$eq$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1925$4831_Y
+ found ctrl output: $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$8339_CMP
+ ctrl inputs: { \softshell.cpus[0].core.cpu.wb_rst_i $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$5573_CMP $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$5572_CMP $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$logic_or$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1882$4813_Y $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$logic_or$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1881$4812_Y $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$logic_or$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1852$4804_Y $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$eq$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1308$4645_Y \softshell.cpus[0].core.cpu.picorv32_core.instr_sw \softshell.cpus[0].core.cpu.picorv32_core.instr_sh \softshell.cpus[0].core.cpu.picorv32_core.instr_sb \softshell.cpus[0].core.cpu.picorv32_core.instr_lw \softshell.cpus[0].core.cpu.picorv32_core.mem_do_wdata \softshell.cpus[0].core.cpu.picorv32_core.mem_do_rdata }
+ ctrl outputs: { $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$8339_CMP $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$eq$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1925$4831_Y $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$eq$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1918$4824_Y $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$0\mem_wordsize[1:0] }
+ transition: 2'00 13'000---0------ -> 2'00 5'00100
+ transition: 2'00 13'0-----1------ -> 2'00 5'00100
+ transition: 2'00 13'01---0------- -> 2'00 5'00100
+ transition: 2'00 13'01---1-000-0- -> INVALID_STATE(2'xx) 5'001xx <ignored invalid transition!>
+ transition: 2'00 13'01---1---1-0- -> 2'10 5'00110
+ transition: 2'00 13'01---1--1--0- -> 2'01 5'00101
+ transition: 2'00 13'01---1-1---0- -> 2'00 5'00100
+ transition: 2'00 13'01---1-----1- -> 2'00 5'00100
+ transition: 2'00 13'0-1--0------- -> 2'00 5'00100
+ transition: 2'00 13'0-1001----0-0 -> INVALID_STATE(2'xx) 5'001xx <ignored invalid transition!>
+ transition: 2'00 13'0-1-11------0 -> 2'10 5'00110
+ transition: 2'00 13'0-11-1------0 -> 2'01 5'00101
+ transition: 2'00 13'0-1--1----1-0 -> 2'00 5'00100
+ transition: 2'00 13'0-1--1------1 -> 2'00 5'00100
+ transition: 2'00 13'1------------ -> 2'00 5'00100
+ transition: 2'10 13'000---0------ -> 2'10 5'10010
+ transition: 2'10 13'0-----1------ -> 2'00 5'10000
+ transition: 2'10 13'01---0------- -> 2'10 5'10010
+ transition: 2'10 13'01---1-000-0- -> INVALID_STATE(2'xx) 5'100xx <ignored invalid transition!>
+ transition: 2'10 13'01---1---1-0- -> 2'10 5'10010
+ transition: 2'10 13'01---1--1--0- -> 2'01 5'10001
+ transition: 2'10 13'01---1-1---0- -> 2'00 5'10000
+ transition: 2'10 13'01---1-----1- -> 2'10 5'10010
+ transition: 2'10 13'0-1--0------- -> 2'10 5'10010
+ transition: 2'10 13'0-1001----0-0 -> INVALID_STATE(2'xx) 5'100xx <ignored invalid transition!>
+ transition: 2'10 13'0-1-11------0 -> 2'10 5'10010
+ transition: 2'10 13'0-11-1------0 -> 2'01 5'10001
+ transition: 2'10 13'0-1--1----1-0 -> 2'00 5'10000
+ transition: 2'10 13'0-1--1------1 -> 2'10 5'10010
+ transition: 2'10 13'1------------ -> 2'10 5'10010
+ transition: 2'01 13'000---0------ -> 2'01 5'01001
+ transition: 2'01 13'0-----1------ -> 2'00 5'01000
+ transition: 2'01 13'01---0------- -> 2'01 5'01001
+ transition: 2'01 13'01---1-000-0- -> INVALID_STATE(2'xx) 5'010xx <ignored invalid transition!>
+ transition: 2'01 13'01---1---1-0- -> 2'10 5'01010
+ transition: 2'01 13'01---1--1--0- -> 2'01 5'01001
+ transition: 2'01 13'01---1-1---0- -> 2'00 5'01000
+ transition: 2'01 13'01---1-----1- -> 2'01 5'01001
+ transition: 2'01 13'0-1--0------- -> 2'01 5'01001
+ transition: 2'01 13'0-1001----0-0 -> INVALID_STATE(2'xx) 5'010xx <ignored invalid transition!>
+ transition: 2'01 13'0-1-11------0 -> 2'10 5'01010
+ transition: 2'01 13'0-11-1------0 -> 2'01 5'01001
+ transition: 2'01 13'0-1--1----1-0 -> 2'00 5'01000
+ transition: 2'01 13'0-1--1------1 -> 2'01 5'01001
+ transition: 2'01 13'1------------ -> 2'01 5'01001
+Extracting FSM `\softshell.cpus[0].core.cpu.state' from module `\user_proj_example'.
+ found $dff cell for state register: $flatten\softshell.\cpus[0].core.\cpu.$procdff$16288
+ root of input selection tree: $flatten\softshell.\cpus[0].core.\cpu.$0\state[1:0]
+ found reset state: 2'00 (guessed from mux tree)
+ found ctrl input: \softshell.cpus[0].core.cpu.wb_rst_i
+ found ctrl input: $flatten\softshell.\cpus[0].core.\cpu.$procmux$5101_CMP
+ found ctrl input: $flatten\softshell.\cpus[0].core.\cpu.$procmux$5114_CMP
+ found state code: 2'00
+ found ctrl input: \softshell.cpus[0].core.cpu.wbm_ack_i
+ found state code: 2'10
+ found ctrl input: \softshell.cpus[0].core.cpu.picorv32_core.mem_valid
+ found state code: 2'01
+ found ctrl output: $flatten\softshell.\cpus[0].core.\cpu.$procmux$5114_CMP
+ found ctrl output: $flatten\softshell.\cpus[0].core.\cpu.$procmux$5107_CMP
+ found ctrl output: $flatten\softshell.\cpus[0].core.\cpu.$procmux$5101_CMP
+ ctrl inputs: { \softshell.cpus[0].core.cpu.wb_rst_i \softshell.cpus[0].core.cpu.wbm_ack_i \softshell.cpus[0].core.cpu.picorv32_core.mem_valid }
+ ctrl outputs: { $flatten\softshell.\cpus[0].core.\cpu.$0\state[1:0] $flatten\softshell.\cpus[0].core.\cpu.$procmux$5101_CMP $flatten\softshell.\cpus[0].core.\cpu.$procmux$5107_CMP $flatten\softshell.\cpus[0].core.\cpu.$procmux$5114_CMP }
+ transition: 2'00 3'0-0 -> 2'00 5'00001
+ transition: 2'00 3'0-1 -> 2'01 5'01001
+ transition: 2'00 3'1-- -> 2'00 5'00001
+ transition: 2'10 3'0-- -> 2'00 5'00010
+ transition: 2'10 3'1-- -> 2'00 5'00010
+ transition: 2'01 3'00- -> 2'01 5'01100
+ transition: 2'01 3'01- -> 2'10 5'10100
+ transition: 2'01 3'1-- -> 2'00 5'00100
+Extracting FSM `\softshell.cpus[1].core.cpu.picorv32_core.cpu_state' from module `\user_proj_example'.
+ found $dff cell for state register: $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procdff$16567
+ root of input selection tree: $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$0\cpu_state[7:0]
+ found ctrl input: $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1933$4157_Y
+ found ctrl input: $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1917$4140_Y
+ found ctrl input: \softshell.cpus[1].core.cpu.wb_rst_i
+ found ctrl input: $auto$opt_reduce.cc:134:opt_mux$17187
+ found ctrl input: $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10149_CMP
+ found ctrl input: $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10008_CMP
+ found ctrl input: $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10165_CMP
+ found ctrl input: $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10018_CMP
+ found ctrl input: $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$eq$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1308$3962_Y
+ found ctrl input: $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$logic_or$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1852$4121_Y
+ found ctrl input: $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1867$4125_Y
+ found state code: 8'01000000
+ found ctrl input: $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$eq$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1826$4103_Y
+ found ctrl input: \softshell.cpus[1].core.cpu.picorv32_core.is_beq_bne_blt_bge_bltu_bgeu
+ found ctrl input: \softshell.cpus[1].core.cpu.picorv32_core.mem_done
+ found ctrl input: \softshell.cpus[1].core.cpu.picorv32_core.is_sb_sh_sw
+ found ctrl input: \softshell.cpus[1].core.cpu.picorv32_core.instr_trap
+ found state code: 8'00001000
+ found state code: 8'00000010
+ found ctrl input: \softshell.cpus[1].core.flexio.pcpi_ready
+ found ctrl input: $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1600$4057_Y
+ found ctrl input: $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1603$4061_Y
+ found state code: 8'10000000
+ found ctrl input: $auto$opt_reduce.cc:134:opt_mux$16933
+ found ctrl input: $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1691$4075_Y
+ found ctrl input: $auto$opt_reduce.cc:134:opt_mux$16931
+ found state code: 8'00000001
+ found ctrl input: $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1533$4036_Y
+ found ctrl input: $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1543$4044_Y
+ found ctrl input: \softshell.cpus[1].core.cpu.picorv32_core.decoder_trigger
+ found ctrl input: \softshell.cpus[1].core.cpu.picorv32_core.instr_jal
+ found state code: 8'00100000
+ found ctrl input: $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1925$4150_Y
+ found ctrl input: $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1918$4143_Y
+ found ctrl input: $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1920$4147_Y
+ found ctrl output: $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$eq$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1308$3962_Y
+ found ctrl output: $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$9225_CMP
+ found ctrl output: $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10008_CMP
+ found ctrl output: $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10018_CMP
+ found ctrl output: $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10034_CMP
+ found ctrl output: $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10149_CMP
+ found ctrl output: $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10165_CMP
+ found ctrl output: $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10223_CMP
+ ctrl inputs: { $auto$opt_reduce.cc:134:opt_mux$16931 $auto$opt_reduce.cc:134:opt_mux$16933 $auto$opt_reduce.cc:134:opt_mux$17187 \softshell.cpus[1].core.cpu.wb_rst_i $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1933$4157_Y $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1925$4150_Y $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1920$4147_Y $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1918$4143_Y $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1917$4140_Y $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1867$4125_Y $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$logic_or$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1852$4121_Y $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$eq$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1826$4103_Y $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1691$4075_Y $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1603$4061_Y $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1600$4057_Y $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1543$4044_Y $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1533$4036_Y \softshell.cpus[1].core.cpu.picorv32_core.is_beq_bne_blt_bge_bltu_bgeu \softshell.cpus[1].core.cpu.picorv32_core.is_sb_sh_sw \softshell.cpus[1].core.cpu.picorv32_core.decoder_trigger \softshell.cpus[1].core.cpu.picorv32_core.instr_trap \softshell.cpus[1].core.cpu.picorv32_core.instr_jal \softshell.cpus[1].core.cpu.picorv32_core.mem_done \softshell.cpus[1].core.flexio.pcpi_ready }
+ ctrl outputs: { $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10223_CMP $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10165_CMP $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10149_CMP $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10034_CMP $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10018_CMP $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10008_CMP $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$9225_CMP $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$0\cpu_state[7:0] $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$eq$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1308$3962_Y }
+ transition: 8'10000000 24'---00---0--------------- -> 8'10000000 16'0000001100000000
+ transition: 8'10000000 24'---10---0--------------- -> 8'01000000 16'0000001010000000
+ transition: 8'10000000 24'---000-01--------------- -> 8'10000000 16'0000001100000000
+ transition: 8'10000000 24'---100-01--------------- -> 8'01000000 16'0000001010000000
+ transition: 8'10000000 24'----00011--------------- -> 8'10000000 16'0000001100000000
+ transition: 8'10000000 24'---000111--------------- -> 8'10000000 16'0000001100000000
+ transition: 8'10000000 24'---100111--------------- -> 8'01000000 16'0000001010000000
+ transition: 8'10000000 24'----010-1--------------- -> 8'10000000 16'0000001100000000
+ transition: 8'10000000 24'---001101--------------- -> 8'10000000 16'0000001100000000
+ transition: 8'10000000 24'---101101--------------- -> 8'01000000 16'0000001010000000
+ transition: 8'10000000 24'---001111--------------- -> 8'10000000 16'0000001100000000
+ transition: 8'10000000 24'---101111--------------- -> 8'01000000 16'0000001010000000
+ transition: 8'10000000 24'----1-0----------------- -> 8'10000000 16'0000001100000000
+ transition: 8'10000000 24'---01-1-0--------------- -> 8'10000000 16'0000001100000000
+ transition: 8'10000000 24'---11-1-0--------------- -> 8'01000000 16'0000001010000000
+ transition: 8'10000000 24'---010101--------------- -> 8'10000000 16'0000001100000000
+ transition: 8'10000000 24'---110101--------------- -> 8'01000000 16'0000001010000000
+ transition: 8'10000000 24'---010111--------------- -> 8'10000000 16'0000001100000000
+ transition: 8'10000000 24'---110111--------------- -> 8'01000000 16'0000001010000000
+ transition: 8'10000000 24'---011101--------------- -> 8'10000000 16'0000001100000000
+ transition: 8'10000000 24'---111101--------------- -> 8'01000000 16'0000001010000000
+ transition: 8'10000000 24'---011111--------------- -> 8'10000000 16'0000001100000000
+ transition: 8'10000000 24'---111111--------------- -> 8'01000000 16'0000001010000000
+ transition: 8'01000000 24'---00---0------00--0---- -> 8'01000000 16'0000000010000001
+ transition: 8'01000000 24'---00---0------00--1-0-- -> 8'00100000 16'0000000001000001
+ transition: 8'01000000 24'---00---0------00--1-1-- -> 8'01000000 16'0000000010000001
+ transition: 8'01000000 24'---00---0------10------- -> 8'01000000 16'0000000010000001
+ transition: 8'01000000 24'---00---0-------1------- -> 8'01000000 16'0000000010000001
+ transition: 8'01000000 24'---10---0--------------- -> 8'01000000 16'0000000010000001
+ transition: 8'01000000 24'---000-01------00--0---- -> 8'01000000 16'0000000010000001
+ transition: 8'01000000 24'---000-01------00--1-0-- -> 8'00100000 16'0000000001000001
+ transition: 8'01000000 24'---000-01------00--1-1-- -> 8'01000000 16'0000000010000001
+ transition: 8'01000000 24'---000-01------10------- -> 8'01000000 16'0000000010000001
+ transition: 8'01000000 24'---000-01-------1------- -> 8'01000000 16'0000000010000001
+ transition: 8'01000000 24'---100-01--------------- -> 8'01000000 16'0000000010000001
+ transition: 8'01000000 24'----00011--------------- -> 8'10000000 16'0000000100000001
+ transition: 8'01000000 24'---000111------00--0---- -> 8'01000000 16'0000000010000001
+ transition: 8'01000000 24'---000111------00--1-0-- -> 8'00100000 16'0000000001000001
+ transition: 8'01000000 24'---000111------00--1-1-- -> 8'01000000 16'0000000010000001
+ transition: 8'01000000 24'---000111------10------- -> 8'01000000 16'0000000010000001
+ transition: 8'01000000 24'---000111-------1------- -> 8'01000000 16'0000000010000001
+ transition: 8'01000000 24'---100111--------------- -> 8'01000000 16'0000000010000001
+ transition: 8'01000000 24'----010-1--------------- -> 8'10000000 16'0000000100000001
+ transition: 8'01000000 24'---001101------00--0---- -> 8'01000000 16'0000000010000001
+ transition: 8'01000000 24'---001101------00--1-0-- -> 8'00100000 16'0000000001000001
+ transition: 8'01000000 24'---001101------00--1-1-- -> 8'01000000 16'0000000010000001
+ transition: 8'01000000 24'---001101------10------- -> 8'01000000 16'0000000010000001
+ transition: 8'01000000 24'---001101-------1------- -> 8'01000000 16'0000000010000001
+ transition: 8'01000000 24'---101101--------------- -> 8'01000000 16'0000000010000001
+ transition: 8'01000000 24'---001111------00--0---- -> 8'01000000 16'0000000010000001
+ transition: 8'01000000 24'---001111------00--1-0-- -> 8'00100000 16'0000000001000001
+ transition: 8'01000000 24'---001111------00--1-1-- -> 8'01000000 16'0000000010000001
+ transition: 8'01000000 24'---001111------10------- -> 8'01000000 16'0000000010000001
+ transition: 8'01000000 24'---001111-------1------- -> 8'01000000 16'0000000010000001
+ transition: 8'01000000 24'---101111--------------- -> 8'01000000 16'0000000010000001
+ transition: 8'01000000 24'----1-0----------------- -> 8'10000000 16'0000000100000001
+ transition: 8'01000000 24'---01-1-0------00--0---- -> 8'01000000 16'0000000010000001
+ transition: 8'01000000 24'---01-1-0------00--1-0-- -> 8'00100000 16'0000000001000001
+ transition: 8'01000000 24'---01-1-0------00--1-1-- -> 8'01000000 16'0000000010000001
+ transition: 8'01000000 24'---01-1-0------10------- -> 8'01000000 16'0000000010000001
+ transition: 8'01000000 24'---01-1-0-------1------- -> 8'01000000 16'0000000010000001
+ transition: 8'01000000 24'---11-1-0--------------- -> 8'01000000 16'0000000010000001
+ transition: 8'01000000 24'---010101------00--0---- -> 8'01000000 16'0000000010000001
+ transition: 8'01000000 24'---010101------00--1-0-- -> 8'00100000 16'0000000001000001
+ transition: 8'01000000 24'---010101------00--1-1-- -> 8'01000000 16'0000000010000001
+ transition: 8'01000000 24'---010101------10------- -> 8'01000000 16'0000000010000001
+ transition: 8'01000000 24'---010101-------1------- -> 8'01000000 16'0000000010000001
+ transition: 8'01000000 24'---110101--------------- -> 8'01000000 16'0000000010000001
+ transition: 8'01000000 24'---010111------00--0---- -> 8'01000000 16'0000000010000001
+ transition: 8'01000000 24'---010111------00--1-0-- -> 8'00100000 16'0000000001000001
+ transition: 8'01000000 24'---010111------00--1-1-- -> 8'01000000 16'0000000010000001
+ transition: 8'01000000 24'---010111------10------- -> 8'01000000 16'0000000010000001
+ transition: 8'01000000 24'---010111-------1------- -> 8'01000000 16'0000000010000001
+ transition: 8'01000000 24'---110111--------------- -> 8'01000000 16'0000000010000001
+ transition: 8'01000000 24'---011101------00--0---- -> 8'01000000 16'0000000010000001
+ transition: 8'01000000 24'---011101------00--1-0-- -> 8'00100000 16'0000000001000001
+ transition: 8'01000000 24'---011101------00--1-1-- -> 8'01000000 16'0000000010000001
+ transition: 8'01000000 24'---011101------10------- -> 8'01000000 16'0000000010000001
+ transition: 8'01000000 24'---011101-------1------- -> 8'01000000 16'0000000010000001
+ transition: 8'01000000 24'---111101--------------- -> 8'01000000 16'0000000010000001
+ transition: 8'01000000 24'---011111------00--0---- -> 8'01000000 16'0000000010000001
+ transition: 8'01000000 24'---011111------00--1-0-- -> 8'00100000 16'0000000001000001
+ transition: 8'01000000 24'---011111------00--1-1-- -> 8'01000000 16'0000000010000001
+ transition: 8'01000000 24'---011111------10------- -> 8'01000000 16'0000000010000001
+ transition: 8'01000000 24'---011111-------1------- -> 8'01000000 16'0000000010000001
+ transition: 8'01000000 24'---111111--------------- -> 8'01000000 16'0000000010000001
+ transition: 8'00100000 24'00-00---0---0-----0-0--- -> 8'00001000 16'0000100000010000
+ transition: 8'00100000 24'00-00---0---0-----1----- -> 8'00000010 16'0000100000000100
+ transition: 8'00100000 24'---00---0-----0-----1--0 -> 8'00100000 16'0000100001000000
+ transition: 8'00100000 24'---00---0----01-----1--0 -> 8'10000000 16'0000100100000000
+ transition: 8'00100000 24'---00---0----11-----1--0 -> 8'01000000 16'0000100010000000
+ transition: 8'00100000 24'---00---0-----------1--1 -> 8'01000000 16'0000100010000000
+ transition: 8'00100000 24'1--00---0--------------- -> 8'01000000 16'0000100010000000
+ transition: 8'00100000 24'---00---0---1----------- -> 8'00000001 16'0000100000000010
+ transition: 8'00100000 24'-1-00---0--------------- -> 8'00001000 16'0000100000010000
+ transition: 8'00100000 24'---10---0--------------- -> 8'01000000 16'0000100010000000
+ transition: 8'00100000 24'00-000-01---0-----0-0--- -> 8'00001000 16'0000100000010000
+ transition: 8'00100000 24'00-000-01---0-----1----- -> 8'00000010 16'0000100000000100
+ transition: 8'00100000 24'---000-01-----0-----1--0 -> 8'00100000 16'0000100001000000
+ transition: 8'00100000 24'---000-01----01-----1--0 -> 8'10000000 16'0000100100000000
+ transition: 8'00100000 24'---000-01----11-----1--0 -> 8'01000000 16'0000100010000000
+ transition: 8'00100000 24'---000-01-----------1--1 -> 8'01000000 16'0000100010000000
+ transition: 8'00100000 24'1--000-01--------------- -> 8'01000000 16'0000100010000000
+ transition: 8'00100000 24'---000-01---1----------- -> 8'00000001 16'0000100000000010
+ transition: 8'00100000 24'-1-000-01--------------- -> 8'00001000 16'0000100000010000
+ transition: 8'00100000 24'---100-01--------------- -> 8'01000000 16'0000100010000000
+ transition: 8'00100000 24'----00011--------------- -> 8'10000000 16'0000100100000000
+ transition: 8'00100000 24'00-000111---0-----0-0--- -> 8'00001000 16'0000100000010000
+ transition: 8'00100000 24'00-000111---0-----1----- -> 8'00000010 16'0000100000000100
+ transition: 8'00100000 24'---000111-----0-----1--0 -> 8'00100000 16'0000100001000000
+ transition: 8'00100000 24'---000111----01-----1--0 -> 8'10000000 16'0000100100000000
+ transition: 8'00100000 24'---000111----11-----1--0 -> 8'01000000 16'0000100010000000
+ transition: 8'00100000 24'---000111-----------1--1 -> 8'01000000 16'0000100010000000
+ transition: 8'00100000 24'1--000111--------------- -> 8'01000000 16'0000100010000000
+ transition: 8'00100000 24'---000111---1----------- -> 8'00000001 16'0000100000000010
+ transition: 8'00100000 24'-1-000111--------------- -> 8'00001000 16'0000100000010000
+ transition: 8'00100000 24'---100111--------------- -> 8'01000000 16'0000100010000000
+ transition: 8'00100000 24'----010-1--------------- -> 8'10000000 16'0000100100000000
+ transition: 8'00100000 24'00-001101---0-----0-0--- -> 8'00001000 16'0000100000010000
+ transition: 8'00100000 24'00-001101---0-----1----- -> 8'00000010 16'0000100000000100
+ transition: 8'00100000 24'---001101-----0-----1--0 -> 8'00100000 16'0000100001000000
+ transition: 8'00100000 24'---001101----01-----1--0 -> 8'10000000 16'0000100100000000
+ transition: 8'00100000 24'---001101----11-----1--0 -> 8'01000000 16'0000100010000000
+ transition: 8'00100000 24'---001101-----------1--1 -> 8'01000000 16'0000100010000000
+ transition: 8'00100000 24'1--001101--------------- -> 8'01000000 16'0000100010000000
+ transition: 8'00100000 24'---001101---1----------- -> 8'00000001 16'0000100000000010
+ transition: 8'00100000 24'-1-001101--------------- -> 8'00001000 16'0000100000010000
+ transition: 8'00100000 24'---101101--------------- -> 8'01000000 16'0000100010000000
+ transition: 8'00100000 24'00-001111---0-----0-0--- -> 8'00001000 16'0000100000010000
+ transition: 8'00100000 24'00-001111---0-----1----- -> 8'00000010 16'0000100000000100
+ transition: 8'00100000 24'---001111-----0-----1--0 -> 8'00100000 16'0000100001000000
+ transition: 8'00100000 24'---001111----01-----1--0 -> 8'10000000 16'0000100100000000
+ transition: 8'00100000 24'---001111----11-----1--0 -> 8'01000000 16'0000100010000000
+ transition: 8'00100000 24'---001111-----------1--1 -> 8'01000000 16'0000100010000000
+ transition: 8'00100000 24'1--001111--------------- -> 8'01000000 16'0000100010000000
+ transition: 8'00100000 24'---001111---1----------- -> 8'00000001 16'0000100000000010
+ transition: 8'00100000 24'-1-001111--------------- -> 8'00001000 16'0000100000010000
+ transition: 8'00100000 24'---101111--------------- -> 8'01000000 16'0000100010000000
+ transition: 8'00100000 24'----1-0----------------- -> 8'10000000 16'0000100100000000
+ transition: 8'00100000 24'00-01-1-0---0-----0-0--- -> 8'00001000 16'0000100000010000
+ transition: 8'00100000 24'00-01-1-0---0-----1----- -> 8'00000010 16'0000100000000100
+ transition: 8'00100000 24'---01-1-0-----0-----1--0 -> 8'00100000 16'0000100001000000
+ transition: 8'00100000 24'---01-1-0----01-----1--0 -> 8'10000000 16'0000100100000000
+ transition: 8'00100000 24'---01-1-0----11-----1--0 -> 8'01000000 16'0000100010000000
+ transition: 8'00100000 24'---01-1-0-----------1--1 -> 8'01000000 16'0000100010000000
+ transition: 8'00100000 24'1--01-1-0--------------- -> 8'01000000 16'0000100010000000
+ transition: 8'00100000 24'---01-1-0---1----------- -> 8'00000001 16'0000100000000010
+ transition: 8'00100000 24'-1-01-1-0--------------- -> 8'00001000 16'0000100000010000
+ transition: 8'00100000 24'---11-1-0--------------- -> 8'01000000 16'0000100010000000
+ transition: 8'00100000 24'00-010101---0-----0-0--- -> 8'00001000 16'0000100000010000
+ transition: 8'00100000 24'00-010101---0-----1----- -> 8'00000010 16'0000100000000100
+ transition: 8'00100000 24'---010101-----0-----1--0 -> 8'00100000 16'0000100001000000
+ transition: 8'00100000 24'---010101----01-----1--0 -> 8'10000000 16'0000100100000000
+ transition: 8'00100000 24'---010101----11-----1--0 -> 8'01000000 16'0000100010000000
+ transition: 8'00100000 24'---010101-----------1--1 -> 8'01000000 16'0000100010000000
+ transition: 8'00100000 24'1--010101--------------- -> 8'01000000 16'0000100010000000
+ transition: 8'00100000 24'---010101---1----------- -> 8'00000001 16'0000100000000010
+ transition: 8'00100000 24'-1-010101--------------- -> 8'00001000 16'0000100000010000
+ transition: 8'00100000 24'---110101--------------- -> 8'01000000 16'0000100010000000
+ transition: 8'00100000 24'00-010111---0-----0-0--- -> 8'00001000 16'0000100000010000
+ transition: 8'00100000 24'00-010111---0-----1----- -> 8'00000010 16'0000100000000100
+ transition: 8'00100000 24'---010111-----0-----1--0 -> 8'00100000 16'0000100001000000
+ transition: 8'00100000 24'---010111----01-----1--0 -> 8'10000000 16'0000100100000000
+ transition: 8'00100000 24'---010111----11-----1--0 -> 8'01000000 16'0000100010000000
+ transition: 8'00100000 24'---010111-----------1--1 -> 8'01000000 16'0000100010000000
+ transition: 8'00100000 24'1--010111--------------- -> 8'01000000 16'0000100010000000
+ transition: 8'00100000 24'---010111---1----------- -> 8'00000001 16'0000100000000010
+ transition: 8'00100000 24'-1-010111--------------- -> 8'00001000 16'0000100000010000
+ transition: 8'00100000 24'---110111--------------- -> 8'01000000 16'0000100010000000
+ transition: 8'00100000 24'00-011101---0-----0-0--- -> 8'00001000 16'0000100000010000
+ transition: 8'00100000 24'00-011101---0-----1----- -> 8'00000010 16'0000100000000100
+ transition: 8'00100000 24'---011101-----0-----1--0 -> 8'00100000 16'0000100001000000
+ transition: 8'00100000 24'---011101----01-----1--0 -> 8'10000000 16'0000100100000000
+ transition: 8'00100000 24'---011101----11-----1--0 -> 8'01000000 16'0000100010000000
+ transition: 8'00100000 24'---011101-----------1--1 -> 8'01000000 16'0000100010000000
+ transition: 8'00100000 24'1--011101--------------- -> 8'01000000 16'0000100010000000
+ transition: 8'00100000 24'---011101---1----------- -> 8'00000001 16'0000100000000010
+ transition: 8'00100000 24'-1-011101--------------- -> 8'00001000 16'0000100000010000
+ transition: 8'00100000 24'---111101--------------- -> 8'01000000 16'0000100010000000
+ transition: 8'00100000 24'00-011111---0-----0-0--- -> 8'00001000 16'0000100000010000
+ transition: 8'00100000 24'00-011111---0-----1----- -> 8'00000010 16'0000100000000100
+ transition: 8'00100000 24'---011111-----0-----1--0 -> 8'00100000 16'0000100001000000
+ transition: 8'00100000 24'---011111----01-----1--0 -> 8'10000000 16'0000100100000000
+ transition: 8'00100000 24'---011111----11-----1--0 -> 8'01000000 16'0000100010000000
+ transition: 8'00100000 24'---011111-----------1--1 -> 8'01000000 16'0000100010000000
+ transition: 8'00100000 24'1--011111--------------- -> 8'01000000 16'0000100010000000
+ transition: 8'00100000 24'---011111---1----------- -> 8'00000001 16'0000100000000010
+ transition: 8'00100000 24'-1-011111--------------- -> 8'00001000 16'0000100000010000
+ transition: 8'00100000 24'---111111--------------- -> 8'01000000 16'0000100010000000
+ transition: 8'00001000 24'---00---0--------0------ -> 8'01000000 16'0000010010000000
+ transition: 8'00001000 24'---00---0--------1----0- -> 8'00001000 16'0000010000010000
+ transition: 8'00001000 24'---00---0--------1----1- -> 8'01000000 16'0000010010000000
+ transition: 8'00001000 24'---10---0--------------- -> 8'01000000 16'0000010010000000
+ transition: 8'00001000 24'---000-01--------0------ -> 8'01000000 16'0000010010000000
+ transition: 8'00001000 24'---000-01--------1----0- -> 8'00001000 16'0000010000010000
+ transition: 8'00001000 24'---000-01--------1----1- -> 8'01000000 16'0000010010000000
+ transition: 8'00001000 24'---100-01--------------- -> 8'01000000 16'0000010010000000
+ transition: 8'00001000 24'----00011--------------- -> 8'10000000 16'0000010100000000
+ transition: 8'00001000 24'---000111--------0------ -> 8'01000000 16'0000010010000000
+ transition: 8'00001000 24'---000111--------1----0- -> 8'00001000 16'0000010000010000
+ transition: 8'00001000 24'---000111--------1----1- -> 8'01000000 16'0000010010000000
+ transition: 8'00001000 24'---100111--------------- -> 8'01000000 16'0000010010000000
+ transition: 8'00001000 24'----010-1--------------- -> 8'10000000 16'0000010100000000
+ transition: 8'00001000 24'---001101--------0------ -> 8'01000000 16'0000010010000000
+ transition: 8'00001000 24'---001101--------1----0- -> 8'00001000 16'0000010000010000
+ transition: 8'00001000 24'---001101--------1----1- -> 8'01000000 16'0000010010000000
+ transition: 8'00001000 24'---101101--------------- -> 8'01000000 16'0000010010000000
+ transition: 8'00001000 24'---001111--------0------ -> 8'01000000 16'0000010010000000
+ transition: 8'00001000 24'---001111--------1----0- -> 8'00001000 16'0000010000010000
+ transition: 8'00001000 24'---001111--------1----1- -> 8'01000000 16'0000010010000000
+ transition: 8'00001000 24'---101111--------------- -> 8'01000000 16'0000010010000000
+ transition: 8'00001000 24'----1-0----------------- -> 8'10000000 16'0000010100000000
+ transition: 8'00001000 24'---01-1-0--------0------ -> 8'01000000 16'0000010010000000
+ transition: 8'00001000 24'---01-1-0--------1----0- -> 8'00001000 16'0000010000010000
+ transition: 8'00001000 24'---01-1-0--------1----1- -> 8'01000000 16'0000010010000000
+ transition: 8'00001000 24'---11-1-0--------------- -> 8'01000000 16'0000010010000000
+ transition: 8'00001000 24'---010101--------0------ -> 8'01000000 16'0000010010000000
+ transition: 8'00001000 24'---010101--------1----0- -> 8'00001000 16'0000010000010000
+ transition: 8'00001000 24'---010101--------1----1- -> 8'01000000 16'0000010010000000
+ transition: 8'00001000 24'---110101--------------- -> 8'01000000 16'0000010010000000
+ transition: 8'00001000 24'---010111--------0------ -> 8'01000000 16'0000010010000000
+ transition: 8'00001000 24'---010111--------1----0- -> 8'00001000 16'0000010000010000
+ transition: 8'00001000 24'---010111--------1----1- -> 8'01000000 16'0000010010000000
+ transition: 8'00001000 24'---110111--------------- -> 8'01000000 16'0000010010000000
+ transition: 8'00001000 24'---011101--------0------ -> 8'01000000 16'0000010010000000
+ transition: 8'00001000 24'---011101--------1----0- -> 8'00001000 16'0000010000010000
+ transition: 8'00001000 24'---011101--------1----1- -> 8'01000000 16'0000010010000000
+ transition: 8'00001000 24'---111101--------------- -> 8'01000000 16'0000010010000000
+ transition: 8'00001000 24'---011111--------0------ -> 8'01000000 16'0000010010000000
+ transition: 8'00001000 24'---011111--------1----0- -> 8'00001000 16'0000010000010000
+ transition: 8'00001000 24'---011111--------1----1- -> 8'01000000 16'0000010010000000
+ transition: 8'00001000 24'---111111--------------- -> 8'01000000 16'0000010010000000
+ transition: 8'00000010 24'---00---0-0------------- -> 8'00000010 16'1000000000000100
+ transition: 8'00000010 24'---00---001------------- -> 8'00000010 16'1000000000000100
+ transition: 8'00000010 24'---00---011------------- -> 8'01000000 16'1000000010000000
+ transition: 8'00000010 24'---10---0--------------- -> 8'01000000 16'1000000010000000
+ transition: 8'00000010 24'---000-01-0------------- -> 8'00000010 16'1000000000000100
+ transition: 8'00000010 24'---000-0101------------- -> 8'00000010 16'1000000000000100
+ transition: 8'00000010 24'---000-0111------------- -> 8'01000000 16'1000000010000000
+ transition: 8'00000010 24'---100-01--------------- -> 8'01000000 16'1000000010000000
+ transition: 8'00000010 24'----00011--------------- -> 8'10000000 16'1000000100000000
+ transition: 8'00000010 24'---000111-0------------- -> 8'00000010 16'1000000000000100
+ transition: 8'00000010 24'---00011101------------- -> 8'00000010 16'1000000000000100
+ transition: 8'00000010 24'---00011111------------- -> 8'01000000 16'1000000010000000
+ transition: 8'00000010 24'---100111--------------- -> 8'01000000 16'1000000010000000
+ transition: 8'00000010 24'----010-1--------------- -> 8'10000000 16'1000000100000000
+ transition: 8'00000010 24'---001101-0------------- -> 8'00000010 16'1000000000000100
+ transition: 8'00000010 24'---00110101------------- -> 8'00000010 16'1000000000000100
+ transition: 8'00000010 24'---00110111------------- -> 8'01000000 16'1000000010000000
+ transition: 8'00000010 24'---101101--------------- -> 8'01000000 16'1000000010000000
+ transition: 8'00000010 24'---001111-0------------- -> 8'00000010 16'1000000000000100
+ transition: 8'00000010 24'---00111101------------- -> 8'00000010 16'1000000000000100
+ transition: 8'00000010 24'---00111111------------- -> 8'01000000 16'1000000010000000
+ transition: 8'00000010 24'---101111--------------- -> 8'01000000 16'1000000010000000
+ transition: 8'00000010 24'----1-0----------------- -> 8'10000000 16'1000000100000000
+ transition: 8'00000010 24'---01-1-0-0------------- -> 8'00000010 16'1000000000000100
+ transition: 8'00000010 24'---01-1-001------------- -> 8'00000010 16'1000000000000100
+ transition: 8'00000010 24'---01-1-011------------- -> 8'01000000 16'1000000010000000
+ transition: 8'00000010 24'---11-1-0--------------- -> 8'01000000 16'1000000010000000
+ transition: 8'00000010 24'---010101-0------------- -> 8'00000010 16'1000000000000100
+ transition: 8'00000010 24'---01010101------------- -> 8'00000010 16'1000000000000100
+ transition: 8'00000010 24'---01010111------------- -> 8'01000000 16'1000000010000000
+ transition: 8'00000010 24'---110101--------------- -> 8'01000000 16'1000000010000000
+ transition: 8'00000010 24'---010111-0------------- -> 8'00000010 16'1000000000000100
+ transition: 8'00000010 24'---01011101------------- -> 8'00000010 16'1000000000000100
+ transition: 8'00000010 24'---01011111------------- -> 8'01000000 16'1000000010000000
+ transition: 8'00000010 24'---110111--------------- -> 8'01000000 16'1000000010000000
+ transition: 8'00000010 24'---011101-0------------- -> 8'00000010 16'1000000000000100
+ transition: 8'00000010 24'---01110101------------- -> 8'00000010 16'1000000000000100
+ transition: 8'00000010 24'---01110111------------- -> 8'01000000 16'1000000010000000
+ transition: 8'00000010 24'---111101--------------- -> 8'01000000 16'1000000010000000
+ transition: 8'00000010 24'---011111-0------------- -> 8'00000010 16'1000000000000100
+ transition: 8'00000010 24'---01111101------------- -> 8'00000010 16'1000000000000100
+ transition: 8'00000010 24'---01111111------------- -> 8'01000000 16'1000000010000000
+ transition: 8'00000010 24'---111111--------------- -> 8'01000000 16'1000000010000000
+ transition: 8'00000001 24'---00---0-0------------- -> 8'00000001 16'0001000000000010
+ transition: 8'00000001 24'---00---001------------- -> 8'00000001 16'0001000000000010
+ transition: 8'00000001 24'---00---011------------- -> 8'01000000 16'0001000010000000
+ transition: 8'00000001 24'---10---0--------------- -> 8'01000000 16'0001000010000000
+ transition: 8'00000001 24'---000-01-0------------- -> 8'00000001 16'0001000000000010
+ transition: 8'00000001 24'---000-0101------------- -> 8'00000001 16'0001000000000010
+ transition: 8'00000001 24'---000-0111------------- -> 8'01000000 16'0001000010000000
+ transition: 8'00000001 24'---100-01--------------- -> 8'01000000 16'0001000010000000
+ transition: 8'00000001 24'----00011--------------- -> 8'10000000 16'0001000100000000
+ transition: 8'00000001 24'---000111-0------------- -> 8'00000001 16'0001000000000010
+ transition: 8'00000001 24'---00011101------------- -> 8'00000001 16'0001000000000010
+ transition: 8'00000001 24'---00011111------------- -> 8'01000000 16'0001000010000000
+ transition: 8'00000001 24'---100111--------------- -> 8'01000000 16'0001000010000000
+ transition: 8'00000001 24'----010-1--------------- -> 8'10000000 16'0001000100000000
+ transition: 8'00000001 24'---001101-0------------- -> 8'00000001 16'0001000000000010
+ transition: 8'00000001 24'---00110101------------- -> 8'00000001 16'0001000000000010
+ transition: 8'00000001 24'---00110111------------- -> 8'01000000 16'0001000010000000
+ transition: 8'00000001 24'---101101--------------- -> 8'01000000 16'0001000010000000
+ transition: 8'00000001 24'---001111-0------------- -> 8'00000001 16'0001000000000010
+ transition: 8'00000001 24'---00111101------------- -> 8'00000001 16'0001000000000010
+ transition: 8'00000001 24'---00111111------------- -> 8'01000000 16'0001000010000000
+ transition: 8'00000001 24'---101111--------------- -> 8'01000000 16'0001000010000000
+ transition: 8'00000001 24'----1-0----------------- -> 8'10000000 16'0001000100000000
+ transition: 8'00000001 24'---01-1-0-0------------- -> 8'00000001 16'0001000000000010
+ transition: 8'00000001 24'---01-1-001------------- -> 8'00000001 16'0001000000000010
+ transition: 8'00000001 24'---01-1-011------------- -> 8'01000000 16'0001000010000000
+ transition: 8'00000001 24'---11-1-0--------------- -> 8'01000000 16'0001000010000000
+ transition: 8'00000001 24'---010101-0------------- -> 8'00000001 16'0001000000000010
+ transition: 8'00000001 24'---01010101------------- -> 8'00000001 16'0001000000000010
+ transition: 8'00000001 24'---01010111------------- -> 8'01000000 16'0001000010000000
+ transition: 8'00000001 24'---110101--------------- -> 8'01000000 16'0001000010000000
+ transition: 8'00000001 24'---010111-0------------- -> 8'00000001 16'0001000000000010
+ transition: 8'00000001 24'---01011101------------- -> 8'00000001 16'0001000000000010
+ transition: 8'00000001 24'---01011111------------- -> 8'01000000 16'0001000010000000
+ transition: 8'00000001 24'---110111--------------- -> 8'01000000 16'0001000010000000
+ transition: 8'00000001 24'---011101-0------------- -> 8'00000001 16'0001000000000010
+ transition: 8'00000001 24'---01110101------------- -> 8'00000001 16'0001000000000010
+ transition: 8'00000001 24'---01110111------------- -> 8'01000000 16'0001000010000000
+ transition: 8'00000001 24'---111101--------------- -> 8'01000000 16'0001000010000000
+ transition: 8'00000001 24'---011111-0------------- -> 8'00000001 16'0001000000000010
+ transition: 8'00000001 24'---01111101------------- -> 8'00000001 16'0001000000000010
+ transition: 8'00000001 24'---01111111------------- -> 8'01000000 16'0001000010000000
+ transition: 8'00000001 24'---111111--------------- -> 8'01000000 16'0001000010000000
+Extracting FSM `\softshell.cpus[1].core.cpu.picorv32_core.mem_wordsize' from module `\user_proj_example'.
+ found $dff cell for state register: $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procdff$16554
+ root of input selection tree: $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$0\mem_wordsize[1:0]
+ found ctrl input: \softshell.cpus[1].core.cpu.wb_rst_i
+ found ctrl input: $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10034_CMP
+ found ctrl input: $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10223_CMP
+ found ctrl input: $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$eq$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1308$3962_Y
+ found ctrl input: $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$logic_or$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1852$4121_Y
+ found ctrl input: \softshell.cpus[1].core.cpu.picorv32_core.mem_do_rdata
+ found ctrl input: \softshell.cpus[1].core.cpu.picorv32_core.instr_lw
+ found ctrl input: $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$logic_or$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1882$4130_Y
+ found ctrl input: $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$logic_or$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1881$4129_Y
+ found state code: 2'00
+ found state code: 2'01
+ found state code: 2'10
+ found ctrl input: \softshell.cpus[1].core.cpu.picorv32_core.mem_do_wdata
+ found ctrl input: \softshell.cpus[1].core.cpu.picorv32_core.instr_sw
+ found ctrl input: \softshell.cpus[1].core.cpu.picorv32_core.instr_sh
+ found ctrl input: \softshell.cpus[1].core.cpu.picorv32_core.instr_sb
+ found ctrl output: $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$eq$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1918$4141_Y
+ found ctrl output: $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$eq$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1925$4148_Y
+ found ctrl output: $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$11985_CMP
+ ctrl inputs: { \softshell.cpus[1].core.cpu.wb_rst_i $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10223_CMP $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10034_CMP $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$logic_or$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1882$4130_Y $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$logic_or$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1881$4129_Y $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$logic_or$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1852$4121_Y $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$eq$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1308$3962_Y \softshell.cpus[1].core.cpu.picorv32_core.instr_sw \softshell.cpus[1].core.cpu.picorv32_core.instr_sh \softshell.cpus[1].core.cpu.picorv32_core.instr_sb \softshell.cpus[1].core.cpu.picorv32_core.instr_lw \softshell.cpus[1].core.cpu.picorv32_core.mem_do_wdata \softshell.cpus[1].core.cpu.picorv32_core.mem_do_rdata }
+ ctrl outputs: { $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$11985_CMP $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$eq$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1925$4148_Y $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$eq$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1918$4141_Y $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$0\mem_wordsize[1:0] }
+ transition: 2'00 13'000---0------ -> 2'00 5'00100
+ transition: 2'00 13'0-----1------ -> 2'00 5'00100
+ transition: 2'00 13'01---0------- -> 2'00 5'00100
+ transition: 2'00 13'01---1-000-0- -> INVALID_STATE(2'xx) 5'001xx <ignored invalid transition!>
+ transition: 2'00 13'01---1---1-0- -> 2'10 5'00110
+ transition: 2'00 13'01---1--1--0- -> 2'01 5'00101
+ transition: 2'00 13'01---1-1---0- -> 2'00 5'00100
+ transition: 2'00 13'01---1-----1- -> 2'00 5'00100
+ transition: 2'00 13'0-1--0------- -> 2'00 5'00100
+ transition: 2'00 13'0-1001----0-0 -> INVALID_STATE(2'xx) 5'001xx <ignored invalid transition!>
+ transition: 2'00 13'0-1-11------0 -> 2'10 5'00110
+ transition: 2'00 13'0-11-1------0 -> 2'01 5'00101
+ transition: 2'00 13'0-1--1----1-0 -> 2'00 5'00100
+ transition: 2'00 13'0-1--1------1 -> 2'00 5'00100
+ transition: 2'00 13'1------------ -> 2'00 5'00100
+ transition: 2'10 13'000---0------ -> 2'10 5'10010
+ transition: 2'10 13'0-----1------ -> 2'00 5'10000
+ transition: 2'10 13'01---0------- -> 2'10 5'10010
+ transition: 2'10 13'01---1-000-0- -> INVALID_STATE(2'xx) 5'100xx <ignored invalid transition!>
+ transition: 2'10 13'01---1---1-0- -> 2'10 5'10010
+ transition: 2'10 13'01---1--1--0- -> 2'01 5'10001
+ transition: 2'10 13'01---1-1---0- -> 2'00 5'10000
+ transition: 2'10 13'01---1-----1- -> 2'10 5'10010
+ transition: 2'10 13'0-1--0------- -> 2'10 5'10010
+ transition: 2'10 13'0-1001----0-0 -> INVALID_STATE(2'xx) 5'100xx <ignored invalid transition!>
+ transition: 2'10 13'0-1-11------0 -> 2'10 5'10010
+ transition: 2'10 13'0-11-1------0 -> 2'01 5'10001
+ transition: 2'10 13'0-1--1----1-0 -> 2'00 5'10000
+ transition: 2'10 13'0-1--1------1 -> 2'10 5'10010
+ transition: 2'10 13'1------------ -> 2'10 5'10010
+ transition: 2'01 13'000---0------ -> 2'01 5'01001
+ transition: 2'01 13'0-----1------ -> 2'00 5'01000
+ transition: 2'01 13'01---0------- -> 2'01 5'01001
+ transition: 2'01 13'01---1-000-0- -> INVALID_STATE(2'xx) 5'010xx <ignored invalid transition!>
+ transition: 2'01 13'01---1---1-0- -> 2'10 5'01010
+ transition: 2'01 13'01---1--1--0- -> 2'01 5'01001
+ transition: 2'01 13'01---1-1---0- -> 2'00 5'01000
+ transition: 2'01 13'01---1-----1- -> 2'01 5'01001
+ transition: 2'01 13'0-1--0------- -> 2'01 5'01001
+ transition: 2'01 13'0-1001----0-0 -> INVALID_STATE(2'xx) 5'010xx <ignored invalid transition!>
+ transition: 2'01 13'0-1-11------0 -> 2'10 5'01010
+ transition: 2'01 13'0-11-1------0 -> 2'01 5'01001
+ transition: 2'01 13'0-1--1----1-0 -> 2'00 5'01000
+ transition: 2'01 13'0-1--1------1 -> 2'01 5'01001
+ transition: 2'01 13'1------------ -> 2'01 5'01001
+Extracting FSM `\softshell.cpus[1].core.cpu.state' from module `\user_proj_example'.
+ found $dff cell for state register: $flatten\softshell.\cpus[1].core.\cpu.$procdff$16297
+ root of input selection tree: $flatten\softshell.\cpus[1].core.\cpu.$0\state[1:0]
+ found reset state: 2'00 (guessed from mux tree)
+ found ctrl input: \softshell.cpus[1].core.cpu.wb_rst_i
+ found ctrl input: $flatten\softshell.\cpus[1].core.\cpu.$procmux$5208_CMP
+ found ctrl input: $flatten\softshell.\cpus[1].core.\cpu.$procmux$5221_CMP
+ found state code: 2'00
+ found ctrl input: \softshell.cpus[1].core.cpu.wbm_ack_i
+ found state code: 2'10
+ found ctrl input: \softshell.cpus[1].core.cpu.picorv32_core.mem_valid
+ found state code: 2'01
+ found ctrl output: $flatten\softshell.\cpus[1].core.\cpu.$procmux$5221_CMP
+ found ctrl output: $flatten\softshell.\cpus[1].core.\cpu.$procmux$5214_CMP
+ found ctrl output: $flatten\softshell.\cpus[1].core.\cpu.$procmux$5208_CMP
+ ctrl inputs: { \softshell.cpus[1].core.cpu.wb_rst_i \softshell.cpus[1].core.cpu.wbm_ack_i \softshell.cpus[1].core.cpu.picorv32_core.mem_valid }
+ ctrl outputs: { $flatten\softshell.\cpus[1].core.\cpu.$0\state[1:0] $flatten\softshell.\cpus[1].core.\cpu.$procmux$5208_CMP $flatten\softshell.\cpus[1].core.\cpu.$procmux$5214_CMP $flatten\softshell.\cpus[1].core.\cpu.$procmux$5221_CMP }
+ transition: 2'00 3'0-0 -> 2'00 5'00001
+ transition: 2'00 3'0-1 -> 2'01 5'01001
+ transition: 2'00 3'1-- -> 2'00 5'00001
+ transition: 2'10 3'0-- -> 2'00 5'00010
+ transition: 2'10 3'1-- -> 2'00 5'00010
+ transition: 2'01 3'00- -> 2'01 5'01100
+ transition: 2'01 3'01- -> 2'10 5'10100
+ transition: 2'01 3'1-- -> 2'00 5'00100
+Extracting FSM `\softshell.cpus[2].core.cpu.picorv32_core.cpu_state' from module `\user_proj_example'.
+ found $dff cell for state register: $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procdff$16719
+ root of input selection tree: $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$0\cpu_state[7:0]
+ found ctrl input: $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1933$3474_Y
+ found ctrl input: $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1917$3457_Y
+ found ctrl input: \softshell.cpus[2].core.cpu.wb_rst_i
+ found ctrl input: $auto$opt_reduce.cc:134:opt_mux$17203
+ found ctrl input: $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$12085_CMP
+ found ctrl input: $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$12086_CMP
+ found ctrl input: $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$12087_CMP
+ found ctrl input: $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$12088_CMP
+ found ctrl input: $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$eq$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1308$3279_Y
+ found ctrl input: $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$logic_or$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1852$3438_Y
+ found ctrl input: $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1867$3442_Y
+ found state code: 8'01000000
+ found ctrl input: $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$eq$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1826$3420_Y
+ found ctrl input: \softshell.cpus[2].core.cpu.picorv32_core.is_beq_bne_blt_bge_bltu_bgeu
+ found ctrl input: \softshell.cpus[2].core.cpu.picorv32_core.mem_done
+ found ctrl input: \softshell.cpus[2].core.cpu.picorv32_core.is_sb_sh_sw
+ found ctrl input: \softshell.cpus[2].core.cpu.picorv32_core.instr_trap
+ found state code: 8'00001000
+ found state code: 8'00000010
+ found ctrl input: \softshell.cpus[2].core.flexio.pcpi_ready
+ found ctrl input: $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1600$3374_Y
+ found ctrl input: $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1603$3378_Y
+ found state code: 8'10000000
+ found ctrl input: $auto$opt_reduce.cc:134:opt_mux$17073
+ found ctrl input: $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1691$3392_Y
+ found ctrl input: $auto$opt_reduce.cc:134:opt_mux$17071
+ found state code: 8'00000001
+ found ctrl input: $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1533$3353_Y
+ found ctrl input: $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1543$3361_Y
+ found ctrl input: \softshell.cpus[2].core.cpu.picorv32_core.decoder_trigger
+ found ctrl input: \softshell.cpus[2].core.cpu.picorv32_core.instr_jal
+ found state code: 8'00100000
+ found ctrl input: $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1925$3467_Y
+ found ctrl input: $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1918$3460_Y
+ found ctrl input: $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1920$3464_Y
+ found ctrl output: $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$eq$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1308$3279_Y
+ found ctrl output: $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$12083_CMP
+ found ctrl output: $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$12084_CMP
+ found ctrl output: $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$12085_CMP
+ found ctrl output: $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$12086_CMP
+ found ctrl output: $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$12087_CMP
+ found ctrl output: $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$12088_CMP
+ found ctrl output: $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$12090_CMP
+ ctrl inputs: { $auto$opt_reduce.cc:134:opt_mux$17203 $auto$opt_reduce.cc:134:opt_mux$17071 $auto$opt_reduce.cc:134:opt_mux$17073 \softshell.cpus[2].core.cpu.wb_rst_i $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1933$3474_Y $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1925$3467_Y $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1920$3464_Y $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1918$3460_Y $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1917$3457_Y $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1867$3442_Y $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$logic_or$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1852$3438_Y $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$eq$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1826$3420_Y $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1691$3392_Y $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1603$3378_Y $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1600$3374_Y $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1543$3361_Y $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1533$3353_Y \softshell.cpus[2].core.cpu.picorv32_core.is_beq_bne_blt_bge_bltu_bgeu \softshell.cpus[2].core.cpu.picorv32_core.is_sb_sh_sw \softshell.cpus[2].core.cpu.picorv32_core.decoder_trigger \softshell.cpus[2].core.cpu.picorv32_core.instr_trap \softshell.cpus[2].core.cpu.picorv32_core.instr_jal \softshell.cpus[2].core.cpu.picorv32_core.mem_done \softshell.cpus[2].core.flexio.pcpi_ready }
+ ctrl outputs: { $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$12090_CMP $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$12088_CMP $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$12087_CMP $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$12086_CMP $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$12085_CMP $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$12084_CMP $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$12083_CMP $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$0\cpu_state[7:0] $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$eq$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1308$3279_Y }
+ transition: 8'10000000 24'---00---0--------------- -> 8'10000000 16'1000000100000000
+ transition: 8'10000000 24'---10---0--------------- -> 8'01000000 16'1000000010000000
+ transition: 8'10000000 24'---000-01--------------- -> 8'10000000 16'1000000100000000
+ transition: 8'10000000 24'---100-01--------------- -> 8'01000000 16'1000000010000000
+ transition: 8'10000000 24'----00011--------------- -> 8'10000000 16'1000000100000000
+ transition: 8'10000000 24'---000111--------------- -> 8'10000000 16'1000000100000000
+ transition: 8'10000000 24'---100111--------------- -> 8'01000000 16'1000000010000000
+ transition: 8'10000000 24'----010-1--------------- -> 8'10000000 16'1000000100000000
+ transition: 8'10000000 24'---001101--------------- -> 8'10000000 16'1000000100000000
+ transition: 8'10000000 24'---101101--------------- -> 8'01000000 16'1000000010000000
+ transition: 8'10000000 24'---001111--------------- -> 8'10000000 16'1000000100000000
+ transition: 8'10000000 24'---101111--------------- -> 8'01000000 16'1000000010000000
+ transition: 8'10000000 24'----1-0----------------- -> 8'10000000 16'1000000100000000
+ transition: 8'10000000 24'---01-1-0--------------- -> 8'10000000 16'1000000100000000
+ transition: 8'10000000 24'---11-1-0--------------- -> 8'01000000 16'1000000010000000
+ transition: 8'10000000 24'---010101--------------- -> 8'10000000 16'1000000100000000
+ transition: 8'10000000 24'---110101--------------- -> 8'01000000 16'1000000010000000
+ transition: 8'10000000 24'---010111--------------- -> 8'10000000 16'1000000100000000
+ transition: 8'10000000 24'---110111--------------- -> 8'01000000 16'1000000010000000
+ transition: 8'10000000 24'---011101--------------- -> 8'10000000 16'1000000100000000
+ transition: 8'10000000 24'---111101--------------- -> 8'01000000 16'1000000010000000
+ transition: 8'10000000 24'---011111--------------- -> 8'10000000 16'1000000100000000
+ transition: 8'10000000 24'---111111--------------- -> 8'01000000 16'1000000010000000
+ transition: 8'01000000 24'---00---0------00--0---- -> 8'01000000 16'0000000010000001
+ transition: 8'01000000 24'---00---0------00--1-0-- -> 8'00100000 16'0000000001000001
+ transition: 8'01000000 24'---00---0------00--1-1-- -> 8'01000000 16'0000000010000001
+ transition: 8'01000000 24'---00---0------10------- -> 8'01000000 16'0000000010000001
+ transition: 8'01000000 24'---00---0-------1------- -> 8'01000000 16'0000000010000001
+ transition: 8'01000000 24'---10---0--------------- -> 8'01000000 16'0000000010000001
+ transition: 8'01000000 24'---000-01------00--0---- -> 8'01000000 16'0000000010000001
+ transition: 8'01000000 24'---000-01------00--1-0-- -> 8'00100000 16'0000000001000001
+ transition: 8'01000000 24'---000-01------00--1-1-- -> 8'01000000 16'0000000010000001
+ transition: 8'01000000 24'---000-01------10------- -> 8'01000000 16'0000000010000001
+ transition: 8'01000000 24'---000-01-------1------- -> 8'01000000 16'0000000010000001
+ transition: 8'01000000 24'---100-01--------------- -> 8'01000000 16'0000000010000001
+ transition: 8'01000000 24'----00011--------------- -> 8'10000000 16'0000000100000001
+ transition: 8'01000000 24'---000111------00--0---- -> 8'01000000 16'0000000010000001
+ transition: 8'01000000 24'---000111------00--1-0-- -> 8'00100000 16'0000000001000001
+ transition: 8'01000000 24'---000111------00--1-1-- -> 8'01000000 16'0000000010000001
+ transition: 8'01000000 24'---000111------10------- -> 8'01000000 16'0000000010000001
+ transition: 8'01000000 24'---000111-------1------- -> 8'01000000 16'0000000010000001
+ transition: 8'01000000 24'---100111--------------- -> 8'01000000 16'0000000010000001
+ transition: 8'01000000 24'----010-1--------------- -> 8'10000000 16'0000000100000001
+ transition: 8'01000000 24'---001101------00--0---- -> 8'01000000 16'0000000010000001
+ transition: 8'01000000 24'---001101------00--1-0-- -> 8'00100000 16'0000000001000001
+ transition: 8'01000000 24'---001101------00--1-1-- -> 8'01000000 16'0000000010000001
+ transition: 8'01000000 24'---001101------10------- -> 8'01000000 16'0000000010000001
+ transition: 8'01000000 24'---001101-------1------- -> 8'01000000 16'0000000010000001
+ transition: 8'01000000 24'---101101--------------- -> 8'01000000 16'0000000010000001
+ transition: 8'01000000 24'---001111------00--0---- -> 8'01000000 16'0000000010000001
+ transition: 8'01000000 24'---001111------00--1-0-- -> 8'00100000 16'0000000001000001
+ transition: 8'01000000 24'---001111------00--1-1-- -> 8'01000000 16'0000000010000001
+ transition: 8'01000000 24'---001111------10------- -> 8'01000000 16'0000000010000001
+ transition: 8'01000000 24'---001111-------1------- -> 8'01000000 16'0000000010000001
+ transition: 8'01000000 24'---101111--------------- -> 8'01000000 16'0000000010000001
+ transition: 8'01000000 24'----1-0----------------- -> 8'10000000 16'0000000100000001
+ transition: 8'01000000 24'---01-1-0------00--0---- -> 8'01000000 16'0000000010000001
+ transition: 8'01000000 24'---01-1-0------00--1-0-- -> 8'00100000 16'0000000001000001
+ transition: 8'01000000 24'---01-1-0------00--1-1-- -> 8'01000000 16'0000000010000001
+ transition: 8'01000000 24'---01-1-0------10------- -> 8'01000000 16'0000000010000001
+ transition: 8'01000000 24'---01-1-0-------1------- -> 8'01000000 16'0000000010000001
+ transition: 8'01000000 24'---11-1-0--------------- -> 8'01000000 16'0000000010000001
+ transition: 8'01000000 24'---010101------00--0---- -> 8'01000000 16'0000000010000001
+ transition: 8'01000000 24'---010101------00--1-0-- -> 8'00100000 16'0000000001000001
+ transition: 8'01000000 24'---010101------00--1-1-- -> 8'01000000 16'0000000010000001
+ transition: 8'01000000 24'---010101------10------- -> 8'01000000 16'0000000010000001
+ transition: 8'01000000 24'---010101-------1------- -> 8'01000000 16'0000000010000001
+ transition: 8'01000000 24'---110101--------------- -> 8'01000000 16'0000000010000001
+ transition: 8'01000000 24'---010111------00--0---- -> 8'01000000 16'0000000010000001
+ transition: 8'01000000 24'---010111------00--1-0-- -> 8'00100000 16'0000000001000001
+ transition: 8'01000000 24'---010111------00--1-1-- -> 8'01000000 16'0000000010000001
+ transition: 8'01000000 24'---010111------10------- -> 8'01000000 16'0000000010000001
+ transition: 8'01000000 24'---010111-------1------- -> 8'01000000 16'0000000010000001
+ transition: 8'01000000 24'---110111--------------- -> 8'01000000 16'0000000010000001
+ transition: 8'01000000 24'---011101------00--0---- -> 8'01000000 16'0000000010000001
+ transition: 8'01000000 24'---011101------00--1-0-- -> 8'00100000 16'0000000001000001
+ transition: 8'01000000 24'---011101------00--1-1-- -> 8'01000000 16'0000000010000001
+ transition: 8'01000000 24'---011101------10------- -> 8'01000000 16'0000000010000001
+ transition: 8'01000000 24'---011101-------1------- -> 8'01000000 16'0000000010000001
+ transition: 8'01000000 24'---111101--------------- -> 8'01000000 16'0000000010000001
+ transition: 8'01000000 24'---011111------00--0---- -> 8'01000000 16'0000000010000001
+ transition: 8'01000000 24'---011111------00--1-0-- -> 8'00100000 16'0000000001000001
+ transition: 8'01000000 24'---011111------00--1-1-- -> 8'01000000 16'0000000010000001
+ transition: 8'01000000 24'---011111------10------- -> 8'01000000 16'0000000010000001
+ transition: 8'01000000 24'---011111-------1------- -> 8'01000000 16'0000000010000001
+ transition: 8'01000000 24'---111111--------------- -> 8'01000000 16'0000000010000001
+ transition: 8'00100000 24'-0000---0---0-----0-0--- -> 8'00001000 16'0100000000010000
+ transition: 8'00100000 24'-0000---0---0-----1----- -> 8'00000010 16'0100000000000100
+ transition: 8'00100000 24'---00---0-----0-----1--0 -> 8'00100000 16'0100000001000000
+ transition: 8'00100000 24'---00---0----01-----1--0 -> 8'10000000 16'0100000100000000
+ transition: 8'00100000 24'---00---0----11-----1--0 -> 8'01000000 16'0100000010000000
+ transition: 8'00100000 24'---00---0-----------1--1 -> 8'01000000 16'0100000010000000
+ transition: 8'00100000 24'-1-00---0--------------- -> 8'01000000 16'0100000010000000
+ transition: 8'00100000 24'---00---0---1----------- -> 8'00000001 16'0100000000000010
+ transition: 8'00100000 24'--100---0--------------- -> 8'00001000 16'0100000000010000
+ transition: 8'00100000 24'---10---0--------------- -> 8'01000000 16'0100000010000000
+ transition: 8'00100000 24'-00000-01---0-----0-0--- -> 8'00001000 16'0100000000010000
+ transition: 8'00100000 24'-00000-01---0-----1----- -> 8'00000010 16'0100000000000100
+ transition: 8'00100000 24'---000-01-----0-----1--0 -> 8'00100000 16'0100000001000000
+ transition: 8'00100000 24'---000-01----01-----1--0 -> 8'10000000 16'0100000100000000
+ transition: 8'00100000 24'---000-01----11-----1--0 -> 8'01000000 16'0100000010000000
+ transition: 8'00100000 24'---000-01-----------1--1 -> 8'01000000 16'0100000010000000
+ transition: 8'00100000 24'-1-000-01--------------- -> 8'01000000 16'0100000010000000
+ transition: 8'00100000 24'---000-01---1----------- -> 8'00000001 16'0100000000000010
+ transition: 8'00100000 24'--1000-01--------------- -> 8'00001000 16'0100000000010000
+ transition: 8'00100000 24'---100-01--------------- -> 8'01000000 16'0100000010000000
+ transition: 8'00100000 24'----00011--------------- -> 8'10000000 16'0100000100000000
+ transition: 8'00100000 24'-00000111---0-----0-0--- -> 8'00001000 16'0100000000010000
+ transition: 8'00100000 24'-00000111---0-----1----- -> 8'00000010 16'0100000000000100
+ transition: 8'00100000 24'---000111-----0-----1--0 -> 8'00100000 16'0100000001000000
+ transition: 8'00100000 24'---000111----01-----1--0 -> 8'10000000 16'0100000100000000
+ transition: 8'00100000 24'---000111----11-----1--0 -> 8'01000000 16'0100000010000000
+ transition: 8'00100000 24'---000111-----------1--1 -> 8'01000000 16'0100000010000000
+ transition: 8'00100000 24'-1-000111--------------- -> 8'01000000 16'0100000010000000
+ transition: 8'00100000 24'---000111---1----------- -> 8'00000001 16'0100000000000010
+ transition: 8'00100000 24'--1000111--------------- -> 8'00001000 16'0100000000010000
+ transition: 8'00100000 24'---100111--------------- -> 8'01000000 16'0100000010000000
+ transition: 8'00100000 24'----010-1--------------- -> 8'10000000 16'0100000100000000
+ transition: 8'00100000 24'-00001101---0-----0-0--- -> 8'00001000 16'0100000000010000
+ transition: 8'00100000 24'-00001101---0-----1----- -> 8'00000010 16'0100000000000100
+ transition: 8'00100000 24'---001101-----0-----1--0 -> 8'00100000 16'0100000001000000
+ transition: 8'00100000 24'---001101----01-----1--0 -> 8'10000000 16'0100000100000000
+ transition: 8'00100000 24'---001101----11-----1--0 -> 8'01000000 16'0100000010000000
+ transition: 8'00100000 24'---001101-----------1--1 -> 8'01000000 16'0100000010000000
+ transition: 8'00100000 24'-1-001101--------------- -> 8'01000000 16'0100000010000000
+ transition: 8'00100000 24'---001101---1----------- -> 8'00000001 16'0100000000000010
+ transition: 8'00100000 24'--1001101--------------- -> 8'00001000 16'0100000000010000
+ transition: 8'00100000 24'---101101--------------- -> 8'01000000 16'0100000010000000
+ transition: 8'00100000 24'-00001111---0-----0-0--- -> 8'00001000 16'0100000000010000
+ transition: 8'00100000 24'-00001111---0-----1----- -> 8'00000010 16'0100000000000100
+ transition: 8'00100000 24'---001111-----0-----1--0 -> 8'00100000 16'0100000001000000
+ transition: 8'00100000 24'---001111----01-----1--0 -> 8'10000000 16'0100000100000000
+ transition: 8'00100000 24'---001111----11-----1--0 -> 8'01000000 16'0100000010000000
+ transition: 8'00100000 24'---001111-----------1--1 -> 8'01000000 16'0100000010000000
+ transition: 8'00100000 24'-1-001111--------------- -> 8'01000000 16'0100000010000000
+ transition: 8'00100000 24'---001111---1----------- -> 8'00000001 16'0100000000000010
+ transition: 8'00100000 24'--1001111--------------- -> 8'00001000 16'0100000000010000
+ transition: 8'00100000 24'---101111--------------- -> 8'01000000 16'0100000010000000
+ transition: 8'00100000 24'----1-0----------------- -> 8'10000000 16'0100000100000000
+ transition: 8'00100000 24'-0001-1-0---0-----0-0--- -> 8'00001000 16'0100000000010000
+ transition: 8'00100000 24'-0001-1-0---0-----1----- -> 8'00000010 16'0100000000000100
+ transition: 8'00100000 24'---01-1-0-----0-----1--0 -> 8'00100000 16'0100000001000000
+ transition: 8'00100000 24'---01-1-0----01-----1--0 -> 8'10000000 16'0100000100000000
+ transition: 8'00100000 24'---01-1-0----11-----1--0 -> 8'01000000 16'0100000010000000
+ transition: 8'00100000 24'---01-1-0-----------1--1 -> 8'01000000 16'0100000010000000
+ transition: 8'00100000 24'-1-01-1-0--------------- -> 8'01000000 16'0100000010000000
+ transition: 8'00100000 24'---01-1-0---1----------- -> 8'00000001 16'0100000000000010
+ transition: 8'00100000 24'--101-1-0--------------- -> 8'00001000 16'0100000000010000
+ transition: 8'00100000 24'---11-1-0--------------- -> 8'01000000 16'0100000010000000
+ transition: 8'00100000 24'-00010101---0-----0-0--- -> 8'00001000 16'0100000000010000
+ transition: 8'00100000 24'-00010101---0-----1----- -> 8'00000010 16'0100000000000100
+ transition: 8'00100000 24'---010101-----0-----1--0 -> 8'00100000 16'0100000001000000
+ transition: 8'00100000 24'---010101----01-----1--0 -> 8'10000000 16'0100000100000000
+ transition: 8'00100000 24'---010101----11-----1--0 -> 8'01000000 16'0100000010000000
+ transition: 8'00100000 24'---010101-----------1--1 -> 8'01000000 16'0100000010000000
+ transition: 8'00100000 24'-1-010101--------------- -> 8'01000000 16'0100000010000000
+ transition: 8'00100000 24'---010101---1----------- -> 8'00000001 16'0100000000000010
+ transition: 8'00100000 24'--1010101--------------- -> 8'00001000 16'0100000000010000
+ transition: 8'00100000 24'---110101--------------- -> 8'01000000 16'0100000010000000
+ transition: 8'00100000 24'-00010111---0-----0-0--- -> 8'00001000 16'0100000000010000
+ transition: 8'00100000 24'-00010111---0-----1----- -> 8'00000010 16'0100000000000100
+ transition: 8'00100000 24'---010111-----0-----1--0 -> 8'00100000 16'0100000001000000
+ transition: 8'00100000 24'---010111----01-----1--0 -> 8'10000000 16'0100000100000000
+ transition: 8'00100000 24'---010111----11-----1--0 -> 8'01000000 16'0100000010000000
+ transition: 8'00100000 24'---010111-----------1--1 -> 8'01000000 16'0100000010000000
+ transition: 8'00100000 24'-1-010111--------------- -> 8'01000000 16'0100000010000000
+ transition: 8'00100000 24'---010111---1----------- -> 8'00000001 16'0100000000000010
+ transition: 8'00100000 24'--1010111--------------- -> 8'00001000 16'0100000000010000
+ transition: 8'00100000 24'---110111--------------- -> 8'01000000 16'0100000010000000
+ transition: 8'00100000 24'-00011101---0-----0-0--- -> 8'00001000 16'0100000000010000
+ transition: 8'00100000 24'-00011101---0-----1----- -> 8'00000010 16'0100000000000100
+ transition: 8'00100000 24'---011101-----0-----1--0 -> 8'00100000 16'0100000001000000
+ transition: 8'00100000 24'---011101----01-----1--0 -> 8'10000000 16'0100000100000000
+ transition: 8'00100000 24'---011101----11-----1--0 -> 8'01000000 16'0100000010000000
+ transition: 8'00100000 24'---011101-----------1--1 -> 8'01000000 16'0100000010000000
+ transition: 8'00100000 24'-1-011101--------------- -> 8'01000000 16'0100000010000000
+ transition: 8'00100000 24'---011101---1----------- -> 8'00000001 16'0100000000000010
+ transition: 8'00100000 24'--1011101--------------- -> 8'00001000 16'0100000000010000
+ transition: 8'00100000 24'---111101--------------- -> 8'01000000 16'0100000010000000
+ transition: 8'00100000 24'-00011111---0-----0-0--- -> 8'00001000 16'0100000000010000
+ transition: 8'00100000 24'-00011111---0-----1----- -> 8'00000010 16'0100000000000100
+ transition: 8'00100000 24'---011111-----0-----1--0 -> 8'00100000 16'0100000001000000
+ transition: 8'00100000 24'---011111----01-----1--0 -> 8'10000000 16'0100000100000000
+ transition: 8'00100000 24'---011111----11-----1--0 -> 8'01000000 16'0100000010000000
+ transition: 8'00100000 24'---011111-----------1--1 -> 8'01000000 16'0100000010000000
+ transition: 8'00100000 24'-1-011111--------------- -> 8'01000000 16'0100000010000000
+ transition: 8'00100000 24'---011111---1----------- -> 8'00000001 16'0100000000000010
+ transition: 8'00100000 24'--1011111--------------- -> 8'00001000 16'0100000000010000
+ transition: 8'00100000 24'---111111--------------- -> 8'01000000 16'0100000010000000
+ transition: 8'00001000 24'---00---0--------0------ -> 8'01000000 16'0001000010000000
+ transition: 8'00001000 24'---00---0--------1----0- -> 8'00001000 16'0001000000010000
+ transition: 8'00001000 24'---00---0--------1----1- -> 8'01000000 16'0001000010000000
+ transition: 8'00001000 24'---10---0--------------- -> 8'01000000 16'0001000010000000
+ transition: 8'00001000 24'---000-01--------0------ -> 8'01000000 16'0001000010000000
+ transition: 8'00001000 24'---000-01--------1----0- -> 8'00001000 16'0001000000010000
+ transition: 8'00001000 24'---000-01--------1----1- -> 8'01000000 16'0001000010000000
+ transition: 8'00001000 24'---100-01--------------- -> 8'01000000 16'0001000010000000
+ transition: 8'00001000 24'----00011--------------- -> 8'10000000 16'0001000100000000
+ transition: 8'00001000 24'---000111--------0------ -> 8'01000000 16'0001000010000000
+ transition: 8'00001000 24'---000111--------1----0- -> 8'00001000 16'0001000000010000
+ transition: 8'00001000 24'---000111--------1----1- -> 8'01000000 16'0001000010000000
+ transition: 8'00001000 24'---100111--------------- -> 8'01000000 16'0001000010000000
+ transition: 8'00001000 24'----010-1--------------- -> 8'10000000 16'0001000100000000
+ transition: 8'00001000 24'---001101--------0------ -> 8'01000000 16'0001000010000000
+ transition: 8'00001000 24'---001101--------1----0- -> 8'00001000 16'0001000000010000
+ transition: 8'00001000 24'---001101--------1----1- -> 8'01000000 16'0001000010000000
+ transition: 8'00001000 24'---101101--------------- -> 8'01000000 16'0001000010000000
+ transition: 8'00001000 24'---001111--------0------ -> 8'01000000 16'0001000010000000
+ transition: 8'00001000 24'---001111--------1----0- -> 8'00001000 16'0001000000010000
+ transition: 8'00001000 24'---001111--------1----1- -> 8'01000000 16'0001000010000000
+ transition: 8'00001000 24'---101111--------------- -> 8'01000000 16'0001000010000000
+ transition: 8'00001000 24'----1-0----------------- -> 8'10000000 16'0001000100000000
+ transition: 8'00001000 24'---01-1-0--------0------ -> 8'01000000 16'0001000010000000
+ transition: 8'00001000 24'---01-1-0--------1----0- -> 8'00001000 16'0001000000010000
+ transition: 8'00001000 24'---01-1-0--------1----1- -> 8'01000000 16'0001000010000000
+ transition: 8'00001000 24'---11-1-0--------------- -> 8'01000000 16'0001000010000000
+ transition: 8'00001000 24'---010101--------0------ -> 8'01000000 16'0001000010000000
+ transition: 8'00001000 24'---010101--------1----0- -> 8'00001000 16'0001000000010000
+ transition: 8'00001000 24'---010101--------1----1- -> 8'01000000 16'0001000010000000
+ transition: 8'00001000 24'---110101--------------- -> 8'01000000 16'0001000010000000
+ transition: 8'00001000 24'---010111--------0------ -> 8'01000000 16'0001000010000000
+ transition: 8'00001000 24'---010111--------1----0- -> 8'00001000 16'0001000000010000
+ transition: 8'00001000 24'---010111--------1----1- -> 8'01000000 16'0001000010000000
+ transition: 8'00001000 24'---110111--------------- -> 8'01000000 16'0001000010000000
+ transition: 8'00001000 24'---011101--------0------ -> 8'01000000 16'0001000010000000
+ transition: 8'00001000 24'---011101--------1----0- -> 8'00001000 16'0001000000010000
+ transition: 8'00001000 24'---011101--------1----1- -> 8'01000000 16'0001000010000000
+ transition: 8'00001000 24'---111101--------------- -> 8'01000000 16'0001000010000000
+ transition: 8'00001000 24'---011111--------0------ -> 8'01000000 16'0001000010000000
+ transition: 8'00001000 24'---011111--------1----0- -> 8'00001000 16'0001000000010000
+ transition: 8'00001000 24'---011111--------1----1- -> 8'01000000 16'0001000010000000
+ transition: 8'00001000 24'---111111--------------- -> 8'01000000 16'0001000010000000
+ transition: 8'00000010 24'---00---0-0------------- -> 8'00000010 16'0000010000000100
+ transition: 8'00000010 24'---00---001------------- -> 8'00000010 16'0000010000000100
+ transition: 8'00000010 24'---00---011------------- -> 8'01000000 16'0000010010000000
+ transition: 8'00000010 24'---10---0--------------- -> 8'01000000 16'0000010010000000
+ transition: 8'00000010 24'---000-01-0------------- -> 8'00000010 16'0000010000000100
+ transition: 8'00000010 24'---000-0101------------- -> 8'00000010 16'0000010000000100
+ transition: 8'00000010 24'---000-0111------------- -> 8'01000000 16'0000010010000000
+ transition: 8'00000010 24'---100-01--------------- -> 8'01000000 16'0000010010000000
+ transition: 8'00000010 24'----00011--------------- -> 8'10000000 16'0000010100000000
+ transition: 8'00000010 24'---000111-0------------- -> 8'00000010 16'0000010000000100
+ transition: 8'00000010 24'---00011101------------- -> 8'00000010 16'0000010000000100
+ transition: 8'00000010 24'---00011111------------- -> 8'01000000 16'0000010010000000
+ transition: 8'00000010 24'---100111--------------- -> 8'01000000 16'0000010010000000
+ transition: 8'00000010 24'----010-1--------------- -> 8'10000000 16'0000010100000000
+ transition: 8'00000010 24'---001101-0------------- -> 8'00000010 16'0000010000000100
+ transition: 8'00000010 24'---00110101------------- -> 8'00000010 16'0000010000000100
+ transition: 8'00000010 24'---00110111------------- -> 8'01000000 16'0000010010000000
+ transition: 8'00000010 24'---101101--------------- -> 8'01000000 16'0000010010000000
+ transition: 8'00000010 24'---001111-0------------- -> 8'00000010 16'0000010000000100
+ transition: 8'00000010 24'---00111101------------- -> 8'00000010 16'0000010000000100
+ transition: 8'00000010 24'---00111111------------- -> 8'01000000 16'0000010010000000
+ transition: 8'00000010 24'---101111--------------- -> 8'01000000 16'0000010010000000
+ transition: 8'00000010 24'----1-0----------------- -> 8'10000000 16'0000010100000000
+ transition: 8'00000010 24'---01-1-0-0------------- -> 8'00000010 16'0000010000000100
+ transition: 8'00000010 24'---01-1-001------------- -> 8'00000010 16'0000010000000100
+ transition: 8'00000010 24'---01-1-011------------- -> 8'01000000 16'0000010010000000
+ transition: 8'00000010 24'---11-1-0--------------- -> 8'01000000 16'0000010010000000
+ transition: 8'00000010 24'---010101-0------------- -> 8'00000010 16'0000010000000100
+ transition: 8'00000010 24'---01010101------------- -> 8'00000010 16'0000010000000100
+ transition: 8'00000010 24'---01010111------------- -> 8'01000000 16'0000010010000000
+ transition: 8'00000010 24'---110101--------------- -> 8'01000000 16'0000010010000000
+ transition: 8'00000010 24'---010111-0------------- -> 8'00000010 16'0000010000000100
+ transition: 8'00000010 24'---01011101------------- -> 8'00000010 16'0000010000000100
+ transition: 8'00000010 24'---01011111------------- -> 8'01000000 16'0000010010000000
+ transition: 8'00000010 24'---110111--------------- -> 8'01000000 16'0000010010000000
+ transition: 8'00000010 24'---011101-0------------- -> 8'00000010 16'0000010000000100
+ transition: 8'00000010 24'---01110101------------- -> 8'00000010 16'0000010000000100
+ transition: 8'00000010 24'---01110111------------- -> 8'01000000 16'0000010010000000
+ transition: 8'00000010 24'---111101--------------- -> 8'01000000 16'0000010010000000
+ transition: 8'00000010 24'---011111-0------------- -> 8'00000010 16'0000010000000100
+ transition: 8'00000010 24'---01111101------------- -> 8'00000010 16'0000010000000100
+ transition: 8'00000010 24'---01111111------------- -> 8'01000000 16'0000010010000000
+ transition: 8'00000010 24'---111111--------------- -> 8'01000000 16'0000010010000000
+ transition: 8'00000001 24'---00---0-0------------- -> 8'00000001 16'0000001000000010
+ transition: 8'00000001 24'---00---001------------- -> 8'00000001 16'0000001000000010
+ transition: 8'00000001 24'---00---011------------- -> 8'01000000 16'0000001010000000
+ transition: 8'00000001 24'---10---0--------------- -> 8'01000000 16'0000001010000000
+ transition: 8'00000001 24'---000-01-0------------- -> 8'00000001 16'0000001000000010
+ transition: 8'00000001 24'---000-0101------------- -> 8'00000001 16'0000001000000010
+ transition: 8'00000001 24'---000-0111------------- -> 8'01000000 16'0000001010000000
+ transition: 8'00000001 24'---100-01--------------- -> 8'01000000 16'0000001010000000
+ transition: 8'00000001 24'----00011--------------- -> 8'10000000 16'0000001100000000
+ transition: 8'00000001 24'---000111-0------------- -> 8'00000001 16'0000001000000010
+ transition: 8'00000001 24'---00011101------------- -> 8'00000001 16'0000001000000010
+ transition: 8'00000001 24'---00011111------------- -> 8'01000000 16'0000001010000000
+ transition: 8'00000001 24'---100111--------------- -> 8'01000000 16'0000001010000000
+ transition: 8'00000001 24'----010-1--------------- -> 8'10000000 16'0000001100000000
+ transition: 8'00000001 24'---001101-0------------- -> 8'00000001 16'0000001000000010
+ transition: 8'00000001 24'---00110101------------- -> 8'00000001 16'0000001000000010
+ transition: 8'00000001 24'---00110111------------- -> 8'01000000 16'0000001010000000
+ transition: 8'00000001 24'---101101--------------- -> 8'01000000 16'0000001010000000
+ transition: 8'00000001 24'---001111-0------------- -> 8'00000001 16'0000001000000010
+ transition: 8'00000001 24'---00111101------------- -> 8'00000001 16'0000001000000010
+ transition: 8'00000001 24'---00111111------------- -> 8'01000000 16'0000001010000000
+ transition: 8'00000001 24'---101111--------------- -> 8'01000000 16'0000001010000000
+ transition: 8'00000001 24'----1-0----------------- -> 8'10000000 16'0000001100000000
+ transition: 8'00000001 24'---01-1-0-0------------- -> 8'00000001 16'0000001000000010
+ transition: 8'00000001 24'---01-1-001------------- -> 8'00000001 16'0000001000000010
+ transition: 8'00000001 24'---01-1-011------------- -> 8'01000000 16'0000001010000000
+ transition: 8'00000001 24'---11-1-0--------------- -> 8'01000000 16'0000001010000000
+ transition: 8'00000001 24'---010101-0------------- -> 8'00000001 16'0000001000000010
+ transition: 8'00000001 24'---01010101------------- -> 8'00000001 16'0000001000000010
+ transition: 8'00000001 24'---01010111------------- -> 8'01000000 16'0000001010000000
+ transition: 8'00000001 24'---110101--------------- -> 8'01000000 16'0000001010000000
+ transition: 8'00000001 24'---010111-0------------- -> 8'00000001 16'0000001000000010
+ transition: 8'00000001 24'---01011101------------- -> 8'00000001 16'0000001000000010
+ transition: 8'00000001 24'---01011111------------- -> 8'01000000 16'0000001010000000
+ transition: 8'00000001 24'---110111--------------- -> 8'01000000 16'0000001010000000
+ transition: 8'00000001 24'---011101-0------------- -> 8'00000001 16'0000001000000010
+ transition: 8'00000001 24'---01110101------------- -> 8'00000001 16'0000001000000010
+ transition: 8'00000001 24'---01110111------------- -> 8'01000000 16'0000001010000000
+ transition: 8'00000001 24'---111101--------------- -> 8'01000000 16'0000001010000000
+ transition: 8'00000001 24'---011111-0------------- -> 8'00000001 16'0000001000000010
+ transition: 8'00000001 24'---01111101------------- -> 8'00000001 16'0000001000000010
+ transition: 8'00000001 24'---01111111------------- -> 8'01000000 16'0000001010000000
+ transition: 8'00000001 24'---111111--------------- -> 8'01000000 16'0000001010000000
+Extracting FSM `\softshell.cpus[2].core.cpu.picorv32_core.mem_wordsize' from module `\user_proj_example'.
+ found $dff cell for state register: $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procdff$16706
+ root of input selection tree: $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$0\mem_wordsize[1:0]
+ found ctrl input: \softshell.cpus[2].core.cpu.wb_rst_i
+ found ctrl input: $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$12083_CMP
+ found ctrl input: $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$12084_CMP
+ found ctrl input: $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$eq$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1308$3279_Y
+ found ctrl input: $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$logic_or$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1852$3438_Y
+ found ctrl input: \softshell.cpus[2].core.cpu.picorv32_core.mem_do_rdata
+ found ctrl input: \softshell.cpus[2].core.cpu.picorv32_core.instr_lw
+ found ctrl input: $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$logic_or$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1882$3447_Y
+ found ctrl input: $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$logic_or$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1881$3446_Y
+ found state code: 2'00
+ found state code: 2'01
+ found state code: 2'10
+ found ctrl input: \softshell.cpus[2].core.cpu.picorv32_core.mem_do_wdata
+ found ctrl input: \softshell.cpus[2].core.cpu.picorv32_core.instr_sw
+ found ctrl input: \softshell.cpus[2].core.cpu.picorv32_core.instr_sh
+ found ctrl input: \softshell.cpus[2].core.cpu.picorv32_core.instr_sb
+ found ctrl output: $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$eq$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1918$3458_Y
+ found ctrl output: $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$eq$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1925$3465_Y
+ found ctrl output: $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$14850_CMP
+ ctrl inputs: { \softshell.cpus[2].core.cpu.wb_rst_i $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$12084_CMP $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$12083_CMP $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$logic_or$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1882$3447_Y $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$logic_or$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1881$3446_Y $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$logic_or$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1852$3438_Y $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$eq$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1308$3279_Y \softshell.cpus[2].core.cpu.picorv32_core.instr_sw \softshell.cpus[2].core.cpu.picorv32_core.instr_sh \softshell.cpus[2].core.cpu.picorv32_core.instr_sb \softshell.cpus[2].core.cpu.picorv32_core.instr_lw \softshell.cpus[2].core.cpu.picorv32_core.mem_do_wdata \softshell.cpus[2].core.cpu.picorv32_core.mem_do_rdata }
+ ctrl outputs: { $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$14850_CMP $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$eq$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1925$3465_Y $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$eq$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1918$3458_Y $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$0\mem_wordsize[1:0] }
+ transition: 2'00 13'000---0------ -> 2'00 5'00100
+ transition: 2'00 13'0-----1------ -> 2'00 5'00100
+ transition: 2'00 13'01---0------- -> 2'00 5'00100
+ transition: 2'00 13'01---1-000-0- -> INVALID_STATE(2'xx) 5'001xx <ignored invalid transition!>
+ transition: 2'00 13'01---1---1-0- -> 2'10 5'00110
+ transition: 2'00 13'01---1--1--0- -> 2'01 5'00101
+ transition: 2'00 13'01---1-1---0- -> 2'00 5'00100
+ transition: 2'00 13'01---1-----1- -> 2'00 5'00100
+ transition: 2'00 13'0-1--0------- -> 2'00 5'00100
+ transition: 2'00 13'0-1001----0-0 -> INVALID_STATE(2'xx) 5'001xx <ignored invalid transition!>
+ transition: 2'00 13'0-1-11------0 -> 2'10 5'00110
+ transition: 2'00 13'0-11-1------0 -> 2'01 5'00101
+ transition: 2'00 13'0-1--1----1-0 -> 2'00 5'00100
+ transition: 2'00 13'0-1--1------1 -> 2'00 5'00100
+ transition: 2'00 13'1------------ -> 2'00 5'00100
+ transition: 2'10 13'000---0------ -> 2'10 5'10010
+ transition: 2'10 13'0-----1------ -> 2'00 5'10000
+ transition: 2'10 13'01---0------- -> 2'10 5'10010
+ transition: 2'10 13'01---1-000-0- -> INVALID_STATE(2'xx) 5'100xx <ignored invalid transition!>
+ transition: 2'10 13'01---1---1-0- -> 2'10 5'10010
+ transition: 2'10 13'01---1--1--0- -> 2'01 5'10001
+ transition: 2'10 13'01---1-1---0- -> 2'00 5'10000
+ transition: 2'10 13'01---1-----1- -> 2'10 5'10010
+ transition: 2'10 13'0-1--0------- -> 2'10 5'10010
+ transition: 2'10 13'0-1001----0-0 -> INVALID_STATE(2'xx) 5'100xx <ignored invalid transition!>
+ transition: 2'10 13'0-1-11------0 -> 2'10 5'10010
+ transition: 2'10 13'0-11-1------0 -> 2'01 5'10001
+ transition: 2'10 13'0-1--1----1-0 -> 2'00 5'10000
+ transition: 2'10 13'0-1--1------1 -> 2'10 5'10010
+ transition: 2'10 13'1------------ -> 2'10 5'10010
+ transition: 2'01 13'000---0------ -> 2'01 5'01001
+ transition: 2'01 13'0-----1------ -> 2'00 5'01000
+ transition: 2'01 13'01---0------- -> 2'01 5'01001
+ transition: 2'01 13'01---1-000-0- -> INVALID_STATE(2'xx) 5'010xx <ignored invalid transition!>
+ transition: 2'01 13'01---1---1-0- -> 2'10 5'01010
+ transition: 2'01 13'01---1--1--0- -> 2'01 5'01001
+ transition: 2'01 13'01---1-1---0- -> 2'00 5'01000
+ transition: 2'01 13'01---1-----1- -> 2'01 5'01001
+ transition: 2'01 13'0-1--0------- -> 2'01 5'01001
+ transition: 2'01 13'0-1001----0-0 -> INVALID_STATE(2'xx) 5'010xx <ignored invalid transition!>
+ transition: 2'01 13'0-1-11------0 -> 2'10 5'01010
+ transition: 2'01 13'0-11-1------0 -> 2'01 5'01001
+ transition: 2'01 13'0-1--1----1-0 -> 2'00 5'01000
+ transition: 2'01 13'0-1--1------1 -> 2'01 5'01001
+ transition: 2'01 13'1------------ -> 2'01 5'01001
+Extracting FSM `\softshell.cpus[2].core.cpu.state' from module `\user_proj_example'.
+ found $dff cell for state register: $flatten\softshell.\cpus[2].core.\cpu.$procdff$16306
+ root of input selection tree: $flatten\softshell.\cpus[2].core.\cpu.$0\state[1:0]
+ found reset state: 2'00 (guessed from mux tree)
+ found ctrl input: \softshell.cpus[2].core.cpu.wb_rst_i
+ found ctrl input: $flatten\softshell.\cpus[2].core.\cpu.$procmux$5315_CMP
+ found ctrl input: $flatten\softshell.\cpus[2].core.\cpu.$procmux$5328_CMP
+ found state code: 2'00
+ found ctrl input: \softshell.cpus[2].core.cpu.wbm_ack_i
+ found state code: 2'10
+ found ctrl input: \softshell.cpus[2].core.cpu.picorv32_core.mem_valid
+ found state code: 2'01
+ found ctrl output: $flatten\softshell.\cpus[2].core.\cpu.$procmux$5328_CMP
+ found ctrl output: $flatten\softshell.\cpus[2].core.\cpu.$procmux$5321_CMP
+ found ctrl output: $flatten\softshell.\cpus[2].core.\cpu.$procmux$5315_CMP
+ ctrl inputs: { \softshell.cpus[2].core.cpu.wb_rst_i \softshell.cpus[2].core.cpu.wbm_ack_i \softshell.cpus[2].core.cpu.picorv32_core.mem_valid }
+ ctrl outputs: { $flatten\softshell.\cpus[2].core.\cpu.$0\state[1:0] $flatten\softshell.\cpus[2].core.\cpu.$procmux$5315_CMP $flatten\softshell.\cpus[2].core.\cpu.$procmux$5321_CMP $flatten\softshell.\cpus[2].core.\cpu.$procmux$5328_CMP }
+ transition: 2'00 3'0-0 -> 2'00 5'00001
+ transition: 2'00 3'0-1 -> 2'01 5'01001
+ transition: 2'00 3'1-- -> 2'00 5'00001
+ transition: 2'10 3'0-- -> 2'00 5'00010
+ transition: 2'10 3'1-- -> 2'00 5'00010
+ transition: 2'01 3'00- -> 2'01 5'01100
+ transition: 2'01 3'01- -> 2'10 5'10100
+ transition: 2'01 3'1-- -> 2'00 5'00100
+Extracting FSM `\softshell.flash.spimemio.state' from module `\user_proj_example'.
+ found $dff cell for state register: $flatten\softshell.\flash.\spimemio.$procdff$16510
+ root of input selection tree: $flatten\softshell.\flash.\spimemio.$0\state[3:0]
+ found reset state: 4'0000 (guessed from mux tree)
+ found ctrl input: $flatten\softshell.\flash.\spimemio.$logic_or$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/spimemio.v:373$696_Y
+ found ctrl input: \softshell.flash.spimemio.jump
+ found ctrl input: $flatten\softshell.\flash.\spimemio.$procmux$8764_CMP
+ found ctrl input: $flatten\softshell.\flash.\spimemio.$procmux$8767_CMP
+ found ctrl input: $flatten\softshell.\flash.\spimemio.$procmux$8770_CMP
+ found ctrl input: $flatten\softshell.\flash.\spimemio.$procmux$8773_CMP
+ found ctrl input: $flatten\softshell.\flash.\spimemio.$procmux$8776_CMP
+ found ctrl input: $flatten\softshell.\flash.\spimemio.$procmux$8779_CMP
+ found ctrl input: $flatten\softshell.\flash.\spimemio.$procmux$8782_CMP
+ found ctrl input: $flatten\softshell.\flash.\spimemio.$procmux$8787_CMP
+ found ctrl input: $flatten\softshell.\flash.\spimemio.$procmux$8790_CMP
+ found ctrl input: $flatten\softshell.\flash.\spimemio.$procmux$8750_CMP
+ found ctrl input: $flatten\softshell.\flash.\spimemio.$procmux$8796_CMP
+ found ctrl input: $flatten\softshell.\flash.\spimemio.$procmux$8753_CMP
+ found ctrl input: $flatten\softshell.\flash.\spimemio.$procmux$8802_CMP
+ found ctrl input: $flatten\softshell.\flash.\spimemio.$logic_or$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/spimemio.v:512$714_Y
+ found ctrl input: \softshell.flash.spimemio.xfer.din_ready
+ found state code: 4'1001
+ found state code: 4'1100
+ found state code: 4'1011
+ found state code: 4'1010
+ found ctrl input: $flatten\softshell.\flash.\spimemio.$logic_or$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/spimemio.v:472$710_Y
+ found state code: 4'1000
+ found state code: 4'0111
+ found ctrl input: $flatten\softshell.\flash.\spimemio.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/spimemio.v:216$617_Y
+ found state code: 4'0110
+ found state code: 4'0101
+ found ctrl input: \softshell.flash.spimemio.dout_valid
+ found state code: 4'0100
+ found state code: 4'0011
+ found state code: 4'0010
+ found state code: 4'0001
+ found ctrl input: \softshell.flash.spimemio.config_cont
+ found state code: 4'0000
+ found ctrl output: $flatten\softshell.\flash.\spimemio.$procmux$8802_CMP
+ found ctrl output: $flatten\softshell.\flash.\spimemio.$procmux$8796_CMP
+ found ctrl output: $flatten\softshell.\flash.\spimemio.$procmux$8790_CMP
+ found ctrl output: $flatten\softshell.\flash.\spimemio.$procmux$8787_CMP
+ found ctrl output: $flatten\softshell.\flash.\spimemio.$procmux$8782_CMP
+ found ctrl output: $flatten\softshell.\flash.\spimemio.$procmux$8779_CMP
+ found ctrl output: $flatten\softshell.\flash.\spimemio.$procmux$8776_CMP
+ found ctrl output: $flatten\softshell.\flash.\spimemio.$procmux$8773_CMP
+ found ctrl output: $flatten\softshell.\flash.\spimemio.$procmux$8770_CMP
+ found ctrl output: $flatten\softshell.\flash.\spimemio.$procmux$8767_CMP
+ found ctrl output: $flatten\softshell.\flash.\spimemio.$procmux$8764_CMP
+ found ctrl output: $flatten\softshell.\flash.\spimemio.$procmux$8753_CMP
+ found ctrl output: $flatten\softshell.\flash.\spimemio.$procmux$8750_CMP
+ ctrl inputs: { \softshell.flash.spimemio.dout_valid \softshell.flash.spimemio.jump \softshell.flash.spimemio.config_cont $flatten\softshell.\flash.\spimemio.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/spimemio.v:216$617_Y $flatten\softshell.\flash.\spimemio.$logic_or$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/spimemio.v:373$696_Y $flatten\softshell.\flash.\spimemio.$logic_or$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/spimemio.v:472$710_Y $flatten\softshell.\flash.\spimemio.$logic_or$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/spimemio.v:512$714_Y \softshell.flash.spimemio.xfer.din_ready }
+ ctrl outputs: { $flatten\softshell.\flash.\spimemio.$0\state[3:0] $flatten\softshell.\flash.\spimemio.$procmux$8750_CMP $flatten\softshell.\flash.\spimemio.$procmux$8753_CMP $flatten\softshell.\flash.\spimemio.$procmux$8764_CMP $flatten\softshell.\flash.\spimemio.$procmux$8767_CMP $flatten\softshell.\flash.\spimemio.$procmux$8770_CMP $flatten\softshell.\flash.\spimemio.$procmux$8773_CMP $flatten\softshell.\flash.\spimemio.$procmux$8776_CMP $flatten\softshell.\flash.\spimemio.$procmux$8779_CMP $flatten\softshell.\flash.\spimemio.$procmux$8782_CMP $flatten\softshell.\flash.\spimemio.$procmux$8787_CMP $flatten\softshell.\flash.\spimemio.$procmux$8790_CMP $flatten\softshell.\flash.\spimemio.$procmux$8796_CMP $flatten\softshell.\flash.\spimemio.$procmux$8802_CMP }
+ transition: 4'0000 8'-0--0--0 -> 4'0000 17'00000000000000001
+ transition: 4'0000 8'-0--0--1 -> 4'0001 17'00010000000000001
+ transition: 4'0000 8'-10-0--- -> 4'0100 17'01000000000000001
+ transition: 4'0000 8'-11-0--- -> 4'0101 17'01010000000000001
+ transition: 4'0000 8'----1--- -> 4'0000 17'00000000000000001
+ transition: 4'1000 8'-0--0--0 -> 4'1000 17'10000000001000000
+ transition: 4'1000 8'-0--0--1 -> 4'1001 17'10010000001000000
+ transition: 4'1000 8'-10-0--- -> 4'0100 17'01000000001000000
+ transition: 4'1000 8'-11-0--- -> 4'0101 17'01010000001000000
+ transition: 4'1000 8'----1--- -> 4'0000 17'00000000001000000
+ transition: 4'0100 8'-0--0--0 -> 4'0100 17'01000000000000100
+ transition: 4'0100 8'-0--0--1 -> 4'0101 17'01010000000000100
+ transition: 4'0100 8'-10-0--- -> 4'0100 17'01000000000000100
+ transition: 4'0100 8'-11-0--- -> 4'0101 17'01010000000000100
+ transition: 4'0100 8'----1--- -> 4'0000 17'00000000000000100
+ transition: 4'1100 8'-0--0-0- -> 4'1100 17'11000010000000000
+ transition: 4'1100 8'-0--0-10 -> 4'1100 17'11000010000000000
+ transition: 4'1100 8'-0--0-11 -> 4'1001 17'10010010000000000
+ transition: 4'1100 8'-10-0--- -> 4'0100 17'01000010000000000
+ transition: 4'1100 8'-11-0--- -> 4'0101 17'01010010000000000
+ transition: 4'1100 8'----1--- -> 4'0000 17'00000010000000000
+ transition: 4'0010 8'-0--0--0 -> 4'0010 17'00100000000000010
+ transition: 4'0010 8'-0--0--1 -> 4'0011 17'00110000000000010
+ transition: 4'0010 8'-10-0--- -> 4'0100 17'01000000000000010
+ transition: 4'0010 8'-11-0--- -> 4'0101 17'01010000000000010
+ transition: 4'0010 8'----1--- -> 4'0000 17'00000000000000010
+ transition: 4'1010 8'-0--0--0 -> 4'1010 17'10100000100000000
+ transition: 4'1010 8'-0--0--1 -> 4'1011 17'10110000100000000
+ transition: 4'1010 8'-10-0--- -> 4'0100 17'01000000100000000
+ transition: 4'1010 8'-11-0--- -> 4'0101 17'01010000100000000
+ transition: 4'1010 8'----1--- -> 4'0000 17'00000000100000000
+ transition: 4'0110 8'-0--0--0 -> 4'0110 17'01100000000010000
+ transition: 4'0110 8'-0--0--1 -> 4'0111 17'01110000000010000
+ transition: 4'0110 8'-10-0--- -> 4'0100 17'01000000000010000
+ transition: 4'0110 8'-11-0--- -> 4'0101 17'01010000000010000
+ transition: 4'0110 8'----1--- -> 4'0000 17'00000000000010000
+ transition: 4'0001 8'00--0--- -> 4'0001 17'00010100000000000
+ transition: 4'0001 8'10--0--- -> 4'0010 17'00100100000000000
+ transition: 4'0001 8'-10-0--- -> 4'0100 17'01000100000000000
+ transition: 4'0001 8'-11-0--- -> 4'0101 17'01010100000000000
+ transition: 4'0001 8'----1--- -> 4'0000 17'00000100000000000
+ transition: 4'1001 8'-0--0--0 -> 4'1001 17'10010000010000000
+ transition: 4'1001 8'-0--0--1 -> 4'1010 17'10100000010000000
+ transition: 4'1001 8'-10-0--- -> 4'0100 17'01000000010000000
+ transition: 4'1001 8'-11-0--- -> 4'0101 17'01010000010000000
+ transition: 4'1001 8'----1--- -> 4'0000 17'00000000010000000
+ transition: 4'0101 8'-0-00--- -> 4'0101 17'01010000000001000
+ transition: 4'0101 8'-0-10--0 -> 4'0101 17'01010000000001000
+ transition: 4'0101 8'-0-10--1 -> 4'0110 17'01100000000001000
+ transition: 4'0101 8'-10-0--- -> 4'0100 17'01000000000001000
+ transition: 4'0101 8'-11-0--- -> 4'0101 17'01010000000001000
+ transition: 4'0101 8'----1--- -> 4'0000 17'00000000000001000
+ transition: 4'0011 8'00--0--- -> 4'0011 17'00111000000000000
+ transition: 4'0011 8'10--0--- -> 4'0100 17'01001000000000000
+ transition: 4'0011 8'-10-0--- -> 4'0100 17'01001000000000000
+ transition: 4'0011 8'-11-0--- -> 4'0101 17'01011000000000000
+ transition: 4'0011 8'----1--- -> 4'0000 17'00001000000000000
+ transition: 4'1011 8'-0--0--0 -> 4'1011 17'10110001000000000
+ transition: 4'1011 8'-0--0--1 -> 4'1100 17'11000001000000000
+ transition: 4'1011 8'-10-0--- -> 4'0100 17'01000001000000000
+ transition: 4'1011 8'-11-0--- -> 4'0101 17'01010001000000000
+ transition: 4'1011 8'----1--- -> 4'0000 17'00000001000000000
+ transition: 4'0111 8'-0--0--0 -> 4'0111 17'01110000000100000
+ transition: 4'0111 8'-0--00-1 -> 4'1001 17'10010000000100000
+ transition: 4'0111 8'-0--01-1 -> 4'1000 17'10000000000100000
+ transition: 4'0111 8'-10-0--- -> 4'0100 17'01000000000100000
+ transition: 4'0111 8'-11-0--- -> 4'0101 17'01010000000100000
+ transition: 4'0111 8'----1--- -> 4'0000 17'00000000000100000
+
+23.8.3. Executing FSM_OPT pass (simple optimizations of FSMs).
+Optimizing FSM `$fsm$\softshell.flash.spimemio.state$17278' from module `\user_proj_example'.
+Optimizing FSM `$fsm$\softshell.cpus[2].core.cpu.state$17273' from module `\user_proj_example'.
+ Merging pattern 3'0-- and 3'1-- from group (1 0 5'00010).
+ Merging pattern 3'1-- and 3'0-- from group (1 0 5'00010).
+Optimizing FSM `$fsm$\softshell.cpus[2].core.cpu.picorv32_core.mem_wordsize$17268' from module `\user_proj_example'.
+Optimizing FSM `$fsm$\softshell.cpus[2].core.cpu.picorv32_core.cpu_state$17258' from module `\user_proj_example'.
+ Merging pattern 24'---010101--------------- and 24'---010111--------------- from group (0 0 16'1000000100000000).
+ Merging pattern 24'---001101--------------- and 24'---001111--------------- from group (0 0 16'1000000100000000).
+ Merging pattern 24'---011101--------------- and 24'---011111--------------- from group (0 0 16'1000000100000000).
+ Merging pattern 24'---010111--------------- and 24'---010101--------------- from group (0 0 16'1000000100000000).
+ Merging pattern 24'---001111--------------- and 24'---001101--------------- from group (0 0 16'1000000100000000).
+ Merging pattern 24'---011111--------------- and 24'---011101--------------- from group (0 0 16'1000000100000000).
+ Merging pattern 24'---0101-1--------------- and 24'---0111-1--------------- from group (0 0 16'1000000100000000).
+ Merging pattern 24'---0111-1--------------- and 24'---0101-1--------------- from group (0 0 16'1000000100000000).
+ Merging pattern 24'---01-1-0--------------- and 24'---01-1-1--------------- from group (0 0 16'1000000100000000).
+ Merging pattern 24'---01-1-1--------------- and 24'---01-1-0--------------- from group (0 0 16'1000000100000000).
+ Merging pattern 24'---110101--------------- and 24'---110111--------------- from group (0 1 16'1000000010000000).
+ Merging pattern 24'---101101--------------- and 24'---101111--------------- from group (0 1 16'1000000010000000).
+ Merging pattern 24'---111101--------------- and 24'---111111--------------- from group (0 1 16'1000000010000000).
+ Merging pattern 24'---110111--------------- and 24'---110101--------------- from group (0 1 16'1000000010000000).
+ Merging pattern 24'---101111--------------- and 24'---101101--------------- from group (0 1 16'1000000010000000).
+ Merging pattern 24'---111111--------------- and 24'---111101--------------- from group (0 1 16'1000000010000000).
+ Merging pattern 24'---1101-1--------------- and 24'---1111-1--------------- from group (0 1 16'1000000010000000).
+ Merging pattern 24'---1111-1--------------- and 24'---1101-1--------------- from group (0 1 16'1000000010000000).
+ Merging pattern 24'---11-1-0--------------- and 24'---11-1-1--------------- from group (0 1 16'1000000010000000).
+ Merging pattern 24'---11-1-1--------------- and 24'---11-1-0--------------- from group (0 1 16'1000000010000000).
+ Merging pattern 24'---010101------00--1-1-- and 24'---010111------00--1-1-- from group (1 1 16'0000000010000001).
+ Merging pattern 24'---001101------00--1-1-- and 24'---001111------00--1-1-- from group (1 1 16'0000000010000001).
+ Merging pattern 24'---011101------00--1-1-- and 24'---011111------00--1-1-- from group (1 1 16'0000000010000001).
+ Merging pattern 24'---010111------00--1-1-- and 24'---010101------00--1-1-- from group (1 1 16'0000000010000001).
+ Merging pattern 24'---001111------00--1-1-- and 24'---001101------00--1-1-- from group (1 1 16'0000000010000001).
+ Merging pattern 24'---011111------00--1-1-- and 24'---011101------00--1-1-- from group (1 1 16'0000000010000001).
+ Merging pattern 24'---010101------00--0---- and 24'---010111------00--0---- from group (1 1 16'0000000010000001).
+ Merging pattern 24'---001101------00--0---- and 24'---001111------00--0---- from group (1 1 16'0000000010000001).
+ Merging pattern 24'---011101------00--0---- and 24'---011111------00--0---- from group (1 1 16'0000000010000001).
+ Merging pattern 24'---010111------00--0---- and 24'---010101------00--0---- from group (1 1 16'0000000010000001).
+ Merging pattern 24'---001111------00--0---- and 24'---001101------00--0---- from group (1 1 16'0000000010000001).
+ Merging pattern 24'---011111------00--0---- and 24'---011101------00--0---- from group (1 1 16'0000000010000001).
+ Merging pattern 24'---010101------10------- and 24'---010111------10------- from group (1 1 16'0000000010000001).
+ Merging pattern 24'---001101------10------- and 24'---001111------10------- from group (1 1 16'0000000010000001).
+ Merging pattern 24'---011101------10------- and 24'---011111------10------- from group (1 1 16'0000000010000001).
+ Merging pattern 24'---010111------10------- and 24'---010101------10------- from group (1 1 16'0000000010000001).
+ Merging pattern 24'---001111------10------- and 24'---001101------10------- from group (1 1 16'0000000010000001).
+ Merging pattern 24'---011111------10------- and 24'---011101------10------- from group (1 1 16'0000000010000001).
+ Merging pattern 24'---010101-------1------- and 24'---010111-------1------- from group (1 1 16'0000000010000001).
+ Merging pattern 24'---001101-------1------- and 24'---001111-------1------- from group (1 1 16'0000000010000001).
+ Merging pattern 24'---011101-------1------- and 24'---011111-------1------- from group (1 1 16'0000000010000001).
+ Merging pattern 24'---010111-------1------- and 24'---010101-------1------- from group (1 1 16'0000000010000001).
+ Merging pattern 24'---001111-------1------- and 24'---001101-------1------- from group (1 1 16'0000000010000001).
+ Merging pattern 24'---011111-------1------- and 24'---011101-------1------- from group (1 1 16'0000000010000001).
+ Merging pattern 24'---110101--------------- and 24'---110111--------------- from group (1 1 16'0000000010000001).
+ Merging pattern 24'---101101--------------- and 24'---101111--------------- from group (1 1 16'0000000010000001).
+ Merging pattern 24'---111101--------------- and 24'---111111--------------- from group (1 1 16'0000000010000001).
+ Merging pattern 24'---110111--------------- and 24'---110101--------------- from group (1 1 16'0000000010000001).
+ Merging pattern 24'---101111--------------- and 24'---101101--------------- from group (1 1 16'0000000010000001).
+ Merging pattern 24'---111111--------------- and 24'---111101--------------- from group (1 1 16'0000000010000001).
+ Merging pattern 24'---0101-1------00--1-1-- and 24'---0111-1------00--1-1-- from group (1 1 16'0000000010000001).
+ Merging pattern 24'---0111-1------00--1-1-- and 24'---0101-1------00--1-1-- from group (1 1 16'0000000010000001).
+ Merging pattern 24'---0101-1------00--0---- and 24'---0111-1------00--0---- from group (1 1 16'0000000010000001).
+ Merging pattern 24'---0111-1------00--0---- and 24'---0101-1------00--0---- from group (1 1 16'0000000010000001).
+ Merging pattern 24'---0101-1------10------- and 24'---0111-1------10------- from group (1 1 16'0000000010000001).
+ Merging pattern 24'---0111-1------10------- and 24'---0101-1------10------- from group (1 1 16'0000000010000001).
+ Merging pattern 24'---0101-1-------1------- and 24'---0111-1-------1------- from group (1 1 16'0000000010000001).
+ Merging pattern 24'---0111-1-------1------- and 24'---0101-1-------1------- from group (1 1 16'0000000010000001).
+ Merging pattern 24'---1101-1--------------- and 24'---1111-1--------------- from group (1 1 16'0000000010000001).
+ Merging pattern 24'---1111-1--------------- and 24'---1101-1--------------- from group (1 1 16'0000000010000001).
+ Merging pattern 24'---01-1-0------00--1-1-- and 24'---01-1-1------00--1-1-- from group (1 1 16'0000000010000001).
+ Merging pattern 24'---01-1-1------00--1-1-- and 24'---01-1-0------00--1-1-- from group (1 1 16'0000000010000001).
+ Merging pattern 24'---01-1-0------00--0---- and 24'---01-1-1------00--0---- from group (1 1 16'0000000010000001).
+ Merging pattern 24'---01-1-1------00--0---- and 24'---01-1-0------00--0---- from group (1 1 16'0000000010000001).
+ Merging pattern 24'---01-1-0------10------- and 24'---01-1-1------10------- from group (1 1 16'0000000010000001).
+ Merging pattern 24'---01-1-1------10------- and 24'---01-1-0------10------- from group (1 1 16'0000000010000001).
+ Merging pattern 24'---01-1-0-------1------- and 24'---01-1-1-------1------- from group (1 1 16'0000000010000001).
+ Merging pattern 24'---01-1-1-------1------- and 24'---01-1-0-------1------- from group (1 1 16'0000000010000001).
+ Merging pattern 24'---11-1-0--------------- and 24'---11-1-1--------------- from group (1 1 16'0000000010000001).
+ Merging pattern 24'---11-1-1--------------- and 24'---11-1-0--------------- from group (1 1 16'0000000010000001).
+ Merging pattern 24'---010101------00--1-0-- and 24'---010111------00--1-0-- from group (1 2 16'0000000001000001).
+ Merging pattern 24'---001101------00--1-0-- and 24'---001111------00--1-0-- from group (1 2 16'0000000001000001).
+ Merging pattern 24'---011101------00--1-0-- and 24'---011111------00--1-0-- from group (1 2 16'0000000001000001).
+ Merging pattern 24'---010111------00--1-0-- and 24'---010101------00--1-0-- from group (1 2 16'0000000001000001).
+ Merging pattern 24'---001111------00--1-0-- and 24'---001101------00--1-0-- from group (1 2 16'0000000001000001).
+ Merging pattern 24'---011111------00--1-0-- and 24'---011101------00--1-0-- from group (1 2 16'0000000001000001).
+ Merging pattern 24'---0101-1------00--1-0-- and 24'---0111-1------00--1-0-- from group (1 2 16'0000000001000001).
+ Merging pattern 24'---0111-1------00--1-0-- and 24'---0101-1------00--1-0-- from group (1 2 16'0000000001000001).
+ Merging pattern 24'---01-1-0------00--1-0-- and 24'---01-1-1------00--1-0-- from group (1 2 16'0000000001000001).
+ Merging pattern 24'---01-1-1------00--1-0-- and 24'---01-1-0------00--1-0-- from group (1 2 16'0000000001000001).
+ Merging pattern 24'---010101----01-----1--0 and 24'---010111----01-----1--0 from group (2 0 16'0100000100000000).
+ Merging pattern 24'---001101----01-----1--0 and 24'---001111----01-----1--0 from group (2 0 16'0100000100000000).
+ Merging pattern 24'---011101----01-----1--0 and 24'---011111----01-----1--0 from group (2 0 16'0100000100000000).
+ Merging pattern 24'---010111----01-----1--0 and 24'---010101----01-----1--0 from group (2 0 16'0100000100000000).
+ Merging pattern 24'---001111----01-----1--0 and 24'---001101----01-----1--0 from group (2 0 16'0100000100000000).
+ Merging pattern 24'---011111----01-----1--0 and 24'---011101----01-----1--0 from group (2 0 16'0100000100000000).
+ Merging pattern 24'---0101-1----01-----1--0 and 24'---0111-1----01-----1--0 from group (2 0 16'0100000100000000).
+ Merging pattern 24'---0111-1----01-----1--0 and 24'---0101-1----01-----1--0 from group (2 0 16'0100000100000000).
+ Merging pattern 24'---01-1-0----01-----1--0 and 24'---01-1-1----01-----1--0 from group (2 0 16'0100000100000000).
+ Merging pattern 24'---01-1-1----01-----1--0 and 24'---01-1-0----01-----1--0 from group (2 0 16'0100000100000000).
+ Merging pattern 24'---010101----11-----1--0 and 24'---010111----11-----1--0 from group (2 1 16'0100000010000000).
+ Merging pattern 24'---001101----11-----1--0 and 24'---001111----11-----1--0 from group (2 1 16'0100000010000000).
+ Merging pattern 24'---011101----11-----1--0 and 24'---011111----11-----1--0 from group (2 1 16'0100000010000000).
+ Merging pattern 24'---010111----11-----1--0 and 24'---010101----11-----1--0 from group (2 1 16'0100000010000000).
+ Merging pattern 24'---001111----11-----1--0 and 24'---001101----11-----1--0 from group (2 1 16'0100000010000000).
+ Merging pattern 24'---011111----11-----1--0 and 24'---011101----11-----1--0 from group (2 1 16'0100000010000000).
+ Merging pattern 24'---010101-----------1--1 and 24'---010111-----------1--1 from group (2 1 16'0100000010000000).
+ Merging pattern 24'---001101-----------1--1 and 24'---001111-----------1--1 from group (2 1 16'0100000010000000).
+ Merging pattern 24'---011101-----------1--1 and 24'---011111-----------1--1 from group (2 1 16'0100000010000000).
+ Merging pattern 24'---010111-----------1--1 and 24'---010101-----------1--1 from group (2 1 16'0100000010000000).
+ Merging pattern 24'---001111-----------1--1 and 24'---001101-----------1--1 from group (2 1 16'0100000010000000).
+ Merging pattern 24'---011111-----------1--1 and 24'---011101-----------1--1 from group (2 1 16'0100000010000000).
+ Merging pattern 24'-1-010101--------------- and 24'-1-010111--------------- from group (2 1 16'0100000010000000).
+ Merging pattern 24'---110101--------------- and 24'---110111--------------- from group (2 1 16'0100000010000000).
+ Merging pattern 24'-1-001101--------------- and 24'-1-001111--------------- from group (2 1 16'0100000010000000).
+ Merging pattern 24'---101101--------------- and 24'---101111--------------- from group (2 1 16'0100000010000000).
+ Merging pattern 24'-1-011101--------------- and 24'-1-011111--------------- from group (2 1 16'0100000010000000).
+ Merging pattern 24'---111101--------------- and 24'---111111--------------- from group (2 1 16'0100000010000000).
+ Merging pattern 24'-1-010111--------------- and 24'-1-010101--------------- from group (2 1 16'0100000010000000).
+ Merging pattern 24'---110111--------------- and 24'---110101--------------- from group (2 1 16'0100000010000000).
+ Merging pattern 24'-1-001111--------------- and 24'-1-001101--------------- from group (2 1 16'0100000010000000).
+ Merging pattern 24'---101111--------------- and 24'---101101--------------- from group (2 1 16'0100000010000000).
+ Merging pattern 24'-1-011111--------------- and 24'-1-011101--------------- from group (2 1 16'0100000010000000).
+ Merging pattern 24'---111111--------------- and 24'---111101--------------- from group (2 1 16'0100000010000000).
+ Merging pattern 24'---0101-1----11-----1--0 and 24'---0111-1----11-----1--0 from group (2 1 16'0100000010000000).
+ Merging pattern 24'---0111-1----11-----1--0 and 24'---0101-1----11-----1--0 from group (2 1 16'0100000010000000).
+ Merging pattern 24'---0101-1-----------1--1 and 24'---0111-1-----------1--1 from group (2 1 16'0100000010000000).
+ Merging pattern 24'---0111-1-----------1--1 and 24'---0101-1-----------1--1 from group (2 1 16'0100000010000000).
+ Merging pattern 24'-1-0101-1--------------- and 24'-1-0111-1--------------- from group (2 1 16'0100000010000000).
+ Merging pattern 24'---1101-1--------------- and 24'---1111-1--------------- from group (2 1 16'0100000010000000).
+ Merging pattern 24'-1-0111-1--------------- and 24'-1-0101-1--------------- from group (2 1 16'0100000010000000).
+ Merging pattern 24'---1111-1--------------- and 24'---1101-1--------------- from group (2 1 16'0100000010000000).
+ Merging pattern 24'---01-1-0----11-----1--0 and 24'---01-1-1----11-----1--0 from group (2 1 16'0100000010000000).
+ Merging pattern 24'---01-1-1----11-----1--0 and 24'---01-1-0----11-----1--0 from group (2 1 16'0100000010000000).
+ Merging pattern 24'---01-1-0-----------1--1 and 24'---01-1-1-----------1--1 from group (2 1 16'0100000010000000).
+ Merging pattern 24'---01-1-1-----------1--1 and 24'---01-1-0-----------1--1 from group (2 1 16'0100000010000000).
+ Merging pattern 24'-1-01-1-0--------------- and 24'-1-01-1-1--------------- from group (2 1 16'0100000010000000).
+ Merging pattern 24'---11-1-0--------------- and 24'---11-1-1--------------- from group (2 1 16'0100000010000000).
+ Merging pattern 24'-1-01-1-1--------------- and 24'-1-01-1-0--------------- from group (2 1 16'0100000010000000).
+ Merging pattern 24'---11-1-1--------------- and 24'---11-1-0--------------- from group (2 1 16'0100000010000000).
+ Merging pattern 24'---010101-----0-----1--0 and 24'---010111-----0-----1--0 from group (2 2 16'0100000001000000).
+ Merging pattern 24'---001101-----0-----1--0 and 24'---001111-----0-----1--0 from group (2 2 16'0100000001000000).
+ Merging pattern 24'---011101-----0-----1--0 and 24'---011111-----0-----1--0 from group (2 2 16'0100000001000000).
+ Merging pattern 24'---010111-----0-----1--0 and 24'---010101-----0-----1--0 from group (2 2 16'0100000001000000).
+ Merging pattern 24'---001111-----0-----1--0 and 24'---001101-----0-----1--0 from group (2 2 16'0100000001000000).
+ Merging pattern 24'---011111-----0-----1--0 and 24'---011101-----0-----1--0 from group (2 2 16'0100000001000000).
+ Merging pattern 24'---0101-1-----0-----1--0 and 24'---0111-1-----0-----1--0 from group (2 2 16'0100000001000000).
+ Merging pattern 24'---0111-1-----0-----1--0 and 24'---0101-1-----0-----1--0 from group (2 2 16'0100000001000000).
+ Merging pattern 24'---01-1-0-----0-----1--0 and 24'---01-1-1-----0-----1--0 from group (2 2 16'0100000001000000).
+ Merging pattern 24'---01-1-1-----0-----1--0 and 24'---01-1-0-----0-----1--0 from group (2 2 16'0100000001000000).
+ Merging pattern 24'-00010101---0-----0-0--- and 24'-00010111---0-----0-0--- from group (2 3 16'0100000000010000).
+ Merging pattern 24'-00001101---0-----0-0--- and 24'-00001111---0-----0-0--- from group (2 3 16'0100000000010000).
+ Merging pattern 24'-00011101---0-----0-0--- and 24'-00011111---0-----0-0--- from group (2 3 16'0100000000010000).
+ Merging pattern 24'-00010111---0-----0-0--- and 24'-00010101---0-----0-0--- from group (2 3 16'0100000000010000).
+ Merging pattern 24'-00001111---0-----0-0--- and 24'-00001101---0-----0-0--- from group (2 3 16'0100000000010000).
+ Merging pattern 24'-00011111---0-----0-0--- and 24'-00011101---0-----0-0--- from group (2 3 16'0100000000010000).
+ Merging pattern 24'--1010101--------------- and 24'--1010111--------------- from group (2 3 16'0100000000010000).
+ Merging pattern 24'--1001101--------------- and 24'--1001111--------------- from group (2 3 16'0100000000010000).
+ Merging pattern 24'--1011101--------------- and 24'--1011111--------------- from group (2 3 16'0100000000010000).
+ Merging pattern 24'--1010111--------------- and 24'--1010101--------------- from group (2 3 16'0100000000010000).
+ Merging pattern 24'--1001111--------------- and 24'--1001101--------------- from group (2 3 16'0100000000010000).
+ Merging pattern 24'--1011111--------------- and 24'--1011101--------------- from group (2 3 16'0100000000010000).
+ Merging pattern 24'-000101-1---0-----0-0--- and 24'-000111-1---0-----0-0--- from group (2 3 16'0100000000010000).
+ Merging pattern 24'-000111-1---0-----0-0--- and 24'-000101-1---0-----0-0--- from group (2 3 16'0100000000010000).
+ Merging pattern 24'--10101-1--------------- and 24'--10111-1--------------- from group (2 3 16'0100000000010000).
+ Merging pattern 24'--10111-1--------------- and 24'--10101-1--------------- from group (2 3 16'0100000000010000).
+ Merging pattern 24'-0001-1-0---0-----0-0--- and 24'-0001-1-1---0-----0-0--- from group (2 3 16'0100000000010000).
+ Merging pattern 24'-0001-1-1---0-----0-0--- and 24'-0001-1-0---0-----0-0--- from group (2 3 16'0100000000010000).
+ Merging pattern 24'--101-1-0--------------- and 24'--101-1-1--------------- from group (2 3 16'0100000000010000).
+ Merging pattern 24'--101-1-1--------------- and 24'--101-1-0--------------- from group (2 3 16'0100000000010000).
+ Merging pattern 24'-00010101---0-----1----- and 24'-00010111---0-----1----- from group (2 4 16'0100000000000100).
+ Merging pattern 24'-00001101---0-----1----- and 24'-00001111---0-----1----- from group (2 4 16'0100000000000100).
+ Merging pattern 24'-00011101---0-----1----- and 24'-00011111---0-----1----- from group (2 4 16'0100000000000100).
+ Merging pattern 24'-00010111---0-----1----- and 24'-00010101---0-----1----- from group (2 4 16'0100000000000100).
+ Merging pattern 24'-00001111---0-----1----- and 24'-00001101---0-----1----- from group (2 4 16'0100000000000100).
+ Merging pattern 24'-00011111---0-----1----- and 24'-00011101---0-----1----- from group (2 4 16'0100000000000100).
+ Merging pattern 24'-000101-1---0-----1----- and 24'-000111-1---0-----1----- from group (2 4 16'0100000000000100).
+ Merging pattern 24'-000111-1---0-----1----- and 24'-000101-1---0-----1----- from group (2 4 16'0100000000000100).
+ Merging pattern 24'-0001-1-0---0-----1----- and 24'-0001-1-1---0-----1----- from group (2 4 16'0100000000000100).
+ Merging pattern 24'-0001-1-1---0-----1----- and 24'-0001-1-0---0-----1----- from group (2 4 16'0100000000000100).
+ Merging pattern 24'---010101---1----------- and 24'---010111---1----------- from group (2 5 16'0100000000000010).
+ Merging pattern 24'---001101---1----------- and 24'---001111---1----------- from group (2 5 16'0100000000000010).
+ Merging pattern 24'---011101---1----------- and 24'---011111---1----------- from group (2 5 16'0100000000000010).
+ Merging pattern 24'---010111---1----------- and 24'---010101---1----------- from group (2 5 16'0100000000000010).
+ Merging pattern 24'---001111---1----------- and 24'---001101---1----------- from group (2 5 16'0100000000000010).
+ Merging pattern 24'---011111---1----------- and 24'---011101---1----------- from group (2 5 16'0100000000000010).
+ Merging pattern 24'---0101-1---1----------- and 24'---0111-1---1----------- from group (2 5 16'0100000000000010).
+ Merging pattern 24'---0111-1---1----------- and 24'---0101-1---1----------- from group (2 5 16'0100000000000010).
+ Merging pattern 24'---01-1-0---1----------- and 24'---01-1-1---1----------- from group (2 5 16'0100000000000010).
+ Merging pattern 24'---01-1-1---1----------- and 24'---01-1-0---1----------- from group (2 5 16'0100000000000010).
+ Merging pattern 24'---010101--------1----1- and 24'---010111--------1----1- from group (3 1 16'0001000010000000).
+ Merging pattern 24'---001101--------1----1- and 24'---001111--------1----1- from group (3 1 16'0001000010000000).
+ Merging pattern 24'---011101--------1----1- and 24'---011111--------1----1- from group (3 1 16'0001000010000000).
+ Merging pattern 24'---010111--------1----1- and 24'---010101--------1----1- from group (3 1 16'0001000010000000).
+ Merging pattern 24'---001111--------1----1- and 24'---001101--------1----1- from group (3 1 16'0001000010000000).
+ Merging pattern 24'---011111--------1----1- and 24'---011101--------1----1- from group (3 1 16'0001000010000000).
+ Merging pattern 24'---010101--------0------ and 24'---010111--------0------ from group (3 1 16'0001000010000000).
+ Merging pattern 24'---001101--------0------ and 24'---001111--------0------ from group (3 1 16'0001000010000000).
+ Merging pattern 24'---011101--------0------ and 24'---011111--------0------ from group (3 1 16'0001000010000000).
+ Merging pattern 24'---010111--------0------ and 24'---010101--------0------ from group (3 1 16'0001000010000000).
+ Merging pattern 24'---001111--------0------ and 24'---001101--------0------ from group (3 1 16'0001000010000000).
+ Merging pattern 24'---011111--------0------ and 24'---011101--------0------ from group (3 1 16'0001000010000000).
+ Merging pattern 24'---110101--------------- and 24'---110111--------------- from group (3 1 16'0001000010000000).
+ Merging pattern 24'---101101--------------- and 24'---101111--------------- from group (3 1 16'0001000010000000).
+ Merging pattern 24'---111101--------------- and 24'---111111--------------- from group (3 1 16'0001000010000000).
+ Merging pattern 24'---110111--------------- and 24'---110101--------------- from group (3 1 16'0001000010000000).
+ Merging pattern 24'---101111--------------- and 24'---101101--------------- from group (3 1 16'0001000010000000).
+ Merging pattern 24'---111111--------------- and 24'---111101--------------- from group (3 1 16'0001000010000000).
+ Merging pattern 24'---0101-1--------1----1- and 24'---0111-1--------1----1- from group (3 1 16'0001000010000000).
+ Merging pattern 24'---0111-1--------1----1- and 24'---0101-1--------1----1- from group (3 1 16'0001000010000000).
+ Merging pattern 24'---0101-1--------0------ and 24'---0111-1--------0------ from group (3 1 16'0001000010000000).
+ Merging pattern 24'---0111-1--------0------ and 24'---0101-1--------0------ from group (3 1 16'0001000010000000).
+ Merging pattern 24'---1101-1--------------- and 24'---1111-1--------------- from group (3 1 16'0001000010000000).
+ Merging pattern 24'---1111-1--------------- and 24'---1101-1--------------- from group (3 1 16'0001000010000000).
+ Merging pattern 24'---01-1-0--------1----1- and 24'---01-1-1--------1----1- from group (3 1 16'0001000010000000).
+ Merging pattern 24'---01-1-1--------1----1- and 24'---01-1-0--------1----1- from group (3 1 16'0001000010000000).
+ Merging pattern 24'---01-1-0--------0------ and 24'---01-1-1--------0------ from group (3 1 16'0001000010000000).
+ Merging pattern 24'---01-1-1--------0------ and 24'---01-1-0--------0------ from group (3 1 16'0001000010000000).
+ Merging pattern 24'---11-1-0--------------- and 24'---11-1-1--------------- from group (3 1 16'0001000010000000).
+ Merging pattern 24'---11-1-1--------------- and 24'---11-1-0--------------- from group (3 1 16'0001000010000000).
+ Merging pattern 24'---010101--------1----0- and 24'---010111--------1----0- from group (3 3 16'0001000000010000).
+ Merging pattern 24'---001101--------1----0- and 24'---001111--------1----0- from group (3 3 16'0001000000010000).
+ Merging pattern 24'---011101--------1----0- and 24'---011111--------1----0- from group (3 3 16'0001000000010000).
+ Merging pattern 24'---010111--------1----0- and 24'---010101--------1----0- from group (3 3 16'0001000000010000).
+ Merging pattern 24'---001111--------1----0- and 24'---001101--------1----0- from group (3 3 16'0001000000010000).
+ Merging pattern 24'---011111--------1----0- and 24'---011101--------1----0- from group (3 3 16'0001000000010000).
+ Merging pattern 24'---0101-1--------1----0- and 24'---0111-1--------1----0- from group (3 3 16'0001000000010000).
+ Merging pattern 24'---0111-1--------1----0- and 24'---0101-1--------1----0- from group (3 3 16'0001000000010000).
+ Merging pattern 24'---01-1-0--------1----0- and 24'---01-1-1--------1----0- from group (3 3 16'0001000000010000).
+ Merging pattern 24'---01-1-1--------1----0- and 24'---01-1-0--------1----0- from group (3 3 16'0001000000010000).
+ Merging pattern 24'---01010111------------- and 24'---01011111------------- from group (4 1 16'0000010010000000).
+ Merging pattern 24'---00110111------------- and 24'---00111111------------- from group (4 1 16'0000010010000000).
+ Merging pattern 24'---01110111------------- and 24'---01111111------------- from group (4 1 16'0000010010000000).
+ Merging pattern 24'---01011111------------- and 24'---01010111------------- from group (4 1 16'0000010010000000).
+ Merging pattern 24'---00111111------------- and 24'---00110111------------- from group (4 1 16'0000010010000000).
+ Merging pattern 24'---01111111------------- and 24'---01110111------------- from group (4 1 16'0000010010000000).
+ Merging pattern 24'---110101--------------- and 24'---110111--------------- from group (4 1 16'0000010010000000).
+ Merging pattern 24'---101101--------------- and 24'---101111--------------- from group (4 1 16'0000010010000000).
+ Merging pattern 24'---111101--------------- and 24'---111111--------------- from group (4 1 16'0000010010000000).
+ Merging pattern 24'---110111--------------- and 24'---110101--------------- from group (4 1 16'0000010010000000).
+ Merging pattern 24'---101111--------------- and 24'---101101--------------- from group (4 1 16'0000010010000000).
+ Merging pattern 24'---111111--------------- and 24'---111101--------------- from group (4 1 16'0000010010000000).
+ Merging pattern 24'---0101-111------------- and 24'---0111-111------------- from group (4 1 16'0000010010000000).
+ Merging pattern 24'---0111-111------------- and 24'---0101-111------------- from group (4 1 16'0000010010000000).
+ Merging pattern 24'---1101-1--------------- and 24'---1111-1--------------- from group (4 1 16'0000010010000000).
+ Merging pattern 24'---1111-1--------------- and 24'---1101-1--------------- from group (4 1 16'0000010010000000).
+ Merging pattern 24'---01-1-011------------- and 24'---01-1-111------------- from group (4 1 16'0000010010000000).
+ Merging pattern 24'---01-1-111------------- and 24'---01-1-011------------- from group (4 1 16'0000010010000000).
+ Merging pattern 24'---11-1-0--------------- and 24'---11-1-1--------------- from group (4 1 16'0000010010000000).
+ Merging pattern 24'---11-1-1--------------- and 24'---11-1-0--------------- from group (4 1 16'0000010010000000).
+ Merging pattern 24'---010101-0------------- and 24'---010111-0------------- from group (4 4 16'0000010000000100).
+ Merging pattern 24'---001101-0------------- and 24'---001111-0------------- from group (4 4 16'0000010000000100).
+ Merging pattern 24'---011101-0------------- and 24'---011111-0------------- from group (4 4 16'0000010000000100).
+ Merging pattern 24'---010111-0------------- and 24'---010101-0------------- from group (4 4 16'0000010000000100).
+ Merging pattern 24'---001111-0------------- and 24'---001101-0------------- from group (4 4 16'0000010000000100).
+ Merging pattern 24'---011111-0------------- and 24'---011101-0------------- from group (4 4 16'0000010000000100).
+ Merging pattern 24'---01010101------------- and 24'---01011101------------- from group (4 4 16'0000010000000100).
+ Merging pattern 24'---00110101------------- and 24'---00111101------------- from group (4 4 16'0000010000000100).
+ Merging pattern 24'---01110101------------- and 24'---01111101------------- from group (4 4 16'0000010000000100).
+ Merging pattern 24'---01011101------------- and 24'---01010101------------- from group (4 4 16'0000010000000100).
+ Merging pattern 24'---00111101------------- and 24'---00110101------------- from group (4 4 16'0000010000000100).
+ Merging pattern 24'---01111101------------- and 24'---01110101------------- from group (4 4 16'0000010000000100).
+ Merging pattern 24'---0101-1-0------------- and 24'---0111-1-0------------- from group (4 4 16'0000010000000100).
+ Merging pattern 24'---0111-1-0------------- and 24'---0101-1-0------------- from group (4 4 16'0000010000000100).
+ Merging pattern 24'---0101-101------------- and 24'---0111-101------------- from group (4 4 16'0000010000000100).
+ Merging pattern 24'---0111-101------------- and 24'---0101-101------------- from group (4 4 16'0000010000000100).
+ Merging pattern 24'---01-1-0-0------------- and 24'---01-1-1-0------------- from group (4 4 16'0000010000000100).
+ Merging pattern 24'---01-1-1-0------------- and 24'---01-1-0-0------------- from group (4 4 16'0000010000000100).
+ Merging pattern 24'---01-1-001------------- and 24'---01-1-101------------- from group (4 4 16'0000010000000100).
+ Merging pattern 24'---01-1-101------------- and 24'---01-1-001------------- from group (4 4 16'0000010000000100).
+ Merging pattern 24'---01010111------------- and 24'---01011111------------- from group (5 1 16'0000001010000000).
+ Merging pattern 24'---00110111------------- and 24'---00111111------------- from group (5 1 16'0000001010000000).
+ Merging pattern 24'---01110111------------- and 24'---01111111------------- from group (5 1 16'0000001010000000).
+ Merging pattern 24'---01011111------------- and 24'---01010111------------- from group (5 1 16'0000001010000000).
+ Merging pattern 24'---00111111------------- and 24'---00110111------------- from group (5 1 16'0000001010000000).
+ Merging pattern 24'---01111111------------- and 24'---01110111------------- from group (5 1 16'0000001010000000).
+ Merging pattern 24'---110101--------------- and 24'---110111--------------- from group (5 1 16'0000001010000000).
+ Merging pattern 24'---101101--------------- and 24'---101111--------------- from group (5 1 16'0000001010000000).
+ Merging pattern 24'---111101--------------- and 24'---111111--------------- from group (5 1 16'0000001010000000).
+ Merging pattern 24'---110111--------------- and 24'---110101--------------- from group (5 1 16'0000001010000000).
+ Merging pattern 24'---101111--------------- and 24'---101101--------------- from group (5 1 16'0000001010000000).
+ Merging pattern 24'---111111--------------- and 24'---111101--------------- from group (5 1 16'0000001010000000).
+ Merging pattern 24'---0101-111------------- and 24'---0111-111------------- from group (5 1 16'0000001010000000).
+ Merging pattern 24'---0111-111------------- and 24'---0101-111------------- from group (5 1 16'0000001010000000).
+ Merging pattern 24'---1101-1--------------- and 24'---1111-1--------------- from group (5 1 16'0000001010000000).
+ Merging pattern 24'---1111-1--------------- and 24'---1101-1--------------- from group (5 1 16'0000001010000000).
+ Merging pattern 24'---01-1-011------------- and 24'---01-1-111------------- from group (5 1 16'0000001010000000).
+ Merging pattern 24'---01-1-111------------- and 24'---01-1-011------------- from group (5 1 16'0000001010000000).
+ Merging pattern 24'---11-1-0--------------- and 24'---11-1-1--------------- from group (5 1 16'0000001010000000).
+ Merging pattern 24'---11-1-1--------------- and 24'---11-1-0--------------- from group (5 1 16'0000001010000000).
+ Merging pattern 24'---010101-0------------- and 24'---010111-0------------- from group (5 5 16'0000001000000010).
+ Merging pattern 24'---001101-0------------- and 24'---001111-0------------- from group (5 5 16'0000001000000010).
+ Merging pattern 24'---011101-0------------- and 24'---011111-0------------- from group (5 5 16'0000001000000010).
+ Merging pattern 24'---010111-0------------- and 24'---010101-0------------- from group (5 5 16'0000001000000010).
+ Merging pattern 24'---001111-0------------- and 24'---001101-0------------- from group (5 5 16'0000001000000010).
+ Merging pattern 24'---011111-0------------- and 24'---011101-0------------- from group (5 5 16'0000001000000010).
+ Merging pattern 24'---01010101------------- and 24'---01011101------------- from group (5 5 16'0000001000000010).
+ Merging pattern 24'---00110101------------- and 24'---00111101------------- from group (5 5 16'0000001000000010).
+ Merging pattern 24'---01110101------------- and 24'---01111101------------- from group (5 5 16'0000001000000010).
+ Merging pattern 24'---01011101------------- and 24'---01010101------------- from group (5 5 16'0000001000000010).
+ Merging pattern 24'---00111101------------- and 24'---00110101------------- from group (5 5 16'0000001000000010).
+ Merging pattern 24'---01111101------------- and 24'---01110101------------- from group (5 5 16'0000001000000010).
+ Merging pattern 24'---0101-1-0------------- and 24'---0111-1-0------------- from group (5 5 16'0000001000000010).
+ Merging pattern 24'---0111-1-0------------- and 24'---0101-1-0------------- from group (5 5 16'0000001000000010).
+ Merging pattern 24'---0101-101------------- and 24'---0111-101------------- from group (5 5 16'0000001000000010).
+ Merging pattern 24'---0111-101------------- and 24'---0101-101------------- from group (5 5 16'0000001000000010).
+ Merging pattern 24'---01-1-0-0------------- and 24'---01-1-1-0------------- from group (5 5 16'0000001000000010).
+ Merging pattern 24'---01-1-1-0------------- and 24'---01-1-0-0------------- from group (5 5 16'0000001000000010).
+ Merging pattern 24'---01-1-001------------- and 24'---01-1-101------------- from group (5 5 16'0000001000000010).
+ Merging pattern 24'---01-1-101------------- and 24'---01-1-001------------- from group (5 5 16'0000001000000010).
+ Removing unused input signal $auto$opt_reduce.cc:134:opt_mux$17203.
+ Removing unused input signal $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$eq$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1826$3420_Y.
+Optimizing FSM `$fsm$\softshell.cpus[1].core.cpu.state$17253' from module `\user_proj_example'.
+ Merging pattern 3'0-- and 3'1-- from group (1 0 5'00010).
+ Merging pattern 3'1-- and 3'0-- from group (1 0 5'00010).
+Optimizing FSM `$fsm$\softshell.cpus[1].core.cpu.picorv32_core.mem_wordsize$17248' from module `\user_proj_example'.
+Optimizing FSM `$fsm$\softshell.cpus[1].core.cpu.picorv32_core.cpu_state$17238' from module `\user_proj_example'.
+ Merging pattern 24'---010101--------------- and 24'---010111--------------- from group (0 0 16'0000001100000000).
+ Merging pattern 24'---001101--------------- and 24'---001111--------------- from group (0 0 16'0000001100000000).
+ Merging pattern 24'---011101--------------- and 24'---011111--------------- from group (0 0 16'0000001100000000).
+ Merging pattern 24'---010111--------------- and 24'---010101--------------- from group (0 0 16'0000001100000000).
+ Merging pattern 24'---001111--------------- and 24'---001101--------------- from group (0 0 16'0000001100000000).
+ Merging pattern 24'---011111--------------- and 24'---011101--------------- from group (0 0 16'0000001100000000).
+ Merging pattern 24'---0101-1--------------- and 24'---0111-1--------------- from group (0 0 16'0000001100000000).
+ Merging pattern 24'---0111-1--------------- and 24'---0101-1--------------- from group (0 0 16'0000001100000000).
+ Merging pattern 24'---01-1-0--------------- and 24'---01-1-1--------------- from group (0 0 16'0000001100000000).
+ Merging pattern 24'---01-1-1--------------- and 24'---01-1-0--------------- from group (0 0 16'0000001100000000).
+ Merging pattern 24'---110101--------------- and 24'---110111--------------- from group (0 1 16'0000001010000000).
+ Merging pattern 24'---101101--------------- and 24'---101111--------------- from group (0 1 16'0000001010000000).
+ Merging pattern 24'---111101--------------- and 24'---111111--------------- from group (0 1 16'0000001010000000).
+ Merging pattern 24'---110111--------------- and 24'---110101--------------- from group (0 1 16'0000001010000000).
+ Merging pattern 24'---101111--------------- and 24'---101101--------------- from group (0 1 16'0000001010000000).
+ Merging pattern 24'---111111--------------- and 24'---111101--------------- from group (0 1 16'0000001010000000).
+ Merging pattern 24'---1101-1--------------- and 24'---1111-1--------------- from group (0 1 16'0000001010000000).
+ Merging pattern 24'---1111-1--------------- and 24'---1101-1--------------- from group (0 1 16'0000001010000000).
+ Merging pattern 24'---11-1-0--------------- and 24'---11-1-1--------------- from group (0 1 16'0000001010000000).
+ Merging pattern 24'---11-1-1--------------- and 24'---11-1-0--------------- from group (0 1 16'0000001010000000).
+ Merging pattern 24'---010101------00--1-1-- and 24'---010111------00--1-1-- from group (1 1 16'0000000010000001).
+ Merging pattern 24'---001101------00--1-1-- and 24'---001111------00--1-1-- from group (1 1 16'0000000010000001).
+ Merging pattern 24'---011101------00--1-1-- and 24'---011111------00--1-1-- from group (1 1 16'0000000010000001).
+ Merging pattern 24'---010111------00--1-1-- and 24'---010101------00--1-1-- from group (1 1 16'0000000010000001).
+ Merging pattern 24'---001111------00--1-1-- and 24'---001101------00--1-1-- from group (1 1 16'0000000010000001).
+ Merging pattern 24'---011111------00--1-1-- and 24'---011101------00--1-1-- from group (1 1 16'0000000010000001).
+ Merging pattern 24'---010101------00--0---- and 24'---010111------00--0---- from group (1 1 16'0000000010000001).
+ Merging pattern 24'---001101------00--0---- and 24'---001111------00--0---- from group (1 1 16'0000000010000001).
+ Merging pattern 24'---011101------00--0---- and 24'---011111------00--0---- from group (1 1 16'0000000010000001).
+ Merging pattern 24'---010111------00--0---- and 24'---010101------00--0---- from group (1 1 16'0000000010000001).
+ Merging pattern 24'---001111------00--0---- and 24'---001101------00--0---- from group (1 1 16'0000000010000001).
+ Merging pattern 24'---011111------00--0---- and 24'---011101------00--0---- from group (1 1 16'0000000010000001).
+ Merging pattern 24'---010101------10------- and 24'---010111------10------- from group (1 1 16'0000000010000001).
+ Merging pattern 24'---001101------10------- and 24'---001111------10------- from group (1 1 16'0000000010000001).
+ Merging pattern 24'---011101------10------- and 24'---011111------10------- from group (1 1 16'0000000010000001).
+ Merging pattern 24'---010111------10------- and 24'---010101------10------- from group (1 1 16'0000000010000001).
+ Merging pattern 24'---001111------10------- and 24'---001101------10------- from group (1 1 16'0000000010000001).
+ Merging pattern 24'---011111------10------- and 24'---011101------10------- from group (1 1 16'0000000010000001).
+ Merging pattern 24'---010101-------1------- and 24'---010111-------1------- from group (1 1 16'0000000010000001).
+ Merging pattern 24'---001101-------1------- and 24'---001111-------1------- from group (1 1 16'0000000010000001).
+ Merging pattern 24'---011101-------1------- and 24'---011111-------1------- from group (1 1 16'0000000010000001).
+ Merging pattern 24'---010111-------1------- and 24'---010101-------1------- from group (1 1 16'0000000010000001).
+ Merging pattern 24'---001111-------1------- and 24'---001101-------1------- from group (1 1 16'0000000010000001).
+ Merging pattern 24'---011111-------1------- and 24'---011101-------1------- from group (1 1 16'0000000010000001).
+ Merging pattern 24'---110101--------------- and 24'---110111--------------- from group (1 1 16'0000000010000001).
+ Merging pattern 24'---101101--------------- and 24'---101111--------------- from group (1 1 16'0000000010000001).
+ Merging pattern 24'---111101--------------- and 24'---111111--------------- from group (1 1 16'0000000010000001).
+ Merging pattern 24'---110111--------------- and 24'---110101--------------- from group (1 1 16'0000000010000001).
+ Merging pattern 24'---101111--------------- and 24'---101101--------------- from group (1 1 16'0000000010000001).
+ Merging pattern 24'---111111--------------- and 24'---111101--------------- from group (1 1 16'0000000010000001).
+ Merging pattern 24'---0101-1------00--1-1-- and 24'---0111-1------00--1-1-- from group (1 1 16'0000000010000001).
+ Merging pattern 24'---0111-1------00--1-1-- and 24'---0101-1------00--1-1-- from group (1 1 16'0000000010000001).
+ Merging pattern 24'---0101-1------00--0---- and 24'---0111-1------00--0---- from group (1 1 16'0000000010000001).
+ Merging pattern 24'---0111-1------00--0---- and 24'---0101-1------00--0---- from group (1 1 16'0000000010000001).
+ Merging pattern 24'---0101-1------10------- and 24'---0111-1------10------- from group (1 1 16'0000000010000001).
+ Merging pattern 24'---0111-1------10------- and 24'---0101-1------10------- from group (1 1 16'0000000010000001).
+ Merging pattern 24'---0101-1-------1------- and 24'---0111-1-------1------- from group (1 1 16'0000000010000001).
+ Merging pattern 24'---0111-1-------1------- and 24'---0101-1-------1------- from group (1 1 16'0000000010000001).
+ Merging pattern 24'---1101-1--------------- and 24'---1111-1--------------- from group (1 1 16'0000000010000001).
+ Merging pattern 24'---1111-1--------------- and 24'---1101-1--------------- from group (1 1 16'0000000010000001).
+ Merging pattern 24'---01-1-0------00--1-1-- and 24'---01-1-1------00--1-1-- from group (1 1 16'0000000010000001).
+ Merging pattern 24'---01-1-1------00--1-1-- and 24'---01-1-0------00--1-1-- from group (1 1 16'0000000010000001).
+ Merging pattern 24'---01-1-0------00--0---- and 24'---01-1-1------00--0---- from group (1 1 16'0000000010000001).
+ Merging pattern 24'---01-1-1------00--0---- and 24'---01-1-0------00--0---- from group (1 1 16'0000000010000001).
+ Merging pattern 24'---01-1-0------10------- and 24'---01-1-1------10------- from group (1 1 16'0000000010000001).
+ Merging pattern 24'---01-1-1------10------- and 24'---01-1-0------10------- from group (1 1 16'0000000010000001).
+ Merging pattern 24'---01-1-0-------1------- and 24'---01-1-1-------1------- from group (1 1 16'0000000010000001).
+ Merging pattern 24'---01-1-1-------1------- and 24'---01-1-0-------1------- from group (1 1 16'0000000010000001).
+ Merging pattern 24'---11-1-0--------------- and 24'---11-1-1--------------- from group (1 1 16'0000000010000001).
+ Merging pattern 24'---11-1-1--------------- and 24'---11-1-0--------------- from group (1 1 16'0000000010000001).
+ Merging pattern 24'---010101------00--1-0-- and 24'---010111------00--1-0-- from group (1 2 16'0000000001000001).
+ Merging pattern 24'---001101------00--1-0-- and 24'---001111------00--1-0-- from group (1 2 16'0000000001000001).
+ Merging pattern 24'---011101------00--1-0-- and 24'---011111------00--1-0-- from group (1 2 16'0000000001000001).
+ Merging pattern 24'---010111------00--1-0-- and 24'---010101------00--1-0-- from group (1 2 16'0000000001000001).
+ Merging pattern 24'---001111------00--1-0-- and 24'---001101------00--1-0-- from group (1 2 16'0000000001000001).
+ Merging pattern 24'---011111------00--1-0-- and 24'---011101------00--1-0-- from group (1 2 16'0000000001000001).
+ Merging pattern 24'---0101-1------00--1-0-- and 24'---0111-1------00--1-0-- from group (1 2 16'0000000001000001).
+ Merging pattern 24'---0111-1------00--1-0-- and 24'---0101-1------00--1-0-- from group (1 2 16'0000000001000001).
+ Merging pattern 24'---01-1-0------00--1-0-- and 24'---01-1-1------00--1-0-- from group (1 2 16'0000000001000001).
+ Merging pattern 24'---01-1-1------00--1-0-- and 24'---01-1-0------00--1-0-- from group (1 2 16'0000000001000001).
+ Merging pattern 24'---010101----01-----1--0 and 24'---010111----01-----1--0 from group (2 0 16'0000100100000000).
+ Merging pattern 24'---001101----01-----1--0 and 24'---001111----01-----1--0 from group (2 0 16'0000100100000000).
+ Merging pattern 24'---011101----01-----1--0 and 24'---011111----01-----1--0 from group (2 0 16'0000100100000000).
+ Merging pattern 24'---010111----01-----1--0 and 24'---010101----01-----1--0 from group (2 0 16'0000100100000000).
+ Merging pattern 24'---001111----01-----1--0 and 24'---001101----01-----1--0 from group (2 0 16'0000100100000000).
+ Merging pattern 24'---011111----01-----1--0 and 24'---011101----01-----1--0 from group (2 0 16'0000100100000000).
+ Merging pattern 24'---0101-1----01-----1--0 and 24'---0111-1----01-----1--0 from group (2 0 16'0000100100000000).
+ Merging pattern 24'---0111-1----01-----1--0 and 24'---0101-1----01-----1--0 from group (2 0 16'0000100100000000).
+ Merging pattern 24'---01-1-0----01-----1--0 and 24'---01-1-1----01-----1--0 from group (2 0 16'0000100100000000).
+ Merging pattern 24'---01-1-1----01-----1--0 and 24'---01-1-0----01-----1--0 from group (2 0 16'0000100100000000).
+ Merging pattern 24'---010101----11-----1--0 and 24'---010111----11-----1--0 from group (2 1 16'0000100010000000).
+ Merging pattern 24'---001101----11-----1--0 and 24'---001111----11-----1--0 from group (2 1 16'0000100010000000).
+ Merging pattern 24'---011101----11-----1--0 and 24'---011111----11-----1--0 from group (2 1 16'0000100010000000).
+ Merging pattern 24'---010111----11-----1--0 and 24'---010101----11-----1--0 from group (2 1 16'0000100010000000).
+ Merging pattern 24'---001111----11-----1--0 and 24'---001101----11-----1--0 from group (2 1 16'0000100010000000).
+ Merging pattern 24'---011111----11-----1--0 and 24'---011101----11-----1--0 from group (2 1 16'0000100010000000).
+ Merging pattern 24'---010101-----------1--1 and 24'---010111-----------1--1 from group (2 1 16'0000100010000000).
+ Merging pattern 24'---001101-----------1--1 and 24'---001111-----------1--1 from group (2 1 16'0000100010000000).
+ Merging pattern 24'---011101-----------1--1 and 24'---011111-----------1--1 from group (2 1 16'0000100010000000).
+ Merging pattern 24'---010111-----------1--1 and 24'---010101-----------1--1 from group (2 1 16'0000100010000000).
+ Merging pattern 24'---001111-----------1--1 and 24'---001101-----------1--1 from group (2 1 16'0000100010000000).
+ Merging pattern 24'---011111-----------1--1 and 24'---011101-----------1--1 from group (2 1 16'0000100010000000).
+ Merging pattern 24'1--010101--------------- and 24'1--010111--------------- from group (2 1 16'0000100010000000).
+ Merging pattern 24'---110101--------------- and 24'---110111--------------- from group (2 1 16'0000100010000000).
+ Merging pattern 24'1--001101--------------- and 24'1--001111--------------- from group (2 1 16'0000100010000000).
+ Merging pattern 24'---101101--------------- and 24'---101111--------------- from group (2 1 16'0000100010000000).
+ Merging pattern 24'1--011101--------------- and 24'1--011111--------------- from group (2 1 16'0000100010000000).
+ Merging pattern 24'---111101--------------- and 24'---111111--------------- from group (2 1 16'0000100010000000).
+ Merging pattern 24'1--010111--------------- and 24'1--010101--------------- from group (2 1 16'0000100010000000).
+ Merging pattern 24'---110111--------------- and 24'---110101--------------- from group (2 1 16'0000100010000000).
+ Merging pattern 24'1--001111--------------- and 24'1--001101--------------- from group (2 1 16'0000100010000000).
+ Merging pattern 24'---101111--------------- and 24'---101101--------------- from group (2 1 16'0000100010000000).
+ Merging pattern 24'1--011111--------------- and 24'1--011101--------------- from group (2 1 16'0000100010000000).
+ Merging pattern 24'---111111--------------- and 24'---111101--------------- from group (2 1 16'0000100010000000).
+ Merging pattern 24'---0101-1----11-----1--0 and 24'---0111-1----11-----1--0 from group (2 1 16'0000100010000000).
+ Merging pattern 24'---0111-1----11-----1--0 and 24'---0101-1----11-----1--0 from group (2 1 16'0000100010000000).
+ Merging pattern 24'---0101-1-----------1--1 and 24'---0111-1-----------1--1 from group (2 1 16'0000100010000000).
+ Merging pattern 24'---0111-1-----------1--1 and 24'---0101-1-----------1--1 from group (2 1 16'0000100010000000).
+ Merging pattern 24'1--0101-1--------------- and 24'1--0111-1--------------- from group (2 1 16'0000100010000000).
+ Merging pattern 24'---1101-1--------------- and 24'---1111-1--------------- from group (2 1 16'0000100010000000).
+ Merging pattern 24'1--0111-1--------------- and 24'1--0101-1--------------- from group (2 1 16'0000100010000000).
+ Merging pattern 24'---1111-1--------------- and 24'---1101-1--------------- from group (2 1 16'0000100010000000).
+ Merging pattern 24'---01-1-0----11-----1--0 and 24'---01-1-1----11-----1--0 from group (2 1 16'0000100010000000).
+ Merging pattern 24'---01-1-1----11-----1--0 and 24'---01-1-0----11-----1--0 from group (2 1 16'0000100010000000).
+ Merging pattern 24'---01-1-0-----------1--1 and 24'---01-1-1-----------1--1 from group (2 1 16'0000100010000000).
+ Merging pattern 24'---01-1-1-----------1--1 and 24'---01-1-0-----------1--1 from group (2 1 16'0000100010000000).
+ Merging pattern 24'1--01-1-0--------------- and 24'1--01-1-1--------------- from group (2 1 16'0000100010000000).
+ Merging pattern 24'---11-1-0--------------- and 24'---11-1-1--------------- from group (2 1 16'0000100010000000).
+ Merging pattern 24'1--01-1-1--------------- and 24'1--01-1-0--------------- from group (2 1 16'0000100010000000).
+ Merging pattern 24'---11-1-1--------------- and 24'---11-1-0--------------- from group (2 1 16'0000100010000000).
+ Merging pattern 24'---010101-----0-----1--0 and 24'---010111-----0-----1--0 from group (2 2 16'0000100001000000).
+ Merging pattern 24'---001101-----0-----1--0 and 24'---001111-----0-----1--0 from group (2 2 16'0000100001000000).
+ Merging pattern 24'---011101-----0-----1--0 and 24'---011111-----0-----1--0 from group (2 2 16'0000100001000000).
+ Merging pattern 24'---010111-----0-----1--0 and 24'---010101-----0-----1--0 from group (2 2 16'0000100001000000).
+ Merging pattern 24'---001111-----0-----1--0 and 24'---001101-----0-----1--0 from group (2 2 16'0000100001000000).
+ Merging pattern 24'---011111-----0-----1--0 and 24'---011101-----0-----1--0 from group (2 2 16'0000100001000000).
+ Merging pattern 24'---0101-1-----0-----1--0 and 24'---0111-1-----0-----1--0 from group (2 2 16'0000100001000000).
+ Merging pattern 24'---0111-1-----0-----1--0 and 24'---0101-1-----0-----1--0 from group (2 2 16'0000100001000000).
+ Merging pattern 24'---01-1-0-----0-----1--0 and 24'---01-1-1-----0-----1--0 from group (2 2 16'0000100001000000).
+ Merging pattern 24'---01-1-1-----0-----1--0 and 24'---01-1-0-----0-----1--0 from group (2 2 16'0000100001000000).
+ Merging pattern 24'00-010101---0-----0-0--- and 24'00-010111---0-----0-0--- from group (2 3 16'0000100000010000).
+ Merging pattern 24'00-001101---0-----0-0--- and 24'00-001111---0-----0-0--- from group (2 3 16'0000100000010000).
+ Merging pattern 24'00-011101---0-----0-0--- and 24'00-011111---0-----0-0--- from group (2 3 16'0000100000010000).
+ Merging pattern 24'00-010111---0-----0-0--- and 24'00-010101---0-----0-0--- from group (2 3 16'0000100000010000).
+ Merging pattern 24'00-001111---0-----0-0--- and 24'00-001101---0-----0-0--- from group (2 3 16'0000100000010000).
+ Merging pattern 24'00-011111---0-----0-0--- and 24'00-011101---0-----0-0--- from group (2 3 16'0000100000010000).
+ Merging pattern 24'-1-010101--------------- and 24'-1-010111--------------- from group (2 3 16'0000100000010000).
+ Merging pattern 24'-1-001101--------------- and 24'-1-001111--------------- from group (2 3 16'0000100000010000).
+ Merging pattern 24'-1-011101--------------- and 24'-1-011111--------------- from group (2 3 16'0000100000010000).
+ Merging pattern 24'-1-010111--------------- and 24'-1-010101--------------- from group (2 3 16'0000100000010000).
+ Merging pattern 24'-1-001111--------------- and 24'-1-001101--------------- from group (2 3 16'0000100000010000).
+ Merging pattern 24'-1-011111--------------- and 24'-1-011101--------------- from group (2 3 16'0000100000010000).
+ Merging pattern 24'00-0101-1---0-----0-0--- and 24'00-0111-1---0-----0-0--- from group (2 3 16'0000100000010000).
+ Merging pattern 24'00-0111-1---0-----0-0--- and 24'00-0101-1---0-----0-0--- from group (2 3 16'0000100000010000).
+ Merging pattern 24'-1-0101-1--------------- and 24'-1-0111-1--------------- from group (2 3 16'0000100000010000).
+ Merging pattern 24'-1-0111-1--------------- and 24'-1-0101-1--------------- from group (2 3 16'0000100000010000).
+ Merging pattern 24'00-01-1-0---0-----0-0--- and 24'00-01-1-1---0-----0-0--- from group (2 3 16'0000100000010000).
+ Merging pattern 24'00-01-1-1---0-----0-0--- and 24'00-01-1-0---0-----0-0--- from group (2 3 16'0000100000010000).
+ Merging pattern 24'-1-01-1-0--------------- and 24'-1-01-1-1--------------- from group (2 3 16'0000100000010000).
+ Merging pattern 24'-1-01-1-1--------------- and 24'-1-01-1-0--------------- from group (2 3 16'0000100000010000).
+ Merging pattern 24'00-010101---0-----1----- and 24'00-010111---0-----1----- from group (2 4 16'0000100000000100).
+ Merging pattern 24'00-001101---0-----1----- and 24'00-001111---0-----1----- from group (2 4 16'0000100000000100).
+ Merging pattern 24'00-011101---0-----1----- and 24'00-011111---0-----1----- from group (2 4 16'0000100000000100).
+ Merging pattern 24'00-010111---0-----1----- and 24'00-010101---0-----1----- from group (2 4 16'0000100000000100).
+ Merging pattern 24'00-001111---0-----1----- and 24'00-001101---0-----1----- from group (2 4 16'0000100000000100).
+ Merging pattern 24'00-011111---0-----1----- and 24'00-011101---0-----1----- from group (2 4 16'0000100000000100).
+ Merging pattern 24'00-0101-1---0-----1----- and 24'00-0111-1---0-----1----- from group (2 4 16'0000100000000100).
+ Merging pattern 24'00-0111-1---0-----1----- and 24'00-0101-1---0-----1----- from group (2 4 16'0000100000000100).
+ Merging pattern 24'00-01-1-0---0-----1----- and 24'00-01-1-1---0-----1----- from group (2 4 16'0000100000000100).
+ Merging pattern 24'00-01-1-1---0-----1----- and 24'00-01-1-0---0-----1----- from group (2 4 16'0000100000000100).
+ Merging pattern 24'---010101---1----------- and 24'---010111---1----------- from group (2 5 16'0000100000000010).
+ Merging pattern 24'---001101---1----------- and 24'---001111---1----------- from group (2 5 16'0000100000000010).
+ Merging pattern 24'---011101---1----------- and 24'---011111---1----------- from group (2 5 16'0000100000000010).
+ Merging pattern 24'---010111---1----------- and 24'---010101---1----------- from group (2 5 16'0000100000000010).
+ Merging pattern 24'---001111---1----------- and 24'---001101---1----------- from group (2 5 16'0000100000000010).
+ Merging pattern 24'---011111---1----------- and 24'---011101---1----------- from group (2 5 16'0000100000000010).
+ Merging pattern 24'---0101-1---1----------- and 24'---0111-1---1----------- from group (2 5 16'0000100000000010).
+ Merging pattern 24'---0111-1---1----------- and 24'---0101-1---1----------- from group (2 5 16'0000100000000010).
+ Merging pattern 24'---01-1-0---1----------- and 24'---01-1-1---1----------- from group (2 5 16'0000100000000010).
+ Merging pattern 24'---01-1-1---1----------- and 24'---01-1-0---1----------- from group (2 5 16'0000100000000010).
+ Merging pattern 24'---010101--------1----1- and 24'---010111--------1----1- from group (3 1 16'0000010010000000).
+ Merging pattern 24'---001101--------1----1- and 24'---001111--------1----1- from group (3 1 16'0000010010000000).
+ Merging pattern 24'---011101--------1----1- and 24'---011111--------1----1- from group (3 1 16'0000010010000000).
+ Merging pattern 24'---010111--------1----1- and 24'---010101--------1----1- from group (3 1 16'0000010010000000).
+ Merging pattern 24'---001111--------1----1- and 24'---001101--------1----1- from group (3 1 16'0000010010000000).
+ Merging pattern 24'---011111--------1----1- and 24'---011101--------1----1- from group (3 1 16'0000010010000000).
+ Merging pattern 24'---010101--------0------ and 24'---010111--------0------ from group (3 1 16'0000010010000000).
+ Merging pattern 24'---001101--------0------ and 24'---001111--------0------ from group (3 1 16'0000010010000000).
+ Merging pattern 24'---011101--------0------ and 24'---011111--------0------ from group (3 1 16'0000010010000000).
+ Merging pattern 24'---010111--------0------ and 24'---010101--------0------ from group (3 1 16'0000010010000000).
+ Merging pattern 24'---001111--------0------ and 24'---001101--------0------ from group (3 1 16'0000010010000000).
+ Merging pattern 24'---011111--------0------ and 24'---011101--------0------ from group (3 1 16'0000010010000000).
+ Merging pattern 24'---110101--------------- and 24'---110111--------------- from group (3 1 16'0000010010000000).
+ Merging pattern 24'---101101--------------- and 24'---101111--------------- from group (3 1 16'0000010010000000).
+ Merging pattern 24'---111101--------------- and 24'---111111--------------- from group (3 1 16'0000010010000000).
+ Merging pattern 24'---110111--------------- and 24'---110101--------------- from group (3 1 16'0000010010000000).
+ Merging pattern 24'---101111--------------- and 24'---101101--------------- from group (3 1 16'0000010010000000).
+ Merging pattern 24'---111111--------------- and 24'---111101--------------- from group (3 1 16'0000010010000000).
+ Merging pattern 24'---0101-1--------1----1- and 24'---0111-1--------1----1- from group (3 1 16'0000010010000000).
+ Merging pattern 24'---0111-1--------1----1- and 24'---0101-1--------1----1- from group (3 1 16'0000010010000000).
+ Merging pattern 24'---0101-1--------0------ and 24'---0111-1--------0------ from group (3 1 16'0000010010000000).
+ Merging pattern 24'---0111-1--------0------ and 24'---0101-1--------0------ from group (3 1 16'0000010010000000).
+ Merging pattern 24'---1101-1--------------- and 24'---1111-1--------------- from group (3 1 16'0000010010000000).
+ Merging pattern 24'---1111-1--------------- and 24'---1101-1--------------- from group (3 1 16'0000010010000000).
+ Merging pattern 24'---01-1-0--------1----1- and 24'---01-1-1--------1----1- from group (3 1 16'0000010010000000).
+ Merging pattern 24'---01-1-1--------1----1- and 24'---01-1-0--------1----1- from group (3 1 16'0000010010000000).
+ Merging pattern 24'---01-1-0--------0------ and 24'---01-1-1--------0------ from group (3 1 16'0000010010000000).
+ Merging pattern 24'---01-1-1--------0------ and 24'---01-1-0--------0------ from group (3 1 16'0000010010000000).
+ Merging pattern 24'---11-1-0--------------- and 24'---11-1-1--------------- from group (3 1 16'0000010010000000).
+ Merging pattern 24'---11-1-1--------------- and 24'---11-1-0--------------- from group (3 1 16'0000010010000000).
+ Merging pattern 24'---010101--------1----0- and 24'---010111--------1----0- from group (3 3 16'0000010000010000).
+ Merging pattern 24'---001101--------1----0- and 24'---001111--------1----0- from group (3 3 16'0000010000010000).
+ Merging pattern 24'---011101--------1----0- and 24'---011111--------1----0- from group (3 3 16'0000010000010000).
+ Merging pattern 24'---010111--------1----0- and 24'---010101--------1----0- from group (3 3 16'0000010000010000).
+ Merging pattern 24'---001111--------1----0- and 24'---001101--------1----0- from group (3 3 16'0000010000010000).
+ Merging pattern 24'---011111--------1----0- and 24'---011101--------1----0- from group (3 3 16'0000010000010000).
+ Merging pattern 24'---0101-1--------1----0- and 24'---0111-1--------1----0- from group (3 3 16'0000010000010000).
+ Merging pattern 24'---0111-1--------1----0- and 24'---0101-1--------1----0- from group (3 3 16'0000010000010000).
+ Merging pattern 24'---01-1-0--------1----0- and 24'---01-1-1--------1----0- from group (3 3 16'0000010000010000).
+ Merging pattern 24'---01-1-1--------1----0- and 24'---01-1-0--------1----0- from group (3 3 16'0000010000010000).
+ Merging pattern 24'---01010111------------- and 24'---01011111------------- from group (4 1 16'1000000010000000).
+ Merging pattern 24'---00110111------------- and 24'---00111111------------- from group (4 1 16'1000000010000000).
+ Merging pattern 24'---01110111------------- and 24'---01111111------------- from group (4 1 16'1000000010000000).
+ Merging pattern 24'---01011111------------- and 24'---01010111------------- from group (4 1 16'1000000010000000).
+ Merging pattern 24'---00111111------------- and 24'---00110111------------- from group (4 1 16'1000000010000000).
+ Merging pattern 24'---01111111------------- and 24'---01110111------------- from group (4 1 16'1000000010000000).
+ Merging pattern 24'---110101--------------- and 24'---110111--------------- from group (4 1 16'1000000010000000).
+ Merging pattern 24'---101101--------------- and 24'---101111--------------- from group (4 1 16'1000000010000000).
+ Merging pattern 24'---111101--------------- and 24'---111111--------------- from group (4 1 16'1000000010000000).
+ Merging pattern 24'---110111--------------- and 24'---110101--------------- from group (4 1 16'1000000010000000).
+ Merging pattern 24'---101111--------------- and 24'---101101--------------- from group (4 1 16'1000000010000000).
+ Merging pattern 24'---111111--------------- and 24'---111101--------------- from group (4 1 16'1000000010000000).
+ Merging pattern 24'---0101-111------------- and 24'---0111-111------------- from group (4 1 16'1000000010000000).
+ Merging pattern 24'---0111-111------------- and 24'---0101-111------------- from group (4 1 16'1000000010000000).
+ Merging pattern 24'---1101-1--------------- and 24'---1111-1--------------- from group (4 1 16'1000000010000000).
+ Merging pattern 24'---1111-1--------------- and 24'---1101-1--------------- from group (4 1 16'1000000010000000).
+ Merging pattern 24'---01-1-011------------- and 24'---01-1-111------------- from group (4 1 16'1000000010000000).
+ Merging pattern 24'---01-1-111------------- and 24'---01-1-011------------- from group (4 1 16'1000000010000000).
+ Merging pattern 24'---11-1-0--------------- and 24'---11-1-1--------------- from group (4 1 16'1000000010000000).
+ Merging pattern 24'---11-1-1--------------- and 24'---11-1-0--------------- from group (4 1 16'1000000010000000).
+ Merging pattern 24'---010101-0------------- and 24'---010111-0------------- from group (4 4 16'1000000000000100).
+ Merging pattern 24'---001101-0------------- and 24'---001111-0------------- from group (4 4 16'1000000000000100).
+ Merging pattern 24'---011101-0------------- and 24'---011111-0------------- from group (4 4 16'1000000000000100).
+ Merging pattern 24'---010111-0------------- and 24'---010101-0------------- from group (4 4 16'1000000000000100).
+ Merging pattern 24'---001111-0------------- and 24'---001101-0------------- from group (4 4 16'1000000000000100).
+ Merging pattern 24'---011111-0------------- and 24'---011101-0------------- from group (4 4 16'1000000000000100).
+ Merging pattern 24'---01010101------------- and 24'---01011101------------- from group (4 4 16'1000000000000100).
+ Merging pattern 24'---00110101------------- and 24'---00111101------------- from group (4 4 16'1000000000000100).
+ Merging pattern 24'---01110101------------- and 24'---01111101------------- from group (4 4 16'1000000000000100).
+ Merging pattern 24'---01011101------------- and 24'---01010101------------- from group (4 4 16'1000000000000100).
+ Merging pattern 24'---00111101------------- and 24'---00110101------------- from group (4 4 16'1000000000000100).
+ Merging pattern 24'---01111101------------- and 24'---01110101------------- from group (4 4 16'1000000000000100).
+ Merging pattern 24'---0101-1-0------------- and 24'---0111-1-0------------- from group (4 4 16'1000000000000100).
+ Merging pattern 24'---0111-1-0------------- and 24'---0101-1-0------------- from group (4 4 16'1000000000000100).
+ Merging pattern 24'---0101-101------------- and 24'---0111-101------------- from group (4 4 16'1000000000000100).
+ Merging pattern 24'---0111-101------------- and 24'---0101-101------------- from group (4 4 16'1000000000000100).
+ Merging pattern 24'---01-1-0-0------------- and 24'---01-1-1-0------------- from group (4 4 16'1000000000000100).
+ Merging pattern 24'---01-1-1-0------------- and 24'---01-1-0-0------------- from group (4 4 16'1000000000000100).
+ Merging pattern 24'---01-1-001------------- and 24'---01-1-101------------- from group (4 4 16'1000000000000100).
+ Merging pattern 24'---01-1-101------------- and 24'---01-1-001------------- from group (4 4 16'1000000000000100).
+ Merging pattern 24'---01010111------------- and 24'---01011111------------- from group (5 1 16'0001000010000000).
+ Merging pattern 24'---00110111------------- and 24'---00111111------------- from group (5 1 16'0001000010000000).
+ Merging pattern 24'---01110111------------- and 24'---01111111------------- from group (5 1 16'0001000010000000).
+ Merging pattern 24'---01011111------------- and 24'---01010111------------- from group (5 1 16'0001000010000000).
+ Merging pattern 24'---00111111------------- and 24'---00110111------------- from group (5 1 16'0001000010000000).
+ Merging pattern 24'---01111111------------- and 24'---01110111------------- from group (5 1 16'0001000010000000).
+ Merging pattern 24'---110101--------------- and 24'---110111--------------- from group (5 1 16'0001000010000000).
+ Merging pattern 24'---101101--------------- and 24'---101111--------------- from group (5 1 16'0001000010000000).
+ Merging pattern 24'---111101--------------- and 24'---111111--------------- from group (5 1 16'0001000010000000).
+ Merging pattern 24'---110111--------------- and 24'---110101--------------- from group (5 1 16'0001000010000000).
+ Merging pattern 24'---101111--------------- and 24'---101101--------------- from group (5 1 16'0001000010000000).
+ Merging pattern 24'---111111--------------- and 24'---111101--------------- from group (5 1 16'0001000010000000).
+ Merging pattern 24'---0101-111------------- and 24'---0111-111------------- from group (5 1 16'0001000010000000).
+ Merging pattern 24'---0111-111------------- and 24'---0101-111------------- from group (5 1 16'0001000010000000).
+ Merging pattern 24'---1101-1--------------- and 24'---1111-1--------------- from group (5 1 16'0001000010000000).
+ Merging pattern 24'---1111-1--------------- and 24'---1101-1--------------- from group (5 1 16'0001000010000000).
+ Merging pattern 24'---01-1-011------------- and 24'---01-1-111------------- from group (5 1 16'0001000010000000).
+ Merging pattern 24'---01-1-111------------- and 24'---01-1-011------------- from group (5 1 16'0001000010000000).
+ Merging pattern 24'---11-1-0--------------- and 24'---11-1-1--------------- from group (5 1 16'0001000010000000).
+ Merging pattern 24'---11-1-1--------------- and 24'---11-1-0--------------- from group (5 1 16'0001000010000000).
+ Merging pattern 24'---010101-0------------- and 24'---010111-0------------- from group (5 5 16'0001000000000010).
+ Merging pattern 24'---001101-0------------- and 24'---001111-0------------- from group (5 5 16'0001000000000010).
+ Merging pattern 24'---011101-0------------- and 24'---011111-0------------- from group (5 5 16'0001000000000010).
+ Merging pattern 24'---010111-0------------- and 24'---010101-0------------- from group (5 5 16'0001000000000010).
+ Merging pattern 24'---001111-0------------- and 24'---001101-0------------- from group (5 5 16'0001000000000010).
+ Merging pattern 24'---011111-0------------- and 24'---011101-0------------- from group (5 5 16'0001000000000010).
+ Merging pattern 24'---01010101------------- and 24'---01011101------------- from group (5 5 16'0001000000000010).
+ Merging pattern 24'---00110101------------- and 24'---00111101------------- from group (5 5 16'0001000000000010).
+ Merging pattern 24'---01110101------------- and 24'---01111101------------- from group (5 5 16'0001000000000010).
+ Merging pattern 24'---01011101------------- and 24'---01010101------------- from group (5 5 16'0001000000000010).
+ Merging pattern 24'---00111101------------- and 24'---00110101------------- from group (5 5 16'0001000000000010).
+ Merging pattern 24'---01111101------------- and 24'---01110101------------- from group (5 5 16'0001000000000010).
+ Merging pattern 24'---0101-1-0------------- and 24'---0111-1-0------------- from group (5 5 16'0001000000000010).
+ Merging pattern 24'---0111-1-0------------- and 24'---0101-1-0------------- from group (5 5 16'0001000000000010).
+ Merging pattern 24'---0101-101------------- and 24'---0111-101------------- from group (5 5 16'0001000000000010).
+ Merging pattern 24'---0111-101------------- and 24'---0101-101------------- from group (5 5 16'0001000000000010).
+ Merging pattern 24'---01-1-0-0------------- and 24'---01-1-1-0------------- from group (5 5 16'0001000000000010).
+ Merging pattern 24'---01-1-1-0------------- and 24'---01-1-0-0------------- from group (5 5 16'0001000000000010).
+ Merging pattern 24'---01-1-001------------- and 24'---01-1-101------------- from group (5 5 16'0001000000000010).
+ Merging pattern 24'---01-1-101------------- and 24'---01-1-001------------- from group (5 5 16'0001000000000010).
+ Removing unused input signal $auto$opt_reduce.cc:134:opt_mux$17187.
+ Removing unused input signal $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$eq$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1826$4103_Y.
+Optimizing FSM `$fsm$\softshell.cpus[0].core.cpu.state$17233' from module `\user_proj_example'.
+ Merging pattern 3'0-- and 3'1-- from group (1 0 5'00010).
+ Merging pattern 3'1-- and 3'0-- from group (1 0 5'00010).
+Optimizing FSM `$fsm$\softshell.cpus[0].core.cpu.picorv32_core.mem_wordsize$17228' from module `\user_proj_example'.
+Optimizing FSM `$fsm$\softshell.cpus[0].core.cpu.picorv32_core.cpu_state$17218' from module `\user_proj_example'.
+ Merging pattern 24'--010101---------------- and 24'--010111---------------- from group (0 0 16'1000000100000000).
+ Merging pattern 24'--001101---------------- and 24'--001111---------------- from group (0 0 16'1000000100000000).
+ Merging pattern 24'--011101---------------- and 24'--011111---------------- from group (0 0 16'1000000100000000).
+ Merging pattern 24'--010111---------------- and 24'--010101---------------- from group (0 0 16'1000000100000000).
+ Merging pattern 24'--001111---------------- and 24'--001101---------------- from group (0 0 16'1000000100000000).
+ Merging pattern 24'--011111---------------- and 24'--011101---------------- from group (0 0 16'1000000100000000).
+ Merging pattern 24'--0101-1---------------- and 24'--0111-1---------------- from group (0 0 16'1000000100000000).
+ Merging pattern 24'--0111-1---------------- and 24'--0101-1---------------- from group (0 0 16'1000000100000000).
+ Merging pattern 24'--01-1-0---------------- and 24'--01-1-1---------------- from group (0 0 16'1000000100000000).
+ Merging pattern 24'--01-1-1---------------- and 24'--01-1-0---------------- from group (0 0 16'1000000100000000).
+ Merging pattern 24'--110101---------------- and 24'--110111---------------- from group (0 1 16'1000000010000000).
+ Merging pattern 24'--101101---------------- and 24'--101111---------------- from group (0 1 16'1000000010000000).
+ Merging pattern 24'--111101---------------- and 24'--111111---------------- from group (0 1 16'1000000010000000).
+ Merging pattern 24'--110111---------------- and 24'--110101---------------- from group (0 1 16'1000000010000000).
+ Merging pattern 24'--101111---------------- and 24'--101101---------------- from group (0 1 16'1000000010000000).
+ Merging pattern 24'--111111---------------- and 24'--111101---------------- from group (0 1 16'1000000010000000).
+ Merging pattern 24'--1101-1---------------- and 24'--1111-1---------------- from group (0 1 16'1000000010000000).
+ Merging pattern 24'--1111-1---------------- and 24'--1101-1---------------- from group (0 1 16'1000000010000000).
+ Merging pattern 24'--11-1-0---------------- and 24'--11-1-1---------------- from group (0 1 16'1000000010000000).
+ Merging pattern 24'--11-1-1---------------- and 24'--11-1-0---------------- from group (0 1 16'1000000010000000).
+ Merging pattern 24'--010101------00--1-1--- and 24'--010111------00--1-1--- from group (1 1 16'0000000010000001).
+ Merging pattern 24'--001101------00--1-1--- and 24'--001111------00--1-1--- from group (1 1 16'0000000010000001).
+ Merging pattern 24'--011101------00--1-1--- and 24'--011111------00--1-1--- from group (1 1 16'0000000010000001).
+ Merging pattern 24'--010111------00--1-1--- and 24'--010101------00--1-1--- from group (1 1 16'0000000010000001).
+ Merging pattern 24'--001111------00--1-1--- and 24'--001101------00--1-1--- from group (1 1 16'0000000010000001).
+ Merging pattern 24'--011111------00--1-1--- and 24'--011101------00--1-1--- from group (1 1 16'0000000010000001).
+ Merging pattern 24'--010101------00--0----- and 24'--010111------00--0----- from group (1 1 16'0000000010000001).
+ Merging pattern 24'--001101------00--0----- and 24'--001111------00--0----- from group (1 1 16'0000000010000001).
+ Merging pattern 24'--011101------00--0----- and 24'--011111------00--0----- from group (1 1 16'0000000010000001).
+ Merging pattern 24'--010111------00--0----- and 24'--010101------00--0----- from group (1 1 16'0000000010000001).
+ Merging pattern 24'--001111------00--0----- and 24'--001101------00--0----- from group (1 1 16'0000000010000001).
+ Merging pattern 24'--011111------00--0----- and 24'--011101------00--0----- from group (1 1 16'0000000010000001).
+ Merging pattern 24'--010101------10-------- and 24'--010111------10-------- from group (1 1 16'0000000010000001).
+ Merging pattern 24'--001101------10-------- and 24'--001111------10-------- from group (1 1 16'0000000010000001).
+ Merging pattern 24'--011101------10-------- and 24'--011111------10-------- from group (1 1 16'0000000010000001).
+ Merging pattern 24'--010111------10-------- and 24'--010101------10-------- from group (1 1 16'0000000010000001).
+ Merging pattern 24'--001111------10-------- and 24'--001101------10-------- from group (1 1 16'0000000010000001).
+ Merging pattern 24'--011111------10-------- and 24'--011101------10-------- from group (1 1 16'0000000010000001).
+ Merging pattern 24'--010101-------1-------- and 24'--010111-------1-------- from group (1 1 16'0000000010000001).
+ Merging pattern 24'--001101-------1-------- and 24'--001111-------1-------- from group (1 1 16'0000000010000001).
+ Merging pattern 24'--011101-------1-------- and 24'--011111-------1-------- from group (1 1 16'0000000010000001).
+ Merging pattern 24'--010111-------1-------- and 24'--010101-------1-------- from group (1 1 16'0000000010000001).
+ Merging pattern 24'--001111-------1-------- and 24'--001101-------1-------- from group (1 1 16'0000000010000001).
+ Merging pattern 24'--011111-------1-------- and 24'--011101-------1-------- from group (1 1 16'0000000010000001).
+ Merging pattern 24'--110101---------------- and 24'--110111---------------- from group (1 1 16'0000000010000001).
+ Merging pattern 24'--101101---------------- and 24'--101111---------------- from group (1 1 16'0000000010000001).
+ Merging pattern 24'--111101---------------- and 24'--111111---------------- from group (1 1 16'0000000010000001).
+ Merging pattern 24'--110111---------------- and 24'--110101---------------- from group (1 1 16'0000000010000001).
+ Merging pattern 24'--101111---------------- and 24'--101101---------------- from group (1 1 16'0000000010000001).
+ Merging pattern 24'--111111---------------- and 24'--111101---------------- from group (1 1 16'0000000010000001).
+ Merging pattern 24'--0101-1------00--1-1--- and 24'--0111-1------00--1-1--- from group (1 1 16'0000000010000001).
+ Merging pattern 24'--0111-1------00--1-1--- and 24'--0101-1------00--1-1--- from group (1 1 16'0000000010000001).
+ Merging pattern 24'--0101-1------00--0----- and 24'--0111-1------00--0----- from group (1 1 16'0000000010000001).
+ Merging pattern 24'--0111-1------00--0----- and 24'--0101-1------00--0----- from group (1 1 16'0000000010000001).
+ Merging pattern 24'--0101-1------10-------- and 24'--0111-1------10-------- from group (1 1 16'0000000010000001).
+ Merging pattern 24'--0111-1------10-------- and 24'--0101-1------10-------- from group (1 1 16'0000000010000001).
+ Merging pattern 24'--0101-1-------1-------- and 24'--0111-1-------1-------- from group (1 1 16'0000000010000001).
+ Merging pattern 24'--0111-1-------1-------- and 24'--0101-1-------1-------- from group (1 1 16'0000000010000001).
+ Merging pattern 24'--1101-1---------------- and 24'--1111-1---------------- from group (1 1 16'0000000010000001).
+ Merging pattern 24'--1111-1---------------- and 24'--1101-1---------------- from group (1 1 16'0000000010000001).
+ Merging pattern 24'--01-1-0------00--1-1--- and 24'--01-1-1------00--1-1--- from group (1 1 16'0000000010000001).
+ Merging pattern 24'--01-1-1------00--1-1--- and 24'--01-1-0------00--1-1--- from group (1 1 16'0000000010000001).
+ Merging pattern 24'--01-1-0------00--0----- and 24'--01-1-1------00--0----- from group (1 1 16'0000000010000001).
+ Merging pattern 24'--01-1-1------00--0----- and 24'--01-1-0------00--0----- from group (1 1 16'0000000010000001).
+ Merging pattern 24'--01-1-0------10-------- and 24'--01-1-1------10-------- from group (1 1 16'0000000010000001).
+ Merging pattern 24'--01-1-1------10-------- and 24'--01-1-0------10-------- from group (1 1 16'0000000010000001).
+ Merging pattern 24'--01-1-0-------1-------- and 24'--01-1-1-------1-------- from group (1 1 16'0000000010000001).
+ Merging pattern 24'--01-1-1-------1-------- and 24'--01-1-0-------1-------- from group (1 1 16'0000000010000001).
+ Merging pattern 24'--11-1-0---------------- and 24'--11-1-1---------------- from group (1 1 16'0000000010000001).
+ Merging pattern 24'--11-1-1---------------- and 24'--11-1-0---------------- from group (1 1 16'0000000010000001).
+ Merging pattern 24'--010101------00--1-0--- and 24'--010111------00--1-0--- from group (1 2 16'0000000001000001).
+ Merging pattern 24'--001101------00--1-0--- and 24'--001111------00--1-0--- from group (1 2 16'0000000001000001).
+ Merging pattern 24'--011101------00--1-0--- and 24'--011111------00--1-0--- from group (1 2 16'0000000001000001).
+ Merging pattern 24'--010111------00--1-0--- and 24'--010101------00--1-0--- from group (1 2 16'0000000001000001).
+ Merging pattern 24'--001111------00--1-0--- and 24'--001101------00--1-0--- from group (1 2 16'0000000001000001).
+ Merging pattern 24'--011111------00--1-0--- and 24'--011101------00--1-0--- from group (1 2 16'0000000001000001).
+ Merging pattern 24'--0101-1------00--1-0--- and 24'--0111-1------00--1-0--- from group (1 2 16'0000000001000001).
+ Merging pattern 24'--0111-1------00--1-0--- and 24'--0101-1------00--1-0--- from group (1 2 16'0000000001000001).
+ Merging pattern 24'--01-1-0------00--1-0--- and 24'--01-1-1------00--1-0--- from group (1 2 16'0000000001000001).
+ Merging pattern 24'--01-1-1------00--1-0--- and 24'--01-1-0------00--1-0--- from group (1 2 16'0000000001000001).
+ Merging pattern 24'--010101----01-----1--0- and 24'--010111----01-----1--0- from group (2 0 16'0100000100000000).
+ Merging pattern 24'--001101----01-----1--0- and 24'--001111----01-----1--0- from group (2 0 16'0100000100000000).
+ Merging pattern 24'--011101----01-----1--0- and 24'--011111----01-----1--0- from group (2 0 16'0100000100000000).
+ Merging pattern 24'--010111----01-----1--0- and 24'--010101----01-----1--0- from group (2 0 16'0100000100000000).
+ Merging pattern 24'--001111----01-----1--0- and 24'--001101----01-----1--0- from group (2 0 16'0100000100000000).
+ Merging pattern 24'--011111----01-----1--0- and 24'--011101----01-----1--0- from group (2 0 16'0100000100000000).
+ Merging pattern 24'--0101-1----01-----1--0- and 24'--0111-1----01-----1--0- from group (2 0 16'0100000100000000).
+ Merging pattern 24'--0111-1----01-----1--0- and 24'--0101-1----01-----1--0- from group (2 0 16'0100000100000000).
+ Merging pattern 24'--01-1-0----01-----1--0- and 24'--01-1-1----01-----1--0- from group (2 0 16'0100000100000000).
+ Merging pattern 24'--01-1-1----01-----1--0- and 24'--01-1-0----01-----1--0- from group (2 0 16'0100000100000000).
+ Merging pattern 24'--010101----11-----1--0- and 24'--010111----11-----1--0- from group (2 1 16'0100000010000000).
+ Merging pattern 24'--001101----11-----1--0- and 24'--001111----11-----1--0- from group (2 1 16'0100000010000000).
+ Merging pattern 24'--011101----11-----1--0- and 24'--011111----11-----1--0- from group (2 1 16'0100000010000000).
+ Merging pattern 24'--010111----11-----1--0- and 24'--010101----11-----1--0- from group (2 1 16'0100000010000000).
+ Merging pattern 24'--001111----11-----1--0- and 24'--001101----11-----1--0- from group (2 1 16'0100000010000000).
+ Merging pattern 24'--011111----11-----1--0- and 24'--011101----11-----1--0- from group (2 1 16'0100000010000000).
+ Merging pattern 24'--010101-----------1--1- and 24'--010111-----------1--1- from group (2 1 16'0100000010000000).
+ Merging pattern 24'--001101-----------1--1- and 24'--001111-----------1--1- from group (2 1 16'0100000010000000).
+ Merging pattern 24'--011101-----------1--1- and 24'--011111-----------1--1- from group (2 1 16'0100000010000000).
+ Merging pattern 24'--010111-----------1--1- and 24'--010101-----------1--1- from group (2 1 16'0100000010000000).
+ Merging pattern 24'--001111-----------1--1- and 24'--001101-----------1--1- from group (2 1 16'0100000010000000).
+ Merging pattern 24'--011111-----------1--1- and 24'--011101-----------1--1- from group (2 1 16'0100000010000000).
+ Merging pattern 24'1-010101---------------- and 24'1-010111---------------- from group (2 1 16'0100000010000000).
+ Merging pattern 24'--110101---------------- and 24'--110111---------------- from group (2 1 16'0100000010000000).
+ Merging pattern 24'1-001101---------------- and 24'1-001111---------------- from group (2 1 16'0100000010000000).
+ Merging pattern 24'--101101---------------- and 24'--101111---------------- from group (2 1 16'0100000010000000).
+ Merging pattern 24'1-011101---------------- and 24'1-011111---------------- from group (2 1 16'0100000010000000).
+ Merging pattern 24'--111101---------------- and 24'--111111---------------- from group (2 1 16'0100000010000000).
+ Merging pattern 24'1-010111---------------- and 24'1-010101---------------- from group (2 1 16'0100000010000000).
+ Merging pattern 24'--110111---------------- and 24'--110101---------------- from group (2 1 16'0100000010000000).
+ Merging pattern 24'1-001111---------------- and 24'1-001101---------------- from group (2 1 16'0100000010000000).
+ Merging pattern 24'--101111---------------- and 24'--101101---------------- from group (2 1 16'0100000010000000).
+ Merging pattern 24'1-011111---------------- and 24'1-011101---------------- from group (2 1 16'0100000010000000).
+ Merging pattern 24'--111111---------------- and 24'--111101---------------- from group (2 1 16'0100000010000000).
+ Merging pattern 24'--0101-1----11-----1--0- and 24'--0111-1----11-----1--0- from group (2 1 16'0100000010000000).
+ Merging pattern 24'--0111-1----11-----1--0- and 24'--0101-1----11-----1--0- from group (2 1 16'0100000010000000).
+ Merging pattern 24'--0101-1-----------1--1- and 24'--0111-1-----------1--1- from group (2 1 16'0100000010000000).
+ Merging pattern 24'--0111-1-----------1--1- and 24'--0101-1-----------1--1- from group (2 1 16'0100000010000000).
+ Merging pattern 24'1-0101-1---------------- and 24'1-0111-1---------------- from group (2 1 16'0100000010000000).
+ Merging pattern 24'--1101-1---------------- and 24'--1111-1---------------- from group (2 1 16'0100000010000000).
+ Merging pattern 24'1-0111-1---------------- and 24'1-0101-1---------------- from group (2 1 16'0100000010000000).
+ Merging pattern 24'--1111-1---------------- and 24'--1101-1---------------- from group (2 1 16'0100000010000000).
+ Merging pattern 24'--01-1-0----11-----1--0- and 24'--01-1-1----11-----1--0- from group (2 1 16'0100000010000000).
+ Merging pattern 24'--01-1-1----11-----1--0- and 24'--01-1-0----11-----1--0- from group (2 1 16'0100000010000000).
+ Merging pattern 24'--01-1-0-----------1--1- and 24'--01-1-1-----------1--1- from group (2 1 16'0100000010000000).
+ Merging pattern 24'--01-1-1-----------1--1- and 24'--01-1-0-----------1--1- from group (2 1 16'0100000010000000).
+ Merging pattern 24'1-01-1-0---------------- and 24'1-01-1-1---------------- from group (2 1 16'0100000010000000).
+ Merging pattern 24'--11-1-0---------------- and 24'--11-1-1---------------- from group (2 1 16'0100000010000000).
+ Merging pattern 24'1-01-1-1---------------- and 24'1-01-1-0---------------- from group (2 1 16'0100000010000000).
+ Merging pattern 24'--11-1-1---------------- and 24'--11-1-0---------------- from group (2 1 16'0100000010000000).
+ Merging pattern 24'--010101-----0-----1--0- and 24'--010111-----0-----1--0- from group (2 2 16'0100000001000000).
+ Merging pattern 24'--001101-----0-----1--0- and 24'--001111-----0-----1--0- from group (2 2 16'0100000001000000).
+ Merging pattern 24'--011101-----0-----1--0- and 24'--011111-----0-----1--0- from group (2 2 16'0100000001000000).
+ Merging pattern 24'--010111-----0-----1--0- and 24'--010101-----0-----1--0- from group (2 2 16'0100000001000000).
+ Merging pattern 24'--001111-----0-----1--0- and 24'--001101-----0-----1--0- from group (2 2 16'0100000001000000).
+ Merging pattern 24'--011111-----0-----1--0- and 24'--011101-----0-----1--0- from group (2 2 16'0100000001000000).
+ Merging pattern 24'--0101-1-----0-----1--0- and 24'--0111-1-----0-----1--0- from group (2 2 16'0100000001000000).
+ Merging pattern 24'--0111-1-----0-----1--0- and 24'--0101-1-----0-----1--0- from group (2 2 16'0100000001000000).
+ Merging pattern 24'--01-1-0-----0-----1--0- and 24'--01-1-1-----0-----1--0- from group (2 2 16'0100000001000000).
+ Merging pattern 24'--01-1-1-----0-----1--0- and 24'--01-1-0-----0-----1--0- from group (2 2 16'0100000001000000).
+ Merging pattern 24'00010101---0-----0-0---- and 24'00010111---0-----0-0---- from group (2 3 16'0100000000010000).
+ Merging pattern 24'00001101---0-----0-0---- and 24'00001111---0-----0-0---- from group (2 3 16'0100000000010000).
+ Merging pattern 24'00011101---0-----0-0---- and 24'00011111---0-----0-0---- from group (2 3 16'0100000000010000).
+ Merging pattern 24'00010111---0-----0-0---- and 24'00010101---0-----0-0---- from group (2 3 16'0100000000010000).
+ Merging pattern 24'00001111---0-----0-0---- and 24'00001101---0-----0-0---- from group (2 3 16'0100000000010000).
+ Merging pattern 24'00011111---0-----0-0---- and 24'00011101---0-----0-0---- from group (2 3 16'0100000000010000).
+ Merging pattern 24'-1010101---------------- and 24'-1010111---------------- from group (2 3 16'0100000000010000).
+ Merging pattern 24'-1001101---------------- and 24'-1001111---------------- from group (2 3 16'0100000000010000).
+ Merging pattern 24'-1011101---------------- and 24'-1011111---------------- from group (2 3 16'0100000000010000).
+ Merging pattern 24'-1010111---------------- and 24'-1010101---------------- from group (2 3 16'0100000000010000).
+ Merging pattern 24'-1001111---------------- and 24'-1001101---------------- from group (2 3 16'0100000000010000).
+ Merging pattern 24'-1011111---------------- and 24'-1011101---------------- from group (2 3 16'0100000000010000).
+ Merging pattern 24'000101-1---0-----0-0---- and 24'000111-1---0-----0-0---- from group (2 3 16'0100000000010000).
+ Merging pattern 24'000111-1---0-----0-0---- and 24'000101-1---0-----0-0---- from group (2 3 16'0100000000010000).
+ Merging pattern 24'-10101-1---------------- and 24'-10111-1---------------- from group (2 3 16'0100000000010000).
+ Merging pattern 24'-10111-1---------------- and 24'-10101-1---------------- from group (2 3 16'0100000000010000).
+ Merging pattern 24'0001-1-0---0-----0-0---- and 24'0001-1-1---0-----0-0---- from group (2 3 16'0100000000010000).
+ Merging pattern 24'0001-1-1---0-----0-0---- and 24'0001-1-0---0-----0-0---- from group (2 3 16'0100000000010000).
+ Merging pattern 24'-101-1-0---------------- and 24'-101-1-1---------------- from group (2 3 16'0100000000010000).
+ Merging pattern 24'-101-1-1---------------- and 24'-101-1-0---------------- from group (2 3 16'0100000000010000).
+ Merging pattern 24'00010101---0-----1------ and 24'00010111---0-----1------ from group (2 4 16'0100000000000100).
+ Merging pattern 24'00001101---0-----1------ and 24'00001111---0-----1------ from group (2 4 16'0100000000000100).
+ Merging pattern 24'00011101---0-----1------ and 24'00011111---0-----1------ from group (2 4 16'0100000000000100).
+ Merging pattern 24'00010111---0-----1------ and 24'00010101---0-----1------ from group (2 4 16'0100000000000100).
+ Merging pattern 24'00001111---0-----1------ and 24'00001101---0-----1------ from group (2 4 16'0100000000000100).
+ Merging pattern 24'00011111---0-----1------ and 24'00011101---0-----1------ from group (2 4 16'0100000000000100).
+ Merging pattern 24'000101-1---0-----1------ and 24'000111-1---0-----1------ from group (2 4 16'0100000000000100).
+ Merging pattern 24'000111-1---0-----1------ and 24'000101-1---0-----1------ from group (2 4 16'0100000000000100).
+ Merging pattern 24'0001-1-0---0-----1------ and 24'0001-1-1---0-----1------ from group (2 4 16'0100000000000100).
+ Merging pattern 24'0001-1-1---0-----1------ and 24'0001-1-0---0-----1------ from group (2 4 16'0100000000000100).
+ Merging pattern 24'--010101---1------------ and 24'--010111---1------------ from group (2 5 16'0100000000000010).
+ Merging pattern 24'--001101---1------------ and 24'--001111---1------------ from group (2 5 16'0100000000000010).
+ Merging pattern 24'--011101---1------------ and 24'--011111---1------------ from group (2 5 16'0100000000000010).
+ Merging pattern 24'--010111---1------------ and 24'--010101---1------------ from group (2 5 16'0100000000000010).
+ Merging pattern 24'--001111---1------------ and 24'--001101---1------------ from group (2 5 16'0100000000000010).
+ Merging pattern 24'--011111---1------------ and 24'--011101---1------------ from group (2 5 16'0100000000000010).
+ Merging pattern 24'--0101-1---1------------ and 24'--0111-1---1------------ from group (2 5 16'0100000000000010).
+ Merging pattern 24'--0111-1---1------------ and 24'--0101-1---1------------ from group (2 5 16'0100000000000010).
+ Merging pattern 24'--01-1-0---1------------ and 24'--01-1-1---1------------ from group (2 5 16'0100000000000010).
+ Merging pattern 24'--01-1-1---1------------ and 24'--01-1-0---1------------ from group (2 5 16'0100000000000010).
+ Merging pattern 24'--010101--------1----1-- and 24'--010111--------1----1-- from group (3 1 16'0001000010000000).
+ Merging pattern 24'--001101--------1----1-- and 24'--001111--------1----1-- from group (3 1 16'0001000010000000).
+ Merging pattern 24'--011101--------1----1-- and 24'--011111--------1----1-- from group (3 1 16'0001000010000000).
+ Merging pattern 24'--010111--------1----1-- and 24'--010101--------1----1-- from group (3 1 16'0001000010000000).
+ Merging pattern 24'--001111--------1----1-- and 24'--001101--------1----1-- from group (3 1 16'0001000010000000).
+ Merging pattern 24'--011111--------1----1-- and 24'--011101--------1----1-- from group (3 1 16'0001000010000000).
+ Merging pattern 24'--010101--------0------- and 24'--010111--------0------- from group (3 1 16'0001000010000000).
+ Merging pattern 24'--001101--------0------- and 24'--001111--------0------- from group (3 1 16'0001000010000000).
+ Merging pattern 24'--011101--------0------- and 24'--011111--------0------- from group (3 1 16'0001000010000000).
+ Merging pattern 24'--010111--------0------- and 24'--010101--------0------- from group (3 1 16'0001000010000000).
+ Merging pattern 24'--001111--------0------- and 24'--001101--------0------- from group (3 1 16'0001000010000000).
+ Merging pattern 24'--011111--------0------- and 24'--011101--------0------- from group (3 1 16'0001000010000000).
+ Merging pattern 24'--110101---------------- and 24'--110111---------------- from group (3 1 16'0001000010000000).
+ Merging pattern 24'--101101---------------- and 24'--101111---------------- from group (3 1 16'0001000010000000).
+ Merging pattern 24'--111101---------------- and 24'--111111---------------- from group (3 1 16'0001000010000000).
+ Merging pattern 24'--110111---------------- and 24'--110101---------------- from group (3 1 16'0001000010000000).
+ Merging pattern 24'--101111---------------- and 24'--101101---------------- from group (3 1 16'0001000010000000).
+ Merging pattern 24'--111111---------------- and 24'--111101---------------- from group (3 1 16'0001000010000000).
+ Merging pattern 24'--0101-1--------1----1-- and 24'--0111-1--------1----1-- from group (3 1 16'0001000010000000).
+ Merging pattern 24'--0111-1--------1----1-- and 24'--0101-1--------1----1-- from group (3 1 16'0001000010000000).
+ Merging pattern 24'--0101-1--------0------- and 24'--0111-1--------0------- from group (3 1 16'0001000010000000).
+ Merging pattern 24'--0111-1--------0------- and 24'--0101-1--------0------- from group (3 1 16'0001000010000000).
+ Merging pattern 24'--1101-1---------------- and 24'--1111-1---------------- from group (3 1 16'0001000010000000).
+ Merging pattern 24'--1111-1---------------- and 24'--1101-1---------------- from group (3 1 16'0001000010000000).
+ Merging pattern 24'--01-1-0--------1----1-- and 24'--01-1-1--------1----1-- from group (3 1 16'0001000010000000).
+ Merging pattern 24'--01-1-1--------1----1-- and 24'--01-1-0--------1----1-- from group (3 1 16'0001000010000000).
+ Merging pattern 24'--01-1-0--------0------- and 24'--01-1-1--------0------- from group (3 1 16'0001000010000000).
+ Merging pattern 24'--01-1-1--------0------- and 24'--01-1-0--------0------- from group (3 1 16'0001000010000000).
+ Merging pattern 24'--11-1-0---------------- and 24'--11-1-1---------------- from group (3 1 16'0001000010000000).
+ Merging pattern 24'--11-1-1---------------- and 24'--11-1-0---------------- from group (3 1 16'0001000010000000).
+ Merging pattern 24'--010101--------1----0-- and 24'--010111--------1----0-- from group (3 3 16'0001000000010000).
+ Merging pattern 24'--001101--------1----0-- and 24'--001111--------1----0-- from group (3 3 16'0001000000010000).
+ Merging pattern 24'--011101--------1----0-- and 24'--011111--------1----0-- from group (3 3 16'0001000000010000).
+ Merging pattern 24'--010111--------1----0-- and 24'--010101--------1----0-- from group (3 3 16'0001000000010000).
+ Merging pattern 24'--001111--------1----0-- and 24'--001101--------1----0-- from group (3 3 16'0001000000010000).
+ Merging pattern 24'--011111--------1----0-- and 24'--011101--------1----0-- from group (3 3 16'0001000000010000).
+ Merging pattern 24'--0101-1--------1----0-- and 24'--0111-1--------1----0-- from group (3 3 16'0001000000010000).
+ Merging pattern 24'--0111-1--------1----0-- and 24'--0101-1--------1----0-- from group (3 3 16'0001000000010000).
+ Merging pattern 24'--01-1-0--------1----0-- and 24'--01-1-1--------1----0-- from group (3 3 16'0001000000010000).
+ Merging pattern 24'--01-1-1--------1----0-- and 24'--01-1-0--------1----0-- from group (3 3 16'0001000000010000).
+ Merging pattern 24'--01010111-------------- and 24'--01011111-------------- from group (4 1 16'0000010010000000).
+ Merging pattern 24'--00110111-------------- and 24'--00111111-------------- from group (4 1 16'0000010010000000).
+ Merging pattern 24'--01110111-------------- and 24'--01111111-------------- from group (4 1 16'0000010010000000).
+ Merging pattern 24'--01011111-------------- and 24'--01010111-------------- from group (4 1 16'0000010010000000).
+ Merging pattern 24'--00111111-------------- and 24'--00110111-------------- from group (4 1 16'0000010010000000).
+ Merging pattern 24'--01111111-------------- and 24'--01110111-------------- from group (4 1 16'0000010010000000).
+ Merging pattern 24'--110101---------------- and 24'--110111---------------- from group (4 1 16'0000010010000000).
+ Merging pattern 24'--101101---------------- and 24'--101111---------------- from group (4 1 16'0000010010000000).
+ Merging pattern 24'--111101---------------- and 24'--111111---------------- from group (4 1 16'0000010010000000).
+ Merging pattern 24'--110111---------------- and 24'--110101---------------- from group (4 1 16'0000010010000000).
+ Merging pattern 24'--101111---------------- and 24'--101101---------------- from group (4 1 16'0000010010000000).
+ Merging pattern 24'--111111---------------- and 24'--111101---------------- from group (4 1 16'0000010010000000).
+ Merging pattern 24'--0101-111-------------- and 24'--0111-111-------------- from group (4 1 16'0000010010000000).
+ Merging pattern 24'--0111-111-------------- and 24'--0101-111-------------- from group (4 1 16'0000010010000000).
+ Merging pattern 24'--1101-1---------------- and 24'--1111-1---------------- from group (4 1 16'0000010010000000).
+ Merging pattern 24'--1111-1---------------- and 24'--1101-1---------------- from group (4 1 16'0000010010000000).
+ Merging pattern 24'--01-1-011-------------- and 24'--01-1-111-------------- from group (4 1 16'0000010010000000).
+ Merging pattern 24'--01-1-111-------------- and 24'--01-1-011-------------- from group (4 1 16'0000010010000000).
+ Merging pattern 24'--11-1-0---------------- and 24'--11-1-1---------------- from group (4 1 16'0000010010000000).
+ Merging pattern 24'--11-1-1---------------- and 24'--11-1-0---------------- from group (4 1 16'0000010010000000).
+ Merging pattern 24'--010101-0-------------- and 24'--010111-0-------------- from group (4 4 16'0000010000000100).
+ Merging pattern 24'--001101-0-------------- and 24'--001111-0-------------- from group (4 4 16'0000010000000100).
+ Merging pattern 24'--011101-0-------------- and 24'--011111-0-------------- from group (4 4 16'0000010000000100).
+ Merging pattern 24'--010111-0-------------- and 24'--010101-0-------------- from group (4 4 16'0000010000000100).
+ Merging pattern 24'--001111-0-------------- and 24'--001101-0-------------- from group (4 4 16'0000010000000100).
+ Merging pattern 24'--011111-0-------------- and 24'--011101-0-------------- from group (4 4 16'0000010000000100).
+ Merging pattern 24'--01010101-------------- and 24'--01011101-------------- from group (4 4 16'0000010000000100).
+ Merging pattern 24'--00110101-------------- and 24'--00111101-------------- from group (4 4 16'0000010000000100).
+ Merging pattern 24'--01110101-------------- and 24'--01111101-------------- from group (4 4 16'0000010000000100).
+ Merging pattern 24'--01011101-------------- and 24'--01010101-------------- from group (4 4 16'0000010000000100).
+ Merging pattern 24'--00111101-------------- and 24'--00110101-------------- from group (4 4 16'0000010000000100).
+ Merging pattern 24'--01111101-------------- and 24'--01110101-------------- from group (4 4 16'0000010000000100).
+ Merging pattern 24'--0101-1-0-------------- and 24'--0111-1-0-------------- from group (4 4 16'0000010000000100).
+ Merging pattern 24'--0111-1-0-------------- and 24'--0101-1-0-------------- from group (4 4 16'0000010000000100).
+ Merging pattern 24'--0101-101-------------- and 24'--0111-101-------------- from group (4 4 16'0000010000000100).
+ Merging pattern 24'--0111-101-------------- and 24'--0101-101-------------- from group (4 4 16'0000010000000100).
+ Merging pattern 24'--01-1-0-0-------------- and 24'--01-1-1-0-------------- from group (4 4 16'0000010000000100).
+ Merging pattern 24'--01-1-1-0-------------- and 24'--01-1-0-0-------------- from group (4 4 16'0000010000000100).
+ Merging pattern 24'--01-1-001-------------- and 24'--01-1-101-------------- from group (4 4 16'0000010000000100).
+ Merging pattern 24'--01-1-101-------------- and 24'--01-1-001-------------- from group (4 4 16'0000010000000100).
+ Merging pattern 24'--01010111-------------- and 24'--01011111-------------- from group (5 1 16'0000001010000000).
+ Merging pattern 24'--00110111-------------- and 24'--00111111-------------- from group (5 1 16'0000001010000000).
+ Merging pattern 24'--01110111-------------- and 24'--01111111-------------- from group (5 1 16'0000001010000000).
+ Merging pattern 24'--01011111-------------- and 24'--01010111-------------- from group (5 1 16'0000001010000000).
+ Merging pattern 24'--00111111-------------- and 24'--00110111-------------- from group (5 1 16'0000001010000000).
+ Merging pattern 24'--01111111-------------- and 24'--01110111-------------- from group (5 1 16'0000001010000000).
+ Merging pattern 24'--110101---------------- and 24'--110111---------------- from group (5 1 16'0000001010000000).
+ Merging pattern 24'--101101---------------- and 24'--101111---------------- from group (5 1 16'0000001010000000).
+ Merging pattern 24'--111101---------------- and 24'--111111---------------- from group (5 1 16'0000001010000000).
+ Merging pattern 24'--110111---------------- and 24'--110101---------------- from group (5 1 16'0000001010000000).
+ Merging pattern 24'--101111---------------- and 24'--101101---------------- from group (5 1 16'0000001010000000).
+ Merging pattern 24'--111111---------------- and 24'--111101---------------- from group (5 1 16'0000001010000000).
+ Merging pattern 24'--0101-111-------------- and 24'--0111-111-------------- from group (5 1 16'0000001010000000).
+ Merging pattern 24'--0111-111-------------- and 24'--0101-111-------------- from group (5 1 16'0000001010000000).
+ Merging pattern 24'--1101-1---------------- and 24'--1111-1---------------- from group (5 1 16'0000001010000000).
+ Merging pattern 24'--1111-1---------------- and 24'--1101-1---------------- from group (5 1 16'0000001010000000).
+ Merging pattern 24'--01-1-011-------------- and 24'--01-1-111-------------- from group (5 1 16'0000001010000000).
+ Merging pattern 24'--01-1-111-------------- and 24'--01-1-011-------------- from group (5 1 16'0000001010000000).
+ Merging pattern 24'--11-1-0---------------- and 24'--11-1-1---------------- from group (5 1 16'0000001010000000).
+ Merging pattern 24'--11-1-1---------------- and 24'--11-1-0---------------- from group (5 1 16'0000001010000000).
+ Merging pattern 24'--010101-0-------------- and 24'--010111-0-------------- from group (5 5 16'0000001000000010).
+ Merging pattern 24'--001101-0-------------- and 24'--001111-0-------------- from group (5 5 16'0000001000000010).
+ Merging pattern 24'--011101-0-------------- and 24'--011111-0-------------- from group (5 5 16'0000001000000010).
+ Merging pattern 24'--010111-0-------------- and 24'--010101-0-------------- from group (5 5 16'0000001000000010).
+ Merging pattern 24'--001111-0-------------- and 24'--001101-0-------------- from group (5 5 16'0000001000000010).
+ Merging pattern 24'--011111-0-------------- and 24'--011101-0-------------- from group (5 5 16'0000001000000010).
+ Merging pattern 24'--01010101-------------- and 24'--01011101-------------- from group (5 5 16'0000001000000010).
+ Merging pattern 24'--00110101-------------- and 24'--00111101-------------- from group (5 5 16'0000001000000010).
+ Merging pattern 24'--01110101-------------- and 24'--01111101-------------- from group (5 5 16'0000001000000010).
+ Merging pattern 24'--01011101-------------- and 24'--01010101-------------- from group (5 5 16'0000001000000010).
+ Merging pattern 24'--00111101-------------- and 24'--00110101-------------- from group (5 5 16'0000001000000010).
+ Merging pattern 24'--01111101-------------- and 24'--01110101-------------- from group (5 5 16'0000001000000010).
+ Merging pattern 24'--0101-1-0-------------- and 24'--0111-1-0-------------- from group (5 5 16'0000001000000010).
+ Merging pattern 24'--0111-1-0-------------- and 24'--0101-1-0-------------- from group (5 5 16'0000001000000010).
+ Merging pattern 24'--0101-101-------------- and 24'--0111-101-------------- from group (5 5 16'0000001000000010).
+ Merging pattern 24'--0111-101-------------- and 24'--0101-101-------------- from group (5 5 16'0000001000000010).
+ Merging pattern 24'--01-1-0-0-------------- and 24'--01-1-1-0-------------- from group (5 5 16'0000001000000010).
+ Merging pattern 24'--01-1-1-0-------------- and 24'--01-1-0-0-------------- from group (5 5 16'0000001000000010).
+ Merging pattern 24'--01-1-001-------------- and 24'--01-1-101-------------- from group (5 5 16'0000001000000010).
+ Merging pattern 24'--01-1-101-------------- and 24'--01-1-001-------------- from group (5 5 16'0000001000000010).
+ Removing unused input signal $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$eq$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1826$4786_Y.
+ Removing unused input signal $auto$opt_reduce.cc:134:opt_mux$17175.
+
+23.8.4. Executing OPT_CLEAN pass (remove unused cells and wires).
+Finding unused cells or wires in module \user_proj_example..
+Removed 192 unused cells and 192 unused wires.
+<suppressed ~193 debug messages>
+
+23.8.5. Executing FSM_OPT pass (simple optimizations of FSMs).
+Optimizing FSM `$fsm$\softshell.cpus[0].core.cpu.picorv32_core.cpu_state$17218' from module `\user_proj_example'.
+ Removing unused output signal $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$0\cpu_state[7:0] [0].
+ Removing unused output signal $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$0\cpu_state[7:0] [1].
+ Removing unused output signal $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$0\cpu_state[7:0] [2].
+ Removing unused output signal $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$0\cpu_state[7:0] [3].
+ Removing unused output signal $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$0\cpu_state[7:0] [4].
+ Removing unused output signal $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$0\cpu_state[7:0] [5].
+ Removing unused output signal $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$0\cpu_state[7:0] [6].
+ Removing unused output signal $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$0\cpu_state[7:0] [7].
+Optimizing FSM `$fsm$\softshell.cpus[0].core.cpu.picorv32_core.mem_wordsize$17228' from module `\user_proj_example'.
+ Removing unused output signal $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$0\mem_wordsize[1:0] [0].
+ Removing unused output signal $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$0\mem_wordsize[1:0] [1].
+Optimizing FSM `$fsm$\softshell.cpus[0].core.cpu.state$17233' from module `\user_proj_example'.
+ Removing unused output signal $flatten\softshell.\cpus[0].core.\cpu.$0\state[1:0] [0].
+ Removing unused output signal $flatten\softshell.\cpus[0].core.\cpu.$0\state[1:0] [1].
+Optimizing FSM `$fsm$\softshell.cpus[1].core.cpu.picorv32_core.cpu_state$17238' from module `\user_proj_example'.
+ Removing unused output signal $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$0\cpu_state[7:0] [0].
+ Removing unused output signal $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$0\cpu_state[7:0] [1].
+ Removing unused output signal $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$0\cpu_state[7:0] [2].
+ Removing unused output signal $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$0\cpu_state[7:0] [3].
+ Removing unused output signal $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$0\cpu_state[7:0] [4].
+ Removing unused output signal $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$0\cpu_state[7:0] [5].
+ Removing unused output signal $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$0\cpu_state[7:0] [6].
+ Removing unused output signal $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$0\cpu_state[7:0] [7].
+Optimizing FSM `$fsm$\softshell.cpus[1].core.cpu.picorv32_core.mem_wordsize$17248' from module `\user_proj_example'.
+ Removing unused output signal $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$0\mem_wordsize[1:0] [0].
+ Removing unused output signal $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$0\mem_wordsize[1:0] [1].
+Optimizing FSM `$fsm$\softshell.cpus[1].core.cpu.state$17253' from module `\user_proj_example'.
+ Removing unused output signal $flatten\softshell.\cpus[1].core.\cpu.$0\state[1:0] [0].
+ Removing unused output signal $flatten\softshell.\cpus[1].core.\cpu.$0\state[1:0] [1].
+Optimizing FSM `$fsm$\softshell.cpus[2].core.cpu.picorv32_core.cpu_state$17258' from module `\user_proj_example'.
+ Removing unused output signal $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$0\cpu_state[7:0] [0].
+ Removing unused output signal $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$0\cpu_state[7:0] [1].
+ Removing unused output signal $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$0\cpu_state[7:0] [2].
+ Removing unused output signal $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$0\cpu_state[7:0] [3].
+ Removing unused output signal $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$0\cpu_state[7:0] [4].
+ Removing unused output signal $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$0\cpu_state[7:0] [5].
+ Removing unused output signal $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$0\cpu_state[7:0] [6].
+ Removing unused output signal $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$0\cpu_state[7:0] [7].
+Optimizing FSM `$fsm$\softshell.cpus[2].core.cpu.picorv32_core.mem_wordsize$17268' from module `\user_proj_example'.
+ Removing unused output signal $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$0\mem_wordsize[1:0] [0].
+ Removing unused output signal $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$0\mem_wordsize[1:0] [1].
+Optimizing FSM `$fsm$\softshell.cpus[2].core.cpu.state$17273' from module `\user_proj_example'.
+ Removing unused output signal $flatten\softshell.\cpus[2].core.\cpu.$0\state[1:0] [0].
+ Removing unused output signal $flatten\softshell.\cpus[2].core.\cpu.$0\state[1:0] [1].
+Optimizing FSM `$fsm$\softshell.flash.spimemio.state$17278' from module `\user_proj_example'.
+ Removing unused output signal $flatten\softshell.\flash.\spimemio.$0\state[3:0] [0].
+ Removing unused output signal $flatten\softshell.\flash.\spimemio.$0\state[3:0] [1].
+ Removing unused output signal $flatten\softshell.\flash.\spimemio.$0\state[3:0] [2].
+ Removing unused output signal $flatten\softshell.\flash.\spimemio.$0\state[3:0] [3].
+
+23.8.6. Executing FSM_RECODE pass (re-assigning FSM state encoding).
+Recoding FSM `$fsm$\softshell.cpus[0].core.cpu.picorv32_core.cpu_state$17218' from module `\user_proj_example' using `auto' encoding:
+ mapping auto encoding to `one-hot` for this FSM.
+ 10000000 -> -----1
+ 01000000 -> ----1-
+ 00100000 -> ---1--
+ 00001000 -> --1---
+ 00000010 -> -1----
+ 00000001 -> 1-----
+Recoding FSM `$fsm$\softshell.cpus[0].core.cpu.picorv32_core.mem_wordsize$17228' from module `\user_proj_example' using `auto' encoding:
+ mapping auto encoding to `one-hot` for this FSM.
+ 00 -> --1
+ 10 -> -1-
+ 01 -> 1--
+Recoding FSM `$fsm$\softshell.cpus[0].core.cpu.state$17233' from module `\user_proj_example' using `auto' encoding:
+ mapping auto encoding to `one-hot` for this FSM.
+ 00 -> --1
+ 10 -> -1-
+ 01 -> 1--
+Recoding FSM `$fsm$\softshell.cpus[1].core.cpu.picorv32_core.cpu_state$17238' from module `\user_proj_example' using `auto' encoding:
+ mapping auto encoding to `one-hot` for this FSM.
+ 10000000 -> -----1
+ 01000000 -> ----1-
+ 00100000 -> ---1--
+ 00001000 -> --1---
+ 00000010 -> -1----
+ 00000001 -> 1-----
+Recoding FSM `$fsm$\softshell.cpus[1].core.cpu.picorv32_core.mem_wordsize$17248' from module `\user_proj_example' using `auto' encoding:
+ mapping auto encoding to `one-hot` for this FSM.
+ 00 -> --1
+ 10 -> -1-
+ 01 -> 1--
+Recoding FSM `$fsm$\softshell.cpus[1].core.cpu.state$17253' from module `\user_proj_example' using `auto' encoding:
+ mapping auto encoding to `one-hot` for this FSM.
+ 00 -> --1
+ 10 -> -1-
+ 01 -> 1--
+Recoding FSM `$fsm$\softshell.cpus[2].core.cpu.picorv32_core.cpu_state$17258' from module `\user_proj_example' using `auto' encoding:
+ mapping auto encoding to `one-hot` for this FSM.
+ 10000000 -> -----1
+ 01000000 -> ----1-
+ 00100000 -> ---1--
+ 00001000 -> --1---
+ 00000010 -> -1----
+ 00000001 -> 1-----
+Recoding FSM `$fsm$\softshell.cpus[2].core.cpu.picorv32_core.mem_wordsize$17268' from module `\user_proj_example' using `auto' encoding:
+ mapping auto encoding to `one-hot` for this FSM.
+ 00 -> --1
+ 10 -> -1-
+ 01 -> 1--
+Recoding FSM `$fsm$\softshell.cpus[2].core.cpu.state$17273' from module `\user_proj_example' using `auto' encoding:
+ mapping auto encoding to `one-hot` for this FSM.
+ 00 -> --1
+ 10 -> -1-
+ 01 -> 1--
+Recoding FSM `$fsm$\softshell.flash.spimemio.state$17278' from module `\user_proj_example' using `auto' encoding:
+ mapping auto encoding to `one-hot` for this FSM.
+ 0000 -> ------------1
+ 1000 -> -----------1-
+ 0100 -> ----------1--
+ 1100 -> ---------1---
+ 0010 -> --------1----
+ 1010 -> -------1-----
+ 0110 -> ------1------
+ 0001 -> -----1-------
+ 1001 -> ----1--------
+ 0101 -> ---1---------
+ 0011 -> --1----------
+ 1011 -> -1-----------
+ 0111 -> 1------------
+
+23.8.7. Executing FSM_INFO pass (dumping all available information on FSM cells).
+
+FSM `$fsm$\softshell.cpus[0].core.cpu.picorv32_core.cpu_state$17218' from module `user_proj_example':
+-------------------------------------
+
+ Information on FSM $fsm$\softshell.cpus[0].core.cpu.picorv32_core.cpu_state$17218 (\softshell.cpus[0].core.cpu.picorv32_core.cpu_state):
+
+ Number of input signals: 22
+ Number of output signals: 8
+ Number of state bits: 6
+
+ Input signals:
+ 0: \softshell.cpus[0].core.flexio.pcpi_ready
+ 1: \softshell.cpus[0].core.cpu.picorv32_core.mem_done
+ 2: \softshell.cpus[0].core.cpu.picorv32_core.instr_jal
+ 3: \softshell.cpus[0].core.cpu.picorv32_core.instr_trap
+ 4: \softshell.cpus[0].core.cpu.picorv32_core.decoder_trigger
+ 5: \softshell.cpus[0].core.cpu.picorv32_core.is_sb_sh_sw
+ 6: \softshell.cpus[0].core.cpu.picorv32_core.is_beq_bne_blt_bge_bltu_bgeu
+ 7: $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1533$4719_Y
+ 8: $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1543$4727_Y
+ 9: $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1600$4740_Y
+ 10: $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1603$4744_Y
+ 11: $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1691$4758_Y
+ 12: $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$logic_or$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1852$4804_Y
+ 13: $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1867$4808_Y
+ 14: $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1917$4823_Y
+ 15: $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1918$4826_Y
+ 16: $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1920$4830_Y
+ 17: $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1925$4833_Y
+ 18: $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1933$4840_Y
+ 19: \softshell.cpus[0].core.cpu.wb_rst_i
+ 20: $auto$opt_reduce.cc:134:opt_mux$17047
+ 21: $auto$opt_reduce.cc:134:opt_mux$17041
+
+ Output signals:
+ 0: $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$eq$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1308$4645_Y
+ 1: $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$5572_CMP
+ 2: $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$5573_CMP
+ 3: $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$5574_CMP
+ 4: $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$5575_CMP
+ 5: $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$5576_CMP
+ 6: $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$5577_CMP
+ 7: $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$5579_CMP
+
+ State encoding:
+ 0: 6'-----1
+ 1: 6'----1-
+ 2: 6'---1--
+ 3: 6'--1---
+ 4: 6'-1----
+ 5: 6'1-----
+
+ Transition Table (state_in, ctrl_in, state_out, ctrl_out):
+ 0: 0 22'--00---0-------------- -> 0 8'10000000
+ 1: 0 22'--000-01-------------- -> 0 8'10000000
+ 2: 0 22'---00011-------------- -> 0 8'10000000
+ 3: 0 22'--000111-------------- -> 0 8'10000000
+ 4: 0 22'---010-1-------------- -> 0 8'10000000
+ 5: 0 22'--0011-1-------------- -> 0 8'10000000
+ 6: 0 22'---1-0---------------- -> 0 8'10000000
+ 7: 0 22'--01-1---------------- -> 0 8'10000000
+ 8: 0 22'--10---0-------------- -> 1 8'10000000
+ 9: 0 22'--100-01-------------- -> 1 8'10000000
+ 10: 0 22'--100111-------------- -> 1 8'10000000
+ 11: 0 22'--1011-1-------------- -> 1 8'10000000
+ 12: 0 22'--11-1---------------- -> 1 8'10000000
+ 13: 1 22'---00011-------------- -> 0 8'00000001
+ 14: 1 22'---010-1-------------- -> 0 8'00000001
+ 15: 1 22'---1-0---------------- -> 0 8'00000001
+ 16: 1 22'--00---0-----00--1-1-- -> 1 8'00000001
+ 17: 1 22'--000-01-----00--1-1-- -> 1 8'00000001
+ 18: 1 22'--000111-----00--1-1-- -> 1 8'00000001
+ 19: 1 22'--0011-1-----00--1-1-- -> 1 8'00000001
+ 20: 1 22'--01-1-------00--1-1-- -> 1 8'00000001
+ 21: 1 22'--00---0-----00--0---- -> 1 8'00000001
+ 22: 1 22'--000-01-----00--0---- -> 1 8'00000001
+ 23: 1 22'--000111-----00--0---- -> 1 8'00000001
+ 24: 1 22'--0011-1-----00--0---- -> 1 8'00000001
+ 25: 1 22'--01-1-------00--0---- -> 1 8'00000001
+ 26: 1 22'--00---0-----10------- -> 1 8'00000001
+ 27: 1 22'--000-01-----10------- -> 1 8'00000001
+ 28: 1 22'--000111-----10------- -> 1 8'00000001
+ 29: 1 22'--0011-1-----10------- -> 1 8'00000001
+ 30: 1 22'--01-1-------10------- -> 1 8'00000001
+ 31: 1 22'--00---0------1------- -> 1 8'00000001
+ 32: 1 22'--000-01------1------- -> 1 8'00000001
+ 33: 1 22'--000111------1------- -> 1 8'00000001
+ 34: 1 22'--0011-1------1------- -> 1 8'00000001
+ 35: 1 22'--01-1--------1------- -> 1 8'00000001
+ 36: 1 22'--10---0-------------- -> 1 8'00000001
+ 37: 1 22'--100-01-------------- -> 1 8'00000001
+ 38: 1 22'--100111-------------- -> 1 8'00000001
+ 39: 1 22'--1011-1-------------- -> 1 8'00000001
+ 40: 1 22'--11-1---------------- -> 1 8'00000001
+ 41: 1 22'--00---0-----00--1-0-- -> 2 8'00000001
+ 42: 1 22'--000-01-----00--1-0-- -> 2 8'00000001
+ 43: 1 22'--000111-----00--1-0-- -> 2 8'00000001
+ 44: 1 22'--0011-1-----00--1-0-- -> 2 8'00000001
+ 45: 1 22'--01-1-------00--1-0-- -> 2 8'00000001
+ 46: 2 22'--00---0---01-----1--0 -> 0 8'01000000
+ 47: 2 22'--000-01---01-----1--0 -> 0 8'01000000
+ 48: 2 22'--000111---01-----1--0 -> 0 8'01000000
+ 49: 2 22'--0011-1---01-----1--0 -> 0 8'01000000
+ 50: 2 22'--01-1-----01-----1--0 -> 0 8'01000000
+ 51: 2 22'---00011-------------- -> 0 8'01000000
+ 52: 2 22'---010-1-------------- -> 0 8'01000000
+ 53: 2 22'---1-0---------------- -> 0 8'01000000
+ 54: 2 22'--00---0---11-----1--0 -> 1 8'01000000
+ 55: 2 22'--000-01---11-----1--0 -> 1 8'01000000
+ 56: 2 22'--000111---11-----1--0 -> 1 8'01000000
+ 57: 2 22'--0011-1---11-----1--0 -> 1 8'01000000
+ 58: 2 22'--01-1-----11-----1--0 -> 1 8'01000000
+ 59: 2 22'--00---0----------1--1 -> 1 8'01000000
+ 60: 2 22'--000-01----------1--1 -> 1 8'01000000
+ 61: 2 22'--000111----------1--1 -> 1 8'01000000
+ 62: 2 22'--0011-1----------1--1 -> 1 8'01000000
+ 63: 2 22'--01-1------------1--1 -> 1 8'01000000
+ 64: 2 22'1-00---0-------------- -> 1 8'01000000
+ 65: 2 22'--10---0-------------- -> 1 8'01000000
+ 66: 2 22'1-000-01-------------- -> 1 8'01000000
+ 67: 2 22'--100-01-------------- -> 1 8'01000000
+ 68: 2 22'1-000111-------------- -> 1 8'01000000
+ 69: 2 22'--100111-------------- -> 1 8'01000000
+ 70: 2 22'1-0011-1-------------- -> 1 8'01000000
+ 71: 2 22'--1011-1-------------- -> 1 8'01000000
+ 72: 2 22'1-01-1---------------- -> 1 8'01000000
+ 73: 2 22'--11-1---------------- -> 1 8'01000000
+ 74: 2 22'--00---0----0-----1--0 -> 2 8'01000000
+ 75: 2 22'--000-01----0-----1--0 -> 2 8'01000000
+ 76: 2 22'--000111----0-----1--0 -> 2 8'01000000
+ 77: 2 22'--0011-1----0-----1--0 -> 2 8'01000000
+ 78: 2 22'--01-1------0-----1--0 -> 2 8'01000000
+ 79: 2 22'0000---0--0-----0-0--- -> 3 8'01000000
+ 80: 2 22'00000-01--0-----0-0--- -> 3 8'01000000
+ 81: 2 22'00000111--0-----0-0--- -> 3 8'01000000
+ 82: 2 22'000011-1--0-----0-0--- -> 3 8'01000000
+ 83: 2 22'0001-1----0-----0-0--- -> 3 8'01000000
+ 84: 2 22'-100---0-------------- -> 3 8'01000000
+ 85: 2 22'-1000-01-------------- -> 3 8'01000000
+ 86: 2 22'-1000111-------------- -> 3 8'01000000
+ 87: 2 22'-10011-1-------------- -> 3 8'01000000
+ 88: 2 22'-101-1---------------- -> 3 8'01000000
+ 89: 2 22'0000---0--0-----1----- -> 4 8'01000000
+ 90: 2 22'00000-01--0-----1----- -> 4 8'01000000
+ 91: 2 22'00000111--0-----1----- -> 4 8'01000000
+ 92: 2 22'000011-1--0-----1----- -> 4 8'01000000
+ 93: 2 22'0001-1----0-----1----- -> 4 8'01000000
+ 94: 2 22'--00---0--1----------- -> 5 8'01000000
+ 95: 2 22'--000-01--1----------- -> 5 8'01000000
+ 96: 2 22'--000111--1----------- -> 5 8'01000000
+ 97: 2 22'--0011-1--1----------- -> 5 8'01000000
+ 98: 2 22'--01-1----1----------- -> 5 8'01000000
+ 99: 3 22'---00011-------------- -> 0 8'00010000
+ 100: 3 22'---010-1-------------- -> 0 8'00010000
+ 101: 3 22'---1-0---------------- -> 0 8'00010000
+ 102: 3 22'--00---0-------1----1- -> 1 8'00010000
+ 103: 3 22'--000-01-------1----1- -> 1 8'00010000
+ 104: 3 22'--000111-------1----1- -> 1 8'00010000
+ 105: 3 22'--0011-1-------1----1- -> 1 8'00010000
+ 106: 3 22'--01-1---------1----1- -> 1 8'00010000
+ 107: 3 22'--00---0-------0------ -> 1 8'00010000
+ 108: 3 22'--000-01-------0------ -> 1 8'00010000
+ 109: 3 22'--000111-------0------ -> 1 8'00010000
+ 110: 3 22'--0011-1-------0------ -> 1 8'00010000
+ 111: 3 22'--01-1---------0------ -> 1 8'00010000
+ 112: 3 22'--10---0-------------- -> 1 8'00010000
+ 113: 3 22'--100-01-------------- -> 1 8'00010000
+ 114: 3 22'--100111-------------- -> 1 8'00010000
+ 115: 3 22'--1011-1-------------- -> 1 8'00010000
+ 116: 3 22'--11-1---------------- -> 1 8'00010000
+ 117: 3 22'--00---0-------1----0- -> 3 8'00010000
+ 118: 3 22'--000-01-------1----0- -> 3 8'00010000
+ 119: 3 22'--000111-------1----0- -> 3 8'00010000
+ 120: 3 22'--0011-1-------1----0- -> 3 8'00010000
+ 121: 3 22'--01-1---------1----0- -> 3 8'00010000
+ 122: 4 22'---00011-------------- -> 0 8'00000100
+ 123: 4 22'---010-1-------------- -> 0 8'00000100
+ 124: 4 22'---1-0---------------- -> 0 8'00000100
+ 125: 4 22'--00---011------------ -> 1 8'00000100
+ 126: 4 22'--000-0111------------ -> 1 8'00000100
+ 127: 4 22'--00011111------------ -> 1 8'00000100
+ 128: 4 22'--0011-111------------ -> 1 8'00000100
+ 129: 4 22'--01-1--11------------ -> 1 8'00000100
+ 130: 4 22'--10---0-------------- -> 1 8'00000100
+ 131: 4 22'--100-01-------------- -> 1 8'00000100
+ 132: 4 22'--100111-------------- -> 1 8'00000100
+ 133: 4 22'--1011-1-------------- -> 1 8'00000100
+ 134: 4 22'--11-1---------------- -> 1 8'00000100
+ 135: 4 22'--00---0-0------------ -> 4 8'00000100
+ 136: 4 22'--000-01-0------------ -> 4 8'00000100
+ 137: 4 22'--000111-0------------ -> 4 8'00000100
+ 138: 4 22'--0011-1-0------------ -> 4 8'00000100
+ 139: 4 22'--01-1---0------------ -> 4 8'00000100
+ 140: 4 22'--00---001------------ -> 4 8'00000100
+ 141: 4 22'--000-0101------------ -> 4 8'00000100
+ 142: 4 22'--00011101------------ -> 4 8'00000100
+ 143: 4 22'--0011-101------------ -> 4 8'00000100
+ 144: 4 22'--01-1--01------------ -> 4 8'00000100
+ 145: 5 22'---00011-------------- -> 0 8'00000010
+ 146: 5 22'---010-1-------------- -> 0 8'00000010
+ 147: 5 22'---1-0---------------- -> 0 8'00000010
+ 148: 5 22'--00---011------------ -> 1 8'00000010
+ 149: 5 22'--000-0111------------ -> 1 8'00000010
+ 150: 5 22'--00011111------------ -> 1 8'00000010
+ 151: 5 22'--0011-111------------ -> 1 8'00000010
+ 152: 5 22'--01-1--11------------ -> 1 8'00000010
+ 153: 5 22'--10---0-------------- -> 1 8'00000010
+ 154: 5 22'--100-01-------------- -> 1 8'00000010
+ 155: 5 22'--100111-------------- -> 1 8'00000010
+ 156: 5 22'--1011-1-------------- -> 1 8'00000010
+ 157: 5 22'--11-1---------------- -> 1 8'00000010
+ 158: 5 22'--00---0-0------------ -> 5 8'00000010
+ 159: 5 22'--000-01-0------------ -> 5 8'00000010
+ 160: 5 22'--000111-0------------ -> 5 8'00000010
+ 161: 5 22'--0011-1-0------------ -> 5 8'00000010
+ 162: 5 22'--01-1---0------------ -> 5 8'00000010
+ 163: 5 22'--00---001------------ -> 5 8'00000010
+ 164: 5 22'--000-0101------------ -> 5 8'00000010
+ 165: 5 22'--00011101------------ -> 5 8'00000010
+ 166: 5 22'--0011-101------------ -> 5 8'00000010
+ 167: 5 22'--01-1--01------------ -> 5 8'00000010
+
+-------------------------------------
+
+FSM `$fsm$\softshell.cpus[0].core.cpu.picorv32_core.mem_wordsize$17228' from module `user_proj_example':
+-------------------------------------
+
+ Information on FSM $fsm$\softshell.cpus[0].core.cpu.picorv32_core.mem_wordsize$17228 (\softshell.cpus[0].core.cpu.picorv32_core.mem_wordsize):
+
+ Number of input signals: 13
+ Number of output signals: 3
+ Number of state bits: 3
+
+ Input signals:
+ 0: \softshell.cpus[0].core.cpu.picorv32_core.mem_do_rdata
+ 1: \softshell.cpus[0].core.cpu.picorv32_core.mem_do_wdata
+ 2: \softshell.cpus[0].core.cpu.picorv32_core.instr_lw
+ 3: \softshell.cpus[0].core.cpu.picorv32_core.instr_sb
+ 4: \softshell.cpus[0].core.cpu.picorv32_core.instr_sh
+ 5: \softshell.cpus[0].core.cpu.picorv32_core.instr_sw
+ 6: $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$eq$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1308$4645_Y
+ 7: $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$logic_or$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1852$4804_Y
+ 8: $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$logic_or$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1881$4812_Y
+ 9: $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$logic_or$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1882$4813_Y
+ 10: $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$5572_CMP
+ 11: $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$5573_CMP
+ 12: \softshell.cpus[0].core.cpu.wb_rst_i
+
+ Output signals:
+ 0: $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$eq$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1918$4824_Y
+ 1: $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$eq$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1925$4831_Y
+ 2: $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$8339_CMP
+
+ State encoding:
+ 0: 3'--1
+ 1: 3'-1-
+ 2: 3'1--
+
+ Transition Table (state_in, ctrl_in, state_out, ctrl_out):
+ 0: 0 13'0-1--1----1-0 -> 0 3'001
+ 1: 0 13'0-1--1------1 -> 0 3'001
+ 2: 0 13'01---1-1---0- -> 0 3'001
+ 3: 0 13'01---1-----1- -> 0 3'001
+ 4: 0 13'000---0------ -> 0 3'001
+ 5: 0 13'0-----1------ -> 0 3'001
+ 6: 0 13'0-1--0------- -> 0 3'001
+ 7: 0 13'01---0------- -> 0 3'001
+ 8: 0 13'1------------ -> 0 3'001
+ 9: 0 13'0-1-11------0 -> 1 3'001
+ 10: 0 13'01---1---1-0- -> 1 3'001
+ 11: 0 13'0-11-1------0 -> 2 3'001
+ 12: 0 13'01---1--1--0- -> 2 3'001
+ 13: 1 13'0-1--1----1-0 -> 0 3'100
+ 14: 1 13'01---1-1---0- -> 0 3'100
+ 15: 1 13'0-----1------ -> 0 3'100
+ 16: 1 13'0-1-11------0 -> 1 3'100
+ 17: 1 13'0-1--1------1 -> 1 3'100
+ 18: 1 13'01---1---1-0- -> 1 3'100
+ 19: 1 13'01---1-----1- -> 1 3'100
+ 20: 1 13'000---0------ -> 1 3'100
+ 21: 1 13'0-1--0------- -> 1 3'100
+ 22: 1 13'01---0------- -> 1 3'100
+ 23: 1 13'1------------ -> 1 3'100
+ 24: 1 13'0-11-1------0 -> 2 3'100
+ 25: 1 13'01---1--1--0- -> 2 3'100
+ 26: 2 13'0-1--1----1-0 -> 0 3'010
+ 27: 2 13'01---1-1---0- -> 0 3'010
+ 28: 2 13'0-----1------ -> 0 3'010
+ 29: 2 13'0-1-11------0 -> 1 3'010
+ 30: 2 13'01---1---1-0- -> 1 3'010
+ 31: 2 13'0-11-1------0 -> 2 3'010
+ 32: 2 13'0-1--1------1 -> 2 3'010
+ 33: 2 13'01---1--1--0- -> 2 3'010
+ 34: 2 13'01---1-----1- -> 2 3'010
+ 35: 2 13'000---0------ -> 2 3'010
+ 36: 2 13'0-1--0------- -> 2 3'010
+ 37: 2 13'01---0------- -> 2 3'010
+ 38: 2 13'1------------ -> 2 3'010
+
+-------------------------------------
+
+FSM `$fsm$\softshell.cpus[0].core.cpu.state$17233' from module `user_proj_example':
+-------------------------------------
+
+ Information on FSM $fsm$\softshell.cpus[0].core.cpu.state$17233 (\softshell.cpus[0].core.cpu.state):
+
+ Number of input signals: 3
+ Number of output signals: 3
+ Number of state bits: 3
+
+ Input signals:
+ 0: \softshell.cpus[0].core.cpu.picorv32_core.mem_valid
+ 1: \softshell.cpus[0].core.cpu.wbm_ack_i
+ 2: \softshell.cpus[0].core.cpu.wb_rst_i
+
+ Output signals:
+ 0: $flatten\softshell.\cpus[0].core.\cpu.$procmux$5114_CMP
+ 1: $flatten\softshell.\cpus[0].core.\cpu.$procmux$5107_CMP
+ 2: $flatten\softshell.\cpus[0].core.\cpu.$procmux$5101_CMP
+
+ State encoding:
+ 0: 3'--1 <RESET STATE>
+ 1: 3'-1-
+ 2: 3'1--
+
+ Transition Table (state_in, ctrl_in, state_out, ctrl_out):
+ 0: 0 3'0-0 -> 0 3'001
+ 1: 0 3'1-- -> 0 3'001
+ 2: 0 3'0-1 -> 2 3'001
+ 3: 1 3'--- -> 0 3'010
+ 4: 2 3'1-- -> 0 3'100
+ 5: 2 3'01- -> 1 3'100
+ 6: 2 3'00- -> 2 3'100
+
+-------------------------------------
+
+FSM `$fsm$\softshell.cpus[1].core.cpu.picorv32_core.cpu_state$17238' from module `user_proj_example':
+-------------------------------------
+
+ Information on FSM $fsm$\softshell.cpus[1].core.cpu.picorv32_core.cpu_state$17238 (\softshell.cpus[1].core.cpu.picorv32_core.cpu_state):
+
+ Number of input signals: 22
+ Number of output signals: 8
+ Number of state bits: 6
+
+ Input signals:
+ 0: \softshell.cpus[1].core.flexio.pcpi_ready
+ 1: \softshell.cpus[1].core.cpu.picorv32_core.mem_done
+ 2: \softshell.cpus[1].core.cpu.picorv32_core.instr_jal
+ 3: \softshell.cpus[1].core.cpu.picorv32_core.instr_trap
+ 4: \softshell.cpus[1].core.cpu.picorv32_core.decoder_trigger
+ 5: \softshell.cpus[1].core.cpu.picorv32_core.is_sb_sh_sw
+ 6: \softshell.cpus[1].core.cpu.picorv32_core.is_beq_bne_blt_bge_bltu_bgeu
+ 7: $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1533$4036_Y
+ 8: $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1543$4044_Y
+ 9: $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1600$4057_Y
+ 10: $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1603$4061_Y
+ 11: $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1691$4075_Y
+ 12: $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$logic_or$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1852$4121_Y
+ 13: $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1867$4125_Y
+ 14: $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1917$4140_Y
+ 15: $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1918$4143_Y
+ 16: $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1920$4147_Y
+ 17: $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1925$4150_Y
+ 18: $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1933$4157_Y
+ 19: \softshell.cpus[1].core.cpu.wb_rst_i
+ 20: $auto$opt_reduce.cc:134:opt_mux$16933
+ 21: $auto$opt_reduce.cc:134:opt_mux$16931
+
+ Output signals:
+ 0: $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$eq$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1308$3962_Y
+ 1: $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$9225_CMP
+ 2: $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10008_CMP
+ 3: $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10018_CMP
+ 4: $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10034_CMP
+ 5: $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10149_CMP
+ 6: $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10165_CMP
+ 7: $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10223_CMP
+
+ State encoding:
+ 0: 6'-----1
+ 1: 6'----1-
+ 2: 6'---1--
+ 3: 6'--1---
+ 4: 6'-1----
+ 5: 6'1-----
+
+ Transition Table (state_in, ctrl_in, state_out, ctrl_out):
+ 0: 0 22'--00---0-------------- -> 0 8'00000010
+ 1: 0 22'--000-01-------------- -> 0 8'00000010
+ 2: 0 22'---00011-------------- -> 0 8'00000010
+ 3: 0 22'--000111-------------- -> 0 8'00000010
+ 4: 0 22'---010-1-------------- -> 0 8'00000010
+ 5: 0 22'--0011-1-------------- -> 0 8'00000010
+ 6: 0 22'---1-0---------------- -> 0 8'00000010
+ 7: 0 22'--01-1---------------- -> 0 8'00000010
+ 8: 0 22'--10---0-------------- -> 1 8'00000010
+ 9: 0 22'--100-01-------------- -> 1 8'00000010
+ 10: 0 22'--100111-------------- -> 1 8'00000010
+ 11: 0 22'--1011-1-------------- -> 1 8'00000010
+ 12: 0 22'--11-1---------------- -> 1 8'00000010
+ 13: 1 22'---00011-------------- -> 0 8'00000001
+ 14: 1 22'---010-1-------------- -> 0 8'00000001
+ 15: 1 22'---1-0---------------- -> 0 8'00000001
+ 16: 1 22'--00---0-----00--1-1-- -> 1 8'00000001
+ 17: 1 22'--000-01-----00--1-1-- -> 1 8'00000001
+ 18: 1 22'--000111-----00--1-1-- -> 1 8'00000001
+ 19: 1 22'--0011-1-----00--1-1-- -> 1 8'00000001
+ 20: 1 22'--01-1-------00--1-1-- -> 1 8'00000001
+ 21: 1 22'--00---0-----00--0---- -> 1 8'00000001
+ 22: 1 22'--000-01-----00--0---- -> 1 8'00000001
+ 23: 1 22'--000111-----00--0---- -> 1 8'00000001
+ 24: 1 22'--0011-1-----00--0---- -> 1 8'00000001
+ 25: 1 22'--01-1-------00--0---- -> 1 8'00000001
+ 26: 1 22'--00---0-----10------- -> 1 8'00000001
+ 27: 1 22'--000-01-----10------- -> 1 8'00000001
+ 28: 1 22'--000111-----10------- -> 1 8'00000001
+ 29: 1 22'--0011-1-----10------- -> 1 8'00000001
+ 30: 1 22'--01-1-------10------- -> 1 8'00000001
+ 31: 1 22'--00---0------1------- -> 1 8'00000001
+ 32: 1 22'--000-01------1------- -> 1 8'00000001
+ 33: 1 22'--000111------1------- -> 1 8'00000001
+ 34: 1 22'--0011-1------1------- -> 1 8'00000001
+ 35: 1 22'--01-1--------1------- -> 1 8'00000001
+ 36: 1 22'--10---0-------------- -> 1 8'00000001
+ 37: 1 22'--100-01-------------- -> 1 8'00000001
+ 38: 1 22'--100111-------------- -> 1 8'00000001
+ 39: 1 22'--1011-1-------------- -> 1 8'00000001
+ 40: 1 22'--11-1---------------- -> 1 8'00000001
+ 41: 1 22'--00---0-----00--1-0-- -> 2 8'00000001
+ 42: 1 22'--000-01-----00--1-0-- -> 2 8'00000001
+ 43: 1 22'--000111-----00--1-0-- -> 2 8'00000001
+ 44: 1 22'--0011-1-----00--1-0-- -> 2 8'00000001
+ 45: 1 22'--01-1-------00--1-0-- -> 2 8'00000001
+ 46: 2 22'--00---0---01-----1--0 -> 0 8'00001000
+ 47: 2 22'--000-01---01-----1--0 -> 0 8'00001000
+ 48: 2 22'--000111---01-----1--0 -> 0 8'00001000
+ 49: 2 22'--0011-1---01-----1--0 -> 0 8'00001000
+ 50: 2 22'--01-1-----01-----1--0 -> 0 8'00001000
+ 51: 2 22'---00011-------------- -> 0 8'00001000
+ 52: 2 22'---010-1-------------- -> 0 8'00001000
+ 53: 2 22'---1-0---------------- -> 0 8'00001000
+ 54: 2 22'--00---0---11-----1--0 -> 1 8'00001000
+ 55: 2 22'--000-01---11-----1--0 -> 1 8'00001000
+ 56: 2 22'--000111---11-----1--0 -> 1 8'00001000
+ 57: 2 22'--0011-1---11-----1--0 -> 1 8'00001000
+ 58: 2 22'--01-1-----11-----1--0 -> 1 8'00001000
+ 59: 2 22'--00---0----------1--1 -> 1 8'00001000
+ 60: 2 22'--000-01----------1--1 -> 1 8'00001000
+ 61: 2 22'--000111----------1--1 -> 1 8'00001000
+ 62: 2 22'--0011-1----------1--1 -> 1 8'00001000
+ 63: 2 22'--01-1------------1--1 -> 1 8'00001000
+ 64: 2 22'1-00---0-------------- -> 1 8'00001000
+ 65: 2 22'--10---0-------------- -> 1 8'00001000
+ 66: 2 22'1-000-01-------------- -> 1 8'00001000
+ 67: 2 22'--100-01-------------- -> 1 8'00001000
+ 68: 2 22'1-000111-------------- -> 1 8'00001000
+ 69: 2 22'--100111-------------- -> 1 8'00001000
+ 70: 2 22'1-0011-1-------------- -> 1 8'00001000
+ 71: 2 22'--1011-1-------------- -> 1 8'00001000
+ 72: 2 22'1-01-1---------------- -> 1 8'00001000
+ 73: 2 22'--11-1---------------- -> 1 8'00001000
+ 74: 2 22'--00---0----0-----1--0 -> 2 8'00001000
+ 75: 2 22'--000-01----0-----1--0 -> 2 8'00001000
+ 76: 2 22'--000111----0-----1--0 -> 2 8'00001000
+ 77: 2 22'--0011-1----0-----1--0 -> 2 8'00001000
+ 78: 2 22'--01-1------0-----1--0 -> 2 8'00001000
+ 79: 2 22'0000---0--0-----0-0--- -> 3 8'00001000
+ 80: 2 22'00000-01--0-----0-0--- -> 3 8'00001000
+ 81: 2 22'00000111--0-----0-0--- -> 3 8'00001000
+ 82: 2 22'000011-1--0-----0-0--- -> 3 8'00001000
+ 83: 2 22'0001-1----0-----0-0--- -> 3 8'00001000
+ 84: 2 22'-100---0-------------- -> 3 8'00001000
+ 85: 2 22'-1000-01-------------- -> 3 8'00001000
+ 86: 2 22'-1000111-------------- -> 3 8'00001000
+ 87: 2 22'-10011-1-------------- -> 3 8'00001000
+ 88: 2 22'-101-1---------------- -> 3 8'00001000
+ 89: 2 22'0000---0--0-----1----- -> 4 8'00001000
+ 90: 2 22'00000-01--0-----1----- -> 4 8'00001000
+ 91: 2 22'00000111--0-----1----- -> 4 8'00001000
+ 92: 2 22'000011-1--0-----1----- -> 4 8'00001000
+ 93: 2 22'0001-1----0-----1----- -> 4 8'00001000
+ 94: 2 22'--00---0--1----------- -> 5 8'00001000
+ 95: 2 22'--000-01--1----------- -> 5 8'00001000
+ 96: 2 22'--000111--1----------- -> 5 8'00001000
+ 97: 2 22'--0011-1--1----------- -> 5 8'00001000
+ 98: 2 22'--01-1----1----------- -> 5 8'00001000
+ 99: 3 22'---00011-------------- -> 0 8'00000100
+ 100: 3 22'---010-1-------------- -> 0 8'00000100
+ 101: 3 22'---1-0---------------- -> 0 8'00000100
+ 102: 3 22'--00---0-------1----1- -> 1 8'00000100
+ 103: 3 22'--000-01-------1----1- -> 1 8'00000100
+ 104: 3 22'--000111-------1----1- -> 1 8'00000100
+ 105: 3 22'--0011-1-------1----1- -> 1 8'00000100
+ 106: 3 22'--01-1---------1----1- -> 1 8'00000100
+ 107: 3 22'--00---0-------0------ -> 1 8'00000100
+ 108: 3 22'--000-01-------0------ -> 1 8'00000100
+ 109: 3 22'--000111-------0------ -> 1 8'00000100
+ 110: 3 22'--0011-1-------0------ -> 1 8'00000100
+ 111: 3 22'--01-1---------0------ -> 1 8'00000100
+ 112: 3 22'--10---0-------------- -> 1 8'00000100
+ 113: 3 22'--100-01-------------- -> 1 8'00000100
+ 114: 3 22'--100111-------------- -> 1 8'00000100
+ 115: 3 22'--1011-1-------------- -> 1 8'00000100
+ 116: 3 22'--11-1---------------- -> 1 8'00000100
+ 117: 3 22'--00---0-------1----0- -> 3 8'00000100
+ 118: 3 22'--000-01-------1----0- -> 3 8'00000100
+ 119: 3 22'--000111-------1----0- -> 3 8'00000100
+ 120: 3 22'--0011-1-------1----0- -> 3 8'00000100
+ 121: 3 22'--01-1---------1----0- -> 3 8'00000100
+ 122: 4 22'---00011-------------- -> 0 8'10000000
+ 123: 4 22'---010-1-------------- -> 0 8'10000000
+ 124: 4 22'---1-0---------------- -> 0 8'10000000
+ 125: 4 22'--00---011------------ -> 1 8'10000000
+ 126: 4 22'--000-0111------------ -> 1 8'10000000
+ 127: 4 22'--00011111------------ -> 1 8'10000000
+ 128: 4 22'--0011-111------------ -> 1 8'10000000
+ 129: 4 22'--01-1--11------------ -> 1 8'10000000
+ 130: 4 22'--10---0-------------- -> 1 8'10000000
+ 131: 4 22'--100-01-------------- -> 1 8'10000000
+ 132: 4 22'--100111-------------- -> 1 8'10000000
+ 133: 4 22'--1011-1-------------- -> 1 8'10000000
+ 134: 4 22'--11-1---------------- -> 1 8'10000000
+ 135: 4 22'--00---0-0------------ -> 4 8'10000000
+ 136: 4 22'--000-01-0------------ -> 4 8'10000000
+ 137: 4 22'--000111-0------------ -> 4 8'10000000
+ 138: 4 22'--0011-1-0------------ -> 4 8'10000000
+ 139: 4 22'--01-1---0------------ -> 4 8'10000000
+ 140: 4 22'--00---001------------ -> 4 8'10000000
+ 141: 4 22'--000-0101------------ -> 4 8'10000000
+ 142: 4 22'--00011101------------ -> 4 8'10000000
+ 143: 4 22'--0011-101------------ -> 4 8'10000000
+ 144: 4 22'--01-1--01------------ -> 4 8'10000000
+ 145: 5 22'---00011-------------- -> 0 8'00010000
+ 146: 5 22'---010-1-------------- -> 0 8'00010000
+ 147: 5 22'---1-0---------------- -> 0 8'00010000
+ 148: 5 22'--00---011------------ -> 1 8'00010000
+ 149: 5 22'--000-0111------------ -> 1 8'00010000
+ 150: 5 22'--00011111------------ -> 1 8'00010000
+ 151: 5 22'--0011-111------------ -> 1 8'00010000
+ 152: 5 22'--01-1--11------------ -> 1 8'00010000
+ 153: 5 22'--10---0-------------- -> 1 8'00010000
+ 154: 5 22'--100-01-------------- -> 1 8'00010000
+ 155: 5 22'--100111-------------- -> 1 8'00010000
+ 156: 5 22'--1011-1-------------- -> 1 8'00010000
+ 157: 5 22'--11-1---------------- -> 1 8'00010000
+ 158: 5 22'--00---0-0------------ -> 5 8'00010000
+ 159: 5 22'--000-01-0------------ -> 5 8'00010000
+ 160: 5 22'--000111-0------------ -> 5 8'00010000
+ 161: 5 22'--0011-1-0------------ -> 5 8'00010000
+ 162: 5 22'--01-1---0------------ -> 5 8'00010000
+ 163: 5 22'--00---001------------ -> 5 8'00010000
+ 164: 5 22'--000-0101------------ -> 5 8'00010000
+ 165: 5 22'--00011101------------ -> 5 8'00010000
+ 166: 5 22'--0011-101------------ -> 5 8'00010000
+ 167: 5 22'--01-1--01------------ -> 5 8'00010000
+
+-------------------------------------
+
+FSM `$fsm$\softshell.cpus[1].core.cpu.picorv32_core.mem_wordsize$17248' from module `user_proj_example':
+-------------------------------------
+
+ Information on FSM $fsm$\softshell.cpus[1].core.cpu.picorv32_core.mem_wordsize$17248 (\softshell.cpus[1].core.cpu.picorv32_core.mem_wordsize):
+
+ Number of input signals: 13
+ Number of output signals: 3
+ Number of state bits: 3
+
+ Input signals:
+ 0: \softshell.cpus[1].core.cpu.picorv32_core.mem_do_rdata
+ 1: \softshell.cpus[1].core.cpu.picorv32_core.mem_do_wdata
+ 2: \softshell.cpus[1].core.cpu.picorv32_core.instr_lw
+ 3: \softshell.cpus[1].core.cpu.picorv32_core.instr_sb
+ 4: \softshell.cpus[1].core.cpu.picorv32_core.instr_sh
+ 5: \softshell.cpus[1].core.cpu.picorv32_core.instr_sw
+ 6: $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$eq$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1308$3962_Y
+ 7: $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$logic_or$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1852$4121_Y
+ 8: $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$logic_or$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1881$4129_Y
+ 9: $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$logic_or$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1882$4130_Y
+ 10: $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10034_CMP
+ 11: $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10223_CMP
+ 12: \softshell.cpus[1].core.cpu.wb_rst_i
+
+ Output signals:
+ 0: $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$eq$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1918$4141_Y
+ 1: $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$eq$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1925$4148_Y
+ 2: $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$11985_CMP
+
+ State encoding:
+ 0: 3'--1
+ 1: 3'-1-
+ 2: 3'1--
+
+ Transition Table (state_in, ctrl_in, state_out, ctrl_out):
+ 0: 0 13'0-1--1----1-0 -> 0 3'001
+ 1: 0 13'0-1--1------1 -> 0 3'001
+ 2: 0 13'01---1-1---0- -> 0 3'001
+ 3: 0 13'01---1-----1- -> 0 3'001
+ 4: 0 13'000---0------ -> 0 3'001
+ 5: 0 13'0-----1------ -> 0 3'001
+ 6: 0 13'0-1--0------- -> 0 3'001
+ 7: 0 13'01---0------- -> 0 3'001
+ 8: 0 13'1------------ -> 0 3'001
+ 9: 0 13'0-1-11------0 -> 1 3'001
+ 10: 0 13'01---1---1-0- -> 1 3'001
+ 11: 0 13'0-11-1------0 -> 2 3'001
+ 12: 0 13'01---1--1--0- -> 2 3'001
+ 13: 1 13'0-1--1----1-0 -> 0 3'100
+ 14: 1 13'01---1-1---0- -> 0 3'100
+ 15: 1 13'0-----1------ -> 0 3'100
+ 16: 1 13'0-1-11------0 -> 1 3'100
+ 17: 1 13'0-1--1------1 -> 1 3'100
+ 18: 1 13'01---1---1-0- -> 1 3'100
+ 19: 1 13'01---1-----1- -> 1 3'100
+ 20: 1 13'000---0------ -> 1 3'100
+ 21: 1 13'0-1--0------- -> 1 3'100
+ 22: 1 13'01---0------- -> 1 3'100
+ 23: 1 13'1------------ -> 1 3'100
+ 24: 1 13'0-11-1------0 -> 2 3'100
+ 25: 1 13'01---1--1--0- -> 2 3'100
+ 26: 2 13'0-1--1----1-0 -> 0 3'010
+ 27: 2 13'01---1-1---0- -> 0 3'010
+ 28: 2 13'0-----1------ -> 0 3'010
+ 29: 2 13'0-1-11------0 -> 1 3'010
+ 30: 2 13'01---1---1-0- -> 1 3'010
+ 31: 2 13'0-11-1------0 -> 2 3'010
+ 32: 2 13'0-1--1------1 -> 2 3'010
+ 33: 2 13'01---1--1--0- -> 2 3'010
+ 34: 2 13'01---1-----1- -> 2 3'010
+ 35: 2 13'000---0------ -> 2 3'010
+ 36: 2 13'0-1--0------- -> 2 3'010
+ 37: 2 13'01---0------- -> 2 3'010
+ 38: 2 13'1------------ -> 2 3'010
+
+-------------------------------------
+
+FSM `$fsm$\softshell.cpus[1].core.cpu.state$17253' from module `user_proj_example':
+-------------------------------------
+
+ Information on FSM $fsm$\softshell.cpus[1].core.cpu.state$17253 (\softshell.cpus[1].core.cpu.state):
+
+ Number of input signals: 3
+ Number of output signals: 3
+ Number of state bits: 3
+
+ Input signals:
+ 0: \softshell.cpus[1].core.cpu.picorv32_core.mem_valid
+ 1: \softshell.cpus[1].core.cpu.wbm_ack_i
+ 2: \softshell.cpus[1].core.cpu.wb_rst_i
+
+ Output signals:
+ 0: $flatten\softshell.\cpus[1].core.\cpu.$procmux$5221_CMP
+ 1: $flatten\softshell.\cpus[1].core.\cpu.$procmux$5214_CMP
+ 2: $flatten\softshell.\cpus[1].core.\cpu.$procmux$5208_CMP
+
+ State encoding:
+ 0: 3'--1 <RESET STATE>
+ 1: 3'-1-
+ 2: 3'1--
+
+ Transition Table (state_in, ctrl_in, state_out, ctrl_out):
+ 0: 0 3'0-0 -> 0 3'001
+ 1: 0 3'1-- -> 0 3'001
+ 2: 0 3'0-1 -> 2 3'001
+ 3: 1 3'--- -> 0 3'010
+ 4: 2 3'1-- -> 0 3'100
+ 5: 2 3'01- -> 1 3'100
+ 6: 2 3'00- -> 2 3'100
+
+-------------------------------------
+
+FSM `$fsm$\softshell.cpus[2].core.cpu.picorv32_core.cpu_state$17258' from module `user_proj_example':
+-------------------------------------
+
+ Information on FSM $fsm$\softshell.cpus[2].core.cpu.picorv32_core.cpu_state$17258 (\softshell.cpus[2].core.cpu.picorv32_core.cpu_state):
+
+ Number of input signals: 22
+ Number of output signals: 8
+ Number of state bits: 6
+
+ Input signals:
+ 0: \softshell.cpus[2].core.flexio.pcpi_ready
+ 1: \softshell.cpus[2].core.cpu.picorv32_core.mem_done
+ 2: \softshell.cpus[2].core.cpu.picorv32_core.instr_jal
+ 3: \softshell.cpus[2].core.cpu.picorv32_core.instr_trap
+ 4: \softshell.cpus[2].core.cpu.picorv32_core.decoder_trigger
+ 5: \softshell.cpus[2].core.cpu.picorv32_core.is_sb_sh_sw
+ 6: \softshell.cpus[2].core.cpu.picorv32_core.is_beq_bne_blt_bge_bltu_bgeu
+ 7: $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1533$3353_Y
+ 8: $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1543$3361_Y
+ 9: $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1600$3374_Y
+ 10: $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1603$3378_Y
+ 11: $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1691$3392_Y
+ 12: $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$logic_or$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1852$3438_Y
+ 13: $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1867$3442_Y
+ 14: $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1917$3457_Y
+ 15: $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1918$3460_Y
+ 16: $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1920$3464_Y
+ 17: $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1925$3467_Y
+ 18: $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1933$3474_Y
+ 19: \softshell.cpus[2].core.cpu.wb_rst_i
+ 20: $auto$opt_reduce.cc:134:opt_mux$17073
+ 21: $auto$opt_reduce.cc:134:opt_mux$17071
+
+ Output signals:
+ 0: $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$eq$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1308$3279_Y
+ 1: $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$12083_CMP
+ 2: $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$12084_CMP
+ 3: $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$12085_CMP
+ 4: $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$12086_CMP
+ 5: $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$12087_CMP
+ 6: $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$12088_CMP
+ 7: $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$12090_CMP
+
+ State encoding:
+ 0: 6'-----1
+ 1: 6'----1-
+ 2: 6'---1--
+ 3: 6'--1---
+ 4: 6'-1----
+ 5: 6'1-----
+
+ Transition Table (state_in, ctrl_in, state_out, ctrl_out):
+ 0: 0 22'--00---0-------------- -> 0 8'10000000
+ 1: 0 22'--000-01-------------- -> 0 8'10000000
+ 2: 0 22'---00011-------------- -> 0 8'10000000
+ 3: 0 22'--000111-------------- -> 0 8'10000000
+ 4: 0 22'---010-1-------------- -> 0 8'10000000
+ 5: 0 22'--0011-1-------------- -> 0 8'10000000
+ 6: 0 22'---1-0---------------- -> 0 8'10000000
+ 7: 0 22'--01-1---------------- -> 0 8'10000000
+ 8: 0 22'--10---0-------------- -> 1 8'10000000
+ 9: 0 22'--100-01-------------- -> 1 8'10000000
+ 10: 0 22'--100111-------------- -> 1 8'10000000
+ 11: 0 22'--1011-1-------------- -> 1 8'10000000
+ 12: 0 22'--11-1---------------- -> 1 8'10000000
+ 13: 1 22'---00011-------------- -> 0 8'00000001
+ 14: 1 22'---010-1-------------- -> 0 8'00000001
+ 15: 1 22'---1-0---------------- -> 0 8'00000001
+ 16: 1 22'--00---0-----00--1-1-- -> 1 8'00000001
+ 17: 1 22'--000-01-----00--1-1-- -> 1 8'00000001
+ 18: 1 22'--000111-----00--1-1-- -> 1 8'00000001
+ 19: 1 22'--0011-1-----00--1-1-- -> 1 8'00000001
+ 20: 1 22'--01-1-------00--1-1-- -> 1 8'00000001
+ 21: 1 22'--00---0-----00--0---- -> 1 8'00000001
+ 22: 1 22'--000-01-----00--0---- -> 1 8'00000001
+ 23: 1 22'--000111-----00--0---- -> 1 8'00000001
+ 24: 1 22'--0011-1-----00--0---- -> 1 8'00000001
+ 25: 1 22'--01-1-------00--0---- -> 1 8'00000001
+ 26: 1 22'--00---0-----10------- -> 1 8'00000001
+ 27: 1 22'--000-01-----10------- -> 1 8'00000001
+ 28: 1 22'--000111-----10------- -> 1 8'00000001
+ 29: 1 22'--0011-1-----10------- -> 1 8'00000001
+ 30: 1 22'--01-1-------10------- -> 1 8'00000001
+ 31: 1 22'--00---0------1------- -> 1 8'00000001
+ 32: 1 22'--000-01------1------- -> 1 8'00000001
+ 33: 1 22'--000111------1------- -> 1 8'00000001
+ 34: 1 22'--0011-1------1------- -> 1 8'00000001
+ 35: 1 22'--01-1--------1------- -> 1 8'00000001
+ 36: 1 22'--10---0-------------- -> 1 8'00000001
+ 37: 1 22'--100-01-------------- -> 1 8'00000001
+ 38: 1 22'--100111-------------- -> 1 8'00000001
+ 39: 1 22'--1011-1-------------- -> 1 8'00000001
+ 40: 1 22'--11-1---------------- -> 1 8'00000001
+ 41: 1 22'--00---0-----00--1-0-- -> 2 8'00000001
+ 42: 1 22'--000-01-----00--1-0-- -> 2 8'00000001
+ 43: 1 22'--000111-----00--1-0-- -> 2 8'00000001
+ 44: 1 22'--0011-1-----00--1-0-- -> 2 8'00000001
+ 45: 1 22'--01-1-------00--1-0-- -> 2 8'00000001
+ 46: 2 22'--00---0---01-----1--0 -> 0 8'01000000
+ 47: 2 22'--000-01---01-----1--0 -> 0 8'01000000
+ 48: 2 22'--000111---01-----1--0 -> 0 8'01000000
+ 49: 2 22'--0011-1---01-----1--0 -> 0 8'01000000
+ 50: 2 22'--01-1-----01-----1--0 -> 0 8'01000000
+ 51: 2 22'---00011-------------- -> 0 8'01000000
+ 52: 2 22'---010-1-------------- -> 0 8'01000000
+ 53: 2 22'---1-0---------------- -> 0 8'01000000
+ 54: 2 22'--00---0---11-----1--0 -> 1 8'01000000
+ 55: 2 22'--000-01---11-----1--0 -> 1 8'01000000
+ 56: 2 22'--000111---11-----1--0 -> 1 8'01000000
+ 57: 2 22'--0011-1---11-----1--0 -> 1 8'01000000
+ 58: 2 22'--01-1-----11-----1--0 -> 1 8'01000000
+ 59: 2 22'--00---0----------1--1 -> 1 8'01000000
+ 60: 2 22'--000-01----------1--1 -> 1 8'01000000
+ 61: 2 22'--000111----------1--1 -> 1 8'01000000
+ 62: 2 22'--0011-1----------1--1 -> 1 8'01000000
+ 63: 2 22'--01-1------------1--1 -> 1 8'01000000
+ 64: 2 22'1-00---0-------------- -> 1 8'01000000
+ 65: 2 22'--10---0-------------- -> 1 8'01000000
+ 66: 2 22'1-000-01-------------- -> 1 8'01000000
+ 67: 2 22'--100-01-------------- -> 1 8'01000000
+ 68: 2 22'1-000111-------------- -> 1 8'01000000
+ 69: 2 22'--100111-------------- -> 1 8'01000000
+ 70: 2 22'1-0011-1-------------- -> 1 8'01000000
+ 71: 2 22'--1011-1-------------- -> 1 8'01000000
+ 72: 2 22'1-01-1---------------- -> 1 8'01000000
+ 73: 2 22'--11-1---------------- -> 1 8'01000000
+ 74: 2 22'--00---0----0-----1--0 -> 2 8'01000000
+ 75: 2 22'--000-01----0-----1--0 -> 2 8'01000000
+ 76: 2 22'--000111----0-----1--0 -> 2 8'01000000
+ 77: 2 22'--0011-1----0-----1--0 -> 2 8'01000000
+ 78: 2 22'--01-1------0-----1--0 -> 2 8'01000000
+ 79: 2 22'0000---0--0-----0-0--- -> 3 8'01000000
+ 80: 2 22'00000-01--0-----0-0--- -> 3 8'01000000
+ 81: 2 22'00000111--0-----0-0--- -> 3 8'01000000
+ 82: 2 22'000011-1--0-----0-0--- -> 3 8'01000000
+ 83: 2 22'0001-1----0-----0-0--- -> 3 8'01000000
+ 84: 2 22'-100---0-------------- -> 3 8'01000000
+ 85: 2 22'-1000-01-------------- -> 3 8'01000000
+ 86: 2 22'-1000111-------------- -> 3 8'01000000
+ 87: 2 22'-10011-1-------------- -> 3 8'01000000
+ 88: 2 22'-101-1---------------- -> 3 8'01000000
+ 89: 2 22'0000---0--0-----1----- -> 4 8'01000000
+ 90: 2 22'00000-01--0-----1----- -> 4 8'01000000
+ 91: 2 22'00000111--0-----1----- -> 4 8'01000000
+ 92: 2 22'000011-1--0-----1----- -> 4 8'01000000
+ 93: 2 22'0001-1----0-----1----- -> 4 8'01000000
+ 94: 2 22'--00---0--1----------- -> 5 8'01000000
+ 95: 2 22'--000-01--1----------- -> 5 8'01000000
+ 96: 2 22'--000111--1----------- -> 5 8'01000000
+ 97: 2 22'--0011-1--1----------- -> 5 8'01000000
+ 98: 2 22'--01-1----1----------- -> 5 8'01000000
+ 99: 3 22'---00011-------------- -> 0 8'00010000
+ 100: 3 22'---010-1-------------- -> 0 8'00010000
+ 101: 3 22'---1-0---------------- -> 0 8'00010000
+ 102: 3 22'--00---0-------1----1- -> 1 8'00010000
+ 103: 3 22'--000-01-------1----1- -> 1 8'00010000
+ 104: 3 22'--000111-------1----1- -> 1 8'00010000
+ 105: 3 22'--0011-1-------1----1- -> 1 8'00010000
+ 106: 3 22'--01-1---------1----1- -> 1 8'00010000
+ 107: 3 22'--00---0-------0------ -> 1 8'00010000
+ 108: 3 22'--000-01-------0------ -> 1 8'00010000
+ 109: 3 22'--000111-------0------ -> 1 8'00010000
+ 110: 3 22'--0011-1-------0------ -> 1 8'00010000
+ 111: 3 22'--01-1---------0------ -> 1 8'00010000
+ 112: 3 22'--10---0-------------- -> 1 8'00010000
+ 113: 3 22'--100-01-------------- -> 1 8'00010000
+ 114: 3 22'--100111-------------- -> 1 8'00010000
+ 115: 3 22'--1011-1-------------- -> 1 8'00010000
+ 116: 3 22'--11-1---------------- -> 1 8'00010000
+ 117: 3 22'--00---0-------1----0- -> 3 8'00010000
+ 118: 3 22'--000-01-------1----0- -> 3 8'00010000
+ 119: 3 22'--000111-------1----0- -> 3 8'00010000
+ 120: 3 22'--0011-1-------1----0- -> 3 8'00010000
+ 121: 3 22'--01-1---------1----0- -> 3 8'00010000
+ 122: 4 22'---00011-------------- -> 0 8'00000100
+ 123: 4 22'---010-1-------------- -> 0 8'00000100
+ 124: 4 22'---1-0---------------- -> 0 8'00000100
+ 125: 4 22'--00---011------------ -> 1 8'00000100
+ 126: 4 22'--000-0111------------ -> 1 8'00000100
+ 127: 4 22'--00011111------------ -> 1 8'00000100
+ 128: 4 22'--0011-111------------ -> 1 8'00000100
+ 129: 4 22'--01-1--11------------ -> 1 8'00000100
+ 130: 4 22'--10---0-------------- -> 1 8'00000100
+ 131: 4 22'--100-01-------------- -> 1 8'00000100
+ 132: 4 22'--100111-------------- -> 1 8'00000100
+ 133: 4 22'--1011-1-------------- -> 1 8'00000100
+ 134: 4 22'--11-1---------------- -> 1 8'00000100
+ 135: 4 22'--00---0-0------------ -> 4 8'00000100
+ 136: 4 22'--000-01-0------------ -> 4 8'00000100
+ 137: 4 22'--000111-0------------ -> 4 8'00000100
+ 138: 4 22'--0011-1-0------------ -> 4 8'00000100
+ 139: 4 22'--01-1---0------------ -> 4 8'00000100
+ 140: 4 22'--00---001------------ -> 4 8'00000100
+ 141: 4 22'--000-0101------------ -> 4 8'00000100
+ 142: 4 22'--00011101------------ -> 4 8'00000100
+ 143: 4 22'--0011-101------------ -> 4 8'00000100
+ 144: 4 22'--01-1--01------------ -> 4 8'00000100
+ 145: 5 22'---00011-------------- -> 0 8'00000010
+ 146: 5 22'---010-1-------------- -> 0 8'00000010
+ 147: 5 22'---1-0---------------- -> 0 8'00000010
+ 148: 5 22'--00---011------------ -> 1 8'00000010
+ 149: 5 22'--000-0111------------ -> 1 8'00000010
+ 150: 5 22'--00011111------------ -> 1 8'00000010
+ 151: 5 22'--0011-111------------ -> 1 8'00000010
+ 152: 5 22'--01-1--11------------ -> 1 8'00000010
+ 153: 5 22'--10---0-------------- -> 1 8'00000010
+ 154: 5 22'--100-01-------------- -> 1 8'00000010
+ 155: 5 22'--100111-------------- -> 1 8'00000010
+ 156: 5 22'--1011-1-------------- -> 1 8'00000010
+ 157: 5 22'--11-1---------------- -> 1 8'00000010
+ 158: 5 22'--00---0-0------------ -> 5 8'00000010
+ 159: 5 22'--000-01-0------------ -> 5 8'00000010
+ 160: 5 22'--000111-0------------ -> 5 8'00000010
+ 161: 5 22'--0011-1-0------------ -> 5 8'00000010
+ 162: 5 22'--01-1---0------------ -> 5 8'00000010
+ 163: 5 22'--00---001------------ -> 5 8'00000010
+ 164: 5 22'--000-0101------------ -> 5 8'00000010
+ 165: 5 22'--00011101------------ -> 5 8'00000010
+ 166: 5 22'--0011-101------------ -> 5 8'00000010
+ 167: 5 22'--01-1--01------------ -> 5 8'00000010
+
+-------------------------------------
+
+FSM `$fsm$\softshell.cpus[2].core.cpu.picorv32_core.mem_wordsize$17268' from module `user_proj_example':
+-------------------------------------
+
+ Information on FSM $fsm$\softshell.cpus[2].core.cpu.picorv32_core.mem_wordsize$17268 (\softshell.cpus[2].core.cpu.picorv32_core.mem_wordsize):
+
+ Number of input signals: 13
+ Number of output signals: 3
+ Number of state bits: 3
+
+ Input signals:
+ 0: \softshell.cpus[2].core.cpu.picorv32_core.mem_do_rdata
+ 1: \softshell.cpus[2].core.cpu.picorv32_core.mem_do_wdata
+ 2: \softshell.cpus[2].core.cpu.picorv32_core.instr_lw
+ 3: \softshell.cpus[2].core.cpu.picorv32_core.instr_sb
+ 4: \softshell.cpus[2].core.cpu.picorv32_core.instr_sh
+ 5: \softshell.cpus[2].core.cpu.picorv32_core.instr_sw
+ 6: $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$eq$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1308$3279_Y
+ 7: $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$logic_or$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1852$3438_Y
+ 8: $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$logic_or$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1881$3446_Y
+ 9: $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$logic_or$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1882$3447_Y
+ 10: $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$12083_CMP
+ 11: $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$12084_CMP
+ 12: \softshell.cpus[2].core.cpu.wb_rst_i
+
+ Output signals:
+ 0: $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$eq$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1918$3458_Y
+ 1: $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$eq$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1925$3465_Y
+ 2: $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$14850_CMP
+
+ State encoding:
+ 0: 3'--1
+ 1: 3'-1-
+ 2: 3'1--
+
+ Transition Table (state_in, ctrl_in, state_out, ctrl_out):
+ 0: 0 13'0-1--1----1-0 -> 0 3'001
+ 1: 0 13'0-1--1------1 -> 0 3'001
+ 2: 0 13'01---1-1---0- -> 0 3'001
+ 3: 0 13'01---1-----1- -> 0 3'001
+ 4: 0 13'000---0------ -> 0 3'001
+ 5: 0 13'0-----1------ -> 0 3'001
+ 6: 0 13'0-1--0------- -> 0 3'001
+ 7: 0 13'01---0------- -> 0 3'001
+ 8: 0 13'1------------ -> 0 3'001
+ 9: 0 13'0-1-11------0 -> 1 3'001
+ 10: 0 13'01---1---1-0- -> 1 3'001
+ 11: 0 13'0-11-1------0 -> 2 3'001
+ 12: 0 13'01---1--1--0- -> 2 3'001
+ 13: 1 13'0-1--1----1-0 -> 0 3'100
+ 14: 1 13'01---1-1---0- -> 0 3'100
+ 15: 1 13'0-----1------ -> 0 3'100
+ 16: 1 13'0-1-11------0 -> 1 3'100
+ 17: 1 13'0-1--1------1 -> 1 3'100
+ 18: 1 13'01---1---1-0- -> 1 3'100
+ 19: 1 13'01---1-----1- -> 1 3'100
+ 20: 1 13'000---0------ -> 1 3'100
+ 21: 1 13'0-1--0------- -> 1 3'100
+ 22: 1 13'01---0------- -> 1 3'100
+ 23: 1 13'1------------ -> 1 3'100
+ 24: 1 13'0-11-1------0 -> 2 3'100
+ 25: 1 13'01---1--1--0- -> 2 3'100
+ 26: 2 13'0-1--1----1-0 -> 0 3'010
+ 27: 2 13'01---1-1---0- -> 0 3'010
+ 28: 2 13'0-----1------ -> 0 3'010
+ 29: 2 13'0-1-11------0 -> 1 3'010
+ 30: 2 13'01---1---1-0- -> 1 3'010
+ 31: 2 13'0-11-1------0 -> 2 3'010
+ 32: 2 13'0-1--1------1 -> 2 3'010
+ 33: 2 13'01---1--1--0- -> 2 3'010
+ 34: 2 13'01---1-----1- -> 2 3'010
+ 35: 2 13'000---0------ -> 2 3'010
+ 36: 2 13'0-1--0------- -> 2 3'010
+ 37: 2 13'01---0------- -> 2 3'010
+ 38: 2 13'1------------ -> 2 3'010
+
+-------------------------------------
+
+FSM `$fsm$\softshell.cpus[2].core.cpu.state$17273' from module `user_proj_example':
+-------------------------------------
+
+ Information on FSM $fsm$\softshell.cpus[2].core.cpu.state$17273 (\softshell.cpus[2].core.cpu.state):
+
+ Number of input signals: 3
+ Number of output signals: 3
+ Number of state bits: 3
+
+ Input signals:
+ 0: \softshell.cpus[2].core.cpu.picorv32_core.mem_valid
+ 1: \softshell.cpus[2].core.cpu.wbm_ack_i
+ 2: \softshell.cpus[2].core.cpu.wb_rst_i
+
+ Output signals:
+ 0: $flatten\softshell.\cpus[2].core.\cpu.$procmux$5328_CMP
+ 1: $flatten\softshell.\cpus[2].core.\cpu.$procmux$5321_CMP
+ 2: $flatten\softshell.\cpus[2].core.\cpu.$procmux$5315_CMP
+
+ State encoding:
+ 0: 3'--1 <RESET STATE>
+ 1: 3'-1-
+ 2: 3'1--
+
+ Transition Table (state_in, ctrl_in, state_out, ctrl_out):
+ 0: 0 3'0-0 -> 0 3'001
+ 1: 0 3'1-- -> 0 3'001
+ 2: 0 3'0-1 -> 2 3'001
+ 3: 1 3'--- -> 0 3'010
+ 4: 2 3'1-- -> 0 3'100
+ 5: 2 3'01- -> 1 3'100
+ 6: 2 3'00- -> 2 3'100
+
+-------------------------------------
+
+FSM `$fsm$\softshell.flash.spimemio.state$17278' from module `user_proj_example':
+-------------------------------------
+
+ Information on FSM $fsm$\softshell.flash.spimemio.state$17278 (\softshell.flash.spimemio.state):
+
+ Number of input signals: 8
+ Number of output signals: 13
+ Number of state bits: 13
+
+ Input signals:
+ 0: \softshell.flash.spimemio.xfer.din_ready
+ 1: $flatten\softshell.\flash.\spimemio.$logic_or$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/spimemio.v:512$714_Y
+ 2: $flatten\softshell.\flash.\spimemio.$logic_or$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/spimemio.v:472$710_Y
+ 3: $flatten\softshell.\flash.\spimemio.$logic_or$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/spimemio.v:373$696_Y
+ 4: $flatten\softshell.\flash.\spimemio.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/spimemio.v:216$617_Y
+ 5: \softshell.flash.spimemio.config_cont
+ 6: \softshell.flash.spimemio.jump
+ 7: \softshell.flash.spimemio.dout_valid
+
+ Output signals:
+ 0: $flatten\softshell.\flash.\spimemio.$procmux$8802_CMP
+ 1: $flatten\softshell.\flash.\spimemio.$procmux$8796_CMP
+ 2: $flatten\softshell.\flash.\spimemio.$procmux$8790_CMP
+ 3: $flatten\softshell.\flash.\spimemio.$procmux$8787_CMP
+ 4: $flatten\softshell.\flash.\spimemio.$procmux$8782_CMP
+ 5: $flatten\softshell.\flash.\spimemio.$procmux$8779_CMP
+ 6: $flatten\softshell.\flash.\spimemio.$procmux$8776_CMP
+ 7: $flatten\softshell.\flash.\spimemio.$procmux$8773_CMP
+ 8: $flatten\softshell.\flash.\spimemio.$procmux$8770_CMP
+ 9: $flatten\softshell.\flash.\spimemio.$procmux$8767_CMP
+ 10: $flatten\softshell.\flash.\spimemio.$procmux$8764_CMP
+ 11: $flatten\softshell.\flash.\spimemio.$procmux$8753_CMP
+ 12: $flatten\softshell.\flash.\spimemio.$procmux$8750_CMP
+
+ State encoding:
+ 0: 13'------------1 <RESET STATE>
+ 1: 13'-----------1-
+ 2: 13'----------1--
+ 3: 13'---------1---
+ 4: 13'--------1----
+ 5: 13'-------1-----
+ 6: 13'------1------
+ 7: 13'-----1-------
+ 8: 13'----1--------
+ 9: 13'---1---------
+ 10: 13'--1----------
+ 11: 13'-1-----------
+ 12: 13'1------------
+
+ Transition Table (state_in, ctrl_in, state_out, ctrl_out):
+ 0: 0 8'-0--0--0 -> 0 13'0000000000001
+ 1: 0 8'----1--- -> 0 13'0000000000001
+ 2: 0 8'-10-0--- -> 2 13'0000000000001
+ 3: 0 8'-0--0--1 -> 7 13'0000000000001
+ 4: 0 8'-11-0--- -> 9 13'0000000000001
+ 5: 1 8'----1--- -> 0 13'0000001000000
+ 6: 1 8'-0--0--0 -> 1 13'0000001000000
+ 7: 1 8'-10-0--- -> 2 13'0000001000000
+ 8: 1 8'-0--0--1 -> 8 13'0000001000000
+ 9: 1 8'-11-0--- -> 9 13'0000001000000
+ 10: 2 8'----1--- -> 0 13'0000000000100
+ 11: 2 8'-0--0--0 -> 2 13'0000000000100
+ 12: 2 8'-10-0--- -> 2 13'0000000000100
+ 13: 2 8'-0--0--1 -> 9 13'0000000000100
+ 14: 2 8'-11-0--- -> 9 13'0000000000100
+ 15: 3 8'----1--- -> 0 13'0010000000000
+ 16: 3 8'-10-0--- -> 2 13'0010000000000
+ 17: 3 8'-0--0-10 -> 3 13'0010000000000
+ 18: 3 8'-0--0-0- -> 3 13'0010000000000
+ 19: 3 8'-0--0-11 -> 8 13'0010000000000
+ 20: 3 8'-11-0--- -> 9 13'0010000000000
+ 21: 4 8'----1--- -> 0 13'0000000000010
+ 22: 4 8'-10-0--- -> 2 13'0000000000010
+ 23: 4 8'-0--0--0 -> 4 13'0000000000010
+ 24: 4 8'-11-0--- -> 9 13'0000000000010
+ 25: 4 8'-0--0--1 -> 10 13'0000000000010
+ 26: 5 8'----1--- -> 0 13'0000100000000
+ 27: 5 8'-10-0--- -> 2 13'0000100000000
+ 28: 5 8'-0--0--0 -> 5 13'0000100000000
+ 29: 5 8'-11-0--- -> 9 13'0000100000000
+ 30: 5 8'-0--0--1 -> 11 13'0000100000000
+ 31: 6 8'----1--- -> 0 13'0000000010000
+ 32: 6 8'-10-0--- -> 2 13'0000000010000
+ 33: 6 8'-0--0--0 -> 6 13'0000000010000
+ 34: 6 8'-11-0--- -> 9 13'0000000010000
+ 35: 6 8'-0--0--1 -> 12 13'0000000010000
+ 36: 7 8'----1--- -> 0 13'0100000000000
+ 37: 7 8'-10-0--- -> 2 13'0100000000000
+ 38: 7 8'10--0--- -> 4 13'0100000000000
+ 39: 7 8'00--0--- -> 7 13'0100000000000
+ 40: 7 8'-11-0--- -> 9 13'0100000000000
+ 41: 8 8'----1--- -> 0 13'0000010000000
+ 42: 8 8'-10-0--- -> 2 13'0000010000000
+ 43: 8 8'-0--0--1 -> 5 13'0000010000000
+ 44: 8 8'-0--0--0 -> 8 13'0000010000000
+ 45: 8 8'-11-0--- -> 9 13'0000010000000
+ 46: 9 8'----1--- -> 0 13'0000000001000
+ 47: 9 8'-10-0--- -> 2 13'0000000001000
+ 48: 9 8'-0-10--1 -> 6 13'0000000001000
+ 49: 9 8'-0-10--0 -> 9 13'0000000001000
+ 50: 9 8'-0-00--- -> 9 13'0000000001000
+ 51: 9 8'-11-0--- -> 9 13'0000000001000
+ 52: 10 8'----1--- -> 0 13'1000000000000
+ 53: 10 8'-10-0--- -> 2 13'1000000000000
+ 54: 10 8'10--0--- -> 2 13'1000000000000
+ 55: 10 8'-11-0--- -> 9 13'1000000000000
+ 56: 10 8'00--0--- -> 10 13'1000000000000
+ 57: 11 8'----1--- -> 0 13'0001000000000
+ 58: 11 8'-10-0--- -> 2 13'0001000000000
+ 59: 11 8'-0--0--1 -> 3 13'0001000000000
+ 60: 11 8'-11-0--- -> 9 13'0001000000000
+ 61: 11 8'-0--0--0 -> 11 13'0001000000000
+ 62: 12 8'----1--- -> 0 13'0000000100000
+ 63: 12 8'-0--01-1 -> 1 13'0000000100000
+ 64: 12 8'-10-0--- -> 2 13'0000000100000
+ 65: 12 8'-0--00-1 -> 8 13'0000000100000
+ 66: 12 8'-11-0--- -> 9 13'0000000100000
+ 67: 12 8'-0--0--0 -> 12 13'0000000100000
+
+-------------------------------------
+
+23.8.8. Executing FSM_MAP pass (mapping FSMs to basic logic).
+Mapping FSM `$fsm$\softshell.cpus[0].core.cpu.picorv32_core.cpu_state$17218' from module `\user_proj_example'.
+Mapping FSM `$fsm$\softshell.cpus[0].core.cpu.picorv32_core.mem_wordsize$17228' from module `\user_proj_example'.
+Mapping FSM `$fsm$\softshell.cpus[0].core.cpu.state$17233' from module `\user_proj_example'.
+Mapping FSM `$fsm$\softshell.cpus[1].core.cpu.picorv32_core.cpu_state$17238' from module `\user_proj_example'.
+Mapping FSM `$fsm$\softshell.cpus[1].core.cpu.picorv32_core.mem_wordsize$17248' from module `\user_proj_example'.
+Mapping FSM `$fsm$\softshell.cpus[1].core.cpu.state$17253' from module `\user_proj_example'.
+Mapping FSM `$fsm$\softshell.cpus[2].core.cpu.picorv32_core.cpu_state$17258' from module `\user_proj_example'.
+Mapping FSM `$fsm$\softshell.cpus[2].core.cpu.picorv32_core.mem_wordsize$17268' from module `\user_proj_example'.
+Mapping FSM `$fsm$\softshell.cpus[2].core.cpu.state$17273' from module `\user_proj_example'.
+Mapping FSM `$fsm$\softshell.flash.spimemio.state$17278' from module `\user_proj_example'.
+
+23.9. Executing OPT pass (performing simple optimizations).
+
+23.9.1. Executing OPT_EXPR pass (perform const folding).
+Optimizing module user_proj_example.
+<suppressed ~65 debug messages>
+
+23.9.2. Executing OPT_MERGE pass (detect identical cells).
+Finding identical cells in module `\user_proj_example'.
+<suppressed ~276 debug messages>
+Removed a total of 92 cells.
+
+23.9.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
+Running muxtree optimizer on module \user_proj_example..
+ Creating internal representation of mux trees.
+ Evaluating internal representation of mux trees.
+ Analyzing evaluation results.
+ dead port 2/7 on $pmux $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$6254.
+ dead port 4/7 on $pmux $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$6254.
+ dead port 1/2 on $mux $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$6257.
+ dead port 2/2 on $mux $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$6257.
+ dead port 1/2 on $mux $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$6267.
+ dead port 2/2 on $mux $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$6267.
+ dead port 1/2 on $mux $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$6308.
+ dead port 2/2 on $mux $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$6308.
+ dead port 1/2 on $mux $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$6311.
+ dead port 2/2 on $mux $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$6311.
+ dead port 1/4 on $pmux $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$6313.
+ dead port 2/4 on $pmux $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$6313.
+ dead port 3/6 on $pmux $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$6501.
+ dead port 1/2 on $mux $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$6517.
+ dead port 2/2 on $mux $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$6517.
+ dead port 1/2 on $mux $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$6783.
+ dead port 2/2 on $mux $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$6783.
+ dead port 1/5 on $pmux $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$6785.
+ dead port 2/5 on $pmux $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$6785.
+ dead port 1/3 on $pmux $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$6795.
+ dead port 2/3 on $pmux $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$6795.
+ dead port 3/3 on $pmux $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$6795.
+ dead port 1/3 on $pmux $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$6992.
+ dead port 3/5 on $pmux $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$7017.
+ dead port 1/4 on $pmux $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$7026.
+ dead port 2/4 on $pmux $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$7026.
+ dead port 3/4 on $pmux $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$7026.
+ dead port 4/4 on $pmux $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$7026.
+ dead port 1/4 on $pmux $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$7031.
+ dead port 2/4 on $pmux $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$7031.
+ dead port 3/4 on $pmux $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$7031.
+ dead port 4/4 on $pmux $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$7031.
+ dead port 1/2 on $mux $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$7035.
+ dead port 2/2 on $mux $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$7035.
+ dead port 1/2 on $mux $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$7038.
+ dead port 2/2 on $mux $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$7038.
+ dead port 3/6 on $pmux $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10147.
+ dead port 1/2 on $mux $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10163.
+ dead port 2/2 on $mux $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10163.
+ dead port 1/2 on $mux $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10429.
+ dead port 2/2 on $mux $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10429.
+ dead port 1/5 on $pmux $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10431.
+ dead port 2/5 on $pmux $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10431.
+ dead port 1/3 on $pmux $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10441.
+ dead port 2/3 on $pmux $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10441.
+ dead port 3/3 on $pmux $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10441.
+ dead port 1/3 on $pmux $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10638.
+ dead port 3/5 on $pmux $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10663.
+ dead port 1/4 on $pmux $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10672.
+ dead port 2/4 on $pmux $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10672.
+ dead port 3/4 on $pmux $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10672.
+ dead port 4/4 on $pmux $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10672.
+ dead port 1/4 on $pmux $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10677.
+ dead port 2/4 on $pmux $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10677.
+ dead port 3/4 on $pmux $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10677.
+ dead port 4/4 on $pmux $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10677.
+ dead port 1/2 on $mux $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10681.
+ dead port 2/2 on $mux $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10681.
+ dead port 1/2 on $mux $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10684.
+ dead port 2/2 on $mux $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10684.
+ dead port 2/7 on $pmux $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$9900.
+ dead port 4/7 on $pmux $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$9900.
+ dead port 1/2 on $mux $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$9903.
+ dead port 2/2 on $mux $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$9903.
+ dead port 1/2 on $mux $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$9913.
+ dead port 2/2 on $mux $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$9913.
+ dead port 1/2 on $mux $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$9954.
+ dead port 2/2 on $mux $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$9954.
+ dead port 1/2 on $mux $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$9957.
+ dead port 2/2 on $mux $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$9957.
+ dead port 1/4 on $pmux $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$9959.
+ dead port 2/4 on $pmux $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$9959.
+ dead port 2/7 on $pmux $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$12765.
+ dead port 4/7 on $pmux $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$12765.
+ dead port 1/2 on $mux $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$12768.
+ dead port 2/2 on $mux $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$12768.
+ dead port 1/2 on $mux $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$12778.
+ dead port 2/2 on $mux $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$12778.
+ dead port 1/2 on $mux $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$12819.
+ dead port 2/2 on $mux $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$12819.
+ dead port 1/2 on $mux $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$12822.
+ dead port 2/2 on $mux $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$12822.
+ dead port 1/4 on $pmux $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$12824.
+ dead port 2/4 on $pmux $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$12824.
+ dead port 3/6 on $pmux $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$13012.
+ dead port 1/2 on $mux $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$13028.
+ dead port 2/2 on $mux $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$13028.
+ dead port 1/2 on $mux $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$13294.
+ dead port 2/2 on $mux $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$13294.
+ dead port 1/5 on $pmux $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$13296.
+ dead port 2/5 on $pmux $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$13296.
+ dead port 1/3 on $pmux $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$13306.
+ dead port 2/3 on $pmux $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$13306.
+ dead port 3/3 on $pmux $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$13306.
+ dead port 1/3 on $pmux $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$13503.
+ dead port 3/5 on $pmux $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$13528.
+ dead port 1/4 on $pmux $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$13537.
+ dead port 2/4 on $pmux $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$13537.
+ dead port 3/4 on $pmux $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$13537.
+ dead port 4/4 on $pmux $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$13537.
+ dead port 1/4 on $pmux $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$13542.
+ dead port 2/4 on $pmux $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$13542.
+ dead port 3/4 on $pmux $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$13542.
+ dead port 4/4 on $pmux $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$13542.
+ dead port 1/2 on $mux $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$13546.
+ dead port 2/2 on $mux $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$13546.
+ dead port 1/2 on $mux $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$13549.
+ dead port 2/2 on $mux $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$13549.
+Removed 108 multiplexer ports.
+<suppressed ~821 debug messages>
+
+23.9.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
+ Optimizing cells in module \user_proj_example.
+ New input vector for $reduce_or cell $auto$opt_reduce.cc:128:opt_mux$17062: { \softshell.cpus[2].core.cpu.picorv32_core.cpu_state [5:4] \softshell.cpus[2].core.cpu.picorv32_core.cpu_state [2:0] }
+ New input vector for $reduce_or cell $auto$opt_reduce.cc:128:opt_mux$17060: \softshell.cpus[2].core.cpu.picorv32_core.cpu_state [4:0]
+ New input vector for $reduce_or cell $auto$opt_reduce.cc:128:opt_mux$17058: { \softshell.cpus[2].core.cpu.picorv32_core.cpu_state [5] \softshell.cpus[2].core.cpu.picorv32_core.cpu_state [3:0] }
+ New input vector for $reduce_or cell $auto$opt_reduce.cc:128:opt_mux$17052: { \softshell.cpus[2].core.cpu.picorv32_core.cpu_state [5:2] \softshell.cpus[2].core.cpu.picorv32_core.cpu_state [0] }
+ New input vector for $reduce_or cell $auto$opt_reduce.cc:128:opt_mux$17050: { \softshell.cpus[2].core.cpu.picorv32_core.cpu_state [5:3] \softshell.cpus[2].core.cpu.picorv32_core.cpu_state [0] }
+ New input vector for $reduce_or cell $auto$opt_reduce.cc:128:opt_mux$17032: { \softshell.cpus[0].core.cpu.picorv32_core.cpu_state [5:4] \softshell.cpus[0].core.cpu.picorv32_core.cpu_state [2:0] }
+ New input vector for $reduce_or cell $auto$opt_reduce.cc:128:opt_mux$17030: { \softshell.cpus[1].core.cpu.picorv32_core.cpu_state [5:4] \softshell.cpus[1].core.cpu.picorv32_core.cpu_state [2:0] }
+ New input vector for $reduce_or cell $auto$opt_reduce.cc:128:opt_mux$17026: \softshell.cpus[0].core.cpu.picorv32_core.cpu_state [4:0]
+ New input vector for $reduce_or cell $auto$opt_reduce.cc:128:opt_mux$17024: \softshell.cpus[1].core.cpu.picorv32_core.cpu_state [4:0]
+ New input vector for $reduce_or cell $auto$opt_reduce.cc:128:opt_mux$17022: { \softshell.cpus[0].core.cpu.picorv32_core.cpu_state [5] \softshell.cpus[0].core.cpu.picorv32_core.cpu_state [3:0] }
+ New input vector for $reduce_or cell $auto$opt_reduce.cc:128:opt_mux$17020: { \softshell.cpus[1].core.cpu.picorv32_core.cpu_state [5] \softshell.cpus[1].core.cpu.picorv32_core.cpu_state [3:0] }
+ New input vector for $reduce_or cell $auto$opt_reduce.cc:128:opt_mux$17008: { \softshell.cpus[1].core.cpu.picorv32_core.cpu_state [5:2] \softshell.cpus[1].core.cpu.picorv32_core.cpu_state [0] }
+ New input vector for $reduce_or cell $auto$opt_reduce.cc:128:opt_mux$17004: { \softshell.cpus[1].core.cpu.picorv32_core.cpu_state [5:3] \softshell.cpus[1].core.cpu.picorv32_core.cpu_state [0] }
+ New input vector for $reduce_or cell $auto$opt_reduce.cc:128:opt_mux$16982: { \softshell.cpus[0].core.cpu.picorv32_core.cpu_state [5:2] \softshell.cpus[0].core.cpu.picorv32_core.cpu_state [0] }
+ New input vector for $reduce_or cell $auto$opt_reduce.cc:128:opt_mux$16976: { \softshell.cpus[0].core.cpu.picorv32_core.cpu_state [5:3] \softshell.cpus[0].core.cpu.picorv32_core.cpu_state [0] }
+ Optimizing cells in module \user_proj_example.
+Performed a total of 15 changes.
+
+23.9.5. Executing OPT_MERGE pass (detect identical cells).
+Finding identical cells in module `\user_proj_example'.
+Removed a total of 0 cells.
+
+23.9.6. Executing OPT_DFF pass (perform DFF optimizations).
+Adding SRST signal on $flatten\softshell.\uart0.\simpleuart.$procdff$16535 ($dff) from module user_proj_example (D = { $flatten\softshell.\uart0.\simpleuart.$procmux$9136_Y $flatten\softshell.\uart0.\simpleuart.$procmux$9141_Y $flatten\softshell.\uart0.\simpleuart.$procmux$9146_Y $flatten\softshell.\uart0.\simpleuart.$procmux$9151_Y }, Q = \softshell.uart0.simpleuart.cfg_divider, rval = 1).
+Adding EN signal on $auto$opt_dff.cc:702:run$19271 ($sdff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.uart0.simpleuart.cfg_divider [7:0]).
+Adding EN signal on $auto$opt_dff.cc:702:run$19271 ($sdff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.uart0.simpleuart.cfg_divider [15:8]).
+Adding EN signal on $auto$opt_dff.cc:702:run$19271 ($sdff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.uart0.simpleuart.cfg_divider [23:16]).
+Adding EN signal on $auto$opt_dff.cc:702:run$19271 ($sdff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.uart0.simpleuart.cfg_divider [31:24]).
+Adding SRST signal on $flatten\softshell.\uart0.\simpleuart.$procdff$16534 ($dff) from module user_proj_example (D = $flatten\softshell.\uart0.\simpleuart.$procmux$9156_Y, Q = \softshell.uart0.simpleuart.enabled, rval = 1'0).
+Adding EN signal on $auto$opt_dff.cc:702:run$19276 ($sdff) from module user_proj_example (D = \softshell.flash.spimemio.cfgreg_di [0], Q = \softshell.uart0.simpleuart.enabled).
+Adding SRST signal on $flatten\softshell.\uart0.\simpleuart.$procdff$16533 ($dff) from module user_proj_example (D = $flatten\softshell.\uart0.\simpleuart.$procmux$9097_Y, Q = \softshell.uart0.simpleuart.recv_buf_valid, rval = 1'0).
+Adding SRST signal on $flatten\softshell.\uart0.\simpleuart.$procdff$16532 ($dff) from module user_proj_example (D = $flatten\softshell.\uart0.\simpleuart.$procmux$9105_Y, Q = \softshell.uart0.simpleuart.recv_buf_data, rval = 8'00000000).
+Adding EN signal on $auto$opt_dff.cc:702:run$19279 ($sdff) from module user_proj_example (D = \softshell.uart0.simpleuart.recv_pattern, Q = \softshell.uart0.simpleuart.recv_buf_data).
+Adding SRST signal on $flatten\softshell.\uart0.\simpleuart.$procdff$16531 ($dff) from module user_proj_example (D = $flatten\softshell.\uart0.\simpleuart.$procmux$9113_Y, Q = \softshell.uart0.simpleuart.recv_pattern, rval = 8'00000000).
+Adding EN signal on $auto$opt_dff.cc:702:run$19283 ($sdff) from module user_proj_example (D = { \softshell.uart0.simpleuart.ser_rx \softshell.uart0.simpleuart.recv_pattern [7:1] }, Q = \softshell.uart0.simpleuart.recv_pattern).
+Adding SRST signal on $flatten\softshell.\uart0.\simpleuart.$procdff$16530 ($dff) from module user_proj_example (D = $flatten\softshell.\uart0.\simpleuart.$procmux$9083_Y, Q = \softshell.uart0.simpleuart.recv_divcnt, rval = 0).
+Adding SRST signal on $flatten\softshell.\uart0.\simpleuart.$procdff$16529 ($dff) from module user_proj_example (D = $flatten\softshell.\uart0.\simpleuart.$procmux$9125_Y, Q = \softshell.uart0.simpleuart.recv_state, rval = 4'0000).
+Adding EN signal on $auto$opt_dff.cc:702:run$19290 ($sdff) from module user_proj_example (D = $flatten\softshell.\uart0.\simpleuart.$procmux$9125_Y, Q = \softshell.uart0.simpleuart.recv_state).
+Adding SRST signal on $flatten\softshell.\uart0.\simpleuart.$procdff$16528 ($dff) from module user_proj_example (D = $flatten\softshell.\uart0.\simpleuart.$procmux$9053_Y, Q = \softshell.uart0.simpleuart.send_dummy, rval = 1'1).
+Adding EN signal on $auto$opt_dff.cc:702:run$19302 ($sdff) from module user_proj_example (D = $flatten\softshell.\uart0.\simpleuart.$procmux$9053_Y, Q = \softshell.uart0.simpleuart.send_dummy).
+Adding SRST signal on $flatten\softshell.\uart0.\simpleuart.$procdff$16527 ($dff) from module user_proj_example (D = $flatten\softshell.\uart0.\simpleuart.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/simpleuart.v:197$599_Y, Q = \softshell.uart0.simpleuart.send_divcnt, rval = 0).
+Adding SRST signal on $flatten\softshell.\uart0.\simpleuart.$procdff$16526 ($dff) from module user_proj_example (D = $flatten\softshell.\uart0.\simpleuart.$procmux$9064_Y, Q = \softshell.uart0.simpleuart.send_bitcnt, rval = 4'0000).
+Adding EN signal on $auto$opt_dff.cc:702:run$19309 ($sdff) from module user_proj_example (D = $flatten\softshell.\uart0.\simpleuart.$procmux$9064_Y, Q = \softshell.uart0.simpleuart.send_bitcnt).
+Adding SRST signal on $flatten\softshell.\uart0.\simpleuart.$procdff$16525 ($dff) from module user_proj_example (D = $flatten\softshell.\uart0.\simpleuart.$procmux$9069_Y [9], Q = \softshell.uart0.simpleuart.send_pattern [9], rval = 1'1).
+Adding SRST signal on $flatten\softshell.\uart0.\simpleuart.$procdff$16525 ($dff) from module user_proj_example (D = $flatten\softshell.\uart0.\simpleuart.$procmux$9072_Y [8:0], Q = \softshell.uart0.simpleuart.send_pattern [8:0], rval = 9'111111111).
+Adding EN signal on $auto$opt_dff.cc:702:run$19318 ($sdff) from module user_proj_example (D = $flatten\softshell.\uart0.\simpleuart.$procmux$9072_Y [8:0], Q = \softshell.uart0.simpleuart.send_pattern [8:0]).
+Adding EN signal on $auto$opt_dff.cc:702:run$19315 ($sdff) from module user_proj_example (D = 1'1, Q = \softshell.uart0.simpleuart.send_pattern [9]).
+Setting constant 1-bit at position 0 on $auto$opt_dff.cc:764:run$19322 ($sdffe) from module user_proj_example.
+Adding EN signal on $flatten\softshell.\shared_mem.\ram.$procdff$16853 ($dff) from module user_proj_example (D = { $flatten\softshell.\shared_mem.\ram.$memrd$\ram3$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:119$2783_DATA $flatten\softshell.\shared_mem.\ram.$memrd$\ram2$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:118$2782_DATA $flatten\softshell.\shared_mem.\ram.$memrd$\ram1$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:117$2781_DATA $flatten\softshell.\shared_mem.\ram.$memrd$\ram0$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:116$2780_DATA }, Q = \softshell.shared_mem.ram.dout).
+Adding SRST signal on $flatten\softshell.\shared_mem.$procdff$16867 ($dff) from module user_proj_example (D = $flatten\softshell.\shared_mem.$and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:50$1939_Y, Q = \softshell.shared_mem.wb_ack_read, rval = 1'0).
+Adding SRST signal on $flatten\softshell.\shared_mem.$procdff$16866 ($dff) from module user_proj_example (D = $flatten\softshell.\shared_mem.$ternary$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:49$1935_Y, Q = \softshell.shared_mem.wb_ack_o, rval = 1'0).
+Adding EN signal on $flatten\softshell.\pinmux.$procdff$16903 ($adff) from module user_proj_example (D = \softshell.flash.spimemio.cfgreg_di [4:0], Q = \softshell.pinmux.reg_mux_out[31]).
+Adding EN signal on $flatten\softshell.\pinmux.$procdff$16902 ($adff) from module user_proj_example (D = \softshell.flash.spimemio.cfgreg_di [4:0], Q = \softshell.pinmux.reg_mux_out[30]).
+Adding EN signal on $flatten\softshell.\pinmux.$procdff$16901 ($adff) from module user_proj_example (D = \softshell.flash.spimemio.cfgreg_di [4:0], Q = \softshell.pinmux.reg_mux_out[29]).
+Adding EN signal on $flatten\softshell.\pinmux.$procdff$16900 ($adff) from module user_proj_example (D = \softshell.flash.spimemio.cfgreg_di [4:0], Q = \softshell.pinmux.reg_mux_out[28]).
+Adding EN signal on $flatten\softshell.\pinmux.$procdff$16899 ($adff) from module user_proj_example (D = \softshell.flash.spimemio.cfgreg_di [4:0], Q = \softshell.pinmux.reg_mux_out[27]).
+Adding EN signal on $flatten\softshell.\pinmux.$procdff$16898 ($adff) from module user_proj_example (D = \softshell.flash.spimemio.cfgreg_di [4:0], Q = \softshell.pinmux.reg_mux_out[26]).
+Adding EN signal on $flatten\softshell.\pinmux.$procdff$16897 ($adff) from module user_proj_example (D = \softshell.flash.spimemio.cfgreg_di [4:0], Q = \softshell.pinmux.reg_mux_out[25]).
+Adding EN signal on $flatten\softshell.\pinmux.$procdff$16896 ($adff) from module user_proj_example (D = \softshell.flash.spimemio.cfgreg_di [4:0], Q = \softshell.pinmux.reg_mux_out[24]).
+Adding EN signal on $flatten\softshell.\pinmux.$procdff$16895 ($adff) from module user_proj_example (D = \softshell.flash.spimemio.cfgreg_di [4:0], Q = \softshell.pinmux.reg_mux_out[23]).
+Adding EN signal on $flatten\softshell.\pinmux.$procdff$16894 ($adff) from module user_proj_example (D = \softshell.flash.spimemio.cfgreg_di [4:0], Q = \softshell.pinmux.reg_mux_out[22]).
+Adding EN signal on $flatten\softshell.\pinmux.$procdff$16893 ($adff) from module user_proj_example (D = \softshell.flash.spimemio.cfgreg_di [4:0], Q = \softshell.pinmux.reg_mux_out[21]).
+Adding EN signal on $flatten\softshell.\pinmux.$procdff$16892 ($adff) from module user_proj_example (D = \softshell.flash.spimemio.cfgreg_di [4:0], Q = \softshell.pinmux.reg_mux_out[20]).
+Adding EN signal on $flatten\softshell.\pinmux.$procdff$16891 ($adff) from module user_proj_example (D = \softshell.flash.spimemio.cfgreg_di [4:0], Q = \softshell.pinmux.reg_mux_out[19]).
+Adding EN signal on $flatten\softshell.\pinmux.$procdff$16890 ($adff) from module user_proj_example (D = \softshell.flash.spimemio.cfgreg_di [4:0], Q = \softshell.pinmux.reg_mux_out[18]).
+Adding EN signal on $flatten\softshell.\pinmux.$procdff$16889 ($adff) from module user_proj_example (D = \softshell.flash.spimemio.cfgreg_di [4:0], Q = \softshell.pinmux.reg_mux_out[17]).
+Adding EN signal on $flatten\softshell.\pinmux.$procdff$16888 ($adff) from module user_proj_example (D = \softshell.flash.spimemio.cfgreg_di [4:0], Q = \softshell.pinmux.reg_mux_out[16]).
+Adding EN signal on $flatten\softshell.\pinmux.$procdff$16887 ($adff) from module user_proj_example (D = \softshell.flash.spimemio.cfgreg_di [4:0], Q = \softshell.pinmux.reg_mux_out[15]).
+Adding EN signal on $flatten\softshell.\pinmux.$procdff$16886 ($adff) from module user_proj_example (D = \softshell.flash.spimemio.cfgreg_di [4:0], Q = \softshell.pinmux.reg_mux_out[14]).
+Adding EN signal on $flatten\softshell.\pinmux.$procdff$16885 ($adff) from module user_proj_example (D = \softshell.flash.spimemio.cfgreg_di [4:0], Q = \softshell.pinmux.reg_mux_out[13]).
+Adding EN signal on $flatten\softshell.\pinmux.$procdff$16884 ($adff) from module user_proj_example (D = \softshell.flash.spimemio.cfgreg_di [4:0], Q = \softshell.pinmux.reg_mux_out[12]).
+Adding EN signal on $flatten\softshell.\pinmux.$procdff$16883 ($adff) from module user_proj_example (D = \softshell.flash.spimemio.cfgreg_di [4:0], Q = \softshell.pinmux.reg_mux_out[11]).
+Adding EN signal on $flatten\softshell.\pinmux.$procdff$16882 ($adff) from module user_proj_example (D = \softshell.flash.spimemio.cfgreg_di [4:0], Q = \softshell.pinmux.reg_mux_out[10]).
+Adding EN signal on $flatten\softshell.\pinmux.$procdff$16881 ($adff) from module user_proj_example (D = \softshell.flash.spimemio.cfgreg_di [4:0], Q = \softshell.pinmux.reg_mux_out[9]).
+Adding EN signal on $flatten\softshell.\pinmux.$procdff$16880 ($adff) from module user_proj_example (D = \softshell.flash.spimemio.cfgreg_di [4:0], Q = \softshell.pinmux.reg_mux_out[8]).
+Adding EN signal on $flatten\softshell.\pinmux.$procdff$16879 ($adff) from module user_proj_example (D = \softshell.flash.spimemio.cfgreg_di [4:0], Q = \softshell.pinmux.reg_mux_out[7]).
+Adding EN signal on $flatten\softshell.\pinmux.$procdff$16878 ($adff) from module user_proj_example (D = \softshell.flash.spimemio.cfgreg_di [4:0], Q = \softshell.pinmux.reg_mux_out[6]).
+Adding EN signal on $flatten\softshell.\pinmux.$procdff$16877 ($adff) from module user_proj_example (D = \softshell.flash.spimemio.cfgreg_di [4:0], Q = \softshell.pinmux.reg_mux_out[5]).
+Adding EN signal on $flatten\softshell.\pinmux.$procdff$16876 ($adff) from module user_proj_example (D = \softshell.flash.spimemio.cfgreg_di [4:0], Q = \softshell.pinmux.reg_mux_out[4]).
+Adding EN signal on $flatten\softshell.\pinmux.$procdff$16875 ($adff) from module user_proj_example (D = \softshell.flash.spimemio.cfgreg_di [4:0], Q = \softshell.pinmux.reg_mux_out[3]).
+Adding EN signal on $flatten\softshell.\pinmux.$procdff$16874 ($adff) from module user_proj_example (D = \softshell.flash.spimemio.cfgreg_di [4:0], Q = \softshell.pinmux.reg_mux_out[2]).
+Adding EN signal on $flatten\softshell.\pinmux.$procdff$16873 ($adff) from module user_proj_example (D = \softshell.flash.spimemio.cfgreg_di [4:0], Q = \softshell.pinmux.reg_mux_out[1]).
+Adding EN signal on $flatten\softshell.\pinmux.$procdff$16872 ($adff) from module user_proj_example (D = \softshell.flash.spimemio.cfgreg_di [4:0], Q = \softshell.pinmux.reg_mux_out[0]).
+Adding EN signal on $flatten\softshell.\pinmux.$procdff$16871 ($adff) from module user_proj_example (D = \softshell.flash.spimemio.cfgreg_di [5:0], Q = \softshell.pinmux.reg_mux_in[0]).
+Adding EN signal on $flatten\softshell.\pinmux.$procdff$16869 ($adff) from module user_proj_example (D = $flatten\softshell.\pinmux.$procmux$16173_Y, Q = \softshell.pinmux.wb_dat_o).
+Adding SRST signal on $flatten\softshell.\flash.\spimemio.\xfer.$procdff$16493 ($dff) from module user_proj_example (D = \softshell.flash.spimemio.xfer.fetch, Q = \softshell.flash.spimemio.xfer.last_fetch, rval = 1'1).
+Adding SRST signal on $flatten\softshell.\flash.\spimemio.\xfer.$procdff$16492 ($dff) from module user_proj_example (D = \softshell.flash.spimemio.xfer.next_fetch, Q = \softshell.flash.spimemio.xfer.fetch, rval = 1'1).
+Adding SRST signal on $flatten\softshell.\flash.\spimemio.\xfer.$procdff$16491 ($dff) from module user_proj_example (D = $flatten\softshell.\flash.\spimemio.\xfer.$procmux$8386_Y, Q = \softshell.flash.spimemio.xfer.xfer_tag, rval = 4'0000).
+Adding EN signal on $auto$opt_dff.cc:702:run$19502 ($sdff) from module user_proj_example (D = \softshell.flash.spimemio.din_tag, Q = \softshell.flash.spimemio.xfer.xfer_tag).
+Adding SRST signal on $flatten\softshell.\flash.\spimemio.\xfer.$procdff$16490 ($dff) from module user_proj_example (D = $flatten\softshell.\flash.\spimemio.\xfer.$procmux$8391_Y, Q = \softshell.flash.spimemio.xfer.xfer_rd, rval = 1'0).
+Adding EN signal on $auto$opt_dff.cc:702:run$19504 ($sdff) from module user_proj_example (D = \softshell.flash.spimemio.din_rd, Q = \softshell.flash.spimemio.xfer.xfer_rd).
+Adding SRST signal on $flatten\softshell.\flash.\spimemio.\xfer.$procdff$16489 ($dff) from module user_proj_example (D = $flatten\softshell.\flash.\spimemio.\xfer.$procmux$8396_Y, Q = \softshell.flash.spimemio.xfer.xfer_qspi, rval = 1'0).
+Adding EN signal on $auto$opt_dff.cc:702:run$19506 ($sdff) from module user_proj_example (D = \softshell.flash.spimemio.din_qspi, Q = \softshell.flash.spimemio.xfer.xfer_qspi).
+Adding SRST signal on $flatten\softshell.\flash.\spimemio.\xfer.$procdff$16487 ($dff) from module user_proj_example (D = $flatten\softshell.\flash.\spimemio.\xfer.$procmux$8409_Y, Q = \softshell.flash.spimemio.xfer.dummy_count, rval = 4'0000).
+Adding EN signal on $auto$opt_dff.cc:702:run$19508 ($sdff) from module user_proj_example (D = $flatten\softshell.\flash.\spimemio.\xfer.$procmux$8409_Y, Q = \softshell.flash.spimemio.xfer.dummy_count).
+Adding SRST signal on $flatten\softshell.\flash.\spimemio.\xfer.$procdff$16486 ($dff) from module user_proj_example (D = $flatten\softshell.\flash.\spimemio.\xfer.$procmux$8419_Y [3], Q = \softshell.flash.spimemio.xfer.count [3], rval = 1'0).
+Adding SRST signal on $flatten\softshell.\flash.\spimemio.\xfer.$procdff$16486 ($dff) from module user_proj_example (D = $flatten\softshell.\flash.\spimemio.\xfer.$procmux$8417_Y [2:0], Q = \softshell.flash.spimemio.xfer.count [2:0], rval = 3'000).
+Adding EN signal on $auto$opt_dff.cc:702:run$19515 ($sdff) from module user_proj_example (D = $flatten\softshell.\flash.\spimemio.\xfer.$2\next_count[3:0] [2:0], Q = \softshell.flash.spimemio.xfer.count [2:0]).
+Adding EN signal on $auto$opt_dff.cc:702:run$19512 ($sdff) from module user_proj_example (D = $flatten\softshell.\flash.\spimemio.\xfer.$procmux$8419_Y [3], Q = \softshell.flash.spimemio.xfer.count [3]).
+Adding EN signal on $flatten\softshell.\flash.\spimemio.\xfer.$procdff$16485 ($dff) from module user_proj_example (D = $flatten\softshell.\flash.\spimemio.\xfer.$2\next_ibuffer[7:0], Q = \softshell.flash.spimemio.xfer.ibuffer).
+Adding EN signal on $flatten\softshell.\flash.\spimemio.\xfer.$procdff$16484 ($dff) from module user_proj_example (D = $flatten\softshell.\flash.\spimemio.\xfer.$procmux$8437_Y, Q = \softshell.flash.spimemio.xfer.obuffer).
+Adding SRST signal on $flatten\softshell.\flash.\spimemio.\xfer.$procdff$16483 ($dff) from module user_proj_example (D = $flatten\softshell.\flash.\spimemio.\xfer.$procmux$8442_Y, Q = \softshell.flash.spimemio.xfer.xfer_ddr, rval = 1'0).
+Adding EN signal on $auto$opt_dff.cc:702:run$19568 ($sdff) from module user_proj_example (D = \softshell.flash.spimemio.xfer.din_ddr, Q = \softshell.flash.spimemio.xfer.xfer_ddr).
+Adding SRST signal on $flatten\softshell.\flash.\spimemio.\xfer.$procdff$16482 ($dff) from module user_proj_example (D = $flatten\softshell.\flash.\spimemio.\xfer.$procmux$8447_Y, Q = \softshell.flash.spimemio.xfer.xfer_dspi, rval = 1'0).
+Adding EN signal on $auto$opt_dff.cc:702:run$19570 ($sdff) from module user_proj_example (D = \softshell.flash.spimemio.xfer.din_dspi, Q = \softshell.flash.spimemio.xfer.xfer_dspi).
+Adding SRST signal on $flatten\softshell.\flash.\spimemio.\xfer.$procdff$16481 ($dff) from module user_proj_example (D = $flatten\softshell.\flash.\spimemio.\xfer.$procmux$8455_Y, Q = \softshell.flash.spimemio.xfer.flash_clk, rval = 1'0).
+Adding EN signal on $auto$opt_dff.cc:702:run$19574 ($sdff) from module user_proj_example (D = $flatten\softshell.\flash.\spimemio.\xfer.$procmux$8455_Y, Q = \softshell.flash.spimemio.xfer.flash_clk).
+Adding SRST signal on $flatten\softshell.\flash.\spimemio.\xfer.$procdff$16480 ($dff) from module user_proj_example (D = $flatten\softshell.\flash.\spimemio.\xfer.$procmux$8462_Y, Q = \softshell.flash.spimemio.xfer.flash_csb, rval = 1'1).
+Adding EN signal on $auto$opt_dff.cc:702:run$19578 ($sdff) from module user_proj_example (D = 1'0, Q = \softshell.flash.spimemio.xfer.flash_csb).
+Adding SRST signal on $flatten\softshell.\flash.\spimemio.$procdff$16524 ($dff) from module user_proj_example (D = $flatten\softshell.\flash.\spimemio.$procmux$8994_Y, Q = \softshell.flash.spimemio.config_do, rval = 4'0000).
+Adding EN signal on $auto$opt_dff.cc:702:run$19580 ($sdff) from module user_proj_example (D = \softshell.flash.spimemio.cfgreg_di [3:0], Q = \softshell.flash.spimemio.config_do).
+Adding SRST signal on $flatten\softshell.\flash.\spimemio.$procdff$16523 ($dff) from module user_proj_example (D = $flatten\softshell.\flash.\spimemio.$procmux$8999_Y, Q = \softshell.flash.spimemio.config_clk, rval = 1'0).
+Adding EN signal on $auto$opt_dff.cc:702:run$19582 ($sdff) from module user_proj_example (D = \softshell.flash.spimemio.cfgreg_di [4], Q = \softshell.flash.spimemio.config_clk).
+Adding SRST signal on $flatten\softshell.\flash.\spimemio.$procdff$16522 ($dff) from module user_proj_example (D = $flatten\softshell.\flash.\spimemio.$procmux$9004_Y, Q = \softshell.flash.spimemio.config_csb, rval = 1'0).
+Adding EN signal on $auto$opt_dff.cc:702:run$19584 ($sdff) from module user_proj_example (D = \softshell.flash.spimemio.cfgreg_di [5], Q = \softshell.flash.spimemio.config_csb).
+Adding SRST signal on $flatten\softshell.\flash.\spimemio.$procdff$16521 ($dff) from module user_proj_example (D = $flatten\softshell.\flash.\spimemio.$procmux$9009_Y, Q = \softshell.flash.spimemio.config_oe, rval = 4'0000).
+Adding EN signal on $auto$opt_dff.cc:702:run$19586 ($sdff) from module user_proj_example (D = \softshell.flash.spimemio.cfgreg_di [11:8], Q = \softshell.flash.spimemio.config_oe).
+Adding SRST signal on $flatten\softshell.\flash.\spimemio.$procdff$16520 ($dff) from module user_proj_example (D = $flatten\softshell.\flash.\spimemio.$procmux$9014_Y, Q = \softshell.flash.spimemio.config_dummy, rval = 4'1000).
+Adding EN signal on $auto$opt_dff.cc:702:run$19588 ($sdff) from module user_proj_example (D = \softshell.flash.spimemio.cfgreg_di [19:16], Q = \softshell.flash.spimemio.config_dummy).
+Adding SRST signal on $flatten\softshell.\flash.\spimemio.$procdff$16519 ($dff) from module user_proj_example (D = $flatten\softshell.\flash.\spimemio.$procmux$9019_Y, Q = \softshell.flash.spimemio.config_cont, rval = 1'0).
+Adding EN signal on $auto$opt_dff.cc:702:run$19590 ($sdff) from module user_proj_example (D = \softshell.flash.spimemio.cfgreg_di [20], Q = \softshell.flash.spimemio.config_cont).
+Adding SRST signal on $flatten\softshell.\flash.\spimemio.$procdff$16518 ($dff) from module user_proj_example (D = $flatten\softshell.\flash.\spimemio.$procmux$9024_Y, Q = \softshell.flash.spimemio.config_qspi, rval = 1'0).
+Adding EN signal on $auto$opt_dff.cc:702:run$19592 ($sdff) from module user_proj_example (D = \softshell.flash.spimemio.cfgreg_di [21], Q = \softshell.flash.spimemio.config_qspi).
+Adding SRST signal on $flatten\softshell.\flash.\spimemio.$procdff$16517 ($dff) from module user_proj_example (D = $flatten\softshell.\flash.\spimemio.$procmux$9029_Y, Q = \softshell.flash.spimemio.config_ddr, rval = 1'0).
+Adding EN signal on $auto$opt_dff.cc:702:run$19594 ($sdff) from module user_proj_example (D = \softshell.flash.spimemio.cfgreg_di [22], Q = \softshell.flash.spimemio.config_ddr).
+Adding SRST signal on $flatten\softshell.\flash.\spimemio.$procdff$16516 ($dff) from module user_proj_example (D = $flatten\softshell.\flash.\spimemio.$procmux$9034_Y, Q = \softshell.flash.spimemio.config_en, rval = 1'1).
+Adding EN signal on $auto$opt_dff.cc:702:run$19596 ($sdff) from module user_proj_example (D = \softshell.flash.spimemio.cfgreg_di [31], Q = \softshell.flash.spimemio.config_en).
+Adding SRST signal on $flatten\softshell.\flash.\spimemio.$procdff$16515 ($dff) from module user_proj_example (D = $flatten\softshell.\flash.\spimemio.$logic_or$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/spimemio.v:244$628_Y, Q = \softshell.flash.spimemio.softreset, rval = 1'1).
+Adding EN signal on $flatten\softshell.\flash.\spimemio.$procdff$16509 ($dff) from module user_proj_example (D = $flatten\softshell.\flash.\spimemio.$procmux$8823_Y, Q = \softshell.flash.spimemio.rd_inc).
+Adding SRST signal on $auto$opt_dff.cc:764:run$19605 ($dffe) from module user_proj_example (D = $flatten\softshell.\flash.\spimemio.$procmux$8811_Y, Q = \softshell.flash.spimemio.rd_inc, rval = 1'0).
+Adding EN signal on $flatten\softshell.\flash.\spimemio.$procdff$16508 ($dff) from module user_proj_example (D = $flatten\softshell.\flash.\spimemio.$procmux$8830_Y, Q = \softshell.flash.spimemio.rd_wait).
+Adding SRST signal on $auto$opt_dff.cc:764:run$19615 ($dffe) from module user_proj_example (D = $flatten\softshell.\flash.\spimemio.$procmux$8828_Y, Q = \softshell.flash.spimemio.rd_wait, rval = 1'0).
+Adding SRST signal on $flatten\softshell.\flash.\spimemio.$procdff$16507 ($dff) from module user_proj_example (D = $flatten\softshell.\flash.\spimemio.$procmux$8835_Y, Q = \softshell.flash.spimemio.rd_valid, rval = 1'0).
+Adding EN signal on $auto$opt_dff.cc:702:run$19619 ($sdff) from module user_proj_example (D = 1'1, Q = \softshell.flash.spimemio.rd_valid).
+Adding EN signal on $flatten\softshell.\flash.\spimemio.$procdff$16506 ($dff) from module user_proj_example (D = $flatten\softshell.\flash.\spimemio.$ternary$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/spimemio.v:388$707_Y [23:0], Q = \softshell.flash.spimemio.rd_addr).
+Adding EN signal on $flatten\softshell.\flash.\spimemio.$procdff$16505 ($dff) from module user_proj_example (D = \softshell.flash.spimemio.xfer.ibuffer, Q = \softshell.flash.spimemio.buffer [23:16]).
+Adding EN signal on $flatten\softshell.\flash.\spimemio.$procdff$16505 ($dff) from module user_proj_example (D = \softshell.flash.spimemio.xfer.ibuffer, Q = \softshell.flash.spimemio.buffer [15:8]).
+Adding EN signal on $flatten\softshell.\flash.\spimemio.$procdff$16505 ($dff) from module user_proj_example (D = \softshell.flash.spimemio.xfer.ibuffer, Q = \softshell.flash.spimemio.buffer [7:0]).
+Adding SRST signal on $flatten\softshell.\flash.\spimemio.$procdff$16504 ($dff) from module user_proj_example (D = $flatten\softshell.\flash.\spimemio.$procmux$8894_Y, Q = \softshell.flash.spimemio.din_rd, rval = 1'0).
+Adding EN signal on $auto$opt_dff.cc:702:run$19643 ($sdff) from module user_proj_example (D = 1'1, Q = \softshell.flash.spimemio.din_rd).
+Adding SRST signal on $flatten\softshell.\flash.\spimemio.$procdff$16503 ($dff) from module user_proj_example (D = $flatten\softshell.\flash.\spimemio.$procmux$8915_Y, Q = \softshell.flash.spimemio.din_ddr, rval = 1'0).
+Adding SRST signal on $flatten\softshell.\flash.\spimemio.$procdff$16502 ($dff) from module user_proj_example (D = $flatten\softshell.\flash.\spimemio.$procmux$8934_Y, Q = \softshell.flash.spimemio.din_qspi, rval = 1'0).
+Adding SRST signal on $flatten\softshell.\flash.\spimemio.$procdff$16500 ($dff) from module user_proj_example (D = $flatten\softshell.\flash.\spimemio.$procmux$8944_Y, Q = \softshell.flash.spimemio.din_tag, rval = 4'0000).
+Adding EN signal on $auto$opt_dff.cc:702:run$19649 ($sdff) from module user_proj_example (D = $flatten\softshell.\flash.\spimemio.$procmux$8944_Y, Q = \softshell.flash.spimemio.din_tag).
+Adding EN signal on $flatten\softshell.\flash.\spimemio.$procdff$16499 ($dff) from module user_proj_example (D = $flatten\softshell.\flash.\spimemio.$procmux$8963_Y, Q = \softshell.flash.spimemio.din_data).
+Adding SRST signal on $flatten\softshell.\flash.\spimemio.$procdff$16498 ($dff) from module user_proj_example (D = $flatten\softshell.\flash.\spimemio.$procmux$8851_Y, Q = \softshell.flash.spimemio.din_valid, rval = 1'0).
+Adding SRST signal on $flatten\softshell.\flash.\spimemio.$procdff$16497 ($dff) from module user_proj_example (D = $flatten\softshell.\flash.\spimemio.$procmux$8749_Y, Q = \softshell.flash.spimemio.xfer_resetn, rval = 1'0).
+Adding EN signal on $flatten\softshell.\flash.\spimemio.$procdff$16496 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.xfer.ibuffer \softshell.flash.spimemio.buffer }, Q = \softshell.flash.spimemio.rdata).
+Adding EN signal on $flatten\softshell.\cpus[2].core.\soc_mem.\ram.$procdff$16840 ($dff) from module user_proj_example (D = { $flatten\softshell.\cpus[2].core.\soc_mem.\ram.$memrd$\ram3$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:119$2809_DATA $flatten\softshell.\cpus[2].core.\soc_mem.\ram.$memrd$\ram2$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:118$2808_DATA $flatten\softshell.\cpus[2].core.\soc_mem.\ram.$memrd$\ram1$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:117$2807_DATA $flatten\softshell.\cpus[2].core.\soc_mem.\ram.$memrd$\ram0$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:116$2806_DATA }, Q = \softshell.cpus[2].core.soc_mem.ram.dout).
+Adding SRST signal on $flatten\softshell.\cpus[2].core.\soc_mem.$procdff$16310 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[2].core.\soc_mem.$and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:50$2729_Y, Q = \softshell.cpus[2].core.soc_mem.wb_ack_read, rval = 1'0).
+Adding SRST signal on $flatten\softshell.\cpus[2].core.\soc_mem.$procdff$16309 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[2].core.\soc_mem.$ternary$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:49$2725_Y, Q = \softshell.cpus[2].core.soc_mem.wb_ack_o, rval = 1'0).
+Adding EN signal on $flatten\softshell.\cpus[2].core.\gpio.\gpio_ctrl.$procdff$16316 ($dff) from module user_proj_example (D = \softshell.cpus[2].core.cpu.wbm_dat_o, Q = \softshell.cpus[2].core.gpio.gpio_ctrl.gpio_pd).
+Adding EN signal on $flatten\softshell.\cpus[2].core.\gpio.\gpio_ctrl.$procdff$16315 ($dff) from module user_proj_example (D = \softshell.cpus[2].core.cpu.wbm_dat_o, Q = \softshell.cpus[2].core.gpio.gpio_ctrl.gpio_pu).
+Adding EN signal on $flatten\softshell.\cpus[2].core.\gpio.\gpio_ctrl.$procdff$16314 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[2].core.\gpio.\gpio_ctrl.$procmux$5457_Y, Q = \softshell.cpus[2].core.gpio.gpio_ctrl.iomem_ready).
+Adding EN signal on $flatten\softshell.\cpus[2].core.\gpio.\gpio_ctrl.$procdff$16313 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[2].core.\gpio.\gpio_ctrl.$procmux$5471_Y, Q = \softshell.cpus[2].core.gpio.gpio_ctrl.iomem_rdata).
+Adding SRST signal on $flatten\softshell.\cpus[2].core.\gpio.\gpio_ctrl.$procdff$16312 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[2].core.\gpio.\gpio_ctrl.$procmux$5486_Y, Q = \softshell.cpus[2].core.gpio.gpio_ctrl.gpio_oeb, rval = 32'11111111111111111111111111111111).
+Adding EN signal on $auto$opt_dff.cc:702:run$19708 ($sdff) from module user_proj_example (D = $flatten\softshell.\cpus[2].core.\gpio.\gpio_ctrl.$not$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/gpio32_wb.v:117$2715_Y, Q = \softshell.cpus[2].core.gpio.gpio_ctrl.gpio_oeb).
+Adding SRST signal on $flatten\softshell.\cpus[2].core.\gpio.\gpio_ctrl.$procdff$16311 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[2].core.\gpio.\gpio_ctrl.$procmux$5496_Y, Q = \softshell.cpus[2].core.gpio.gpio_ctrl.gpio_out, rval = 0).
+Adding EN signal on $auto$opt_dff.cc:702:run$19714 ($sdff) from module user_proj_example (D = \softshell.cpus[2].core.cpu.wbm_dat_o, Q = \softshell.cpus[2].core.gpio.gpio_ctrl.gpio_out).
+Adding EN signal on $flatten\softshell.\cpus[2].core.\flexio.\out_fifo.$procdff$16327 ($adff) from module user_proj_example (D = $flatten\softshell.\cpus[2].core.\flexio.\out_fifo.$xor$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:131$2006_Y, Q = \softshell.cpus[2].core.flexio.out_fifo.wgray).
+Adding EN signal on $flatten\softshell.\cpus[2].core.\flexio.\out_fifo.$procdff$16326 ($adff) from module user_proj_example (D = \softshell.cpus[2].core.flexio.out_fifo.next_wr_addr, Q = \softshell.cpus[2].core.flexio.out_fifo.wr_addr).
+Adding EN signal on $flatten\softshell.\cpus[2].core.\flexio.\out_fifo.$procdff$16322 ($adff) from module user_proj_example (D = $flatten\softshell.\cpus[2].core.\flexio.\out_fifo.$xor$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:153$2019_Y, Q = \softshell.cpus[2].core.flexio.out_fifo.rgray).
+Adding EN signal on $flatten\softshell.\cpus[2].core.\flexio.\out_fifo.$procdff$16321 ($adff) from module user_proj_example (D = \softshell.cpus[2].core.flexio.out_fifo.next_rd_addr, Q = \softshell.cpus[2].core.flexio.out_fifo.rd_addr).
+Adding EN signal on $flatten\softshell.\cpus[2].core.\flexio.$procdff$16923 ($adff) from module user_proj_example (D = \softshell.cpus[2].core.cpu.picorv32_core.reg_op1, Q = \softshell.cpus[2].core.flexio.out_wr_data).
+Adding EN signal on $flatten\softshell.\cpus[2].core.\flexio.$procdff$16921 ($adff) from module user_proj_example (D = \softshell.cpus[2].core.cpu.picorv32_core.reg_op2 [23:0], Q = \softshell.cpus[2].core.flexio.cfg_clk_div).
+Adding EN signal on $flatten\softshell.\cpus[2].core.\flexio.$procdff$16920 ($adff) from module user_proj_example (D = \softshell.cpus[2].core.cpu.picorv32_core.reg_op1 [19:16], Q = \softshell.cpus[2].core.flexio.cfg_bits_per_clock).
+Adding EN signal on $flatten\softshell.\cpus[2].core.\flexio.$procdff$16919 ($adff) from module user_proj_example (D = \softshell.cpus[2].core.cpu.picorv32_core.reg_op1 [31:24], Q = \softshell.cpus[2].core.flexio.cfg_out_bit_mask).
+Adding EN signal on $flatten\softshell.\cpus[2].core.\flexio.$procdff$16914 ($adff) from module user_proj_example (D = $flatten\softshell.\cpus[2].core.\flexio.$0\out_shift_cnt[4:0], Q = \softshell.cpus[2].core.flexio.out_shift_cnt).
+Adding EN signal on $flatten\softshell.\cpus[2].core.\flexio.$procdff$16913 ($adff) from module user_proj_example (D = $flatten\softshell.\cpus[2].core.\flexio.$0\out_shift_reg[31:0], Q = \softshell.cpus[2].core.flexio.out_shift_reg).
+Adding SRST signal on $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procdff$16839 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:397$2905_Y, Q = \softshell.cpus[2].core.cpu.picorv32_core.last_mem_valid, rval = 1'0).
+Adding SRST signal on $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procdff$16838 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$14876_Y, Q = \softshell.cpus[2].core.cpu.picorv32_core.mem_la_firstword_reg, rval = 1'0).
+Adding EN signal on $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procdff$16837 ($dff) from module user_proj_example (D = \softshell.cpus[2].core.cpu.picorv32_core.mem_rdata_latched [6:0], Q = \softshell.cpus[2].core.cpu.picorv32_core.mem_rdata_q [6:0]).
+Adding EN signal on $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procdff$16835 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$14508_Y, Q = \softshell.cpus[2].core.cpu.picorv32_core.mem_16bit_buffer).
+Adding SRST signal on $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procdff$16834 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$14529_Y, Q = \softshell.cpus[2].core.cpu.picorv32_core.prefetched_high_word, rval = 1'0).
+Adding EN signal on $auto$opt_dff.cc:702:run$19760 ($sdff) from module user_proj_example (D = $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$14520_Y, Q = \softshell.cpus[2].core.cpu.picorv32_core.prefetched_high_word).
+Adding SRST signal on $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procdff$16833 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$14543_Y, Q = \softshell.cpus[2].core.cpu.picorv32_core.mem_la_secondword, rval = 1'0).
+Adding EN signal on $auto$opt_dff.cc:702:run$19768 ($sdff) from module user_proj_example (D = $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$14539_Y, Q = \softshell.cpus[2].core.cpu.picorv32_core.mem_la_secondword).
+Adding EN signal on $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procdff$16832 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$0\mem_state[1:0], Q = \softshell.cpus[2].core.cpu.picorv32_core.mem_state).
+Adding EN signal on $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procdff$16831 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$14578_Y, Q = \softshell.cpus[2].core.cpu.picorv32_core.mem_wstrb).
+Adding EN signal on $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procdff$16830 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$0\mem_valid[0:0], Q = \softshell.cpus[2].core.cpu.picorv32_core.mem_valid).
+Adding EN signal on $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procdff$16829 ($dff) from module user_proj_example (D = \softshell.cpus[2].core.cpu.picorv32_core.mem_la_addr, Q = \softshell.cpus[2].core.cpu.picorv32_core.mem_addr).
+Adding EN signal on $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procdff$16828 ($dff) from module user_proj_example (D = \softshell.cpus[2].core.cpu.picorv32_core.mem_la_wdata, Q = \softshell.cpus[2].core.cpu.picorv32_core.mem_wdata).
+Adding SRST signal on $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procdff$16811 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$reduce_or$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:862$2984_Y, Q = \softshell.cpus[2].core.cpu.picorv32_core.is_compare, rval = 1'0).
+Adding EN signal on $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procdff$16810 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$13911_Y, Q = \softshell.cpus[2].core.cpu.picorv32_core.is_alu_reg_reg).
+Adding EN signal on $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procdff$16809 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$13947_Y, Q = \softshell.cpus[2].core.cpu.picorv32_core.is_alu_reg_imm).
+Adding SRST signal on $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procdff$16807 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$13959_Y, Q = \softshell.cpus[2].core.cpu.picorv32_core.is_beq_bne_blt_bge_bltu_bgeu, rval = 1'0).
+Adding EN signal on $auto$opt_dff.cc:702:run$19818 ($sdff) from module user_proj_example (D = $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$13957_Y, Q = \softshell.cpus[2].core.cpu.picorv32_core.is_beq_bne_blt_bge_bltu_bgeu).
+Adding SRST signal on $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procdff$16804 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$reduce_or$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:858$2980_Y, Q = \softshell.cpus[2].core.cpu.picorv32_core.is_lui_auipc_jal_jalr_addi_add_sub, rval = 1'0).
+Adding EN signal on $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procdff$16802 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$13972_Y, Q = \softshell.cpus[2].core.cpu.picorv32_core.is_sb_sh_sw).
+Adding EN signal on $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procdff$16801 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$logic_or$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1098$3222_Y, Q = \softshell.cpus[2].core.cpu.picorv32_core.is_jalr_addi_slti_sltiu_xori_ori_andi).
+Adding EN signal on $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procdff$16800 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1092$3213_Y, Q = \softshell.cpus[2].core.cpu.picorv32_core.is_slli_srli_srai).
+Adding EN signal on $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procdff$16799 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$13992_Y, Q = \softshell.cpus[2].core.cpu.picorv32_core.is_lb_lh_lw_lbu_lhu).
+Adding EN signal on $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procdff$16797 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$13996_Y, Q = \softshell.cpus[2].core.cpu.picorv32_core.compressed_instr).
+Adding EN signal on $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procdff$16796 ($dff) from module user_proj_example (D = { $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$13829_Y $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$14042_Y $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$13837_Y $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$13805_Y $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$13825_Y $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$13809_Y $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$13813_Y $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$13821_Y $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$13833_Y $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$13817_Y 1'0 }, Q = \softshell.cpus[2].core.cpu.picorv32_core.decoded_imm_j).
+Setting constant 0-bit at position 0 on $auto$opt_dff.cc:764:run$19826 ($dffe) from module user_proj_example.
+Adding EN signal on $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procdff$16795 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$14005_Y, Q = \softshell.cpus[2].core.cpu.picorv32_core.decoded_imm).
+Adding EN signal on $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procdff$16794 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$14038_Y, Q = \softshell.cpus[2].core.cpu.picorv32_core.decoded_rs2).
+Adding EN signal on $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procdff$16793 ($dff) from module user_proj_example (D = { $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$13801_Y $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$13888_Y }, Q = \softshell.cpus[2].core.cpu.picorv32_core.decoded_rs1).
+Adding EN signal on $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procdff$16792 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$14089_Y, Q = \softshell.cpus[2].core.cpu.picorv32_core.decoded_rd).
+Adding EN signal on $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procdff$16791 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1090$3200_Y, Q = \softshell.cpus[2].core.cpu.picorv32_core.instr_timer).
+Adding EN signal on $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procdff$16790 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:870$2998_Y, Q = \softshell.cpus[2].core.cpu.picorv32_core.instr_waitirq).
+Adding EN signal on $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procdff$16789 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1089$3196_Y, Q = \softshell.cpus[2].core.cpu.picorv32_core.instr_maskirq).
+Adding EN signal on $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procdff$16788 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:869$2994_Y, Q = \softshell.cpus[2].core.cpu.picorv32_core.instr_retirq).
+Adding EN signal on $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procdff$16787 ($dff) from module user_proj_example (D = 1'0, Q = \softshell.cpus[2].core.cpu.picorv32_core.instr_setq).
+Setting constant 0-bit at position 0 on $auto$opt_dff.cc:764:run$19835 ($dffe) from module user_proj_example.
+Adding EN signal on $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procdff$16786 ($dff) from module user_proj_example (D = 1'0, Q = \softshell.cpus[2].core.cpu.picorv32_core.instr_getq).
+Setting constant 0-bit at position 0 on $auto$opt_dff.cc:764:run$19836 ($dffe) from module user_proj_example.
+Adding EN signal on $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procdff$16785 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$logic_or$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1084$3183_Y, Q = \softshell.cpus[2].core.cpu.picorv32_core.instr_ecall_ebreak).
+Adding EN signal on $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procdff$16784 ($dff) from module user_proj_example (D = 1'0, Q = \softshell.cpus[2].core.cpu.picorv32_core.instr_rdinstrh).
+Setting constant 0-bit at position 0 on $auto$opt_dff.cc:764:run$19838 ($dffe) from module user_proj_example.
+Adding EN signal on $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procdff$16783 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1081$3169_Y, Q = \softshell.cpus[2].core.cpu.picorv32_core.instr_rdinstr).
+Adding EN signal on $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procdff$16782 ($dff) from module user_proj_example (D = 1'0, Q = \softshell.cpus[2].core.cpu.picorv32_core.instr_rdcycleh).
+Setting constant 0-bit at position 0 on $auto$opt_dff.cc:764:run$19840 ($dffe) from module user_proj_example.
+Adding EN signal on $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procdff$16781 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1077$3157_Y, Q = \softshell.cpus[2].core.cpu.picorv32_core.instr_rdcycle).
+Adding SRST signal on $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procdff$16780 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$14115_Y, Q = \softshell.cpus[2].core.cpu.picorv32_core.instr_and, rval = 1'0).
+Adding EN signal on $auto$opt_dff.cc:702:run$19842 ($sdff) from module user_proj_example (D = $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1075$3149_Y, Q = \softshell.cpus[2].core.cpu.picorv32_core.instr_and).
+Adding SRST signal on $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procdff$16779 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$14119_Y, Q = \softshell.cpus[2].core.cpu.picorv32_core.instr_or, rval = 1'0).
+Adding EN signal on $auto$opt_dff.cc:702:run$19844 ($sdff) from module user_proj_example (D = $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1074$3145_Y, Q = \softshell.cpus[2].core.cpu.picorv32_core.instr_or).
+Adding SRST signal on $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procdff$16778 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$14123_Y, Q = \softshell.cpus[2].core.cpu.picorv32_core.instr_sra, rval = 1'0).
+Adding EN signal on $auto$opt_dff.cc:702:run$19846 ($sdff) from module user_proj_example (D = $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1073$3141_Y, Q = \softshell.cpus[2].core.cpu.picorv32_core.instr_sra).
+Adding SRST signal on $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procdff$16777 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$14127_Y, Q = \softshell.cpus[2].core.cpu.picorv32_core.instr_srl, rval = 1'0).
+Adding EN signal on $auto$opt_dff.cc:702:run$19848 ($sdff) from module user_proj_example (D = $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1072$3137_Y, Q = \softshell.cpus[2].core.cpu.picorv32_core.instr_srl).
+Adding SRST signal on $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procdff$16776 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$14131_Y, Q = \softshell.cpus[2].core.cpu.picorv32_core.instr_xor, rval = 1'0).
+Adding EN signal on $auto$opt_dff.cc:702:run$19850 ($sdff) from module user_proj_example (D = $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1071$3133_Y, Q = \softshell.cpus[2].core.cpu.picorv32_core.instr_xor).
+Adding SRST signal on $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procdff$16775 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$14135_Y, Q = \softshell.cpus[2].core.cpu.picorv32_core.instr_sltu, rval = 1'0).
+Adding EN signal on $auto$opt_dff.cc:702:run$19852 ($sdff) from module user_proj_example (D = $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1070$3129_Y, Q = \softshell.cpus[2].core.cpu.picorv32_core.instr_sltu).
+Adding SRST signal on $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procdff$16774 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$14139_Y, Q = \softshell.cpus[2].core.cpu.picorv32_core.instr_slt, rval = 1'0).
+Adding EN signal on $auto$opt_dff.cc:702:run$19854 ($sdff) from module user_proj_example (D = $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1069$3125_Y, Q = \softshell.cpus[2].core.cpu.picorv32_core.instr_slt).
+Adding SRST signal on $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procdff$16773 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$14143_Y, Q = \softshell.cpus[2].core.cpu.picorv32_core.instr_sll, rval = 1'0).
+Adding EN signal on $auto$opt_dff.cc:702:run$19856 ($sdff) from module user_proj_example (D = $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1068$3121_Y, Q = \softshell.cpus[2].core.cpu.picorv32_core.instr_sll).
+Adding SRST signal on $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procdff$16772 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$14147_Y, Q = \softshell.cpus[2].core.cpu.picorv32_core.instr_sub, rval = 1'0).
+Adding EN signal on $auto$opt_dff.cc:702:run$19858 ($sdff) from module user_proj_example (D = $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1067$3117_Y, Q = \softshell.cpus[2].core.cpu.picorv32_core.instr_sub).
+Adding SRST signal on $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procdff$16771 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$14151_Y, Q = \softshell.cpus[2].core.cpu.picorv32_core.instr_add, rval = 1'0).
+Adding EN signal on $auto$opt_dff.cc:702:run$19860 ($sdff) from module user_proj_example (D = $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1066$3113_Y, Q = \softshell.cpus[2].core.cpu.picorv32_core.instr_add).
+Adding EN signal on $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procdff$16770 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1064$3109_Y, Q = \softshell.cpus[2].core.cpu.picorv32_core.instr_srai).
+Adding EN signal on $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procdff$16769 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1063$3105_Y, Q = \softshell.cpus[2].core.cpu.picorv32_core.instr_srli).
+Adding EN signal on $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procdff$16768 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1062$3101_Y, Q = \softshell.cpus[2].core.cpu.picorv32_core.instr_slli).
+Adding SRST signal on $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procdff$16767 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$14161_Y, Q = \softshell.cpus[2].core.cpu.picorv32_core.instr_andi, rval = 1'0).
+Adding EN signal on $auto$opt_dff.cc:702:run$19865 ($sdff) from module user_proj_example (D = $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1060$3097_Y, Q = \softshell.cpus[2].core.cpu.picorv32_core.instr_andi).
+Adding SRST signal on $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procdff$16766 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$14165_Y, Q = \softshell.cpus[2].core.cpu.picorv32_core.instr_ori, rval = 1'0).
+Adding EN signal on $auto$opt_dff.cc:702:run$19867 ($sdff) from module user_proj_example (D = $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1059$3095_Y, Q = \softshell.cpus[2].core.cpu.picorv32_core.instr_ori).
+Adding SRST signal on $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procdff$16765 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$14169_Y, Q = \softshell.cpus[2].core.cpu.picorv32_core.instr_xori, rval = 1'0).
+Adding EN signal on $auto$opt_dff.cc:702:run$19869 ($sdff) from module user_proj_example (D = $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1058$3093_Y, Q = \softshell.cpus[2].core.cpu.picorv32_core.instr_xori).
+Adding SRST signal on $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procdff$16764 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$14173_Y, Q = \softshell.cpus[2].core.cpu.picorv32_core.instr_sltiu, rval = 1'0).
+Adding EN signal on $auto$opt_dff.cc:702:run$19871 ($sdff) from module user_proj_example (D = $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1057$3091_Y, Q = \softshell.cpus[2].core.cpu.picorv32_core.instr_sltiu).
+Adding SRST signal on $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procdff$16763 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$14177_Y, Q = \softshell.cpus[2].core.cpu.picorv32_core.instr_slti, rval = 1'0).
+Adding EN signal on $auto$opt_dff.cc:702:run$19873 ($sdff) from module user_proj_example (D = $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1056$3089_Y, Q = \softshell.cpus[2].core.cpu.picorv32_core.instr_slti).
+Adding SRST signal on $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procdff$16762 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$14181_Y, Q = \softshell.cpus[2].core.cpu.picorv32_core.instr_addi, rval = 1'0).
+Adding EN signal on $auto$opt_dff.cc:702:run$19875 ($sdff) from module user_proj_example (D = $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1055$3087_Y, Q = \softshell.cpus[2].core.cpu.picorv32_core.instr_addi).
+Adding EN signal on $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procdff$16761 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1053$3085_Y, Q = \softshell.cpus[2].core.cpu.picorv32_core.instr_sw).
+Adding EN signal on $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procdff$16760 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1052$3083_Y, Q = \softshell.cpus[2].core.cpu.picorv32_core.instr_sh).
+Adding EN signal on $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procdff$16759 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1051$3081_Y, Q = \softshell.cpus[2].core.cpu.picorv32_core.instr_sb).
+Adding EN signal on $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procdff$16758 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1049$3079_Y, Q = \softshell.cpus[2].core.cpu.picorv32_core.instr_lhu).
+Adding EN signal on $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procdff$16757 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1048$3077_Y, Q = \softshell.cpus[2].core.cpu.picorv32_core.instr_lbu).
+Adding EN signal on $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procdff$16756 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1047$3075_Y, Q = \softshell.cpus[2].core.cpu.picorv32_core.instr_lw).
+Adding EN signal on $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procdff$16755 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1046$3073_Y, Q = \softshell.cpus[2].core.cpu.picorv32_core.instr_lh).
+Adding EN signal on $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procdff$16754 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1045$3071_Y, Q = \softshell.cpus[2].core.cpu.picorv32_core.instr_lb).
+Adding SRST signal on $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procdff$16753 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$14201_Y, Q = \softshell.cpus[2].core.cpu.picorv32_core.instr_bgeu, rval = 1'0).
+Adding EN signal on $auto$opt_dff.cc:702:run$19885 ($sdff) from module user_proj_example (D = $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1043$3069_Y, Q = \softshell.cpus[2].core.cpu.picorv32_core.instr_bgeu).
+Adding SRST signal on $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procdff$16752 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$14205_Y, Q = \softshell.cpus[2].core.cpu.picorv32_core.instr_bltu, rval = 1'0).
+Adding EN signal on $auto$opt_dff.cc:702:run$19887 ($sdff) from module user_proj_example (D = $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1042$3067_Y, Q = \softshell.cpus[2].core.cpu.picorv32_core.instr_bltu).
+Adding SRST signal on $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procdff$16751 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$14209_Y, Q = \softshell.cpus[2].core.cpu.picorv32_core.instr_bge, rval = 1'0).
+Adding EN signal on $auto$opt_dff.cc:702:run$19889 ($sdff) from module user_proj_example (D = $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1041$3065_Y, Q = \softshell.cpus[2].core.cpu.picorv32_core.instr_bge).
+Adding SRST signal on $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procdff$16750 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$14213_Y, Q = \softshell.cpus[2].core.cpu.picorv32_core.instr_blt, rval = 1'0).
+Adding EN signal on $auto$opt_dff.cc:702:run$19891 ($sdff) from module user_proj_example (D = $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1040$3063_Y, Q = \softshell.cpus[2].core.cpu.picorv32_core.instr_blt).
+Adding SRST signal on $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procdff$16749 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$14217_Y, Q = \softshell.cpus[2].core.cpu.picorv32_core.instr_bne, rval = 1'0).
+Adding EN signal on $auto$opt_dff.cc:702:run$19893 ($sdff) from module user_proj_example (D = $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1039$3061_Y, Q = \softshell.cpus[2].core.cpu.picorv32_core.instr_bne).
+Adding SRST signal on $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procdff$16748 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$14221_Y, Q = \softshell.cpus[2].core.cpu.picorv32_core.instr_beq, rval = 1'0).
+Adding EN signal on $auto$opt_dff.cc:702:run$19895 ($sdff) from module user_proj_example (D = $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1038$3059_Y, Q = \softshell.cpus[2].core.cpu.picorv32_core.instr_beq).
+Adding EN signal on $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procdff$16747 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$14234_Y, Q = \softshell.cpus[2].core.cpu.picorv32_core.instr_jalr).
+Adding EN signal on $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procdff$16746 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$14246_Y, Q = \softshell.cpus[2].core.cpu.picorv32_core.instr_jal).
+Adding EN signal on $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procdff$16745 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$eq$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:866$2987_Y, Q = \softshell.cpus[2].core.cpu.picorv32_core.instr_auipc).
+Adding EN signal on $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procdff$16744 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$14266_Y, Q = \softshell.cpus[2].core.cpu.picorv32_core.instr_lui).
+Adding EN signal on $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procdff$16743 ($dff) from module user_proj_example (D = \softshell.cpus[2].core.cpu.picorv32_core.mem_rdata_q, Q = \softshell.cpus[2].core.cpu.picorv32_core.pcpi_insn).
+Adding SRST signal on $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procdff$16737 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$12618_Y, Q = \softshell.cpus[2].core.cpu.picorv32_core.do_waitirq, rval = 1'0).
+Adding SRST signal on $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procdff$16735 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$logic_not$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1424$3312_Y, Q = \softshell.cpus[2].core.cpu.picorv32_core.pcpi_timeout, rval = 1'0).
+Adding SRST signal on $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procdff$16734 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$12857_Y, Q = \softshell.cpus[2].core.cpu.picorv32_core.pcpi_timeout_counter, rval = 4'1111).
+Adding EN signal on $auto$opt_dff.cc:702:run$19910 ($sdff) from module user_proj_example (D = $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$sub$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1421$3311_Y [3:0], Q = \softshell.cpus[2].core.cpu.picorv32_core.pcpi_timeout_counter).
+Adding SRST signal on $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procdff$16732 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$12872_Y, Q = \softshell.cpus[2].core.cpu.picorv32_core.latched_rd, rval = 5'00010).
+Adding EN signal on $auto$opt_dff.cc:702:run$19912 ($sdff) from module user_proj_example (D = $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$12872_Y, Q = \softshell.cpus[2].core.cpu.picorv32_core.latched_rd).
+Adding SRST signal on $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procdff$16731 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$12898_Y, Q = \softshell.cpus[2].core.cpu.picorv32_core.latched_is_lb, rval = 1'0).
+Adding EN signal on $auto$opt_dff.cc:702:run$19920 ($sdff) from module user_proj_example (D = $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$12898_Y, Q = \softshell.cpus[2].core.cpu.picorv32_core.latched_is_lb).
+Adding SRST signal on $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procdff$16730 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$12911_Y, Q = \softshell.cpus[2].core.cpu.picorv32_core.latched_is_lh, rval = 1'0).
+Adding EN signal on $auto$opt_dff.cc:702:run$19930 ($sdff) from module user_proj_example (D = $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$12911_Y, Q = \softshell.cpus[2].core.cpu.picorv32_core.latched_is_lh).
+Adding SRST signal on $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procdff$16729 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$12924_Y, Q = \softshell.cpus[2].core.cpu.picorv32_core.latched_is_lu, rval = 1'0).
+Adding EN signal on $auto$opt_dff.cc:702:run$19940 ($sdff) from module user_proj_example (D = $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$12924_Y, Q = \softshell.cpus[2].core.cpu.picorv32_core.latched_is_lu).
+Adding EN signal on $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procdff$16727 ($dff) from module user_proj_example (D = \softshell.cpus[2].core.cpu.picorv32_core.compressed_instr, Q = \softshell.cpus[2].core.cpu.picorv32_core.latched_compr).
+Adding SRST signal on $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procdff$16726 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$12969_Y, Q = \softshell.cpus[2].core.cpu.picorv32_core.latched_branch, rval = 1'0).
+Adding EN signal on $auto$opt_dff.cc:702:run$19957 ($sdff) from module user_proj_example (D = $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$12969_Y, Q = \softshell.cpus[2].core.cpu.picorv32_core.latched_branch).
+Adding SRST signal on $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procdff$16725 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$13005_Y, Q = \softshell.cpus[2].core.cpu.picorv32_core.latched_stalu, rval = 1'0).
+Adding EN signal on $auto$opt_dff.cc:702:run$19965 ($sdff) from module user_proj_example (D = $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$13005_Y, Q = \softshell.cpus[2].core.cpu.picorv32_core.latched_stalu).
+Adding SRST signal on $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procdff$16724 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$13012_Y, Q = \softshell.cpus[2].core.cpu.picorv32_core.latched_store, rval = 1'1).
+Adding EN signal on $auto$opt_dff.cc:702:run$19973 ($sdff) from module user_proj_example (D = $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$13012_Y, Q = \softshell.cpus[2].core.cpu.picorv32_core.latched_store).
+Adding SRST signal on $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procdff$16720 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$13070_Y, Q = \softshell.cpus[2].core.cpu.picorv32_core.irq_state, rval = 2'00).
+Adding EN signal on $auto$opt_dff.cc:702:run$19983 ($sdff) from module user_proj_example (D = $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$ternary$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1535$3357_Y, Q = \softshell.cpus[2].core.cpu.picorv32_core.irq_state).
+Adding SRST signal on $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procdff$16713 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$12632_Y, Q = \softshell.cpus[2].core.cpu.picorv32_core.decoder_pseudo_trigger, rval = 1'0).
+Adding SRST signal on $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procdff$16710 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$13282_Y, Q = \softshell.cpus[2].core.cpu.picorv32_core.mem_do_wdata, rval = 1'1).
+Adding EN signal on $auto$opt_dff.cc:702:run$19994 ($sdff) from module user_proj_example (D = 1'0, Q = \softshell.cpus[2].core.cpu.picorv32_core.mem_do_wdata).
+Adding SRST signal on $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procdff$16709 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$13286_Y, Q = \softshell.cpus[2].core.cpu.picorv32_core.mem_do_rdata, rval = 1'1).
+Adding EN signal on $auto$opt_dff.cc:702:run$19996 ($sdff) from module user_proj_example (D = 1'0, Q = \softshell.cpus[2].core.cpu.picorv32_core.mem_do_rdata).
+Adding SRST signal on $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procdff$16708 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$13360_Y, Q = \softshell.cpus[2].core.cpu.picorv32_core.mem_do_rinst, rval = 1'1).
+Adding EN signal on $auto$opt_dff.cc:702:run$19998 ($sdff) from module user_proj_example (D = $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$13360_Y, Q = \softshell.cpus[2].core.cpu.picorv32_core.mem_do_rinst).
+Adding SRST signal on $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procdff$16707 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$13385_Y, Q = \softshell.cpus[2].core.cpu.picorv32_core.mem_do_prefetch, rval = 1'0).
+Adding EN signal on $auto$opt_dff.cc:702:run$20010 ($sdff) from module user_proj_example (D = $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1568$3371_Y, Q = \softshell.cpus[2].core.cpu.picorv32_core.mem_do_prefetch).
+Adding SRST signal on $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procdff$16705 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$13431_Y, Q = \softshell.cpus[2].core.cpu.picorv32_core.timer, rval = 0).
+Adding SRST signal on $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procdff$16703 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$13449_Y, Q = \softshell.cpus[2].core.cpu.picorv32_core.irq_mask, rval = 32'11111111111111111111111111111111).
+Adding EN signal on $auto$opt_dff.cc:702:run$20023 ($sdff) from module user_proj_example (D = \softshell.cpus[2].core.cpu.picorv32_core.cpuregs_rs1, Q = \softshell.cpus[2].core.cpu.picorv32_core.irq_mask).
+Adding SRST signal on $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procdff$16702 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$13468_Y, Q = \softshell.cpus[2].core.cpu.picorv32_core.irq_active, rval = 1'0).
+Adding EN signal on $auto$opt_dff.cc:702:run$20027 ($sdff) from module user_proj_example (D = $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$13468_Y, Q = \softshell.cpus[2].core.cpu.picorv32_core.irq_active).
+Adding SRST signal on $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procdff$16701 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$13493_Y, Q = \softshell.cpus[2].core.cpu.picorv32_core.irq_delay, rval = 1'0).
+Adding EN signal on $auto$opt_dff.cc:702:run$20037 ($sdff) from module user_proj_example (D = \softshell.cpus[2].core.cpu.picorv32_core.irq_active, Q = \softshell.cpus[2].core.cpu.picorv32_core.irq_delay).
+Adding SRST signal on $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procdff$16699 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$12765_Y, Q = \softshell.cpus[2].core.cpu.picorv32_core.reg_out, rval = 128).
+Adding EN signal on $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procdff$16698 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$13506_Y, Q = \softshell.cpus[2].core.cpu.picorv32_core.reg_op2).
+Adding EN signal on $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procdff$16697 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$13528_Y, Q = \softshell.cpus[2].core.cpu.picorv32_core.reg_op1).
+Adding SRST signal on $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procdff$16696 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$13589_Y, Q = \softshell.cpus[2].core.cpu.picorv32_core.reg_next_pc, rval = 809697280).
+Adding EN signal on $auto$opt_dff.cc:702:run$20066 ($sdff) from module user_proj_example (D = $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$13587_Y, Q = \softshell.cpus[2].core.cpu.picorv32_core.reg_next_pc).
+Adding SRST signal on $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procdff$16695 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$13601_Y, Q = \softshell.cpus[2].core.cpu.picorv32_core.reg_pc, rval = 809697280).
+Adding EN signal on $auto$opt_dff.cc:702:run$20068 ($sdff) from module user_proj_example (D = $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$3\current_pc[31:0], Q = \softshell.cpus[2].core.cpu.picorv32_core.reg_pc).
+Adding SRST signal on $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procdff$16694 ($dff) from module user_proj_example (D = { $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$12499_Y $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$12464_Y }, Q = \softshell.cpus[2].core.cpu.picorv32_core.count_instr, rval = 64'0000000000000000000000000000000000000000000000000000000000000000).
+Adding EN signal on $auto$opt_dff.cc:702:run$20070 ($sdff) from module user_proj_example (D = { 32'00000000000000000000000000000000 $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1559$3367_Y [31:0] }, Q = \softshell.cpus[2].core.cpu.picorv32_core.count_instr).
+Setting constant 0-bit at position 32 on $auto$opt_dff.cc:764:run$20077 ($sdffe) from module user_proj_example.
+Setting constant 0-bit at position 33 on $auto$opt_dff.cc:764:run$20077 ($sdffe) from module user_proj_example.
+Setting constant 0-bit at position 34 on $auto$opt_dff.cc:764:run$20077 ($sdffe) from module user_proj_example.
+Setting constant 0-bit at position 35 on $auto$opt_dff.cc:764:run$20077 ($sdffe) from module user_proj_example.
+Setting constant 0-bit at position 36 on $auto$opt_dff.cc:764:run$20077 ($sdffe) from module user_proj_example.
+Setting constant 0-bit at position 37 on $auto$opt_dff.cc:764:run$20077 ($sdffe) from module user_proj_example.
+Setting constant 0-bit at position 38 on $auto$opt_dff.cc:764:run$20077 ($sdffe) from module user_proj_example.
+Setting constant 0-bit at position 39 on $auto$opt_dff.cc:764:run$20077 ($sdffe) from module user_proj_example.
+Setting constant 0-bit at position 40 on $auto$opt_dff.cc:764:run$20077 ($sdffe) from module user_proj_example.
+Setting constant 0-bit at position 41 on $auto$opt_dff.cc:764:run$20077 ($sdffe) from module user_proj_example.
+Setting constant 0-bit at position 42 on $auto$opt_dff.cc:764:run$20077 ($sdffe) from module user_proj_example.
+Setting constant 0-bit at position 43 on $auto$opt_dff.cc:764:run$20077 ($sdffe) from module user_proj_example.
+Setting constant 0-bit at position 44 on $auto$opt_dff.cc:764:run$20077 ($sdffe) from module user_proj_example.
+Setting constant 0-bit at position 45 on $auto$opt_dff.cc:764:run$20077 ($sdffe) from module user_proj_example.
+Setting constant 0-bit at position 46 on $auto$opt_dff.cc:764:run$20077 ($sdffe) from module user_proj_example.
+Setting constant 0-bit at position 47 on $auto$opt_dff.cc:764:run$20077 ($sdffe) from module user_proj_example.
+Setting constant 0-bit at position 48 on $auto$opt_dff.cc:764:run$20077 ($sdffe) from module user_proj_example.
+Setting constant 0-bit at position 49 on $auto$opt_dff.cc:764:run$20077 ($sdffe) from module user_proj_example.
+Setting constant 0-bit at position 50 on $auto$opt_dff.cc:764:run$20077 ($sdffe) from module user_proj_example.
+Setting constant 0-bit at position 51 on $auto$opt_dff.cc:764:run$20077 ($sdffe) from module user_proj_example.
+Setting constant 0-bit at position 52 on $auto$opt_dff.cc:764:run$20077 ($sdffe) from module user_proj_example.
+Setting constant 0-bit at position 53 on $auto$opt_dff.cc:764:run$20077 ($sdffe) from module user_proj_example.
+Setting constant 0-bit at position 54 on $auto$opt_dff.cc:764:run$20077 ($sdffe) from module user_proj_example.
+Setting constant 0-bit at position 55 on $auto$opt_dff.cc:764:run$20077 ($sdffe) from module user_proj_example.
+Setting constant 0-bit at position 56 on $auto$opt_dff.cc:764:run$20077 ($sdffe) from module user_proj_example.
+Setting constant 0-bit at position 57 on $auto$opt_dff.cc:764:run$20077 ($sdffe) from module user_proj_example.
+Setting constant 0-bit at position 58 on $auto$opt_dff.cc:764:run$20077 ($sdffe) from module user_proj_example.
+Setting constant 0-bit at position 59 on $auto$opt_dff.cc:764:run$20077 ($sdffe) from module user_proj_example.
+Setting constant 0-bit at position 60 on $auto$opt_dff.cc:764:run$20077 ($sdffe) from module user_proj_example.
+Setting constant 0-bit at position 61 on $auto$opt_dff.cc:764:run$20077 ($sdffe) from module user_proj_example.
+Setting constant 0-bit at position 62 on $auto$opt_dff.cc:764:run$20077 ($sdffe) from module user_proj_example.
+Setting constant 0-bit at position 63 on $auto$opt_dff.cc:764:run$20077 ($sdffe) from module user_proj_example.
+Adding SRST signal on $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procdff$16693 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1428$3313_Y [31:0], Q = \softshell.cpus[2].core.cpu.picorv32_core.count_cycle [31:0], rval = 0).
+Adding SRST signal on $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procdff$16689 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$12851_Y, Q = \softshell.cpus[2].core.cpu.picorv32_core.trap, rval = 1'0).
+Adding SRST signal on $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procdff$16688 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$13662_Y, Q = \softshell.cpus[2].core.cpu.picorv32_core.pcpi_valid, rval = 1'0).
+Adding EN signal on $auto$opt_dff.cc:702:run$20080 ($sdff) from module user_proj_example (D = $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$13658_Y, Q = \softshell.cpus[2].core.cpu.picorv32_core.pcpi_valid).
+Adding EN signal on $flatten\softshell.\cpus[2].core.\cpu.$procdff$16308 ($dff) from module user_proj_example (D = \softshell.cpus[2].core.cpu.wbm_dat_i, Q = \softshell.cpus[2].core.cpu.mem_rdata).
+Adding EN signal on $flatten\softshell.\cpus[2].core.\cpu.$procdff$16307 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[2].core.\cpu.$procmux$5320_Y, Q = \softshell.cpus[2].core.cpu.mem_ready).
+Adding SRST signal on $flatten\softshell.\cpus[2].core.\cpu.$procdff$16305 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[2].core.\cpu.$procmux$5351_Y, Q = \softshell.cpus[2].core.cpu.wbm_sel_o, rval = 4'0000).
+Adding EN signal on $auto$opt_dff.cc:702:run$20100 ($sdff) from module user_proj_example (D = \softshell.cpus[2].core.cpu.picorv32_core.mem_wstrb, Q = \softshell.cpus[2].core.cpu.wbm_sel_o).
+Adding SRST signal on $flatten\softshell.\cpus[2].core.\cpu.$procdff$16304 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[2].core.\cpu.$procmux$5360_Y, Q = \softshell.cpus[2].core.cpu.wbm_we_o, rval = 1'0).
+Adding EN signal on $auto$opt_dff.cc:702:run$20104 ($sdff) from module user_proj_example (D = $flatten\softshell.\cpus[2].core.\cpu.$procmux$5360_Y, Q = \softshell.cpus[2].core.cpu.wbm_we_o).
+Adding SRST signal on $flatten\softshell.\cpus[2].core.\cpu.$procdff$16303 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[2].core.\cpu.$procmux$5373_Y, Q = \softshell.cpus[2].core.cpu.wbm_cyc_o, rval = 1'0).
+Adding EN signal on $auto$opt_dff.cc:702:run$20112 ($sdff) from module user_proj_example (D = $flatten\softshell.\cpus[2].core.\cpu.$procmux$5373_Y, Q = \softshell.cpus[2].core.cpu.wbm_cyc_o).
+Adding SRST signal on $flatten\softshell.\cpus[2].core.\cpu.$procdff$16302 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[2].core.\cpu.$procmux$5386_Y, Q = \softshell.cpus[2].core.cpu.wbm_stb_o, rval = 1'0).
+Adding EN signal on $auto$opt_dff.cc:702:run$20120 ($sdff) from module user_proj_example (D = $flatten\softshell.\cpus[2].core.\cpu.$procmux$5386_Y, Q = \softshell.cpus[2].core.cpu.wbm_stb_o).
+Adding SRST signal on $flatten\softshell.\cpus[2].core.\cpu.$procdff$16301 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[2].core.\cpu.$procmux$5401_Y, Q = \softshell.cpus[2].core.cpu.wbm_adr_o, rval = 0).
+Adding EN signal on $auto$opt_dff.cc:702:run$20128 ($sdff) from module user_proj_example (D = \softshell.cpus[2].core.cpu.picorv32_core.mem_addr, Q = \softshell.cpus[2].core.cpu.wbm_adr_o).
+Adding SRST signal on $flatten\softshell.\cpus[2].core.\cpu.$procdff$16300 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[2].core.\cpu.$procmux$5412_Y, Q = \softshell.cpus[2].core.cpu.wbm_dat_o, rval = 0).
+Adding EN signal on $auto$opt_dff.cc:702:run$20132 ($sdff) from module user_proj_example (D = \softshell.cpus[2].core.cpu.picorv32_core.mem_wdata, Q = \softshell.cpus[2].core.cpu.wbm_dat_o).
+Adding EN signal on $flatten\softshell.\cpus[1].core.\soc_mem.\ram.$procdff$16840 ($dff) from module user_proj_example (D = { $flatten\softshell.\cpus[1].core.\soc_mem.\ram.$memrd$\ram3$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:119$2809_DATA $flatten\softshell.\cpus[1].core.\soc_mem.\ram.$memrd$\ram2$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:118$2808_DATA $flatten\softshell.\cpus[1].core.\soc_mem.\ram.$memrd$\ram1$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:117$2807_DATA $flatten\softshell.\cpus[1].core.\soc_mem.\ram.$memrd$\ram0$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:116$2806_DATA }, Q = \softshell.cpus[1].core.soc_mem.ram.dout).
+Adding SRST signal on $flatten\softshell.\cpus[1].core.\soc_mem.$procdff$16310 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[1].core.\soc_mem.$and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:50$2729_Y, Q = \softshell.cpus[1].core.soc_mem.wb_ack_read, rval = 1'0).
+Adding SRST signal on $flatten\softshell.\cpus[1].core.\soc_mem.$procdff$16309 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[1].core.\soc_mem.$ternary$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:49$2725_Y, Q = \softshell.cpus[1].core.soc_mem.wb_ack_o, rval = 1'0).
+Adding EN signal on $flatten\softshell.\cpus[1].core.\gpio.\gpio_ctrl.$procdff$16316 ($dff) from module user_proj_example (D = \softshell.cpus[1].core.cpu.wbm_dat_o, Q = \softshell.cpus[1].core.gpio.gpio_ctrl.gpio_pd).
+Adding EN signal on $flatten\softshell.\cpus[1].core.\gpio.\gpio_ctrl.$procdff$16315 ($dff) from module user_proj_example (D = \softshell.cpus[1].core.cpu.wbm_dat_o, Q = \softshell.cpus[1].core.gpio.gpio_ctrl.gpio_pu).
+Adding EN signal on $flatten\softshell.\cpus[1].core.\gpio.\gpio_ctrl.$procdff$16314 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[1].core.\gpio.\gpio_ctrl.$procmux$5457_Y, Q = \softshell.cpus[1].core.gpio.gpio_ctrl.iomem_ready).
+Adding EN signal on $flatten\softshell.\cpus[1].core.\gpio.\gpio_ctrl.$procdff$16313 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[1].core.\gpio.\gpio_ctrl.$procmux$5471_Y, Q = \softshell.cpus[1].core.gpio.gpio_ctrl.iomem_rdata).
+Adding SRST signal on $flatten\softshell.\cpus[1].core.\gpio.\gpio_ctrl.$procdff$16312 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[1].core.\gpio.\gpio_ctrl.$procmux$5486_Y, Q = \softshell.cpus[1].core.gpio.gpio_ctrl.gpio_oeb, rval = 32'11111111111111111111111111111111).
+Adding EN signal on $auto$opt_dff.cc:702:run$20167 ($sdff) from module user_proj_example (D = $flatten\softshell.\cpus[1].core.\gpio.\gpio_ctrl.$not$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/gpio32_wb.v:117$2715_Y, Q = \softshell.cpus[1].core.gpio.gpio_ctrl.gpio_oeb).
+Adding SRST signal on $flatten\softshell.\cpus[1].core.\gpio.\gpio_ctrl.$procdff$16311 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[1].core.\gpio.\gpio_ctrl.$procmux$5496_Y, Q = \softshell.cpus[1].core.gpio.gpio_ctrl.gpio_out, rval = 0).
+Adding EN signal on $auto$opt_dff.cc:702:run$20173 ($sdff) from module user_proj_example (D = \softshell.cpus[1].core.cpu.wbm_dat_o, Q = \softshell.cpus[1].core.gpio.gpio_ctrl.gpio_out).
+Adding EN signal on $flatten\softshell.\cpus[1].core.\flexio.\out_fifo.$procdff$16327 ($adff) from module user_proj_example (D = $flatten\softshell.\cpus[1].core.\flexio.\out_fifo.$xor$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:131$2006_Y, Q = \softshell.cpus[1].core.flexio.out_fifo.wgray).
+Adding EN signal on $flatten\softshell.\cpus[1].core.\flexio.\out_fifo.$procdff$16326 ($adff) from module user_proj_example (D = \softshell.cpus[1].core.flexio.out_fifo.next_wr_addr, Q = \softshell.cpus[1].core.flexio.out_fifo.wr_addr).
+Adding EN signal on $flatten\softshell.\cpus[1].core.\flexio.\out_fifo.$procdff$16322 ($adff) from module user_proj_example (D = $flatten\softshell.\cpus[1].core.\flexio.\out_fifo.$xor$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:153$2019_Y, Q = \softshell.cpus[1].core.flexio.out_fifo.rgray).
+Adding EN signal on $flatten\softshell.\cpus[1].core.\flexio.\out_fifo.$procdff$16321 ($adff) from module user_proj_example (D = \softshell.cpus[1].core.flexio.out_fifo.next_rd_addr, Q = \softshell.cpus[1].core.flexio.out_fifo.rd_addr).
+Adding EN signal on $flatten\softshell.\cpus[1].core.\flexio.$procdff$16923 ($adff) from module user_proj_example (D = \softshell.cpus[1].core.cpu.picorv32_core.reg_op1, Q = \softshell.cpus[1].core.flexio.out_wr_data).
+Adding EN signal on $flatten\softshell.\cpus[1].core.\flexio.$procdff$16921 ($adff) from module user_proj_example (D = \softshell.cpus[1].core.cpu.picorv32_core.reg_op2 [23:0], Q = \softshell.cpus[1].core.flexio.cfg_clk_div).
+Adding EN signal on $flatten\softshell.\cpus[1].core.\flexio.$procdff$16920 ($adff) from module user_proj_example (D = \softshell.cpus[1].core.cpu.picorv32_core.reg_op1 [19:16], Q = \softshell.cpus[1].core.flexio.cfg_bits_per_clock).
+Adding EN signal on $flatten\softshell.\cpus[1].core.\flexio.$procdff$16919 ($adff) from module user_proj_example (D = \softshell.cpus[1].core.cpu.picorv32_core.reg_op1 [31:24], Q = \softshell.cpus[1].core.flexio.cfg_out_bit_mask).
+Adding EN signal on $flatten\softshell.\cpus[1].core.\flexio.$procdff$16914 ($adff) from module user_proj_example (D = $flatten\softshell.\cpus[1].core.\flexio.$0\out_shift_cnt[4:0], Q = \softshell.cpus[1].core.flexio.out_shift_cnt).
+Adding EN signal on $flatten\softshell.\cpus[1].core.\flexio.$procdff$16913 ($adff) from module user_proj_example (D = $flatten\softshell.\cpus[1].core.\flexio.$0\out_shift_reg[31:0], Q = \softshell.cpus[1].core.flexio.out_shift_reg).
+Adding SRST signal on $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procdff$16687 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:397$3588_Y, Q = \softshell.cpus[1].core.cpu.picorv32_core.last_mem_valid, rval = 1'0).
+Adding SRST signal on $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procdff$16686 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$12011_Y, Q = \softshell.cpus[1].core.cpu.picorv32_core.mem_la_firstword_reg, rval = 1'0).
+Adding EN signal on $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procdff$16685 ($dff) from module user_proj_example (D = \softshell.cpus[1].core.cpu.picorv32_core.mem_rdata_latched [6:0], Q = \softshell.cpus[1].core.cpu.picorv32_core.mem_rdata_q [6:0]).
+Adding EN signal on $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procdff$16683 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$11643_Y, Q = \softshell.cpus[1].core.cpu.picorv32_core.mem_16bit_buffer).
+Adding SRST signal on $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procdff$16682 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$11664_Y, Q = \softshell.cpus[1].core.cpu.picorv32_core.prefetched_high_word, rval = 1'0).
+Adding EN signal on $auto$opt_dff.cc:702:run$20219 ($sdff) from module user_proj_example (D = $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$11655_Y, Q = \softshell.cpus[1].core.cpu.picorv32_core.prefetched_high_word).
+Adding SRST signal on $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procdff$16681 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$11678_Y, Q = \softshell.cpus[1].core.cpu.picorv32_core.mem_la_secondword, rval = 1'0).
+Adding EN signal on $auto$opt_dff.cc:702:run$20227 ($sdff) from module user_proj_example (D = $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$11674_Y, Q = \softshell.cpus[1].core.cpu.picorv32_core.mem_la_secondword).
+Adding EN signal on $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procdff$16680 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$0\mem_state[1:0], Q = \softshell.cpus[1].core.cpu.picorv32_core.mem_state).
+Adding EN signal on $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procdff$16679 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$11713_Y, Q = \softshell.cpus[1].core.cpu.picorv32_core.mem_wstrb).
+Adding EN signal on $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procdff$16678 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$0\mem_valid[0:0], Q = \softshell.cpus[1].core.cpu.picorv32_core.mem_valid).
+Adding EN signal on $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procdff$16677 ($dff) from module user_proj_example (D = \softshell.cpus[1].core.cpu.picorv32_core.mem_la_addr, Q = \softshell.cpus[1].core.cpu.picorv32_core.mem_addr).
+Adding EN signal on $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procdff$16676 ($dff) from module user_proj_example (D = \softshell.cpus[1].core.cpu.picorv32_core.mem_la_wdata, Q = \softshell.cpus[1].core.cpu.picorv32_core.mem_wdata).
+Adding SRST signal on $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procdff$16659 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$reduce_or$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:862$3667_Y, Q = \softshell.cpus[1].core.cpu.picorv32_core.is_compare, rval = 1'0).
+Adding EN signal on $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procdff$16658 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$11046_Y, Q = \softshell.cpus[1].core.cpu.picorv32_core.is_alu_reg_reg).
+Adding EN signal on $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procdff$16657 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$11082_Y, Q = \softshell.cpus[1].core.cpu.picorv32_core.is_alu_reg_imm).
+Adding SRST signal on $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procdff$16655 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$11094_Y, Q = \softshell.cpus[1].core.cpu.picorv32_core.is_beq_bne_blt_bge_bltu_bgeu, rval = 1'0).
+Adding EN signal on $auto$opt_dff.cc:702:run$20277 ($sdff) from module user_proj_example (D = $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$11092_Y, Q = \softshell.cpus[1].core.cpu.picorv32_core.is_beq_bne_blt_bge_bltu_bgeu).
+Adding SRST signal on $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procdff$16652 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$reduce_or$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:858$3663_Y, Q = \softshell.cpus[1].core.cpu.picorv32_core.is_lui_auipc_jal_jalr_addi_add_sub, rval = 1'0).
+Adding EN signal on $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procdff$16650 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$11107_Y, Q = \softshell.cpus[1].core.cpu.picorv32_core.is_sb_sh_sw).
+Adding EN signal on $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procdff$16649 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$logic_or$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1098$3905_Y, Q = \softshell.cpus[1].core.cpu.picorv32_core.is_jalr_addi_slti_sltiu_xori_ori_andi).
+Adding EN signal on $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procdff$16648 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1092$3896_Y, Q = \softshell.cpus[1].core.cpu.picorv32_core.is_slli_srli_srai).
+Adding EN signal on $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procdff$16647 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$11127_Y, Q = \softshell.cpus[1].core.cpu.picorv32_core.is_lb_lh_lw_lbu_lhu).
+Adding EN signal on $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procdff$16645 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$11131_Y, Q = \softshell.cpus[1].core.cpu.picorv32_core.compressed_instr).
+Adding EN signal on $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procdff$16644 ($dff) from module user_proj_example (D = { $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10964_Y $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$11177_Y $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10972_Y $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10940_Y $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10960_Y $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10944_Y $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10948_Y $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10956_Y $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10968_Y $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10952_Y 1'0 }, Q = \softshell.cpus[1].core.cpu.picorv32_core.decoded_imm_j).
+Setting constant 0-bit at position 0 on $auto$opt_dff.cc:764:run$20285 ($dffe) from module user_proj_example.
+Adding EN signal on $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procdff$16643 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$11140_Y, Q = \softshell.cpus[1].core.cpu.picorv32_core.decoded_imm).
+Adding EN signal on $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procdff$16642 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$11173_Y, Q = \softshell.cpus[1].core.cpu.picorv32_core.decoded_rs2).
+Adding EN signal on $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procdff$16641 ($dff) from module user_proj_example (D = { $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10936_Y $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$11023_Y }, Q = \softshell.cpus[1].core.cpu.picorv32_core.decoded_rs1).
+Adding EN signal on $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procdff$16640 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$11224_Y, Q = \softshell.cpus[1].core.cpu.picorv32_core.decoded_rd).
+Adding EN signal on $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procdff$16639 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1090$3883_Y, Q = \softshell.cpus[1].core.cpu.picorv32_core.instr_timer).
+Adding EN signal on $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procdff$16638 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:870$3681_Y, Q = \softshell.cpus[1].core.cpu.picorv32_core.instr_waitirq).
+Adding EN signal on $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procdff$16637 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1089$3879_Y, Q = \softshell.cpus[1].core.cpu.picorv32_core.instr_maskirq).
+Adding EN signal on $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procdff$16636 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:869$3677_Y, Q = \softshell.cpus[1].core.cpu.picorv32_core.instr_retirq).
+Adding EN signal on $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procdff$16635 ($dff) from module user_proj_example (D = 1'0, Q = \softshell.cpus[1].core.cpu.picorv32_core.instr_setq).
+Setting constant 0-bit at position 0 on $auto$opt_dff.cc:764:run$20294 ($dffe) from module user_proj_example.
+Adding EN signal on $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procdff$16634 ($dff) from module user_proj_example (D = 1'0, Q = \softshell.cpus[1].core.cpu.picorv32_core.instr_getq).
+Setting constant 0-bit at position 0 on $auto$opt_dff.cc:764:run$20295 ($dffe) from module user_proj_example.
+Adding EN signal on $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procdff$16633 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$logic_or$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1084$3866_Y, Q = \softshell.cpus[1].core.cpu.picorv32_core.instr_ecall_ebreak).
+Adding EN signal on $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procdff$16632 ($dff) from module user_proj_example (D = 1'0, Q = \softshell.cpus[1].core.cpu.picorv32_core.instr_rdinstrh).
+Setting constant 0-bit at position 0 on $auto$opt_dff.cc:764:run$20297 ($dffe) from module user_proj_example.
+Adding EN signal on $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procdff$16631 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1081$3852_Y, Q = \softshell.cpus[1].core.cpu.picorv32_core.instr_rdinstr).
+Adding EN signal on $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procdff$16630 ($dff) from module user_proj_example (D = 1'0, Q = \softshell.cpus[1].core.cpu.picorv32_core.instr_rdcycleh).
+Setting constant 0-bit at position 0 on $auto$opt_dff.cc:764:run$20299 ($dffe) from module user_proj_example.
+Adding EN signal on $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procdff$16629 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1077$3840_Y, Q = \softshell.cpus[1].core.cpu.picorv32_core.instr_rdcycle).
+Adding SRST signal on $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procdff$16628 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$11250_Y, Q = \softshell.cpus[1].core.cpu.picorv32_core.instr_and, rval = 1'0).
+Adding EN signal on $auto$opt_dff.cc:702:run$20301 ($sdff) from module user_proj_example (D = $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1075$3832_Y, Q = \softshell.cpus[1].core.cpu.picorv32_core.instr_and).
+Adding SRST signal on $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procdff$16627 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$11254_Y, Q = \softshell.cpus[1].core.cpu.picorv32_core.instr_or, rval = 1'0).
+Adding EN signal on $auto$opt_dff.cc:702:run$20303 ($sdff) from module user_proj_example (D = $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1074$3828_Y, Q = \softshell.cpus[1].core.cpu.picorv32_core.instr_or).
+Adding SRST signal on $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procdff$16626 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$11258_Y, Q = \softshell.cpus[1].core.cpu.picorv32_core.instr_sra, rval = 1'0).
+Adding EN signal on $auto$opt_dff.cc:702:run$20305 ($sdff) from module user_proj_example (D = $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1073$3824_Y, Q = \softshell.cpus[1].core.cpu.picorv32_core.instr_sra).
+Adding SRST signal on $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procdff$16625 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$11262_Y, Q = \softshell.cpus[1].core.cpu.picorv32_core.instr_srl, rval = 1'0).
+Adding EN signal on $auto$opt_dff.cc:702:run$20307 ($sdff) from module user_proj_example (D = $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1072$3820_Y, Q = \softshell.cpus[1].core.cpu.picorv32_core.instr_srl).
+Adding SRST signal on $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procdff$16624 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$11266_Y, Q = \softshell.cpus[1].core.cpu.picorv32_core.instr_xor, rval = 1'0).
+Adding EN signal on $auto$opt_dff.cc:702:run$20309 ($sdff) from module user_proj_example (D = $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1071$3816_Y, Q = \softshell.cpus[1].core.cpu.picorv32_core.instr_xor).
+Adding SRST signal on $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procdff$16623 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$11270_Y, Q = \softshell.cpus[1].core.cpu.picorv32_core.instr_sltu, rval = 1'0).
+Adding EN signal on $auto$opt_dff.cc:702:run$20311 ($sdff) from module user_proj_example (D = $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1070$3812_Y, Q = \softshell.cpus[1].core.cpu.picorv32_core.instr_sltu).
+Adding SRST signal on $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procdff$16622 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$11274_Y, Q = \softshell.cpus[1].core.cpu.picorv32_core.instr_slt, rval = 1'0).
+Adding EN signal on $auto$opt_dff.cc:702:run$20313 ($sdff) from module user_proj_example (D = $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1069$3808_Y, Q = \softshell.cpus[1].core.cpu.picorv32_core.instr_slt).
+Adding SRST signal on $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procdff$16621 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$11278_Y, Q = \softshell.cpus[1].core.cpu.picorv32_core.instr_sll, rval = 1'0).
+Adding EN signal on $auto$opt_dff.cc:702:run$20315 ($sdff) from module user_proj_example (D = $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1068$3804_Y, Q = \softshell.cpus[1].core.cpu.picorv32_core.instr_sll).
+Adding SRST signal on $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procdff$16620 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$11282_Y, Q = \softshell.cpus[1].core.cpu.picorv32_core.instr_sub, rval = 1'0).
+Adding EN signal on $auto$opt_dff.cc:702:run$20317 ($sdff) from module user_proj_example (D = $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1067$3800_Y, Q = \softshell.cpus[1].core.cpu.picorv32_core.instr_sub).
+Adding SRST signal on $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procdff$16619 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$11286_Y, Q = \softshell.cpus[1].core.cpu.picorv32_core.instr_add, rval = 1'0).
+Adding EN signal on $auto$opt_dff.cc:702:run$20319 ($sdff) from module user_proj_example (D = $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1066$3796_Y, Q = \softshell.cpus[1].core.cpu.picorv32_core.instr_add).
+Adding EN signal on $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procdff$16618 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1064$3792_Y, Q = \softshell.cpus[1].core.cpu.picorv32_core.instr_srai).
+Adding EN signal on $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procdff$16617 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1063$3788_Y, Q = \softshell.cpus[1].core.cpu.picorv32_core.instr_srli).
+Adding EN signal on $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procdff$16616 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1062$3784_Y, Q = \softshell.cpus[1].core.cpu.picorv32_core.instr_slli).
+Adding SRST signal on $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procdff$16615 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$11296_Y, Q = \softshell.cpus[1].core.cpu.picorv32_core.instr_andi, rval = 1'0).
+Adding EN signal on $auto$opt_dff.cc:702:run$20324 ($sdff) from module user_proj_example (D = $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1060$3780_Y, Q = \softshell.cpus[1].core.cpu.picorv32_core.instr_andi).
+Adding SRST signal on $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procdff$16614 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$11300_Y, Q = \softshell.cpus[1].core.cpu.picorv32_core.instr_ori, rval = 1'0).
+Adding EN signal on $auto$opt_dff.cc:702:run$20326 ($sdff) from module user_proj_example (D = $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1059$3778_Y, Q = \softshell.cpus[1].core.cpu.picorv32_core.instr_ori).
+Adding SRST signal on $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procdff$16613 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$11304_Y, Q = \softshell.cpus[1].core.cpu.picorv32_core.instr_xori, rval = 1'0).
+Adding EN signal on $auto$opt_dff.cc:702:run$20328 ($sdff) from module user_proj_example (D = $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1058$3776_Y, Q = \softshell.cpus[1].core.cpu.picorv32_core.instr_xori).
+Adding SRST signal on $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procdff$16612 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$11308_Y, Q = \softshell.cpus[1].core.cpu.picorv32_core.instr_sltiu, rval = 1'0).
+Adding EN signal on $auto$opt_dff.cc:702:run$20330 ($sdff) from module user_proj_example (D = $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1057$3774_Y, Q = \softshell.cpus[1].core.cpu.picorv32_core.instr_sltiu).
+Adding SRST signal on $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procdff$16611 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$11312_Y, Q = \softshell.cpus[1].core.cpu.picorv32_core.instr_slti, rval = 1'0).
+Adding EN signal on $auto$opt_dff.cc:702:run$20332 ($sdff) from module user_proj_example (D = $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1056$3772_Y, Q = \softshell.cpus[1].core.cpu.picorv32_core.instr_slti).
+Adding SRST signal on $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procdff$16610 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$11316_Y, Q = \softshell.cpus[1].core.cpu.picorv32_core.instr_addi, rval = 1'0).
+Adding EN signal on $auto$opt_dff.cc:702:run$20334 ($sdff) from module user_proj_example (D = $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1055$3770_Y, Q = \softshell.cpus[1].core.cpu.picorv32_core.instr_addi).
+Adding EN signal on $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procdff$16609 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1053$3768_Y, Q = \softshell.cpus[1].core.cpu.picorv32_core.instr_sw).
+Adding EN signal on $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procdff$16608 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1052$3766_Y, Q = \softshell.cpus[1].core.cpu.picorv32_core.instr_sh).
+Adding EN signal on $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procdff$16607 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1051$3764_Y, Q = \softshell.cpus[1].core.cpu.picorv32_core.instr_sb).
+Adding EN signal on $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procdff$16606 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1049$3762_Y, Q = \softshell.cpus[1].core.cpu.picorv32_core.instr_lhu).
+Adding EN signal on $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procdff$16605 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1048$3760_Y, Q = \softshell.cpus[1].core.cpu.picorv32_core.instr_lbu).
+Adding EN signal on $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procdff$16604 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1047$3758_Y, Q = \softshell.cpus[1].core.cpu.picorv32_core.instr_lw).
+Adding EN signal on $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procdff$16603 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1046$3756_Y, Q = \softshell.cpus[1].core.cpu.picorv32_core.instr_lh).
+Adding EN signal on $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procdff$16602 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1045$3754_Y, Q = \softshell.cpus[1].core.cpu.picorv32_core.instr_lb).
+Adding SRST signal on $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procdff$16601 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$11336_Y, Q = \softshell.cpus[1].core.cpu.picorv32_core.instr_bgeu, rval = 1'0).
+Adding EN signal on $auto$opt_dff.cc:702:run$20344 ($sdff) from module user_proj_example (D = $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1043$3752_Y, Q = \softshell.cpus[1].core.cpu.picorv32_core.instr_bgeu).
+Adding SRST signal on $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procdff$16600 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$11340_Y, Q = \softshell.cpus[1].core.cpu.picorv32_core.instr_bltu, rval = 1'0).
+Adding EN signal on $auto$opt_dff.cc:702:run$20346 ($sdff) from module user_proj_example (D = $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1042$3750_Y, Q = \softshell.cpus[1].core.cpu.picorv32_core.instr_bltu).
+Adding SRST signal on $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procdff$16599 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$11344_Y, Q = \softshell.cpus[1].core.cpu.picorv32_core.instr_bge, rval = 1'0).
+Adding EN signal on $auto$opt_dff.cc:702:run$20348 ($sdff) from module user_proj_example (D = $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1041$3748_Y, Q = \softshell.cpus[1].core.cpu.picorv32_core.instr_bge).
+Adding SRST signal on $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procdff$16598 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$11348_Y, Q = \softshell.cpus[1].core.cpu.picorv32_core.instr_blt, rval = 1'0).
+Adding EN signal on $auto$opt_dff.cc:702:run$20350 ($sdff) from module user_proj_example (D = $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1040$3746_Y, Q = \softshell.cpus[1].core.cpu.picorv32_core.instr_blt).
+Adding SRST signal on $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procdff$16597 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$11352_Y, Q = \softshell.cpus[1].core.cpu.picorv32_core.instr_bne, rval = 1'0).
+Adding EN signal on $auto$opt_dff.cc:702:run$20352 ($sdff) from module user_proj_example (D = $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1039$3744_Y, Q = \softshell.cpus[1].core.cpu.picorv32_core.instr_bne).
+Adding SRST signal on $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procdff$16596 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$11356_Y, Q = \softshell.cpus[1].core.cpu.picorv32_core.instr_beq, rval = 1'0).
+Adding EN signal on $auto$opt_dff.cc:702:run$20354 ($sdff) from module user_proj_example (D = $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1038$3742_Y, Q = \softshell.cpus[1].core.cpu.picorv32_core.instr_beq).
+Adding EN signal on $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procdff$16595 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$11369_Y, Q = \softshell.cpus[1].core.cpu.picorv32_core.instr_jalr).
+Adding EN signal on $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procdff$16594 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$11381_Y, Q = \softshell.cpus[1].core.cpu.picorv32_core.instr_jal).
+Adding EN signal on $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procdff$16593 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$eq$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:866$3670_Y, Q = \softshell.cpus[1].core.cpu.picorv32_core.instr_auipc).
+Adding EN signal on $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procdff$16592 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$11401_Y, Q = \softshell.cpus[1].core.cpu.picorv32_core.instr_lui).
+Adding EN signal on $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procdff$16591 ($dff) from module user_proj_example (D = \softshell.cpus[1].core.cpu.picorv32_core.mem_rdata_q, Q = \softshell.cpus[1].core.cpu.picorv32_core.pcpi_insn).
+Adding SRST signal on $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procdff$16585 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$9753_Y, Q = \softshell.cpus[1].core.cpu.picorv32_core.do_waitirq, rval = 1'0).
+Adding SRST signal on $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procdff$16583 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$logic_not$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1424$3995_Y, Q = \softshell.cpus[1].core.cpu.picorv32_core.pcpi_timeout, rval = 1'0).
+Adding SRST signal on $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procdff$16582 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$9992_Y, Q = \softshell.cpus[1].core.cpu.picorv32_core.pcpi_timeout_counter, rval = 4'1111).
+Adding EN signal on $auto$opt_dff.cc:702:run$20369 ($sdff) from module user_proj_example (D = $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$sub$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1421$3994_Y [3:0], Q = \softshell.cpus[1].core.cpu.picorv32_core.pcpi_timeout_counter).
+Adding SRST signal on $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procdff$16580 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10007_Y, Q = \softshell.cpus[1].core.cpu.picorv32_core.latched_rd, rval = 5'00010).
+Adding EN signal on $auto$opt_dff.cc:702:run$20371 ($sdff) from module user_proj_example (D = $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10007_Y, Q = \softshell.cpus[1].core.cpu.picorv32_core.latched_rd).
+Adding SRST signal on $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procdff$16579 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10033_Y, Q = \softshell.cpus[1].core.cpu.picorv32_core.latched_is_lb, rval = 1'0).
+Adding EN signal on $auto$opt_dff.cc:702:run$20379 ($sdff) from module user_proj_example (D = $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10033_Y, Q = \softshell.cpus[1].core.cpu.picorv32_core.latched_is_lb).
+Adding SRST signal on $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procdff$16578 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10046_Y, Q = \softshell.cpus[1].core.cpu.picorv32_core.latched_is_lh, rval = 1'0).
+Adding EN signal on $auto$opt_dff.cc:702:run$20389 ($sdff) from module user_proj_example (D = $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10046_Y, Q = \softshell.cpus[1].core.cpu.picorv32_core.latched_is_lh).
+Adding SRST signal on $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procdff$16577 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10059_Y, Q = \softshell.cpus[1].core.cpu.picorv32_core.latched_is_lu, rval = 1'0).
+Adding EN signal on $auto$opt_dff.cc:702:run$20399 ($sdff) from module user_proj_example (D = $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10059_Y, Q = \softshell.cpus[1].core.cpu.picorv32_core.latched_is_lu).
+Adding EN signal on $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procdff$16575 ($dff) from module user_proj_example (D = \softshell.cpus[1].core.cpu.picorv32_core.compressed_instr, Q = \softshell.cpus[1].core.cpu.picorv32_core.latched_compr).
+Adding SRST signal on $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procdff$16574 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10104_Y, Q = \softshell.cpus[1].core.cpu.picorv32_core.latched_branch, rval = 1'0).
+Adding EN signal on $auto$opt_dff.cc:702:run$20416 ($sdff) from module user_proj_example (D = $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10104_Y, Q = \softshell.cpus[1].core.cpu.picorv32_core.latched_branch).
+Adding SRST signal on $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procdff$16573 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10140_Y, Q = \softshell.cpus[1].core.cpu.picorv32_core.latched_stalu, rval = 1'0).
+Adding EN signal on $auto$opt_dff.cc:702:run$20424 ($sdff) from module user_proj_example (D = $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10140_Y, Q = \softshell.cpus[1].core.cpu.picorv32_core.latched_stalu).
+Adding SRST signal on $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procdff$16572 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10147_Y, Q = \softshell.cpus[1].core.cpu.picorv32_core.latched_store, rval = 1'1).
+Adding EN signal on $auto$opt_dff.cc:702:run$20432 ($sdff) from module user_proj_example (D = $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10147_Y, Q = \softshell.cpus[1].core.cpu.picorv32_core.latched_store).
+Adding SRST signal on $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procdff$16568 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10205_Y, Q = \softshell.cpus[1].core.cpu.picorv32_core.irq_state, rval = 2'00).
+Adding EN signal on $auto$opt_dff.cc:702:run$20442 ($sdff) from module user_proj_example (D = $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$ternary$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1535$4040_Y, Q = \softshell.cpus[1].core.cpu.picorv32_core.irq_state).
+Adding SRST signal on $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procdff$16561 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$9767_Y, Q = \softshell.cpus[1].core.cpu.picorv32_core.decoder_pseudo_trigger, rval = 1'0).
+Adding SRST signal on $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procdff$16558 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10417_Y, Q = \softshell.cpus[1].core.cpu.picorv32_core.mem_do_wdata, rval = 1'1).
+Adding EN signal on $auto$opt_dff.cc:702:run$20453 ($sdff) from module user_proj_example (D = 1'0, Q = \softshell.cpus[1].core.cpu.picorv32_core.mem_do_wdata).
+Adding SRST signal on $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procdff$16557 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10421_Y, Q = \softshell.cpus[1].core.cpu.picorv32_core.mem_do_rdata, rval = 1'1).
+Adding EN signal on $auto$opt_dff.cc:702:run$20455 ($sdff) from module user_proj_example (D = 1'0, Q = \softshell.cpus[1].core.cpu.picorv32_core.mem_do_rdata).
+Adding SRST signal on $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procdff$16556 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10495_Y, Q = \softshell.cpus[1].core.cpu.picorv32_core.mem_do_rinst, rval = 1'1).
+Adding EN signal on $auto$opt_dff.cc:702:run$20457 ($sdff) from module user_proj_example (D = $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10495_Y, Q = \softshell.cpus[1].core.cpu.picorv32_core.mem_do_rinst).
+Adding SRST signal on $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procdff$16555 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10520_Y, Q = \softshell.cpus[1].core.cpu.picorv32_core.mem_do_prefetch, rval = 1'0).
+Adding EN signal on $auto$opt_dff.cc:702:run$20469 ($sdff) from module user_proj_example (D = $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1568$4054_Y, Q = \softshell.cpus[1].core.cpu.picorv32_core.mem_do_prefetch).
+Adding SRST signal on $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procdff$16553 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10566_Y, Q = \softshell.cpus[1].core.cpu.picorv32_core.timer, rval = 0).
+Adding SRST signal on $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procdff$16551 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10584_Y, Q = \softshell.cpus[1].core.cpu.picorv32_core.irq_mask, rval = 32'11111111111111111111111111111111).
+Adding EN signal on $auto$opt_dff.cc:702:run$20482 ($sdff) from module user_proj_example (D = \softshell.cpus[1].core.cpu.picorv32_core.cpuregs_rs1, Q = \softshell.cpus[1].core.cpu.picorv32_core.irq_mask).
+Adding SRST signal on $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procdff$16550 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10603_Y, Q = \softshell.cpus[1].core.cpu.picorv32_core.irq_active, rval = 1'0).
+Adding EN signal on $auto$opt_dff.cc:702:run$20486 ($sdff) from module user_proj_example (D = $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10603_Y, Q = \softshell.cpus[1].core.cpu.picorv32_core.irq_active).
+Adding SRST signal on $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procdff$16549 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10628_Y, Q = \softshell.cpus[1].core.cpu.picorv32_core.irq_delay, rval = 1'0).
+Adding EN signal on $auto$opt_dff.cc:702:run$20496 ($sdff) from module user_proj_example (D = \softshell.cpus[1].core.cpu.picorv32_core.irq_active, Q = \softshell.cpus[1].core.cpu.picorv32_core.irq_delay).
+Adding SRST signal on $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procdff$16547 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$9900_Y, Q = \softshell.cpus[1].core.cpu.picorv32_core.reg_out, rval = 128).
+Adding EN signal on $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procdff$16546 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10641_Y, Q = \softshell.cpus[1].core.cpu.picorv32_core.reg_op2).
+Adding EN signal on $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procdff$16545 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10663_Y, Q = \softshell.cpus[1].core.cpu.picorv32_core.reg_op1).
+Adding SRST signal on $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procdff$16544 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10724_Y, Q = \softshell.cpus[1].core.cpu.picorv32_core.reg_next_pc, rval = 809631744).
+Adding EN signal on $auto$opt_dff.cc:702:run$20525 ($sdff) from module user_proj_example (D = $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10722_Y, Q = \softshell.cpus[1].core.cpu.picorv32_core.reg_next_pc).
+Adding SRST signal on $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procdff$16543 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10736_Y, Q = \softshell.cpus[1].core.cpu.picorv32_core.reg_pc, rval = 809631744).
+Adding EN signal on $auto$opt_dff.cc:702:run$20527 ($sdff) from module user_proj_example (D = $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$3\current_pc[31:0], Q = \softshell.cpus[1].core.cpu.picorv32_core.reg_pc).
+Adding SRST signal on $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procdff$16542 ($dff) from module user_proj_example (D = { $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$9634_Y $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$9599_Y }, Q = \softshell.cpus[1].core.cpu.picorv32_core.count_instr, rval = 64'0000000000000000000000000000000000000000000000000000000000000000).
+Adding EN signal on $auto$opt_dff.cc:702:run$20529 ($sdff) from module user_proj_example (D = { 32'00000000000000000000000000000000 $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1559$4050_Y [31:0] }, Q = \softshell.cpus[1].core.cpu.picorv32_core.count_instr).
+Setting constant 0-bit at position 32 on $auto$opt_dff.cc:764:run$20536 ($sdffe) from module user_proj_example.
+Setting constant 0-bit at position 33 on $auto$opt_dff.cc:764:run$20536 ($sdffe) from module user_proj_example.
+Setting constant 0-bit at position 34 on $auto$opt_dff.cc:764:run$20536 ($sdffe) from module user_proj_example.
+Setting constant 0-bit at position 35 on $auto$opt_dff.cc:764:run$20536 ($sdffe) from module user_proj_example.
+Setting constant 0-bit at position 36 on $auto$opt_dff.cc:764:run$20536 ($sdffe) from module user_proj_example.
+Setting constant 0-bit at position 37 on $auto$opt_dff.cc:764:run$20536 ($sdffe) from module user_proj_example.
+Setting constant 0-bit at position 38 on $auto$opt_dff.cc:764:run$20536 ($sdffe) from module user_proj_example.
+Setting constant 0-bit at position 39 on $auto$opt_dff.cc:764:run$20536 ($sdffe) from module user_proj_example.
+Setting constant 0-bit at position 40 on $auto$opt_dff.cc:764:run$20536 ($sdffe) from module user_proj_example.
+Setting constant 0-bit at position 41 on $auto$opt_dff.cc:764:run$20536 ($sdffe) from module user_proj_example.
+Setting constant 0-bit at position 42 on $auto$opt_dff.cc:764:run$20536 ($sdffe) from module user_proj_example.
+Setting constant 0-bit at position 43 on $auto$opt_dff.cc:764:run$20536 ($sdffe) from module user_proj_example.
+Setting constant 0-bit at position 44 on $auto$opt_dff.cc:764:run$20536 ($sdffe) from module user_proj_example.
+Setting constant 0-bit at position 45 on $auto$opt_dff.cc:764:run$20536 ($sdffe) from module user_proj_example.
+Setting constant 0-bit at position 46 on $auto$opt_dff.cc:764:run$20536 ($sdffe) from module user_proj_example.
+Setting constant 0-bit at position 47 on $auto$opt_dff.cc:764:run$20536 ($sdffe) from module user_proj_example.
+Setting constant 0-bit at position 48 on $auto$opt_dff.cc:764:run$20536 ($sdffe) from module user_proj_example.
+Setting constant 0-bit at position 49 on $auto$opt_dff.cc:764:run$20536 ($sdffe) from module user_proj_example.
+Setting constant 0-bit at position 50 on $auto$opt_dff.cc:764:run$20536 ($sdffe) from module user_proj_example.
+Setting constant 0-bit at position 51 on $auto$opt_dff.cc:764:run$20536 ($sdffe) from module user_proj_example.
+Setting constant 0-bit at position 52 on $auto$opt_dff.cc:764:run$20536 ($sdffe) from module user_proj_example.
+Setting constant 0-bit at position 53 on $auto$opt_dff.cc:764:run$20536 ($sdffe) from module user_proj_example.
+Setting constant 0-bit at position 54 on $auto$opt_dff.cc:764:run$20536 ($sdffe) from module user_proj_example.
+Setting constant 0-bit at position 55 on $auto$opt_dff.cc:764:run$20536 ($sdffe) from module user_proj_example.
+Setting constant 0-bit at position 56 on $auto$opt_dff.cc:764:run$20536 ($sdffe) from module user_proj_example.
+Setting constant 0-bit at position 57 on $auto$opt_dff.cc:764:run$20536 ($sdffe) from module user_proj_example.
+Setting constant 0-bit at position 58 on $auto$opt_dff.cc:764:run$20536 ($sdffe) from module user_proj_example.
+Setting constant 0-bit at position 59 on $auto$opt_dff.cc:764:run$20536 ($sdffe) from module user_proj_example.
+Setting constant 0-bit at position 60 on $auto$opt_dff.cc:764:run$20536 ($sdffe) from module user_proj_example.
+Setting constant 0-bit at position 61 on $auto$opt_dff.cc:764:run$20536 ($sdffe) from module user_proj_example.
+Setting constant 0-bit at position 62 on $auto$opt_dff.cc:764:run$20536 ($sdffe) from module user_proj_example.
+Setting constant 0-bit at position 63 on $auto$opt_dff.cc:764:run$20536 ($sdffe) from module user_proj_example.
+Adding SRST signal on $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procdff$16541 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1428$3996_Y [31:0], Q = \softshell.cpus[1].core.cpu.picorv32_core.count_cycle [31:0], rval = 0).
+Adding SRST signal on $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procdff$16537 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$9986_Y, Q = \softshell.cpus[1].core.cpu.picorv32_core.trap, rval = 1'0).
+Adding SRST signal on $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procdff$16536 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10797_Y, Q = \softshell.cpus[1].core.cpu.picorv32_core.pcpi_valid, rval = 1'0).
+Adding EN signal on $auto$opt_dff.cc:702:run$20539 ($sdff) from module user_proj_example (D = $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10793_Y, Q = \softshell.cpus[1].core.cpu.picorv32_core.pcpi_valid).
+Adding EN signal on $flatten\softshell.\cpus[1].core.\cpu.$procdff$16299 ($dff) from module user_proj_example (D = \softshell.cpus[1].core.cpu.wbm_dat_i, Q = \softshell.cpus[1].core.cpu.mem_rdata).
+Adding EN signal on $flatten\softshell.\cpus[1].core.\cpu.$procdff$16298 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[1].core.\cpu.$procmux$5213_Y, Q = \softshell.cpus[1].core.cpu.mem_ready).
+Adding SRST signal on $flatten\softshell.\cpus[1].core.\cpu.$procdff$16296 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[1].core.\cpu.$procmux$5244_Y, Q = \softshell.cpus[1].core.cpu.wbm_sel_o, rval = 4'0000).
+Adding EN signal on $auto$opt_dff.cc:702:run$20559 ($sdff) from module user_proj_example (D = \softshell.cpus[1].core.cpu.picorv32_core.mem_wstrb, Q = \softshell.cpus[1].core.cpu.wbm_sel_o).
+Adding SRST signal on $flatten\softshell.\cpus[1].core.\cpu.$procdff$16295 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[1].core.\cpu.$procmux$5253_Y, Q = \softshell.cpus[1].core.cpu.wbm_we_o, rval = 1'0).
+Adding EN signal on $auto$opt_dff.cc:702:run$20563 ($sdff) from module user_proj_example (D = $flatten\softshell.\cpus[1].core.\cpu.$procmux$5253_Y, Q = \softshell.cpus[1].core.cpu.wbm_we_o).
+Adding SRST signal on $flatten\softshell.\cpus[1].core.\cpu.$procdff$16294 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[1].core.\cpu.$procmux$5266_Y, Q = \softshell.cpus[1].core.cpu.wbm_cyc_o, rval = 1'0).
+Adding EN signal on $auto$opt_dff.cc:702:run$20571 ($sdff) from module user_proj_example (D = $flatten\softshell.\cpus[1].core.\cpu.$procmux$5266_Y, Q = \softshell.cpus[1].core.cpu.wbm_cyc_o).
+Adding SRST signal on $flatten\softshell.\cpus[1].core.\cpu.$procdff$16293 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[1].core.\cpu.$procmux$5279_Y, Q = \softshell.cpus[1].core.cpu.wbm_stb_o, rval = 1'0).
+Adding EN signal on $auto$opt_dff.cc:702:run$20579 ($sdff) from module user_proj_example (D = $flatten\softshell.\cpus[1].core.\cpu.$procmux$5279_Y, Q = \softshell.cpus[1].core.cpu.wbm_stb_o).
+Adding SRST signal on $flatten\softshell.\cpus[1].core.\cpu.$procdff$16292 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[1].core.\cpu.$procmux$5294_Y, Q = \softshell.cpus[1].core.cpu.wbm_adr_o, rval = 0).
+Adding EN signal on $auto$opt_dff.cc:702:run$20587 ($sdff) from module user_proj_example (D = \softshell.cpus[1].core.cpu.picorv32_core.mem_addr, Q = \softshell.cpus[1].core.cpu.wbm_adr_o).
+Adding SRST signal on $flatten\softshell.\cpus[1].core.\cpu.$procdff$16291 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[1].core.\cpu.$procmux$5305_Y, Q = \softshell.cpus[1].core.cpu.wbm_dat_o, rval = 0).
+Adding EN signal on $auto$opt_dff.cc:702:run$20591 ($sdff) from module user_proj_example (D = \softshell.cpus[1].core.cpu.picorv32_core.mem_wdata, Q = \softshell.cpus[1].core.cpu.wbm_dat_o).
+Adding EN signal on $flatten\softshell.\cpus[0].core.\soc_mem.\ram.$procdff$16840 ($dff) from module user_proj_example (D = { $flatten\softshell.\cpus[0].core.\soc_mem.\ram.$memrd$\ram3$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:119$2809_DATA $flatten\softshell.\cpus[0].core.\soc_mem.\ram.$memrd$\ram2$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:118$2808_DATA $flatten\softshell.\cpus[0].core.\soc_mem.\ram.$memrd$\ram1$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:117$2807_DATA $flatten\softshell.\cpus[0].core.\soc_mem.\ram.$memrd$\ram0$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:116$2806_DATA }, Q = \softshell.cpus[0].core.soc_mem.ram.dout).
+Adding SRST signal on $flatten\softshell.\cpus[0].core.\soc_mem.$procdff$16310 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[0].core.\soc_mem.$and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:50$2729_Y, Q = \softshell.cpus[0].core.soc_mem.wb_ack_read, rval = 1'0).
+Adding SRST signal on $flatten\softshell.\cpus[0].core.\soc_mem.$procdff$16309 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[0].core.\soc_mem.$ternary$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:49$2725_Y, Q = \softshell.cpus[0].core.soc_mem.wb_ack_o, rval = 1'0).
+Adding EN signal on $flatten\softshell.\cpus[0].core.\gpio.\gpio_ctrl.$procdff$16316 ($dff) from module user_proj_example (D = \softshell.cpus[0].core.cpu.wbm_dat_o, Q = \softshell.cpus[0].core.gpio.gpio_ctrl.gpio_pd).
+Adding EN signal on $flatten\softshell.\cpus[0].core.\gpio.\gpio_ctrl.$procdff$16315 ($dff) from module user_proj_example (D = \softshell.cpus[0].core.cpu.wbm_dat_o, Q = \softshell.cpus[0].core.gpio.gpio_ctrl.gpio_pu).
+Adding EN signal on $flatten\softshell.\cpus[0].core.\gpio.\gpio_ctrl.$procdff$16314 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[0].core.\gpio.\gpio_ctrl.$procmux$5457_Y, Q = \softshell.cpus[0].core.gpio.gpio_ctrl.iomem_ready).
+Adding EN signal on $flatten\softshell.\cpus[0].core.\gpio.\gpio_ctrl.$procdff$16313 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[0].core.\gpio.\gpio_ctrl.$procmux$5471_Y, Q = \softshell.cpus[0].core.gpio.gpio_ctrl.iomem_rdata).
+Adding SRST signal on $flatten\softshell.\cpus[0].core.\gpio.\gpio_ctrl.$procdff$16312 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[0].core.\gpio.\gpio_ctrl.$procmux$5486_Y, Q = \softshell.cpus[0].core.gpio.gpio_ctrl.gpio_oeb, rval = 32'11111111111111111111111111111111).
+Adding EN signal on $auto$opt_dff.cc:702:run$20626 ($sdff) from module user_proj_example (D = $flatten\softshell.\cpus[0].core.\gpio.\gpio_ctrl.$not$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/gpio32_wb.v:117$2715_Y, Q = \softshell.cpus[0].core.gpio.gpio_ctrl.gpio_oeb).
+Adding SRST signal on $flatten\softshell.\cpus[0].core.\gpio.\gpio_ctrl.$procdff$16311 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[0].core.\gpio.\gpio_ctrl.$procmux$5496_Y, Q = \softshell.cpus[0].core.gpio.gpio_ctrl.gpio_out, rval = 0).
+Adding EN signal on $auto$opt_dff.cc:702:run$20632 ($sdff) from module user_proj_example (D = \softshell.cpus[0].core.cpu.wbm_dat_o, Q = \softshell.cpus[0].core.gpio.gpio_ctrl.gpio_out).
+Adding EN signal on $flatten\softshell.\cpus[0].core.\flexio.\out_fifo.$procdff$16327 ($adff) from module user_proj_example (D = $flatten\softshell.\cpus[0].core.\flexio.\out_fifo.$xor$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:131$2006_Y, Q = \softshell.cpus[0].core.flexio.out_fifo.wgray).
+Adding EN signal on $flatten\softshell.\cpus[0].core.\flexio.\out_fifo.$procdff$16326 ($adff) from module user_proj_example (D = \softshell.cpus[0].core.flexio.out_fifo.next_wr_addr, Q = \softshell.cpus[0].core.flexio.out_fifo.wr_addr).
+Adding EN signal on $flatten\softshell.\cpus[0].core.\flexio.\out_fifo.$procdff$16322 ($adff) from module user_proj_example (D = $flatten\softshell.\cpus[0].core.\flexio.\out_fifo.$xor$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:153$2019_Y, Q = \softshell.cpus[0].core.flexio.out_fifo.rgray).
+Adding EN signal on $flatten\softshell.\cpus[0].core.\flexio.\out_fifo.$procdff$16321 ($adff) from module user_proj_example (D = \softshell.cpus[0].core.flexio.out_fifo.next_rd_addr, Q = \softshell.cpus[0].core.flexio.out_fifo.rd_addr).
+Adding EN signal on $flatten\softshell.\cpus[0].core.\flexio.$procdff$16923 ($adff) from module user_proj_example (D = \softshell.cpus[0].core.cpu.picorv32_core.reg_op1, Q = \softshell.cpus[0].core.flexio.out_wr_data).
+Adding EN signal on $flatten\softshell.\cpus[0].core.\flexio.$procdff$16921 ($adff) from module user_proj_example (D = \softshell.cpus[0].core.cpu.picorv32_core.reg_op2 [23:0], Q = \softshell.cpus[0].core.flexio.cfg_clk_div).
+Adding EN signal on $flatten\softshell.\cpus[0].core.\flexio.$procdff$16920 ($adff) from module user_proj_example (D = \softshell.cpus[0].core.cpu.picorv32_core.reg_op1 [19:16], Q = \softshell.cpus[0].core.flexio.cfg_bits_per_clock).
+Adding EN signal on $flatten\softshell.\cpus[0].core.\flexio.$procdff$16919 ($adff) from module user_proj_example (D = \softshell.cpus[0].core.cpu.picorv32_core.reg_op1 [31:24], Q = \softshell.cpus[0].core.flexio.cfg_out_bit_mask).
+Adding EN signal on $flatten\softshell.\cpus[0].core.\flexio.$procdff$16914 ($adff) from module user_proj_example (D = $flatten\softshell.\cpus[0].core.\flexio.$0\out_shift_cnt[4:0], Q = \softshell.cpus[0].core.flexio.out_shift_cnt).
+Adding EN signal on $flatten\softshell.\cpus[0].core.\flexio.$procdff$16913 ($adff) from module user_proj_example (D = $flatten\softshell.\cpus[0].core.\flexio.$0\out_shift_reg[31:0], Q = \softshell.cpus[0].core.flexio.out_shift_reg).
+Adding SRST signal on $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procdff$16479 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:397$4271_Y, Q = \softshell.cpus[0].core.cpu.picorv32_core.last_mem_valid, rval = 1'0).
+Adding SRST signal on $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procdff$16478 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$8365_Y, Q = \softshell.cpus[0].core.cpu.picorv32_core.mem_la_firstword_reg, rval = 1'0).
+Adding EN signal on $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procdff$16477 ($dff) from module user_proj_example (D = \softshell.cpus[0].core.cpu.picorv32_core.mem_rdata_latched [6:0], Q = \softshell.cpus[0].core.cpu.picorv32_core.mem_rdata_q [6:0]).
+Adding EN signal on $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procdff$16475 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$7997_Y, Q = \softshell.cpus[0].core.cpu.picorv32_core.mem_16bit_buffer).
+Adding SRST signal on $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procdff$16474 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$8018_Y, Q = \softshell.cpus[0].core.cpu.picorv32_core.prefetched_high_word, rval = 1'0).
+Adding EN signal on $auto$opt_dff.cc:702:run$20678 ($sdff) from module user_proj_example (D = $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$8009_Y, Q = \softshell.cpus[0].core.cpu.picorv32_core.prefetched_high_word).
+Adding SRST signal on $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procdff$16473 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$8032_Y, Q = \softshell.cpus[0].core.cpu.picorv32_core.mem_la_secondword, rval = 1'0).
+Adding EN signal on $auto$opt_dff.cc:702:run$20686 ($sdff) from module user_proj_example (D = $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$8028_Y, Q = \softshell.cpus[0].core.cpu.picorv32_core.mem_la_secondword).
+Adding EN signal on $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procdff$16472 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$0\mem_state[1:0], Q = \softshell.cpus[0].core.cpu.picorv32_core.mem_state).
+Adding EN signal on $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procdff$16471 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$8067_Y, Q = \softshell.cpus[0].core.cpu.picorv32_core.mem_wstrb).
+Adding EN signal on $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procdff$16470 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$0\mem_valid[0:0], Q = \softshell.cpus[0].core.cpu.picorv32_core.mem_valid).
+Adding EN signal on $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procdff$16469 ($dff) from module user_proj_example (D = \softshell.cpus[0].core.cpu.picorv32_core.mem_la_addr, Q = \softshell.cpus[0].core.cpu.picorv32_core.mem_addr).
+Adding EN signal on $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procdff$16468 ($dff) from module user_proj_example (D = \softshell.cpus[0].core.cpu.picorv32_core.mem_la_wdata, Q = \softshell.cpus[0].core.cpu.picorv32_core.mem_wdata).
+Adding SRST signal on $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procdff$16451 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$reduce_or$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:862$4350_Y, Q = \softshell.cpus[0].core.cpu.picorv32_core.is_compare, rval = 1'0).
+Adding EN signal on $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procdff$16450 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$7400_Y, Q = \softshell.cpus[0].core.cpu.picorv32_core.is_alu_reg_reg).
+Adding EN signal on $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procdff$16449 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$7436_Y, Q = \softshell.cpus[0].core.cpu.picorv32_core.is_alu_reg_imm).
+Adding SRST signal on $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procdff$16447 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$7448_Y, Q = \softshell.cpus[0].core.cpu.picorv32_core.is_beq_bne_blt_bge_bltu_bgeu, rval = 1'0).
+Adding EN signal on $auto$opt_dff.cc:702:run$20736 ($sdff) from module user_proj_example (D = $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$7446_Y, Q = \softshell.cpus[0].core.cpu.picorv32_core.is_beq_bne_blt_bge_bltu_bgeu).
+Adding SRST signal on $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procdff$16444 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$reduce_or$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:858$4346_Y, Q = \softshell.cpus[0].core.cpu.picorv32_core.is_lui_auipc_jal_jalr_addi_add_sub, rval = 1'0).
+Adding EN signal on $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procdff$16442 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$7461_Y, Q = \softshell.cpus[0].core.cpu.picorv32_core.is_sb_sh_sw).
+Adding EN signal on $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procdff$16441 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$logic_or$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1098$4588_Y, Q = \softshell.cpus[0].core.cpu.picorv32_core.is_jalr_addi_slti_sltiu_xori_ori_andi).
+Adding EN signal on $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procdff$16440 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1092$4579_Y, Q = \softshell.cpus[0].core.cpu.picorv32_core.is_slli_srli_srai).
+Adding EN signal on $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procdff$16439 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$7481_Y, Q = \softshell.cpus[0].core.cpu.picorv32_core.is_lb_lh_lw_lbu_lhu).
+Adding EN signal on $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procdff$16437 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$7485_Y, Q = \softshell.cpus[0].core.cpu.picorv32_core.compressed_instr).
+Adding EN signal on $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procdff$16436 ($dff) from module user_proj_example (D = { $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$7318_Y $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$7531_Y $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$7326_Y $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$7294_Y $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$7314_Y $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$7298_Y $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$7302_Y $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$7310_Y $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$7322_Y $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$7306_Y 1'0 }, Q = \softshell.cpus[0].core.cpu.picorv32_core.decoded_imm_j).
+Setting constant 0-bit at position 0 on $auto$opt_dff.cc:764:run$20744 ($dffe) from module user_proj_example.
+Adding EN signal on $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procdff$16435 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$7494_Y, Q = \softshell.cpus[0].core.cpu.picorv32_core.decoded_imm).
+Adding EN signal on $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procdff$16434 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$7527_Y, Q = \softshell.cpus[0].core.cpu.picorv32_core.decoded_rs2).
+Adding EN signal on $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procdff$16433 ($dff) from module user_proj_example (D = { $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$7290_Y $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$7377_Y }, Q = \softshell.cpus[0].core.cpu.picorv32_core.decoded_rs1).
+Adding EN signal on $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procdff$16432 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$7578_Y, Q = \softshell.cpus[0].core.cpu.picorv32_core.decoded_rd).
+Adding EN signal on $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procdff$16431 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1090$4566_Y, Q = \softshell.cpus[0].core.cpu.picorv32_core.instr_timer).
+Adding EN signal on $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procdff$16430 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:870$4364_Y, Q = \softshell.cpus[0].core.cpu.picorv32_core.instr_waitirq).
+Adding EN signal on $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procdff$16429 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1089$4562_Y, Q = \softshell.cpus[0].core.cpu.picorv32_core.instr_maskirq).
+Adding EN signal on $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procdff$16428 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:869$4360_Y, Q = \softshell.cpus[0].core.cpu.picorv32_core.instr_retirq).
+Adding EN signal on $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procdff$16427 ($dff) from module user_proj_example (D = 1'0, Q = \softshell.cpus[0].core.cpu.picorv32_core.instr_setq).
+Setting constant 0-bit at position 0 on $auto$opt_dff.cc:764:run$20753 ($dffe) from module user_proj_example.
+Adding EN signal on $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procdff$16426 ($dff) from module user_proj_example (D = 1'0, Q = \softshell.cpus[0].core.cpu.picorv32_core.instr_getq).
+Setting constant 0-bit at position 0 on $auto$opt_dff.cc:764:run$20754 ($dffe) from module user_proj_example.
+Adding EN signal on $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procdff$16425 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$logic_or$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1084$4549_Y, Q = \softshell.cpus[0].core.cpu.picorv32_core.instr_ecall_ebreak).
+Adding EN signal on $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procdff$16424 ($dff) from module user_proj_example (D = 1'0, Q = \softshell.cpus[0].core.cpu.picorv32_core.instr_rdinstrh).
+Setting constant 0-bit at position 0 on $auto$opt_dff.cc:764:run$20756 ($dffe) from module user_proj_example.
+Adding EN signal on $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procdff$16423 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1081$4535_Y, Q = \softshell.cpus[0].core.cpu.picorv32_core.instr_rdinstr).
+Adding EN signal on $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procdff$16422 ($dff) from module user_proj_example (D = 1'0, Q = \softshell.cpus[0].core.cpu.picorv32_core.instr_rdcycleh).
+Setting constant 0-bit at position 0 on $auto$opt_dff.cc:764:run$20758 ($dffe) from module user_proj_example.
+Adding EN signal on $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procdff$16421 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1077$4523_Y, Q = \softshell.cpus[0].core.cpu.picorv32_core.instr_rdcycle).
+Adding SRST signal on $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procdff$16420 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$7604_Y, Q = \softshell.cpus[0].core.cpu.picorv32_core.instr_and, rval = 1'0).
+Adding EN signal on $auto$opt_dff.cc:702:run$20760 ($sdff) from module user_proj_example (D = $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1075$4515_Y, Q = \softshell.cpus[0].core.cpu.picorv32_core.instr_and).
+Adding SRST signal on $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procdff$16419 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$7608_Y, Q = \softshell.cpus[0].core.cpu.picorv32_core.instr_or, rval = 1'0).
+Adding EN signal on $auto$opt_dff.cc:702:run$20762 ($sdff) from module user_proj_example (D = $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1074$4511_Y, Q = \softshell.cpus[0].core.cpu.picorv32_core.instr_or).
+Adding SRST signal on $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procdff$16418 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$7612_Y, Q = \softshell.cpus[0].core.cpu.picorv32_core.instr_sra, rval = 1'0).
+Adding EN signal on $auto$opt_dff.cc:702:run$20764 ($sdff) from module user_proj_example (D = $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1073$4507_Y, Q = \softshell.cpus[0].core.cpu.picorv32_core.instr_sra).
+Adding SRST signal on $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procdff$16417 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$7616_Y, Q = \softshell.cpus[0].core.cpu.picorv32_core.instr_srl, rval = 1'0).
+Adding EN signal on $auto$opt_dff.cc:702:run$20766 ($sdff) from module user_proj_example (D = $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1072$4503_Y, Q = \softshell.cpus[0].core.cpu.picorv32_core.instr_srl).
+Adding SRST signal on $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procdff$16416 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$7620_Y, Q = \softshell.cpus[0].core.cpu.picorv32_core.instr_xor, rval = 1'0).
+Adding EN signal on $auto$opt_dff.cc:702:run$20768 ($sdff) from module user_proj_example (D = $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1071$4499_Y, Q = \softshell.cpus[0].core.cpu.picorv32_core.instr_xor).
+Adding SRST signal on $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procdff$16415 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$7624_Y, Q = \softshell.cpus[0].core.cpu.picorv32_core.instr_sltu, rval = 1'0).
+Adding EN signal on $auto$opt_dff.cc:702:run$20770 ($sdff) from module user_proj_example (D = $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1070$4495_Y, Q = \softshell.cpus[0].core.cpu.picorv32_core.instr_sltu).
+Adding SRST signal on $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procdff$16414 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$7628_Y, Q = \softshell.cpus[0].core.cpu.picorv32_core.instr_slt, rval = 1'0).
+Adding EN signal on $auto$opt_dff.cc:702:run$20772 ($sdff) from module user_proj_example (D = $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1069$4491_Y, Q = \softshell.cpus[0].core.cpu.picorv32_core.instr_slt).
+Adding SRST signal on $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procdff$16413 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$7632_Y, Q = \softshell.cpus[0].core.cpu.picorv32_core.instr_sll, rval = 1'0).
+Adding EN signal on $auto$opt_dff.cc:702:run$20774 ($sdff) from module user_proj_example (D = $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1068$4487_Y, Q = \softshell.cpus[0].core.cpu.picorv32_core.instr_sll).
+Adding SRST signal on $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procdff$16412 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$7636_Y, Q = \softshell.cpus[0].core.cpu.picorv32_core.instr_sub, rval = 1'0).
+Adding EN signal on $auto$opt_dff.cc:702:run$20776 ($sdff) from module user_proj_example (D = $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1067$4483_Y, Q = \softshell.cpus[0].core.cpu.picorv32_core.instr_sub).
+Adding SRST signal on $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procdff$16411 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$7640_Y, Q = \softshell.cpus[0].core.cpu.picorv32_core.instr_add, rval = 1'0).
+Adding EN signal on $auto$opt_dff.cc:702:run$20778 ($sdff) from module user_proj_example (D = $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1066$4479_Y, Q = \softshell.cpus[0].core.cpu.picorv32_core.instr_add).
+Adding EN signal on $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procdff$16410 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1064$4475_Y, Q = \softshell.cpus[0].core.cpu.picorv32_core.instr_srai).
+Adding EN signal on $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procdff$16409 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1063$4471_Y, Q = \softshell.cpus[0].core.cpu.picorv32_core.instr_srli).
+Adding EN signal on $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procdff$16408 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1062$4467_Y, Q = \softshell.cpus[0].core.cpu.picorv32_core.instr_slli).
+Adding SRST signal on $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procdff$16407 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$7650_Y, Q = \softshell.cpus[0].core.cpu.picorv32_core.instr_andi, rval = 1'0).
+Adding EN signal on $auto$opt_dff.cc:702:run$20783 ($sdff) from module user_proj_example (D = $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1060$4463_Y, Q = \softshell.cpus[0].core.cpu.picorv32_core.instr_andi).
+Adding SRST signal on $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procdff$16406 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$7654_Y, Q = \softshell.cpus[0].core.cpu.picorv32_core.instr_ori, rval = 1'0).
+Adding EN signal on $auto$opt_dff.cc:702:run$20785 ($sdff) from module user_proj_example (D = $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1059$4461_Y, Q = \softshell.cpus[0].core.cpu.picorv32_core.instr_ori).
+Adding SRST signal on $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procdff$16405 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$7658_Y, Q = \softshell.cpus[0].core.cpu.picorv32_core.instr_xori, rval = 1'0).
+Adding EN signal on $auto$opt_dff.cc:702:run$20787 ($sdff) from module user_proj_example (D = $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1058$4459_Y, Q = \softshell.cpus[0].core.cpu.picorv32_core.instr_xori).
+Adding SRST signal on $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procdff$16404 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$7662_Y, Q = \softshell.cpus[0].core.cpu.picorv32_core.instr_sltiu, rval = 1'0).
+Adding EN signal on $auto$opt_dff.cc:702:run$20789 ($sdff) from module user_proj_example (D = $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1057$4457_Y, Q = \softshell.cpus[0].core.cpu.picorv32_core.instr_sltiu).
+Adding SRST signal on $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procdff$16403 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$7666_Y, Q = \softshell.cpus[0].core.cpu.picorv32_core.instr_slti, rval = 1'0).
+Adding EN signal on $auto$opt_dff.cc:702:run$20791 ($sdff) from module user_proj_example (D = $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1056$4455_Y, Q = \softshell.cpus[0].core.cpu.picorv32_core.instr_slti).
+Adding SRST signal on $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procdff$16402 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$7670_Y, Q = \softshell.cpus[0].core.cpu.picorv32_core.instr_addi, rval = 1'0).
+Adding EN signal on $auto$opt_dff.cc:702:run$20793 ($sdff) from module user_proj_example (D = $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1055$4453_Y, Q = \softshell.cpus[0].core.cpu.picorv32_core.instr_addi).
+Adding EN signal on $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procdff$16401 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1053$4451_Y, Q = \softshell.cpus[0].core.cpu.picorv32_core.instr_sw).
+Adding EN signal on $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procdff$16400 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1052$4449_Y, Q = \softshell.cpus[0].core.cpu.picorv32_core.instr_sh).
+Adding EN signal on $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procdff$16399 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1051$4447_Y, Q = \softshell.cpus[0].core.cpu.picorv32_core.instr_sb).
+Adding EN signal on $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procdff$16398 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1049$4445_Y, Q = \softshell.cpus[0].core.cpu.picorv32_core.instr_lhu).
+Adding EN signal on $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procdff$16397 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1048$4443_Y, Q = \softshell.cpus[0].core.cpu.picorv32_core.instr_lbu).
+Adding EN signal on $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procdff$16396 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1047$4441_Y, Q = \softshell.cpus[0].core.cpu.picorv32_core.instr_lw).
+Adding EN signal on $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procdff$16395 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1046$4439_Y, Q = \softshell.cpus[0].core.cpu.picorv32_core.instr_lh).
+Adding EN signal on $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procdff$16394 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1045$4437_Y, Q = \softshell.cpus[0].core.cpu.picorv32_core.instr_lb).
+Adding SRST signal on $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procdff$16393 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$7690_Y, Q = \softshell.cpus[0].core.cpu.picorv32_core.instr_bgeu, rval = 1'0).
+Adding EN signal on $auto$opt_dff.cc:702:run$20803 ($sdff) from module user_proj_example (D = $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1043$4435_Y, Q = \softshell.cpus[0].core.cpu.picorv32_core.instr_bgeu).
+Adding SRST signal on $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procdff$16392 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$7694_Y, Q = \softshell.cpus[0].core.cpu.picorv32_core.instr_bltu, rval = 1'0).
+Adding EN signal on $auto$opt_dff.cc:702:run$20805 ($sdff) from module user_proj_example (D = $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1042$4433_Y, Q = \softshell.cpus[0].core.cpu.picorv32_core.instr_bltu).
+Adding SRST signal on $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procdff$16391 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$7698_Y, Q = \softshell.cpus[0].core.cpu.picorv32_core.instr_bge, rval = 1'0).
+Adding EN signal on $auto$opt_dff.cc:702:run$20807 ($sdff) from module user_proj_example (D = $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1041$4431_Y, Q = \softshell.cpus[0].core.cpu.picorv32_core.instr_bge).
+Adding SRST signal on $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procdff$16390 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$7702_Y, Q = \softshell.cpus[0].core.cpu.picorv32_core.instr_blt, rval = 1'0).
+Adding EN signal on $auto$opt_dff.cc:702:run$20809 ($sdff) from module user_proj_example (D = $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1040$4429_Y, Q = \softshell.cpus[0].core.cpu.picorv32_core.instr_blt).
+Adding SRST signal on $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procdff$16389 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$7706_Y, Q = \softshell.cpus[0].core.cpu.picorv32_core.instr_bne, rval = 1'0).
+Adding EN signal on $auto$opt_dff.cc:702:run$20811 ($sdff) from module user_proj_example (D = $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1039$4427_Y, Q = \softshell.cpus[0].core.cpu.picorv32_core.instr_bne).
+Adding SRST signal on $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procdff$16388 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$7710_Y, Q = \softshell.cpus[0].core.cpu.picorv32_core.instr_beq, rval = 1'0).
+Adding EN signal on $auto$opt_dff.cc:702:run$20813 ($sdff) from module user_proj_example (D = $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1038$4425_Y, Q = \softshell.cpus[0].core.cpu.picorv32_core.instr_beq).
+Adding EN signal on $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procdff$16387 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$7723_Y, Q = \softshell.cpus[0].core.cpu.picorv32_core.instr_jalr).
+Adding EN signal on $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procdff$16386 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$7735_Y, Q = \softshell.cpus[0].core.cpu.picorv32_core.instr_jal).
+Adding EN signal on $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procdff$16385 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$eq$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:866$4353_Y, Q = \softshell.cpus[0].core.cpu.picorv32_core.instr_auipc).
+Adding EN signal on $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procdff$16384 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$7755_Y, Q = \softshell.cpus[0].core.cpu.picorv32_core.instr_lui).
+Adding EN signal on $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procdff$16383 ($dff) from module user_proj_example (D = \softshell.cpus[0].core.cpu.picorv32_core.mem_rdata_q, Q = \softshell.cpus[0].core.cpu.picorv32_core.pcpi_insn).
+Adding SRST signal on $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procdff$16377 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$6107_Y, Q = \softshell.cpus[0].core.cpu.picorv32_core.do_waitirq, rval = 1'0).
+Adding SRST signal on $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procdff$16375 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$logic_not$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1424$4678_Y, Q = \softshell.cpus[0].core.cpu.picorv32_core.pcpi_timeout, rval = 1'0).
+Adding SRST signal on $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procdff$16374 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$6346_Y, Q = \softshell.cpus[0].core.cpu.picorv32_core.pcpi_timeout_counter, rval = 4'1111).
+Adding EN signal on $auto$opt_dff.cc:702:run$20828 ($sdff) from module user_proj_example (D = $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$sub$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1421$4677_Y [3:0], Q = \softshell.cpus[0].core.cpu.picorv32_core.pcpi_timeout_counter).
+Adding SRST signal on $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procdff$16372 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$6361_Y, Q = \softshell.cpus[0].core.cpu.picorv32_core.latched_rd, rval = 5'00010).
+Adding EN signal on $auto$opt_dff.cc:702:run$20830 ($sdff) from module user_proj_example (D = $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$6361_Y, Q = \softshell.cpus[0].core.cpu.picorv32_core.latched_rd).
+Adding SRST signal on $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procdff$16371 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$6387_Y, Q = \softshell.cpus[0].core.cpu.picorv32_core.latched_is_lb, rval = 1'0).
+Adding EN signal on $auto$opt_dff.cc:702:run$20838 ($sdff) from module user_proj_example (D = $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$6387_Y, Q = \softshell.cpus[0].core.cpu.picorv32_core.latched_is_lb).
+Adding SRST signal on $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procdff$16370 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$6400_Y, Q = \softshell.cpus[0].core.cpu.picorv32_core.latched_is_lh, rval = 1'0).
+Adding EN signal on $auto$opt_dff.cc:702:run$20848 ($sdff) from module user_proj_example (D = $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$6400_Y, Q = \softshell.cpus[0].core.cpu.picorv32_core.latched_is_lh).
+Adding SRST signal on $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procdff$16369 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$6413_Y, Q = \softshell.cpus[0].core.cpu.picorv32_core.latched_is_lu, rval = 1'0).
+Adding EN signal on $auto$opt_dff.cc:702:run$20858 ($sdff) from module user_proj_example (D = $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$6413_Y, Q = \softshell.cpus[0].core.cpu.picorv32_core.latched_is_lu).
+Adding EN signal on $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procdff$16367 ($dff) from module user_proj_example (D = \softshell.cpus[0].core.cpu.picorv32_core.compressed_instr, Q = \softshell.cpus[0].core.cpu.picorv32_core.latched_compr).
+Adding SRST signal on $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procdff$16366 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$6458_Y, Q = \softshell.cpus[0].core.cpu.picorv32_core.latched_branch, rval = 1'0).
+Adding EN signal on $auto$opt_dff.cc:702:run$20875 ($sdff) from module user_proj_example (D = $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$6458_Y, Q = \softshell.cpus[0].core.cpu.picorv32_core.latched_branch).
+Adding SRST signal on $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procdff$16365 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$6494_Y, Q = \softshell.cpus[0].core.cpu.picorv32_core.latched_stalu, rval = 1'0).
+Adding EN signal on $auto$opt_dff.cc:702:run$20883 ($sdff) from module user_proj_example (D = $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$6494_Y, Q = \softshell.cpus[0].core.cpu.picorv32_core.latched_stalu).
+Adding SRST signal on $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procdff$16364 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$6501_Y, Q = \softshell.cpus[0].core.cpu.picorv32_core.latched_store, rval = 1'1).
+Adding EN signal on $auto$opt_dff.cc:702:run$20891 ($sdff) from module user_proj_example (D = $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$6501_Y, Q = \softshell.cpus[0].core.cpu.picorv32_core.latched_store).
+Adding SRST signal on $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procdff$16360 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$6559_Y, Q = \softshell.cpus[0].core.cpu.picorv32_core.irq_state, rval = 2'00).
+Adding EN signal on $auto$opt_dff.cc:702:run$20901 ($sdff) from module user_proj_example (D = $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$ternary$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1535$4723_Y, Q = \softshell.cpus[0].core.cpu.picorv32_core.irq_state).
+Adding SRST signal on $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procdff$16353 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$6121_Y, Q = \softshell.cpus[0].core.cpu.picorv32_core.decoder_pseudo_trigger, rval = 1'0).
+Adding SRST signal on $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procdff$16350 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$6771_Y, Q = \softshell.cpus[0].core.cpu.picorv32_core.mem_do_wdata, rval = 1'1).
+Adding EN signal on $auto$opt_dff.cc:702:run$20912 ($sdff) from module user_proj_example (D = 1'0, Q = \softshell.cpus[0].core.cpu.picorv32_core.mem_do_wdata).
+Adding SRST signal on $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procdff$16349 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$6775_Y, Q = \softshell.cpus[0].core.cpu.picorv32_core.mem_do_rdata, rval = 1'1).
+Adding EN signal on $auto$opt_dff.cc:702:run$20914 ($sdff) from module user_proj_example (D = 1'0, Q = \softshell.cpus[0].core.cpu.picorv32_core.mem_do_rdata).
+Adding SRST signal on $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procdff$16348 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$6849_Y, Q = \softshell.cpus[0].core.cpu.picorv32_core.mem_do_rinst, rval = 1'1).
+Adding EN signal on $auto$opt_dff.cc:702:run$20916 ($sdff) from module user_proj_example (D = $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$6849_Y, Q = \softshell.cpus[0].core.cpu.picorv32_core.mem_do_rinst).
+Adding SRST signal on $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procdff$16347 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$6874_Y, Q = \softshell.cpus[0].core.cpu.picorv32_core.mem_do_prefetch, rval = 1'0).
+Adding EN signal on $auto$opt_dff.cc:702:run$20928 ($sdff) from module user_proj_example (D = $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1568$4737_Y, Q = \softshell.cpus[0].core.cpu.picorv32_core.mem_do_prefetch).
+Adding SRST signal on $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procdff$16345 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$6920_Y, Q = \softshell.cpus[0].core.cpu.picorv32_core.timer, rval = 0).
+Adding SRST signal on $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procdff$16343 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$6938_Y, Q = \softshell.cpus[0].core.cpu.picorv32_core.irq_mask, rval = 32'11111111111111111111111111111111).
+Adding EN signal on $auto$opt_dff.cc:702:run$20941 ($sdff) from module user_proj_example (D = \softshell.cpus[0].core.cpu.picorv32_core.cpuregs_rs1, Q = \softshell.cpus[0].core.cpu.picorv32_core.irq_mask).
+Adding SRST signal on $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procdff$16342 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$6957_Y, Q = \softshell.cpus[0].core.cpu.picorv32_core.irq_active, rval = 1'0).
+Adding EN signal on $auto$opt_dff.cc:702:run$20945 ($sdff) from module user_proj_example (D = $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$6957_Y, Q = \softshell.cpus[0].core.cpu.picorv32_core.irq_active).
+Adding SRST signal on $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procdff$16341 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$6982_Y, Q = \softshell.cpus[0].core.cpu.picorv32_core.irq_delay, rval = 1'0).
+Adding EN signal on $auto$opt_dff.cc:702:run$20955 ($sdff) from module user_proj_example (D = \softshell.cpus[0].core.cpu.picorv32_core.irq_active, Q = \softshell.cpus[0].core.cpu.picorv32_core.irq_delay).
+Adding SRST signal on $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procdff$16339 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$6254_Y, Q = \softshell.cpus[0].core.cpu.picorv32_core.reg_out, rval = 128).
+Adding EN signal on $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procdff$16338 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$6995_Y, Q = \softshell.cpus[0].core.cpu.picorv32_core.reg_op2).
+Adding EN signal on $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procdff$16337 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$7017_Y, Q = \softshell.cpus[0].core.cpu.picorv32_core.reg_op1).
+Adding SRST signal on $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procdff$16336 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$7078_Y, Q = \softshell.cpus[0].core.cpu.picorv32_core.reg_next_pc, rval = 809566208).
+Adding EN signal on $auto$opt_dff.cc:702:run$20984 ($sdff) from module user_proj_example (D = $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$7076_Y, Q = \softshell.cpus[0].core.cpu.picorv32_core.reg_next_pc).
+Adding SRST signal on $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procdff$16335 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$7090_Y, Q = \softshell.cpus[0].core.cpu.picorv32_core.reg_pc, rval = 809566208).
+Adding EN signal on $auto$opt_dff.cc:702:run$20986 ($sdff) from module user_proj_example (D = $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$3\current_pc[31:0], Q = \softshell.cpus[0].core.cpu.picorv32_core.reg_pc).
+Adding SRST signal on $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procdff$16334 ($dff) from module user_proj_example (D = { $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$5988_Y $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$5953_Y }, Q = \softshell.cpus[0].core.cpu.picorv32_core.count_instr, rval = 64'0000000000000000000000000000000000000000000000000000000000000000).
+Adding EN signal on $auto$opt_dff.cc:702:run$20988 ($sdff) from module user_proj_example (D = { 32'00000000000000000000000000000000 $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1559$4733_Y [31:0] }, Q = \softshell.cpus[0].core.cpu.picorv32_core.count_instr).
+Setting constant 0-bit at position 32 on $auto$opt_dff.cc:764:run$20995 ($sdffe) from module user_proj_example.
+Setting constant 0-bit at position 33 on $auto$opt_dff.cc:764:run$20995 ($sdffe) from module user_proj_example.
+Setting constant 0-bit at position 34 on $auto$opt_dff.cc:764:run$20995 ($sdffe) from module user_proj_example.
+Setting constant 0-bit at position 35 on $auto$opt_dff.cc:764:run$20995 ($sdffe) from module user_proj_example.
+Setting constant 0-bit at position 36 on $auto$opt_dff.cc:764:run$20995 ($sdffe) from module user_proj_example.
+Setting constant 0-bit at position 37 on $auto$opt_dff.cc:764:run$20995 ($sdffe) from module user_proj_example.
+Setting constant 0-bit at position 38 on $auto$opt_dff.cc:764:run$20995 ($sdffe) from module user_proj_example.
+Setting constant 0-bit at position 39 on $auto$opt_dff.cc:764:run$20995 ($sdffe) from module user_proj_example.
+Setting constant 0-bit at position 40 on $auto$opt_dff.cc:764:run$20995 ($sdffe) from module user_proj_example.
+Setting constant 0-bit at position 41 on $auto$opt_dff.cc:764:run$20995 ($sdffe) from module user_proj_example.
+Setting constant 0-bit at position 42 on $auto$opt_dff.cc:764:run$20995 ($sdffe) from module user_proj_example.
+Setting constant 0-bit at position 43 on $auto$opt_dff.cc:764:run$20995 ($sdffe) from module user_proj_example.
+Setting constant 0-bit at position 44 on $auto$opt_dff.cc:764:run$20995 ($sdffe) from module user_proj_example.
+Setting constant 0-bit at position 45 on $auto$opt_dff.cc:764:run$20995 ($sdffe) from module user_proj_example.
+Setting constant 0-bit at position 46 on $auto$opt_dff.cc:764:run$20995 ($sdffe) from module user_proj_example.
+Setting constant 0-bit at position 47 on $auto$opt_dff.cc:764:run$20995 ($sdffe) from module user_proj_example.
+Setting constant 0-bit at position 48 on $auto$opt_dff.cc:764:run$20995 ($sdffe) from module user_proj_example.
+Setting constant 0-bit at position 49 on $auto$opt_dff.cc:764:run$20995 ($sdffe) from module user_proj_example.
+Setting constant 0-bit at position 50 on $auto$opt_dff.cc:764:run$20995 ($sdffe) from module user_proj_example.
+Setting constant 0-bit at position 51 on $auto$opt_dff.cc:764:run$20995 ($sdffe) from module user_proj_example.
+Setting constant 0-bit at position 52 on $auto$opt_dff.cc:764:run$20995 ($sdffe) from module user_proj_example.
+Setting constant 0-bit at position 53 on $auto$opt_dff.cc:764:run$20995 ($sdffe) from module user_proj_example.
+Setting constant 0-bit at position 54 on $auto$opt_dff.cc:764:run$20995 ($sdffe) from module user_proj_example.
+Setting constant 0-bit at position 55 on $auto$opt_dff.cc:764:run$20995 ($sdffe) from module user_proj_example.
+Setting constant 0-bit at position 56 on $auto$opt_dff.cc:764:run$20995 ($sdffe) from module user_proj_example.
+Setting constant 0-bit at position 57 on $auto$opt_dff.cc:764:run$20995 ($sdffe) from module user_proj_example.
+Setting constant 0-bit at position 58 on $auto$opt_dff.cc:764:run$20995 ($sdffe) from module user_proj_example.
+Setting constant 0-bit at position 59 on $auto$opt_dff.cc:764:run$20995 ($sdffe) from module user_proj_example.
+Setting constant 0-bit at position 60 on $auto$opt_dff.cc:764:run$20995 ($sdffe) from module user_proj_example.
+Setting constant 0-bit at position 61 on $auto$opt_dff.cc:764:run$20995 ($sdffe) from module user_proj_example.
+Setting constant 0-bit at position 62 on $auto$opt_dff.cc:764:run$20995 ($sdffe) from module user_proj_example.
+Setting constant 0-bit at position 63 on $auto$opt_dff.cc:764:run$20995 ($sdffe) from module user_proj_example.
+Adding SRST signal on $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procdff$16333 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1428$4679_Y [31:0], Q = \softshell.cpus[0].core.cpu.picorv32_core.count_cycle [31:0], rval = 0).
+Adding SRST signal on $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procdff$16329 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$6340_Y, Q = \softshell.cpus[0].core.cpu.picorv32_core.trap, rval = 1'0).
+Adding SRST signal on $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procdff$16328 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$7151_Y, Q = \softshell.cpus[0].core.cpu.picorv32_core.pcpi_valid, rval = 1'0).
+Adding EN signal on $auto$opt_dff.cc:702:run$20998 ($sdff) from module user_proj_example (D = $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$7147_Y, Q = \softshell.cpus[0].core.cpu.picorv32_core.pcpi_valid).
+Adding EN signal on $flatten\softshell.\cpus[0].core.\cpu.$procdff$16290 ($dff) from module user_proj_example (D = \softshell.cpus[0].core.cpu.wbm_dat_i, Q = \softshell.cpus[0].core.cpu.mem_rdata).
+Adding EN signal on $flatten\softshell.\cpus[0].core.\cpu.$procdff$16289 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[0].core.\cpu.$procmux$5106_Y, Q = \softshell.cpus[0].core.cpu.mem_ready).
+Adding SRST signal on $flatten\softshell.\cpus[0].core.\cpu.$procdff$16287 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[0].core.\cpu.$procmux$5137_Y, Q = \softshell.cpus[0].core.cpu.wbm_sel_o, rval = 4'0000).
+Adding EN signal on $auto$opt_dff.cc:702:run$21018 ($sdff) from module user_proj_example (D = \softshell.cpus[0].core.cpu.picorv32_core.mem_wstrb, Q = \softshell.cpus[0].core.cpu.wbm_sel_o).
+Adding SRST signal on $flatten\softshell.\cpus[0].core.\cpu.$procdff$16286 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[0].core.\cpu.$procmux$5146_Y, Q = \softshell.cpus[0].core.cpu.wbm_we_o, rval = 1'0).
+Adding EN signal on $auto$opt_dff.cc:702:run$21022 ($sdff) from module user_proj_example (D = $flatten\softshell.\cpus[0].core.\cpu.$procmux$5146_Y, Q = \softshell.cpus[0].core.cpu.wbm_we_o).
+Adding SRST signal on $flatten\softshell.\cpus[0].core.\cpu.$procdff$16285 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[0].core.\cpu.$procmux$5159_Y, Q = \softshell.cpus[0].core.cpu.wbm_cyc_o, rval = 1'0).
+Adding EN signal on $auto$opt_dff.cc:702:run$21030 ($sdff) from module user_proj_example (D = $flatten\softshell.\cpus[0].core.\cpu.$procmux$5159_Y, Q = \softshell.cpus[0].core.cpu.wbm_cyc_o).
+Adding SRST signal on $flatten\softshell.\cpus[0].core.\cpu.$procdff$16284 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[0].core.\cpu.$procmux$5172_Y, Q = \softshell.cpus[0].core.cpu.wbm_stb_o, rval = 1'0).
+Adding EN signal on $auto$opt_dff.cc:702:run$21038 ($sdff) from module user_proj_example (D = $flatten\softshell.\cpus[0].core.\cpu.$procmux$5172_Y, Q = \softshell.cpus[0].core.cpu.wbm_stb_o).
+Adding SRST signal on $flatten\softshell.\cpus[0].core.\cpu.$procdff$16283 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[0].core.\cpu.$procmux$5187_Y, Q = \softshell.cpus[0].core.cpu.wbm_adr_o, rval = 0).
+Adding EN signal on $auto$opt_dff.cc:702:run$21046 ($sdff) from module user_proj_example (D = \softshell.cpus[0].core.cpu.picorv32_core.mem_addr, Q = \softshell.cpus[0].core.cpu.wbm_adr_o).
+Adding SRST signal on $flatten\softshell.\cpus[0].core.\cpu.$procdff$16282 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[0].core.\cpu.$procmux$5198_Y, Q = \softshell.cpus[0].core.cpu.wbm_dat_o, rval = 0).
+Adding EN signal on $auto$opt_dff.cc:702:run$21050 ($sdff) from module user_proj_example (D = \softshell.cpus[0].core.cpu.picorv32_core.mem_wdata, Q = \softshell.cpus[0].core.cpu.wbm_dat_o).
+Adding SRST signal on $flatten\softshell.\arbiter.\arb_inst.$procdff$16281 ($dff) from module user_proj_example (D = \softshell.arbiter.arb_inst.mask_next, Q = \softshell.arbiter.arb_inst.mask_reg, rval = 4'0000).
+Adding EN signal on $auto$opt_dff.cc:702:run$21054 ($sdff) from module user_proj_example (D = $flatten\softshell.\arbiter.\arb_inst.$4\mask_next[3:0], Q = \softshell.arbiter.arb_inst.mask_reg).
+Adding SRST signal on $flatten\softshell.\arbiter.\arb_inst.$procdff$16279 ($dff) from module user_proj_example (D = \softshell.arbiter.arb_inst.grant_valid_next, Q = \softshell.arbiter.arb_inst.grant_valid_reg, rval = 1'0).
+Adding EN signal on $auto$opt_dff.cc:702:run$21060 ($sdff) from module user_proj_example (D = $flatten\softshell.\arbiter.\arb_inst.$2\grant_valid_next[0:0], Q = \softshell.arbiter.arb_inst.grant_valid_reg).
+Adding SRST signal on $flatten\softshell.\arbiter.\arb_inst.$procdff$16278 ($dff) from module user_proj_example (D = \softshell.arbiter.arb_inst.grant_next, Q = \softshell.arbiter.arb_inst.grant_reg, rval = 4'0000).
+Adding EN signal on $auto$opt_dff.cc:702:run$21062 ($sdff) from module user_proj_example (D = $flatten\softshell.\arbiter.\arb_inst.$2\grant_next[3:0], Q = \softshell.arbiter.arb_inst.grant_reg).
+
+23.9.7. Executing OPT_CLEAN pass (remove unused cells and wires).
+Finding unused cells or wires in module \user_proj_example..
+Removed 1049 unused cells and 1225 unused wires.
+<suppressed ~1057 debug messages>
+
+23.9.8. Executing OPT_EXPR pass (perform const folding).
+Optimizing module user_proj_example.
+<suppressed ~75 debug messages>
+
+23.9.9. Rerunning OPT passes. (Maybe there is more to do..)
+
+23.9.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
+Running muxtree optimizer on module \user_proj_example..
+ Creating internal representation of mux trees.
+ Evaluating internal representation of mux trees.
+ Analyzing evaluation results.
+Removed 0 multiplexer ports.
+<suppressed ~476 debug messages>
+
+23.9.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
+ Optimizing cells in module \user_proj_example.
+ New input vector for $reduce_or cell $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$reduce_or$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:687$2970: { \softshell.cpus[2].core.cpu.picorv32_core.instr_rdinstr \softshell.cpus[2].core.cpu.picorv32_core.instr_rdcycle }
+ New input vector for $reduce_or cell $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$reduce_or$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:687$3653: { \softshell.cpus[1].core.cpu.picorv32_core.instr_rdinstr \softshell.cpus[1].core.cpu.picorv32_core.instr_rdcycle }
+ New input vector for $reduce_or cell $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$reduce_or$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:687$4336: { \softshell.cpus[0].core.cpu.picorv32_core.instr_rdinstr \softshell.cpus[0].core.cpu.picorv32_core.instr_rdcycle }
+ New input vector for $reduce_or cell $auto$opt_reduce.cc:128:opt_mux$17084: { \softshell.cpus[2].core.cpu.picorv32_core.instr_timer \softshell.cpus[2].core.cpu.picorv32_core.instr_maskirq \softshell.cpus[2].core.cpu.picorv32_core.instr_retirq \softshell.cpus[2].core.cpu.picorv32_core.instr_rdinstr \softshell.cpus[2].core.cpu.picorv32_core.instr_rdcycle }
+ New input vector for $reduce_or cell $auto$opt_reduce.cc:128:opt_mux$17082: { $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1691$3392_Y \softshell.cpus[2].core.cpu.picorv32_core.instr_timer \softshell.cpus[2].core.cpu.picorv32_core.instr_maskirq \softshell.cpus[2].core.cpu.picorv32_core.instr_retirq \softshell.cpus[2].core.cpu.picorv32_core.instr_rdinstr \softshell.cpus[2].core.cpu.picorv32_core.instr_rdcycle }
+ New input vector for $reduce_or cell $auto$opt_reduce.cc:128:opt_mux$17076: { \softshell.cpus[0].core.cpu.picorv32_core.instr_timer \softshell.cpus[0].core.cpu.picorv32_core.instr_maskirq \softshell.cpus[0].core.cpu.picorv32_core.instr_retirq \softshell.cpus[0].core.cpu.picorv32_core.instr_rdinstr \softshell.cpus[0].core.cpu.picorv32_core.instr_rdcycle }
+ New input vector for $reduce_or cell $auto$opt_reduce.cc:128:opt_mux$17066: { $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1691$4758_Y \softshell.cpus[0].core.cpu.picorv32_core.instr_timer \softshell.cpus[0].core.cpu.picorv32_core.instr_maskirq \softshell.cpus[0].core.cpu.picorv32_core.instr_retirq \softshell.cpus[0].core.cpu.picorv32_core.instr_rdinstr \softshell.cpus[0].core.cpu.picorv32_core.instr_rdcycle }
+ New input vector for $reduce_or cell $auto$opt_reduce.cc:128:opt_mux$16942: { \softshell.cpus[1].core.cpu.picorv32_core.instr_timer \softshell.cpus[1].core.cpu.picorv32_core.instr_maskirq \softshell.cpus[1].core.cpu.picorv32_core.instr_retirq \softshell.cpus[1].core.cpu.picorv32_core.instr_rdinstr \softshell.cpus[1].core.cpu.picorv32_core.instr_rdcycle }
+ New input vector for $reduce_or cell $auto$opt_reduce.cc:128:opt_mux$16940: { $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1691$4075_Y \softshell.cpus[1].core.cpu.picorv32_core.instr_timer \softshell.cpus[1].core.cpu.picorv32_core.instr_maskirq \softshell.cpus[1].core.cpu.picorv32_core.instr_retirq \softshell.cpus[1].core.cpu.picorv32_core.instr_rdinstr \softshell.cpus[1].core.cpu.picorv32_core.instr_rdcycle }
+ Optimizing cells in module \user_proj_example.
+Performed a total of 9 changes.
+
+23.9.12. Executing OPT_MERGE pass (detect identical cells).
+Finding identical cells in module `\user_proj_example'.
+<suppressed ~645 debug messages>
+Removed a total of 215 cells.
+
+23.9.13. Executing OPT_DFF pass (perform DFF optimizations).
+
+23.9.14. Executing OPT_CLEAN pass (remove unused cells and wires).
+Finding unused cells or wires in module \user_proj_example..
+Removed 0 unused cells and 203 unused wires.
+<suppressed ~1 debug messages>
+
+23.9.15. Executing OPT_EXPR pass (perform const folding).
+Optimizing module user_proj_example.
+<suppressed ~6 debug messages>
+
+23.9.16. Rerunning OPT passes. (Maybe there is more to do..)
+
+23.9.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
+Running muxtree optimizer on module \user_proj_example..
+ Creating internal representation of mux trees.
+ Evaluating internal representation of mux trees.
+ Analyzing evaluation results.
+Removed 0 multiplexer ports.
+<suppressed ~473 debug messages>
+
+23.9.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
+ Optimizing cells in module \user_proj_example.
+Performed a total of 0 changes.
+
+23.9.19. Executing OPT_MERGE pass (detect identical cells).
+Finding identical cells in module `\user_proj_example'.
+Removed a total of 0 cells.
+
+23.9.20. Executing OPT_DFF pass (perform DFF optimizations).
+
+23.9.21. Executing OPT_CLEAN pass (remove unused cells and wires).
+Finding unused cells or wires in module \user_proj_example..
+
+23.9.22. Executing OPT_EXPR pass (perform const folding).
+Optimizing module user_proj_example.
+
+23.9.23. Finished OPT passes. (There is nothing left to do.)
+
+23.10. Executing WREDUCE pass (reducing word size of cells).
+Removed top 4 bits (of 5) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$17322 ($eq).
+Removed top 6 bits (of 9) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$18898 ($eq).
+Removed top 5 bits (of 10) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$18902 ($eq).
+Removed top 1 bits (of 6) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$18808 ($eq).
+Removed top 5 bits (of 7) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$18812 ($eq).
+Removed top 4 bits (of 9) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$18816 ($eq).
+Removed top 3 bits (of 10) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$18820 ($eq).
+Removed top 2 bits (of 9) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$18824 ($eq).
+Removed top 1 bits (of 7) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$18828 ($eq).
+Removed top 3 bits (of 5) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$18833 ($eq).
+Removed top 4 bits (of 7) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$18837 ($eq).
+Removed top 3 bits (of 8) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$18841 ($eq).
+Removed top 2 bits (of 7) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$18845 ($eq).
+Removed top 1 bits (of 5) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$18849 ($eq).
+Removed top 6 bits (of 10) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$18857 ($eq).
+Removed top 5 bits (of 11) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$18861 ($eq).
+Removed top 4 bits (of 10) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$18865 ($eq).
+Removed top 3 bits (of 8) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$18869 ($eq).
+Removed top 3 bits (of 5) from port B of cell user_proj_example.$auto$opt_dff.cc:218:make_patterns_logic$19535 ($ne).
+Removed top 3 bits (of 9) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$18800 ($eq).
+Removed top 2 bits (of 8) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$18804 ($eq).
+Removed top 4 bits (of 9) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$18906 ($eq).
+Removed top 3 bits (of 7) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$18910 ($eq).
+Removed top 6 bits (of 7) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$18894 ($eq).
+Removed top 3 bits (of 4) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$18955 ($eq).
+Removed top 4 bits (of 6) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$18959 ($eq).
+Removed top 3 bits (of 7) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$18963 ($eq).
+Removed top 2 bits (of 6) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$18967 ($eq).
+Removed top 1 bits (of 4) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$18971 ($eq).
+Removed top 4 bits (of 6) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$18979 ($eq).
+Removed top 3 bits (of 7) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$18983 ($eq).
+Removed top 2 bits (of 6) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$18987 ($eq).
+Removed top 1 bits (of 4) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$18991 ($eq).
+Removed top 4 bits (of 5) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$18995 ($eq).
+Removed top 4 bits (of 7) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$18999 ($eq).
+Removed top 3 bits (of 8) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$19003 ($eq).
+Removed top 2 bits (of 7) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$19007 ($eq).
+Removed top 1 bits (of 5) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$19011 ($eq).
+Removed top 1 bits (of 5) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$19020 ($eq).
+Removed top 1 bits (of 5) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$19026 ($eq).
+Removed top 1 bits (of 2) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$19036 ($eq).
+Removed top 1 bits (of 5) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$19051 ($eq).
+Removed top 1 bits (of 5) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$19057 ($eq).
+Removed top 1 bits (of 5) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$19080 ($eq).
+Removed top 1 bits (of 4) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$19082 ($eq).
+Removed top 1 bits (of 5) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$19086 ($eq).
+Removed top 1 bits (of 4) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$19088 ($eq).
+Removed top 1 bits (of 3) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$19096 ($eq).
+Removed top 1 bits (of 3) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$19100 ($eq).
+Removed top 4 bits (of 8) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$17429 ($eq).
+Removed top 3 bits (of 9) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$17433 ($eq).
+Removed top 2 bits (of 8) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$17437 ($eq).
+Removed top 1 bits (of 6) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$17441 ($eq).
+Removed top 4 bits (of 6) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$17449 ($eq).
+Removed top 1 bits (of 2) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$19120 ($eq).
+Removed top 1 bits (of 2) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$19124 ($eq).
+Removed top 3 bits (of 7) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$17453 ($eq).
+Removed top 2 bits (of 4) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$19148 ($eq).
+Removed top 2 bits (of 4) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$19164 ($eq).
+Removed top 1 bits (of 4) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$19199 ($eq).
+Removed top 2 bits (of 4) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$19217 ($eq).
+Removed top 3 bits (of 4) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$19221 ($eq).
+Removed top 1 bits (of 4) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$19230 ($eq).
+Removed top 2 bits (of 3) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$19234 ($eq).
+Removed top 3 bits (of 8) from port B of cell user_proj_example.$auto$opt_dff.cc:218:make_patterns_logic$19524 ($ne).
+Removed top 4 bits (of 8) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$18796 ($eq).
+Removed top 4 bits (of 6) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$18792 ($eq).
+Removed top 2 bits (of 6) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$18374 ($eq).
+Removed top 4 bits (of 5) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$18382 ($eq).
+Removed top 3 bits (of 7) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$18350 ($eq).
+Removed top 1 bits (of 4) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$18378 ($eq).
+Removed top 4 bits (of 6) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$18366 ($eq).
+Removed top 2 bits (of 6) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$18354 ($eq).
+Removed top 6 bits (of 7) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$18281 ($eq).
+Removed top 6 bits (of 9) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$18285 ($eq).
+Removed top 5 bits (of 10) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$18289 ($eq).
+Removed top 4 bits (of 9) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$18293 ($eq).
+Removed top 3 bits (of 7) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$18297 ($eq).
+Removed top 4 bits (of 10) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$18252 ($eq).
+Removed top 3 bits (of 8) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$18256 ($eq).
+Removed top 3 bits (of 4) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$18342 ($eq).
+Removed top 3 bits (of 7) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$18370 ($eq).
+Removed top 1 bits (of 4) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$18358 ($eq).
+Removed top 4 bits (of 6) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$18346 ($eq).
+Removed top 3 bits (of 8) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$18619 ($eq).
+Removed top 2 bits (of 7) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$18623 ($eq).
+Removed top 1 bits (of 5) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$18627 ($eq).
+Removed top 5 bits (of 7) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$18631 ($eq).
+Removed top 4 bits (of 9) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$18635 ($eq).
+Removed top 3 bits (of 10) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$18639 ($eq).
+Removed top 2 bits (of 9) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$18643 ($eq).
+Removed top 1 bits (of 7) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$18647 ($eq).
+Removed top 4 bits (of 8) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$18655 ($eq).
+Removed top 3 bits (of 9) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$18659 ($eq).
+Removed top 2 bits (of 8) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$18663 ($eq).
+Removed top 1 bits (of 6) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$18667 ($eq).
+Removed top 4 bits (of 6) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$18675 ($eq).
+Removed top 3 bits (of 7) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$18679 ($eq).
+Removed top 2 bits (of 6) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$18683 ($eq).
+Removed top 1 bits (of 4) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$18687 ($eq).
+Removed top 3 bits (of 5) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$18691 ($eq).
+Removed top 4 bits (of 7) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$18695 ($eq).
+Removed top 3 bits (of 8) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$18699 ($eq).
+Removed top 2 bits (of 7) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$18703 ($eq).
+Removed top 1 bits (of 5) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$18707 ($eq).
+Removed top 3 bits (of 4) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$18711 ($eq).
+Removed top 4 bits (of 6) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$18715 ($eq).
+Removed top 3 bits (of 7) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$18719 ($eq).
+Removed top 2 bits (of 6) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$18723 ($eq).
+Removed top 1 bits (of 4) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$18727 ($eq).
+Removed top 3 bits (of 5) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$18731 ($eq).
+Removed top 4 bits (of 7) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$18737 ($eq).
+Removed top 3 bits (of 8) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$18743 ($eq).
+Removed top 2 bits (of 7) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$18749 ($eq).
+Removed top 1 bits (of 5) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$18755 ($eq).
+Removed top 4 bits (of 7) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$18386 ($eq).
+Removed top 3 bits (of 8) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$18390 ($eq).
+Removed top 2 bits (of 7) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$18394 ($eq).
+Removed top 1 bits (of 5) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$18398 ($eq).
+Removed top 2 bits (of 7) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$17397 ($eq).
+Removed top 1 bits (of 5) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$18407 ($eq).
+Removed top 1 bits (of 5) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$17401 ($eq).
+Removed top 5 bits (of 7) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$17405 ($eq).
+Removed top 1 bits (of 5) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$18413 ($eq).
+Removed top 4 bits (of 9) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$17409 ($eq).
+Removed top 3 bits (of 10) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$17413 ($eq).
+Removed top 1 bits (of 2) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$18423 ($eq).
+Removed top 2 bits (of 9) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$17417 ($eq).
+Removed top 1 bits (of 7) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$17421 ($eq).
+Removed top 1 bits (of 5) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$18438 ($eq).
+Removed top 1 bits (of 5) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$18444 ($eq).
+Removed top 1 bits (of 5) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$18467 ($eq).
+Removed top 1 bits (of 4) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$18469 ($eq).
+Removed top 1 bits (of 5) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$18473 ($eq).
+Removed top 1 bits (of 4) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$18475 ($eq).
+Removed top 1 bits (of 3) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$18483 ($eq).
+Removed top 1 bits (of 3) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$18487 ($eq).
+Removed top 1 bits (of 2) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$18507 ($eq).
+Removed top 1 bits (of 2) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$18511 ($eq).
+Removed top 4 bits (of 7) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$18524 ($eq).
+Removed top 4 bits (of 9) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$18528 ($eq).
+Removed top 3 bits (of 10) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$18532 ($eq).
+Removed top 2 bits (of 9) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$18536 ($eq).
+Removed top 1 bits (of 7) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$18540 ($eq).
+Removed top 4 bits (of 5) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$18548 ($eq).
+Removed top 3 bits (of 5) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$18552 ($eq).
+Removed top 3 bits (of 6) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$18554 ($eq).
+Removed top 1 bits (of 4) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$18558 ($eq).
+Removed top 2 bits (of 5) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$18560 ($eq).
+Removed top 1 bits (of 3) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$18566 ($eq).
+Removed top 3 bits (of 7) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$18571 ($eq).
+Removed top 4 bits (of 9) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$18575 ($eq).
+Removed top 3 bits (of 10) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$18579 ($eq).
+Removed top 2 bits (of 9) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$18583 ($eq).
+Removed top 1 bits (of 7) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$18587 ($eq).
+Removed top 3 bits (of 5) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$18591 ($eq).
+Removed top 4 bits (of 7) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$18595 ($eq).
+Removed top 3 bits (of 8) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$18599 ($eq).
+Removed top 2 bits (of 7) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$18603 ($eq).
+Removed top 1 bits (of 5) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$18607 ($eq).
+Removed top 3 bits (of 5) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$18611 ($eq).
+Removed top 4 bits (of 7) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$18615 ($eq).
+Removed top 5 bits (of 11) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$18248 ($eq).
+Removed top 6 bits (of 10) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$18244 ($eq).
+Removed top 3 bits (of 8) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$17393 ($eq).
+Removed top 3 bits (of 5) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$17326 ($eq).
+Removed top 2 bits (of 7) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$18232 ($eq).
+Removed top 3 bits (of 8) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$18228 ($eq).
+Removed top 3 bits (of 7) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$17345 ($eq).
+Removed top 2 bits (of 7) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$17781 ($eq).
+Removed top 1 bits (of 5) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$17831 ($eq).
+Removed top 1 bits (of 5) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$17785 ($eq).
+Removed top 3 bits (of 4) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$17729 ($eq).
+Removed top 4 bits (of 6) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$17733 ($eq).
+Removed top 3 bits (of 7) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$17737 ($eq).
+Removed top 2 bits (of 6) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$17741 ($eq).
+Removed top 1 bits (of 4) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$17745 ($eq).
+Removed top 4 bits (of 6) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$17753 ($eq).
+Removed top 3 bits (of 7) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$17757 ($eq).
+Removed top 2 bits (of 6) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$17761 ($eq).
+Removed top 1 bits (of 4) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$17765 ($eq).
+Removed top 4 bits (of 5) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$17769 ($eq).
+Removed top 3 bits (of 8) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$17777 ($eq).
+Removed top 4 bits (of 7) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$17773 ($eq).
+Removed top 4 bits (of 7) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$18224 ($eq).
+Removed top 1 bits (of 5) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$17794 ($eq).
+Removed top 1 bits (of 2) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$17810 ($eq).
+Removed top 1 bits (of 5) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$17825 ($eq).
+Removed top 1 bits (of 5) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$17800 ($eq).
+Removed top 1 bits (of 5) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$17854 ($eq).
+Removed top 1 bits (of 4) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$17856 ($eq).
+Removed top 1 bits (of 5) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$17860 ($eq).
+Removed top 1 bits (of 4) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$17862 ($eq).
+Removed top 1 bits (of 3) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$17870 ($eq).
+Removed top 1 bits (of 3) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$17874 ($eq).
+Removed top 1 bits (of 2) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$17894 ($eq).
+Removed top 1 bits (of 2) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$17898 ($eq).
+Removed top 4 bits (of 7) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$17911 ($eq).
+Removed top 4 bits (of 9) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$17915 ($eq).
+Removed top 3 bits (of 10) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$17919 ($eq).
+Removed top 2 bits (of 9) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$17923 ($eq).
+Removed top 1 bits (of 7) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$17927 ($eq).
+Removed top 4 bits (of 5) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$17935 ($eq).
+Removed top 3 bits (of 5) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$17939 ($eq).
+Removed top 3 bits (of 6) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$17941 ($eq).
+Removed top 1 bits (of 4) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$17945 ($eq).
+Removed top 2 bits (of 5) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$17947 ($eq).
+Removed top 1 bits (of 3) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$17953 ($eq).
+Removed top 3 bits (of 7) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$17958 ($eq).
+Removed top 4 bits (of 9) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$17962 ($eq).
+Removed top 3 bits (of 10) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$17966 ($eq).
+Removed top 2 bits (of 9) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$17970 ($eq).
+Removed top 1 bits (of 7) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$17974 ($eq).
+Removed top 3 bits (of 5) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$17978 ($eq).
+Removed top 4 bits (of 7) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$17982 ($eq).
+Removed top 3 bits (of 8) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$17986 ($eq).
+Removed top 2 bits (of 7) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$17990 ($eq).
+Removed top 1 bits (of 5) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$17994 ($eq).
+Removed top 3 bits (of 5) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$17998 ($eq).
+Removed top 4 bits (of 7) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$18002 ($eq).
+Removed top 3 bits (of 8) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$18006 ($eq).
+Removed top 1 bits (of 7) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$17361 ($eq).
+Removed top 2 bits (of 7) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$18010 ($eq).
+Removed top 3 bits (of 5) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$17365 ($eq).
+Removed top 4 bits (of 7) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$17369 ($eq).
+Removed top 1 bits (of 5) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$18014 ($eq).
+Removed top 5 bits (of 7) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$18018 ($eq).
+Removed top 3 bits (of 8) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$17373 ($eq).
+Removed top 2 bits (of 7) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$17377 ($eq).
+Removed top 1 bits (of 5) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$17381 ($eq).
+Removed top 4 bits (of 9) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$18022 ($eq).
+Removed top 3 bits (of 10) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$18026 ($eq).
+Removed top 3 bits (of 5) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$17385 ($eq).
+Removed top 4 bits (of 7) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$17389 ($eq).
+Removed top 2 bits (of 9) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$18030 ($eq).
+Removed top 1 bits (of 7) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$18034 ($eq).
+Removed top 4 bits (of 8) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$18042 ($eq).
+Removed top 3 bits (of 9) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$18046 ($eq).
+Removed top 2 bits (of 8) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$18050 ($eq).
+Removed top 1 bits (of 6) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$18054 ($eq).
+Removed top 4 bits (of 6) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$18062 ($eq).
+Removed top 3 bits (of 7) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$18066 ($eq).
+Removed top 2 bits (of 6) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$18070 ($eq).
+Removed top 1 bits (of 4) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$18074 ($eq).
+Removed top 3 bits (of 5) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$18078 ($eq).
+Removed top 4 bits (of 7) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$18082 ($eq).
+Removed top 3 bits (of 8) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$18086 ($eq).
+Removed top 2 bits (of 7) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$18090 ($eq).
+Removed top 1 bits (of 5) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$18094 ($eq).
+Removed top 3 bits (of 4) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$18098 ($eq).
+Removed top 4 bits (of 6) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$18102 ($eq).
+Removed top 3 bits (of 7) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$18106 ($eq).
+Removed top 2 bits (of 6) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$18110 ($eq).
+Removed top 1 bits (of 4) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$18114 ($eq).
+Removed top 3 bits (of 5) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$18118 ($eq).
+Removed top 4 bits (of 7) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$18124 ($eq).
+Removed top 3 bits (of 8) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$18130 ($eq).
+Removed top 2 bits (of 7) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$18136 ($eq).
+Removed top 1 bits (of 5) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$18142 ($eq).
+Removed top 4 bits (of 6) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$18179 ($eq).
+Removed top 4 bits (of 8) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$18183 ($eq).
+Removed top 3 bits (of 9) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$18187 ($eq).
+Removed top 2 bits (of 8) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$18191 ($eq).
+Removed top 1 bits (of 6) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$18195 ($eq).
+Removed top 5 bits (of 7) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$18199 ($eq).
+Removed top 4 bits (of 9) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$18203 ($eq).
+Removed top 3 bits (of 10) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$18207 ($eq).
+Removed top 2 bits (of 9) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$18211 ($eq).
+Removed top 1 bits (of 7) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$18215 ($eq).
+Removed top 3 bits (of 5) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$18220 ($eq).
+Removed top 1 bits (of 5) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$18236 ($eq).
+Removed top 3 bits (of 7) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$17684 ($eq).
+Removed top 4 bits (of 9) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$17680 ($eq).
+Removed top 5 bits (of 10) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$17676 ($eq).
+Removed top 4 bits (of 7) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$17298 ($eq).
+Removed top 4 bits (of 9) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$17302 ($eq).
+Removed top 3 bits (of 10) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$17306 ($eq).
+Removed top 3 bits (of 8) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$17473 ($eq).
+Removed top 4 bits (of 7) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$17469 ($eq).
+Removed top 3 bits (of 5) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$17465 ($eq).
+Removed top 1 bits (of 4) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$17461 ($eq).
+Removed top 2 bits (of 6) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$17457 ($eq).
+Removed top 3 bits (of 9) from port B of cell user_proj_example.$auto$opt_dff.cc:218:make_patterns_logic$19550 ($ne).
+Removed top 2 bits (of 4) from port B of cell user_proj_example.$auto$opt_dff.cc:218:make_patterns_logic$19777 ($ne).
+Removed top 1 bits (of 2) from port B of cell user_proj_example.$auto$opt_dff.cc:218:make_patterns_logic$19785 ($ne).
+Removed top 1 bits (of 2) from port B of cell user_proj_example.$auto$opt_dff.cc:218:make_patterns_logic$19799 ($ne).
+Removed top 2 bits (of 32) from port B of cell user_proj_example.$flatten\softshell.\cpus[2].core.\interconnect.$xor$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/verilog-wishbone/rtl/wb_mux_3.v:117$404 ($xor).
+Removed top 1 bits (of 3) from port B of cell user_proj_example.$flatten\softshell.\cpus[2].core.\flexio.\out_fifo.$xor$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:131$2006 ($xor).
+Removed top 2 bits (of 4) from port B of cell user_proj_example.$auto$opt_dff.cc:218:make_patterns_logic$20236 ($ne).
+Removed top 31 bits (of 32) from port B of cell user_proj_example.$flatten\softshell.\cpus[2].core.\flexio.\out_fifo.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:144$2013 ($add).
+Removed top 29 bits (of 32) from port Y of cell user_proj_example.$flatten\softshell.\cpus[2].core.\flexio.\out_fifo.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:144$2013 ($add).
+Removed top 1 bits (of 3) from port B of cell user_proj_example.$flatten\softshell.\cpus[2].core.\flexio.\out_fifo.$xor$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:153$2019 ($xor).
+Removed cell user_proj_example.$flatten\softshell.\cpus[2].core.\flexio.\out_fifo.$procmux$5507 ($mux).
+Removed cell user_proj_example.$flatten\softshell.\cpus[2].core.\flexio.\out_fifo.$procmux$5509 ($mux).
+Removed top 31 bits (of 32) from FF cell user_proj_example.$flatten\softshell.\cpus[2].core.\flexio.\out_fifo.$procdff$16325 ($dff).
+Removed cell user_proj_example.$flatten\softshell.\cpus[2].core.\flexio.$procmux$16199 ($mux).
+Removed top 2 bits (of 4) from port B of cell user_proj_example.$flatten\softshell.\cpus[2].core.\flexio.$procmux$16190_CMP0 ($eq).
+Removed top 1 bits (of 4) from port B of cell user_proj_example.$flatten\softshell.\cpus[2].core.\flexio.$procmux$16189_CMP0 ($eq).
+Removed cell user_proj_example.$flatten\softshell.\cpus[2].core.\flexio.$procmux$16183 ($mux).
+Removed top 4 bits (of 5) from port B of cell user_proj_example.$flatten\softshell.\cpus[2].core.\flexio.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/pcpi_flexio.v:174$266 ($add).
+Removed top 15 bits (of 16) from port B of cell user_proj_example.$flatten\softshell.\cpus[2].core.\flexio.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/pcpi_flexio.v:143$257 ($add).
+Removed top 31 bits (of 32) from port B of cell user_proj_example.$flatten\softshell.\cpus[2].core.\flexio.\out_fifo.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:122$2000 ($add).
+Removed top 29 bits (of 32) from port Y of cell user_proj_example.$flatten\softshell.\cpus[2].core.\flexio.\out_fifo.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:122$2000 ($add).
+Removed top 5 bits (of 7) from port B of cell user_proj_example.$flatten\softshell.\cpus[2].core.\flexio.$eq$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/pcpi_flexio.v:48$245 ($eq).
+Removed top 6 bits (of 7) from port B of cell user_proj_example.$flatten\softshell.\cpus[2].core.\flexio.$eq$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/pcpi_flexio.v:38$242 ($eq).
+Removed top 1 bits (of 3) from port B of cell user_proj_example.$auto$opt_dff.cc:218:make_patterns_logic$19977 ($ne).
+Removed top 16 bits (of 32) from mux cell user_proj_example.$flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$ternary$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:388$2898 ($mux).
+Removed top 16 bits (of 32) from mux cell user_proj_example.$flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$ternary$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:386$2900 ($mux).
+Removed top 3 bits (of 4) from port A of cell user_proj_example.$flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$shl$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:419$2908 ($shl).
+Removed top 3 bits (of 5) from port B of cell user_proj_example.$flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$eq$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:465$2913 ($eq).
+Removed top 1 bits (of 2) from port B of cell user_proj_example.$flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$eq$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:478$2915 ($eq).
+Removed top 1 bits (of 3) from port B of cell user_proj_example.$flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$eq$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:486$2917 ($eq).
+Removed top 1 bits (of 2) from port B of cell user_proj_example.$flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$eq$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:488$2919 ($eq).
+Removed top 1 bits (of 7) from mux cell user_proj_example.$flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$ternary$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:491$2923 ($mux).
+Removed top 30 bits (of 32) from mux cell user_proj_example.$flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$ternary$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:617$2967 ($mux).
+Removed top 1 bits (of 7) from port B of cell user_proj_example.$flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$eq$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:865$2986 ($eq).
+Removed top 2 bits (of 7) from port B of cell user_proj_example.$flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$eq$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:866$2987 ($eq).
+Removed top 3 bits (of 7) from port B of cell user_proj_example.$flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$eq$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:869$2992 ($eq).
+Removed top 5 bits (of 7) from port B of cell user_proj_example.$flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$eq$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:869$2993 ($eq).
+Removed top 4 bits (of 7) from port B of cell user_proj_example.$flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$eq$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:870$2997 ($eq).
+Removed top 5 bits (of 7) from port B of cell user_proj_example.$flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$eq$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:873$3001 ($eq).
+Removed top 1 bits (of 7) from port B of cell user_proj_example.$flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$eq$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:874$3002 ($eq).
+Removed top 2 bits (of 7) from port B of cell user_proj_example.$flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$eq$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:875$3003 ($eq).
+Removed top 1 bits (of 7) from port B of cell user_proj_example.$flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$eq$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:876$3004 ($eq).
+Removed top 28 bits (of 32) from port A of cell user_proj_example.$flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:906$3017 ($add).
+Removed top 27 bits (of 32) from port Y of cell user_proj_example.$flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:906$3017 ($add).
+Removed top 28 bits (of 32) from port A of cell user_proj_example.$flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:910$3018 ($add).
+Removed top 27 bits (of 32) from port Y of cell user_proj_example.$flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:910$3018 ($add).
+Removed top 2 bits (of 3) from port B of cell user_proj_example.$flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$eq$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1039$3060 ($eq).
+Removed top 1 bits (of 3) from port B of cell user_proj_example.$flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$eq$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1047$3074 ($eq).
+Removed top 1 bits (of 3) from port B of cell user_proj_example.$flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$eq$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1057$3090 ($eq).
+Removed top 1 bits (of 7) from port B of cell user_proj_example.$flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$eq$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1064$3108 ($eq).
+Removed top 3 bits (of 7) from port B of cell user_proj_example.$flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$eq$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1089$3194 ($eq).
+Removed top 5 bits (of 7) from port B of cell user_proj_example.$flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$eq$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1089$3195 ($eq).
+Removed top 4 bits (of 7) from port B of cell user_proj_example.$flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$eq$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1090$3199 ($eq).
+Removed top 29 bits (of 32) from mux cell user_proj_example.$flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$ternary$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1312$3280 ($mux).
+Removed top 29 bits (of 32) from port B of cell user_proj_example.$flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1312$3281 ($add).
+Removed top 31 bits (of 32) from port B of cell user_proj_example.$flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$sub$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1421$3311 ($sub).
+Removed top 28 bits (of 32) from port Y of cell user_proj_example.$flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$sub$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1421$3311 ($sub).
+Removed top 32 bits (of 64) from port A of cell user_proj_example.$flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1428$3313 ($add).
+Removed top 31 bits (of 32) from port B of cell user_proj_example.$flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1428$3313 ($add).
+Removed top 32 bits (of 64) from port Y of cell user_proj_example.$flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1428$3313 ($add).
+Removed top 31 bits (of 32) from port B of cell user_proj_example.$flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$sub$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1438$3318 ($sub).
+Removed top 1 bits (of 2) from port B of cell user_proj_example.$flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$eq$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1536$3355 ($eq).
+Removed top 29 bits (of 32) from mux cell user_proj_example.$flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$ternary$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1541$3358 ($mux).
+Removed top 29 bits (of 32) from mux cell user_proj_example.$flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$ternary$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1547$3363 ($mux).
+Removed top 29 bits (of 32) from port B of cell user_proj_example.$flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1547$3364 ($add).
+Removed top 32 bits (of 64) from port A of cell user_proj_example.$flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1559$3367 ($add).
+Removed top 31 bits (of 32) from port B of cell user_proj_example.$flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1559$3367 ($add).
+Removed top 32 bits (of 64) from port Y of cell user_proj_example.$flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1559$3367 ($add).
+Removed top 1 bits (of 2) from port B of cell user_proj_example.$auto$opt_dff.cc:218:make_patterns_logic$20244 ($ne).
+Removed top 1 bits (of 33) from port Y of cell user_proj_example.$flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$sshr$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1240$3496 ($sshr).
+Removed top 2 bits (of 5) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$17334 ($eq).
+Removed top 1 bits (of 4) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$17332 ($eq).
+Removed top 6 bits (of 9) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$17672 ($eq).
+Removed top 6 bits (of 7) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$17668 ($eq).
+Removed top 3 bits (of 6) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$17328 ($eq).
+Removed top 1 bits (of 2) from port B of cell user_proj_example.$auto$opt_dff.cc:218:make_patterns_logic$21012 ($ne).
+Removed cell user_proj_example.$flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$12761 ($mux).
+Removed cell user_proj_example.$flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$12763 ($mux).
+Removed cell user_proj_example.$flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$12776 ($mux).
+Removed cell user_proj_example.$flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$12804 ($mux).
+Removed cell user_proj_example.$flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$12806 ($mux).
+Removed cell user_proj_example.$flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$12809 ($mux).
+Removed cell user_proj_example.$flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$12867 ($mux).
+Removed cell user_proj_example.$flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$12894 ($mux).
+Removed cell user_proj_example.$flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$12896 ($mux).
+Removed cell user_proj_example.$flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$12907 ($mux).
+Removed cell user_proj_example.$flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$12909 ($mux).
+Removed cell user_proj_example.$flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$12920 ($mux).
+Removed cell user_proj_example.$flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$12922 ($mux).
+Removed cell user_proj_example.$flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$12977 ($mux).
+Removed cell user_proj_example.$flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$13000 ($mux).
+Removed cell user_proj_example.$flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$13026 ($mux).
+Removed top 3 bits (of 8) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$17643 ($eq).
+Removed cell user_proj_example.$flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$13310 ($mux).
+Removed cell user_proj_example.$flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$13358 ($mux).
+Removed top 4 bits (of 10) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$17639 ($eq).
+Removed top 5 bits (of 11) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$17635 ($eq).
+Removed cell user_proj_example.$flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$13466 ($mux).
+Removed top 1 bits (of 3) from port B of cell user_proj_example.$auto$opt_dff.cc:218:make_patterns_logic$20895 ($ne).
+Removed cell user_proj_example.$flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$13472 ($mux).
+Removed cell user_proj_example.$flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$13524 ($mux).
+Removed cell user_proj_example.$flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$13526 ($mux).
+Removed cell user_proj_example.$flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$13532 ($mux).
+Removed cell user_proj_example.$flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$13534 ($mux).
+Removed cell user_proj_example.$flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$13618 ($mux).
+Removed cell user_proj_example.$flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$13621 ($mux).
+Removed cell user_proj_example.$flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$13706 ($mux).
+Removed top 1 bits (of 3) from port B of cell user_proj_example.$flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$13794_CMP0 ($eq).
+Removed top 1 bits (of 2) from port B of cell user_proj_example.$flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$13796_CMP0 ($eq).
+Removed top 1 bits (of 3) from port B of cell user_proj_example.$flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$13799_CMP0 ($eq).
+Removed top 2 bits (of 4) from mux cell user_proj_example.$flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$13857 ($mux).
+Removed top 1 bits (of 2) from port B of cell user_proj_example.$auto$opt_dff.cc:218:make_patterns_logic$20717 ($ne).
+Removed top 2 bits (of 3) from port B of cell user_proj_example.$flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$14081_CMP0 ($eq).
+Removed top 1 bits (of 2) from port B of cell user_proj_example.$auto$opt_dff.cc:218:make_patterns_logic$20703 ($ne).
+Removed cell user_proj_example.$flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$14501 ($mux).
+Removed cell user_proj_example.$flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$14503 ($mux).
+Removed cell user_proj_example.$flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$14506 ($mux).
+Removed cell user_proj_example.$flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$14508 ($mux).
+Removed top 1 bits (of 2) from port B of cell user_proj_example.$flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$14513_CMP0 ($eq).
+Removed cell user_proj_example.$flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$14548 ($mux).
+Removed cell user_proj_example.$flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$14552 ($mux).
+Removed cell user_proj_example.$flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$14556 ($mux).
+Removed cell user_proj_example.$flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$14558 ($mux).
+Removed cell user_proj_example.$flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$14561 ($mux).
+Removed top 2 bits (of 4) from port B of cell user_proj_example.$auto$opt_dff.cc:218:make_patterns_logic$20695 ($ne).
+Removed cell user_proj_example.$flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$14567 ($mux).
+Removed cell user_proj_example.$flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$14584 ($mux).
+Removed cell user_proj_example.$flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$14591 ($mux).
+Removed cell user_proj_example.$flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$14594 ($mux).
+Removed cell user_proj_example.$flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$14600 ($mux).
+Removed top 2 bits (of 6) from mux cell user_proj_example.$flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$14828 ($mux).
+Removed top 24 bits (of 32) from mux cell user_proj_example.$flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$14844 ($pmux).
+Removed top 1 bits (of 2) from port B of cell user_proj_example.$flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$14847_CMP0 ($eq).
+Removed top 16 bits (of 32) from mux cell user_proj_example.$flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$14853 ($pmux).
+Removed top 6 bits (of 10) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$17631 ($eq).
+Removed top 31 bits (of 32) from FF cell user_proj_example.$flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.\cpuregs.$procdff$16926 ($dff).
+Removed cell user_proj_example.$flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.\cpuregs.$procmux$16276 ($mux).
+Removed cell user_proj_example.$flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.\cpuregs.$procmux$16274 ($mux).
+Removed cell user_proj_example.$flatten\softshell.\cpus[2].core.\cpu.$procmux$5358 ($mux).
+Removed cell user_proj_example.$flatten\softshell.\cpus[2].core.\cpu.$procmux$5326 ($mux).
+Removed cell user_proj_example.$flatten\softshell.\cpus[2].core.\cpu.$procmux$5322 ($mux).
+Removed top 1 bits (of 5) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$17623 ($eq).
+Removed cell user_proj_example.$flatten\softshell.\cpus[2].core.\soc_mem.\ram.$procmux$14903 ($mux).
+Removed cell user_proj_example.$flatten\softshell.\cpus[2].core.\soc_mem.\ram.$procmux$14905 ($mux).
+Removed cell user_proj_example.$flatten\softshell.\cpus[2].core.\soc_mem.\ram.$procmux$14907 ($mux).
+Removed cell user_proj_example.$flatten\softshell.\cpus[2].core.\soc_mem.\ram.$procmux$14909 ($mux).
+Removed cell user_proj_example.$flatten\softshell.\cpus[2].core.\soc_mem.\ram.$procmux$14915 ($mux).
+Removed cell user_proj_example.$flatten\softshell.\cpus[2].core.\soc_mem.\ram.$procmux$14917 ($mux).
+Removed cell user_proj_example.$flatten\softshell.\cpus[2].core.\soc_mem.\ram.$procmux$14919 ($mux).
+Removed cell user_proj_example.$flatten\softshell.\cpus[2].core.\soc_mem.\ram.$procmux$14921 ($mux).
+Removed cell user_proj_example.$flatten\softshell.\cpus[2].core.\soc_mem.\ram.$procmux$14927 ($mux).
+Removed cell user_proj_example.$flatten\softshell.\cpus[2].core.\soc_mem.\ram.$procmux$14929 ($mux).
+Removed cell user_proj_example.$flatten\softshell.\cpus[2].core.\soc_mem.\ram.$procmux$14931 ($mux).
+Removed cell user_proj_example.$flatten\softshell.\cpus[2].core.\soc_mem.\ram.$procmux$14933 ($mux).
+Removed cell user_proj_example.$flatten\softshell.\cpus[2].core.\soc_mem.\ram.$procmux$14939 ($mux).
+Removed cell user_proj_example.$flatten\softshell.\cpus[2].core.\soc_mem.\ram.$procmux$14941 ($mux).
+Removed cell user_proj_example.$flatten\softshell.\cpus[2].core.\soc_mem.\ram.$procmux$14943 ($mux).
+Removed cell user_proj_example.$flatten\softshell.\cpus[2].core.\soc_mem.\ram.$procmux$14945 ($mux).
+Removed top 7 bits (of 8) from FF cell user_proj_example.$flatten\softshell.\cpus[2].core.\soc_mem.\ram.$procdff$16843 ($dff).
+Removed top 7 bits (of 8) from FF cell user_proj_example.$flatten\softshell.\cpus[2].core.\soc_mem.\ram.$procdff$16846 ($dff).
+Removed top 7 bits (of 8) from FF cell user_proj_example.$flatten\softshell.\cpus[2].core.\soc_mem.\ram.$procdff$16849 ($dff).
+Removed top 7 bits (of 8) from FF cell user_proj_example.$flatten\softshell.\cpus[2].core.\soc_mem.\ram.$procdff$16852 ($dff).
+Removed top 5 bits (of 8) from port B of cell user_proj_example.$flatten\softshell.\cpus[2].core.\gpio.\gpio_ctrl.$eq$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/gpio32_wb.v:98$2707 ($eq).
+Removed top 4 bits (of 8) from port B of cell user_proj_example.$flatten\softshell.\cpus[2].core.\gpio.\gpio_ctrl.$eq$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/gpio32_wb.v:99$2708 ($eq).
+Removed top 4 bits (of 8) from port B of cell user_proj_example.$flatten\softshell.\cpus[2].core.\gpio.\gpio_ctrl.$eq$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/gpio32_wb.v:100$2709 ($eq).
+Removed cell user_proj_example.$flatten\softshell.\cpus[2].core.\gpio.\gpio_ctrl.$procmux$5462 ($mux).
+Removed top 3 bits (of 4) from port Y of cell user_proj_example.$flatten\softshell.\cpus[2].core.\gpio.$and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/gpio32_wb.v:38$768 ($and).
+Removed top 3 bits (of 4) from port A of cell user_proj_example.$flatten\softshell.\cpus[2].core.\gpio.$and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/gpio32_wb.v:38$768 ($and).
+Removed top 3 bits (of 4) from port B of cell user_proj_example.$flatten\softshell.\cpus[2].core.\gpio.$and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/gpio32_wb.v:38$768 ($and).
+Removed top 2 bits (of 32) from port B of cell user_proj_example.$flatten\softshell.\cpus[2].core.\interconnect.$xor$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/verilog-wishbone/rtl/wb_mux_3.v:119$412 ($xor).
+Removed top 2 bits (of 32) from port B of cell user_proj_example.$flatten\softshell.\cpus[1].core.\interconnect.$xor$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/verilog-wishbone/rtl/wb_mux_3.v:117$404 ($xor).
+Removed top 1 bits (of 3) from port B of cell user_proj_example.$flatten\softshell.\cpus[1].core.\flexio.\out_fifo.$xor$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:131$2006 ($xor).
+Removed top 31 bits (of 32) from port B of cell user_proj_example.$flatten\softshell.\cpus[1].core.\flexio.\out_fifo.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:144$2013 ($add).
+Removed top 29 bits (of 32) from port Y of cell user_proj_example.$flatten\softshell.\cpus[1].core.\flexio.\out_fifo.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:144$2013 ($add).
+Removed top 1 bits (of 3) from port B of cell user_proj_example.$flatten\softshell.\cpus[1].core.\flexio.\out_fifo.$xor$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:153$2019 ($xor).
+Removed cell user_proj_example.$flatten\softshell.\cpus[1].core.\flexio.\out_fifo.$procmux$5507 ($mux).
+Removed cell user_proj_example.$flatten\softshell.\cpus[1].core.\flexio.\out_fifo.$procmux$5509 ($mux).
+Removed top 31 bits (of 32) from FF cell user_proj_example.$flatten\softshell.\cpus[1].core.\flexio.\out_fifo.$procdff$16325 ($dff).
+Removed cell user_proj_example.$flatten\softshell.\cpus[1].core.\flexio.$procmux$16199 ($mux).
+Removed top 2 bits (of 4) from port B of cell user_proj_example.$flatten\softshell.\cpus[1].core.\flexio.$procmux$16190_CMP0 ($eq).
+Removed top 1 bits (of 4) from port B of cell user_proj_example.$flatten\softshell.\cpus[1].core.\flexio.$procmux$16189_CMP0 ($eq).
+Removed cell user_proj_example.$flatten\softshell.\cpus[1].core.\flexio.$procmux$16183 ($mux).
+Removed top 4 bits (of 5) from port B of cell user_proj_example.$flatten\softshell.\cpus[1].core.\flexio.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/pcpi_flexio.v:174$266 ($add).
+Removed top 15 bits (of 16) from port B of cell user_proj_example.$flatten\softshell.\cpus[1].core.\flexio.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/pcpi_flexio.v:143$257 ($add).
+Removed top 31 bits (of 32) from port B of cell user_proj_example.$flatten\softshell.\cpus[1].core.\flexio.\out_fifo.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:122$2000 ($add).
+Removed top 29 bits (of 32) from port Y of cell user_proj_example.$flatten\softshell.\cpus[1].core.\flexio.\out_fifo.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:122$2000 ($add).
+Removed top 5 bits (of 7) from port B of cell user_proj_example.$flatten\softshell.\cpus[1].core.\flexio.$eq$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/pcpi_flexio.v:48$245 ($eq).
+Removed top 6 bits (of 7) from port B of cell user_proj_example.$flatten\softshell.\cpus[1].core.\flexio.$eq$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/pcpi_flexio.v:38$242 ($eq).
+Removed top 16 bits (of 32) from mux cell user_proj_example.$flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$ternary$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:388$3581 ($mux).
+Removed top 16 bits (of 32) from mux cell user_proj_example.$flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$ternary$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:386$3583 ($mux).
+Removed top 3 bits (of 4) from port A of cell user_proj_example.$flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$shl$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:419$3591 ($shl).
+Removed top 3 bits (of 5) from port B of cell user_proj_example.$flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$eq$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:465$3596 ($eq).
+Removed top 1 bits (of 2) from port B of cell user_proj_example.$flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$eq$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:478$3598 ($eq).
+Removed top 1 bits (of 3) from port B of cell user_proj_example.$flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$eq$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:486$3600 ($eq).
+Removed top 1 bits (of 2) from port B of cell user_proj_example.$flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$eq$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:488$3602 ($eq).
+Removed top 1 bits (of 7) from mux cell user_proj_example.$flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$ternary$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:491$3606 ($mux).
+Removed top 30 bits (of 32) from mux cell user_proj_example.$flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$ternary$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:617$3650 ($mux).
+Removed top 1 bits (of 7) from port B of cell user_proj_example.$flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$eq$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:865$3669 ($eq).
+Removed top 2 bits (of 7) from port B of cell user_proj_example.$flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$eq$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:866$3670 ($eq).
+Removed top 3 bits (of 7) from port B of cell user_proj_example.$flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$eq$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:869$3675 ($eq).
+Removed top 5 bits (of 7) from port B of cell user_proj_example.$flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$eq$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:869$3676 ($eq).
+Removed top 4 bits (of 7) from port B of cell user_proj_example.$flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$eq$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:870$3680 ($eq).
+Removed top 5 bits (of 7) from port B of cell user_proj_example.$flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$eq$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:873$3684 ($eq).
+Removed top 1 bits (of 7) from port B of cell user_proj_example.$flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$eq$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:874$3685 ($eq).
+Removed top 2 bits (of 7) from port B of cell user_proj_example.$flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$eq$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:875$3686 ($eq).
+Removed top 1 bits (of 7) from port B of cell user_proj_example.$flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$eq$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:876$3687 ($eq).
+Removed top 28 bits (of 32) from port A of cell user_proj_example.$flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:906$3700 ($add).
+Removed top 27 bits (of 32) from port Y of cell user_proj_example.$flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:906$3700 ($add).
+Removed top 28 bits (of 32) from port A of cell user_proj_example.$flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:910$3701 ($add).
+Removed top 27 bits (of 32) from port Y of cell user_proj_example.$flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:910$3701 ($add).
+Removed top 2 bits (of 3) from port B of cell user_proj_example.$flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$eq$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1039$3743 ($eq).
+Removed top 1 bits (of 3) from port B of cell user_proj_example.$flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$eq$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1047$3757 ($eq).
+Removed top 1 bits (of 3) from port B of cell user_proj_example.$flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$eq$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1057$3773 ($eq).
+Removed top 1 bits (of 7) from port B of cell user_proj_example.$flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$eq$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1064$3791 ($eq).
+Removed top 3 bits (of 7) from port B of cell user_proj_example.$flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$eq$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1089$3877 ($eq).
+Removed top 5 bits (of 7) from port B of cell user_proj_example.$flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$eq$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1089$3878 ($eq).
+Removed top 4 bits (of 7) from port B of cell user_proj_example.$flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$eq$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1090$3882 ($eq).
+Removed top 29 bits (of 32) from mux cell user_proj_example.$flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$ternary$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1312$3963 ($mux).
+Removed top 29 bits (of 32) from port B of cell user_proj_example.$flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1312$3964 ($add).
+Removed top 31 bits (of 32) from port B of cell user_proj_example.$flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$sub$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1421$3994 ($sub).
+Removed top 28 bits (of 32) from port Y of cell user_proj_example.$flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$sub$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1421$3994 ($sub).
+Removed top 32 bits (of 64) from port A of cell user_proj_example.$flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1428$3996 ($add).
+Removed top 31 bits (of 32) from port B of cell user_proj_example.$flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1428$3996 ($add).
+Removed top 32 bits (of 64) from port Y of cell user_proj_example.$flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1428$3996 ($add).
+Removed top 31 bits (of 32) from port B of cell user_proj_example.$flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$sub$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1438$4001 ($sub).
+Removed top 1 bits (of 2) from port B of cell user_proj_example.$flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$eq$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1536$4038 ($eq).
+Removed top 29 bits (of 32) from mux cell user_proj_example.$flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$ternary$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1541$4041 ($mux).
+Removed top 29 bits (of 32) from mux cell user_proj_example.$flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$ternary$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1547$4046 ($mux).
+Removed top 29 bits (of 32) from port B of cell user_proj_example.$flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1547$4047 ($add).
+Removed top 32 bits (of 64) from port A of cell user_proj_example.$flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1559$4050 ($add).
+Removed top 31 bits (of 32) from port B of cell user_proj_example.$flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1559$4050 ($add).
+Removed top 32 bits (of 64) from port Y of cell user_proj_example.$flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1559$4050 ($add).
+Removed top 1 bits (of 2) from port B of cell user_proj_example.$auto$opt_dff.cc:218:make_patterns_logic$20258 ($ne).
+Removed top 1 bits (of 33) from port Y of cell user_proj_example.$flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$sshr$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1240$4179 ($sshr).
+Removed top 2 bits (of 7) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$17619 ($eq).
+Removed cell user_proj_example.$flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$9896 ($mux).
+Removed cell user_proj_example.$flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$9898 ($mux).
+Removed top 1 bits (of 2) from port B of cell user_proj_example.$auto$opt_dff.cc:218:make_patterns_logic$19296 ($ne).
+Removed cell user_proj_example.$flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$9911 ($mux).
+Removed cell user_proj_example.$flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$9939 ($mux).
+Removed cell user_proj_example.$flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$9941 ($mux).
+Removed cell user_proj_example.$flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$9944 ($mux).
+Removed top 1 bits (of 2) from port B of cell user_proj_example.$auto$opt_dff.cc:218:make_patterns_logic$19294 ($ne).
+Removed cell user_proj_example.$flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10002 ($mux).
+Removed cell user_proj_example.$flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10029 ($mux).
+Removed cell user_proj_example.$flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10031 ($mux).
+Removed cell user_proj_example.$flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10042 ($mux).
+Removed cell user_proj_example.$flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10044 ($mux).
+Removed cell user_proj_example.$flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10055 ($mux).
+Removed cell user_proj_example.$flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10057 ($mux).
+Removed cell user_proj_example.$flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10112 ($mux).
+Removed cell user_proj_example.$flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10135 ($mux).
+Removed top 3 bits (of 8) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$17615 ($eq).
+Removed cell user_proj_example.$flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10161 ($mux).
+Removed top 4 bits (of 7) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$17611 ($eq).
+Removed top 3 bits (of 5) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$17607 ($eq).
+Removed top 1 bits (of 7) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$17602 ($eq).
+Removed top 2 bits (of 9) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$17598 ($eq).
+Removed top 3 bits (of 10) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$17594 ($eq).
+Removed top 4 bits (of 9) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$17590 ($eq).
+Removed cell user_proj_example.$flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10445 ($mux).
+Removed cell user_proj_example.$flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10493 ($mux).
+Removed top 5 bits (of 7) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$17586 ($eq).
+Removed top 1 bits (of 6) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$17582 ($eq).
+Removed cell user_proj_example.$flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10601 ($mux).
+Removed cell user_proj_example.$flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10607 ($mux).
+Removed cell user_proj_example.$flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10659 ($mux).
+Removed cell user_proj_example.$flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10661 ($mux).
+Removed cell user_proj_example.$flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10667 ($mux).
+Removed cell user_proj_example.$flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10669 ($mux).
+Removed top 1 bits (of 2) from port B of cell user_proj_example.$auto$opt_dff.cc:218:make_patterns_logic$19298 ($ne).
+Removed cell user_proj_example.$flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10753 ($mux).
+Removed cell user_proj_example.$flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10756 ($mux).
+Removed cell user_proj_example.$flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10841 ($mux).
+Removed top 1 bits (of 3) from port B of cell user_proj_example.$flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10929_CMP0 ($eq).
+Removed top 1 bits (of 2) from port B of cell user_proj_example.$flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10931_CMP0 ($eq).
+Removed top 1 bits (of 3) from port B of cell user_proj_example.$flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10934_CMP0 ($eq).
+Removed top 2 bits (of 4) from mux cell user_proj_example.$flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10992 ($mux).
+Removed top 2 bits (of 3) from port B of cell user_proj_example.$flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$11216_CMP0 ($eq).
+Removed cell user_proj_example.$flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$11636 ($mux).
+Removed cell user_proj_example.$flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$11638 ($mux).
+Removed cell user_proj_example.$flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$11641 ($mux).
+Removed cell user_proj_example.$flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$11643 ($mux).
+Removed top 1 bits (of 2) from port B of cell user_proj_example.$flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$11648_CMP0 ($eq).
+Removed cell user_proj_example.$flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$11683 ($mux).
+Removed cell user_proj_example.$flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$11687 ($mux).
+Removed cell user_proj_example.$flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$11691 ($mux).
+Removed cell user_proj_example.$flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$11693 ($mux).
+Removed cell user_proj_example.$flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$11696 ($mux).
+Removed cell user_proj_example.$flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$11702 ($mux).
+Removed cell user_proj_example.$flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$11719 ($mux).
+Removed cell user_proj_example.$flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$11726 ($mux).
+Removed cell user_proj_example.$flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$11729 ($mux).
+Removed cell user_proj_example.$flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$11735 ($mux).
+Removed top 2 bits (of 6) from mux cell user_proj_example.$flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$11963 ($mux).
+Removed top 24 bits (of 32) from mux cell user_proj_example.$flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$11979 ($pmux).
+Removed top 1 bits (of 2) from port B of cell user_proj_example.$flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$11982_CMP0 ($eq).
+Removed top 16 bits (of 32) from mux cell user_proj_example.$flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$11988 ($pmux).
+Removed top 2 bits (of 8) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$17578 ($eq).
+Removed top 31 bits (of 32) from FF cell user_proj_example.$flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.\cpuregs.$procdff$16926 ($dff).
+Removed cell user_proj_example.$flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.\cpuregs.$procmux$16276 ($mux).
+Removed cell user_proj_example.$flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.\cpuregs.$procmux$16274 ($mux).
+Removed cell user_proj_example.$flatten\softshell.\cpus[1].core.\cpu.$procmux$5251 ($mux).
+Removed top 3 bits (of 9) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$17574 ($eq).
+Removed cell user_proj_example.$flatten\softshell.\cpus[1].core.\cpu.$procmux$5219 ($mux).
+Removed cell user_proj_example.$flatten\softshell.\cpus[1].core.\cpu.$procmux$5215 ($mux).
+Removed top 4 bits (of 8) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$17570 ($eq).
+Removed cell user_proj_example.$flatten\softshell.\cpus[1].core.\soc_mem.\ram.$procmux$14903 ($mux).
+Removed cell user_proj_example.$flatten\softshell.\cpus[1].core.\soc_mem.\ram.$procmux$14905 ($mux).
+Removed cell user_proj_example.$flatten\softshell.\cpus[1].core.\soc_mem.\ram.$procmux$14907 ($mux).
+Removed cell user_proj_example.$flatten\softshell.\cpus[1].core.\soc_mem.\ram.$procmux$14909 ($mux).
+Removed cell user_proj_example.$flatten\softshell.\cpus[1].core.\soc_mem.\ram.$procmux$14915 ($mux).
+Removed cell user_proj_example.$flatten\softshell.\cpus[1].core.\soc_mem.\ram.$procmux$14917 ($mux).
+Removed cell user_proj_example.$flatten\softshell.\cpus[1].core.\soc_mem.\ram.$procmux$14919 ($mux).
+Removed cell user_proj_example.$flatten\softshell.\cpus[1].core.\soc_mem.\ram.$procmux$14921 ($mux).
+Removed cell user_proj_example.$flatten\softshell.\cpus[1].core.\soc_mem.\ram.$procmux$14927 ($mux).
+Removed cell user_proj_example.$flatten\softshell.\cpus[1].core.\soc_mem.\ram.$procmux$14929 ($mux).
+Removed cell user_proj_example.$flatten\softshell.\cpus[1].core.\soc_mem.\ram.$procmux$14931 ($mux).
+Removed cell user_proj_example.$flatten\softshell.\cpus[1].core.\soc_mem.\ram.$procmux$14933 ($mux).
+Removed cell user_proj_example.$flatten\softshell.\cpus[1].core.\soc_mem.\ram.$procmux$14939 ($mux).
+Removed cell user_proj_example.$flatten\softshell.\cpus[1].core.\soc_mem.\ram.$procmux$14941 ($mux).
+Removed cell user_proj_example.$flatten\softshell.\cpus[1].core.\soc_mem.\ram.$procmux$14943 ($mux).
+Removed cell user_proj_example.$flatten\softshell.\cpus[1].core.\soc_mem.\ram.$procmux$14945 ($mux).
+Removed top 7 bits (of 8) from FF cell user_proj_example.$flatten\softshell.\cpus[1].core.\soc_mem.\ram.$procdff$16843 ($dff).
+Removed top 7 bits (of 8) from FF cell user_proj_example.$flatten\softshell.\cpus[1].core.\soc_mem.\ram.$procdff$16846 ($dff).
+Removed top 7 bits (of 8) from FF cell user_proj_example.$flatten\softshell.\cpus[1].core.\soc_mem.\ram.$procdff$16849 ($dff).
+Removed top 7 bits (of 8) from FF cell user_proj_example.$flatten\softshell.\cpus[1].core.\soc_mem.\ram.$procdff$16852 ($dff).
+Removed top 5 bits (of 8) from port B of cell user_proj_example.$flatten\softshell.\cpus[1].core.\gpio.\gpio_ctrl.$eq$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/gpio32_wb.v:98$2707 ($eq).
+Removed top 4 bits (of 8) from port B of cell user_proj_example.$flatten\softshell.\cpus[1].core.\gpio.\gpio_ctrl.$eq$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/gpio32_wb.v:99$2708 ($eq).
+Removed top 4 bits (of 8) from port B of cell user_proj_example.$flatten\softshell.\cpus[1].core.\gpio.\gpio_ctrl.$eq$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/gpio32_wb.v:100$2709 ($eq).
+Removed cell user_proj_example.$flatten\softshell.\cpus[1].core.\gpio.\gpio_ctrl.$procmux$5462 ($mux).
+Removed top 3 bits (of 4) from port Y of cell user_proj_example.$flatten\softshell.\cpus[1].core.\gpio.$and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/gpio32_wb.v:38$768 ($and).
+Removed top 3 bits (of 4) from port A of cell user_proj_example.$flatten\softshell.\cpus[1].core.\gpio.$and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/gpio32_wb.v:38$768 ($and).
+Removed top 3 bits (of 4) from port B of cell user_proj_example.$flatten\softshell.\cpus[1].core.\gpio.$and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/gpio32_wb.v:38$768 ($and).
+Removed top 2 bits (of 32) from port B of cell user_proj_example.$flatten\softshell.\cpus[1].core.\interconnect.$xor$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/verilog-wishbone/rtl/wb_mux_3.v:119$412 ($xor).
+Removed top 2 bits (of 32) from port B of cell user_proj_example.$flatten\softshell.\cpus[0].core.\interconnect.$xor$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/verilog-wishbone/rtl/wb_mux_3.v:117$404 ($xor).
+Removed top 1 bits (of 3) from port B of cell user_proj_example.$flatten\softshell.\cpus[0].core.\flexio.\out_fifo.$xor$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:131$2006 ($xor).
+Removed top 31 bits (of 32) from port B of cell user_proj_example.$flatten\softshell.\cpus[0].core.\flexio.\out_fifo.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:144$2013 ($add).
+Removed top 29 bits (of 32) from port Y of cell user_proj_example.$flatten\softshell.\cpus[0].core.\flexio.\out_fifo.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:144$2013 ($add).
+Removed top 1 bits (of 3) from port B of cell user_proj_example.$flatten\softshell.\cpus[0].core.\flexio.\out_fifo.$xor$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:153$2019 ($xor).
+Removed cell user_proj_example.$flatten\softshell.\cpus[0].core.\flexio.\out_fifo.$procmux$5507 ($mux).
+Removed cell user_proj_example.$flatten\softshell.\cpus[0].core.\flexio.\out_fifo.$procmux$5509 ($mux).
+Removed top 31 bits (of 32) from FF cell user_proj_example.$flatten\softshell.\cpus[0].core.\flexio.\out_fifo.$procdff$16325 ($dff).
+Removed cell user_proj_example.$flatten\softshell.\cpus[0].core.\flexio.$procmux$16199 ($mux).
+Removed top 2 bits (of 4) from port B of cell user_proj_example.$flatten\softshell.\cpus[0].core.\flexio.$procmux$16190_CMP0 ($eq).
+Removed top 1 bits (of 4) from port B of cell user_proj_example.$flatten\softshell.\cpus[0].core.\flexio.$procmux$16189_CMP0 ($eq).
+Removed cell user_proj_example.$flatten\softshell.\cpus[0].core.\flexio.$procmux$16183 ($mux).
+Removed top 4 bits (of 5) from port B of cell user_proj_example.$flatten\softshell.\cpus[0].core.\flexio.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/pcpi_flexio.v:174$266 ($add).
+Removed top 15 bits (of 16) from port B of cell user_proj_example.$flatten\softshell.\cpus[0].core.\flexio.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/pcpi_flexio.v:143$257 ($add).
+Removed top 31 bits (of 32) from port B of cell user_proj_example.$flatten\softshell.\cpus[0].core.\flexio.\out_fifo.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:122$2000 ($add).
+Removed top 29 bits (of 32) from port Y of cell user_proj_example.$flatten\softshell.\cpus[0].core.\flexio.\out_fifo.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:122$2000 ($add).
+Removed top 5 bits (of 7) from port B of cell user_proj_example.$flatten\softshell.\cpus[0].core.\flexio.$eq$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/pcpi_flexio.v:48$245 ($eq).
+Removed top 6 bits (of 7) from port B of cell user_proj_example.$flatten\softshell.\cpus[0].core.\flexio.$eq$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/pcpi_flexio.v:38$242 ($eq).
+Removed top 16 bits (of 32) from mux cell user_proj_example.$flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$ternary$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:388$4264 ($mux).
+Removed top 16 bits (of 32) from mux cell user_proj_example.$flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$ternary$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:386$4266 ($mux).
+Removed top 3 bits (of 4) from port A of cell user_proj_example.$flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$shl$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:419$4274 ($shl).
+Removed top 3 bits (of 5) from port B of cell user_proj_example.$flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$eq$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:465$4279 ($eq).
+Removed top 1 bits (of 2) from port B of cell user_proj_example.$flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$eq$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:478$4281 ($eq).
+Removed top 1 bits (of 3) from port B of cell user_proj_example.$flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$eq$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:486$4283 ($eq).
+Removed top 1 bits (of 2) from port B of cell user_proj_example.$flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$eq$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:488$4285 ($eq).
+Removed top 1 bits (of 7) from mux cell user_proj_example.$flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$ternary$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:491$4289 ($mux).
+Removed top 30 bits (of 32) from mux cell user_proj_example.$flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$ternary$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:617$4333 ($mux).
+Removed top 1 bits (of 7) from port B of cell user_proj_example.$flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$eq$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:865$4352 ($eq).
+Removed top 2 bits (of 7) from port B of cell user_proj_example.$flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$eq$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:866$4353 ($eq).
+Removed top 3 bits (of 7) from port B of cell user_proj_example.$flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$eq$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:869$4358 ($eq).
+Removed top 5 bits (of 7) from port B of cell user_proj_example.$flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$eq$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:869$4359 ($eq).
+Removed top 4 bits (of 7) from port B of cell user_proj_example.$flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$eq$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:870$4363 ($eq).
+Removed top 5 bits (of 7) from port B of cell user_proj_example.$flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$eq$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:873$4367 ($eq).
+Removed top 1 bits (of 7) from port B of cell user_proj_example.$flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$eq$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:874$4368 ($eq).
+Removed top 2 bits (of 7) from port B of cell user_proj_example.$flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$eq$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:875$4369 ($eq).
+Removed top 1 bits (of 7) from port B of cell user_proj_example.$flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$eq$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:876$4370 ($eq).
+Removed top 28 bits (of 32) from port A of cell user_proj_example.$flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:906$4383 ($add).
+Removed top 27 bits (of 32) from port Y of cell user_proj_example.$flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:906$4383 ($add).
+Removed top 28 bits (of 32) from port A of cell user_proj_example.$flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:910$4384 ($add).
+Removed top 27 bits (of 32) from port Y of cell user_proj_example.$flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:910$4384 ($add).
+Removed top 2 bits (of 3) from port B of cell user_proj_example.$flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$eq$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1039$4426 ($eq).
+Removed top 1 bits (of 3) from port B of cell user_proj_example.$flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$eq$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1047$4440 ($eq).
+Removed top 1 bits (of 3) from port B of cell user_proj_example.$flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$eq$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1057$4456 ($eq).
+Removed top 1 bits (of 7) from port B of cell user_proj_example.$flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$eq$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1064$4474 ($eq).
+Removed top 3 bits (of 7) from port B of cell user_proj_example.$flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$eq$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1089$4560 ($eq).
+Removed top 5 bits (of 7) from port B of cell user_proj_example.$flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$eq$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1089$4561 ($eq).
+Removed top 4 bits (of 7) from port B of cell user_proj_example.$flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$eq$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1090$4565 ($eq).
+Removed top 29 bits (of 32) from mux cell user_proj_example.$flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$ternary$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1312$4646 ($mux).
+Removed top 29 bits (of 32) from port B of cell user_proj_example.$flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1312$4647 ($add).
+Removed top 31 bits (of 32) from port B of cell user_proj_example.$flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$sub$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1421$4677 ($sub).
+Removed top 28 bits (of 32) from port Y of cell user_proj_example.$flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$sub$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1421$4677 ($sub).
+Removed top 32 bits (of 64) from port A of cell user_proj_example.$flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1428$4679 ($add).
+Removed top 31 bits (of 32) from port B of cell user_proj_example.$flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1428$4679 ($add).
+Removed top 32 bits (of 64) from port Y of cell user_proj_example.$flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1428$4679 ($add).
+Removed top 31 bits (of 32) from port B of cell user_proj_example.$flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$sub$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1438$4684 ($sub).
+Removed top 1 bits (of 2) from port B of cell user_proj_example.$flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$eq$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1536$4721 ($eq).
+Removed top 29 bits (of 32) from mux cell user_proj_example.$flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$ternary$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1541$4724 ($mux).
+Removed top 29 bits (of 32) from mux cell user_proj_example.$flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$ternary$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1547$4729 ($mux).
+Removed top 29 bits (of 32) from port B of cell user_proj_example.$flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1547$4730 ($add).
+Removed top 32 bits (of 64) from port A of cell user_proj_example.$flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1559$4733 ($add).
+Removed top 31 bits (of 32) from port B of cell user_proj_example.$flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1559$4733 ($add).
+Removed top 32 bits (of 64) from port Y of cell user_proj_example.$flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1559$4733 ($add).
+Removed top 1 bits (of 33) from port Y of cell user_proj_example.$flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$sshr$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1240$4862 ($sshr).
+Removed top 4 bits (of 6) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$17566 ($eq).
+Removed top 4 bits (of 9) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$17349 ($eq).
+Removed top 2 bits (of 7) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$17477 ($eq).
+Removed top 3 bits (of 10) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$17353 ($eq).
+Removed top 1 bits (of 3) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$17340 ($eq).
+Removed top 2 bits (of 9) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$17357 ($eq).
+Removed cell user_proj_example.$flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$6250 ($mux).
+Removed cell user_proj_example.$flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$6252 ($mux).
+Removed cell user_proj_example.$flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$6265 ($mux).
+Removed cell user_proj_example.$flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$6293 ($mux).
+Removed cell user_proj_example.$flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$6295 ($mux).
+Removed cell user_proj_example.$flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$6298 ($mux).
+Removed cell user_proj_example.$flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$6356 ($mux).
+Removed cell user_proj_example.$flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$6383 ($mux).
+Removed cell user_proj_example.$flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$6385 ($mux).
+Removed cell user_proj_example.$flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$6396 ($mux).
+Removed cell user_proj_example.$flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$6398 ($mux).
+Removed cell user_proj_example.$flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$6409 ($mux).
+Removed cell user_proj_example.$flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$6411 ($mux).
+Removed cell user_proj_example.$flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$6466 ($mux).
+Removed cell user_proj_example.$flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$6489 ($mux).
+Removed cell user_proj_example.$flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$6515 ($mux).
+Removed cell user_proj_example.$flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$6799 ($mux).
+Removed cell user_proj_example.$flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$6847 ($mux).
+Removed top 1 bits (of 5) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$17529 ($eq).
+Removed cell user_proj_example.$flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$6955 ($mux).
+Removed cell user_proj_example.$flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$6961 ($mux).
+Removed cell user_proj_example.$flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$7013 ($mux).
+Removed cell user_proj_example.$flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$7015 ($mux).
+Removed cell user_proj_example.$flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$7021 ($mux).
+Removed cell user_proj_example.$flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$7023 ($mux).
+Removed cell user_proj_example.$flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$7107 ($mux).
+Removed cell user_proj_example.$flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$7110 ($mux).
+Removed cell user_proj_example.$flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$7195 ($mux).
+Removed top 1 bits (of 3) from port B of cell user_proj_example.$flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$7283_CMP0 ($eq).
+Removed top 1 bits (of 2) from port B of cell user_proj_example.$flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$7285_CMP0 ($eq).
+Removed top 1 bits (of 3) from port B of cell user_proj_example.$flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$7288_CMP0 ($eq).
+Removed top 2 bits (of 4) from mux cell user_proj_example.$flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$7346 ($mux).
+Removed top 2 bits (of 3) from port B of cell user_proj_example.$flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$7570_CMP0 ($eq).
+Removed cell user_proj_example.$flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$7990 ($mux).
+Removed cell user_proj_example.$flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$7992 ($mux).
+Removed cell user_proj_example.$flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$7995 ($mux).
+Removed cell user_proj_example.$flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$7997 ($mux).
+Removed top 1 bits (of 2) from port B of cell user_proj_example.$flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$8002_CMP0 ($eq).
+Removed cell user_proj_example.$flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$8037 ($mux).
+Removed cell user_proj_example.$flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$8041 ($mux).
+Removed cell user_proj_example.$flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$8045 ($mux).
+Removed cell user_proj_example.$flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$8047 ($mux).
+Removed cell user_proj_example.$flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$8050 ($mux).
+Removed cell user_proj_example.$flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$8056 ($mux).
+Removed cell user_proj_example.$flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$8073 ($mux).
+Removed cell user_proj_example.$flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$8080 ($mux).
+Removed cell user_proj_example.$flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$8083 ($mux).
+Removed cell user_proj_example.$flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$8089 ($mux).
+Removed top 2 bits (of 6) from mux cell user_proj_example.$flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$8317 ($mux).
+Removed top 24 bits (of 32) from mux cell user_proj_example.$flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$8333 ($pmux).
+Removed top 1 bits (of 2) from port B of cell user_proj_example.$flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$8336_CMP0 ($eq).
+Removed top 16 bits (of 32) from mux cell user_proj_example.$flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$8342 ($pmux).
+Removed top 31 bits (of 32) from FF cell user_proj_example.$flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.\cpuregs.$procdff$16926 ($dff).
+Removed cell user_proj_example.$flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.\cpuregs.$procmux$16276 ($mux).
+Removed cell user_proj_example.$flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.\cpuregs.$procmux$16274 ($mux).
+Removed cell user_proj_example.$flatten\softshell.\cpus[0].core.\cpu.$procmux$5144 ($mux).
+Removed top 2 bits (of 7) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$17523 ($eq).
+Removed cell user_proj_example.$flatten\softshell.\cpus[0].core.\cpu.$procmux$5112 ($mux).
+Removed cell user_proj_example.$flatten\softshell.\cpus[0].core.\cpu.$procmux$5108 ($mux).
+Removed top 3 bits (of 8) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$17517 ($eq).
+Removed cell user_proj_example.$flatten\softshell.\cpus[0].core.\soc_mem.\ram.$procmux$14903 ($mux).
+Removed cell user_proj_example.$flatten\softshell.\cpus[0].core.\soc_mem.\ram.$procmux$14905 ($mux).
+Removed cell user_proj_example.$flatten\softshell.\cpus[0].core.\soc_mem.\ram.$procmux$14907 ($mux).
+Removed cell user_proj_example.$flatten\softshell.\cpus[0].core.\soc_mem.\ram.$procmux$14909 ($mux).
+Removed cell user_proj_example.$flatten\softshell.\cpus[0].core.\soc_mem.\ram.$procmux$14915 ($mux).
+Removed cell user_proj_example.$flatten\softshell.\cpus[0].core.\soc_mem.\ram.$procmux$14917 ($mux).
+Removed cell user_proj_example.$flatten\softshell.\cpus[0].core.\soc_mem.\ram.$procmux$14919 ($mux).
+Removed cell user_proj_example.$flatten\softshell.\cpus[0].core.\soc_mem.\ram.$procmux$14921 ($mux).
+Removed cell user_proj_example.$flatten\softshell.\cpus[0].core.\soc_mem.\ram.$procmux$14927 ($mux).
+Removed cell user_proj_example.$flatten\softshell.\cpus[0].core.\soc_mem.\ram.$procmux$14929 ($mux).
+Removed cell user_proj_example.$flatten\softshell.\cpus[0].core.\soc_mem.\ram.$procmux$14931 ($mux).
+Removed cell user_proj_example.$flatten\softshell.\cpus[0].core.\soc_mem.\ram.$procmux$14933 ($mux).
+Removed cell user_proj_example.$flatten\softshell.\cpus[0].core.\soc_mem.\ram.$procmux$14939 ($mux).
+Removed cell user_proj_example.$flatten\softshell.\cpus[0].core.\soc_mem.\ram.$procmux$14941 ($mux).
+Removed cell user_proj_example.$flatten\softshell.\cpus[0].core.\soc_mem.\ram.$procmux$14943 ($mux).
+Removed cell user_proj_example.$flatten\softshell.\cpus[0].core.\soc_mem.\ram.$procmux$14945 ($mux).
+Removed top 7 bits (of 8) from FF cell user_proj_example.$flatten\softshell.\cpus[0].core.\soc_mem.\ram.$procdff$16843 ($dff).
+Removed top 7 bits (of 8) from FF cell user_proj_example.$flatten\softshell.\cpus[0].core.\soc_mem.\ram.$procdff$16846 ($dff).
+Removed top 7 bits (of 8) from FF cell user_proj_example.$flatten\softshell.\cpus[0].core.\soc_mem.\ram.$procdff$16849 ($dff).
+Removed top 7 bits (of 8) from FF cell user_proj_example.$flatten\softshell.\cpus[0].core.\soc_mem.\ram.$procdff$16852 ($dff).
+Removed top 5 bits (of 8) from port B of cell user_proj_example.$flatten\softshell.\cpus[0].core.\gpio.\gpio_ctrl.$eq$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/gpio32_wb.v:98$2707 ($eq).
+Removed top 4 bits (of 8) from port B of cell user_proj_example.$flatten\softshell.\cpus[0].core.\gpio.\gpio_ctrl.$eq$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/gpio32_wb.v:99$2708 ($eq).
+Removed top 4 bits (of 8) from port B of cell user_proj_example.$flatten\softshell.\cpus[0].core.\gpio.\gpio_ctrl.$eq$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/gpio32_wb.v:100$2709 ($eq).
+Removed cell user_proj_example.$flatten\softshell.\cpus[0].core.\gpio.\gpio_ctrl.$procmux$5462 ($mux).
+Removed top 3 bits (of 4) from port Y of cell user_proj_example.$flatten\softshell.\cpus[0].core.\gpio.$and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/gpio32_wb.v:38$768 ($and).
+Removed top 3 bits (of 4) from port A of cell user_proj_example.$flatten\softshell.\cpus[0].core.\gpio.$and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/gpio32_wb.v:38$768 ($and).
+Removed top 3 bits (of 4) from port B of cell user_proj_example.$flatten\softshell.\cpus[0].core.\gpio.$and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/gpio32_wb.v:38$768 ($and).
+Removed top 2 bits (of 32) from port B of cell user_proj_example.$flatten\softshell.\cpus[0].core.\interconnect.$xor$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/verilog-wishbone/rtl/wb_mux_3.v:119$412 ($xor).
+Removed top 2 bits (of 32) from port B of cell user_proj_example.$flatten\softshell.\interconnect.$xor$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/verilog-wishbone/rtl/wb_mux_5.v:158$449 ($xor).
+Removed top 2 bits (of 32) from port B of cell user_proj_example.$flatten\softshell.\interconnect.$xor$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/verilog-wishbone/rtl/wb_mux_5.v:159$453 ($xor).
+Removed top 2 bits (of 32) from port B of cell user_proj_example.$flatten\softshell.\interconnect.$xor$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/verilog-wishbone/rtl/wb_mux_5.v:160$457 ($xor).
+Removed top 2 bits (of 32) from port B of cell user_proj_example.$flatten\softshell.\interconnect.$xor$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/verilog-wishbone/rtl/wb_mux_5.v:161$461 ($xor).
+Removed top 1 bits (of 2) from port B of cell user_proj_example.$auto$opt_dff.cc:218:make_patterns_logic$20420 ($ne).
+Removed top 30 bits (of 32) from port A of cell user_proj_example.$flatten\softshell.\arbiter.\arb_inst.\priority_encoder_inst.$shl$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/verilog-wishbone/rtl/priority_encoder.v:96$4863 ($shl).
+Removed top 28 bits (of 32) from port Y of cell user_proj_example.$flatten\softshell.\arbiter.\arb_inst.\priority_encoder_inst.$shl$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/verilog-wishbone/rtl/priority_encoder.v:96$4863 ($shl).
+Removed top 1 bits (of 5) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$17481 ($eq).
+Removed top 31 bits (of 32) from port B of cell user_proj_example.$flatten\softshell.\arbiter.\arb_inst.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/verilog-wishbone/rtl/arbiter.v:132$2755 ($add).
+Removed top 29 bits (of 32) from port Y of cell user_proj_example.$flatten\softshell.\arbiter.\arb_inst.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/verilog-wishbone/rtl/arbiter.v:132$2755 ($add).
+Removed top 31 bits (of 32) from port B of cell user_proj_example.$flatten\softshell.\arbiter.\arb_inst.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/verilog-wishbone/rtl/arbiter.v:123$2753 ($add).
+Removed top 29 bits (of 32) from port Y of cell user_proj_example.$flatten\softshell.\arbiter.\arb_inst.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/verilog-wishbone/rtl/arbiter.v:123$2753 ($add).
+Removed top 30 bits (of 32) from port A of cell user_proj_example.$flatten\softshell.\arbiter.\arb_inst.\priority_encoder_masked.$shl$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/verilog-wishbone/rtl/priority_encoder.v:96$4863 ($shl).
+Removed top 28 bits (of 32) from port Y of cell user_proj_example.$flatten\softshell.\arbiter.\arb_inst.\priority_encoder_masked.$shl$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/verilog-wishbone/rtl/priority_encoder.v:96$4863 ($shl).
+Removed top 3 bits (of 4) from port B of cell user_proj_example.$flatten\softshell.\flash.\spimemio.\xfer.$sub$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/spimemio.v:633$727 ($sub).
+Removed top 1 bits (of 4) from port B of cell user_proj_example.$flatten\softshell.\flash.\spimemio.\xfer.$sub$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/spimemio.v:653$734 ($sub).
+Removed top 2 bits (of 4) from port B of cell user_proj_example.$flatten\softshell.\flash.\spimemio.\xfer.$sub$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/spimemio.v:686$746 ($sub).
+Removed top 1 bits (of 2) from port B of cell user_proj_example.$auto$opt_dff.cc:218:make_patterns_logic$20490 ($ne).
+Removed top 28 bits (of 32) from mux cell user_proj_example.$flatten\softshell.\flash.\spimemio.\xfer.$ternary$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/spimemio.v:729$765 ($mux).
+Removed cell user_proj_example.$flatten\softshell.\flash.\spimemio.\xfer.$procmux$8407 ($mux).
+Removed top 1 bits (of 4) from mux cell user_proj_example.$flatten\softshell.\flash.\spimemio.\xfer.$procmux$8414 ($mux).
+Removed top 1 bits (of 4) from mux cell user_proj_example.$flatten\softshell.\flash.\spimemio.\xfer.$procmux$8417 ($mux).
+Removed cell user_proj_example.$flatten\softshell.\flash.\spimemio.\xfer.$procmux$8432 ($mux).
+Removed cell user_proj_example.$flatten\softshell.\flash.\spimemio.\xfer.$procmux$8435 ($mux).
+Removed cell user_proj_example.$flatten\softshell.\flash.\spimemio.\xfer.$procmux$8452 ($mux).
+Removed cell user_proj_example.$flatten\softshell.\flash.\spimemio.\xfer.$procmux$8455 ($mux).
+Removed cell user_proj_example.$flatten\softshell.\flash.\spimemio.\xfer.$procmux$8472 ($mux).
+Removed cell user_proj_example.$flatten\softshell.\flash.\spimemio.\xfer.$procmux$8474 ($mux).
+Removed top 1 bits (of 2) from port B of cell user_proj_example.$flatten\softshell.\flash.\spimemio.\xfer.$procmux$8476_CMP0 ($eq).
+Removed cell user_proj_example.$flatten\softshell.\flash.\spimemio.\xfer.$procmux$8478 ($mux).
+Removed cell user_proj_example.$flatten\softshell.\flash.\spimemio.\xfer.$procmux$8483 ($mux).
+Removed cell user_proj_example.$flatten\softshell.\flash.\spimemio.\xfer.$procmux$8496 ($mux).
+Removed top 1 bits (of 7) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$17314 ($eq).
+Removed cell user_proj_example.$flatten\softshell.\flash.\spimemio.\xfer.$procmux$8513 ($mux).
+Removed cell user_proj_example.$flatten\softshell.\flash.\spimemio.\xfer.$procmux$8515 ($mux).
+Removed cell user_proj_example.$flatten\softshell.\flash.\spimemio.\xfer.$procmux$8522 ($mux).
+Removed cell user_proj_example.$flatten\softshell.\flash.\spimemio.\xfer.$procmux$8533 ($mux).
+Removed cell user_proj_example.$flatten\softshell.\flash.\spimemio.\xfer.$procmux$8547 ($mux).
+Removed cell user_proj_example.$flatten\softshell.\flash.\spimemio.\xfer.$procmux$8549 ($mux).
+Removed cell user_proj_example.$flatten\softshell.\flash.\spimemio.\xfer.$procmux$8557 ($mux).
+Removed cell user_proj_example.$flatten\softshell.\flash.\spimemio.\xfer.$procmux$8569 ($mux).
+Removed cell user_proj_example.$flatten\softshell.\flash.\spimemio.\xfer.$procmux$8587 ($mux).
+Removed cell user_proj_example.$flatten\softshell.\flash.\spimemio.\xfer.$procmux$8597 ($mux).
+Removed top 2 bits (of 5) from port B of cell user_proj_example.$auto$opt_dff.cc:218:make_patterns_logic$20461 ($ne).
+Removed cell user_proj_example.$flatten\softshell.\flash.\spimemio.\xfer.$procmux$8607 ($mux).
+Removed top 2 bits (of 3) from port B of cell user_proj_example.$auto$opt_dff.cc:218:make_patterns_logic$20438 ($ne).
+Removed top 2 bits (of 9) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$17310 ($eq).
+Removed top 1 bits (of 4) from mux cell user_proj_example.$flatten\softshell.\flash.\spimemio.\xfer.$procmux$8691 ($mux).
+Removed cell user_proj_example.$flatten\softshell.\flash.\spimemio.\xfer.$procmux$8697 ($mux).
+Removed top 1 bits (of 2) from port B of cell user_proj_example.$flatten\softshell.\flash.\spimemio.$procmux$8978_CMP0 ($eq).
+Removed cell user_proj_example.$flatten\softshell.\flash.\spimemio.$procmux$8972 ($mux).
+Removed top 1 bits (of 2) from port B of cell user_proj_example.$auto$opt_dff.cc:218:make_patterns_logic$20515 ($ne).
+Removed cell user_proj_example.$flatten\softshell.\flash.\spimemio.$procmux$8952 ($mux).
+Removed cell user_proj_example.$flatten\softshell.\flash.\spimemio.$procmux$8942 ($mux).
+Removed cell user_proj_example.$flatten\softshell.\flash.\spimemio.$procmux$8828 ($mux).
+Removed cell user_proj_example.$flatten\softshell.\flash.\spimemio.$procmux$8811 ($mux).
+Removed top 4 bits (of 7) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$17511 ($eq).
+Removed top 3 bits (of 5) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$17505 ($eq).
+Removed top 1 bits (of 4) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$17501 ($eq).
+Removed top 2 bits (of 6) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$17497 ($eq).
+Removed top 3 bits (of 7) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$17493 ($eq).
+Removed top 4 bits (of 6) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$17489 ($eq).
+Removed top 3 bits (of 4) from port B of cell user_proj_example.$auto$fsm_map.cc:77:implement_pattern_cache$17485 ($eq).
+Removed top 1 bits (of 8) from mux cell user_proj_example.$flatten\softshell.\flash.\spimemio.$ternary$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/spimemio.v:478$712 ($mux).
+Removed top 8 bits (of 32) from mux cell user_proj_example.$flatten\softshell.\flash.\spimemio.$ternary$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/spimemio.v:388$707 ($mux).
+Removed top 1 bits (of 4) from port B of cell user_proj_example.$flatten\softshell.\flash.\spimemio.$eq$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/spimemio.v:386$703 ($eq).
+Removed top 2 bits (of 4) from port B of cell user_proj_example.$flatten\softshell.\flash.\spimemio.$eq$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/spimemio.v:385$701 ($eq).
+Removed top 2 bits (of 4) from port B of cell user_proj_example.$flatten\softshell.\flash.\spimemio.$eq$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/spimemio.v:384$699 ($eq).
+Removed top 3 bits (of 4) from port B of cell user_proj_example.$flatten\softshell.\flash.\spimemio.$eq$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/spimemio.v:383$697 ($eq).
+Removed top 29 bits (of 32) from port B of cell user_proj_example.$flatten\softshell.\flash.\spimemio.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/spimemio.v:216$618 ($add).
+Removed top 7 bits (of 32) from port Y of cell user_proj_example.$flatten\softshell.\flash.\spimemio.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/spimemio.v:216$618 ($add).
+Removed top 2 bits (of 32) from port B of cell user_proj_example.$flatten\softshell.\uart0.$eq$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/simpleuart.v:52$1719 ($eq).
+Removed top 2 bits (of 32) from port B of cell user_proj_example.$flatten\softshell.\uart0.$eq$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/simpleuart.v:53$1721 ($eq).
+Removed top 2 bits (of 32) from port B of cell user_proj_example.$flatten\softshell.\uart0.$eq$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/simpleuart.v:54$1723 ($eq).
+Removed cell user_proj_example.$flatten\softshell.\uart0.\simpleuart.$procmux$9130 ($mux).
+Removed cell user_proj_example.$flatten\softshell.\uart0.\simpleuart.$procmux$9127 ($mux).
+Removed cell user_proj_example.$flatten\softshell.\uart0.\simpleuart.$procmux$9123 ($mux).
+Removed cell user_proj_example.$flatten\softshell.\uart0.\simpleuart.$procmux$9120 ($mux).
+Removed top 3 bits (of 4) from port B of cell user_proj_example.$flatten\softshell.\uart0.\simpleuart.$procmux$9087_CMP0 ($eq).
+Removed top 1 bits (of 10) from mux cell user_proj_example.$flatten\softshell.\uart0.\simpleuart.$procmux$9072 ($mux).
+Removed cell user_proj_example.$flatten\softshell.\uart0.\simpleuart.$procmux$9069 ($mux).
+Removed cell user_proj_example.$flatten\softshell.\uart0.\simpleuart.$procmux$9058 ($mux).
+Removed cell user_proj_example.$flatten\softshell.\uart0.\simpleuart.$procmux$9050 ($mux).
+Removed top 31 bits (of 32) from port B of cell user_proj_example.$flatten\softshell.\uart0.\simpleuart.$sub$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/simpleuart.v:217$607 ($sub).
+Removed top 28 bits (of 32) from port Y of cell user_proj_example.$flatten\softshell.\uart0.\simpleuart.$sub$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/simpleuart.v:217$607 ($sub).
+Removed top 31 bits (of 32) from port B of cell user_proj_example.$flatten\softshell.\uart0.\simpleuart.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/simpleuart.v:197$599 ($add).
+Removed top 31 bits (of 32) from port B of cell user_proj_example.$flatten\softshell.\uart0.\simpleuart.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/simpleuart.v:184$596 ($add).
+Removed top 28 bits (of 32) from port Y of cell user_proj_example.$flatten\softshell.\uart0.\simpleuart.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/simpleuart.v:184$596 ($add).
+Removed top 1 bits (of 2) from port B of cell user_proj_example.$auto$opt_dff.cc:218:make_patterns_logic$20375 ($ne).
+Removed top 31 bits (of 32) from port B of cell user_proj_example.$flatten\softshell.\uart0.\simpleuart.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/simpleuart.v:159$589 ($add).
+Removed top 3 bits (of 16) from port B of cell user_proj_example.$flatten\softshell.\pinmux.$and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/pinmux.v:67$1814 ($and).
+Removed top 2 bits (of 16) from port B of cell user_proj_example.$flatten\softshell.\pinmux.$and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/pinmux.v:68$1816 ($and).
+Removed top 1 bits (of 5) from port B of cell user_proj_example.$flatten\softshell.\pinmux.$procmux$15052_CMP0 ($eq).
+Removed top 1 bits (of 5) from port B of cell user_proj_example.$flatten\softshell.\pinmux.$procmux$15053_CMP0 ($eq).
+Removed top 1 bits (of 5) from port B of cell user_proj_example.$flatten\softshell.\pinmux.$procmux$15054_CMP0 ($eq).
+Removed top 1 bits (of 5) from port B of cell user_proj_example.$flatten\softshell.\pinmux.$procmux$15055_CMP0 ($eq).
+Removed top 1 bits (of 5) from port B of cell user_proj_example.$flatten\softshell.\pinmux.$procmux$15056_CMP0 ($eq).
+Removed top 1 bits (of 5) from port B of cell user_proj_example.$flatten\softshell.\pinmux.$procmux$15057_CMP0 ($eq).
+Removed top 1 bits (of 5) from port B of cell user_proj_example.$flatten\softshell.\pinmux.$procmux$15058_CMP0 ($eq).
+Removed top 1 bits (of 5) from port B of cell user_proj_example.$flatten\softshell.\pinmux.$procmux$15059_CMP0 ($eq).
+Removed top 2 bits (of 5) from port B of cell user_proj_example.$flatten\softshell.\pinmux.$procmux$15060_CMP0 ($eq).
+Removed top 2 bits (of 5) from port B of cell user_proj_example.$flatten\softshell.\pinmux.$procmux$15061_CMP0 ($eq).
+Removed top 2 bits (of 5) from port B of cell user_proj_example.$flatten\softshell.\pinmux.$procmux$15062_CMP0 ($eq).
+Removed top 2 bits (of 5) from port B of cell user_proj_example.$flatten\softshell.\pinmux.$procmux$15063_CMP0 ($eq).
+Removed top 3 bits (of 5) from port B of cell user_proj_example.$flatten\softshell.\pinmux.$procmux$15064_CMP0 ($eq).
+Removed top 3 bits (of 5) from port B of cell user_proj_example.$flatten\softshell.\pinmux.$procmux$15065_CMP0 ($eq).
+Removed top 4 bits (of 5) from port B of cell user_proj_example.$flatten\softshell.\pinmux.$procmux$15066_CMP0 ($eq).
+Removed cell user_proj_example.$flatten\softshell.\pinmux.$procmux$15132 ($mux).
+Removed top 1 bits (of 2) from port B of cell user_proj_example.$auto$opt_dff.cc:218:make_patterns_logic$20385 ($ne).
+Removed cell user_proj_example.$flatten\softshell.\pinmux.$procmux$16170 ($mux).
+Removed top 26 bits (of 32) from mux cell user_proj_example.$flatten\softshell.\pinmux.$procmux$16173 ($mux).
+Removed top 7 bits (of 8) from FF cell user_proj_example.$flatten\softshell.\shared_mem.\ram.$procdff$16865 ($dff).
+Removed top 7 bits (of 8) from FF cell user_proj_example.$flatten\softshell.\shared_mem.\ram.$procdff$16862 ($dff).
+Removed top 7 bits (of 8) from FF cell user_proj_example.$flatten\softshell.\shared_mem.\ram.$procdff$16859 ($dff).
+Removed top 7 bits (of 8) from FF cell user_proj_example.$flatten\softshell.\shared_mem.\ram.$procdff$16856 ($dff).
+Removed cell user_proj_example.$flatten\softshell.\shared_mem.\ram.$procmux$15001 ($mux).
+Removed cell user_proj_example.$flatten\softshell.\shared_mem.\ram.$procmux$14999 ($mux).
+Removed cell user_proj_example.$flatten\softshell.\shared_mem.\ram.$procmux$14997 ($mux).
+Removed cell user_proj_example.$flatten\softshell.\shared_mem.\ram.$procmux$14995 ($mux).
+Removed cell user_proj_example.$flatten\softshell.\shared_mem.\ram.$procmux$14989 ($mux).
+Removed cell user_proj_example.$flatten\softshell.\shared_mem.\ram.$procmux$14987 ($mux).
+Removed cell user_proj_example.$flatten\softshell.\shared_mem.\ram.$procmux$14985 ($mux).
+Removed cell user_proj_example.$flatten\softshell.\shared_mem.\ram.$procmux$14983 ($mux).
+Removed cell user_proj_example.$flatten\softshell.\shared_mem.\ram.$procmux$14977 ($mux).
+Removed cell user_proj_example.$flatten\softshell.\shared_mem.\ram.$procmux$14975 ($mux).
+Removed cell user_proj_example.$flatten\softshell.\shared_mem.\ram.$procmux$14973 ($mux).
+Removed cell user_proj_example.$flatten\softshell.\shared_mem.\ram.$procmux$14971 ($mux).
+Removed cell user_proj_example.$flatten\softshell.\shared_mem.\ram.$procmux$14965 ($mux).
+Removed cell user_proj_example.$flatten\softshell.\shared_mem.\ram.$procmux$14963 ($mux).
+Removed cell user_proj_example.$flatten\softshell.\shared_mem.\ram.$procmux$14961 ($mux).
+Removed cell user_proj_example.$flatten\softshell.\shared_mem.\ram.$procmux$14959 ($mux).
+Removed top 1 bits (of 7) from port B of cell user_proj_example.$flatten\softshell.\cpus[2].core.\flexio.$eq$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/pcpi_flexio.v:37$241 ($eq).
+Removed top 1 bits (of 7) from port B of cell user_proj_example.$flatten\softshell.\cpus[1].core.\flexio.$eq$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/pcpi_flexio.v:37$241 ($eq).
+Removed top 1 bits (of 7) from port B of cell user_proj_example.$flatten\softshell.\cpus[0].core.\flexio.$eq$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/pcpi_flexio.v:37$241 ($eq).
+Removed top 24 bits (of 32) from port B of cell user_proj_example.$flatten\softshell.$or$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/softshell_top.v:638$13 ($or).
+Removed top 2 bits (of 32) from port B of cell user_proj_example.$flatten\softshell.\interconnect.$xor$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/verilog-wishbone/rtl/wb_mux_5.v:157$445 ($xor).
+Removed top 2 bits (of 32) from port B of cell user_proj_example.$flatten\softshell.$eq$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/softshell_top.v:440$7 ($eq).
+Removed top 12 bits (of 32) from port B of cell user_proj_example.$flatten\softshell.$and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/softshell_top.v:368$3 ($and).
+Removed top 8 bits (of 32) from port Y of cell user_proj_example.$flatten\softshell.$and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/softshell_top.v:368$3 ($and).
+Removed top 8 bits (of 32) from port A of cell user_proj_example.$flatten\softshell.$and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/softshell_top.v:368$3 ($and).
+Removed top 7 bits (of 32) from port B of cell user_proj_example.$flatten\softshell.\flash.\spimemio.$ne$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/spimemio.v:216$619 ($ne).
+Removed top 29 bits (of 32) from wire user_proj_example.$flatten\softshell.\arbiter.\arb_inst.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/verilog-wishbone/rtl/arbiter.v:123$2753_Y.
+Removed top 29 bits (of 32) from wire user_proj_example.$flatten\softshell.\arbiter.\arb_inst.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/verilog-wishbone/rtl/arbiter.v:132$2755_Y.
+Removed top 16 bits (of 32) from wire user_proj_example.$flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$2\mem_rdata_word[31:0].
+Removed top 24 bits (of 32) from wire user_proj_example.$flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$3\mem_rdata_word[31:0].
+Removed top 32 bits (of 64) from wire user_proj_example.$flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1428$4679_Y.
+Removed top 32 bits (of 64) from wire user_proj_example.$flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1559$4733_Y.
+Removed top 27 bits (of 32) from wire user_proj_example.$flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:906$4383_Y.
+Removed top 2 bits (of 4) from wire user_proj_example.$flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$7346_Y.
+Removed top 28 bits (of 32) from wire user_proj_example.$flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$sub$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1421$4677_Y.
+Removed top 29 bits (of 32) from wire user_proj_example.$flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$ternary$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1312$4646_Y.
+Removed top 1 bits (of 7) from wire user_proj_example.$flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$ternary$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:491$4289_Y.
+Removed top 16 bits (of 32) from wire user_proj_example.$flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$2\mem_rdata_word[31:0].
+Removed top 24 bits (of 32) from wire user_proj_example.$flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$3\mem_rdata_word[31:0].
+Removed top 32 bits (of 64) from wire user_proj_example.$flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1428$3996_Y.
+Removed top 32 bits (of 64) from wire user_proj_example.$flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1559$4050_Y.
+Removed top 27 bits (of 32) from wire user_proj_example.$flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:906$3700_Y.
+Removed top 2 bits (of 4) from wire user_proj_example.$flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10992_Y.
+Removed top 28 bits (of 32) from wire user_proj_example.$flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$sub$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1421$3994_Y.
+Removed top 29 bits (of 32) from wire user_proj_example.$flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$ternary$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1312$3963_Y.
+Removed top 29 bits (of 32) from wire user_proj_example.$flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$ternary$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1541$4041_Y.
+Removed top 29 bits (of 32) from wire user_proj_example.$flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$ternary$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1547$4046_Y.
+Removed top 1 bits (of 7) from wire user_proj_example.$flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$ternary$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:491$3606_Y.
+Removed top 16 bits (of 32) from wire user_proj_example.$flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$2\mem_rdata_word[31:0].
+Removed top 24 bits (of 32) from wire user_proj_example.$flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$3\mem_rdata_word[31:0].
+Removed top 32 bits (of 64) from wire user_proj_example.$flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1428$3313_Y.
+Removed top 32 bits (of 64) from wire user_proj_example.$flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1559$3367_Y.
+Removed top 27 bits (of 32) from wire user_proj_example.$flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:906$3017_Y.
+Removed top 2 bits (of 4) from wire user_proj_example.$flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$13857_Y.
+Removed top 28 bits (of 32) from wire user_proj_example.$flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$sub$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1421$3311_Y.
+Removed top 29 bits (of 32) from wire user_proj_example.$flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$ternary$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1312$3280_Y.
+Removed top 29 bits (of 32) from wire user_proj_example.$flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$ternary$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1541$3358_Y.
+Removed top 29 bits (of 32) from wire user_proj_example.$flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$ternary$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1547$3363_Y.
+Removed top 1 bits (of 7) from wire user_proj_example.$flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$ternary$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:491$2923_Y.
+Removed top 7 bits (of 32) from wire user_proj_example.$flatten\softshell.\flash.\spimemio.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/spimemio.v:216$618_Y.
+Removed top 8 bits (of 32) from wire user_proj_example.$flatten\softshell.\flash.\spimemio.$ternary$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/spimemio.v:388$707_Y.
+Removed top 1 bits (of 8) from wire user_proj_example.$flatten\softshell.\flash.\spimemio.$ternary$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/spimemio.v:478$712_Y.
+Removed top 3 bits (of 4) from wire user_proj_example.$flatten\softshell.\flash.\spimemio.\xfer.$reduce_or$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/spimemio.v:633$726_Y.
+Removed top 28 bits (of 32) from wire user_proj_example.$flatten\softshell.\flash.\spimemio.\xfer.$ternary$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/spimemio.v:729$765_Y.
+Removed top 26 bits (of 32) from wire user_proj_example.$flatten\softshell.\pinmux.$procmux$16173_Y.
+Removed top 2 bits (of 10) from wire user_proj_example.$flatten\softshell.\uart0.\simpleuart.$procmux$9069_Y.
+Removed top 1 bits (of 10) from wire user_proj_example.$flatten\softshell.\uart0.\simpleuart.$procmux$9072_Y.
+
+23.11. Executing PEEPOPT pass (run peephole optimizers).
+
+23.12. Executing OPT_CLEAN pass (remove unused cells and wires).
+Finding unused cells or wires in module \user_proj_example..
+Removed 1 unused cells and 306 unused wires.
+<suppressed ~2 debug messages>
+
+23.13. Executing ALUMACC pass (create $alu and $macc cells).
+Extracting $alu and $macc cells in module user_proj_example:
+ creating $macc model for $flatten\softshell.\arbiter.\arb_inst.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/verilog-wishbone/rtl/arbiter.v:123$2753 ($add).
+ creating $macc model for $flatten\softshell.\arbiter.\arb_inst.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/verilog-wishbone/rtl/arbiter.v:132$2755 ($add).
+ creating $macc model for $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1235$4854 ($add).
+ creating $macc model for $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1312$4647 ($add).
+ creating $macc model for $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1428$4679 ($add).
+ creating $macc model for $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1547$4730 ($add).
+ creating $macc model for $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1559$4733 ($add).
+ creating $macc model for $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1564$4734 ($add).
+ creating $macc model for $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1801$4781 ($add).
+ creating $macc model for $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1864$4806 ($add).
+ creating $macc model for $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:382$4257 ($add).
+ creating $macc model for $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:906$4383 ($add).
+ creating $macc model for $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:910$4384 ($add).
+ creating $macc model for $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$sub$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1235$4853 ($sub).
+ creating $macc model for $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$sub$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1421$4677 ($sub).
+ creating $macc model for $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$sub$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1438$4684 ($sub).
+ creating $macc model for $flatten\softshell.\cpus[0].core.\flexio.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/pcpi_flexio.v:143$257 ($add).
+ creating $macc model for $flatten\softshell.\cpus[0].core.\flexio.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/pcpi_flexio.v:174$266 ($add).
+ creating $macc model for $flatten\softshell.\cpus[0].core.\flexio.\out_fifo.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:122$2000 ($add).
+ creating $macc model for $flatten\softshell.\cpus[0].core.\flexio.\out_fifo.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:144$2013 ($add).
+ creating $macc model for $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1235$4171 ($add).
+ creating $macc model for $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1312$3964 ($add).
+ creating $macc model for $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1428$3996 ($add).
+ creating $macc model for $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1547$4047 ($add).
+ creating $macc model for $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1559$4050 ($add).
+ creating $macc model for $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1564$4051 ($add).
+ creating $macc model for $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1801$4098 ($add).
+ creating $macc model for $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1864$4123 ($add).
+ creating $macc model for $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:382$3574 ($add).
+ creating $macc model for $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:906$3700 ($add).
+ creating $macc model for $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:910$3701 ($add).
+ creating $macc model for $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$sub$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1235$4170 ($sub).
+ creating $macc model for $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$sub$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1421$3994 ($sub).
+ creating $macc model for $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$sub$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1438$4001 ($sub).
+ creating $macc model for $flatten\softshell.\cpus[1].core.\flexio.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/pcpi_flexio.v:143$257 ($add).
+ creating $macc model for $flatten\softshell.\cpus[1].core.\flexio.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/pcpi_flexio.v:174$266 ($add).
+ creating $macc model for $flatten\softshell.\cpus[1].core.\flexio.\out_fifo.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:122$2000 ($add).
+ creating $macc model for $flatten\softshell.\cpus[1].core.\flexio.\out_fifo.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:144$2013 ($add).
+ creating $macc model for $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1235$3488 ($add).
+ creating $macc model for $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1312$3281 ($add).
+ creating $macc model for $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1428$3313 ($add).
+ creating $macc model for $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1547$3364 ($add).
+ creating $macc model for $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1559$3367 ($add).
+ creating $macc model for $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1564$3368 ($add).
+ creating $macc model for $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1801$3415 ($add).
+ creating $macc model for $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1864$3440 ($add).
+ creating $macc model for $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:382$2891 ($add).
+ creating $macc model for $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:906$3017 ($add).
+ creating $macc model for $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:910$3018 ($add).
+ creating $macc model for $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$sub$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1235$3487 ($sub).
+ creating $macc model for $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$sub$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1421$3311 ($sub).
+ creating $macc model for $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$sub$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1438$3318 ($sub).
+ creating $macc model for $flatten\softshell.\cpus[2].core.\flexio.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/pcpi_flexio.v:143$257 ($add).
+ creating $macc model for $flatten\softshell.\cpus[2].core.\flexio.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/pcpi_flexio.v:174$266 ($add).
+ creating $macc model for $flatten\softshell.\cpus[2].core.\flexio.\out_fifo.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:122$2000 ($add).
+ creating $macc model for $flatten\softshell.\cpus[2].core.\flexio.\out_fifo.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:144$2013 ($add).
+ creating $macc model for $flatten\softshell.\flash.\spimemio.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/spimemio.v:216$618 ($add).
+ creating $macc model for $flatten\softshell.\flash.\spimemio.\xfer.$sub$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/spimemio.v:633$727 ($sub).
+ creating $macc model for $flatten\softshell.\flash.\spimemio.\xfer.$sub$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/spimemio.v:653$734 ($sub).
+ creating $macc model for $flatten\softshell.\flash.\spimemio.\xfer.$sub$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/spimemio.v:686$746 ($sub).
+ creating $macc model for $flatten\softshell.\flash.\spimemio.\xfer.$sub$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/spimemio.v:716$758 ($sub).
+ creating $macc model for $flatten\softshell.\uart0.\simpleuart.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/simpleuart.v:159$589 ($add).
+ creating $macc model for $flatten\softshell.\uart0.\simpleuart.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/simpleuart.v:184$596 ($add).
+ creating $macc model for $flatten\softshell.\uart0.\simpleuart.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/simpleuart.v:197$599 ($add).
+ creating $macc model for $flatten\softshell.\uart0.\simpleuart.$sub$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/simpleuart.v:217$607 ($sub).
+ creating $alu model for $macc $flatten\softshell.\uart0.\simpleuart.$sub$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/simpleuart.v:217$607.
+ creating $alu model for $macc $flatten\softshell.\uart0.\simpleuart.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/simpleuart.v:197$599.
+ creating $alu model for $macc $flatten\softshell.\uart0.\simpleuart.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/simpleuart.v:184$596.
+ creating $alu model for $macc $flatten\softshell.\uart0.\simpleuart.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/simpleuart.v:159$589.
+ creating $alu model for $macc $flatten\softshell.\flash.\spimemio.\xfer.$sub$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/spimemio.v:716$758.
+ creating $alu model for $macc $flatten\softshell.\flash.\spimemio.\xfer.$sub$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/spimemio.v:686$746.
+ creating $alu model for $macc $flatten\softshell.\flash.\spimemio.\xfer.$sub$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/spimemio.v:653$734.
+ creating $alu model for $macc $flatten\softshell.\flash.\spimemio.\xfer.$sub$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/spimemio.v:633$727.
+ creating $alu model for $macc $flatten\softshell.\flash.\spimemio.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/spimemio.v:216$618.
+ creating $alu model for $macc $flatten\softshell.\cpus[2].core.\flexio.\out_fifo.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:144$2013.
+ creating $alu model for $macc $flatten\softshell.\cpus[2].core.\flexio.\out_fifo.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:122$2000.
+ creating $alu model for $macc $flatten\softshell.\cpus[2].core.\flexio.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/pcpi_flexio.v:174$266.
+ creating $alu model for $macc $flatten\softshell.\cpus[2].core.\flexio.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/pcpi_flexio.v:143$257.
+ creating $alu model for $macc $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$sub$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1438$3318.
+ creating $alu model for $macc $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$sub$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1421$3311.
+ creating $alu model for $macc $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$sub$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1235$3487.
+ creating $alu model for $macc $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:910$3018.
+ creating $alu model for $macc $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:906$3017.
+ creating $alu model for $macc $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:382$2891.
+ creating $alu model for $macc $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1864$3440.
+ creating $alu model for $macc $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1801$3415.
+ creating $alu model for $macc $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1564$3368.
+ creating $alu model for $macc $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1559$3367.
+ creating $alu model for $macc $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1547$3364.
+ creating $alu model for $macc $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1428$3313.
+ creating $alu model for $macc $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1312$3281.
+ creating $alu model for $macc $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1235$3488.
+ creating $alu model for $macc $flatten\softshell.\cpus[1].core.\flexio.\out_fifo.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:144$2013.
+ creating $alu model for $macc $flatten\softshell.\cpus[1].core.\flexio.\out_fifo.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:122$2000.
+ creating $alu model for $macc $flatten\softshell.\cpus[1].core.\flexio.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/pcpi_flexio.v:174$266.
+ creating $alu model for $macc $flatten\softshell.\cpus[1].core.\flexio.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/pcpi_flexio.v:143$257.
+ creating $alu model for $macc $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$sub$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1438$4001.
+ creating $alu model for $macc $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$sub$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1421$3994.
+ creating $alu model for $macc $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$sub$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1235$4170.
+ creating $alu model for $macc $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:910$3701.
+ creating $alu model for $macc $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:906$3700.
+ creating $alu model for $macc $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:382$3574.
+ creating $alu model for $macc $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1864$4123.
+ creating $alu model for $macc $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1801$4098.
+ creating $alu model for $macc $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1564$4051.
+ creating $alu model for $macc $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1559$4050.
+ creating $alu model for $macc $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1547$4047.
+ creating $alu model for $macc $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1428$3996.
+ creating $alu model for $macc $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1312$3964.
+ creating $alu model for $macc $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1235$4171.
+ creating $alu model for $macc $flatten\softshell.\cpus[0].core.\flexio.\out_fifo.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:144$2013.
+ creating $alu model for $macc $flatten\softshell.\cpus[0].core.\flexio.\out_fifo.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:122$2000.
+ creating $alu model for $macc $flatten\softshell.\cpus[0].core.\flexio.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/pcpi_flexio.v:174$266.
+ creating $alu model for $macc $flatten\softshell.\cpus[0].core.\flexio.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/pcpi_flexio.v:143$257.
+ creating $alu model for $macc $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$sub$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1438$4684.
+ creating $alu model for $macc $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$sub$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1421$4677.
+ creating $alu model for $macc $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$sub$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1235$4853.
+ creating $alu model for $macc $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:910$4384.
+ creating $alu model for $macc $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:906$4383.
+ creating $alu model for $macc $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:382$4257.
+ creating $alu model for $macc $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1864$4806.
+ creating $alu model for $macc $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1801$4781.
+ creating $alu model for $macc $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1564$4734.
+ creating $alu model for $macc $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1559$4733.
+ creating $alu model for $macc $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1547$4730.
+ creating $alu model for $macc $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1428$4679.
+ creating $alu model for $macc $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1312$4647.
+ creating $alu model for $macc $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1235$4854.
+ creating $alu model for $macc $flatten\softshell.\arbiter.\arb_inst.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/verilog-wishbone/rtl/arbiter.v:132$2755.
+ creating $alu model for $macc $flatten\softshell.\arbiter.\arb_inst.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/verilog-wishbone/rtl/arbiter.v:123$2753.
+ creating $alu model for $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$lt$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1237$4857 ($lt): new $alu
+ creating $alu model for $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$lt$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1238$4858 ($lt): new $alu
+ creating $alu model for $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$lt$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1237$4174 ($lt): new $alu
+ creating $alu model for $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$lt$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1238$4175 ($lt): new $alu
+ creating $alu model for $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$lt$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1237$3491 ($lt): new $alu
+ creating $alu model for $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$lt$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1238$3492 ($lt): new $alu
+ creating $alu model for $flatten\softshell.\uart0.\simpleuart.$gt$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/simpleuart.v:169$593 ($gt): new $alu
+ creating $alu model for $flatten\softshell.\uart0.\simpleuart.$gt$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/simpleuart.v:175$594 ($gt): new $alu
+ creating $alu model for $flatten\softshell.\uart0.\simpleuart.$gt$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/simpleuart.v:215$605 ($gt): new $alu
+ creating $alu model for $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$eq$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1236$4856 ($eq): merged with $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$lt$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1238$4858.
+ creating $alu model for $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$eq$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1236$4173 ($eq): merged with $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$lt$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1238$4175.
+ creating $alu model for $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$eq$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1236$3490 ($eq): merged with $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$lt$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1238$3492.
+ creating $alu cell for $flatten\softshell.\uart0.\simpleuart.$gt$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/simpleuart.v:215$605: $auto$alumacc.cc:485:replace_alu$21114
+ creating $alu cell for $flatten\softshell.\uart0.\simpleuart.$gt$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/simpleuart.v:175$594: $auto$alumacc.cc:485:replace_alu$21125
+ creating $alu cell for $flatten\softshell.\uart0.\simpleuart.$gt$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/simpleuart.v:169$593: $auto$alumacc.cc:485:replace_alu$21130
+ creating $alu cell for $flatten\softshell.\arbiter.\arb_inst.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/verilog-wishbone/rtl/arbiter.v:123$2753: $auto$alumacc.cc:485:replace_alu$21135
+ creating $alu cell for $flatten\softshell.\arbiter.\arb_inst.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/verilog-wishbone/rtl/arbiter.v:132$2755: $auto$alumacc.cc:485:replace_alu$21138
+ creating $alu cell for $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$lt$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1238$4858, $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$eq$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1236$4856: $auto$alumacc.cc:485:replace_alu$21141
+ creating $alu cell for $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$lt$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1237$4857: $auto$alumacc.cc:485:replace_alu$21152
+ creating $alu cell for $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1235$4854: $auto$alumacc.cc:485:replace_alu$21165
+ creating $alu cell for $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1312$4647: $auto$alumacc.cc:485:replace_alu$21168
+ creating $alu cell for $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1428$4679: $auto$alumacc.cc:485:replace_alu$21171
+ creating $alu cell for $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1547$4730: $auto$alumacc.cc:485:replace_alu$21174
+ creating $alu cell for $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1559$4733: $auto$alumacc.cc:485:replace_alu$21177
+ creating $alu cell for $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1564$4734: $auto$alumacc.cc:485:replace_alu$21180
+ creating $alu cell for $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1801$4781: $auto$alumacc.cc:485:replace_alu$21183
+ creating $alu cell for $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1864$4806: $auto$alumacc.cc:485:replace_alu$21186
+ creating $alu cell for $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:382$4257: $auto$alumacc.cc:485:replace_alu$21189
+ creating $alu cell for $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:906$4383: $auto$alumacc.cc:485:replace_alu$21192
+ creating $alu cell for $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:910$4384: $auto$alumacc.cc:485:replace_alu$21195
+ creating $alu cell for $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$sub$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1235$4853: $auto$alumacc.cc:485:replace_alu$21198
+ creating $alu cell for $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$sub$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1421$4677: $auto$alumacc.cc:485:replace_alu$21201
+ creating $alu cell for $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$sub$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1438$4684: $auto$alumacc.cc:485:replace_alu$21204
+ creating $alu cell for $flatten\softshell.\cpus[0].core.\flexio.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/pcpi_flexio.v:143$257: $auto$alumacc.cc:485:replace_alu$21207
+ creating $alu cell for $flatten\softshell.\cpus[0].core.\flexio.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/pcpi_flexio.v:174$266: $auto$alumacc.cc:485:replace_alu$21210
+ creating $alu cell for $flatten\softshell.\cpus[0].core.\flexio.\out_fifo.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:122$2000: $auto$alumacc.cc:485:replace_alu$21213
+ creating $alu cell for $flatten\softshell.\cpus[0].core.\flexio.\out_fifo.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:144$2013: $auto$alumacc.cc:485:replace_alu$21216
+ creating $alu cell for $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$lt$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1238$4175, $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$eq$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1236$4173: $auto$alumacc.cc:485:replace_alu$21219
+ creating $alu cell for $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$lt$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1237$4174: $auto$alumacc.cc:485:replace_alu$21230
+ creating $alu cell for $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1235$4171: $auto$alumacc.cc:485:replace_alu$21243
+ creating $alu cell for $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1312$3964: $auto$alumacc.cc:485:replace_alu$21246
+ creating $alu cell for $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1428$3996: $auto$alumacc.cc:485:replace_alu$21249
+ creating $alu cell for $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1547$4047: $auto$alumacc.cc:485:replace_alu$21252
+ creating $alu cell for $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1559$4050: $auto$alumacc.cc:485:replace_alu$21255
+ creating $alu cell for $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1564$4051: $auto$alumacc.cc:485:replace_alu$21258
+ creating $alu cell for $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1801$4098: $auto$alumacc.cc:485:replace_alu$21261
+ creating $alu cell for $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1864$4123: $auto$alumacc.cc:485:replace_alu$21264
+ creating $alu cell for $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:382$3574: $auto$alumacc.cc:485:replace_alu$21267
+ creating $alu cell for $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:906$3700: $auto$alumacc.cc:485:replace_alu$21270
+ creating $alu cell for $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:910$3701: $auto$alumacc.cc:485:replace_alu$21273
+ creating $alu cell for $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$sub$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1235$4170: $auto$alumacc.cc:485:replace_alu$21276
+ creating $alu cell for $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$sub$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1421$3994: $auto$alumacc.cc:485:replace_alu$21279
+ creating $alu cell for $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$sub$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1438$4001: $auto$alumacc.cc:485:replace_alu$21282
+ creating $alu cell for $flatten\softshell.\cpus[1].core.\flexio.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/pcpi_flexio.v:143$257: $auto$alumacc.cc:485:replace_alu$21285
+ creating $alu cell for $flatten\softshell.\cpus[1].core.\flexio.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/pcpi_flexio.v:174$266: $auto$alumacc.cc:485:replace_alu$21288
+ creating $alu cell for $flatten\softshell.\cpus[1].core.\flexio.\out_fifo.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:122$2000: $auto$alumacc.cc:485:replace_alu$21291
+ creating $alu cell for $flatten\softshell.\cpus[1].core.\flexio.\out_fifo.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:144$2013: $auto$alumacc.cc:485:replace_alu$21294
+ creating $alu cell for $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$lt$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1238$3492, $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$eq$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1236$3490: $auto$alumacc.cc:485:replace_alu$21297
+ creating $alu cell for $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$lt$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1237$3491: $auto$alumacc.cc:485:replace_alu$21308
+ creating $alu cell for $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1235$3488: $auto$alumacc.cc:485:replace_alu$21321
+ creating $alu cell for $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1312$3281: $auto$alumacc.cc:485:replace_alu$21324
+ creating $alu cell for $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1428$3313: $auto$alumacc.cc:485:replace_alu$21327
+ creating $alu cell for $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1547$3364: $auto$alumacc.cc:485:replace_alu$21330
+ creating $alu cell for $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1559$3367: $auto$alumacc.cc:485:replace_alu$21333
+ creating $alu cell for $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1564$3368: $auto$alumacc.cc:485:replace_alu$21336
+ creating $alu cell for $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1801$3415: $auto$alumacc.cc:485:replace_alu$21339
+ creating $alu cell for $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1864$3440: $auto$alumacc.cc:485:replace_alu$21342
+ creating $alu cell for $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:382$2891: $auto$alumacc.cc:485:replace_alu$21345
+ creating $alu cell for $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:906$3017: $auto$alumacc.cc:485:replace_alu$21348
+ creating $alu cell for $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:910$3018: $auto$alumacc.cc:485:replace_alu$21351
+ creating $alu cell for $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$sub$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1235$3487: $auto$alumacc.cc:485:replace_alu$21354
+ creating $alu cell for $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$sub$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1421$3311: $auto$alumacc.cc:485:replace_alu$21357
+ creating $alu cell for $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$sub$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1438$3318: $auto$alumacc.cc:485:replace_alu$21360
+ creating $alu cell for $flatten\softshell.\cpus[2].core.\flexio.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/pcpi_flexio.v:143$257: $auto$alumacc.cc:485:replace_alu$21363
+ creating $alu cell for $flatten\softshell.\cpus[2].core.\flexio.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/pcpi_flexio.v:174$266: $auto$alumacc.cc:485:replace_alu$21366
+ creating $alu cell for $flatten\softshell.\cpus[2].core.\flexio.\out_fifo.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:122$2000: $auto$alumacc.cc:485:replace_alu$21369
+ creating $alu cell for $flatten\softshell.\cpus[2].core.\flexio.\out_fifo.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:144$2013: $auto$alumacc.cc:485:replace_alu$21372
+ creating $alu cell for $flatten\softshell.\flash.\spimemio.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/spimemio.v:216$618: $auto$alumacc.cc:485:replace_alu$21375
+ creating $alu cell for $flatten\softshell.\flash.\spimemio.\xfer.$sub$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/spimemio.v:633$727: $auto$alumacc.cc:485:replace_alu$21378
+ creating $alu cell for $flatten\softshell.\flash.\spimemio.\xfer.$sub$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/spimemio.v:653$734: $auto$alumacc.cc:485:replace_alu$21381
+ creating $alu cell for $flatten\softshell.\flash.\spimemio.\xfer.$sub$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/spimemio.v:686$746: $auto$alumacc.cc:485:replace_alu$21384
+ creating $alu cell for $flatten\softshell.\flash.\spimemio.\xfer.$sub$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/spimemio.v:716$758: $auto$alumacc.cc:485:replace_alu$21387
+ creating $alu cell for $flatten\softshell.\uart0.\simpleuart.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/simpleuart.v:159$589: $auto$alumacc.cc:485:replace_alu$21390
+ creating $alu cell for $flatten\softshell.\uart0.\simpleuart.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/simpleuart.v:184$596: $auto$alumacc.cc:485:replace_alu$21393
+ creating $alu cell for $flatten\softshell.\uart0.\simpleuart.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/simpleuart.v:197$599: $auto$alumacc.cc:485:replace_alu$21396
+ creating $alu cell for $flatten\softshell.\uart0.\simpleuart.$sub$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/simpleuart.v:217$607: $auto$alumacc.cc:485:replace_alu$21399
+ created 74 $alu and 0 $macc cells.
+
+23.14. Executing SHARE pass (SAT-based resource sharing).
+Found 15 cells in module user_proj_example that may be considered for resource sharing.
+ Analyzing resource sharing options for $flatten\softshell.\cpus[2].core.\flexio.\out_fifo.$memrd$\mem$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:160$2021 ($memrd):
+ Found 1 activation_patterns using ctrl signal $flatten\softshell.\cpus[2].core.\flexio.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/pcpi_flexio.v:157$263_Y.
+ No candidates found.
+ Analyzing resource sharing options for $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.\cpuregs.$memrd$\regs$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/rv_core.v:289$31 ($memrd):
+ Found 1 activation_patterns using ctrl signal { $auto$opt_reduce.cc:134:opt_mux$17083 $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$12829_CTRL $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$reduce_bool$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1386$3295_Y \softshell.cpus[2].core.cpu.picorv32_core.is_lui_auipc_jal }.
+ Found 1 candidates: $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.\cpuregs.$memrd$\regs$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/rv_core.v:288$30
+ Analyzing resource sharing with $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.\cpuregs.$memrd$\regs$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/rv_core.v:288$30 ($memrd):
+ Found 1 activation_patterns using ctrl signal $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$reduce_bool$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1385$3293_Y.
+ Activation pattern for cell $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.\cpuregs.$memrd$\regs$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/rv_core.v:289$31: { $auto$opt_reduce.cc:134:opt_mux$17083 $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$12829_CTRL $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$reduce_bool$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1386$3295_Y \softshell.cpus[2].core.cpu.picorv32_core.is_lui_auipc_jal } = 4'0010
+ Activation pattern for cell $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.\cpuregs.$memrd$\regs$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/rv_core.v:288$30: $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$reduce_bool$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1385$3293_Y = 1'1
+ Adding exclusive control bits: \softshell.cpus[2].core.cpu.picorv32_core.instr_timer vs. \softshell.cpus[2].core.cpu.picorv32_core.instr_trap
+ Adding exclusive control bits: \softshell.cpus[2].core.cpu.picorv32_core.instr_maskirq vs. \softshell.cpus[2].core.cpu.picorv32_core.instr_timer
+ Adding exclusive control bits: \softshell.cpus[2].core.cpu.picorv32_core.instr_maskirq vs. \softshell.cpus[2].core.cpu.picorv32_core.instr_trap
+ Adding exclusive control bits: \softshell.cpus[2].core.cpu.picorv32_core.instr_retirq vs. \softshell.cpus[2].core.cpu.picorv32_core.instr_timer
+ Adding exclusive control bits: \softshell.cpus[2].core.cpu.picorv32_core.instr_retirq vs. \softshell.cpus[2].core.cpu.picorv32_core.instr_maskirq
+ Adding exclusive control bits: \softshell.cpus[2].core.cpu.picorv32_core.instr_retirq vs. \softshell.cpus[2].core.cpu.picorv32_core.instr_trap
+ Adding exclusive control bits: \softshell.cpus[2].core.cpu.picorv32_core.instr_rdcycle vs. \softshell.cpus[2].core.cpu.picorv32_core.instr_rdinstr
+ Adding exclusive control bits: \softshell.cpus[2].core.cpu.picorv32_core.instr_trap vs. $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1691$3392_Y
+ Adding exclusive control bits: $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$12829_CTRL vs. $auto$opt_reduce.cc:134:opt_mux$17083
+ Adding exclusive control bits: \softshell.cpus[2].core.cpu.picorv32_core.is_lui_auipc_jal vs. $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$12829_CTRL
+ Adding exclusive control bits: \softshell.cpus[2].core.cpu.picorv32_core.is_lui_auipc_jal vs. $auto$opt_reduce.cc:134:opt_mux$17083
+ Adding exclusive control bits: \softshell.cpus[2].core.cpu.picorv32_core.instr_bge vs. \softshell.cpus[2].core.cpu.picorv32_core.instr_bgeu
+ Adding exclusive control bits: \softshell.cpus[2].core.cpu.picorv32_core.instr_bne vs. \softshell.cpus[2].core.cpu.picorv32_core.instr_bgeu
+ Adding exclusive control bits: \softshell.cpus[2].core.cpu.picorv32_core.instr_bne vs. \softshell.cpus[2].core.cpu.picorv32_core.instr_bge
+ Adding exclusive control bits: \softshell.cpus[2].core.cpu.picorv32_core.instr_beq vs. \softshell.cpus[2].core.cpu.picorv32_core.instr_bgeu
+ Adding exclusive control bits: \softshell.cpus[2].core.cpu.picorv32_core.instr_beq vs. \softshell.cpus[2].core.cpu.picorv32_core.instr_bge
+ Adding exclusive control bits: \softshell.cpus[2].core.cpu.picorv32_core.instr_beq vs. \softshell.cpus[2].core.cpu.picorv32_core.instr_bne
+ Size of SAT problem: 7 cells, 126 variables, 263 clauses
+ According to the SAT solver this pair of cells can not be shared.
+ Model from SAT solver: { $auto$opt_reduce.cc:134:opt_mux$17083 $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$12829_CTRL $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$reduce_bool$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1386$3295_Y $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$reduce_bool$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1385$3293_Y \softshell.cpus[2].core.cpu.picorv32_core.is_lui_auipc_jal } = 5'00110
+ Analyzing resource sharing options for $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.\cpuregs.$memrd$\regs$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/rv_core.v:288$30 ($memrd):
+ Found 1 activation_patterns using ctrl signal $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$reduce_bool$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1385$3293_Y.
+ No candidates found.
+ Analyzing resource sharing options for $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$sshr$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1240$3496 ($sshr):
+ Found 1 activation_patterns using ctrl signal $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1277$3271_Y.
+ Found 2 candidates: $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$sshr$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1240$4179 $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$sshr$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1240$4862
+ Analyzing resource sharing with $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$sshr$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1240$4179 ($sshr):
+ Found 1 activation_patterns using ctrl signal $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1277$3954_Y.
+ Activation pattern for cell $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$sshr$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1240$3496: $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1277$3271_Y = 1'1
+ Activation pattern for cell $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$sshr$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1240$4179: $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1277$3954_Y = 1'1
+ Size of SAT problem: 6 cells, 45 variables, 97 clauses
+ According to the SAT solver this pair of cells can not be shared.
+ Model from SAT solver: { $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1277$3954_Y $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1277$3271_Y } = 2'11
+ Analyzing resource sharing with $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$sshr$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1240$4862 ($sshr):
+ Found 1 activation_patterns using ctrl signal $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1277$4637_Y.
+ Activation pattern for cell $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$sshr$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1240$3496: $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1277$3271_Y = 1'1
+ Activation pattern for cell $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$sshr$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1240$4862: $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1277$4637_Y = 1'1
+ Size of SAT problem: 6 cells, 45 variables, 97 clauses
+ According to the SAT solver this pair of cells can not be shared.
+ Model from SAT solver: { $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1277$4637_Y $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1277$3271_Y } = 2'11
+ Analyzing resource sharing options for $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$shl$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1239$3493 ($shl):
+ Found 1 activation_patterns using ctrl signal $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1275$3267_Y.
+ Found 2 candidates: $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$shl$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1239$4176 $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$shl$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1239$4859
+ Analyzing resource sharing with $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$shl$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1239$4176 ($shl):
+ Found 1 activation_patterns using ctrl signal $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1275$3950_Y.
+ Activation pattern for cell $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$shl$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1239$3493: $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1275$3267_Y = 1'1
+ Activation pattern for cell $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$shl$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1239$4176: $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1275$3950_Y = 1'1
+ Size of SAT problem: 2 cells, 21 variables, 45 clauses
+ According to the SAT solver this pair of cells can not be shared.
+ Model from SAT solver: { $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1275$3950_Y $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1275$3267_Y } = 2'11
+ Analyzing resource sharing with $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$shl$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1239$4859 ($shl):
+ Found 1 activation_patterns using ctrl signal $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1275$4633_Y.
+ Activation pattern for cell $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$shl$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1239$3493: $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1275$3267_Y = 1'1
+ Activation pattern for cell $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$shl$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1239$4859: $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1275$4633_Y = 1'1
+ Size of SAT problem: 2 cells, 21 variables, 45 clauses
+ According to the SAT solver this pair of cells can not be shared.
+ Model from SAT solver: { $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1275$4633_Y $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1275$3267_Y } = 2'11
+ Analyzing resource sharing options for $flatten\softshell.\cpus[1].core.\flexio.\out_fifo.$memrd$\mem$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:160$2021 ($memrd):
+ Found 1 activation_patterns using ctrl signal $flatten\softshell.\cpus[1].core.\flexio.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/pcpi_flexio.v:157$263_Y.
+ No candidates found.
+ Analyzing resource sharing options for $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.\cpuregs.$memrd$\regs$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/rv_core.v:289$31 ($memrd):
+ Found 1 activation_patterns using ctrl signal { $auto$opt_reduce.cc:134:opt_mux$16941 $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10258_CTRL $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$reduce_bool$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1386$3978_Y \softshell.cpus[1].core.cpu.picorv32_core.is_lui_auipc_jal }.
+ Found 1 candidates: $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.\cpuregs.$memrd$\regs$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/rv_core.v:288$30
+ Analyzing resource sharing with $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.\cpuregs.$memrd$\regs$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/rv_core.v:288$30 ($memrd):
+ Found 1 activation_patterns using ctrl signal $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$reduce_bool$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1385$3976_Y.
+ Activation pattern for cell $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.\cpuregs.$memrd$\regs$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/rv_core.v:289$31: { $auto$opt_reduce.cc:134:opt_mux$16941 $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10258_CTRL $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$reduce_bool$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1386$3978_Y \softshell.cpus[1].core.cpu.picorv32_core.is_lui_auipc_jal } = 4'0010
+ Activation pattern for cell $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.\cpuregs.$memrd$\regs$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/rv_core.v:288$30: $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$reduce_bool$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1385$3976_Y = 1'1
+ Adding exclusive control bits: \softshell.cpus[1].core.cpu.picorv32_core.instr_trap vs. $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1691$4075_Y
+ Adding exclusive control bits: $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10258_CTRL vs. $auto$opt_reduce.cc:134:opt_mux$16941
+ Adding exclusive control bits: \softshell.cpus[1].core.cpu.picorv32_core.is_lui_auipc_jal vs. $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10258_CTRL
+ Adding exclusive control bits: \softshell.cpus[1].core.cpu.picorv32_core.is_lui_auipc_jal vs. $auto$opt_reduce.cc:134:opt_mux$16941
+ Adding exclusive control bits: \softshell.cpus[1].core.cpu.picorv32_core.instr_bge vs. \softshell.cpus[1].core.cpu.picorv32_core.instr_bgeu
+ Adding exclusive control bits: \softshell.cpus[1].core.cpu.picorv32_core.instr_bne vs. \softshell.cpus[1].core.cpu.picorv32_core.instr_bgeu
+ Adding exclusive control bits: \softshell.cpus[1].core.cpu.picorv32_core.instr_bne vs. \softshell.cpus[1].core.cpu.picorv32_core.instr_bge
+ Adding exclusive control bits: \softshell.cpus[1].core.cpu.picorv32_core.instr_beq vs. \softshell.cpus[1].core.cpu.picorv32_core.instr_bgeu
+ Adding exclusive control bits: \softshell.cpus[1].core.cpu.picorv32_core.instr_beq vs. \softshell.cpus[1].core.cpu.picorv32_core.instr_bge
+ Adding exclusive control bits: \softshell.cpus[1].core.cpu.picorv32_core.instr_beq vs. \softshell.cpus[1].core.cpu.picorv32_core.instr_bne
+ Adding exclusive control bits: \softshell.cpus[1].core.cpu.picorv32_core.instr_timer vs. \softshell.cpus[1].core.cpu.picorv32_core.instr_trap
+ Adding exclusive control bits: \softshell.cpus[1].core.cpu.picorv32_core.instr_maskirq vs. \softshell.cpus[1].core.cpu.picorv32_core.instr_timer
+ Adding exclusive control bits: \softshell.cpus[1].core.cpu.picorv32_core.instr_maskirq vs. \softshell.cpus[1].core.cpu.picorv32_core.instr_trap
+ Adding exclusive control bits: \softshell.cpus[1].core.cpu.picorv32_core.instr_retirq vs. \softshell.cpus[1].core.cpu.picorv32_core.instr_timer
+ Adding exclusive control bits: \softshell.cpus[1].core.cpu.picorv32_core.instr_retirq vs. \softshell.cpus[1].core.cpu.picorv32_core.instr_maskirq
+ Adding exclusive control bits: \softshell.cpus[1].core.cpu.picorv32_core.instr_retirq vs. \softshell.cpus[1].core.cpu.picorv32_core.instr_trap
+ Adding exclusive control bits: \softshell.cpus[1].core.cpu.picorv32_core.instr_rdcycle vs. \softshell.cpus[1].core.cpu.picorv32_core.instr_rdinstr
+ Size of SAT problem: 7 cells, 126 variables, 263 clauses
+ According to the SAT solver this pair of cells can not be shared.
+ Model from SAT solver: { $auto$opt_reduce.cc:134:opt_mux$16941 $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10258_CTRL $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$reduce_bool$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1386$3978_Y $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$reduce_bool$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1385$3976_Y \softshell.cpus[1].core.cpu.picorv32_core.is_lui_auipc_jal } = 5'00110
+ Analyzing resource sharing options for $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.\cpuregs.$memrd$\regs$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/rv_core.v:288$30 ($memrd):
+ Found 1 activation_patterns using ctrl signal $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$reduce_bool$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1385$3976_Y.
+ No candidates found.
+ Analyzing resource sharing options for $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$sshr$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1240$4179 ($sshr):
+ Found 1 activation_patterns using ctrl signal $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1277$3954_Y.
+ Found 1 candidates: $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$sshr$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1240$4862
+ Analyzing resource sharing with $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$sshr$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1240$4862 ($sshr):
+ Found 1 activation_patterns using ctrl signal $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1277$4637_Y.
+ Activation pattern for cell $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$sshr$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1240$4179: $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1277$3954_Y = 1'1
+ Activation pattern for cell $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$sshr$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1240$4862: $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1277$4637_Y = 1'1
+ Size of SAT problem: 6 cells, 45 variables, 97 clauses
+ According to the SAT solver this pair of cells can not be shared.
+ Model from SAT solver: { $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1277$4637_Y $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1277$3954_Y } = 2'11
+ Analyzing resource sharing options for $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$shl$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1239$4176 ($shl):
+ Found 1 activation_patterns using ctrl signal $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1275$3950_Y.
+ Found 1 candidates: $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$shl$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1239$4859
+ Analyzing resource sharing with $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$shl$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1239$4859 ($shl):
+ Found 1 activation_patterns using ctrl signal $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1275$4633_Y.
+ Activation pattern for cell $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$shl$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1239$4176: $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1275$3950_Y = 1'1
+ Activation pattern for cell $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$shl$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1239$4859: $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1275$4633_Y = 1'1
+ Size of SAT problem: 2 cells, 21 variables, 45 clauses
+ According to the SAT solver this pair of cells can not be shared.
+ Model from SAT solver: { $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1275$4633_Y $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1275$3950_Y } = 2'11
+ Analyzing resource sharing options for $flatten\softshell.\cpus[0].core.\flexio.\out_fifo.$memrd$\mem$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:160$2021 ($memrd):
+ Found 1 activation_patterns using ctrl signal $flatten\softshell.\cpus[0].core.\flexio.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/pcpi_flexio.v:157$263_Y.
+ No candidates found.
+ Analyzing resource sharing options for $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.\cpuregs.$memrd$\regs$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/rv_core.v:289$31 ($memrd):
+ Found 1 activation_patterns using ctrl signal { $auto$opt_reduce.cc:134:opt_mux$17067 $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$6318_CTRL $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$reduce_bool$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1386$4661_Y \softshell.cpus[0].core.cpu.picorv32_core.is_lui_auipc_jal }.
+ Found 1 candidates: $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.\cpuregs.$memrd$\regs$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/rv_core.v:288$30
+ Analyzing resource sharing with $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.\cpuregs.$memrd$\regs$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/rv_core.v:288$30 ($memrd):
+ Found 1 activation_patterns using ctrl signal $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$reduce_bool$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1385$4659_Y.
+ Activation pattern for cell $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.\cpuregs.$memrd$\regs$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/rv_core.v:289$31: { $auto$opt_reduce.cc:134:opt_mux$17067 $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$6318_CTRL $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$reduce_bool$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1386$4661_Y \softshell.cpus[0].core.cpu.picorv32_core.is_lui_auipc_jal } = 4'0010
+ Activation pattern for cell $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.\cpuregs.$memrd$\regs$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/rv_core.v:288$30: $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$reduce_bool$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1385$4659_Y = 1'1
+ Adding exclusive control bits: \softshell.cpus[0].core.cpu.picorv32_core.instr_timer vs. \softshell.cpus[0].core.cpu.picorv32_core.instr_trap
+ Adding exclusive control bits: \softshell.cpus[0].core.cpu.picorv32_core.instr_maskirq vs. \softshell.cpus[0].core.cpu.picorv32_core.instr_timer
+ Adding exclusive control bits: \softshell.cpus[0].core.cpu.picorv32_core.instr_maskirq vs. \softshell.cpus[0].core.cpu.picorv32_core.instr_trap
+ Adding exclusive control bits: \softshell.cpus[0].core.cpu.picorv32_core.instr_retirq vs. \softshell.cpus[0].core.cpu.picorv32_core.instr_timer
+ Adding exclusive control bits: \softshell.cpus[0].core.cpu.picorv32_core.instr_retirq vs. \softshell.cpus[0].core.cpu.picorv32_core.instr_maskirq
+ Adding exclusive control bits: \softshell.cpus[0].core.cpu.picorv32_core.instr_retirq vs. \softshell.cpus[0].core.cpu.picorv32_core.instr_trap
+ Adding exclusive control bits: \softshell.cpus[0].core.cpu.picorv32_core.instr_rdcycle vs. \softshell.cpus[0].core.cpu.picorv32_core.instr_rdinstr
+ Adding exclusive control bits: \softshell.cpus[0].core.cpu.picorv32_core.instr_trap vs. $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1691$4758_Y
+ Adding exclusive control bits: $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$6318_CTRL vs. $auto$opt_reduce.cc:134:opt_mux$17067
+ Adding exclusive control bits: \softshell.cpus[0].core.cpu.picorv32_core.is_lui_auipc_jal vs. $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$6318_CTRL
+ Adding exclusive control bits: \softshell.cpus[0].core.cpu.picorv32_core.is_lui_auipc_jal vs. $auto$opt_reduce.cc:134:opt_mux$17067
+ Adding exclusive control bits: \softshell.cpus[0].core.cpu.picorv32_core.instr_bge vs. \softshell.cpus[0].core.cpu.picorv32_core.instr_bgeu
+ Adding exclusive control bits: \softshell.cpus[0].core.cpu.picorv32_core.instr_bne vs. \softshell.cpus[0].core.cpu.picorv32_core.instr_bgeu
+ Adding exclusive control bits: \softshell.cpus[0].core.cpu.picorv32_core.instr_bne vs. \softshell.cpus[0].core.cpu.picorv32_core.instr_bge
+ Adding exclusive control bits: \softshell.cpus[0].core.cpu.picorv32_core.instr_beq vs. \softshell.cpus[0].core.cpu.picorv32_core.instr_bgeu
+ Adding exclusive control bits: \softshell.cpus[0].core.cpu.picorv32_core.instr_beq vs. \softshell.cpus[0].core.cpu.picorv32_core.instr_bge
+ Adding exclusive control bits: \softshell.cpus[0].core.cpu.picorv32_core.instr_beq vs. \softshell.cpus[0].core.cpu.picorv32_core.instr_bne
+ Size of SAT problem: 7 cells, 126 variables, 263 clauses
+ According to the SAT solver this pair of cells can not be shared.
+ Model from SAT solver: { $auto$opt_reduce.cc:134:opt_mux$17067 $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$6318_CTRL $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$reduce_bool$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1386$4661_Y $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$reduce_bool$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1385$4659_Y \softshell.cpus[0].core.cpu.picorv32_core.is_lui_auipc_jal } = 5'00110
+ Analyzing resource sharing options for $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.\cpuregs.$memrd$\regs$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/rv_core.v:288$30 ($memrd):
+ Found 1 activation_patterns using ctrl signal $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$reduce_bool$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1385$4659_Y.
+ No candidates found.
+ Analyzing resource sharing options for $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$sshr$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1240$4862 ($sshr):
+ Found 1 activation_patterns using ctrl signal $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1277$4637_Y.
+ No candidates found.
+ Analyzing resource sharing options for $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$shl$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1239$4859 ($shl):
+ Found 1 activation_patterns using ctrl signal $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1275$4633_Y.
+ No candidates found.
+
+23.15. Executing OPT pass (performing simple optimizations).
+
+23.15.1. Executing OPT_EXPR pass (perform const folding).
+Optimizing module user_proj_example.
+<suppressed ~9 debug messages>
+
+23.15.2. Executing OPT_MERGE pass (detect identical cells).
+Finding identical cells in module `\user_proj_example'.
+<suppressed ~39 debug messages>
+Removed a total of 13 cells.
+
+23.15.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
+Running muxtree optimizer on module \user_proj_example..
+ Creating internal representation of mux trees.
+ Evaluating internal representation of mux trees.
+ Analyzing evaluation results.
+Removed 0 multiplexer ports.
+<suppressed ~423 debug messages>
+
+23.15.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
+ Optimizing cells in module \user_proj_example.
+ New ctrl vector for $pmux cell $flatten\softshell.\cpus[0].core.\cpu.$procmux$5106: { \softshell.cpus[0].core.cpu.state [2] $auto$opt_reduce.cc:134:opt_mux$21403 }
+ New ctrl vector for $pmux cell $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$6811: { $auto$opt_reduce.cc:134:opt_mux$17041 $auto$opt_reduce.cc:134:opt_mux$21405 $auto$opt_reduce.cc:134:opt_mux$17047 }
+ New ctrl vector for $pmux cell $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$7017: { \softshell.cpus[0].core.cpu.picorv32_core.cpu_state [2] $auto$opt_reduce.cc:134:opt_mux$21407 }
+ New ctrl vector for $pmux cell $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$8039: { $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$logic_not$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:379$4237_Y $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$8002_CMP $auto$opt_reduce.cc:134:opt_mux$21409 }
+ New ctrl vector for $pmux cell $flatten\softshell.\cpus[1].core.\cpu.$procmux$5213: { \softshell.cpus[1].core.cpu.state [2] $auto$opt_reduce.cc:134:opt_mux$21411 }
+ New ctrl vector for $pmux cell $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10457: { $auto$opt_reduce.cc:134:opt_mux$16931 $auto$opt_reduce.cc:134:opt_mux$21413 $auto$opt_reduce.cc:134:opt_mux$16933 }
+ New ctrl vector for $pmux cell $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10663: { \softshell.cpus[1].core.cpu.picorv32_core.cpu_state [2] $auto$opt_reduce.cc:134:opt_mux$21415 }
+ New ctrl vector for $pmux cell $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$11685: { $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$logic_not$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:379$3554_Y $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$11648_CMP $auto$opt_reduce.cc:134:opt_mux$21417 }
+ New ctrl vector for $pmux cell $flatten\softshell.\cpus[2].core.\cpu.$procmux$5320: { \softshell.cpus[2].core.cpu.state [2] $auto$opt_reduce.cc:134:opt_mux$21419 }
+ New ctrl vector for $pmux cell $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$13322: { $auto$opt_reduce.cc:134:opt_mux$17071 $auto$opt_reduce.cc:134:opt_mux$21421 $auto$opt_reduce.cc:134:opt_mux$17073 }
+ New ctrl vector for $pmux cell $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$13528: { \softshell.cpus[2].core.cpu.picorv32_core.cpu_state [2] $auto$opt_reduce.cc:134:opt_mux$21423 }
+ New ctrl vector for $pmux cell $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$14550: { $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$logic_not$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:379$2871_Y $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$14513_CMP $auto$opt_reduce.cc:134:opt_mux$21425 }
+ New ctrl vector for $pmux cell $flatten\softshell.\flash.\spimemio.$procmux$8944: { $auto$opt_reduce.cc:134:opt_mux$21427 \softshell.flash.spimemio.state [8] \softshell.flash.spimemio.state [5] \softshell.flash.spimemio.state [11] \softshell.flash.spimemio.state [3] }
+ New ctrl vector for $pmux cell $flatten\softshell.\flash.\spimemio.\xfer.$procmux$8599: { $flatten\softshell.\flash.\spimemio.\xfer.$procmux$8477_CMP $auto$opt_reduce.cc:134:opt_mux$21429 }
+ New ctrl vector for $pmux cell $flatten\softshell.\flash.\spimemio.\xfer.$procmux$8609: { $flatten\softshell.\flash.\spimemio.\xfer.$procmux$8477_CMP $auto$opt_reduce.cc:134:opt_mux$21431 }
+ New input vector for $reduce_or cell $auto$opt_reduce.cc:128:opt_mux$21426: { \softshell.flash.spimemio.state [12] \softshell.flash.spimemio.state [9] \softshell.flash.spimemio.state [6] \softshell.flash.spimemio.state [4] \softshell.flash.spimemio.state [2:0] }
+ Optimizing cells in module \user_proj_example.
+Performed a total of 16 changes.
+
+23.15.5. Executing OPT_MERGE pass (detect identical cells).
+Finding identical cells in module `\user_proj_example'.
+<suppressed ~15 debug messages>
+Removed a total of 5 cells.
+
+23.15.6. Executing OPT_DFF pass (perform DFF optimizations).
+Adding SRST signal on $flatten\softshell.\shared_mem.\ram.$procdff$16865 ($dff) from module user_proj_example (D = $flatten\softshell.\shared_mem.\ram.$procmux$14991_Y [7], Q = $flatten\softshell.\shared_mem.\ram.$memwr$\ram3$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:109$2765_EN [7], rval = 1'0).
+Adding SRST signal on $flatten\softshell.\shared_mem.\ram.$procdff$16862 ($dff) from module user_proj_example (D = $flatten\softshell.\shared_mem.\ram.$procmux$14979_Y [7], Q = $flatten\softshell.\shared_mem.\ram.$memwr$\ram2$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:107$2764_EN [7], rval = 1'0).
+Adding SRST signal on $flatten\softshell.\shared_mem.\ram.$procdff$16859 ($dff) from module user_proj_example (D = $flatten\softshell.\shared_mem.\ram.$procmux$14967_Y [7], Q = $flatten\softshell.\shared_mem.\ram.$memwr$\ram1$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:105$2763_EN [7], rval = 1'0).
+Adding SRST signal on $flatten\softshell.\shared_mem.\ram.$procdff$16856 ($dff) from module user_proj_example (D = $flatten\softshell.\shared_mem.\ram.$procmux$14955_Y [7], Q = $flatten\softshell.\shared_mem.\ram.$memwr$\ram0$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:103$2762_EN [7], rval = 1'0).
+Adding SRST signal on $flatten\softshell.\cpus[2].core.\soc_mem.\ram.$procdff$16852 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[2].core.\soc_mem.\ram.$procmux$14935_Y [7], Q = $flatten\softshell.\cpus[2].core.\soc_mem.\ram.$memwr$\ram3$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:109$2791_EN [7], rval = 1'0).
+Adding SRST signal on $flatten\softshell.\cpus[2].core.\soc_mem.\ram.$procdff$16849 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[2].core.\soc_mem.\ram.$procmux$14923_Y [7], Q = $flatten\softshell.\cpus[2].core.\soc_mem.\ram.$memwr$\ram2$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:107$2790_EN [7], rval = 1'0).
+Adding SRST signal on $flatten\softshell.\cpus[2].core.\soc_mem.\ram.$procdff$16846 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[2].core.\soc_mem.\ram.$procmux$14911_Y [7], Q = $flatten\softshell.\cpus[2].core.\soc_mem.\ram.$memwr$\ram1$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:105$2789_EN [7], rval = 1'0).
+Adding SRST signal on $flatten\softshell.\cpus[2].core.\soc_mem.\ram.$procdff$16843 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[2].core.\soc_mem.\ram.$procmux$14899_Y [7], Q = $flatten\softshell.\cpus[2].core.\soc_mem.\ram.$memwr$\ram0$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:103$2788_EN [7], rval = 1'0).
+Adding SRST signal on $flatten\softshell.\cpus[1].core.\soc_mem.\ram.$procdff$16852 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[1].core.\soc_mem.\ram.$procmux$14935_Y [7], Q = $flatten\softshell.\cpus[1].core.\soc_mem.\ram.$memwr$\ram3$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:109$2791_EN [7], rval = 1'0).
+Adding SRST signal on $flatten\softshell.\cpus[1].core.\soc_mem.\ram.$procdff$16849 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[1].core.\soc_mem.\ram.$procmux$14923_Y [7], Q = $flatten\softshell.\cpus[1].core.\soc_mem.\ram.$memwr$\ram2$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:107$2790_EN [7], rval = 1'0).
+Adding SRST signal on $flatten\softshell.\cpus[1].core.\soc_mem.\ram.$procdff$16846 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[1].core.\soc_mem.\ram.$procmux$14911_Y [7], Q = $flatten\softshell.\cpus[1].core.\soc_mem.\ram.$memwr$\ram1$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:105$2789_EN [7], rval = 1'0).
+Adding SRST signal on $flatten\softshell.\cpus[1].core.\soc_mem.\ram.$procdff$16843 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[1].core.\soc_mem.\ram.$procmux$14899_Y [7], Q = $flatten\softshell.\cpus[1].core.\soc_mem.\ram.$memwr$\ram0$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:103$2788_EN [7], rval = 1'0).
+Adding SRST signal on $flatten\softshell.\cpus[0].core.\soc_mem.\ram.$procdff$16852 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[0].core.\soc_mem.\ram.$procmux$14935_Y [7], Q = $flatten\softshell.\cpus[0].core.\soc_mem.\ram.$memwr$\ram3$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:109$2791_EN [7], rval = 1'0).
+Adding SRST signal on $flatten\softshell.\cpus[0].core.\soc_mem.\ram.$procdff$16849 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[0].core.\soc_mem.\ram.$procmux$14923_Y [7], Q = $flatten\softshell.\cpus[0].core.\soc_mem.\ram.$memwr$\ram2$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:107$2790_EN [7], rval = 1'0).
+Adding SRST signal on $flatten\softshell.\cpus[0].core.\soc_mem.\ram.$procdff$16846 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[0].core.\soc_mem.\ram.$procmux$14911_Y [7], Q = $flatten\softshell.\cpus[0].core.\soc_mem.\ram.$memwr$\ram1$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:105$2789_EN [7], rval = 1'0).
+Adding SRST signal on $flatten\softshell.\cpus[0].core.\soc_mem.\ram.$procdff$16843 ($dff) from module user_proj_example (D = $flatten\softshell.\cpus[0].core.\soc_mem.\ram.$procmux$14899_Y [7], Q = $flatten\softshell.\cpus[0].core.\soc_mem.\ram.$memwr$\ram0$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:103$2788_EN [7], rval = 1'0).
+Adding SRST signal on $auto$opt_dff.cc:764:run$20720 ($dffe) from module user_proj_example (D = $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$8075_Y, Q = \softshell.cpus[0].core.cpu.picorv32_core.mem_valid, rval = 1'0).
+Adding SRST signal on $auto$opt_dff.cc:764:run$20706 ($dffe) from module user_proj_example (D = $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$8039_Y, Q = \softshell.cpus[0].core.cpu.picorv32_core.mem_state, rval = 2'00).
+Adding SRST signal on $auto$opt_dff.cc:764:run$20261 ($dffe) from module user_proj_example (D = $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$11721_Y, Q = \softshell.cpus[1].core.cpu.picorv32_core.mem_valid, rval = 1'0).
+Adding SRST signal on $auto$opt_dff.cc:764:run$20247 ($dffe) from module user_proj_example (D = $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$11685_Y, Q = \softshell.cpus[1].core.cpu.picorv32_core.mem_state, rval = 2'00).
+Adding SRST signal on $auto$opt_dff.cc:764:run$19802 ($dffe) from module user_proj_example (D = $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$14586_Y, Q = \softshell.cpus[2].core.cpu.picorv32_core.mem_valid, rval = 1'0).
+Adding SRST signal on $auto$opt_dff.cc:764:run$19788 ($dffe) from module user_proj_example (D = $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$14550_Y, Q = \softshell.cpus[2].core.cpu.picorv32_core.mem_state, rval = 2'00).
+Setting constant 0-bit at position 6 on $auto$opt_dff.cc:764:run$19495 ($adffe) from module user_proj_example.
+Setting constant 0-bit at position 7 on $auto$opt_dff.cc:764:run$19495 ($adffe) from module user_proj_example.
+Setting constant 0-bit at position 8 on $auto$opt_dff.cc:764:run$19495 ($adffe) from module user_proj_example.
+Setting constant 0-bit at position 9 on $auto$opt_dff.cc:764:run$19495 ($adffe) from module user_proj_example.
+Setting constant 0-bit at position 10 on $auto$opt_dff.cc:764:run$19495 ($adffe) from module user_proj_example.
+Setting constant 0-bit at position 11 on $auto$opt_dff.cc:764:run$19495 ($adffe) from module user_proj_example.
+Setting constant 0-bit at position 12 on $auto$opt_dff.cc:764:run$19495 ($adffe) from module user_proj_example.
+Setting constant 0-bit at position 13 on $auto$opt_dff.cc:764:run$19495 ($adffe) from module user_proj_example.
+Setting constant 0-bit at position 14 on $auto$opt_dff.cc:764:run$19495 ($adffe) from module user_proj_example.
+Setting constant 0-bit at position 15 on $auto$opt_dff.cc:764:run$19495 ($adffe) from module user_proj_example.
+Setting constant 0-bit at position 16 on $auto$opt_dff.cc:764:run$19495 ($adffe) from module user_proj_example.
+Setting constant 0-bit at position 17 on $auto$opt_dff.cc:764:run$19495 ($adffe) from module user_proj_example.
+Setting constant 0-bit at position 18 on $auto$opt_dff.cc:764:run$19495 ($adffe) from module user_proj_example.
+Setting constant 0-bit at position 19 on $auto$opt_dff.cc:764:run$19495 ($adffe) from module user_proj_example.
+Setting constant 0-bit at position 20 on $auto$opt_dff.cc:764:run$19495 ($adffe) from module user_proj_example.
+Setting constant 0-bit at position 21 on $auto$opt_dff.cc:764:run$19495 ($adffe) from module user_proj_example.
+Setting constant 0-bit at position 22 on $auto$opt_dff.cc:764:run$19495 ($adffe) from module user_proj_example.
+Setting constant 0-bit at position 23 on $auto$opt_dff.cc:764:run$19495 ($adffe) from module user_proj_example.
+Setting constant 0-bit at position 24 on $auto$opt_dff.cc:764:run$19495 ($adffe) from module user_proj_example.
+Setting constant 0-bit at position 25 on $auto$opt_dff.cc:764:run$19495 ($adffe) from module user_proj_example.
+Setting constant 0-bit at position 26 on $auto$opt_dff.cc:764:run$19495 ($adffe) from module user_proj_example.
+Setting constant 0-bit at position 27 on $auto$opt_dff.cc:764:run$19495 ($adffe) from module user_proj_example.
+Setting constant 0-bit at position 28 on $auto$opt_dff.cc:764:run$19495 ($adffe) from module user_proj_example.
+Setting constant 0-bit at position 29 on $auto$opt_dff.cc:764:run$19495 ($adffe) from module user_proj_example.
+Setting constant 0-bit at position 30 on $auto$opt_dff.cc:764:run$19495 ($adffe) from module user_proj_example.
+Setting constant 0-bit at position 31 on $auto$opt_dff.cc:764:run$19495 ($adffe) from module user_proj_example.
+
+23.15.7. Executing OPT_CLEAN pass (remove unused cells and wires).
+Finding unused cells or wires in module \user_proj_example..
+Removed 22 unused cells and 58 unused wires.
+<suppressed ~23 debug messages>
+
+23.15.8. Executing OPT_EXPR pass (perform const folding).
+Optimizing module user_proj_example.
+
+23.15.9. Rerunning OPT passes. (Maybe there is more to do..)
+
+23.15.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
+Running muxtree optimizer on module \user_proj_example..
+ Creating internal representation of mux trees.
+ Evaluating internal representation of mux trees.
+ Analyzing evaluation results.
+Removed 0 multiplexer ports.
+<suppressed ~423 debug messages>
+
+23.15.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
+ Optimizing cells in module \user_proj_example.
+Performed a total of 0 changes.
+
+23.15.12. Executing OPT_MERGE pass (detect identical cells).
+Finding identical cells in module `\user_proj_example'.
+Removed a total of 0 cells.
+
+23.15.13. Executing OPT_DFF pass (perform DFF optimizations).
+
+23.15.14. Executing OPT_CLEAN pass (remove unused cells and wires).
+Finding unused cells or wires in module \user_proj_example..
+
+23.15.15. Executing OPT_EXPR pass (perform const folding).
+Optimizing module user_proj_example.
+
+23.15.16. Finished OPT passes. (There is nothing left to do.)
+
+23.16. Executing MEMORY pass.
+
+23.16.1. Executing OPT_MEM pass (optimize memories).
+Performed a total of 0 transformations.
+
+23.16.2. Executing MEMORY_DFF pass (merging $dff cells to $memrd and $memwr).
+Checking cell `$flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.\cpuregs.$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/rv_core.v:0$32' in module `\user_proj_example': merged $dff to cell.
+Checking cell `$flatten\softshell.\cpus[0].core.\flexio.\out_fifo.$memwr$\mem$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:0$2034' in module `\user_proj_example': merged $dff to cell.
+Checking cell `$flatten\softshell.\cpus[0].core.\soc_mem.\ram.$memwr$\ram0$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:0$2810' in module `\user_proj_example': merged $dff to cell.
+Checking cell `$flatten\softshell.\cpus[0].core.\soc_mem.\ram.$memwr$\ram1$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:0$2811' in module `\user_proj_example': merged $dff to cell.
+Checking cell `$flatten\softshell.\cpus[0].core.\soc_mem.\ram.$memwr$\ram2$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:0$2812' in module `\user_proj_example': merged $dff to cell.
+Checking cell `$flatten\softshell.\cpus[0].core.\soc_mem.\ram.$memwr$\ram3$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:0$2813' in module `\user_proj_example': merged $dff to cell.
+Checking cell `$flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.\cpuregs.$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/rv_core.v:0$32' in module `\user_proj_example': merged $dff to cell.
+Checking cell `$flatten\softshell.\cpus[1].core.\flexio.\out_fifo.$memwr$\mem$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:0$2034' in module `\user_proj_example': merged $dff to cell.
+Checking cell `$flatten\softshell.\cpus[1].core.\soc_mem.\ram.$memwr$\ram0$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:0$2810' in module `\user_proj_example': merged $dff to cell.
+Checking cell `$flatten\softshell.\cpus[1].core.\soc_mem.\ram.$memwr$\ram1$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:0$2811' in module `\user_proj_example': merged $dff to cell.
+Checking cell `$flatten\softshell.\cpus[1].core.\soc_mem.\ram.$memwr$\ram2$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:0$2812' in module `\user_proj_example': merged $dff to cell.
+Checking cell `$flatten\softshell.\cpus[1].core.\soc_mem.\ram.$memwr$\ram3$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:0$2813' in module `\user_proj_example': merged $dff to cell.
+Checking cell `$flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.\cpuregs.$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/rv_core.v:0$32' in module `\user_proj_example': merged $dff to cell.
+Checking cell `$flatten\softshell.\cpus[2].core.\flexio.\out_fifo.$memwr$\mem$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:0$2034' in module `\user_proj_example': merged $dff to cell.
+Checking cell `$flatten\softshell.\cpus[2].core.\soc_mem.\ram.$memwr$\ram0$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:0$2810' in module `\user_proj_example': merged $dff to cell.
+Checking cell `$flatten\softshell.\cpus[2].core.\soc_mem.\ram.$memwr$\ram1$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:0$2811' in module `\user_proj_example': merged $dff to cell.
+Checking cell `$flatten\softshell.\cpus[2].core.\soc_mem.\ram.$memwr$\ram2$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:0$2812' in module `\user_proj_example': merged $dff to cell.
+Checking cell `$flatten\softshell.\cpus[2].core.\soc_mem.\ram.$memwr$\ram3$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:0$2813' in module `\user_proj_example': merged $dff to cell.
+Checking cell `$flatten\softshell.\shared_mem.\ram.$memwr$\ram0$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:0$2784' in module `\user_proj_example': merged $dff to cell.
+Checking cell `$flatten\softshell.\shared_mem.\ram.$memwr$\ram1$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:0$2785' in module `\user_proj_example': merged $dff to cell.
+Checking cell `$flatten\softshell.\shared_mem.\ram.$memwr$\ram2$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:0$2786' in module `\user_proj_example': merged $dff to cell.
+Checking cell `$flatten\softshell.\shared_mem.\ram.$memwr$\ram3$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:0$2787' in module `\user_proj_example': merged $dff to cell.
+Checking cell `$flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.\cpuregs.$memrd$\regs$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/rv_core.v:288$30' in module `\user_proj_example': merged address $dff to cell.
+Checking cell `$flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.\cpuregs.$memrd$\regs$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/rv_core.v:289$31' in module `\user_proj_example': merged address $dff to cell.
+Checking cell `$flatten\softshell.\cpus[0].core.\flexio.\out_fifo.$memrd$\mem$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:160$2021' in module `\user_proj_example': no (compatible) $dff found.
+Checking cell `$flatten\softshell.\cpus[0].core.\soc_mem.\ram.$memrd$\ram0$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:116$2806' in module `\user_proj_example': merged data $dff to cell.
+Checking cell `$flatten\softshell.\cpus[0].core.\soc_mem.\ram.$memrd$\ram1$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:117$2807' in module `\user_proj_example': merged data $dff to cell.
+Checking cell `$flatten\softshell.\cpus[0].core.\soc_mem.\ram.$memrd$\ram2$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:118$2808' in module `\user_proj_example': merged data $dff to cell.
+Checking cell `$flatten\softshell.\cpus[0].core.\soc_mem.\ram.$memrd$\ram3$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:119$2809' in module `\user_proj_example': merged data $dff to cell.
+Checking cell `$flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.\cpuregs.$memrd$\regs$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/rv_core.v:288$30' in module `\user_proj_example': merged address $dff to cell.
+Checking cell `$flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.\cpuregs.$memrd$\regs$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/rv_core.v:289$31' in module `\user_proj_example': merged address $dff to cell.
+Checking cell `$flatten\softshell.\cpus[1].core.\flexio.\out_fifo.$memrd$\mem$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:160$2021' in module `\user_proj_example': no (compatible) $dff found.
+Checking cell `$flatten\softshell.\cpus[1].core.\soc_mem.\ram.$memrd$\ram0$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:116$2806' in module `\user_proj_example': merged data $dff to cell.
+Checking cell `$flatten\softshell.\cpus[1].core.\soc_mem.\ram.$memrd$\ram1$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:117$2807' in module `\user_proj_example': merged data $dff to cell.
+Checking cell `$flatten\softshell.\cpus[1].core.\soc_mem.\ram.$memrd$\ram2$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:118$2808' in module `\user_proj_example': merged data $dff to cell.
+Checking cell `$flatten\softshell.\cpus[1].core.\soc_mem.\ram.$memrd$\ram3$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:119$2809' in module `\user_proj_example': merged data $dff to cell.
+Checking cell `$flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.\cpuregs.$memrd$\regs$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/rv_core.v:288$30' in module `\user_proj_example': merged address $dff to cell.
+Checking cell `$flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.\cpuregs.$memrd$\regs$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/rv_core.v:289$31' in module `\user_proj_example': merged address $dff to cell.
+Checking cell `$flatten\softshell.\cpus[2].core.\flexio.\out_fifo.$memrd$\mem$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:160$2021' in module `\user_proj_example': no (compatible) $dff found.
+Checking cell `$flatten\softshell.\cpus[2].core.\soc_mem.\ram.$memrd$\ram0$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:116$2806' in module `\user_proj_example': merged data $dff to cell.
+Checking cell `$flatten\softshell.\cpus[2].core.\soc_mem.\ram.$memrd$\ram1$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:117$2807' in module `\user_proj_example': merged data $dff to cell.
+Checking cell `$flatten\softshell.\cpus[2].core.\soc_mem.\ram.$memrd$\ram2$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:118$2808' in module `\user_proj_example': merged data $dff to cell.
+Checking cell `$flatten\softshell.\cpus[2].core.\soc_mem.\ram.$memrd$\ram3$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:119$2809' in module `\user_proj_example': merged data $dff to cell.
+Checking cell `$flatten\softshell.\shared_mem.\ram.$memrd$\ram0$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:116$2780' in module `\user_proj_example': merged data $dff to cell.
+Checking cell `$flatten\softshell.\shared_mem.\ram.$memrd$\ram1$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:117$2781' in module `\user_proj_example': merged data $dff to cell.
+Checking cell `$flatten\softshell.\shared_mem.\ram.$memrd$\ram2$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:118$2782' in module `\user_proj_example': merged data $dff to cell.
+Checking cell `$flatten\softshell.\shared_mem.\ram.$memrd$\ram3$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:119$2783' in module `\user_proj_example': merged data $dff to cell.
+
+23.16.3. Executing OPT_CLEAN pass (remove unused cells and wires).
+Finding unused cells or wires in module \user_proj_example..
+Removed 58 unused cells and 86 unused wires.
+<suppressed ~59 debug messages>
+
+23.16.4. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells).
+
+23.16.5. Executing OPT_CLEAN pass (remove unused cells and wires).
+Finding unused cells or wires in module \user_proj_example..
+
+23.16.6. Executing MEMORY_COLLECT pass (generating $mem cells).
+Collecting $memrd, $memwr and $meminit for memory `\softshell.cpus[0].core.cpu.picorv32_core.cpuregs.regs' in module `\user_proj_example':
+ $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.\cpuregs.$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/rv_core.v:0$32 ($memwr)
+ $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.\cpuregs.$memrd$\regs$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/rv_core.v:288$30 ($memrd)
+ $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.\cpuregs.$memrd$\regs$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/rv_core.v:289$31 ($memrd)
+Collecting $memrd, $memwr and $meminit for memory `\softshell.cpus[0].core.flexio.out_fifo.mem' in module `\user_proj_example':
+ $flatten\softshell.\cpus[0].core.\flexio.\out_fifo.$memwr$\mem$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:0$2034 ($memwr)
+ $flatten\softshell.\cpus[0].core.\flexio.\out_fifo.$memrd$\mem$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:160$2021 ($memrd)
+Collecting $memrd, $memwr and $meminit for memory `\softshell.cpus[0].core.soc_mem.ram.ram0' in module `\user_proj_example':
+ $flatten\softshell.\cpus[0].core.\soc_mem.\ram.$memwr$\ram0$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:0$2810 ($memwr)
+ $flatten\softshell.\cpus[0].core.\soc_mem.\ram.$memrd$\ram0$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:116$2806 ($memrd)
+Collecting $memrd, $memwr and $meminit for memory `\softshell.cpus[0].core.soc_mem.ram.ram1' in module `\user_proj_example':
+ $flatten\softshell.\cpus[0].core.\soc_mem.\ram.$memwr$\ram1$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:0$2811 ($memwr)
+ $flatten\softshell.\cpus[0].core.\soc_mem.\ram.$memrd$\ram1$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:117$2807 ($memrd)
+Collecting $memrd, $memwr and $meminit for memory `\softshell.cpus[0].core.soc_mem.ram.ram2' in module `\user_proj_example':
+ $flatten\softshell.\cpus[0].core.\soc_mem.\ram.$memwr$\ram2$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:0$2812 ($memwr)
+ $flatten\softshell.\cpus[0].core.\soc_mem.\ram.$memrd$\ram2$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:118$2808 ($memrd)
+Collecting $memrd, $memwr and $meminit for memory `\softshell.cpus[0].core.soc_mem.ram.ram3' in module `\user_proj_example':
+ $flatten\softshell.\cpus[0].core.\soc_mem.\ram.$memwr$\ram3$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:0$2813 ($memwr)
+ $flatten\softshell.\cpus[0].core.\soc_mem.\ram.$memrd$\ram3$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:119$2809 ($memrd)
+Collecting $memrd, $memwr and $meminit for memory `\softshell.cpus[1].core.cpu.picorv32_core.cpuregs.regs' in module `\user_proj_example':
+ $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.\cpuregs.$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/rv_core.v:0$32 ($memwr)
+ $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.\cpuregs.$memrd$\regs$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/rv_core.v:288$30 ($memrd)
+ $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.\cpuregs.$memrd$\regs$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/rv_core.v:289$31 ($memrd)
+Collecting $memrd, $memwr and $meminit for memory `\softshell.cpus[1].core.flexio.out_fifo.mem' in module `\user_proj_example':
+ $flatten\softshell.\cpus[1].core.\flexio.\out_fifo.$memwr$\mem$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:0$2034 ($memwr)
+ $flatten\softshell.\cpus[1].core.\flexio.\out_fifo.$memrd$\mem$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:160$2021 ($memrd)
+Collecting $memrd, $memwr and $meminit for memory `\softshell.cpus[1].core.soc_mem.ram.ram0' in module `\user_proj_example':
+ $flatten\softshell.\cpus[1].core.\soc_mem.\ram.$memwr$\ram0$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:0$2810 ($memwr)
+ $flatten\softshell.\cpus[1].core.\soc_mem.\ram.$memrd$\ram0$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:116$2806 ($memrd)
+Collecting $memrd, $memwr and $meminit for memory `\softshell.cpus[1].core.soc_mem.ram.ram1' in module `\user_proj_example':
+ $flatten\softshell.\cpus[1].core.\soc_mem.\ram.$memwr$\ram1$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:0$2811 ($memwr)
+ $flatten\softshell.\cpus[1].core.\soc_mem.\ram.$memrd$\ram1$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:117$2807 ($memrd)
+Collecting $memrd, $memwr and $meminit for memory `\softshell.cpus[1].core.soc_mem.ram.ram2' in module `\user_proj_example':
+ $flatten\softshell.\cpus[1].core.\soc_mem.\ram.$memwr$\ram2$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:0$2812 ($memwr)
+ $flatten\softshell.\cpus[1].core.\soc_mem.\ram.$memrd$\ram2$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:118$2808 ($memrd)
+Collecting $memrd, $memwr and $meminit for memory `\softshell.cpus[1].core.soc_mem.ram.ram3' in module `\user_proj_example':
+ $flatten\softshell.\cpus[1].core.\soc_mem.\ram.$memwr$\ram3$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:0$2813 ($memwr)
+ $flatten\softshell.\cpus[1].core.\soc_mem.\ram.$memrd$\ram3$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:119$2809 ($memrd)
+Collecting $memrd, $memwr and $meminit for memory `\softshell.cpus[2].core.cpu.picorv32_core.cpuregs.regs' in module `\user_proj_example':
+ $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.\cpuregs.$memwr$\regs$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/rv_core.v:0$32 ($memwr)
+ $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.\cpuregs.$memrd$\regs$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/rv_core.v:288$30 ($memrd)
+ $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.\cpuregs.$memrd$\regs$/project/openlane/user_proj_example/../../verilog/rtl/softshell/rtl/rv_core.v:289$31 ($memrd)
+Collecting $memrd, $memwr and $meminit for memory `\softshell.cpus[2].core.flexio.out_fifo.mem' in module `\user_proj_example':
+ $flatten\softshell.\cpus[2].core.\flexio.\out_fifo.$memwr$\mem$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:0$2034 ($memwr)
+ $flatten\softshell.\cpus[2].core.\flexio.\out_fifo.$memrd$\mem$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/wb2axip/rtl/afifo.v:160$2021 ($memrd)
+Collecting $memrd, $memwr and $meminit for memory `\softshell.cpus[2].core.soc_mem.ram.ram0' in module `\user_proj_example':
+ $flatten\softshell.\cpus[2].core.\soc_mem.\ram.$memwr$\ram0$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:0$2810 ($memwr)
+ $flatten\softshell.\cpus[2].core.\soc_mem.\ram.$memrd$\ram0$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:116$2806 ($memrd)
+Collecting $memrd, $memwr and $meminit for memory `\softshell.cpus[2].core.soc_mem.ram.ram1' in module `\user_proj_example':
+ $flatten\softshell.\cpus[2].core.\soc_mem.\ram.$memwr$\ram1$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:0$2811 ($memwr)
+ $flatten\softshell.\cpus[2].core.\soc_mem.\ram.$memrd$\ram1$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:117$2807 ($memrd)
+Collecting $memrd, $memwr and $meminit for memory `\softshell.cpus[2].core.soc_mem.ram.ram2' in module `\user_proj_example':
+ $flatten\softshell.\cpus[2].core.\soc_mem.\ram.$memwr$\ram2$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:0$2812 ($memwr)
+ $flatten\softshell.\cpus[2].core.\soc_mem.\ram.$memrd$\ram2$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:118$2808 ($memrd)
+Collecting $memrd, $memwr and $meminit for memory `\softshell.cpus[2].core.soc_mem.ram.ram3' in module `\user_proj_example':
+ $flatten\softshell.\cpus[2].core.\soc_mem.\ram.$memwr$\ram3$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:0$2813 ($memwr)
+ $flatten\softshell.\cpus[2].core.\soc_mem.\ram.$memrd$\ram3$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:119$2809 ($memrd)
+Collecting $memrd, $memwr and $meminit for memory `\softshell.shared_mem.ram.ram0' in module `\user_proj_example':
+ $flatten\softshell.\shared_mem.\ram.$memwr$\ram0$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:0$2784 ($memwr)
+ $flatten\softshell.\shared_mem.\ram.$memrd$\ram0$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:116$2780 ($memrd)
+Collecting $memrd, $memwr and $meminit for memory `\softshell.shared_mem.ram.ram1' in module `\user_proj_example':
+ $flatten\softshell.\shared_mem.\ram.$memwr$\ram1$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:0$2785 ($memwr)
+ $flatten\softshell.\shared_mem.\ram.$memrd$\ram1$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:117$2781 ($memrd)
+Collecting $memrd, $memwr and $meminit for memory `\softshell.shared_mem.ram.ram2' in module `\user_proj_example':
+ $flatten\softshell.\shared_mem.\ram.$memwr$\ram2$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:0$2786 ($memwr)
+ $flatten\softshell.\shared_mem.\ram.$memrd$\ram2$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:118$2782 ($memrd)
+Collecting $memrd, $memwr and $meminit for memory `\softshell.shared_mem.ram.ram3' in module `\user_proj_example':
+ $flatten\softshell.\shared_mem.\ram.$memwr$\ram3$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:0$2787 ($memwr)
+ $flatten\softshell.\shared_mem.\ram.$memrd$\ram3$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/mem_ff_wb.v:119$2783 ($memrd)
+
+23.17. Executing OPT_CLEAN pass (remove unused cells and wires).
+Finding unused cells or wires in module \user_proj_example..
+
+23.18. Executing OPT pass (performing simple optimizations).
+
+23.18.1. Executing OPT_EXPR pass (perform const folding).
+Optimizing module user_proj_example.
+<suppressed ~826 debug messages>
+
+23.18.2. Executing OPT_MERGE pass (detect identical cells).
+Finding identical cells in module `\user_proj_example'.
+<suppressed ~357 debug messages>
+Removed a total of 119 cells.
+
+23.18.3. Executing OPT_DFF pass (perform DFF optimizations).
+Adding EN signal on $auto$opt_dff.cc:764:run$19625 ($dffe) from module user_proj_example (D = $auto$wreduce.cc:454:run$21098 [1:0], Q = \softshell.flash.spimemio.rd_addr [1:0]).
+
+23.18.4. Executing OPT_CLEAN pass (remove unused cells and wires).
+Finding unused cells or wires in module \user_proj_example..
+Removed 35 unused cells and 343 unused wires.
+<suppressed ~45 debug messages>
+
+23.18.5. Rerunning OPT passes. (Removed registers in this run.)
+
+23.18.6. Executing OPT_EXPR pass (perform const folding).
+Optimizing module user_proj_example.
+<suppressed ~2 debug messages>
+
+23.18.7. Executing OPT_MERGE pass (detect identical cells).
+Finding identical cells in module `\user_proj_example'.
+Removed a total of 0 cells.
+
+23.18.8. Executing OPT_DFF pass (perform DFF optimizations).
+Adding SRST signal on $auto$opt_dff.cc:764:run$19625 ($dffe) from module user_proj_example (D = $auto$wreduce.cc:454:run$21097 [23:20], Q = \softshell.flash.spimemio.rd_addr [23:20], rval = 4'0000).
+
+23.18.9. Executing OPT_CLEAN pass (remove unused cells and wires).
+Finding unused cells or wires in module \user_proj_example..
+Removed 0 unused cells and 1 unused wires.
+<suppressed ~1 debug messages>
+
+23.18.10. Rerunning OPT passes. (Removed registers in this run.)
+
+23.18.11. Executing OPT_EXPR pass (perform const folding).
+Optimizing module user_proj_example.
+
+23.18.12. Executing OPT_MERGE pass (detect identical cells).
+Finding identical cells in module `\user_proj_example'.
+Removed a total of 0 cells.
+
+23.18.13. Executing OPT_DFF pass (perform DFF optimizations).
+
+23.18.14. Executing OPT_CLEAN pass (remove unused cells and wires).
+Finding unused cells or wires in module \user_proj_example..
+
+23.18.15. Finished fast OPT passes.
+
+23.19. Executing MEMORY_MAP pass (converting $mem cells to logic and flip-flops).
+Mapping memory cell \softshell.cpus[0].core.cpu.picorv32_core.cpuregs.regs in module \user_proj_example:
+ created 32 $dff cells and 0 static cells of width 32.
+ read interface: 2 $dff and 62 $mux cells.
+ write interface: 32 write mux blocks.
+Mapping memory cell \softshell.cpus[0].core.flexio.out_fifo.mem in module \user_proj_example:
+ created 4 $dff cells and 0 static cells of width 32.
+ read interface: 0 $dff and 3 $mux cells.
+ write interface: 4 write mux blocks.
+Mapping memory cell \softshell.cpus[0].core.soc_mem.ram.ram0 in module \user_proj_example:
+ created 32 $dff cells and 0 static cells of width 8.
+ read interface: 1 $dff and 31 $mux cells.
+ write interface: 32 write mux blocks.
+Mapping memory cell \softshell.cpus[0].core.soc_mem.ram.ram1 in module \user_proj_example:
+ created 32 $dff cells and 0 static cells of width 8.
+ read interface: 1 $dff and 31 $mux cells.
+ write interface: 32 write mux blocks.
+Mapping memory cell \softshell.cpus[0].core.soc_mem.ram.ram2 in module \user_proj_example:
+ created 32 $dff cells and 0 static cells of width 8.
+ read interface: 1 $dff and 31 $mux cells.
+ write interface: 32 write mux blocks.
+Mapping memory cell \softshell.cpus[0].core.soc_mem.ram.ram3 in module \user_proj_example:
+ created 32 $dff cells and 0 static cells of width 8.
+ read interface: 1 $dff and 31 $mux cells.
+ write interface: 32 write mux blocks.
+Mapping memory cell \softshell.cpus[1].core.cpu.picorv32_core.cpuregs.regs in module \user_proj_example:
+ created 32 $dff cells and 0 static cells of width 32.
+ read interface: 2 $dff and 62 $mux cells.
+ write interface: 32 write mux blocks.
+Mapping memory cell \softshell.cpus[1].core.flexio.out_fifo.mem in module \user_proj_example:
+ created 4 $dff cells and 0 static cells of width 32.
+ read interface: 0 $dff and 3 $mux cells.
+ write interface: 4 write mux blocks.
+Mapping memory cell \softshell.cpus[1].core.soc_mem.ram.ram0 in module \user_proj_example:
+ created 32 $dff cells and 0 static cells of width 8.
+ read interface: 1 $dff and 31 $mux cells.
+ write interface: 32 write mux blocks.
+Mapping memory cell \softshell.cpus[1].core.soc_mem.ram.ram1 in module \user_proj_example:
+ created 32 $dff cells and 0 static cells of width 8.
+ read interface: 1 $dff and 31 $mux cells.
+ write interface: 32 write mux blocks.
+Mapping memory cell \softshell.cpus[1].core.soc_mem.ram.ram2 in module \user_proj_example:
+ created 32 $dff cells and 0 static cells of width 8.
+ read interface: 1 $dff and 31 $mux cells.
+ write interface: 32 write mux blocks.
+Mapping memory cell \softshell.cpus[1].core.soc_mem.ram.ram3 in module \user_proj_example:
+ created 32 $dff cells and 0 static cells of width 8.
+ read interface: 1 $dff and 31 $mux cells.
+ write interface: 32 write mux blocks.
+Mapping memory cell \softshell.cpus[2].core.cpu.picorv32_core.cpuregs.regs in module \user_proj_example:
+ created 32 $dff cells and 0 static cells of width 32.
+ read interface: 2 $dff and 62 $mux cells.
+ write interface: 32 write mux blocks.
+Mapping memory cell \softshell.cpus[2].core.flexio.out_fifo.mem in module \user_proj_example:
+ created 4 $dff cells and 0 static cells of width 32.
+ read interface: 0 $dff and 3 $mux cells.
+ write interface: 4 write mux blocks.
+Mapping memory cell \softshell.cpus[2].core.soc_mem.ram.ram0 in module \user_proj_example:
+ created 32 $dff cells and 0 static cells of width 8.
+ read interface: 1 $dff and 31 $mux cells.
+ write interface: 32 write mux blocks.
+Mapping memory cell \softshell.cpus[2].core.soc_mem.ram.ram1 in module \user_proj_example:
+ created 32 $dff cells and 0 static cells of width 8.
+ read interface: 1 $dff and 31 $mux cells.
+ write interface: 32 write mux blocks.
+Mapping memory cell \softshell.cpus[2].core.soc_mem.ram.ram2 in module \user_proj_example:
+ created 32 $dff cells and 0 static cells of width 8.
+ read interface: 1 $dff and 31 $mux cells.
+ write interface: 32 write mux blocks.
+Mapping memory cell \softshell.cpus[2].core.soc_mem.ram.ram3 in module \user_proj_example:
+ created 32 $dff cells and 0 static cells of width 8.
+ read interface: 1 $dff and 31 $mux cells.
+ write interface: 32 write mux blocks.
+Mapping memory cell \softshell.shared_mem.ram.ram0 in module \user_proj_example:
+ created 512 $dff cells and 0 static cells of width 8.
+ read interface: 1 $dff and 511 $mux cells.
+ write interface: 512 write mux blocks.
+Mapping memory cell \softshell.shared_mem.ram.ram1 in module \user_proj_example:
+ created 512 $dff cells and 0 static cells of width 8.
+ read interface: 1 $dff and 511 $mux cells.
+ write interface: 512 write mux blocks.
+Mapping memory cell \softshell.shared_mem.ram.ram2 in module \user_proj_example:
+ created 512 $dff cells and 0 static cells of width 8.
+ read interface: 1 $dff and 511 $mux cells.
+ write interface: 512 write mux blocks.
+Mapping memory cell \softshell.shared_mem.ram.ram3 in module \user_proj_example:
+ created 512 $dff cells and 0 static cells of width 8.
+ read interface: 1 $dff and 511 $mux cells.
+ write interface: 512 write mux blocks.
+
+23.20. Executing OPT pass (performing simple optimizations).
+
+23.20.1. Executing OPT_EXPR pass (perform const folding).
+Optimizing module user_proj_example.
+<suppressed ~90 debug messages>
+
+23.20.2. Executing OPT_MERGE pass (detect identical cells).
+Finding identical cells in module `\user_proj_example'.
+<suppressed ~3 debug messages>
+Removed a total of 1 cells.
+
+23.20.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
+Running muxtree optimizer on module \user_proj_example..
+ Creating internal representation of mux trees.
+ Evaluating internal representation of mux trees.
+ Analyzing evaluation results.
+Removed 0 multiplexer ports.
+<suppressed ~2912 debug messages>
+
+23.20.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
+ Optimizing cells in module \user_proj_example.
+ New input vector for $reduce_and cell $auto$opt_dff.cc:243:make_patterns_logic$21933: { $auto$opt_dff.cc:217:make_patterns_logic$21930 $flatten\softshell.\flash.\spimemio.$logic_and$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/spimemio.v:386$704_Y $auto$rtlil.cc:2121:Not$19602 }
+ Consolidated identical input bits for $pmux cell $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$6246:
+ Old ports: A=\softshell.cpus[0].core.cpu.picorv32_core.mem_rdata_word, B={ \softshell.cpus[0].core.cpu.picorv32_core.mem_rdata_word [15] \softshell.cpus[0].core.cpu.picorv32_core.mem_rdata_word [15] \softshell.cpus[0].core.cpu.picorv32_core.mem_rdata_word [15] \softshell.cpus[0].core.cpu.picorv32_core.mem_rdata_word [15] \softshell.cpus[0].core.cpu.picorv32_core.mem_rdata_word [15] \softshell.cpus[0].core.cpu.picorv32_core.mem_rdata_word [15] \softshell.cpus[0].core.cpu.picorv32_core.mem_rdata_word [15] \softshell.cpus[0].core.cpu.picorv32_core.mem_rdata_word [15] \softshell.cpus[0].core.cpu.picorv32_core.mem_rdata_word [15] \softshell.cpus[0].core.cpu.picorv32_core.mem_rdata_word [15] \softshell.cpus[0].core.cpu.picorv32_core.mem_rdata_word [15] \softshell.cpus[0].core.cpu.picorv32_core.mem_rdata_word [15] \softshell.cpus[0].core.cpu.picorv32_core.mem_rdata_word [15] \softshell.cpus[0].core.cpu.picorv32_core.mem_rdata_word [15] \softshell.cpus[0].core.cpu.picorv32_core.mem_rdata_word [15] \softshell.cpus[0].core.cpu.picorv32_core.mem_rdata_word [15] \softshell.cpus[0].core.cpu.picorv32_core.mem_rdata_word [15:0] \softshell.cpus[0].core.cpu.picorv32_core.mem_rdata_word [7] \softshell.cpus[0].core.cpu.picorv32_core.mem_rdata_word [7] \softshell.cpus[0].core.cpu.picorv32_core.mem_rdata_word [7] \softshell.cpus[0].core.cpu.picorv32_core.mem_rdata_word [7] \softshell.cpus[0].core.cpu.picorv32_core.mem_rdata_word [7] \softshell.cpus[0].core.cpu.picorv32_core.mem_rdata_word [7] \softshell.cpus[0].core.cpu.picorv32_core.mem_rdata_word [7] \softshell.cpus[0].core.cpu.picorv32_core.mem_rdata_word [7] \softshell.cpus[0].core.cpu.picorv32_core.mem_rdata_word [7] \softshell.cpus[0].core.cpu.picorv32_core.mem_rdata_word [7] \softshell.cpus[0].core.cpu.picorv32_core.mem_rdata_word [7] \softshell.cpus[0].core.cpu.picorv32_core.mem_rdata_word [7] \softshell.cpus[0].core.cpu.picorv32_core.mem_rdata_word [7] \softshell.cpus[0].core.cpu.picorv32_core.mem_rdata_word [7] \softshell.cpus[0].core.cpu.picorv32_core.mem_rdata_word [7] \softshell.cpus[0].core.cpu.picorv32_core.mem_rdata_word [7] \softshell.cpus[0].core.cpu.picorv32_core.mem_rdata_word [7] \softshell.cpus[0].core.cpu.picorv32_core.mem_rdata_word [7] \softshell.cpus[0].core.cpu.picorv32_core.mem_rdata_word [7] \softshell.cpus[0].core.cpu.picorv32_core.mem_rdata_word [7] \softshell.cpus[0].core.cpu.picorv32_core.mem_rdata_word [7] \softshell.cpus[0].core.cpu.picorv32_core.mem_rdata_word [7] \softshell.cpus[0].core.cpu.picorv32_core.mem_rdata_word [7] \softshell.cpus[0].core.cpu.picorv32_core.mem_rdata_word [7] \softshell.cpus[0].core.cpu.picorv32_core.mem_rdata_word [7:0] }, Y=$flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$6246_Y
+ New ports: A=\softshell.cpus[0].core.cpu.picorv32_core.mem_rdata_word [31:8], B={ \softshell.cpus[0].core.cpu.picorv32_core.mem_rdata_word [15] \softshell.cpus[0].core.cpu.picorv32_core.mem_rdata_word [15] \softshell.cpus[0].core.cpu.picorv32_core.mem_rdata_word [15] \softshell.cpus[0].core.cpu.picorv32_core.mem_rdata_word [15] \softshell.cpus[0].core.cpu.picorv32_core.mem_rdata_word [15] \softshell.cpus[0].core.cpu.picorv32_core.mem_rdata_word [15] \softshell.cpus[0].core.cpu.picorv32_core.mem_rdata_word [15] \softshell.cpus[0].core.cpu.picorv32_core.mem_rdata_word [15] \softshell.cpus[0].core.cpu.picorv32_core.mem_rdata_word [15] \softshell.cpus[0].core.cpu.picorv32_core.mem_rdata_word [15] \softshell.cpus[0].core.cpu.picorv32_core.mem_rdata_word [15] \softshell.cpus[0].core.cpu.picorv32_core.mem_rdata_word [15] \softshell.cpus[0].core.cpu.picorv32_core.mem_rdata_word [15] \softshell.cpus[0].core.cpu.picorv32_core.mem_rdata_word [15] \softshell.cpus[0].core.cpu.picorv32_core.mem_rdata_word [15] \softshell.cpus[0].core.cpu.picorv32_core.mem_rdata_word [15] \softshell.cpus[0].core.cpu.picorv32_core.mem_rdata_word [15:7] \softshell.cpus[0].core.cpu.picorv32_core.mem_rdata_word [7] \softshell.cpus[0].core.cpu.picorv32_core.mem_rdata_word [7] \softshell.cpus[0].core.cpu.picorv32_core.mem_rdata_word [7] \softshell.cpus[0].core.cpu.picorv32_core.mem_rdata_word [7] \softshell.cpus[0].core.cpu.picorv32_core.mem_rdata_word [7] \softshell.cpus[0].core.cpu.picorv32_core.mem_rdata_word [7] \softshell.cpus[0].core.cpu.picorv32_core.mem_rdata_word [7] \softshell.cpus[0].core.cpu.picorv32_core.mem_rdata_word [7] \softshell.cpus[0].core.cpu.picorv32_core.mem_rdata_word [7] \softshell.cpus[0].core.cpu.picorv32_core.mem_rdata_word [7] \softshell.cpus[0].core.cpu.picorv32_core.mem_rdata_word [7] \softshell.cpus[0].core.cpu.picorv32_core.mem_rdata_word [7] \softshell.cpus[0].core.cpu.picorv32_core.mem_rdata_word [7] \softshell.cpus[0].core.cpu.picorv32_core.mem_rdata_word [7] \softshell.cpus[0].core.cpu.picorv32_core.mem_rdata_word [7] \softshell.cpus[0].core.cpu.picorv32_core.mem_rdata_word [7] \softshell.cpus[0].core.cpu.picorv32_core.mem_rdata_word [7] \softshell.cpus[0].core.cpu.picorv32_core.mem_rdata_word [7] \softshell.cpus[0].core.cpu.picorv32_core.mem_rdata_word [7] \softshell.cpus[0].core.cpu.picorv32_core.mem_rdata_word [7] \softshell.cpus[0].core.cpu.picorv32_core.mem_rdata_word [7] \softshell.cpus[0].core.cpu.picorv32_core.mem_rdata_word [7] \softshell.cpus[0].core.cpu.picorv32_core.mem_rdata_word [7] }, Y=$flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$6246_Y [31:8]
+ New connections: $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$6246_Y [7:0] = \softshell.cpus[0].core.cpu.picorv32_core.mem_rdata_word [7:0]
+ New ctrl vector for $pmux cell $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$7266: { $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$7285_CMP $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$7267_CMP }
+ New ctrl vector for $pmux cell $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$7268: { $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$7265_CMP $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$7283_CMP }
+ Consolidated identical input bits for $mux cell $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$7318:
+ Old ports: A={ \softshell.cpus[0].core.cpu.picorv32_core.mem_rdata_latched [31] \softshell.cpus[0].core.cpu.picorv32_core.mem_rdata_latched [31] \softshell.cpus[0].core.cpu.picorv32_core.mem_rdata_latched [31] \softshell.cpus[0].core.cpu.picorv32_core.mem_rdata_latched [31] \softshell.cpus[0].core.cpu.picorv32_core.mem_rdata_latched [31] \softshell.cpus[0].core.cpu.picorv32_core.mem_rdata_latched [31] \softshell.cpus[0].core.cpu.picorv32_core.mem_rdata_latched [31] \softshell.cpus[0].core.cpu.picorv32_core.mem_rdata_latched [31] \softshell.cpus[0].core.cpu.picorv32_core.mem_rdata_latched [31] \softshell.cpus[0].core.cpu.picorv32_core.mem_rdata_latched [31] \softshell.cpus[0].core.cpu.picorv32_core.mem_rdata_latched [31] \softshell.cpus[0].core.cpu.picorv32_core.mem_rdata_latched [31] }, B={ \softshell.cpus[0].core.cpu.picorv32_core.mem_rdata_latched [12] \softshell.cpus[0].core.cpu.picorv32_core.mem_rdata_latched [12] \softshell.cpus[0].core.cpu.picorv32_core.mem_rdata_latched [12] \softshell.cpus[0].core.cpu.picorv32_core.mem_rdata_latched [12] \softshell.cpus[0].core.cpu.picorv32_core.mem_rdata_latched [12] \softshell.cpus[0].core.cpu.picorv32_core.mem_rdata_latched [12] \softshell.cpus[0].core.cpu.picorv32_core.mem_rdata_latched [12] \softshell.cpus[0].core.cpu.picorv32_core.mem_rdata_latched [12] \softshell.cpus[0].core.cpu.picorv32_core.mem_rdata_latched [12] \softshell.cpus[0].core.cpu.picorv32_core.mem_rdata_latched [12] \softshell.cpus[0].core.cpu.picorv32_core.mem_rdata_latched [12] \softshell.cpus[0].core.cpu.picorv32_core.mem_rdata_latched [12] }, Y=$flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$7318_Y
+ New ports: A=\softshell.cpus[0].core.cpu.picorv32_core.mem_rdata_latched [31], B=\softshell.cpus[0].core.cpu.picorv32_core.mem_rdata_latched [12], Y=$flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$7318_Y [0]
+ New connections: $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$7318_Y [11:1] = { $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$7318_Y [0] $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$7318_Y [0] $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$7318_Y [0] $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$7318_Y [0] $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$7318_Y [0] $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$7318_Y [0] $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$7318_Y [0] $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$7318_Y [0] $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$7318_Y [0] $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$7318_Y [0] $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$7318_Y [0] }
+ Consolidated identical input bits for $mux cell $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$7346:
+ Old ports: A=2'00, B=2'10, Y=$auto$wreduce.cc:454:run$21071 [1:0]
+ New ports: A=1'0, B=1'1, Y=$auto$wreduce.cc:454:run$21071 [1]
+ New connections: $auto$wreduce.cc:454:run$21071 [0] = 1'0
+ Consolidated identical input bits for $mux cell $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$7524:
+ Old ports: A=5'00000, B={ 2'01 \softshell.cpus[0].core.cpu.picorv32_core.mem_rdata_latched [4:2] }, Y=$flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$7524_Y
+ New ports: A=4'0000, B={ 1'1 \softshell.cpus[0].core.cpu.picorv32_core.mem_rdata_latched [4:2] }, Y=$flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$7524_Y [3:0]
+ New connections: $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$7524_Y [4] = 1'0
+ Consolidated identical input bits for $mux cell $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$7531:
+ Old ports: A=\softshell.cpus[0].core.cpu.picorv32_core.mem_rdata_latched [19:12], B={ \softshell.cpus[0].core.cpu.picorv32_core.mem_rdata_latched [12] \softshell.cpus[0].core.cpu.picorv32_core.mem_rdata_latched [12] \softshell.cpus[0].core.cpu.picorv32_core.mem_rdata_latched [12] \softshell.cpus[0].core.cpu.picorv32_core.mem_rdata_latched [12] \softshell.cpus[0].core.cpu.picorv32_core.mem_rdata_latched [12] \softshell.cpus[0].core.cpu.picorv32_core.mem_rdata_latched [12] \softshell.cpus[0].core.cpu.picorv32_core.mem_rdata_latched [12] \softshell.cpus[0].core.cpu.picorv32_core.mem_rdata_latched [12] }, Y=$flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$7531_Y
+ New ports: A=\softshell.cpus[0].core.cpu.picorv32_core.mem_rdata_latched [19:13], B={ \softshell.cpus[0].core.cpu.picorv32_core.mem_rdata_latched [12] \softshell.cpus[0].core.cpu.picorv32_core.mem_rdata_latched [12] \softshell.cpus[0].core.cpu.picorv32_core.mem_rdata_latched [12] \softshell.cpus[0].core.cpu.picorv32_core.mem_rdata_latched [12] \softshell.cpus[0].core.cpu.picorv32_core.mem_rdata_latched [12] \softshell.cpus[0].core.cpu.picorv32_core.mem_rdata_latched [12] \softshell.cpus[0].core.cpu.picorv32_core.mem_rdata_latched [12] }, Y=$flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$7531_Y [7:1]
+ New connections: $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$7531_Y [0] = \softshell.cpus[0].core.cpu.picorv32_core.mem_rdata_latched [12]
+ Consolidated identical input bits for $mux cell $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$7556:
+ Old ports: A=5'00000, B={ 2'01 \softshell.cpus[0].core.cpu.picorv32_core.mem_rdata_latched [9:7] }, Y=$flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$7556_Y
+ New ports: A=4'0000, B={ 1'1 \softshell.cpus[0].core.cpu.picorv32_core.mem_rdata_latched [9:7] }, Y=$flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$7556_Y [3:0]
+ New connections: $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$7556_Y [4] = 1'0
+ Consolidated identical input bits for $mux cell $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$7574:
+ Old ports: A=5'00000, B={ 2'01 \softshell.cpus[0].core.cpu.picorv32_core.mem_rdata_latched [4:2] }, Y=$flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$7574_Y
+ New ports: A=4'0000, B={ 1'1 \softshell.cpus[0].core.cpu.picorv32_core.mem_rdata_latched [4:2] }, Y=$flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$7574_Y [3:0]
+ New connections: $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$7574_Y [4] = 1'0
+ Consolidated identical input bits for $mux cell $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$8191:
+ Old ports: A={ \softshell.cpus[0].core.cpu.picorv32_core.mem_rdata_latched [12] \softshell.cpus[0].core.cpu.picorv32_core.mem_rdata_latched [12] \softshell.cpus[0].core.cpu.picorv32_core.mem_rdata_latched [12] \softshell.cpus[0].core.cpu.picorv32_core.mem_rdata_latched [12] \softshell.cpus[0].core.cpu.picorv32_core.mem_rdata_latched [12] }, B={ \softshell.cpus[0].core.cpu.picorv32_core.mem_rdata_latched [6] 4'0000 }, Y=$flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$8191_Y
+ New ports: A={ \softshell.cpus[0].core.cpu.picorv32_core.mem_rdata_latched [12] \softshell.cpus[0].core.cpu.picorv32_core.mem_rdata_latched [12] }, B={ \softshell.cpus[0].core.cpu.picorv32_core.mem_rdata_latched [6] 1'0 }, Y={ $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$8191_Y [4] $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$8191_Y [0] }
+ New connections: $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$8191_Y [3:1] = { $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$8191_Y [0] $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$8191_Y [0] $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$8191_Y [0] }
+ Consolidated identical input bits for $pmux cell $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$8358:
+ Old ports: A=\softshell.cpus[0].core.cpu.picorv32_core.reg_op2, B={ \softshell.cpus[0].core.cpu.picorv32_core.reg_op2 [15:0] \softshell.cpus[0].core.cpu.picorv32_core.reg_op2 [15:0] \softshell.cpus[0].core.cpu.picorv32_core.reg_op2 [7:0] \softshell.cpus[0].core.cpu.picorv32_core.reg_op2 [7:0] \softshell.cpus[0].core.cpu.picorv32_core.reg_op2 [7:0] \softshell.cpus[0].core.cpu.picorv32_core.reg_op2 [7:0] }, Y=\softshell.cpus[0].core.cpu.picorv32_core.mem_la_wdata
+ New ports: A=\softshell.cpus[0].core.cpu.picorv32_core.reg_op2 [31:8], B={ \softshell.cpus[0].core.cpu.picorv32_core.reg_op2 [15:0] \softshell.cpus[0].core.cpu.picorv32_core.reg_op2 [15:0] \softshell.cpus[0].core.cpu.picorv32_core.reg_op2 [7:0] \softshell.cpus[0].core.cpu.picorv32_core.reg_op2 [7:0] }, Y=\softshell.cpus[0].core.cpu.picorv32_core.mem_la_wdata [31:8]
+ New connections: \softshell.cpus[0].core.cpu.picorv32_core.mem_la_wdata [7:0] = \softshell.cpus[0].core.cpu.picorv32_core.reg_op2 [7:0]
+ Consolidated identical input bits for $mux cell $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$ternary$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1312$4646:
+ Old ports: A=3'100, B=3'010, Y=$auto$wreduce.cc:454:run$21073 [2:0]
+ New ports: A=2'10, B=2'01, Y=$auto$wreduce.cc:454:run$21073 [2:1]
+ New connections: $auto$wreduce.cc:454:run$21073 [0] = 1'0
+ Consolidated identical input bits for $mux cell $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$ternary$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1536$4722:
+ Old ports: A=2'00, B=2'10, Y=$flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$ternary$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1536$4722_Y
+ New ports: A=1'0, B=1'1, Y=$flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$ternary$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1536$4722_Y [1]
+ New connections: $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$ternary$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1536$4722_Y [0] = 1'0
+ Consolidated identical input bits for $mux cell $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$ternary$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1541$4724:
+ Old ports: A=3'011, B=3'100, Y=$flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$ternary$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1541$4724_Y [2:0]
+ New ports: A=2'01, B=2'10, Y={ $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$ternary$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1541$4724_Y [2] $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$ternary$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1541$4724_Y [0] }
+ New connections: $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$ternary$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1541$4724_Y [1] = $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$ternary$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1541$4724_Y [0]
+ Consolidated identical input bits for $mux cell $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$ternary$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1547$4729:
+ Old ports: A=3'100, B=3'010, Y=$flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$ternary$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1547$4729_Y [2:0]
+ New ports: A=2'10, B=2'01, Y=$flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$ternary$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1547$4729_Y [2:1]
+ New connections: $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$ternary$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1547$4729_Y [0] = 1'0
+ Consolidated identical input bits for $mux cell $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$ternary$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:382$4258:
+ Old ports: A={ \softshell.cpus[0].core.cpu.picorv32_core.reg_op1 [31:2] 2'00 }, B={ $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:382$4257_Y 2'00 }, Y=\softshell.cpus[0].core.cpu.picorv32_core.mem_la_addr
+ New ports: A=\softshell.cpus[0].core.cpu.picorv32_core.reg_op1 [31:2], B=$flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:382$4257_Y, Y=\softshell.cpus[0].core.cpu.picorv32_core.mem_la_addr [31:2]
+ New connections: \softshell.cpus[0].core.cpu.picorv32_core.mem_la_addr [1:0] = 2'00
+ Consolidated identical input bits for $mux cell $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$ternary$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:411$4273:
+ Old ports: A=4'0011, B=4'1100, Y=$flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$ternary$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:411$4273_Y
+ New ports: A=2'01, B=2'10, Y={ $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$ternary$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:411$4273_Y [2] $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$ternary$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:411$4273_Y [0] }
+ New connections: { $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$ternary$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:411$4273_Y [3] $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$ternary$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:411$4273_Y [1] } = { $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$ternary$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:411$4273_Y [2] $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$ternary$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:411$4273_Y [0] }
+ Consolidated identical input bits for $mux cell $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$ternary$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:491$4289:
+ Old ports: A=6'000000, B=6'100000, Y=$auto$wreduce.cc:454:run$21074 [5:0]
+ New ports: A=1'0, B=1'1, Y=$auto$wreduce.cc:454:run$21074 [5]
+ New connections: $auto$wreduce.cc:454:run$21074 [4:0] = 5'00000
+ Consolidated identical input bits for $mux cell $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$ternary$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:617$4333:
+ Old ports: A=2'11, B=2'00, Y=$flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$8045_Y
+ New ports: A=1'1, B=1'0, Y=$flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$8045_Y [0]
+ New connections: $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$8045_Y [1] = $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$8045_Y [0]
+ Consolidated identical input bits for $pmux cell $flatten\softshell.\cpus[0].core.\flexio.$procmux$16187:
+ Old ports: A=5'00000, B=15'100001100011100, Y=$flatten\softshell.\cpus[0].core.\flexio.$procmux$16187_Y
+ New ports: A=3'000, B=9'100110111, Y=$flatten\softshell.\cpus[0].core.\flexio.$procmux$16187_Y [4:2]
+ New connections: $flatten\softshell.\cpus[0].core.\flexio.$procmux$16187_Y [1:0] = 2'00
+ Consolidated identical input bits for $pmux cell $flatten\softshell.\cpus[0].core.\flexio.$procmux$16195:
+ Old ports: A={ \softshell.cpus[0].core.flexio.out_shift_reg [30:0] 1'0 }, B={ \softshell.cpus[0].core.flexio.out_shift_reg [29:0] 2'00 \softshell.cpus[0].core.flexio.out_shift_reg [27:0] 4'0000 \softshell.cpus[0].core.flexio.out_shift_reg [23:0] 8'00000000 }, Y=$flatten\softshell.\cpus[0].core.\flexio.$procmux$16195_Y
+ New ports: A=\softshell.cpus[0].core.flexio.out_shift_reg [30:0], B={ \softshell.cpus[0].core.flexio.out_shift_reg [29:0] 1'0 \softshell.cpus[0].core.flexio.out_shift_reg [27:0] 3'000 \softshell.cpus[0].core.flexio.out_shift_reg [23:0] 7'0000000 }, Y=$flatten\softshell.\cpus[0].core.\flexio.$procmux$16195_Y [31:1]
+ New connections: $flatten\softshell.\cpus[0].core.\flexio.$procmux$16195_Y [0] = 1'0
+ New ctrl vector for $pmux cell $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10912: { $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10931_CMP $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10913_CMP }
+ New ctrl vector for $pmux cell $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10914: { $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10911_CMP $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10929_CMP }
+ Consolidated identical input bits for $mux cell $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10964:
+ Old ports: A={ \softshell.cpus[1].core.cpu.picorv32_core.mem_rdata_latched [31] \softshell.cpus[1].core.cpu.picorv32_core.mem_rdata_latched [31] \softshell.cpus[1].core.cpu.picorv32_core.mem_rdata_latched [31] \softshell.cpus[1].core.cpu.picorv32_core.mem_rdata_latched [31] \softshell.cpus[1].core.cpu.picorv32_core.mem_rdata_latched [31] \softshell.cpus[1].core.cpu.picorv32_core.mem_rdata_latched [31] \softshell.cpus[1].core.cpu.picorv32_core.mem_rdata_latched [31] \softshell.cpus[1].core.cpu.picorv32_core.mem_rdata_latched [31] \softshell.cpus[1].core.cpu.picorv32_core.mem_rdata_latched [31] \softshell.cpus[1].core.cpu.picorv32_core.mem_rdata_latched [31] \softshell.cpus[1].core.cpu.picorv32_core.mem_rdata_latched [31] \softshell.cpus[1].core.cpu.picorv32_core.mem_rdata_latched [31] }, B={ \softshell.cpus[1].core.cpu.picorv32_core.mem_rdata_latched [12] \softshell.cpus[1].core.cpu.picorv32_core.mem_rdata_latched [12] \softshell.cpus[1].core.cpu.picorv32_core.mem_rdata_latched [12] \softshell.cpus[1].core.cpu.picorv32_core.mem_rdata_latched [12] \softshell.cpus[1].core.cpu.picorv32_core.mem_rdata_latched [12] \softshell.cpus[1].core.cpu.picorv32_core.mem_rdata_latched [12] \softshell.cpus[1].core.cpu.picorv32_core.mem_rdata_latched [12] \softshell.cpus[1].core.cpu.picorv32_core.mem_rdata_latched [12] \softshell.cpus[1].core.cpu.picorv32_core.mem_rdata_latched [12] \softshell.cpus[1].core.cpu.picorv32_core.mem_rdata_latched [12] \softshell.cpus[1].core.cpu.picorv32_core.mem_rdata_latched [12] \softshell.cpus[1].core.cpu.picorv32_core.mem_rdata_latched [12] }, Y=$flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10964_Y
+ New ports: A=\softshell.cpus[1].core.cpu.picorv32_core.mem_rdata_latched [31], B=\softshell.cpus[1].core.cpu.picorv32_core.mem_rdata_latched [12], Y=$flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10964_Y [0]
+ New connections: $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10964_Y [11:1] = { $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10964_Y [0] $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10964_Y [0] $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10964_Y [0] $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10964_Y [0] $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10964_Y [0] $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10964_Y [0] $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10964_Y [0] $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10964_Y [0] $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10964_Y [0] $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10964_Y [0] $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10964_Y [0] }
+ Consolidated identical input bits for $mux cell $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10992:
+ Old ports: A=2'00, B=2'10, Y=$auto$wreduce.cc:454:run$21080 [1:0]
+ New ports: A=1'0, B=1'1, Y=$auto$wreduce.cc:454:run$21080 [1]
+ New connections: $auto$wreduce.cc:454:run$21080 [0] = 1'0
+ Consolidated identical input bits for $mux cell $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$11170:
+ Old ports: A=5'00000, B={ 2'01 \softshell.cpus[1].core.cpu.picorv32_core.mem_rdata_latched [4:2] }, Y=$flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$11170_Y
+ New ports: A=4'0000, B={ 1'1 \softshell.cpus[1].core.cpu.picorv32_core.mem_rdata_latched [4:2] }, Y=$flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$11170_Y [3:0]
+ New connections: $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$11170_Y [4] = 1'0
+ Consolidated identical input bits for $mux cell $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$11177:
+ Old ports: A=\softshell.cpus[1].core.cpu.picorv32_core.mem_rdata_latched [19:12], B={ \softshell.cpus[1].core.cpu.picorv32_core.mem_rdata_latched [12] \softshell.cpus[1].core.cpu.picorv32_core.mem_rdata_latched [12] \softshell.cpus[1].core.cpu.picorv32_core.mem_rdata_latched [12] \softshell.cpus[1].core.cpu.picorv32_core.mem_rdata_latched [12] \softshell.cpus[1].core.cpu.picorv32_core.mem_rdata_latched [12] \softshell.cpus[1].core.cpu.picorv32_core.mem_rdata_latched [12] \softshell.cpus[1].core.cpu.picorv32_core.mem_rdata_latched [12] \softshell.cpus[1].core.cpu.picorv32_core.mem_rdata_latched [12] }, Y=$flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$11177_Y
+ New ports: A=\softshell.cpus[1].core.cpu.picorv32_core.mem_rdata_latched [19:13], B={ \softshell.cpus[1].core.cpu.picorv32_core.mem_rdata_latched [12] \softshell.cpus[1].core.cpu.picorv32_core.mem_rdata_latched [12] \softshell.cpus[1].core.cpu.picorv32_core.mem_rdata_latched [12] \softshell.cpus[1].core.cpu.picorv32_core.mem_rdata_latched [12] \softshell.cpus[1].core.cpu.picorv32_core.mem_rdata_latched [12] \softshell.cpus[1].core.cpu.picorv32_core.mem_rdata_latched [12] \softshell.cpus[1].core.cpu.picorv32_core.mem_rdata_latched [12] }, Y=$flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$11177_Y [7:1]
+ New connections: $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$11177_Y [0] = \softshell.cpus[1].core.cpu.picorv32_core.mem_rdata_latched [12]
+ Consolidated identical input bits for $mux cell $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$11202:
+ Old ports: A=5'00000, B={ 2'01 \softshell.cpus[1].core.cpu.picorv32_core.mem_rdata_latched [9:7] }, Y=$flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$11202_Y
+ New ports: A=4'0000, B={ 1'1 \softshell.cpus[1].core.cpu.picorv32_core.mem_rdata_latched [9:7] }, Y=$flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$11202_Y [3:0]
+ New connections: $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$11202_Y [4] = 1'0
+ Consolidated identical input bits for $mux cell $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$11220:
+ Old ports: A=5'00000, B={ 2'01 \softshell.cpus[1].core.cpu.picorv32_core.mem_rdata_latched [4:2] }, Y=$flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$11220_Y
+ New ports: A=4'0000, B={ 1'1 \softshell.cpus[1].core.cpu.picorv32_core.mem_rdata_latched [4:2] }, Y=$flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$11220_Y [3:0]
+ New connections: $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$11220_Y [4] = 1'0
+ Consolidated identical input bits for $mux cell $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$11837:
+ Old ports: A={ \softshell.cpus[1].core.cpu.picorv32_core.mem_rdata_latched [12] \softshell.cpus[1].core.cpu.picorv32_core.mem_rdata_latched [12] \softshell.cpus[1].core.cpu.picorv32_core.mem_rdata_latched [12] \softshell.cpus[1].core.cpu.picorv32_core.mem_rdata_latched [12] \softshell.cpus[1].core.cpu.picorv32_core.mem_rdata_latched [12] }, B={ \softshell.cpus[1].core.cpu.picorv32_core.mem_rdata_latched [6] 4'0000 }, Y=$flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$11837_Y
+ New ports: A={ \softshell.cpus[1].core.cpu.picorv32_core.mem_rdata_latched [12] \softshell.cpus[1].core.cpu.picorv32_core.mem_rdata_latched [12] }, B={ \softshell.cpus[1].core.cpu.picorv32_core.mem_rdata_latched [6] 1'0 }, Y={ $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$11837_Y [4] $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$11837_Y [0] }
+ New connections: $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$11837_Y [3:1] = { $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$11837_Y [0] $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$11837_Y [0] $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$11837_Y [0] }
+ Consolidated identical input bits for $pmux cell $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$12004:
+ Old ports: A=\softshell.cpus[1].core.cpu.picorv32_core.reg_op2, B={ \softshell.cpus[1].core.cpu.picorv32_core.reg_op2 [15:0] \softshell.cpus[1].core.cpu.picorv32_core.reg_op2 [15:0] \softshell.cpus[1].core.cpu.picorv32_core.reg_op2 [7:0] \softshell.cpus[1].core.cpu.picorv32_core.reg_op2 [7:0] \softshell.cpus[1].core.cpu.picorv32_core.reg_op2 [7:0] \softshell.cpus[1].core.cpu.picorv32_core.reg_op2 [7:0] }, Y=\softshell.cpus[1].core.cpu.picorv32_core.mem_la_wdata
+ New ports: A=\softshell.cpus[1].core.cpu.picorv32_core.reg_op2 [31:8], B={ \softshell.cpus[1].core.cpu.picorv32_core.reg_op2 [15:0] \softshell.cpus[1].core.cpu.picorv32_core.reg_op2 [15:0] \softshell.cpus[1].core.cpu.picorv32_core.reg_op2 [7:0] \softshell.cpus[1].core.cpu.picorv32_core.reg_op2 [7:0] }, Y=\softshell.cpus[1].core.cpu.picorv32_core.mem_la_wdata [31:8]
+ New connections: \softshell.cpus[1].core.cpu.picorv32_core.mem_la_wdata [7:0] = \softshell.cpus[1].core.cpu.picorv32_core.reg_op2 [7:0]
+ Consolidated identical input bits for $pmux cell $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$9892:
+ Old ports: A=\softshell.cpus[1].core.cpu.picorv32_core.mem_rdata_word, B={ \softshell.cpus[1].core.cpu.picorv32_core.mem_rdata_word [15] \softshell.cpus[1].core.cpu.picorv32_core.mem_rdata_word [15] \softshell.cpus[1].core.cpu.picorv32_core.mem_rdata_word [15] \softshell.cpus[1].core.cpu.picorv32_core.mem_rdata_word [15] \softshell.cpus[1].core.cpu.picorv32_core.mem_rdata_word [15] \softshell.cpus[1].core.cpu.picorv32_core.mem_rdata_word [15] \softshell.cpus[1].core.cpu.picorv32_core.mem_rdata_word [15] \softshell.cpus[1].core.cpu.picorv32_core.mem_rdata_word [15] \softshell.cpus[1].core.cpu.picorv32_core.mem_rdata_word [15] \softshell.cpus[1].core.cpu.picorv32_core.mem_rdata_word [15] \softshell.cpus[1].core.cpu.picorv32_core.mem_rdata_word [15] \softshell.cpus[1].core.cpu.picorv32_core.mem_rdata_word [15] \softshell.cpus[1].core.cpu.picorv32_core.mem_rdata_word [15] \softshell.cpus[1].core.cpu.picorv32_core.mem_rdata_word [15] \softshell.cpus[1].core.cpu.picorv32_core.mem_rdata_word [15] \softshell.cpus[1].core.cpu.picorv32_core.mem_rdata_word [15] \softshell.cpus[1].core.cpu.picorv32_core.mem_rdata_word [15:0] \softshell.cpus[1].core.cpu.picorv32_core.mem_rdata_word [7] \softshell.cpus[1].core.cpu.picorv32_core.mem_rdata_word [7] \softshell.cpus[1].core.cpu.picorv32_core.mem_rdata_word [7] \softshell.cpus[1].core.cpu.picorv32_core.mem_rdata_word [7] \softshell.cpus[1].core.cpu.picorv32_core.mem_rdata_word [7] \softshell.cpus[1].core.cpu.picorv32_core.mem_rdata_word [7] \softshell.cpus[1].core.cpu.picorv32_core.mem_rdata_word [7] \softshell.cpus[1].core.cpu.picorv32_core.mem_rdata_word [7] \softshell.cpus[1].core.cpu.picorv32_core.mem_rdata_word [7] \softshell.cpus[1].core.cpu.picorv32_core.mem_rdata_word [7] \softshell.cpus[1].core.cpu.picorv32_core.mem_rdata_word [7] \softshell.cpus[1].core.cpu.picorv32_core.mem_rdata_word [7] \softshell.cpus[1].core.cpu.picorv32_core.mem_rdata_word [7] \softshell.cpus[1].core.cpu.picorv32_core.mem_rdata_word [7] \softshell.cpus[1].core.cpu.picorv32_core.mem_rdata_word [7] \softshell.cpus[1].core.cpu.picorv32_core.mem_rdata_word [7] \softshell.cpus[1].core.cpu.picorv32_core.mem_rdata_word [7] \softshell.cpus[1].core.cpu.picorv32_core.mem_rdata_word [7] \softshell.cpus[1].core.cpu.picorv32_core.mem_rdata_word [7] \softshell.cpus[1].core.cpu.picorv32_core.mem_rdata_word [7] \softshell.cpus[1].core.cpu.picorv32_core.mem_rdata_word [7] \softshell.cpus[1].core.cpu.picorv32_core.mem_rdata_word [7] \softshell.cpus[1].core.cpu.picorv32_core.mem_rdata_word [7] \softshell.cpus[1].core.cpu.picorv32_core.mem_rdata_word [7] \softshell.cpus[1].core.cpu.picorv32_core.mem_rdata_word [7:0] }, Y=$flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$9892_Y
+ New ports: A=\softshell.cpus[1].core.cpu.picorv32_core.mem_rdata_word [31:8], B={ \softshell.cpus[1].core.cpu.picorv32_core.mem_rdata_word [15] \softshell.cpus[1].core.cpu.picorv32_core.mem_rdata_word [15] \softshell.cpus[1].core.cpu.picorv32_core.mem_rdata_word [15] \softshell.cpus[1].core.cpu.picorv32_core.mem_rdata_word [15] \softshell.cpus[1].core.cpu.picorv32_core.mem_rdata_word [15] \softshell.cpus[1].core.cpu.picorv32_core.mem_rdata_word [15] \softshell.cpus[1].core.cpu.picorv32_core.mem_rdata_word [15] \softshell.cpus[1].core.cpu.picorv32_core.mem_rdata_word [15] \softshell.cpus[1].core.cpu.picorv32_core.mem_rdata_word [15] \softshell.cpus[1].core.cpu.picorv32_core.mem_rdata_word [15] \softshell.cpus[1].core.cpu.picorv32_core.mem_rdata_word [15] \softshell.cpus[1].core.cpu.picorv32_core.mem_rdata_word [15] \softshell.cpus[1].core.cpu.picorv32_core.mem_rdata_word [15] \softshell.cpus[1].core.cpu.picorv32_core.mem_rdata_word [15] \softshell.cpus[1].core.cpu.picorv32_core.mem_rdata_word [15] \softshell.cpus[1].core.cpu.picorv32_core.mem_rdata_word [15] \softshell.cpus[1].core.cpu.picorv32_core.mem_rdata_word [15:7] \softshell.cpus[1].core.cpu.picorv32_core.mem_rdata_word [7] \softshell.cpus[1].core.cpu.picorv32_core.mem_rdata_word [7] \softshell.cpus[1].core.cpu.picorv32_core.mem_rdata_word [7] \softshell.cpus[1].core.cpu.picorv32_core.mem_rdata_word [7] \softshell.cpus[1].core.cpu.picorv32_core.mem_rdata_word [7] \softshell.cpus[1].core.cpu.picorv32_core.mem_rdata_word [7] \softshell.cpus[1].core.cpu.picorv32_core.mem_rdata_word [7] \softshell.cpus[1].core.cpu.picorv32_core.mem_rdata_word [7] \softshell.cpus[1].core.cpu.picorv32_core.mem_rdata_word [7] \softshell.cpus[1].core.cpu.picorv32_core.mem_rdata_word [7] \softshell.cpus[1].core.cpu.picorv32_core.mem_rdata_word [7] \softshell.cpus[1].core.cpu.picorv32_core.mem_rdata_word [7] \softshell.cpus[1].core.cpu.picorv32_core.mem_rdata_word [7] \softshell.cpus[1].core.cpu.picorv32_core.mem_rdata_word [7] \softshell.cpus[1].core.cpu.picorv32_core.mem_rdata_word [7] \softshell.cpus[1].core.cpu.picorv32_core.mem_rdata_word [7] \softshell.cpus[1].core.cpu.picorv32_core.mem_rdata_word [7] \softshell.cpus[1].core.cpu.picorv32_core.mem_rdata_word [7] \softshell.cpus[1].core.cpu.picorv32_core.mem_rdata_word [7] \softshell.cpus[1].core.cpu.picorv32_core.mem_rdata_word [7] \softshell.cpus[1].core.cpu.picorv32_core.mem_rdata_word [7] \softshell.cpus[1].core.cpu.picorv32_core.mem_rdata_word [7] \softshell.cpus[1].core.cpu.picorv32_core.mem_rdata_word [7] }, Y=$flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$9892_Y [31:8]
+ New connections: $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$9892_Y [7:0] = \softshell.cpus[1].core.cpu.picorv32_core.mem_rdata_word [7:0]
+ Consolidated identical input bits for $mux cell $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$ternary$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1312$3963:
+ Old ports: A=3'100, B=3'010, Y=$auto$wreduce.cc:454:run$21082 [2:0]
+ New ports: A=2'10, B=2'01, Y=$auto$wreduce.cc:454:run$21082 [2:1]
+ New connections: $auto$wreduce.cc:454:run$21082 [0] = 1'0
+ Consolidated identical input bits for $mux cell $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$ternary$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1536$4039:
+ Old ports: A=2'00, B=2'10, Y=$flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$ternary$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1536$4039_Y
+ New ports: A=1'0, B=1'1, Y=$flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$ternary$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1536$4039_Y [1]
+ New connections: $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$ternary$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1536$4039_Y [0] = 1'0
+ Consolidated identical input bits for $mux cell $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$ternary$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1541$4041:
+ Old ports: A=3'011, B=3'100, Y=$auto$wreduce.cc:454:run$21083 [2:0]
+ New ports: A=2'01, B=2'10, Y={ $auto$wreduce.cc:454:run$21083 [2] $auto$wreduce.cc:454:run$21083 [0] }
+ New connections: $auto$wreduce.cc:454:run$21083 [1] = $auto$wreduce.cc:454:run$21083 [0]
+ Consolidated identical input bits for $mux cell $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$ternary$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1547$4046:
+ Old ports: A=3'100, B=3'010, Y=$auto$wreduce.cc:454:run$21084 [2:0]
+ New ports: A=2'10, B=2'01, Y=$auto$wreduce.cc:454:run$21084 [2:1]
+ New connections: $auto$wreduce.cc:454:run$21084 [0] = 1'0
+ Consolidated identical input bits for $mux cell $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$ternary$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:382$3575:
+ Old ports: A={ \softshell.cpus[1].core.cpu.picorv32_core.reg_op1 [31:2] 2'00 }, B={ $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:382$3574_Y 2'00 }, Y=\softshell.cpus[1].core.cpu.picorv32_core.mem_la_addr
+ New ports: A=\softshell.cpus[1].core.cpu.picorv32_core.reg_op1 [31:2], B=$flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:382$3574_Y, Y=\softshell.cpus[1].core.cpu.picorv32_core.mem_la_addr [31:2]
+ New connections: \softshell.cpus[1].core.cpu.picorv32_core.mem_la_addr [1:0] = 2'00
+ Consolidated identical input bits for $mux cell $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$ternary$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:411$3590:
+ Old ports: A=4'0011, B=4'1100, Y=$flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$ternary$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:411$3590_Y
+ New ports: A=2'01, B=2'10, Y={ $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$ternary$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:411$3590_Y [2] $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$ternary$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:411$3590_Y [0] }
+ New connections: { $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$ternary$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:411$3590_Y [3] $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$ternary$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:411$3590_Y [1] } = { $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$ternary$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:411$3590_Y [2] $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$ternary$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:411$3590_Y [0] }
+ Consolidated identical input bits for $mux cell $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$ternary$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:491$3606:
+ Old ports: A=6'000000, B=6'100000, Y=$auto$wreduce.cc:454:run$21085 [5:0]
+ New ports: A=1'0, B=1'1, Y=$auto$wreduce.cc:454:run$21085 [5]
+ New connections: $auto$wreduce.cc:454:run$21085 [4:0] = 5'00000
+ Consolidated identical input bits for $mux cell $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$ternary$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:617$3650:
+ Old ports: A=2'11, B=2'00, Y=$flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$11691_Y
+ New ports: A=1'1, B=1'0, Y=$flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$11691_Y [0]
+ New connections: $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$11691_Y [1] = $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$11691_Y [0]
+ Consolidated identical input bits for $pmux cell $flatten\softshell.\cpus[1].core.\flexio.$procmux$16187:
+ Old ports: A=5'00000, B=15'100001100011100, Y=$flatten\softshell.\cpus[1].core.\flexio.$procmux$16187_Y
+ New ports: A=3'000, B=9'100110111, Y=$flatten\softshell.\cpus[1].core.\flexio.$procmux$16187_Y [4:2]
+ New connections: $flatten\softshell.\cpus[1].core.\flexio.$procmux$16187_Y [1:0] = 2'00
+ Consolidated identical input bits for $pmux cell $flatten\softshell.\cpus[1].core.\flexio.$procmux$16195:
+ Old ports: A={ \softshell.cpus[1].core.flexio.out_shift_reg [30:0] 1'0 }, B={ \softshell.cpus[1].core.flexio.out_shift_reg [29:0] 2'00 \softshell.cpus[1].core.flexio.out_shift_reg [27:0] 4'0000 \softshell.cpus[1].core.flexio.out_shift_reg [23:0] 8'00000000 }, Y=$flatten\softshell.\cpus[1].core.\flexio.$procmux$16195_Y
+ New ports: A=\softshell.cpus[1].core.flexio.out_shift_reg [30:0], B={ \softshell.cpus[1].core.flexio.out_shift_reg [29:0] 1'0 \softshell.cpus[1].core.flexio.out_shift_reg [27:0] 3'000 \softshell.cpus[1].core.flexio.out_shift_reg [23:0] 7'0000000 }, Y=$flatten\softshell.\cpus[1].core.\flexio.$procmux$16195_Y [31:1]
+ New connections: $flatten\softshell.\cpus[1].core.\flexio.$procmux$16195_Y [0] = 1'0
+ Consolidated identical input bits for $pmux cell $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$12757:
+ Old ports: A=\softshell.cpus[2].core.cpu.picorv32_core.mem_rdata_word, B={ \softshell.cpus[2].core.cpu.picorv32_core.mem_rdata_word [15] \softshell.cpus[2].core.cpu.picorv32_core.mem_rdata_word [15] \softshell.cpus[2].core.cpu.picorv32_core.mem_rdata_word [15] \softshell.cpus[2].core.cpu.picorv32_core.mem_rdata_word [15] \softshell.cpus[2].core.cpu.picorv32_core.mem_rdata_word [15] \softshell.cpus[2].core.cpu.picorv32_core.mem_rdata_word [15] \softshell.cpus[2].core.cpu.picorv32_core.mem_rdata_word [15] \softshell.cpus[2].core.cpu.picorv32_core.mem_rdata_word [15] \softshell.cpus[2].core.cpu.picorv32_core.mem_rdata_word [15] \softshell.cpus[2].core.cpu.picorv32_core.mem_rdata_word [15] \softshell.cpus[2].core.cpu.picorv32_core.mem_rdata_word [15] \softshell.cpus[2].core.cpu.picorv32_core.mem_rdata_word [15] \softshell.cpus[2].core.cpu.picorv32_core.mem_rdata_word [15] \softshell.cpus[2].core.cpu.picorv32_core.mem_rdata_word [15] \softshell.cpus[2].core.cpu.picorv32_core.mem_rdata_word [15] \softshell.cpus[2].core.cpu.picorv32_core.mem_rdata_word [15] \softshell.cpus[2].core.cpu.picorv32_core.mem_rdata_word [15:0] \softshell.cpus[2].core.cpu.picorv32_core.mem_rdata_word [7] \softshell.cpus[2].core.cpu.picorv32_core.mem_rdata_word [7] \softshell.cpus[2].core.cpu.picorv32_core.mem_rdata_word [7] \softshell.cpus[2].core.cpu.picorv32_core.mem_rdata_word [7] \softshell.cpus[2].core.cpu.picorv32_core.mem_rdata_word [7] \softshell.cpus[2].core.cpu.picorv32_core.mem_rdata_word [7] \softshell.cpus[2].core.cpu.picorv32_core.mem_rdata_word [7] \softshell.cpus[2].core.cpu.picorv32_core.mem_rdata_word [7] \softshell.cpus[2].core.cpu.picorv32_core.mem_rdata_word [7] \softshell.cpus[2].core.cpu.picorv32_core.mem_rdata_word [7] \softshell.cpus[2].core.cpu.picorv32_core.mem_rdata_word [7] \softshell.cpus[2].core.cpu.picorv32_core.mem_rdata_word [7] \softshell.cpus[2].core.cpu.picorv32_core.mem_rdata_word [7] \softshell.cpus[2].core.cpu.picorv32_core.mem_rdata_word [7] \softshell.cpus[2].core.cpu.picorv32_core.mem_rdata_word [7] \softshell.cpus[2].core.cpu.picorv32_core.mem_rdata_word [7] \softshell.cpus[2].core.cpu.picorv32_core.mem_rdata_word [7] \softshell.cpus[2].core.cpu.picorv32_core.mem_rdata_word [7] \softshell.cpus[2].core.cpu.picorv32_core.mem_rdata_word [7] \softshell.cpus[2].core.cpu.picorv32_core.mem_rdata_word [7] \softshell.cpus[2].core.cpu.picorv32_core.mem_rdata_word [7] \softshell.cpus[2].core.cpu.picorv32_core.mem_rdata_word [7] \softshell.cpus[2].core.cpu.picorv32_core.mem_rdata_word [7] \softshell.cpus[2].core.cpu.picorv32_core.mem_rdata_word [7] \softshell.cpus[2].core.cpu.picorv32_core.mem_rdata_word [7:0] }, Y=$flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$12757_Y
+ New ports: A=\softshell.cpus[2].core.cpu.picorv32_core.mem_rdata_word [31:8], B={ \softshell.cpus[2].core.cpu.picorv32_core.mem_rdata_word [15] \softshell.cpus[2].core.cpu.picorv32_core.mem_rdata_word [15] \softshell.cpus[2].core.cpu.picorv32_core.mem_rdata_word [15] \softshell.cpus[2].core.cpu.picorv32_core.mem_rdata_word [15] \softshell.cpus[2].core.cpu.picorv32_core.mem_rdata_word [15] \softshell.cpus[2].core.cpu.picorv32_core.mem_rdata_word [15] \softshell.cpus[2].core.cpu.picorv32_core.mem_rdata_word [15] \softshell.cpus[2].core.cpu.picorv32_core.mem_rdata_word [15] \softshell.cpus[2].core.cpu.picorv32_core.mem_rdata_word [15] \softshell.cpus[2].core.cpu.picorv32_core.mem_rdata_word [15] \softshell.cpus[2].core.cpu.picorv32_core.mem_rdata_word [15] \softshell.cpus[2].core.cpu.picorv32_core.mem_rdata_word [15] \softshell.cpus[2].core.cpu.picorv32_core.mem_rdata_word [15] \softshell.cpus[2].core.cpu.picorv32_core.mem_rdata_word [15] \softshell.cpus[2].core.cpu.picorv32_core.mem_rdata_word [15] \softshell.cpus[2].core.cpu.picorv32_core.mem_rdata_word [15] \softshell.cpus[2].core.cpu.picorv32_core.mem_rdata_word [15:7] \softshell.cpus[2].core.cpu.picorv32_core.mem_rdata_word [7] \softshell.cpus[2].core.cpu.picorv32_core.mem_rdata_word [7] \softshell.cpus[2].core.cpu.picorv32_core.mem_rdata_word [7] \softshell.cpus[2].core.cpu.picorv32_core.mem_rdata_word [7] \softshell.cpus[2].core.cpu.picorv32_core.mem_rdata_word [7] \softshell.cpus[2].core.cpu.picorv32_core.mem_rdata_word [7] \softshell.cpus[2].core.cpu.picorv32_core.mem_rdata_word [7] \softshell.cpus[2].core.cpu.picorv32_core.mem_rdata_word [7] \softshell.cpus[2].core.cpu.picorv32_core.mem_rdata_word [7] \softshell.cpus[2].core.cpu.picorv32_core.mem_rdata_word [7] \softshell.cpus[2].core.cpu.picorv32_core.mem_rdata_word [7] \softshell.cpus[2].core.cpu.picorv32_core.mem_rdata_word [7] \softshell.cpus[2].core.cpu.picorv32_core.mem_rdata_word [7] \softshell.cpus[2].core.cpu.picorv32_core.mem_rdata_word [7] \softshell.cpus[2].core.cpu.picorv32_core.mem_rdata_word [7] \softshell.cpus[2].core.cpu.picorv32_core.mem_rdata_word [7] \softshell.cpus[2].core.cpu.picorv32_core.mem_rdata_word [7] \softshell.cpus[2].core.cpu.picorv32_core.mem_rdata_word [7] \softshell.cpus[2].core.cpu.picorv32_core.mem_rdata_word [7] \softshell.cpus[2].core.cpu.picorv32_core.mem_rdata_word [7] \softshell.cpus[2].core.cpu.picorv32_core.mem_rdata_word [7] \softshell.cpus[2].core.cpu.picorv32_core.mem_rdata_word [7] \softshell.cpus[2].core.cpu.picorv32_core.mem_rdata_word [7] }, Y=$flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$12757_Y [31:8]
+ New connections: $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$12757_Y [7:0] = \softshell.cpus[2].core.cpu.picorv32_core.mem_rdata_word [7:0]
+ New ctrl vector for $pmux cell $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$13777: { $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$13796_CMP $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$13778_CMP }
+ New ctrl vector for $pmux cell $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$13779: { $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$13776_CMP $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$13794_CMP }
+ Consolidated identical input bits for $mux cell $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$13829:
+ Old ports: A={ \softshell.cpus[2].core.cpu.picorv32_core.mem_rdata_latched [31] \softshell.cpus[2].core.cpu.picorv32_core.mem_rdata_latched [31] \softshell.cpus[2].core.cpu.picorv32_core.mem_rdata_latched [31] \softshell.cpus[2].core.cpu.picorv32_core.mem_rdata_latched [31] \softshell.cpus[2].core.cpu.picorv32_core.mem_rdata_latched [31] \softshell.cpus[2].core.cpu.picorv32_core.mem_rdata_latched [31] \softshell.cpus[2].core.cpu.picorv32_core.mem_rdata_latched [31] \softshell.cpus[2].core.cpu.picorv32_core.mem_rdata_latched [31] \softshell.cpus[2].core.cpu.picorv32_core.mem_rdata_latched [31] \softshell.cpus[2].core.cpu.picorv32_core.mem_rdata_latched [31] \softshell.cpus[2].core.cpu.picorv32_core.mem_rdata_latched [31] \softshell.cpus[2].core.cpu.picorv32_core.mem_rdata_latched [31] }, B={ \softshell.cpus[2].core.cpu.picorv32_core.mem_rdata_latched [12] \softshell.cpus[2].core.cpu.picorv32_core.mem_rdata_latched [12] \softshell.cpus[2].core.cpu.picorv32_core.mem_rdata_latched [12] \softshell.cpus[2].core.cpu.picorv32_core.mem_rdata_latched [12] \softshell.cpus[2].core.cpu.picorv32_core.mem_rdata_latched [12] \softshell.cpus[2].core.cpu.picorv32_core.mem_rdata_latched [12] \softshell.cpus[2].core.cpu.picorv32_core.mem_rdata_latched [12] \softshell.cpus[2].core.cpu.picorv32_core.mem_rdata_latched [12] \softshell.cpus[2].core.cpu.picorv32_core.mem_rdata_latched [12] \softshell.cpus[2].core.cpu.picorv32_core.mem_rdata_latched [12] \softshell.cpus[2].core.cpu.picorv32_core.mem_rdata_latched [12] \softshell.cpus[2].core.cpu.picorv32_core.mem_rdata_latched [12] }, Y=$flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$13829_Y
+ New ports: A=\softshell.cpus[2].core.cpu.picorv32_core.mem_rdata_latched [31], B=\softshell.cpus[2].core.cpu.picorv32_core.mem_rdata_latched [12], Y=$flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$13829_Y [0]
+ New connections: $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$13829_Y [11:1] = { $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$13829_Y [0] $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$13829_Y [0] $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$13829_Y [0] $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$13829_Y [0] $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$13829_Y [0] $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$13829_Y [0] $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$13829_Y [0] $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$13829_Y [0] $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$13829_Y [0] $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$13829_Y [0] $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$13829_Y [0] }
+ Consolidated identical input bits for $mux cell $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$13857:
+ Old ports: A=2'00, B=2'10, Y=$auto$wreduce.cc:454:run$21091 [1:0]
+ New ports: A=1'0, B=1'1, Y=$auto$wreduce.cc:454:run$21091 [1]
+ New connections: $auto$wreduce.cc:454:run$21091 [0] = 1'0
+ Consolidated identical input bits for $mux cell $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$14035:
+ Old ports: A=5'00000, B={ 2'01 \softshell.cpus[2].core.cpu.picorv32_core.mem_rdata_latched [4:2] }, Y=$flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$14035_Y
+ New ports: A=4'0000, B={ 1'1 \softshell.cpus[2].core.cpu.picorv32_core.mem_rdata_latched [4:2] }, Y=$flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$14035_Y [3:0]
+ New connections: $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$14035_Y [4] = 1'0
+ Consolidated identical input bits for $mux cell $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$14042:
+ Old ports: A=\softshell.cpus[2].core.cpu.picorv32_core.mem_rdata_latched [19:12], B={ \softshell.cpus[2].core.cpu.picorv32_core.mem_rdata_latched [12] \softshell.cpus[2].core.cpu.picorv32_core.mem_rdata_latched [12] \softshell.cpus[2].core.cpu.picorv32_core.mem_rdata_latched [12] \softshell.cpus[2].core.cpu.picorv32_core.mem_rdata_latched [12] \softshell.cpus[2].core.cpu.picorv32_core.mem_rdata_latched [12] \softshell.cpus[2].core.cpu.picorv32_core.mem_rdata_latched [12] \softshell.cpus[2].core.cpu.picorv32_core.mem_rdata_latched [12] \softshell.cpus[2].core.cpu.picorv32_core.mem_rdata_latched [12] }, Y=$flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$14042_Y
+ New ports: A=\softshell.cpus[2].core.cpu.picorv32_core.mem_rdata_latched [19:13], B={ \softshell.cpus[2].core.cpu.picorv32_core.mem_rdata_latched [12] \softshell.cpus[2].core.cpu.picorv32_core.mem_rdata_latched [12] \softshell.cpus[2].core.cpu.picorv32_core.mem_rdata_latched [12] \softshell.cpus[2].core.cpu.picorv32_core.mem_rdata_latched [12] \softshell.cpus[2].core.cpu.picorv32_core.mem_rdata_latched [12] \softshell.cpus[2].core.cpu.picorv32_core.mem_rdata_latched [12] \softshell.cpus[2].core.cpu.picorv32_core.mem_rdata_latched [12] }, Y=$flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$14042_Y [7:1]
+ New connections: $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$14042_Y [0] = \softshell.cpus[2].core.cpu.picorv32_core.mem_rdata_latched [12]
+ Consolidated identical input bits for $mux cell $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$14067:
+ Old ports: A=5'00000, B={ 2'01 \softshell.cpus[2].core.cpu.picorv32_core.mem_rdata_latched [9:7] }, Y=$flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$14067_Y
+ New ports: A=4'0000, B={ 1'1 \softshell.cpus[2].core.cpu.picorv32_core.mem_rdata_latched [9:7] }, Y=$flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$14067_Y [3:0]
+ New connections: $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$14067_Y [4] = 1'0
+ Consolidated identical input bits for $mux cell $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$14085:
+ Old ports: A=5'00000, B={ 2'01 \softshell.cpus[2].core.cpu.picorv32_core.mem_rdata_latched [4:2] }, Y=$flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$14085_Y
+ New ports: A=4'0000, B={ 1'1 \softshell.cpus[2].core.cpu.picorv32_core.mem_rdata_latched [4:2] }, Y=$flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$14085_Y [3:0]
+ New connections: $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$14085_Y [4] = 1'0
+ Consolidated identical input bits for $mux cell $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$14702:
+ Old ports: A={ \softshell.cpus[2].core.cpu.picorv32_core.mem_rdata_latched [12] \softshell.cpus[2].core.cpu.picorv32_core.mem_rdata_latched [12] \softshell.cpus[2].core.cpu.picorv32_core.mem_rdata_latched [12] \softshell.cpus[2].core.cpu.picorv32_core.mem_rdata_latched [12] \softshell.cpus[2].core.cpu.picorv32_core.mem_rdata_latched [12] }, B={ \softshell.cpus[2].core.cpu.picorv32_core.mem_rdata_latched [6] 4'0000 }, Y=$flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$14702_Y
+ New ports: A={ \softshell.cpus[2].core.cpu.picorv32_core.mem_rdata_latched [12] \softshell.cpus[2].core.cpu.picorv32_core.mem_rdata_latched [12] }, B={ \softshell.cpus[2].core.cpu.picorv32_core.mem_rdata_latched [6] 1'0 }, Y={ $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$14702_Y [4] $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$14702_Y [0] }
+ New connections: $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$14702_Y [3:1] = { $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$14702_Y [0] $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$14702_Y [0] $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$14702_Y [0] }
+ Consolidated identical input bits for $pmux cell $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$14869:
+ Old ports: A=\softshell.cpus[2].core.cpu.picorv32_core.reg_op2, B={ \softshell.cpus[2].core.cpu.picorv32_core.reg_op2 [15:0] \softshell.cpus[2].core.cpu.picorv32_core.reg_op2 [15:0] \softshell.cpus[2].core.cpu.picorv32_core.reg_op2 [7:0] \softshell.cpus[2].core.cpu.picorv32_core.reg_op2 [7:0] \softshell.cpus[2].core.cpu.picorv32_core.reg_op2 [7:0] \softshell.cpus[2].core.cpu.picorv32_core.reg_op2 [7:0] }, Y=\softshell.cpus[2].core.cpu.picorv32_core.mem_la_wdata
+ New ports: A=\softshell.cpus[2].core.cpu.picorv32_core.reg_op2 [31:8], B={ \softshell.cpus[2].core.cpu.picorv32_core.reg_op2 [15:0] \softshell.cpus[2].core.cpu.picorv32_core.reg_op2 [15:0] \softshell.cpus[2].core.cpu.picorv32_core.reg_op2 [7:0] \softshell.cpus[2].core.cpu.picorv32_core.reg_op2 [7:0] }, Y=\softshell.cpus[2].core.cpu.picorv32_core.mem_la_wdata [31:8]
+ New connections: \softshell.cpus[2].core.cpu.picorv32_core.mem_la_wdata [7:0] = \softshell.cpus[2].core.cpu.picorv32_core.reg_op2 [7:0]
+ Consolidated identical input bits for $mux cell $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$ternary$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1312$3280:
+ Old ports: A=3'100, B=3'010, Y=$auto$wreduce.cc:454:run$21093 [2:0]
+ New ports: A=2'10, B=2'01, Y=$auto$wreduce.cc:454:run$21093 [2:1]
+ New connections: $auto$wreduce.cc:454:run$21093 [0] = 1'0
+ Consolidated identical input bits for $mux cell $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$ternary$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1536$3356:
+ Old ports: A=2'00, B=2'10, Y=$flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$ternary$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1536$3356_Y
+ New ports: A=1'0, B=1'1, Y=$flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$ternary$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1536$3356_Y [1]
+ New connections: $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$ternary$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1536$3356_Y [0] = 1'0
+ Consolidated identical input bits for $mux cell $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$ternary$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1541$3358:
+ Old ports: A=3'011, B=3'100, Y=$auto$wreduce.cc:454:run$21094 [2:0]
+ New ports: A=2'01, B=2'10, Y={ $auto$wreduce.cc:454:run$21094 [2] $auto$wreduce.cc:454:run$21094 [0] }
+ New connections: $auto$wreduce.cc:454:run$21094 [1] = $auto$wreduce.cc:454:run$21094 [0]
+ Consolidated identical input bits for $mux cell $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$ternary$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1547$3363:
+ Old ports: A=3'100, B=3'010, Y=$auto$wreduce.cc:454:run$21095 [2:0]
+ New ports: A=2'10, B=2'01, Y=$auto$wreduce.cc:454:run$21095 [2:1]
+ New connections: $auto$wreduce.cc:454:run$21095 [0] = 1'0
+ Consolidated identical input bits for $mux cell $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$ternary$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:382$2892:
+ Old ports: A={ \softshell.cpus[2].core.cpu.picorv32_core.reg_op1 [31:2] 2'00 }, B={ $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:382$2891_Y 2'00 }, Y=\softshell.cpus[2].core.cpu.picorv32_core.mem_la_addr
+ New ports: A=\softshell.cpus[2].core.cpu.picorv32_core.reg_op1 [31:2], B=$flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:382$2891_Y, Y=\softshell.cpus[2].core.cpu.picorv32_core.mem_la_addr [31:2]
+ New connections: \softshell.cpus[2].core.cpu.picorv32_core.mem_la_addr [1:0] = 2'00
+ Consolidated identical input bits for $mux cell $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$ternary$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:411$2907:
+ Old ports: A=4'0011, B=4'1100, Y=$flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$ternary$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:411$2907_Y
+ New ports: A=2'01, B=2'10, Y={ $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$ternary$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:411$2907_Y [2] $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$ternary$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:411$2907_Y [0] }
+ New connections: { $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$ternary$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:411$2907_Y [3] $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$ternary$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:411$2907_Y [1] } = { $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$ternary$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:411$2907_Y [2] $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$ternary$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:411$2907_Y [0] }
+ Consolidated identical input bits for $mux cell $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$ternary$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:491$2923:
+ Old ports: A=6'000000, B=6'100000, Y=$auto$wreduce.cc:454:run$21096 [5:0]
+ New ports: A=1'0, B=1'1, Y=$auto$wreduce.cc:454:run$21096 [5]
+ New connections: $auto$wreduce.cc:454:run$21096 [4:0] = 5'00000
+ Consolidated identical input bits for $mux cell $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$ternary$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:617$2967:
+ Old ports: A=2'11, B=2'00, Y=$flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$14556_Y
+ New ports: A=1'1, B=1'0, Y=$flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$14556_Y [0]
+ New connections: $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$14556_Y [1] = $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$14556_Y [0]
+ Consolidated identical input bits for $pmux cell $flatten\softshell.\cpus[2].core.\flexio.$procmux$16187:
+ Old ports: A=5'00000, B=15'100001100011100, Y=$flatten\softshell.\cpus[2].core.\flexio.$procmux$16187_Y
+ New ports: A=3'000, B=9'100110111, Y=$flatten\softshell.\cpus[2].core.\flexio.$procmux$16187_Y [4:2]
+ New connections: $flatten\softshell.\cpus[2].core.\flexio.$procmux$16187_Y [1:0] = 2'00
+ Consolidated identical input bits for $pmux cell $flatten\softshell.\cpus[2].core.\flexio.$procmux$16195:
+ Old ports: A={ \softshell.cpus[2].core.flexio.out_shift_reg [30:0] 1'0 }, B={ \softshell.cpus[2].core.flexio.out_shift_reg [29:0] 2'00 \softshell.cpus[2].core.flexio.out_shift_reg [27:0] 4'0000 \softshell.cpus[2].core.flexio.out_shift_reg [23:0] 8'00000000 }, Y=$flatten\softshell.\cpus[2].core.\flexio.$procmux$16195_Y
+ New ports: A=\softshell.cpus[2].core.flexio.out_shift_reg [30:0], B={ \softshell.cpus[2].core.flexio.out_shift_reg [29:0] 1'0 \softshell.cpus[2].core.flexio.out_shift_reg [27:0] 3'000 \softshell.cpus[2].core.flexio.out_shift_reg [23:0] 7'0000000 }, Y=$flatten\softshell.\cpus[2].core.\flexio.$procmux$16195_Y [31:1]
+ New connections: $flatten\softshell.\cpus[2].core.\flexio.$procmux$16195_Y [0] = 1'0
+ Consolidated identical input bits for $pmux cell $flatten\softshell.\flash.\spimemio.$procmux$8944:
+ Old ports: A=4'0000, B=16'0001001000110100, Y=$flatten\softshell.\flash.\spimemio.$procmux$8944_Y
+ New ports: A=3'000, B=12'001010011100, Y=$flatten\softshell.\flash.\spimemio.$procmux$8944_Y [2:0]
+ New connections: $flatten\softshell.\flash.\spimemio.$procmux$8944_Y [3] = 1'0
+ Consolidated identical input bits for $pmux cell $flatten\softshell.\flash.\spimemio.$procmux$8975:
+ Old ports: A=8'11101101, B=24'111010111011101100000011, Y=$flatten\softshell.\flash.\spimemio.$procmux$8975_Y
+ New ports: A=5'10110, B=15'101010110100001, Y={ $flatten\softshell.\flash.\spimemio.$procmux$8975_Y [6] $flatten\softshell.\flash.\spimemio.$procmux$8975_Y [4:1] }
+ New connections: { $flatten\softshell.\flash.\spimemio.$procmux$8975_Y [7] $flatten\softshell.\flash.\spimemio.$procmux$8975_Y [5] $flatten\softshell.\flash.\spimemio.$procmux$8975_Y [0] } = { $flatten\softshell.\flash.\spimemio.$procmux$8975_Y [3] $flatten\softshell.\flash.\spimemio.$procmux$8975_Y [3] 1'1 }
+ Consolidated identical input bits for $mux cell $flatten\softshell.\flash.\spimemio.$ternary$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/spimemio.v:478$712:
+ Old ports: A=7'1111111, B=7'0100101, Y=$auto$wreduce.cc:454:run$21099 [6:0]
+ New ports: A=1'1, B=1'0, Y=$auto$wreduce.cc:454:run$21099 [1]
+ New connections: { $auto$wreduce.cc:454:run$21099 [6:2] $auto$wreduce.cc:454:run$21099 [0] } = { $auto$wreduce.cc:454:run$21099 [1] 1'1 $auto$wreduce.cc:454:run$21099 [1] $auto$wreduce.cc:454:run$21099 [1] 2'11 }
+ Consolidated identical input bits for $mux cell $flatten\softshell.\flash.\spimemio.\xfer.$procmux$8470:
+ Old ports: A=\softshell.flash.spimemio.xfer.count, B={ $flatten\softshell.\flash.\spimemio.\xfer.$sub$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/spimemio.v:686$746_Y [3:1] \softshell.flash.spimemio.xfer.count [0] }, Y=$flatten\softshell.\flash.\spimemio.\xfer.$5\next_count[3:0]
+ New ports: A=\softshell.flash.spimemio.xfer.count [3:1], B=$flatten\softshell.\flash.\spimemio.\xfer.$sub$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/spimemio.v:686$746_Y [3:1], Y=$flatten\softshell.\flash.\spimemio.\xfer.$5\next_count[3:0] [3:1]
+ New connections: $flatten\softshell.\flash.\spimemio.\xfer.$5\next_count[3:0] [0] = \softshell.flash.spimemio.xfer.count [0]
+ Consolidated identical input bits for $mux cell $flatten\softshell.\flash.\spimemio.\xfer.$procmux$8511:
+ Old ports: A=\softshell.flash.spimemio.xfer.count, B={ $flatten\softshell.\flash.\spimemio.\xfer.$sub$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/spimemio.v:653$734_Y [3:2] \softshell.flash.spimemio.xfer.count [1:0] }, Y=$flatten\softshell.\flash.\spimemio.\xfer.$4\next_count[3:0]
+ New ports: A=\softshell.flash.spimemio.xfer.count [3:2], B=$flatten\softshell.\flash.\spimemio.\xfer.$sub$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/spimemio.v:653$734_Y [3:2], Y=$flatten\softshell.\flash.\spimemio.\xfer.$4\next_count[3:0] [3:2]
+ New connections: $flatten\softshell.\flash.\spimemio.\xfer.$4\next_count[3:0] [1:0] = \softshell.flash.spimemio.xfer.count [1:0]
+ Consolidated identical input bits for $pmux cell $flatten\softshell.\flash.\spimemio.\xfer.$procmux$8609:
+ Old ports: A={ \softshell.flash.spimemio.xfer.obuffer [5:0] 2'00 }, B={ \softshell.flash.spimemio.xfer.obuffer [6:0] 1'0 \softshell.flash.spimemio.xfer.obuffer [3:0] 4'0000 }, Y=\softshell.flash.spimemio.xfer.next_obuffer
+ New ports: A={ \softshell.flash.spimemio.xfer.obuffer [5:0] 1'0 }, B={ \softshell.flash.spimemio.xfer.obuffer [6:0] \softshell.flash.spimemio.xfer.obuffer [3:0] 3'000 }, Y=\softshell.flash.spimemio.xfer.next_obuffer [7:1]
+ New connections: \softshell.flash.spimemio.xfer.next_obuffer [0] = 1'0
+ Consolidated identical input bits for $mux cell $flatten\softshell.\interconnect.$ternary$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/verilog-wishbone/rtl/wb_mux_5.v:178$486:
+ Old ports: A=0, B={ 26'00000000000000000000000000 \softshell.pinmux.wb_dat_o [5:0] }, Y=$flatten\softshell.\interconnect.$ternary$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/verilog-wishbone/rtl/wb_mux_5.v:178$486_Y
+ New ports: A=6'000000, B=\softshell.pinmux.wb_dat_o [5:0], Y=$flatten\softshell.\interconnect.$ternary$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/verilog-wishbone/rtl/wb_mux_5.v:178$486_Y [5:0]
+ New connections: $flatten\softshell.\interconnect.$ternary$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/verilog-wishbone/rtl/wb_mux_5.v:178$486_Y [31:6] = 26'00000000000000000000000000
+ Consolidated identical input bits for $mux cell $flatten\softshell.\uart0.\simpleuart.$ternary$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/simpleuart.v:136$584:
+ Old ports: A=32'11111111111111111111111111111111, B={ 24'000000000000000000000000 \softshell.uart0.simpleuart.recv_buf_data }, Y=\softshell.uart0.simpleuart_reg_dat_do
+ New ports: A=9'111111111, B={ 1'0 \softshell.uart0.simpleuart.recv_buf_data }, Y=\softshell.uart0.simpleuart_reg_dat_do [8:0]
+ New connections: \softshell.uart0.simpleuart_reg_dat_do [31:9] = { \softshell.uart0.simpleuart_reg_dat_do [8] \softshell.uart0.simpleuart_reg_dat_do [8] \softshell.uart0.simpleuart_reg_dat_do [8] \softshell.uart0.simpleuart_reg_dat_do [8] \softshell.uart0.simpleuart_reg_dat_do [8] \softshell.uart0.simpleuart_reg_dat_do [8] \softshell.uart0.simpleuart_reg_dat_do [8] \softshell.uart0.simpleuart_reg_dat_do [8] \softshell.uart0.simpleuart_reg_dat_do [8] \softshell.uart0.simpleuart_reg_dat_do [8] \softshell.uart0.simpleuart_reg_dat_do [8] \softshell.uart0.simpleuart_reg_dat_do [8] \softshell.uart0.simpleuart_reg_dat_do [8] \softshell.uart0.simpleuart_reg_dat_do [8] \softshell.uart0.simpleuart_reg_dat_do [8] \softshell.uart0.simpleuart_reg_dat_do [8] \softshell.uart0.simpleuart_reg_dat_do [8] \softshell.uart0.simpleuart_reg_dat_do [8] \softshell.uart0.simpleuart_reg_dat_do [8] \softshell.uart0.simpleuart_reg_dat_do [8] \softshell.uart0.simpleuart_reg_dat_do [8] \softshell.uart0.simpleuart_reg_dat_do [8] \softshell.uart0.simpleuart_reg_dat_do [8] }
+ Optimizing cells in module \user_proj_example.
+ Consolidated identical input bits for $mux cell $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$7558:
+ Old ports: A=$flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$7556_Y, B={ 2'01 \softshell.cpus[0].core.cpu.picorv32_core.mem_rdata_latched [9:7] }, Y=$flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$7558_Y
+ New ports: A=$flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$7556_Y [3:0], B={ 1'1 \softshell.cpus[0].core.cpu.picorv32_core.mem_rdata_latched [9:7] }, Y=$flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$7558_Y [3:0]
+ New connections: $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$7558_Y [4] = 1'0
+ Consolidated identical input bits for $mux cell $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$11204:
+ Old ports: A=$flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$11202_Y, B={ 2'01 \softshell.cpus[1].core.cpu.picorv32_core.mem_rdata_latched [9:7] }, Y=$flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$11204_Y
+ New ports: A=$flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$11202_Y [3:0], B={ 1'1 \softshell.cpus[1].core.cpu.picorv32_core.mem_rdata_latched [9:7] }, Y=$flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$11204_Y [3:0]
+ New connections: $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$11204_Y [4] = 1'0
+ Consolidated identical input bits for $mux cell $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$14069:
+ Old ports: A=$flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$14067_Y, B={ 2'01 \softshell.cpus[2].core.cpu.picorv32_core.mem_rdata_latched [9:7] }, Y=$flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$14069_Y
+ New ports: A=$flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$14067_Y [3:0], B={ 1'1 \softshell.cpus[2].core.cpu.picorv32_core.mem_rdata_latched [9:7] }, Y=$flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$14069_Y [3:0]
+ New connections: $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$14069_Y [4] = 1'0
+ Consolidated identical input bits for $mux cell $flatten\softshell.\flash.\spimemio.$procmux$8965:
+ Old ports: A={ 1'1 $auto$wreduce.cc:454:run$21099 [6:0] }, B={ 4'0000 \softshell.flash.spimemio.config_dummy }, Y=$flatten\softshell.\flash.\spimemio.$procmux$8965_Y
+ New ports: A={ 1'1 $auto$wreduce.cc:454:run$21099 [1] $auto$wreduce.cc:454:run$21099 [1] 1'1 $auto$wreduce.cc:454:run$21099 [1] 1'1 }, B={ 2'00 \softshell.flash.spimemio.config_dummy }, Y=$flatten\softshell.\flash.\spimemio.$procmux$8965_Y [5:0]
+ New connections: $flatten\softshell.\flash.\spimemio.$procmux$8965_Y [7:6] = $flatten\softshell.\flash.\spimemio.$procmux$8965_Y [5:4]
+ Consolidated identical input bits for $mux cell $flatten\softshell.\interconnect.$ternary$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/verilog-wishbone/rtl/wb_mux_5.v:177$487:
+ Old ports: A=$flatten\softshell.\interconnect.$ternary$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/verilog-wishbone/rtl/wb_mux_5.v:178$486_Y, B={ \softshell.flash.spimemio.config_en 8'00000000 \softshell.flash.spimemio.config_ddr \softshell.flash.spimemio.config_qspi \softshell.flash.spimemio.config_cont \softshell.flash.spimemio.config_dummy 4'0000 \softshell.interconnect.wbs3_dat_i [11:8] 2'00 \softshell.flash_csb \softshell.flash_clk \io_in [13:10] }, Y=$flatten\softshell.\interconnect.$ternary$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/verilog-wishbone/rtl/wb_mux_5.v:177$487_Y
+ New ports: A={ 12'000000000000 $flatten\softshell.\interconnect.$ternary$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/verilog-wishbone/rtl/wb_mux_5.v:178$486_Y [5:0] }, B={ \softshell.flash.spimemio.config_en \softshell.flash.spimemio.config_ddr \softshell.flash.spimemio.config_qspi \softshell.flash.spimemio.config_cont \softshell.flash.spimemio.config_dummy \softshell.interconnect.wbs3_dat_i [11:8] \softshell.flash_csb \softshell.flash_clk \io_in [13:10] }, Y={ $flatten\softshell.\interconnect.$ternary$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/verilog-wishbone/rtl/wb_mux_5.v:177$487_Y [31] $flatten\softshell.\interconnect.$ternary$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/verilog-wishbone/rtl/wb_mux_5.v:177$487_Y [22:16] $flatten\softshell.\interconnect.$ternary$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/verilog-wishbone/rtl/wb_mux_5.v:177$487_Y [11:8] $flatten\softshell.\interconnect.$ternary$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/verilog-wishbone/rtl/wb_mux_5.v:177$487_Y [5:0] }
+ New connections: { $flatten\softshell.\interconnect.$ternary$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/verilog-wishbone/rtl/wb_mux_5.v:177$487_Y [30:23] $flatten\softshell.\interconnect.$ternary$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/verilog-wishbone/rtl/wb_mux_5.v:177$487_Y [15:12] $flatten\softshell.\interconnect.$ternary$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/verilog-wishbone/rtl/wb_mux_5.v:177$487_Y [7:6] } = 14'00000000000000
+ Optimizing cells in module \user_proj_example.
+ Consolidated identical input bits for $mux cell $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$7560:
+ Old ports: A=$flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$7558_Y, B={ 2'01 \softshell.cpus[0].core.cpu.picorv32_core.mem_rdata_latched [9:7] }, Y=$flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$7560_Y
+ New ports: A=$flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$7558_Y [3:0], B={ 1'1 \softshell.cpus[0].core.cpu.picorv32_core.mem_rdata_latched [9:7] }, Y=$flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$7560_Y [3:0]
+ New connections: $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$7560_Y [4] = 1'0
+ Consolidated identical input bits for $mux cell $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$11206:
+ Old ports: A=$flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$11204_Y, B={ 2'01 \softshell.cpus[1].core.cpu.picorv32_core.mem_rdata_latched [9:7] }, Y=$flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$11206_Y
+ New ports: A=$flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$11204_Y [3:0], B={ 1'1 \softshell.cpus[1].core.cpu.picorv32_core.mem_rdata_latched [9:7] }, Y=$flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$11206_Y [3:0]
+ New connections: $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$11206_Y [4] = 1'0
+ Consolidated identical input bits for $mux cell $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$14071:
+ Old ports: A=$flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$14069_Y, B={ 2'01 \softshell.cpus[2].core.cpu.picorv32_core.mem_rdata_latched [9:7] }, Y=$flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$14071_Y
+ New ports: A=$flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$14069_Y [3:0], B={ 1'1 \softshell.cpus[2].core.cpu.picorv32_core.mem_rdata_latched [9:7] }, Y=$flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$14071_Y [3:0]
+ New connections: $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$14071_Y [4] = 1'0
+ Optimizing cells in module \user_proj_example.
+Performed a total of 80 changes.
+
+23.20.5. Executing OPT_MERGE pass (detect identical cells).
+Finding identical cells in module `\user_proj_example'.
+<suppressed ~27 debug messages>
+Removed a total of 9 cells.
+
+23.20.6. Executing OPT_SHARE pass.
+ Found cells that share an operand and can be merged by moving the $mux $flatten\softshell.\arbiter.\arb_inst.$procmux$4907 in front of them:
+ $flatten\softshell.\arbiter.\arb_inst.$shl$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/verilog-wishbone/rtl/arbiter.v:123$2754
+ $flatten\softshell.\arbiter.\arb_inst.$shl$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/verilog-wishbone/rtl/arbiter.v:132$2756
+
+ Found cells that share an operand and can be merged by moving the $mux $flatten\softshell.\arbiter.\arb_inst.$procmux$4931 in front of them:
+ $flatten\softshell.\arbiter.\arb_inst.\priority_encoder_masked.$shl$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/verilog-wishbone/rtl/priority_encoder.v:96$4863
+ $flatten\softshell.\arbiter.\arb_inst.\priority_encoder_inst.$shl$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/verilog-wishbone/rtl/priority_encoder.v:96$4863
+
+ Found cells that share an operand and can be merged by moving the $mux $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$ternary$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1235$4855 in front of them:
+ $auto$alumacc.cc:485:replace_alu$21198
+ $auto$alumacc.cc:485:replace_alu$21165
+
+ Found cells that share an operand and can be merged by moving the $mux $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$ternary$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1235$4172 in front of them:
+ $auto$alumacc.cc:485:replace_alu$21276
+ $auto$alumacc.cc:485:replace_alu$21243
+
+ Found cells that share an operand and can be merged by moving the $mux $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$ternary$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1235$3489 in front of them:
+ $auto$alumacc.cc:485:replace_alu$21354
+ $auto$alumacc.cc:485:replace_alu$21321
+
+ Found cells that share an operand and can be merged by moving the $pmux $flatten\softshell.\flash.\spimemio.$procmux$8851 in front of them:
+ $flatten\softshell.\flash.\spimemio.$procmux$8849
+ $flatten\softshell.\flash.\spimemio.$procmux$8873
+
+23.20.7. Executing OPT_DFF pass (perform DFF optimizations).
+Adding EN signal on $memory\softshell.cpus[0].core.soc_mem.ram.ram0$rdreg[0]$22547 ($dff) from module user_proj_example (D = $memory\softshell.cpus[0].core.soc_mem.ram.ram0$rdreg[0]$d$22548, Q = \softshell.cpus[0].core.soc_mem.ram.dout [7:0]).
+Adding EN signal on $memory\softshell.cpus[0].core.soc_mem.ram.ram1$rdreg[0]$22952 ($dff) from module user_proj_example (D = $memory\softshell.cpus[0].core.soc_mem.ram.ram1$rdreg[0]$d$22953, Q = \softshell.cpus[0].core.soc_mem.ram.dout [15:8]).
+Adding EN signal on $memory\softshell.cpus[0].core.soc_mem.ram.ram2$rdreg[0]$23241 ($dff) from module user_proj_example (D = $memory\softshell.cpus[0].core.soc_mem.ram.ram2$rdreg[0]$d$23242, Q = \softshell.cpus[0].core.soc_mem.ram.dout [23:16]).
+Adding EN signal on $memory\softshell.cpus[0].core.soc_mem.ram.ram3$rdreg[0]$23530 ($dff) from module user_proj_example (D = $memory\softshell.cpus[0].core.soc_mem.ram.ram3$rdreg[0]$d$23531, Q = \softshell.cpus[0].core.soc_mem.ram.dout [31:24]).
+Adding EN signal on $memory\softshell.cpus[1].core.soc_mem.ram.ram0$rdreg[0]$24366 ($dff) from module user_proj_example (D = $memory\softshell.cpus[1].core.soc_mem.ram.ram0$rdreg[0]$d$24367, Q = \softshell.cpus[1].core.soc_mem.ram.dout [7:0]).
+Adding EN signal on $memory\softshell.cpus[1].core.soc_mem.ram.ram1$rdreg[0]$24771 ($dff) from module user_proj_example (D = $memory\softshell.cpus[1].core.soc_mem.ram.ram1$rdreg[0]$d$24772, Q = \softshell.cpus[1].core.soc_mem.ram.dout [15:8]).
+Adding EN signal on $memory\softshell.cpus[1].core.soc_mem.ram.ram2$rdreg[0]$25060 ($dff) from module user_proj_example (D = $memory\softshell.cpus[1].core.soc_mem.ram.ram2$rdreg[0]$d$25061, Q = \softshell.cpus[1].core.soc_mem.ram.dout [23:16]).
+Adding EN signal on $memory\softshell.cpus[1].core.soc_mem.ram.ram3$rdreg[0]$25349 ($dff) from module user_proj_example (D = $memory\softshell.cpus[1].core.soc_mem.ram.ram3$rdreg[0]$d$25350, Q = \softshell.cpus[1].core.soc_mem.ram.dout [31:24]).
+Adding EN signal on $memory\softshell.cpus[2].core.soc_mem.ram.ram0$rdreg[0]$26185 ($dff) from module user_proj_example (D = $memory\softshell.cpus[2].core.soc_mem.ram.ram0$rdreg[0]$d$26186, Q = \softshell.cpus[2].core.soc_mem.ram.dout [7:0]).
+Adding EN signal on $memory\softshell.cpus[2].core.soc_mem.ram.ram1$rdreg[0]$26590 ($dff) from module user_proj_example (D = $memory\softshell.cpus[2].core.soc_mem.ram.ram1$rdreg[0]$d$26591, Q = \softshell.cpus[2].core.soc_mem.ram.dout [15:8]).
+Adding EN signal on $memory\softshell.cpus[2].core.soc_mem.ram.ram2$rdreg[0]$26879 ($dff) from module user_proj_example (D = $memory\softshell.cpus[2].core.soc_mem.ram.ram2$rdreg[0]$d$26880, Q = \softshell.cpus[2].core.soc_mem.ram.dout [23:16]).
+Adding EN signal on $memory\softshell.cpus[2].core.soc_mem.ram.ram3$rdreg[0]$27168 ($dff) from module user_proj_example (D = $memory\softshell.cpus[2].core.soc_mem.ram.ram3$rdreg[0]$d$27169, Q = \softshell.cpus[2].core.soc_mem.ram.dout [31:24]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0$rdreg[0]$28417 ($dff) from module user_proj_example (D = $memory\softshell.shared_mem.ram.ram0$rdreg[0]$d$28418, Q = \softshell.shared_mem.ram.dout [7:0]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1$rdreg[0]$34230 ($dff) from module user_proj_example (D = $memory\softshell.shared_mem.ram.ram1$rdreg[0]$d$34231, Q = \softshell.shared_mem.ram.dout [15:8]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2$rdreg[0]$38839 ($dff) from module user_proj_example (D = $memory\softshell.shared_mem.ram.ram2$rdreg[0]$d$38840, Q = \softshell.shared_mem.ram.dout [23:16]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3$rdreg[0]$43448 ($dff) from module user_proj_example (D = $memory\softshell.shared_mem.ram.ram3$rdreg[0]$d$43449, Q = \softshell.shared_mem.ram.dout [31:24]).
+
+23.20.8. Executing OPT_CLEAN pass (remove unused cells and wires).
+Finding unused cells or wires in module \user_proj_example..
+Removed 16 unused cells and 5273 unused wires.
+<suppressed ~21 debug messages>
+
+23.20.9. Executing OPT_EXPR pass (perform const folding).
+Optimizing module user_proj_example.
+<suppressed ~25 debug messages>
+
+23.20.10. Rerunning OPT passes. (Maybe there is more to do..)
+
+23.20.11. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
+Running muxtree optimizer on module \user_proj_example..
+ Creating internal representation of mux trees.
+ Evaluating internal representation of mux trees.
+ Analyzing evaluation results.
+Removed 0 multiplexer ports.
+<suppressed ~2923 debug messages>
+
+23.20.12. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
+ Optimizing cells in module \user_proj_example.
+ Consolidated identical input bits for $mux cell $auto$opt_share.cc:241:merge_operators$47034:
+ Old ports: A={ 29'00000000000000000000000000000 $auto$wreduce.cc:454:run$21065 [2:0] }, B={ 29'00000000000000000000000000000 $auto$wreduce.cc:454:run$21064 [2:0] }, Y=$auto$rtlil.cc:2218:Mux$47035
+ New ports: A=$auto$wreduce.cc:454:run$21065 [2:0], B=$auto$wreduce.cc:454:run$21064 [2:0], Y=$auto$rtlil.cc:2218:Mux$47035 [2:0]
+ New connections: $auto$rtlil.cc:2218:Mux$47035 [31:3] = 29'00000000000000000000000000000
+ Consolidated identical input bits for $mux cell $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$7065:
+ Old ports: A=$flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1547$4730_Y, B={ $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1564$4734_Y [31:1] $auto$alumacc.cc:501:replace_alu$21181 [0] }, Y=$flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$7065_Y
+ New ports: A=$flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1547$4730_Y [31:1], B=$flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1564$4734_Y [31:1], Y=$flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$7065_Y [31:1]
+ New connections: $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$7065_Y [0] = $auto$alumacc.cc:501:replace_alu$21181 [0]
+ Consolidated identical input bits for $mux cell $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$7071:
+ Old ports: A={ $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$3\current_pc[31:0] [31:1] $auto$alumacc.cc:501:replace_alu$21181 [0] }, B=$flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1547$4730_Y, Y=$flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$7071_Y
+ New ports: A=$flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$3\current_pc[31:0] [31:1], B=$flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1547$4730_Y [31:1], Y=$flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$7071_Y [31:1]
+ New connections: $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$7071_Y [0] = $auto$alumacc.cc:501:replace_alu$21181 [0]
+ Consolidated identical input bits for $mux cell $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10711:
+ Old ports: A=$flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1547$4047_Y, B={ $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1564$4051_Y [31:1] $auto$alumacc.cc:501:replace_alu$21259 [0] }, Y=$flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10711_Y
+ New ports: A=$flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1547$4047_Y [31:1], B=$flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1564$4051_Y [31:1], Y=$flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10711_Y [31:1]
+ New connections: $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10711_Y [0] = $auto$alumacc.cc:501:replace_alu$21259 [0]
+ Consolidated identical input bits for $mux cell $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10717:
+ Old ports: A={ $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$3\current_pc[31:0] [31:1] $auto$alumacc.cc:501:replace_alu$21259 [0] }, B=$flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1547$4047_Y, Y=$flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10717_Y
+ New ports: A=$flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$3\current_pc[31:0] [31:1], B=$flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1547$4047_Y [31:1], Y=$flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10717_Y [31:1]
+ New connections: $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10717_Y [0] = $auto$alumacc.cc:501:replace_alu$21259 [0]
+ Consolidated identical input bits for $mux cell $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$13576:
+ Old ports: A=$flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1547$3364_Y, B={ $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1564$3368_Y [31:1] $auto$alumacc.cc:501:replace_alu$21337 [0] }, Y=$flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$13576_Y
+ New ports: A=$flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1547$3364_Y [31:1], B=$flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1564$3368_Y [31:1], Y=$flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$13576_Y [31:1]
+ New connections: $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$13576_Y [0] = $auto$alumacc.cc:501:replace_alu$21337 [0]
+ Consolidated identical input bits for $mux cell $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$13582:
+ Old ports: A={ $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$3\current_pc[31:0] [31:1] $auto$alumacc.cc:501:replace_alu$21337 [0] }, B=$flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1547$3364_Y, Y=$flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$13582_Y
+ New ports: A=$flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$3\current_pc[31:0] [31:1], B=$flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$add$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/picorv32_wb/picorv32.v:1547$3364_Y [31:1], Y=$flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$13582_Y [31:1]
+ New connections: $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$13582_Y [0] = $auto$alumacc.cc:501:replace_alu$21337 [0]
+ New ctrl vector for $pmux cell $flatten\softshell.\flash.\spimemio.$procmux$8851: { $auto$opt_reduce.cc:134:opt_mux$17217 $auto$opt_reduce.cc:134:opt_mux$47080 }
+ Optimizing cells in module \user_proj_example.
+ Consolidated identical input bits for $mux cell $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$7067:
+ Old ports: A={ $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$3\current_pc[31:0] [31:1] $auto$alumacc.cc:501:replace_alu$21181 [0] }, B=$flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$7065_Y, Y=$flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$7067_Y
+ New ports: A=$flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$3\current_pc[31:0] [31:1], B=$flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$7065_Y [31:1], Y=$flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$7067_Y [31:1]
+ New connections: $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$7067_Y [0] = $auto$alumacc.cc:501:replace_alu$21181 [0]
+ Consolidated identical input bits for $mux cell $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10713:
+ Old ports: A={ $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$3\current_pc[31:0] [31:1] $auto$alumacc.cc:501:replace_alu$21259 [0] }, B=$flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10711_Y, Y=$flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10713_Y
+ New ports: A=$flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$3\current_pc[31:0] [31:1], B=$flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10711_Y [31:1], Y=$flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10713_Y [31:1]
+ New connections: $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10713_Y [0] = $auto$alumacc.cc:501:replace_alu$21259 [0]
+ Consolidated identical input bits for $mux cell $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$13578:
+ Old ports: A={ $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$3\current_pc[31:0] [31:1] $auto$alumacc.cc:501:replace_alu$21337 [0] }, B=$flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$13576_Y, Y=$flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$13578_Y
+ New ports: A=$flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$3\current_pc[31:0] [31:1], B=$flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$13576_Y [31:1], Y=$flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$13578_Y [31:1]
+ New connections: $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$13578_Y [0] = $auto$alumacc.cc:501:replace_alu$21337 [0]
+ Optimizing cells in module \user_proj_example.
+ Consolidated identical input bits for $mux cell $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$7073:
+ Old ports: A=$flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$7067_Y, B={ $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$7071_Y [31:1] $auto$alumacc.cc:501:replace_alu$21181 [0] }, Y=$flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$7073_Y
+ New ports: A=$flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$7067_Y [31:1], B=$flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$7071_Y [31:1], Y=$flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$7073_Y [31:1]
+ New connections: $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$7073_Y [0] = $auto$alumacc.cc:501:replace_alu$21181 [0]
+ Consolidated identical input bits for $mux cell $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10719:
+ Old ports: A=$flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10713_Y, B={ $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10717_Y [31:1] $auto$alumacc.cc:501:replace_alu$21259 [0] }, Y=$flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10719_Y
+ New ports: A=$flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10713_Y [31:1], B=$flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10717_Y [31:1], Y=$flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10719_Y [31:1]
+ New connections: $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10719_Y [0] = $auto$alumacc.cc:501:replace_alu$21259 [0]
+ Consolidated identical input bits for $mux cell $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$13584:
+ Old ports: A=$flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$13578_Y, B={ $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$13582_Y [31:1] $auto$alumacc.cc:501:replace_alu$21337 [0] }, Y=$flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$13584_Y
+ New ports: A=$flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$13578_Y [31:1], B=$flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$13582_Y [31:1], Y=$flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$13584_Y [31:1]
+ New connections: $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$13584_Y [0] = $auto$alumacc.cc:501:replace_alu$21337 [0]
+ Optimizing cells in module \user_proj_example.
+ Consolidated identical input bits for $mux cell $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$7076:
+ Old ports: A=$flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$7073_Y, B={ $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$3\current_pc[31:0] [31:1] $auto$alumacc.cc:501:replace_alu$21181 [0] }, Y=$flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$7076_Y
+ New ports: A=$flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$7073_Y [31:1], B=$flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$3\current_pc[31:0] [31:1], Y=$flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$7076_Y [31:1]
+ New connections: $flatten\softshell.\cpus[0].core.\cpu.\picorv32_core.$procmux$7076_Y [0] = $auto$alumacc.cc:501:replace_alu$21181 [0]
+ Consolidated identical input bits for $mux cell $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10722:
+ Old ports: A=$flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10719_Y, B={ $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$3\current_pc[31:0] [31:1] $auto$alumacc.cc:501:replace_alu$21259 [0] }, Y=$flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10722_Y
+ New ports: A=$flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10719_Y [31:1], B=$flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$3\current_pc[31:0] [31:1], Y=$flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10722_Y [31:1]
+ New connections: $flatten\softshell.\cpus[1].core.\cpu.\picorv32_core.$procmux$10722_Y [0] = $auto$alumacc.cc:501:replace_alu$21259 [0]
+ Consolidated identical input bits for $mux cell $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$13587:
+ Old ports: A=$flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$13584_Y, B={ $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$3\current_pc[31:0] [31:1] $auto$alumacc.cc:501:replace_alu$21337 [0] }, Y=$flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$13587_Y
+ New ports: A=$flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$13584_Y [31:1], B=$flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$3\current_pc[31:0] [31:1], Y=$flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$13587_Y [31:1]
+ New connections: $flatten\softshell.\cpus[2].core.\cpu.\picorv32_core.$procmux$13587_Y [0] = $auto$alumacc.cc:501:replace_alu$21337 [0]
+ Optimizing cells in module \user_proj_example.
+Performed a total of 17 changes.
+
+23.20.13. Executing OPT_MERGE pass (detect identical cells).
+Finding identical cells in module `\user_proj_example'.
+Removed a total of 0 cells.
+
+23.20.14. Executing OPT_SHARE pass.
+ Found cells that share an operand and can be merged by moving the $mux $auto$opt_share.cc:241:merge_operators$47034 in front of them:
+ $auto$alumacc.cc:485:replace_alu$21135
+ $auto$alumacc.cc:485:replace_alu$21138
+
+23.20.15. Executing OPT_DFF pass (perform DFF optimizations).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[9]$42442 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[9]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[99]$42622 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[99]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[98]$42620 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[98]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[97]$42618 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[97]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[96]$42616 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[96]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[95]$42614 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[95]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[94]$42612 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[94]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[93]$42610 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[93]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[92]$42608 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[92]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[91]$42606 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[91]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[90]$42604 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[90]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[8]$42440 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[8]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[89]$42602 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[89]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[88]$42600 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[88]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[87]$42598 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[87]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[86]$42596 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[86]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[85]$42594 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[85]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[84]$42592 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[84]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[83]$42590 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[83]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[82]$42588 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[82]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[81]$42586 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[81]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[80]$42584 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[80]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[7]$42438 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[7]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[79]$42582 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[79]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[78]$42580 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[78]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[77]$42578 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[77]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[76]$42576 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[76]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[75]$42574 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[75]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[74]$42572 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[74]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[73]$42570 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[73]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[72]$42568 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[72]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[71]$42566 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[71]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[70]$42564 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[70]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[6]$42436 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[6]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[69]$42562 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[69]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[68]$42560 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[68]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[67]$42558 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[67]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[66]$42556 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[66]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[65]$42554 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[65]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[64]$42552 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[64]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[63]$42550 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[63]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[62]$42548 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[62]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[61]$42546 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[61]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[60]$42544 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[60]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[5]$42434 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[5]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[59]$42542 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[59]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[58]$42540 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[58]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[57]$42538 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[57]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[56]$42536 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[56]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[55]$42534 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[55]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[54]$42532 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[54]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[53]$42530 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[53]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[52]$42528 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[52]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[51]$42526 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[51]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[511]$43446 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[511]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[510]$43444 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[510]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[50]$42524 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[50]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[509]$43442 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[509]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[508]$43440 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[508]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[507]$43438 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[507]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[506]$43436 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[506]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[505]$43434 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[505]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[504]$43432 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[504]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[503]$43430 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[503]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[502]$43428 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[502]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[501]$43426 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[501]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[500]$43424 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[500]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[4]$42432 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[4]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[49]$42522 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[49]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[499]$43422 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[499]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[498]$43420 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[498]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[497]$43418 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[497]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[496]$43416 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[496]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[495]$43414 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[495]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[494]$43412 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[494]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[493]$43410 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[493]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[492]$43408 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[492]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[491]$43406 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[491]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[490]$43404 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[490]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[48]$42520 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[48]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[489]$43402 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[489]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[488]$43400 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[488]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[487]$43398 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[487]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[486]$43396 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[486]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[485]$43394 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[485]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[484]$43392 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[484]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[483]$43390 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[483]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[482]$43388 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[482]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[481]$43386 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[481]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[480]$43384 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[480]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[47]$42518 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[47]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[479]$43382 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[479]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[478]$43380 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[478]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[477]$43378 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[477]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[476]$43376 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[476]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[475]$43374 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[475]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[474]$43372 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[474]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[473]$43370 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[473]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[472]$43368 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[472]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[471]$43366 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[471]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[470]$43364 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[470]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[46]$42516 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[46]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[469]$43362 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[469]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[468]$43360 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[468]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[467]$43358 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[467]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[466]$43356 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[466]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[465]$43354 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[465]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[464]$43352 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[464]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[463]$43350 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[463]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[462]$43348 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[462]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[461]$43346 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[461]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[460]$43344 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[460]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[45]$42514 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[45]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[459]$43342 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[459]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[458]$43340 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[458]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[457]$43338 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[457]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[456]$43336 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[456]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[455]$43334 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[455]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[454]$43332 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[454]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[453]$43330 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[453]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[452]$43328 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[452]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[451]$43326 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[451]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[450]$43324 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[450]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[44]$42512 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[44]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[449]$43322 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[449]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[448]$43320 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[448]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[447]$43318 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[447]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[446]$43316 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[446]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[445]$43314 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[445]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[444]$43312 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[444]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[443]$43310 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[443]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[442]$43308 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[442]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[441]$43306 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[441]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[440]$43304 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[440]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[43]$42510 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[43]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[439]$43302 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[439]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[438]$43300 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[438]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[437]$43298 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[437]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[436]$43296 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[436]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[435]$43294 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[435]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[434]$43292 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[434]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[433]$43290 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[433]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[432]$43288 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[432]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[431]$43286 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[431]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[430]$43284 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[430]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[42]$42508 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[42]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[429]$43282 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[429]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[428]$43280 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[428]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[427]$43278 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[427]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[426]$43276 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[426]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[425]$43274 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[425]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[424]$43272 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[424]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[423]$43270 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[423]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[422]$43268 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[422]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[421]$43266 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[421]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[420]$43264 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[420]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[41]$42506 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[41]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[419]$43262 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[419]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[418]$43260 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[418]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[417]$43258 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[417]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[416]$43256 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[416]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[415]$43254 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[415]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[414]$43252 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[414]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[413]$43250 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[413]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[412]$43248 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[412]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[411]$43246 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[411]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[410]$43244 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[410]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[40]$42504 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[40]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[409]$43242 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[409]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[408]$43240 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[408]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[407]$43238 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[407]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[406]$43236 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[406]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[405]$43234 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[405]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[404]$43232 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[404]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[403]$43230 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[403]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[402]$43228 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[402]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[401]$43226 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[401]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[400]$43224 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[400]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[3]$42430 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[3]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[39]$42502 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[39]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[399]$43222 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[399]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[398]$43220 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[398]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[397]$43218 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[397]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[396]$43216 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[396]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[395]$43214 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[395]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[394]$43212 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[394]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[393]$43210 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[393]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[392]$43208 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[392]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[391]$43206 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[391]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[390]$43204 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[390]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[38]$42500 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[38]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[389]$43202 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[389]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[388]$43200 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[388]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[387]$43198 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[387]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[386]$43196 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[386]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[385]$43194 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[385]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[384]$43192 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[384]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[383]$43190 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[383]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[382]$43188 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[382]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[381]$43186 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[381]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[380]$43184 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[380]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[37]$42498 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[37]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[379]$43182 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[379]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[378]$43180 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[378]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[377]$43178 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[377]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[376]$43176 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[376]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[375]$43174 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[375]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[374]$43172 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[374]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[373]$43170 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[373]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[372]$43168 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[372]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[371]$43166 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[371]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[370]$43164 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[370]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[36]$42496 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[36]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[369]$43162 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[369]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[368]$43160 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[368]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[367]$43158 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[367]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[366]$43156 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[366]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[365]$43154 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[365]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[364]$43152 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[364]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[363]$43150 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[363]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[362]$43148 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[362]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[361]$43146 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[361]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[360]$43144 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[360]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[35]$42494 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[35]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[359]$43142 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[359]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[358]$43140 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[358]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[357]$43138 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[357]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[356]$43136 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[356]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[355]$43134 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[355]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[354]$43132 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[354]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[353]$43130 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[353]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[352]$43128 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[352]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[351]$43126 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[351]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[350]$43124 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[350]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[34]$42492 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[34]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[349]$43122 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[349]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[348]$43120 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[348]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[347]$43118 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[347]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[346]$43116 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[346]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[345]$43114 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[345]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[344]$43112 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[344]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[343]$43110 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[343]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[342]$43108 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[342]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[341]$43106 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[341]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[340]$43104 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[340]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[33]$42490 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[33]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[339]$43102 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[339]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[338]$43100 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[338]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[337]$43098 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[337]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[336]$43096 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[336]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[335]$43094 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[335]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[334]$43092 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[334]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[333]$43090 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[333]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[332]$43088 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[332]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[331]$43086 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[331]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[330]$43084 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[330]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[32]$42488 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[32]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[329]$43082 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[329]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[328]$43080 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[328]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[327]$43078 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[327]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[326]$43076 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[326]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[325]$43074 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[325]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[324]$43072 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[324]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[323]$43070 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[323]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[322]$43068 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[322]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[321]$43066 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[321]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[320]$43064 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[320]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[31]$42486 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[31]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[319]$43062 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[319]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[318]$43060 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[318]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[317]$43058 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[317]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[316]$43056 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[316]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[315]$43054 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[315]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[314]$43052 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[314]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[313]$43050 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[313]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[312]$43048 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[312]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[311]$43046 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[311]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[310]$43044 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[310]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[30]$42484 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[30]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[309]$43042 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[309]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[308]$43040 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[308]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[307]$43038 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[307]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[306]$43036 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[306]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[305]$43034 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[305]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[304]$43032 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[304]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[303]$43030 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[303]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[302]$43028 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[302]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[301]$43026 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[301]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[300]$43024 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[300]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[2]$42428 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[2]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[29]$42482 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[29]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[299]$43022 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[299]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[298]$43020 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[298]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[297]$43018 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[297]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[296]$43016 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[296]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[295]$43014 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[295]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[294]$43012 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[294]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[293]$43010 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[293]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[292]$43008 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[292]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[291]$43006 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[291]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[290]$43004 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[290]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[28]$42480 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[28]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[289]$43002 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[289]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[288]$43000 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[288]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[287]$42998 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[287]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[286]$42996 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[286]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[285]$42994 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[285]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[284]$42992 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[284]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[283]$42990 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[283]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[282]$42988 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[282]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[281]$42986 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[281]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[280]$42984 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[280]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[27]$42478 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[27]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[279]$42982 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[279]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[278]$42980 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[278]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[277]$42978 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[277]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[276]$42976 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[276]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[275]$42974 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[275]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[274]$42972 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[274]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[273]$42970 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[273]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[272]$42968 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[272]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[271]$42966 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[271]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[270]$42964 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[270]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[26]$42476 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[26]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[269]$42962 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[269]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[268]$42960 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[268]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[267]$42958 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[267]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[266]$42956 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[266]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[265]$42954 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[265]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[264]$42952 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[264]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[263]$42950 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[263]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[262]$42948 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[262]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[261]$42946 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[261]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[260]$42944 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[260]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[25]$42474 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[25]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[259]$42942 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[259]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[258]$42940 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[258]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[257]$42938 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[257]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[256]$42936 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[256]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[255]$42934 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[255]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[254]$42932 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[254]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[253]$42930 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[253]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[252]$42928 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[252]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[251]$42926 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[251]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[250]$42924 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[250]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[24]$42472 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[24]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[249]$42922 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[249]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[248]$42920 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[248]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[247]$42918 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[247]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[246]$42916 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[246]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[245]$42914 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[245]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[244]$42912 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[244]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[243]$42910 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[243]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[242]$42908 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[242]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[241]$42906 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[241]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[240]$42904 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[240]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[23]$42470 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[23]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[239]$42902 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[239]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[238]$42900 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[238]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[237]$42898 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[237]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[236]$42896 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[236]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[235]$42894 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[235]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[234]$42892 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[234]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[233]$42890 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[233]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[232]$42888 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[232]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[231]$42886 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[231]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[230]$42884 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[230]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[22]$42468 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[22]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[229]$42882 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[229]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[228]$42880 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[228]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[227]$42878 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[227]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[226]$42876 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[226]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[225]$42874 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[225]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[224]$42872 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[224]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[223]$42870 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[223]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[222]$42868 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[222]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[221]$42866 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[221]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[220]$42864 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[220]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[21]$42466 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[21]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[219]$42862 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[219]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[218]$42860 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[218]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[217]$42858 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[217]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[216]$42856 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[216]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[215]$42854 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[215]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[214]$42852 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[214]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[213]$42850 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[213]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[212]$42848 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[212]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[211]$42846 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[211]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[210]$42844 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[210]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[20]$42464 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[20]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[209]$42842 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[209]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[208]$42840 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[208]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[207]$42838 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[207]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[206]$42836 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[206]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[205]$42834 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[205]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[204]$42832 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[204]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[203]$42830 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[203]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[202]$42828 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[202]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[201]$42826 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[201]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[200]$42824 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[200]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[1]$42426 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[1]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[19]$42462 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[19]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[199]$42822 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[199]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[198]$42820 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[198]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[197]$42818 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[197]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[196]$42816 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[196]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[195]$42814 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[195]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[194]$42812 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[194]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[193]$42810 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[193]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[192]$42808 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[192]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[191]$42806 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[191]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[190]$42804 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[190]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[18]$42460 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[18]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[189]$42802 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[189]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[188]$42800 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[188]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[187]$42798 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[187]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[186]$42796 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[186]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[185]$42794 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[185]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[184]$42792 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[184]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[183]$42790 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[183]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[182]$42788 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[182]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[181]$42786 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[181]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[180]$42784 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[180]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[17]$42458 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[17]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[179]$42782 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[179]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[178]$42780 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[178]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[177]$42778 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[177]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[176]$42776 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[176]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[175]$42774 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[175]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[174]$42772 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[174]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[173]$42770 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[173]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[172]$42768 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[172]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[171]$42766 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[171]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[170]$42764 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[170]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[16]$42456 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[16]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[169]$42762 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[169]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[168]$42760 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[168]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[167]$42758 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[167]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[166]$42756 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[166]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[165]$42754 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[165]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[164]$42752 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[164]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[163]$42750 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[163]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[162]$42748 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[162]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[161]$42746 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[161]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[160]$42744 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[160]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[15]$42454 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[15]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[159]$42742 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[159]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[158]$42740 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[158]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[157]$42738 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[157]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[156]$42736 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[156]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[155]$42734 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[155]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[154]$42732 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[154]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[153]$42730 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[153]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[152]$42728 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[152]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[151]$42726 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[151]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[150]$42724 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[150]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[14]$42452 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[14]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[149]$42722 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[149]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[148]$42720 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[148]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[147]$42718 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[147]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[146]$42716 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[146]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[145]$42714 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[145]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[144]$42712 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[144]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[143]$42710 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[143]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[142]$42708 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[142]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[141]$42706 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[141]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[140]$42704 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[140]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[13]$42450 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[13]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[139]$42702 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[139]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[138]$42700 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[138]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[137]$42698 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[137]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[136]$42696 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[136]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[135]$42694 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[135]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[134]$42692 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[134]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[133]$42690 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[133]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[132]$42688 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[132]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[131]$42686 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[131]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[130]$42684 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[130]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[12]$42448 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[12]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[129]$42682 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[129]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[128]$42680 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[128]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[127]$42678 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[127]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[126]$42676 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[126]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[125]$42674 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[125]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[124]$42672 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[124]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[123]$42670 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[123]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[122]$42668 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[122]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[121]$42666 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[121]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[120]$42664 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[120]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[11]$42446 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[11]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[119]$42662 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[119]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[118]$42660 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[118]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[117]$42658 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[117]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[116]$42656 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[116]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[115]$42654 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[115]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[114]$42652 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[114]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[113]$42650 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[113]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[112]$42648 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[112]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[111]$42646 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[111]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[110]$42644 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[110]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[10]$42444 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[10]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[109]$42642 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[109]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[108]$42640 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[108]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[107]$42638 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[107]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[106]$42636 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[106]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[105]$42634 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[105]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[104]$42632 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[104]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[103]$42630 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[103]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[102]$42628 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[102]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[101]$42626 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[101]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[100]$42624 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[100]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram3[0]$42424 ($dff) from module user_proj_example (D = { \softshell.flash.spimemio.cfgreg_di [31] \softshell.shared_mem.ram.din [30:24] }, Q = \softshell.shared_mem.ram.ram3[0]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[9]$37833 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[9]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[99]$38013 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[99]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[98]$38011 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[98]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[97]$38009 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[97]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[96]$38007 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[96]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[95]$38005 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[95]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[94]$38003 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[94]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[93]$38001 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[93]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[92]$37999 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[92]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[91]$37997 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[91]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[90]$37995 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[90]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[8]$37831 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[8]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[89]$37993 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[89]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[88]$37991 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[88]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[87]$37989 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[87]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[86]$37987 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[86]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[85]$37985 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[85]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[84]$37983 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[84]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[83]$37981 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[83]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[82]$37979 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[82]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[81]$37977 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[81]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[80]$37975 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[80]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[7]$37829 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[7]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[79]$37973 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[79]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[78]$37971 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[78]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[77]$37969 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[77]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[76]$37967 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[76]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[75]$37965 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[75]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[74]$37963 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[74]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[73]$37961 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[73]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[72]$37959 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[72]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[71]$37957 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[71]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[70]$37955 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[70]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[6]$37827 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[6]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[69]$37953 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[69]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[68]$37951 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[68]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[67]$37949 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[67]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[66]$37947 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[66]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[65]$37945 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[65]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[64]$37943 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[64]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[63]$37941 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[63]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[62]$37939 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[62]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[61]$37937 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[61]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[60]$37935 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[60]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[5]$37825 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[5]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[59]$37933 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[59]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[58]$37931 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[58]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[57]$37929 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[57]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[56]$37927 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[56]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[55]$37925 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[55]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[54]$37923 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[54]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[53]$37921 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[53]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[52]$37919 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[52]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[51]$37917 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[51]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[511]$38837 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[511]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[510]$38835 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[510]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[50]$37915 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[50]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[509]$38833 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[509]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[508]$38831 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[508]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[507]$38829 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[507]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[506]$38827 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[506]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[505]$38825 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[505]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[504]$38823 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[504]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[503]$38821 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[503]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[502]$38819 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[502]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[501]$38817 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[501]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[500]$38815 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[500]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[4]$37823 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[4]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[49]$37913 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[49]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[499]$38813 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[499]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[498]$38811 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[498]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[497]$38809 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[497]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[496]$38807 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[496]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[495]$38805 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[495]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[494]$38803 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[494]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[493]$38801 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[493]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[492]$38799 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[492]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[491]$38797 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[491]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[490]$38795 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[490]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[48]$37911 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[48]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[489]$38793 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[489]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[488]$38791 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[488]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[487]$38789 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[487]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[486]$38787 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[486]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[485]$38785 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[485]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[484]$38783 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[484]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[483]$38781 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[483]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[482]$38779 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[482]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[481]$38777 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[481]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[480]$38775 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[480]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[47]$37909 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[47]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[479]$38773 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[479]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[478]$38771 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[478]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[477]$38769 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[477]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[476]$38767 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[476]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[475]$38765 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[475]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[474]$38763 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[474]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[473]$38761 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[473]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[472]$38759 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[472]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[471]$38757 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[471]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[470]$38755 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[470]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[46]$37907 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[46]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[469]$38753 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[469]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[468]$38751 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[468]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[467]$38749 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[467]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[466]$38747 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[466]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[465]$38745 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[465]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[464]$38743 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[464]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[463]$38741 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[463]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[462]$38739 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[462]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[461]$38737 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[461]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[460]$38735 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[460]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[45]$37905 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[45]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[459]$38733 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[459]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[458]$38731 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[458]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[457]$38729 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[457]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[456]$38727 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[456]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[455]$38725 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[455]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[454]$38723 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[454]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[453]$38721 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[453]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[452]$38719 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[452]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[451]$38717 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[451]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[450]$38715 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[450]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[44]$37903 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[44]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[449]$38713 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[449]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[448]$38711 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[448]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[447]$38709 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[447]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[446]$38707 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[446]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[445]$38705 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[445]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[444]$38703 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[444]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[443]$38701 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[443]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[442]$38699 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[442]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[441]$38697 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[441]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[440]$38695 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[440]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[43]$37901 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[43]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[439]$38693 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[439]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[438]$38691 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[438]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[437]$38689 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[437]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[436]$38687 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[436]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[435]$38685 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[435]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[434]$38683 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[434]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[433]$38681 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[433]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[432]$38679 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[432]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[431]$38677 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[431]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[430]$38675 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[430]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[42]$37899 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[42]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[429]$38673 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[429]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[428]$38671 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[428]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[427]$38669 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[427]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[426]$38667 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[426]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[425]$38665 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[425]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[424]$38663 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[424]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[423]$38661 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[423]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[422]$38659 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[422]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[421]$38657 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[421]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[420]$38655 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[420]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[41]$37897 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[41]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[419]$38653 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[419]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[418]$38651 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[418]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[417]$38649 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[417]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[416]$38647 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[416]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[415]$38645 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[415]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[414]$38643 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[414]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[413]$38641 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[413]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[412]$38639 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[412]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[411]$38637 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[411]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[410]$38635 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[410]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[40]$37895 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[40]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[409]$38633 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[409]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[408]$38631 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[408]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[407]$38629 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[407]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[406]$38627 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[406]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[405]$38625 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[405]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[404]$38623 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[404]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[403]$38621 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[403]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[402]$38619 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[402]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[401]$38617 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[401]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[400]$38615 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[400]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[3]$37821 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[3]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[39]$37893 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[39]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[399]$38613 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[399]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[398]$38611 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[398]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[397]$38609 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[397]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[396]$38607 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[396]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[395]$38605 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[395]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[394]$38603 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[394]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[393]$38601 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[393]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[392]$38599 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[392]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[391]$38597 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[391]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[390]$38595 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[390]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[38]$37891 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[38]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[389]$38593 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[389]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[388]$38591 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[388]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[387]$38589 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[387]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[386]$38587 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[386]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[385]$38585 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[385]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[384]$38583 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[384]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[383]$38581 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[383]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[382]$38579 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[382]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[381]$38577 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[381]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[380]$38575 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[380]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[37]$37889 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[37]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[379]$38573 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[379]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[378]$38571 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[378]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[377]$38569 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[377]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[376]$38567 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[376]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[375]$38565 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[375]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[374]$38563 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[374]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[373]$38561 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[373]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[372]$38559 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[372]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[371]$38557 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[371]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[370]$38555 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[370]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[36]$37887 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[36]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[369]$38553 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[369]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[368]$38551 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[368]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[367]$38549 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[367]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[366]$38547 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[366]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[365]$38545 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[365]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[364]$38543 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[364]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[363]$38541 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[363]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[362]$38539 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[362]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[361]$38537 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[361]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[360]$38535 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[360]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[35]$37885 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[35]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[359]$38533 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[359]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[358]$38531 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[358]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[357]$38529 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[357]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[356]$38527 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[356]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[355]$38525 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[355]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[354]$38523 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[354]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[353]$38521 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[353]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[352]$38519 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[352]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[351]$38517 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[351]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[350]$38515 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[350]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[34]$37883 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[34]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[349]$38513 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[349]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[348]$38511 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[348]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[347]$38509 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[347]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[346]$38507 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[346]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[345]$38505 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[345]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[344]$38503 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[344]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[343]$38501 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[343]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[342]$38499 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[342]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[341]$38497 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[341]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[340]$38495 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[340]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[33]$37881 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[33]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[339]$38493 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[339]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[338]$38491 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[338]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[337]$38489 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[337]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[336]$38487 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[336]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[335]$38485 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[335]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[334]$38483 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[334]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[333]$38481 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[333]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[332]$38479 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[332]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[331]$38477 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[331]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[330]$38475 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[330]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[32]$37879 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[32]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[329]$38473 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[329]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[328]$38471 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[328]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[327]$38469 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[327]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[326]$38467 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[326]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[325]$38465 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[325]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[324]$38463 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[324]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[323]$38461 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[323]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[322]$38459 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[322]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[321]$38457 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[321]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[320]$38455 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[320]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[31]$37877 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[31]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[319]$38453 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[319]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[318]$38451 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[318]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[317]$38449 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[317]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[316]$38447 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[316]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[315]$38445 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[315]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[314]$38443 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[314]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[313]$38441 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[313]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[312]$38439 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[312]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[311]$38437 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[311]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[310]$38435 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[310]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[30]$37875 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[30]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[309]$38433 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[309]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[308]$38431 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[308]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[307]$38429 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[307]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[306]$38427 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[306]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[305]$38425 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[305]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[304]$38423 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[304]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[303]$38421 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[303]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[302]$38419 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[302]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[301]$38417 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[301]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[300]$38415 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[300]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[2]$37819 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[2]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[29]$37873 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[29]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[299]$38413 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[299]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[298]$38411 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[298]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[297]$38409 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[297]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[296]$38407 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[296]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[295]$38405 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[295]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[294]$38403 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[294]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[293]$38401 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[293]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[292]$38399 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[292]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[291]$38397 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[291]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[290]$38395 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[290]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[28]$37871 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[28]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[289]$38393 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[289]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[288]$38391 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[288]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[287]$38389 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[287]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[286]$38387 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[286]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[285]$38385 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[285]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[284]$38383 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[284]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[283]$38381 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[283]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[282]$38379 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[282]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[281]$38377 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[281]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[280]$38375 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[280]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[27]$37869 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[27]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[279]$38373 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[279]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[278]$38371 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[278]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[277]$38369 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[277]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[276]$38367 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[276]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[275]$38365 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[275]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[274]$38363 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[274]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[273]$38361 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[273]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[272]$38359 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[272]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[271]$38357 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[271]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[270]$38355 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[270]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[26]$37867 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[26]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[269]$38353 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[269]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[268]$38351 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[268]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[267]$38349 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[267]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[266]$38347 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[266]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[265]$38345 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[265]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[264]$38343 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[264]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[263]$38341 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[263]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[262]$38339 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[262]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[261]$38337 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[261]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[260]$38335 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[260]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[25]$37865 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[25]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[259]$38333 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[259]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[258]$38331 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[258]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[257]$38329 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[257]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[256]$38327 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[256]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[255]$38325 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[255]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[254]$38323 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[254]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[253]$38321 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[253]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[252]$38319 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[252]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[251]$38317 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[251]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[250]$38315 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[250]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[24]$37863 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[24]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[249]$38313 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[249]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[248]$38311 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[248]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[247]$38309 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[247]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[246]$38307 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[246]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[245]$38305 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[245]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[244]$38303 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[244]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[243]$38301 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[243]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[242]$38299 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[242]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[241]$38297 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[241]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[240]$38295 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[240]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[23]$37861 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[23]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[239]$38293 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[239]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[238]$38291 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[238]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[237]$38289 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[237]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[236]$38287 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[236]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[235]$38285 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[235]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[234]$38283 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[234]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[233]$38281 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[233]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[232]$38279 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[232]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[231]$38277 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[231]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[230]$38275 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[230]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[22]$37859 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[22]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[229]$38273 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[229]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[228]$38271 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[228]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[227]$38269 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[227]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[226]$38267 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[226]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[225]$38265 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[225]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[224]$38263 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[224]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[223]$38261 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[223]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[222]$38259 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[222]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[221]$38257 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[221]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[220]$38255 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[220]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[21]$37857 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[21]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[219]$38253 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[219]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[218]$38251 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[218]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[217]$38249 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[217]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[216]$38247 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[216]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[215]$38245 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[215]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[214]$38243 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[214]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[213]$38241 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[213]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[212]$38239 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[212]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[211]$38237 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[211]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[210]$38235 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[210]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[20]$37855 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[20]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[209]$38233 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[209]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[208]$38231 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[208]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[207]$38229 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[207]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[206]$38227 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[206]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[205]$38225 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[205]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[204]$38223 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[204]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[203]$38221 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[203]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[202]$38219 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[202]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[201]$38217 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[201]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[200]$38215 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[200]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[1]$37817 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[1]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[19]$37853 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[19]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[199]$38213 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[199]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[198]$38211 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[198]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[197]$38209 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[197]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[196]$38207 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[196]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[195]$38205 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[195]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[194]$38203 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[194]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[193]$38201 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[193]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[192]$38199 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[192]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[191]$38197 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[191]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[190]$38195 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[190]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[18]$37851 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[18]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[189]$38193 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[189]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[188]$38191 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[188]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[187]$38189 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[187]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[186]$38187 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[186]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[185]$38185 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[185]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[184]$38183 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[184]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[183]$38181 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[183]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[182]$38179 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[182]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[181]$38177 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[181]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[180]$38175 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[180]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[17]$37849 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[17]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[179]$38173 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[179]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[178]$38171 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[178]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[177]$38169 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[177]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[176]$38167 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[176]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[175]$38165 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[175]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[174]$38163 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[174]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[173]$38161 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[173]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[172]$38159 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[172]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[171]$38157 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[171]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[170]$38155 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[170]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[16]$37847 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[16]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[169]$38153 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[169]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[168]$38151 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[168]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[167]$38149 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[167]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[166]$38147 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[166]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[165]$38145 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[165]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[164]$38143 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[164]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[163]$38141 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[163]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[162]$38139 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[162]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[161]$38137 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[161]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[160]$38135 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[160]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[15]$37845 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[15]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[159]$38133 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[159]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[158]$38131 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[158]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[157]$38129 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[157]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[156]$38127 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[156]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[155]$38125 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[155]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[154]$38123 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[154]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[153]$38121 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[153]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[152]$38119 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[152]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[151]$38117 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[151]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[150]$38115 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[150]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[14]$37843 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[14]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[149]$38113 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[149]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[148]$38111 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[148]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[147]$38109 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[147]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[146]$38107 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[146]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[145]$38105 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[145]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[144]$38103 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[144]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[143]$38101 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[143]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[142]$38099 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[142]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[141]$38097 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[141]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[140]$38095 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[140]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[13]$37841 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[13]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[139]$38093 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[139]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[138]$38091 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[138]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[137]$38089 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[137]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[136]$38087 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[136]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[135]$38085 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[135]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[134]$38083 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[134]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[133]$38081 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[133]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[132]$38079 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[132]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[131]$38077 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[131]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[130]$38075 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[130]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[12]$37839 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[12]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[129]$38073 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[129]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[128]$38071 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[128]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[127]$38069 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[127]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[126]$38067 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[126]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[125]$38065 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[125]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[124]$38063 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[124]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[123]$38061 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[123]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[122]$38059 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[122]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[121]$38057 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[121]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[120]$38055 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[120]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[11]$37837 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[11]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[119]$38053 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[119]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[118]$38051 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[118]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[117]$38049 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[117]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[116]$38047 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[116]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[115]$38045 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[115]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[114]$38043 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[114]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[113]$38041 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[113]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[112]$38039 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[112]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[111]$38037 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[111]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[110]$38035 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[110]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[10]$37835 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[10]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[109]$38033 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[109]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[108]$38031 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[108]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[107]$38029 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[107]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[106]$38027 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[106]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[105]$38025 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[105]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[104]$38023 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[104]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[103]$38021 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[103]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[102]$38019 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[102]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[101]$38017 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[101]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[100]$38015 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[100]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram2[0]$37815 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [23] \softshell.flash.spimemio.cfgreg_di [22:16] }, Q = \softshell.shared_mem.ram.ram2[0]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[9]$33224 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[9]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[99]$33404 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[99]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[98]$33402 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[98]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[97]$33400 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[97]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[96]$33398 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[96]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[95]$33396 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[95]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[94]$33394 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[94]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[93]$33392 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[93]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[92]$33390 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[92]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[91]$33388 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[91]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[90]$33386 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[90]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[8]$33222 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[8]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[89]$33384 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[89]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[88]$33382 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[88]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[87]$33380 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[87]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[86]$33378 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[86]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[85]$33376 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[85]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[84]$33374 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[84]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[83]$33372 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[83]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[82]$33370 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[82]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[81]$33368 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[81]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[80]$33366 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[80]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[7]$33220 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[7]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[79]$33364 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[79]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[78]$33362 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[78]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[77]$33360 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[77]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[76]$33358 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[76]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[75]$33356 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[75]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[74]$33354 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[74]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[73]$33352 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[73]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[72]$33350 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[72]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[71]$33348 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[71]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[70]$33346 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[70]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[6]$33218 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[6]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[69]$33344 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[69]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[68]$33342 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[68]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[67]$33340 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[67]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[66]$33338 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[66]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[65]$33336 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[65]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[64]$33334 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[64]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[63]$33332 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[63]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[62]$33330 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[62]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[61]$33328 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[61]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[60]$33326 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[60]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[5]$33216 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[5]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[59]$33324 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[59]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[58]$33322 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[58]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[57]$33320 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[57]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[56]$33318 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[56]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[55]$33316 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[55]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[54]$33314 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[54]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[53]$33312 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[53]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[52]$33310 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[52]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[51]$33308 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[51]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[511]$34228 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[511]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[510]$34226 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[510]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[50]$33306 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[50]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[509]$34224 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[509]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[508]$34222 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[508]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[507]$34220 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[507]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[506]$34218 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[506]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[505]$34216 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[505]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[504]$34214 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[504]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[503]$34212 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[503]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[502]$34210 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[502]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[501]$34208 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[501]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[500]$34206 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[500]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[4]$33214 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[4]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[49]$33304 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[49]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[499]$34204 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[499]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[498]$34202 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[498]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[497]$34200 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[497]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[496]$34198 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[496]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[495]$34196 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[495]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[494]$34194 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[494]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[493]$34192 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[493]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[492]$34190 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[492]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[491]$34188 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[491]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[490]$34186 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[490]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[48]$33302 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[48]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[489]$34184 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[489]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[488]$34182 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[488]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[487]$34180 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[487]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[486]$34178 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[486]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[485]$34176 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[485]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[484]$34174 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[484]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[483]$34172 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[483]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[482]$34170 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[482]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[481]$34168 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[481]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[480]$34166 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[480]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[47]$33300 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[47]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[479]$34164 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[479]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[478]$34162 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[478]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[477]$34160 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[477]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[476]$34158 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[476]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[475]$34156 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[475]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[474]$34154 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[474]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[473]$34152 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[473]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[472]$34150 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[472]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[471]$34148 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[471]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[470]$34146 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[470]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[46]$33298 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[46]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[469]$34144 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[469]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[468]$34142 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[468]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[467]$34140 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[467]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[466]$34138 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[466]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[465]$34136 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[465]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[464]$34134 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[464]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[463]$34132 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[463]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[462]$34130 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[462]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[461]$34128 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[461]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[460]$34126 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[460]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[45]$33296 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[45]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[459]$34124 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[459]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[458]$34122 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[458]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[457]$34120 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[457]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[456]$34118 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[456]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[455]$34116 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[455]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[454]$34114 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[454]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[453]$34112 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[453]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[452]$34110 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[452]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[451]$34108 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[451]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[450]$34106 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[450]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[44]$33294 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[44]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[449]$34104 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[449]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[448]$34102 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[448]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[447]$34100 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[447]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[446]$34098 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[446]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[445]$34096 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[445]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[444]$34094 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[444]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[443]$34092 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[443]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[442]$34090 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[442]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[441]$34088 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[441]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[440]$34086 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[440]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[43]$33292 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[43]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[439]$34084 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[439]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[438]$34082 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[438]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[437]$34080 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[437]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[436]$34078 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[436]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[435]$34076 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[435]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[434]$34074 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[434]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[433]$34072 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[433]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[432]$34070 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[432]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[431]$34068 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[431]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[430]$34066 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[430]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[42]$33290 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[42]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[429]$34064 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[429]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[428]$34062 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[428]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[427]$34060 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[427]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[426]$34058 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[426]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[425]$34056 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[425]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[424]$34054 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[424]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[423]$34052 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[423]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[422]$34050 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[422]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[421]$34048 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[421]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[420]$34046 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[420]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[41]$33288 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[41]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[419]$34044 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[419]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[418]$34042 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[418]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[417]$34040 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[417]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[416]$34038 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[416]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[415]$34036 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[415]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[414]$34034 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[414]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[413]$34032 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[413]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[412]$34030 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[412]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[411]$34028 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[411]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[410]$34026 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[410]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[40]$33286 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[40]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[409]$34024 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[409]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[408]$34022 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[408]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[407]$34020 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[407]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[406]$34018 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[406]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[405]$34016 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[405]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[404]$34014 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[404]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[403]$34012 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[403]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[402]$34010 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[402]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[401]$34008 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[401]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[400]$34006 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[400]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[3]$33212 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[3]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[39]$33284 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[39]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[399]$34004 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[399]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[398]$34002 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[398]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[397]$34000 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[397]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[396]$33998 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[396]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[395]$33996 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[395]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[394]$33994 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[394]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[393]$33992 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[393]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[392]$33990 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[392]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[391]$33988 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[391]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[390]$33986 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[390]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[38]$33282 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[38]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[389]$33984 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[389]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[388]$33982 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[388]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[387]$33980 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[387]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[386]$33978 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[386]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[385]$33976 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[385]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[384]$33974 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[384]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[383]$33972 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[383]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[382]$33970 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[382]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[381]$33968 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[381]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[380]$33966 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[380]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[37]$33280 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[37]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[379]$33964 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[379]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[378]$33962 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[378]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[377]$33960 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[377]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[376]$33958 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[376]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[375]$33956 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[375]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[374]$33954 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[374]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[373]$33952 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[373]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[372]$33950 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[372]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[371]$33948 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[371]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[370]$33946 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[370]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[36]$33278 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[36]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[369]$33944 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[369]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[368]$33942 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[368]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[367]$33940 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[367]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[366]$33938 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[366]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[365]$33936 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[365]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[364]$33934 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[364]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[363]$33932 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[363]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[362]$33930 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[362]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[361]$33928 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[361]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[360]$33926 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[360]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[35]$33276 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[35]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[359]$33924 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[359]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[358]$33922 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[358]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[357]$33920 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[357]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[356]$33918 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[356]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[355]$33916 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[355]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[354]$33914 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[354]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[353]$33912 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[353]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[352]$33910 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[352]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[351]$33908 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[351]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[350]$33906 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[350]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[34]$33274 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[34]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[349]$33904 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[349]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[348]$33902 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[348]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[347]$33900 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[347]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[346]$33898 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[346]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[345]$33896 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[345]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[344]$33894 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[344]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[343]$33892 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[343]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[342]$33890 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[342]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[341]$33888 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[341]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[340]$33886 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[340]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[33]$33272 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[33]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[339]$33884 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[339]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[338]$33882 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[338]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[337]$33880 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[337]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[336]$33878 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[336]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[335]$33876 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[335]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[334]$33874 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[334]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[333]$33872 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[333]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[332]$33870 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[332]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[331]$33868 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[331]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[330]$33866 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[330]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[32]$33270 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[32]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[329]$33864 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[329]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[328]$33862 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[328]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[327]$33860 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[327]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[326]$33858 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[326]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[325]$33856 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[325]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[324]$33854 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[324]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[323]$33852 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[323]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[322]$33850 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[322]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[321]$33848 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[321]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[320]$33846 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[320]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[31]$33268 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[31]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[319]$33844 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[319]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[318]$33842 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[318]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[317]$33840 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[317]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[316]$33838 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[316]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[315]$33836 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[315]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[314]$33834 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[314]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[313]$33832 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[313]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[312]$33830 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[312]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[311]$33828 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[311]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[310]$33826 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[310]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[30]$33266 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[30]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[309]$33824 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[309]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[308]$33822 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[308]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[307]$33820 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[307]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[306]$33818 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[306]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[305]$33816 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[305]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[304]$33814 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[304]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[303]$33812 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[303]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[302]$33810 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[302]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[301]$33808 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[301]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[300]$33806 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[300]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[2]$33210 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[2]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[29]$33264 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[29]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[299]$33804 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[299]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[298]$33802 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[298]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[297]$33800 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[297]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[296]$33798 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[296]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[295]$33796 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[295]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[294]$33794 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[294]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[293]$33792 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[293]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[292]$33790 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[292]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[291]$33788 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[291]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[290]$33786 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[290]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[28]$33262 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[28]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[289]$33784 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[289]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[288]$33782 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[288]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[287]$33780 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[287]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[286]$33778 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[286]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[285]$33776 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[285]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[284]$33774 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[284]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[283]$33772 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[283]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[282]$33770 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[282]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[281]$33768 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[281]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[280]$33766 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[280]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[27]$33260 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[27]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[279]$33764 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[279]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[278]$33762 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[278]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[277]$33760 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[277]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[276]$33758 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[276]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[275]$33756 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[275]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[274]$33754 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[274]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[273]$33752 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[273]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[272]$33750 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[272]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[271]$33748 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[271]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[270]$33746 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[270]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[26]$33258 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[26]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[269]$33744 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[269]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[268]$33742 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[268]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[267]$33740 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[267]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[266]$33738 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[266]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[265]$33736 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[265]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[264]$33734 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[264]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[263]$33732 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[263]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[262]$33730 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[262]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[261]$33728 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[261]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[260]$33726 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[260]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[25]$33256 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[25]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[259]$33724 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[259]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[258]$33722 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[258]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[257]$33720 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[257]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[256]$33718 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[256]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[255]$33716 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[255]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[254]$33714 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[254]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[253]$33712 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[253]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[252]$33710 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[252]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[251]$33708 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[251]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[250]$33706 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[250]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[24]$33254 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[24]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[249]$33704 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[249]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[248]$33702 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[248]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[247]$33700 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[247]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[246]$33698 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[246]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[245]$33696 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[245]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[244]$33694 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[244]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[243]$33692 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[243]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[242]$33690 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[242]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[241]$33688 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[241]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[240]$33686 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[240]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[23]$33252 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[23]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[239]$33684 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[239]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[238]$33682 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[238]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[237]$33680 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[237]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[236]$33678 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[236]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[235]$33676 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[235]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[234]$33674 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[234]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[233]$33672 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[233]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[232]$33670 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[232]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[231]$33668 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[231]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[230]$33666 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[230]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[22]$33250 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[22]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[229]$33664 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[229]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[228]$33662 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[228]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[227]$33660 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[227]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[226]$33658 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[226]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[225]$33656 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[225]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[224]$33654 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[224]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[223]$33652 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[223]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[222]$33650 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[222]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[221]$33648 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[221]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[220]$33646 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[220]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[21]$33248 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[21]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[219]$33644 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[219]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[218]$33642 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[218]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[217]$33640 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[217]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[216]$33638 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[216]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[215]$33636 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[215]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[214]$33634 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[214]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[213]$33632 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[213]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[212]$33630 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[212]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[211]$33628 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[211]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[210]$33626 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[210]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[20]$33246 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[20]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[209]$33624 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[209]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[208]$33622 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[208]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[207]$33620 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[207]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[206]$33618 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[206]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[205]$33616 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[205]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[204]$33614 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[204]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[203]$33612 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[203]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[202]$33610 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[202]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[201]$33608 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[201]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[200]$33606 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[200]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[1]$33208 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[1]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[19]$33244 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[19]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[199]$33604 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[199]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[198]$33602 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[198]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[197]$33600 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[197]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[196]$33598 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[196]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[195]$33596 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[195]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[194]$33594 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[194]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[193]$33592 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[193]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[192]$33590 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[192]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[191]$33588 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[191]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[190]$33586 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[190]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[18]$33242 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[18]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[189]$33584 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[189]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[188]$33582 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[188]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[187]$33580 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[187]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[186]$33578 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[186]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[185]$33576 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[185]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[184]$33574 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[184]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[183]$33572 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[183]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[182]$33570 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[182]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[181]$33568 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[181]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[180]$33566 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[180]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[17]$33240 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[17]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[179]$33564 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[179]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[178]$33562 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[178]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[177]$33560 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[177]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[176]$33558 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[176]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[175]$33556 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[175]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[174]$33554 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[174]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[173]$33552 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[173]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[172]$33550 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[172]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[171]$33548 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[171]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[170]$33546 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[170]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[16]$33238 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[16]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[169]$33544 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[169]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[168]$33542 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[168]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[167]$33540 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[167]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[166]$33538 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[166]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[165]$33536 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[165]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[164]$33534 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[164]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[163]$33532 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[163]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[162]$33530 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[162]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[161]$33528 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[161]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[160]$33526 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[160]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[15]$33236 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[15]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[159]$33524 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[159]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[158]$33522 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[158]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[157]$33520 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[157]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[156]$33518 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[156]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[155]$33516 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[155]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[154]$33514 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[154]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[153]$33512 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[153]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[152]$33510 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[152]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[151]$33508 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[151]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[150]$33506 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[150]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[14]$33234 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[14]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[149]$33504 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[149]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[148]$33502 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[148]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[147]$33500 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[147]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[146]$33498 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[146]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[145]$33496 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[145]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[144]$33494 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[144]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[143]$33492 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[143]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[142]$33490 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[142]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[141]$33488 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[141]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[140]$33486 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[140]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[13]$33232 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[13]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[139]$33484 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[139]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[138]$33482 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[138]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[137]$33480 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[137]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[136]$33478 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[136]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[135]$33476 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[135]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[134]$33474 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[134]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[133]$33472 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[133]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[132]$33470 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[132]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[131]$33468 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[131]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[130]$33466 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[130]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[12]$33230 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[12]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[129]$33464 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[129]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[128]$33462 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[128]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[127]$33460 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[127]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[126]$33458 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[126]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[125]$33456 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[125]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[124]$33454 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[124]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[123]$33452 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[123]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[122]$33450 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[122]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[121]$33448 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[121]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[120]$33446 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[120]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[11]$33228 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[11]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[119]$33444 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[119]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[118]$33442 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[118]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[117]$33440 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[117]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[116]$33438 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[116]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[115]$33436 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[115]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[114]$33434 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[114]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[113]$33432 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[113]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[112]$33430 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[112]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[111]$33428 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[111]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[110]$33426 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[110]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[10]$33226 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[10]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[109]$33424 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[109]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[108]$33422 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[108]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[107]$33420 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[107]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[106]$33418 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[106]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[105]$33416 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[105]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[104]$33414 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[104]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[103]$33412 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[103]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[102]$33410 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[102]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[101]$33408 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[101]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[100]$33406 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[100]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram1[0]$33206 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [15:12] \softshell.flash.spimemio.cfgreg_di [11:8] }, Q = \softshell.shared_mem.ram.ram1[0]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[9]$27411 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[9]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[99]$27591 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[99]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[98]$27589 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[98]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[97]$27587 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[97]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[96]$27585 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[96]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[95]$27583 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[95]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[94]$27581 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[94]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[93]$27579 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[93]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[92]$27577 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[92]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[91]$27575 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[91]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[90]$27573 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[90]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[8]$27409 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[8]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[89]$27571 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[89]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[88]$27569 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[88]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[87]$27567 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[87]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[86]$27565 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[86]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[85]$27563 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[85]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[84]$27561 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[84]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[83]$27559 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[83]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[82]$27557 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[82]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[81]$27555 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[81]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[80]$27553 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[80]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[7]$27407 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[7]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[79]$27551 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[79]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[78]$27549 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[78]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[77]$27547 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[77]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[76]$27545 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[76]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[75]$27543 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[75]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[74]$27541 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[74]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[73]$27539 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[73]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[72]$27537 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[72]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[71]$27535 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[71]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[70]$27533 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[70]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[6]$27405 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[6]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[69]$27531 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[69]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[68]$27529 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[68]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[67]$27527 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[67]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[66]$27525 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[66]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[65]$27523 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[65]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[64]$27521 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[64]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[63]$27519 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[63]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[62]$27517 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[62]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[61]$27515 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[61]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[60]$27513 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[60]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[5]$27403 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[5]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[59]$27511 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[59]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[58]$27509 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[58]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[57]$27507 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[57]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[56]$27505 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[56]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[55]$27503 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[55]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[54]$27501 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[54]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[53]$27499 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[53]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[52]$27497 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[52]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[51]$27495 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[51]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[511]$28415 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[511]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[510]$28413 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[510]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[50]$27493 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[50]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[509]$28411 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[509]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[508]$28409 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[508]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[507]$28407 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[507]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[506]$28405 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[506]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[505]$28403 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[505]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[504]$28401 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[504]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[503]$28399 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[503]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[502]$28397 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[502]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[501]$28395 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[501]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[500]$28393 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[500]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[4]$27401 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[4]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[49]$27491 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[49]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[499]$28391 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[499]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[498]$28389 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[498]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[497]$28387 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[497]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[496]$28385 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[496]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[495]$28383 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[495]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[494]$28381 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[494]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[493]$28379 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[493]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[492]$28377 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[492]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[491]$28375 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[491]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[490]$28373 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[490]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[48]$27489 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[48]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[489]$28371 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[489]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[488]$28369 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[488]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[487]$28367 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[487]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[486]$28365 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[486]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[485]$28363 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[485]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[484]$28361 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[484]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[483]$28359 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[483]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[482]$28357 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[482]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[481]$28355 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[481]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[480]$28353 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[480]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[47]$27487 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[47]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[479]$28351 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[479]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[478]$28349 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[478]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[477]$28347 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[477]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[476]$28345 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[476]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[475]$28343 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[475]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[474]$28341 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[474]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[473]$28339 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[473]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[472]$28337 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[472]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[471]$28335 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[471]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[470]$28333 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[470]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[46]$27485 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[46]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[469]$28331 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[469]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[468]$28329 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[468]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[467]$28327 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[467]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[466]$28325 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[466]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[465]$28323 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[465]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[464]$28321 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[464]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[463]$28319 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[463]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[462]$28317 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[462]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[461]$28315 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[461]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[460]$28313 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[460]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[45]$27483 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[45]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[459]$28311 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[459]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[458]$28309 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[458]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[457]$28307 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[457]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[456]$28305 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[456]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[455]$28303 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[455]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[454]$28301 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[454]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[453]$28299 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[453]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[452]$28297 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[452]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[451]$28295 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[451]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[450]$28293 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[450]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[44]$27481 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[44]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[449]$28291 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[449]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[448]$28289 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[448]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[447]$28287 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[447]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[446]$28285 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[446]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[445]$28283 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[445]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[444]$28281 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[444]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[443]$28279 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[443]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[442]$28277 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[442]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[441]$28275 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[441]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[440]$28273 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[440]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[43]$27479 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[43]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[439]$28271 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[439]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[438]$28269 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[438]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[437]$28267 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[437]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[436]$28265 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[436]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[435]$28263 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[435]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[434]$28261 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[434]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[433]$28259 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[433]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[432]$28257 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[432]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[431]$28255 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[431]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[430]$28253 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[430]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[42]$27477 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[42]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[429]$28251 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[429]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[428]$28249 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[428]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[427]$28247 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[427]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[426]$28245 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[426]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[425]$28243 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[425]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[424]$28241 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[424]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[423]$28239 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[423]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[422]$28237 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[422]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[421]$28235 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[421]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[420]$28233 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[420]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[41]$27475 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[41]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[419]$28231 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[419]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[418]$28229 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[418]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[417]$28227 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[417]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[416]$28225 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[416]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[415]$28223 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[415]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[414]$28221 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[414]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[413]$28219 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[413]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[412]$28217 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[412]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[411]$28215 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[411]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[410]$28213 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[410]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[40]$27473 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[40]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[409]$28211 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[409]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[408]$28209 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[408]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[407]$28207 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[407]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[406]$28205 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[406]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[405]$28203 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[405]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[404]$28201 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[404]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[403]$28199 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[403]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[402]$28197 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[402]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[401]$28195 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[401]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[400]$28193 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[400]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[3]$27399 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[3]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[39]$27471 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[39]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[399]$28191 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[399]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[398]$28189 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[398]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[397]$28187 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[397]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[396]$28185 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[396]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[395]$28183 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[395]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[394]$28181 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[394]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[393]$28179 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[393]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[392]$28177 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[392]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[391]$28175 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[391]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[390]$28173 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[390]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[38]$27469 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[38]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[389]$28171 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[389]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[388]$28169 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[388]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[387]$28167 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[387]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[386]$28165 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[386]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[385]$28163 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[385]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[384]$28161 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[384]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[383]$28159 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[383]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[382]$28157 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[382]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[381]$28155 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[381]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[380]$28153 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[380]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[37]$27467 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[37]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[379]$28151 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[379]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[378]$28149 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[378]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[377]$28147 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[377]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[376]$28145 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[376]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[375]$28143 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[375]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[374]$28141 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[374]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[373]$28139 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[373]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[372]$28137 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[372]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[371]$28135 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[371]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[370]$28133 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[370]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[36]$27465 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[36]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[369]$28131 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[369]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[368]$28129 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[368]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[367]$28127 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[367]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[366]$28125 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[366]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[365]$28123 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[365]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[364]$28121 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[364]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[363]$28119 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[363]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[362]$28117 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[362]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[361]$28115 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[361]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[360]$28113 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[360]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[35]$27463 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[35]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[359]$28111 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[359]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[358]$28109 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[358]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[357]$28107 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[357]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[356]$28105 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[356]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[355]$28103 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[355]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[354]$28101 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[354]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[353]$28099 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[353]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[352]$28097 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[352]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[351]$28095 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[351]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[350]$28093 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[350]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[34]$27461 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[34]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[349]$28091 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[349]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[348]$28089 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[348]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[347]$28087 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[347]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[346]$28085 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[346]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[345]$28083 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[345]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[344]$28081 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[344]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[343]$28079 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[343]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[342]$28077 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[342]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[341]$28075 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[341]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[340]$28073 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[340]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[33]$27459 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[33]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[339]$28071 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[339]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[338]$28069 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[338]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[337]$28067 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[337]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[336]$28065 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[336]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[335]$28063 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[335]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[334]$28061 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[334]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[333]$28059 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[333]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[332]$28057 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[332]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[331]$28055 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[331]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[330]$28053 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[330]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[32]$27457 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[32]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[329]$28051 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[329]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[328]$28049 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[328]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[327]$28047 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[327]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[326]$28045 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[326]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[325]$28043 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[325]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[324]$28041 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[324]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[323]$28039 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[323]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[322]$28037 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[322]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[321]$28035 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[321]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[320]$28033 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[320]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[31]$27455 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[31]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[319]$28031 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[319]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[318]$28029 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[318]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[317]$28027 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[317]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[316]$28025 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[316]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[315]$28023 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[315]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[314]$28021 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[314]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[313]$28019 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[313]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[312]$28017 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[312]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[311]$28015 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[311]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[310]$28013 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[310]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[30]$27453 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[30]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[309]$28011 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[309]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[308]$28009 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[308]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[307]$28007 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[307]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[306]$28005 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[306]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[305]$28003 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[305]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[304]$28001 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[304]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[303]$27999 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[303]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[302]$27997 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[302]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[301]$27995 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[301]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[300]$27993 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[300]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[2]$27397 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[2]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[29]$27451 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[29]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[299]$27991 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[299]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[298]$27989 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[298]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[297]$27987 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[297]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[296]$27985 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[296]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[295]$27983 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[295]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[294]$27981 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[294]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[293]$27979 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[293]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[292]$27977 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[292]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[291]$27975 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[291]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[290]$27973 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[290]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[28]$27449 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[28]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[289]$27971 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[289]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[288]$27969 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[288]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[287]$27967 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[287]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[286]$27965 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[286]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[285]$27963 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[285]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[284]$27961 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[284]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[283]$27959 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[283]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[282]$27957 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[282]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[281]$27955 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[281]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[280]$27953 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[280]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[27]$27447 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[27]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[279]$27951 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[279]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[278]$27949 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[278]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[277]$27947 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[277]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[276]$27945 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[276]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[275]$27943 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[275]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[274]$27941 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[274]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[273]$27939 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[273]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[272]$27937 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[272]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[271]$27935 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[271]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[270]$27933 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[270]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[26]$27445 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[26]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[269]$27931 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[269]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[268]$27929 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[268]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[267]$27927 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[267]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[266]$27925 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[266]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[265]$27923 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[265]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[264]$27921 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[264]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[263]$27919 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[263]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[262]$27917 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[262]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[261]$27915 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[261]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[260]$27913 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[260]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[25]$27443 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[25]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[259]$27911 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[259]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[258]$27909 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[258]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[257]$27907 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[257]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[256]$27905 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[256]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[255]$27903 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[255]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[254]$27901 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[254]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[253]$27899 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[253]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[252]$27897 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[252]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[251]$27895 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[251]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[250]$27893 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[250]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[24]$27441 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[24]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[249]$27891 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[249]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[248]$27889 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[248]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[247]$27887 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[247]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[246]$27885 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[246]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[245]$27883 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[245]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[244]$27881 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[244]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[243]$27879 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[243]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[242]$27877 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[242]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[241]$27875 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[241]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[240]$27873 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[240]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[23]$27439 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[23]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[239]$27871 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[239]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[238]$27869 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[238]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[237]$27867 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[237]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[236]$27865 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[236]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[235]$27863 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[235]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[234]$27861 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[234]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[233]$27859 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[233]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[232]$27857 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[232]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[231]$27855 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[231]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[230]$27853 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[230]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[22]$27437 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[22]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[229]$27851 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[229]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[228]$27849 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[228]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[227]$27847 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[227]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[226]$27845 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[226]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[225]$27843 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[225]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[224]$27841 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[224]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[223]$27839 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[223]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[222]$27837 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[222]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[221]$27835 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[221]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[220]$27833 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[220]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[21]$27435 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[21]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[219]$27831 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[219]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[218]$27829 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[218]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[217]$27827 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[217]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[216]$27825 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[216]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[215]$27823 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[215]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[214]$27821 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[214]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[213]$27819 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[213]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[212]$27817 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[212]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[211]$27815 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[211]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[210]$27813 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[210]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[20]$27433 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[20]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[209]$27811 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[209]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[208]$27809 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[208]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[207]$27807 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[207]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[206]$27805 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[206]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[205]$27803 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[205]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[204]$27801 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[204]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[203]$27799 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[203]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[202]$27797 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[202]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[201]$27795 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[201]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[200]$27793 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[200]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[1]$27395 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[1]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[19]$27431 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[19]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[199]$27791 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[199]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[198]$27789 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[198]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[197]$27787 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[197]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[196]$27785 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[196]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[195]$27783 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[195]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[194]$27781 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[194]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[193]$27779 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[193]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[192]$27777 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[192]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[191]$27775 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[191]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[190]$27773 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[190]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[18]$27429 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[18]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[189]$27771 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[189]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[188]$27769 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[188]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[187]$27767 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[187]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[186]$27765 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[186]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[185]$27763 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[185]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[184]$27761 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[184]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[183]$27759 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[183]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[182]$27757 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[182]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[181]$27755 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[181]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[180]$27753 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[180]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[17]$27427 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[17]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[179]$27751 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[179]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[178]$27749 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[178]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[177]$27747 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[177]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[176]$27745 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[176]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[175]$27743 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[175]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[174]$27741 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[174]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[173]$27739 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[173]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[172]$27737 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[172]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[171]$27735 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[171]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[170]$27733 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[170]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[16]$27425 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[16]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[169]$27731 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[169]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[168]$27729 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[168]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[167]$27727 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[167]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[166]$27725 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[166]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[165]$27723 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[165]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[164]$27721 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[164]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[163]$27719 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[163]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[162]$27717 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[162]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[161]$27715 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[161]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[160]$27713 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[160]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[15]$27423 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[15]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[159]$27711 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[159]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[158]$27709 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[158]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[157]$27707 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[157]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[156]$27705 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[156]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[155]$27703 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[155]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[154]$27701 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[154]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[153]$27699 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[153]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[152]$27697 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[152]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[151]$27695 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[151]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[150]$27693 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[150]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[14]$27421 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[14]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[149]$27691 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[149]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[148]$27689 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[148]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[147]$27687 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[147]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[146]$27685 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[146]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[145]$27683 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[145]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[144]$27681 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[144]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[143]$27679 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[143]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[142]$27677 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[142]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[141]$27675 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[141]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[140]$27673 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[140]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[13]$27419 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[13]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[139]$27671 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[139]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[138]$27669 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[138]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[137]$27667 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[137]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[136]$27665 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[136]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[135]$27663 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[135]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[134]$27661 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[134]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[133]$27659 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[133]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[132]$27657 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[132]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[131]$27655 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[131]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[130]$27653 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[130]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[12]$27417 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[12]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[129]$27651 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[129]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[128]$27649 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[128]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[127]$27647 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[127]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[126]$27645 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[126]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[125]$27643 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[125]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[124]$27641 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[124]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[123]$27639 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[123]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[122]$27637 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[122]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[121]$27635 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[121]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[120]$27633 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[120]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[11]$27415 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[11]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[119]$27631 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[119]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[118]$27629 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[118]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[117]$27627 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[117]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[116]$27625 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[116]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[115]$27623 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[115]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[114]$27621 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[114]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[113]$27619 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[113]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[112]$27617 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[112]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[111]$27615 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[111]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[110]$27613 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[110]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[10]$27413 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[10]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[109]$27611 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[109]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[108]$27609 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[108]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[107]$27607 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[107]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[106]$27605 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[106]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[105]$27603 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[105]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[104]$27601 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[104]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[103]$27599 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[103]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[102]$27597 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[102]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[101]$27595 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[101]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[100]$27593 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[100]).
+Adding EN signal on $memory\softshell.shared_mem.ram.ram0[0]$27393 ($dff) from module user_proj_example (D = { \softshell.shared_mem.ram.din [7:6] \softshell.flash.spimemio.cfgreg_di [5:0] }, Q = \softshell.shared_mem.ram.ram0[0]).
+Adding EN signal on $memory\softshell.cpus[2].core.soc_mem.ram.ram3[9]$27122 ($dff) from module user_proj_example (D = \softshell.cpus[2].core.cpu.wbm_dat_o [31:24], Q = \softshell.cpus[2].core.soc_mem.ram.ram3[9]).
+Adding EN signal on $memory\softshell.cpus[2].core.soc_mem.ram.ram3[8]$27120 ($dff) from module user_proj_example (D = \softshell.cpus[2].core.cpu.wbm_dat_o [31:24], Q = \softshell.cpus[2].core.soc_mem.ram.ram3[8]).
+Adding EN signal on $memory\softshell.cpus[2].core.soc_mem.ram.ram3[7]$27118 ($dff) from module user_proj_example (D = \softshell.cpus[2].core.cpu.wbm_dat_o [31:24], Q = \softshell.cpus[2].core.soc_mem.ram.ram3[7]).
+Adding EN signal on $memory\softshell.cpus[2].core.soc_mem.ram.ram3[6]$27116 ($dff) from module user_proj_example (D = \softshell.cpus[2].core.cpu.wbm_dat_o [31:24], Q = \softshell.cpus[2].core.soc_mem.ram.ram3[6]).
+Adding EN signal on $memory\softshell.cpus[2].core.soc_mem.ram.ram3[5]$27114 ($dff) from module user_proj_example (D = \softshell.cpus[2].core.cpu.wbm_dat_o [31:24], Q = \softshell.cpus[2].core.soc_mem.ram.ram3[5]).
+Adding EN signal on $memory\softshell.cpus[2].core.soc_mem.ram.ram3[4]$27112 ($dff) from module user_proj_example (D = \softshell.cpus[2].core.cpu.wbm_dat_o [31:24], Q = \softshell.cpus[2].core.soc_mem.ram.ram3[4]).
+Adding EN signal on $memory\softshell.cpus[2].core.soc_mem.ram.ram3[3]$27110 ($dff) from module user_proj_example (D = \softshell.cpus[2].core.cpu.wbm_dat_o [31:24], Q = \softshell.cpus[2].core.soc_mem.ram.ram3[3]).
+Adding EN signal on $memory\softshell.cpus[2].core.soc_mem.ram.ram3[31]$27166 ($dff) from module user_proj_example (D = \softshell.cpus[2].core.cpu.wbm_dat_o [31:24], Q = \softshell.cpus[2].core.soc_mem.ram.ram3[31]).
+Adding EN signal on $memory\softshell.cpus[2].core.soc_mem.ram.ram3[30]$27164 ($dff) from module user_proj_example (D = \softshell.cpus[2].core.cpu.wbm_dat_o [31:24], Q = \softshell.cpus[2].core.soc_mem.ram.ram3[30]).
+Adding EN signal on $memory\softshell.cpus[2].core.soc_mem.ram.ram3[2]$27108 ($dff) from module user_proj_example (D = \softshell.cpus[2].core.cpu.wbm_dat_o [31:24], Q = \softshell.cpus[2].core.soc_mem.ram.ram3[2]).
+Adding EN signal on $memory\softshell.cpus[2].core.soc_mem.ram.ram3[29]$27162 ($dff) from module user_proj_example (D = \softshell.cpus[2].core.cpu.wbm_dat_o [31:24], Q = \softshell.cpus[2].core.soc_mem.ram.ram3[29]).
+Adding EN signal on $memory\softshell.cpus[2].core.soc_mem.ram.ram3[28]$27160 ($dff) from module user_proj_example (D = \softshell.cpus[2].core.cpu.wbm_dat_o [31:24], Q = \softshell.cpus[2].core.soc_mem.ram.ram3[28]).
+Adding EN signal on $memory\softshell.cpus[2].core.soc_mem.ram.ram3[27]$27158 ($dff) from module user_proj_example (D = \softshell.cpus[2].core.cpu.wbm_dat_o [31:24], Q = \softshell.cpus[2].core.soc_mem.ram.ram3[27]).
+Adding EN signal on $memory\softshell.cpus[2].core.soc_mem.ram.ram3[26]$27156 ($dff) from module user_proj_example (D = \softshell.cpus[2].core.cpu.wbm_dat_o [31:24], Q = \softshell.cpus[2].core.soc_mem.ram.ram3[26]).
+Adding EN signal on $memory\softshell.cpus[2].core.soc_mem.ram.ram3[25]$27154 ($dff) from module user_proj_example (D = \softshell.cpus[2].core.cpu.wbm_dat_o [31:24], Q = \softshell.cpus[2].core.soc_mem.ram.ram3[25]).
+Adding EN signal on $memory\softshell.cpus[2].core.soc_mem.ram.ram3[24]$27152 ($dff) from module user_proj_example (D = \softshell.cpus[2].core.cpu.wbm_dat_o [31:24], Q = \softshell.cpus[2].core.soc_mem.ram.ram3[24]).
+Adding EN signal on $memory\softshell.cpus[2].core.soc_mem.ram.ram3[23]$27150 ($dff) from module user_proj_example (D = \softshell.cpus[2].core.cpu.wbm_dat_o [31:24], Q = \softshell.cpus[2].core.soc_mem.ram.ram3[23]).
+Adding EN signal on $memory\softshell.cpus[2].core.soc_mem.ram.ram3[22]$27148 ($dff) from module user_proj_example (D = \softshell.cpus[2].core.cpu.wbm_dat_o [31:24], Q = \softshell.cpus[2].core.soc_mem.ram.ram3[22]).
+Adding EN signal on $memory\softshell.cpus[2].core.soc_mem.ram.ram3[21]$27146 ($dff) from module user_proj_example (D = \softshell.cpus[2].core.cpu.wbm_dat_o [31:24], Q = \softshell.cpus[2].core.soc_mem.ram.ram3[21]).
+Adding EN signal on $memory\softshell.cpus[2].core.soc_mem.ram.ram3[20]$27144 ($dff) from module user_proj_example (D = \softshell.cpus[2].core.cpu.wbm_dat_o [31:24], Q = \softshell.cpus[2].core.soc_mem.ram.ram3[20]).
+Adding EN signal on $memory\softshell.cpus[2].core.soc_mem.ram.ram3[1]$27106 ($dff) from module user_proj_example (D = \softshell.cpus[2].core.cpu.wbm_dat_o [31:24], Q = \softshell.cpus[2].core.soc_mem.ram.ram3[1]).
+Adding EN signal on $memory\softshell.cpus[2].core.soc_mem.ram.ram3[19]$27142 ($dff) from module user_proj_example (D = \softshell.cpus[2].core.cpu.wbm_dat_o [31:24], Q = \softshell.cpus[2].core.soc_mem.ram.ram3[19]).
+Adding EN signal on $memory\softshell.cpus[2].core.soc_mem.ram.ram3[18]$27140 ($dff) from module user_proj_example (D = \softshell.cpus[2].core.cpu.wbm_dat_o [31:24], Q = \softshell.cpus[2].core.soc_mem.ram.ram3[18]).
+Adding EN signal on $memory\softshell.cpus[2].core.soc_mem.ram.ram3[17]$27138 ($dff) from module user_proj_example (D = \softshell.cpus[2].core.cpu.wbm_dat_o [31:24], Q = \softshell.cpus[2].core.soc_mem.ram.ram3[17]).
+Adding EN signal on $memory\softshell.cpus[2].core.soc_mem.ram.ram3[16]$27136 ($dff) from module user_proj_example (D = \softshell.cpus[2].core.cpu.wbm_dat_o [31:24], Q = \softshell.cpus[2].core.soc_mem.ram.ram3[16]).
+Adding EN signal on $memory\softshell.cpus[2].core.soc_mem.ram.ram3[15]$27134 ($dff) from module user_proj_example (D = \softshell.cpus[2].core.cpu.wbm_dat_o [31:24], Q = \softshell.cpus[2].core.soc_mem.ram.ram3[15]).
+Adding EN signal on $memory\softshell.cpus[2].core.soc_mem.ram.ram3[14]$27132 ($dff) from module user_proj_example (D = \softshell.cpus[2].core.cpu.wbm_dat_o [31:24], Q = \softshell.cpus[2].core.soc_mem.ram.ram3[14]).
+Adding EN signal on $memory\softshell.cpus[2].core.soc_mem.ram.ram3[13]$27130 ($dff) from module user_proj_example (D = \softshell.cpus[2].core.cpu.wbm_dat_o [31:24], Q = \softshell.cpus[2].core.soc_mem.ram.ram3[13]).
+Adding EN signal on $memory\softshell.cpus[2].core.soc_mem.ram.ram3[12]$27128 ($dff) from module user_proj_example (D = \softshell.cpus[2].core.cpu.wbm_dat_o [31:24], Q = \softshell.cpus[2].core.soc_mem.ram.ram3[12]).
+Adding EN signal on $memory\softshell.cpus[2].core.soc_mem.ram.ram3[11]$27126 ($dff) from module user_proj_example (D = \softshell.cpus[2].core.cpu.wbm_dat_o [31:24], Q = \softshell.cpus[2].core.soc_mem.ram.ram3[11]).
+Adding EN signal on $memory\softshell.cpus[2].core.soc_mem.ram.ram3[10]$27124 ($dff) from module user_proj_example (D = \softshell.cpus[2].core.cpu.wbm_dat_o [31:24], Q = \softshell.cpus[2].core.soc_mem.ram.ram3[10]).
+Adding EN signal on $memory\softshell.cpus[2].core.soc_mem.ram.ram3[0]$27104 ($dff) from module user_proj_example (D = \softshell.cpus[2].core.cpu.wbm_dat_o [31:24], Q = \softshell.cpus[2].core.soc_mem.ram.ram3[0]).
+Adding EN signal on $memory\softshell.cpus[2].core.soc_mem.ram.ram2[9]$26833 ($dff) from module user_proj_example (D = \softshell.cpus[2].core.cpu.wbm_dat_o [23:16], Q = \softshell.cpus[2].core.soc_mem.ram.ram2[9]).
+Adding EN signal on $memory\softshell.cpus[2].core.soc_mem.ram.ram2[8]$26831 ($dff) from module user_proj_example (D = \softshell.cpus[2].core.cpu.wbm_dat_o [23:16], Q = \softshell.cpus[2].core.soc_mem.ram.ram2[8]).
+Adding EN signal on $memory\softshell.cpus[2].core.soc_mem.ram.ram2[7]$26829 ($dff) from module user_proj_example (D = \softshell.cpus[2].core.cpu.wbm_dat_o [23:16], Q = \softshell.cpus[2].core.soc_mem.ram.ram2[7]).
+Adding EN signal on $memory\softshell.cpus[2].core.soc_mem.ram.ram2[6]$26827 ($dff) from module user_proj_example (D = \softshell.cpus[2].core.cpu.wbm_dat_o [23:16], Q = \softshell.cpus[2].core.soc_mem.ram.ram2[6]).
+Adding EN signal on $memory\softshell.cpus[2].core.soc_mem.ram.ram2[5]$26825 ($dff) from module user_proj_example (D = \softshell.cpus[2].core.cpu.wbm_dat_o [23:16], Q = \softshell.cpus[2].core.soc_mem.ram.ram2[5]).
+Adding EN signal on $memory\softshell.cpus[2].core.soc_mem.ram.ram2[4]$26823 ($dff) from module user_proj_example (D = \softshell.cpus[2].core.cpu.wbm_dat_o [23:16], Q = \softshell.cpus[2].core.soc_mem.ram.ram2[4]).
+Adding EN signal on $memory\softshell.cpus[2].core.soc_mem.ram.ram2[3]$26821 ($dff) from module user_proj_example (D = \softshell.cpus[2].core.cpu.wbm_dat_o [23:16], Q = \softshell.cpus[2].core.soc_mem.ram.ram2[3]).
+Adding EN signal on $memory\softshell.cpus[2].core.soc_mem.ram.ram2[31]$26877 ($dff) from module user_proj_example (D = \softshell.cpus[2].core.cpu.wbm_dat_o [23:16], Q = \softshell.cpus[2].core.soc_mem.ram.ram2[31]).
+Adding EN signal on $memory\softshell.cpus[2].core.soc_mem.ram.ram2[30]$26875 ($dff) from module user_proj_example (D = \softshell.cpus[2].core.cpu.wbm_dat_o [23:16], Q = \softshell.cpus[2].core.soc_mem.ram.ram2[30]).
+Adding EN signal on $memory\softshell.cpus[2].core.soc_mem.ram.ram2[2]$26819 ($dff) from module user_proj_example (D = \softshell.cpus[2].core.cpu.wbm_dat_o [23:16], Q = \softshell.cpus[2].core.soc_mem.ram.ram2[2]).
+Adding EN signal on $memory\softshell.cpus[2].core.soc_mem.ram.ram2[29]$26873 ($dff) from module user_proj_example (D = \softshell.cpus[2].core.cpu.wbm_dat_o [23:16], Q = \softshell.cpus[2].core.soc_mem.ram.ram2[29]).
+Adding EN signal on $memory\softshell.cpus[2].core.soc_mem.ram.ram2[28]$26871 ($dff) from module user_proj_example (D = \softshell.cpus[2].core.cpu.wbm_dat_o [23:16], Q = \softshell.cpus[2].core.soc_mem.ram.ram2[28]).
+Adding EN signal on $memory\softshell.cpus[2].core.soc_mem.ram.ram2[27]$26869 ($dff) from module user_proj_example (D = \softshell.cpus[2].core.cpu.wbm_dat_o [23:16], Q = \softshell.cpus[2].core.soc_mem.ram.ram2[27]).
+Adding EN signal on $memory\softshell.cpus[2].core.soc_mem.ram.ram2[26]$26867 ($dff) from module user_proj_example (D = \softshell.cpus[2].core.cpu.wbm_dat_o [23:16], Q = \softshell.cpus[2].core.soc_mem.ram.ram2[26]).
+Adding EN signal on $memory\softshell.cpus[2].core.soc_mem.ram.ram2[25]$26865 ($dff) from module user_proj_example (D = \softshell.cpus[2].core.cpu.wbm_dat_o [23:16], Q = \softshell.cpus[2].core.soc_mem.ram.ram2[25]).
+Adding EN signal on $memory\softshell.cpus[2].core.soc_mem.ram.ram2[24]$26863 ($dff) from module user_proj_example (D = \softshell.cpus[2].core.cpu.wbm_dat_o [23:16], Q = \softshell.cpus[2].core.soc_mem.ram.ram2[24]).
+Adding EN signal on $memory\softshell.cpus[2].core.soc_mem.ram.ram2[23]$26861 ($dff) from module user_proj_example (D = \softshell.cpus[2].core.cpu.wbm_dat_o [23:16], Q = \softshell.cpus[2].core.soc_mem.ram.ram2[23]).
+Adding EN signal on $memory\softshell.cpus[2].core.soc_mem.ram.ram2[22]$26859 ($dff) from module user_proj_example (D = \softshell.cpus[2].core.cpu.wbm_dat_o [23:16], Q = \softshell.cpus[2].core.soc_mem.ram.ram2[22]).
+Adding EN signal on $memory\softshell.cpus[2].core.soc_mem.ram.ram2[21]$26857 ($dff) from module user_proj_example (D = \softshell.cpus[2].core.cpu.wbm_dat_o [23:16], Q = \softshell.cpus[2].core.soc_mem.ram.ram2[21]).
+Adding EN signal on $memory\softshell.cpus[2].core.soc_mem.ram.ram2[20]$26855 ($dff) from module user_proj_example (D = \softshell.cpus[2].core.cpu.wbm_dat_o [23:16], Q = \softshell.cpus[2].core.soc_mem.ram.ram2[20]).
+Adding EN signal on $memory\softshell.cpus[2].core.soc_mem.ram.ram2[1]$26817 ($dff) from module user_proj_example (D = \softshell.cpus[2].core.cpu.wbm_dat_o [23:16], Q = \softshell.cpus[2].core.soc_mem.ram.ram2[1]).
+Adding EN signal on $memory\softshell.cpus[2].core.soc_mem.ram.ram2[19]$26853 ($dff) from module user_proj_example (D = \softshell.cpus[2].core.cpu.wbm_dat_o [23:16], Q = \softshell.cpus[2].core.soc_mem.ram.ram2[19]).
+Adding EN signal on $memory\softshell.cpus[2].core.soc_mem.ram.ram2[18]$26851 ($dff) from module user_proj_example (D = \softshell.cpus[2].core.cpu.wbm_dat_o [23:16], Q = \softshell.cpus[2].core.soc_mem.ram.ram2[18]).
+Adding EN signal on $memory\softshell.cpus[2].core.soc_mem.ram.ram2[17]$26849 ($dff) from module user_proj_example (D = \softshell.cpus[2].core.cpu.wbm_dat_o [23:16], Q = \softshell.cpus[2].core.soc_mem.ram.ram2[17]).
+Adding EN signal on $memory\softshell.cpus[2].core.soc_mem.ram.ram2[16]$26847 ($dff) from module user_proj_example (D = \softshell.cpus[2].core.cpu.wbm_dat_o [23:16], Q = \softshell.cpus[2].core.soc_mem.ram.ram2[16]).
+Adding EN signal on $memory\softshell.cpus[2].core.soc_mem.ram.ram2[15]$26845 ($dff) from module user_proj_example (D = \softshell.cpus[2].core.cpu.wbm_dat_o [23:16], Q = \softshell.cpus[2].core.soc_mem.ram.ram2[15]).
+Adding EN signal on $memory\softshell.cpus[2].core.soc_mem.ram.ram2[14]$26843 ($dff) from module user_proj_example (D = \softshell.cpus[2].core.cpu.wbm_dat_o [23:16], Q = \softshell.cpus[2].core.soc_mem.ram.ram2[14]).
+Adding EN signal on $memory\softshell.cpus[2].core.soc_mem.ram.ram2[13]$26841 ($dff) from module user_proj_example (D = \softshell.cpus[2].core.cpu.wbm_dat_o [23:16], Q = \softshell.cpus[2].core.soc_mem.ram.ram2[13]).
+Adding EN signal on $memory\softshell.cpus[2].core.soc_mem.ram.ram2[12]$26839 ($dff) from module user_proj_example (D = \softshell.cpus[2].core.cpu.wbm_dat_o [23:16], Q = \softshell.cpus[2].core.soc_mem.ram.ram2[12]).
+Adding EN signal on $memory\softshell.cpus[2].core.soc_mem.ram.ram2[11]$26837 ($dff) from module user_proj_example (D = \softshell.cpus[2].core.cpu.wbm_dat_o [23:16], Q = \softshell.cpus[2].core.soc_mem.ram.ram2[11]).
+Adding EN signal on $memory\softshell.cpus[2].core.soc_mem.ram.ram2[10]$26835 ($dff) from module user_proj_example (D = \softshell.cpus[2].core.cpu.wbm_dat_o [23:16], Q = \softshell.cpus[2].core.soc_mem.ram.ram2[10]).
+Adding EN signal on $memory\softshell.cpus[2].core.soc_mem.ram.ram2[0]$26815 ($dff) from module user_proj_example (D = \softshell.cpus[2].core.cpu.wbm_dat_o [23:16], Q = \softshell.cpus[2].core.soc_mem.ram.ram2[0]).
+Adding EN signal on $memory\softshell.cpus[2].core.soc_mem.ram.ram1[9]$26544 ($dff) from module user_proj_example (D = \softshell.cpus[2].core.cpu.wbm_dat_o [15:8], Q = \softshell.cpus[2].core.soc_mem.ram.ram1[9]).
+Adding EN signal on $memory\softshell.cpus[2].core.soc_mem.ram.ram1[8]$26542 ($dff) from module user_proj_example (D = \softshell.cpus[2].core.cpu.wbm_dat_o [15:8], Q = \softshell.cpus[2].core.soc_mem.ram.ram1[8]).
+Adding EN signal on $memory\softshell.cpus[2].core.soc_mem.ram.ram1[7]$26540 ($dff) from module user_proj_example (D = \softshell.cpus[2].core.cpu.wbm_dat_o [15:8], Q = \softshell.cpus[2].core.soc_mem.ram.ram1[7]).
+Adding EN signal on $memory\softshell.cpus[2].core.soc_mem.ram.ram1[6]$26538 ($dff) from module user_proj_example (D = \softshell.cpus[2].core.cpu.wbm_dat_o [15:8], Q = \softshell.cpus[2].core.soc_mem.ram.ram1[6]).
+Adding EN signal on $memory\softshell.cpus[2].core.soc_mem.ram.ram1[5]$26536 ($dff) from module user_proj_example (D = \softshell.cpus[2].core.cpu.wbm_dat_o [15:8], Q = \softshell.cpus[2].core.soc_mem.ram.ram1[5]).
+Adding EN signal on $memory\softshell.cpus[2].core.soc_mem.ram.ram1[4]$26534 ($dff) from module user_proj_example (D = \softshell.cpus[2].core.cpu.wbm_dat_o [15:8], Q = \softshell.cpus[2].core.soc_mem.ram.ram1[4]).
+Adding EN signal on $memory\softshell.cpus[2].core.soc_mem.ram.ram1[3]$26532 ($dff) from module user_proj_example (D = \softshell.cpus[2].core.cpu.wbm_dat_o [15:8], Q = \softshell.cpus[2].core.soc_mem.ram.ram1[3]).
+Adding EN signal on $memory\softshell.cpus[2].core.soc_mem.ram.ram1[31]$26588 ($dff) from module user_proj_example (D = \softshell.cpus[2].core.cpu.wbm_dat_o [15:8], Q = \softshell.cpus[2].core.soc_mem.ram.ram1[31]).
+Adding EN signal on $memory\softshell.cpus[2].core.soc_mem.ram.ram1[30]$26586 ($dff) from module user_proj_example (D = \softshell.cpus[2].core.cpu.wbm_dat_o [15:8], Q = \softshell.cpus[2].core.soc_mem.ram.ram1[30]).
+Adding EN signal on $memory\softshell.cpus[2].core.soc_mem.ram.ram1[2]$26530 ($dff) from module user_proj_example (D = \softshell.cpus[2].core.cpu.wbm_dat_o [15:8], Q = \softshell.cpus[2].core.soc_mem.ram.ram1[2]).
+Adding EN signal on $memory\softshell.cpus[2].core.soc_mem.ram.ram1[29]$26584 ($dff) from module user_proj_example (D = \softshell.cpus[2].core.cpu.wbm_dat_o [15:8], Q = \softshell.cpus[2].core.soc_mem.ram.ram1[29]).
+Adding EN signal on $memory\softshell.cpus[2].core.soc_mem.ram.ram1[28]$26582 ($dff) from module user_proj_example (D = \softshell.cpus[2].core.cpu.wbm_dat_o [15:8], Q = \softshell.cpus[2].core.soc_mem.ram.ram1[28]).
+Adding EN signal on $memory\softshell.cpus[2].core.soc_mem.ram.ram1[27]$26580 ($dff) from module user_proj_example (D = \softshell.cpus[2].core.cpu.wbm_dat_o [15:8], Q = \softshell.cpus[2].core.soc_mem.ram.ram1[27]).
+Adding EN signal on $memory\softshell.cpus[2].core.soc_mem.ram.ram1[26]$26578 ($dff) from module user_proj_example (D = \softshell.cpus[2].core.cpu.wbm_dat_o [15:8], Q = \softshell.cpus[2].core.soc_mem.ram.ram1[26]).
+Adding EN signal on $memory\softshell.cpus[2].core.soc_mem.ram.ram1[25]$26576 ($dff) from module user_proj_example (D = \softshell.cpus[2].core.cpu.wbm_dat_o [15:8], Q = \softshell.cpus[2].core.soc_mem.ram.ram1[25]).
+Adding EN signal on $memory\softshell.cpus[2].core.soc_mem.ram.ram1[24]$26574 ($dff) from module user_proj_example (D = \softshell.cpus[2].core.cpu.wbm_dat_o [15:8], Q = \softshell.cpus[2].core.soc_mem.ram.ram1[24]).
+Adding EN signal on $memory\softshell.cpus[2].core.soc_mem.ram.ram1[23]$26572 ($dff) from module user_proj_example (D = \softshell.cpus[2].core.cpu.wbm_dat_o [15:8], Q = \softshell.cpus[2].core.soc_mem.ram.ram1[23]).
+Adding EN signal on $memory\softshell.cpus[2].core.soc_mem.ram.ram1[22]$26570 ($dff) from module user_proj_example (D = \softshell.cpus[2].core.cpu.wbm_dat_o [15:8], Q = \softshell.cpus[2].core.soc_mem.ram.ram1[22]).
+Adding EN signal on $memory\softshell.cpus[2].core.soc_mem.ram.ram1[21]$26568 ($dff) from module user_proj_example (D = \softshell.cpus[2].core.cpu.wbm_dat_o [15:8], Q = \softshell.cpus[2].core.soc_mem.ram.ram1[21]).
+Adding EN signal on $memory\softshell.cpus[2].core.soc_mem.ram.ram1[20]$26566 ($dff) from module user_proj_example (D = \softshell.cpus[2].core.cpu.wbm_dat_o [15:8], Q = \softshell.cpus[2].core.soc_mem.ram.ram1[20]).
+Adding EN signal on $memory\softshell.cpus[2].core.soc_mem.ram.ram1[1]$26528 ($dff) from module user_proj_example (D = \softshell.cpus[2].core.cpu.wbm_dat_o [15:8], Q = \softshell.cpus[2].core.soc_mem.ram.ram1[1]).
+Adding EN signal on $memory\softshell.cpus[2].core.soc_mem.ram.ram1[19]$26564 ($dff) from module user_proj_example (D = \softshell.cpus[2].core.cpu.wbm_dat_o [15:8], Q = \softshell.cpus[2].core.soc_mem.ram.ram1[19]).
+Adding EN signal on $memory\softshell.cpus[2].core.soc_mem.ram.ram1[18]$26562 ($dff) from module user_proj_example (D = \softshell.cpus[2].core.cpu.wbm_dat_o [15:8], Q = \softshell.cpus[2].core.soc_mem.ram.ram1[18]).
+Adding EN signal on $memory\softshell.cpus[2].core.soc_mem.ram.ram1[17]$26560 ($dff) from module user_proj_example (D = \softshell.cpus[2].core.cpu.wbm_dat_o [15:8], Q = \softshell.cpus[2].core.soc_mem.ram.ram1[17]).
+Adding EN signal on $memory\softshell.cpus[2].core.soc_mem.ram.ram1[16]$26558 ($dff) from module user_proj_example (D = \softshell.cpus[2].core.cpu.wbm_dat_o [15:8], Q = \softshell.cpus[2].core.soc_mem.ram.ram1[16]).
+Adding EN signal on $memory\softshell.cpus[2].core.soc_mem.ram.ram1[15]$26556 ($dff) from module user_proj_example (D = \softshell.cpus[2].core.cpu.wbm_dat_o [15:8], Q = \softshell.cpus[2].core.soc_mem.ram.ram1[15]).
+Adding EN signal on $memory\softshell.cpus[2].core.soc_mem.ram.ram1[14]$26554 ($dff) from module user_proj_example (D = \softshell.cpus[2].core.cpu.wbm_dat_o [15:8], Q = \softshell.cpus[2].core.soc_mem.ram.ram1[14]).
+Adding EN signal on $memory\softshell.cpus[2].core.soc_mem.ram.ram1[13]$26552 ($dff) from module user_proj_example (D = \softshell.cpus[2].core.cpu.wbm_dat_o [15:8], Q = \softshell.cpus[2].core.soc_mem.ram.ram1[13]).
+Adding EN signal on $memory\softshell.cpus[2].core.soc_mem.ram.ram1[12]$26550 ($dff) from module user_proj_example (D = \softshell.cpus[2].core.cpu.wbm_dat_o [15:8], Q = \softshell.cpus[2].core.soc_mem.ram.ram1[12]).
+Adding EN signal on $memory\softshell.cpus[2].core.soc_mem.ram.ram1[11]$26548 ($dff) from module user_proj_example (D = \softshell.cpus[2].core.cpu.wbm_dat_o [15:8], Q = \softshell.cpus[2].core.soc_mem.ram.ram1[11]).
+Adding EN signal on $memory\softshell.cpus[2].core.soc_mem.ram.ram1[10]$26546 ($dff) from module user_proj_example (D = \softshell.cpus[2].core.cpu.wbm_dat_o [15:8], Q = \softshell.cpus[2].core.soc_mem.ram.ram1[10]).
+Adding EN signal on $memory\softshell.cpus[2].core.soc_mem.ram.ram1[0]$26526 ($dff) from module user_proj_example (D = \softshell.cpus[2].core.cpu.wbm_dat_o [15:8], Q = \softshell.cpus[2].core.soc_mem.ram.ram1[0]).
+Adding EN signal on $memory\softshell.cpus[2].core.soc_mem.ram.ram0[9]$26139 ($dff) from module user_proj_example (D = \softshell.cpus[2].core.cpu.wbm_dat_o [7:0], Q = \softshell.cpus[2].core.soc_mem.ram.ram0[9]).
+Adding EN signal on $memory\softshell.cpus[2].core.soc_mem.ram.ram0[8]$26137 ($dff) from module user_proj_example (D = \softshell.cpus[2].core.cpu.wbm_dat_o [7:0], Q = \softshell.cpus[2].core.soc_mem.ram.ram0[8]).
+Adding EN signal on $memory\softshell.cpus[2].core.soc_mem.ram.ram0[7]$26135 ($dff) from module user_proj_example (D = \softshell.cpus[2].core.cpu.wbm_dat_o [7:0], Q = \softshell.cpus[2].core.soc_mem.ram.ram0[7]).
+Adding EN signal on $memory\softshell.cpus[2].core.soc_mem.ram.ram0[6]$26133 ($dff) from module user_proj_example (D = \softshell.cpus[2].core.cpu.wbm_dat_o [7:0], Q = \softshell.cpus[2].core.soc_mem.ram.ram0[6]).
+Adding EN signal on $memory\softshell.cpus[2].core.soc_mem.ram.ram0[5]$26131 ($dff) from module user_proj_example (D = \softshell.cpus[2].core.cpu.wbm_dat_o [7:0], Q = \softshell.cpus[2].core.soc_mem.ram.ram0[5]).
+Adding EN signal on $memory\softshell.cpus[2].core.soc_mem.ram.ram0[4]$26129 ($dff) from module user_proj_example (D = \softshell.cpus[2].core.cpu.wbm_dat_o [7:0], Q = \softshell.cpus[2].core.soc_mem.ram.ram0[4]).
+Adding EN signal on $memory\softshell.cpus[2].core.soc_mem.ram.ram0[3]$26127 ($dff) from module user_proj_example (D = \softshell.cpus[2].core.cpu.wbm_dat_o [7:0], Q = \softshell.cpus[2].core.soc_mem.ram.ram0[3]).
+Adding EN signal on $memory\softshell.cpus[2].core.soc_mem.ram.ram0[31]$26183 ($dff) from module user_proj_example (D = \softshell.cpus[2].core.cpu.wbm_dat_o [7:0], Q = \softshell.cpus[2].core.soc_mem.ram.ram0[31]).
+Adding EN signal on $memory\softshell.cpus[2].core.soc_mem.ram.ram0[30]$26181 ($dff) from module user_proj_example (D = \softshell.cpus[2].core.cpu.wbm_dat_o [7:0], Q = \softshell.cpus[2].core.soc_mem.ram.ram0[30]).
+Adding EN signal on $memory\softshell.cpus[2].core.soc_mem.ram.ram0[2]$26125 ($dff) from module user_proj_example (D = \softshell.cpus[2].core.cpu.wbm_dat_o [7:0], Q = \softshell.cpus[2].core.soc_mem.ram.ram0[2]).
+Adding EN signal on $memory\softshell.cpus[2].core.soc_mem.ram.ram0[29]$26179 ($dff) from module user_proj_example (D = \softshell.cpus[2].core.cpu.wbm_dat_o [7:0], Q = \softshell.cpus[2].core.soc_mem.ram.ram0[29]).
+Adding EN signal on $memory\softshell.cpus[2].core.soc_mem.ram.ram0[28]$26177 ($dff) from module user_proj_example (D = \softshell.cpus[2].core.cpu.wbm_dat_o [7:0], Q = \softshell.cpus[2].core.soc_mem.ram.ram0[28]).
+Adding EN signal on $memory\softshell.cpus[2].core.soc_mem.ram.ram0[27]$26175 ($dff) from module user_proj_example (D = \softshell.cpus[2].core.cpu.wbm_dat_o [7:0], Q = \softshell.cpus[2].core.soc_mem.ram.ram0[27]).
+Adding EN signal on $memory\softshell.cpus[2].core.soc_mem.ram.ram0[26]$26173 ($dff) from module user_proj_example (D = \softshell.cpus[2].core.cpu.wbm_dat_o [7:0], Q = \softshell.cpus[2].core.soc_mem.ram.ram0[26]).
+Adding EN signal on $memory\softshell.cpus[2].core.soc_mem.ram.ram0[25]$26171 ($dff) from module user_proj_example (D = \softshell.cpus[2].core.cpu.wbm_dat_o [7:0], Q = \softshell.cpus[2].core.soc_mem.ram.ram0[25]).
+Adding EN signal on $memory\softshell.cpus[2].core.soc_mem.ram.ram0[24]$26169 ($dff) from module user_proj_example (D = \softshell.cpus[2].core.cpu.wbm_dat_o [7:0], Q = \softshell.cpus[2].core.soc_mem.ram.ram0[24]).
+Adding EN signal on $memory\softshell.cpus[2].core.soc_mem.ram.ram0[23]$26167 ($dff) from module user_proj_example (D = \softshell.cpus[2].core.cpu.wbm_dat_o [7:0], Q = \softshell.cpus[2].core.soc_mem.ram.ram0[23]).
+Adding EN signal on $memory\softshell.cpus[2].core.soc_mem.ram.ram0[22]$26165 ($dff) from module user_proj_example (D = \softshell.cpus[2].core.cpu.wbm_dat_o [7:0], Q = \softshell.cpus[2].core.soc_mem.ram.ram0[22]).
+Adding EN signal on $memory\softshell.cpus[2].core.soc_mem.ram.ram0[21]$26163 ($dff) from module user_proj_example (D = \softshell.cpus[2].core.cpu.wbm_dat_o [7:0], Q = \softshell.cpus[2].core.soc_mem.ram.ram0[21]).
+Adding EN signal on $memory\softshell.cpus[2].core.soc_mem.ram.ram0[20]$26161 ($dff) from module user_proj_example (D = \softshell.cpus[2].core.cpu.wbm_dat_o [7:0], Q = \softshell.cpus[2].core.soc_mem.ram.ram0[20]).
+Adding EN signal on $memory\softshell.cpus[2].core.soc_mem.ram.ram0[1]$26123 ($dff) from module user_proj_example (D = \softshell.cpus[2].core.cpu.wbm_dat_o [7:0], Q = \softshell.cpus[2].core.soc_mem.ram.ram0[1]).
+Adding EN signal on $memory\softshell.cpus[2].core.soc_mem.ram.ram0[19]$26159 ($dff) from module user_proj_example (D = \softshell.cpus[2].core.cpu.wbm_dat_o [7:0], Q = \softshell.cpus[2].core.soc_mem.ram.ram0[19]).
+Adding EN signal on $memory\softshell.cpus[2].core.soc_mem.ram.ram0[18]$26157 ($dff) from module user_proj_example (D = \softshell.cpus[2].core.cpu.wbm_dat_o [7:0], Q = \softshell.cpus[2].core.soc_mem.ram.ram0[18]).
+Adding EN signal on $memory\softshell.cpus[2].core.soc_mem.ram.ram0[17]$26155 ($dff) from module user_proj_example (D = \softshell.cpus[2].core.cpu.wbm_dat_o [7:0], Q = \softshell.cpus[2].core.soc_mem.ram.ram0[17]).
+Adding EN signal on $memory\softshell.cpus[2].core.soc_mem.ram.ram0[16]$26153 ($dff) from module user_proj_example (D = \softshell.cpus[2].core.cpu.wbm_dat_o [7:0], Q = \softshell.cpus[2].core.soc_mem.ram.ram0[16]).
+Adding EN signal on $memory\softshell.cpus[2].core.soc_mem.ram.ram0[15]$26151 ($dff) from module user_proj_example (D = \softshell.cpus[2].core.cpu.wbm_dat_o [7:0], Q = \softshell.cpus[2].core.soc_mem.ram.ram0[15]).
+Adding EN signal on $memory\softshell.cpus[2].core.soc_mem.ram.ram0[14]$26149 ($dff) from module user_proj_example (D = \softshell.cpus[2].core.cpu.wbm_dat_o [7:0], Q = \softshell.cpus[2].core.soc_mem.ram.ram0[14]).
+Adding EN signal on $memory\softshell.cpus[2].core.soc_mem.ram.ram0[13]$26147 ($dff) from module user_proj_example (D = \softshell.cpus[2].core.cpu.wbm_dat_o [7:0], Q = \softshell.cpus[2].core.soc_mem.ram.ram0[13]).
+Adding EN signal on $memory\softshell.cpus[2].core.soc_mem.ram.ram0[12]$26145 ($dff) from module user_proj_example (D = \softshell.cpus[2].core.cpu.wbm_dat_o [7:0], Q = \softshell.cpus[2].core.soc_mem.ram.ram0[12]).
+Adding EN signal on $memory\softshell.cpus[2].core.soc_mem.ram.ram0[11]$26143 ($dff) from module user_proj_example (D = \softshell.cpus[2].core.cpu.wbm_dat_o [7:0], Q = \softshell.cpus[2].core.soc_mem.ram.ram0[11]).
+Adding EN signal on $memory\softshell.cpus[2].core.soc_mem.ram.ram0[10]$26141 ($dff) from module user_proj_example (D = \softshell.cpus[2].core.cpu.wbm_dat_o [7:0], Q = \softshell.cpus[2].core.soc_mem.ram.ram0[10]).
+Adding EN signal on $memory\softshell.cpus[2].core.soc_mem.ram.ram0[0]$26121 ($dff) from module user_proj_example (D = \softshell.cpus[2].core.cpu.wbm_dat_o [7:0], Q = \softshell.cpus[2].core.soc_mem.ram.ram0[0]).
+Adding EN signal on $memory\softshell.cpus[2].core.flexio.out_fifo.mem[3]$26078 ($dff) from module user_proj_example (D = \softshell.cpus[2].core.flexio.out_wr_data, Q = \softshell.cpus[2].core.flexio.out_fifo.mem[3]).
+Adding EN signal on $memory\softshell.cpus[2].core.flexio.out_fifo.mem[2]$26076 ($dff) from module user_proj_example (D = \softshell.cpus[2].core.flexio.out_wr_data, Q = \softshell.cpus[2].core.flexio.out_fifo.mem[2]).
+Adding EN signal on $memory\softshell.cpus[2].core.flexio.out_fifo.mem[1]$26074 ($dff) from module user_proj_example (D = \softshell.cpus[2].core.flexio.out_wr_data, Q = \softshell.cpus[2].core.flexio.out_fifo.mem[1]).
+Adding EN signal on $memory\softshell.cpus[2].core.flexio.out_fifo.mem[0]$26072 ($dff) from module user_proj_example (D = \softshell.cpus[2].core.flexio.out_wr_data, Q = \softshell.cpus[2].core.flexio.out_fifo.mem[0]).
+Adding EN signal on $memory\softshell.cpus[2].core.cpu.picorv32_core.cpuregs.regs[9]$25592 ($dff) from module user_proj_example (D = \softshell.cpus[2].core.cpu.picorv32_core.cpuregs.wdata, Q = \softshell.cpus[2].core.cpu.picorv32_core.cpuregs.regs[9]).
+Adding EN signal on $memory\softshell.cpus[2].core.cpu.picorv32_core.cpuregs.regs[8]$25590 ($dff) from module user_proj_example (D = \softshell.cpus[2].core.cpu.picorv32_core.cpuregs.wdata, Q = \softshell.cpus[2].core.cpu.picorv32_core.cpuregs.regs[8]).
+Adding EN signal on $memory\softshell.cpus[2].core.cpu.picorv32_core.cpuregs.regs[7]$25588 ($dff) from module user_proj_example (D = \softshell.cpus[2].core.cpu.picorv32_core.cpuregs.wdata, Q = \softshell.cpus[2].core.cpu.picorv32_core.cpuregs.regs[7]).
+Adding EN signal on $memory\softshell.cpus[2].core.cpu.picorv32_core.cpuregs.regs[6]$25586 ($dff) from module user_proj_example (D = \softshell.cpus[2].core.cpu.picorv32_core.cpuregs.wdata, Q = \softshell.cpus[2].core.cpu.picorv32_core.cpuregs.regs[6]).
+Adding EN signal on $memory\softshell.cpus[2].core.cpu.picorv32_core.cpuregs.regs[5]$25584 ($dff) from module user_proj_example (D = \softshell.cpus[2].core.cpu.picorv32_core.cpuregs.wdata, Q = \softshell.cpus[2].core.cpu.picorv32_core.cpuregs.regs[5]).
+Adding EN signal on $memory\softshell.cpus[2].core.cpu.picorv32_core.cpuregs.regs[4]$25582 ($dff) from module user_proj_example (D = \softshell.cpus[2].core.cpu.picorv32_core.cpuregs.wdata, Q = \softshell.cpus[2].core.cpu.picorv32_core.cpuregs.regs[4]).
+Adding EN signal on $memory\softshell.cpus[2].core.cpu.picorv32_core.cpuregs.regs[3]$25580 ($dff) from module user_proj_example (D = \softshell.cpus[2].core.cpu.picorv32_core.cpuregs.wdata, Q = \softshell.cpus[2].core.cpu.picorv32_core.cpuregs.regs[3]).
+Adding EN signal on $memory\softshell.cpus[2].core.cpu.picorv32_core.cpuregs.regs[31]$25636 ($dff) from module user_proj_example (D = \softshell.cpus[2].core.cpu.picorv32_core.cpuregs.wdata, Q = \softshell.cpus[2].core.cpu.picorv32_core.cpuregs.regs[31]).
+Adding EN signal on $memory\softshell.cpus[2].core.cpu.picorv32_core.cpuregs.regs[30]$25634 ($dff) from module user_proj_example (D = \softshell.cpus[2].core.cpu.picorv32_core.cpuregs.wdata, Q = \softshell.cpus[2].core.cpu.picorv32_core.cpuregs.regs[30]).
+Adding EN signal on $memory\softshell.cpus[2].core.cpu.picorv32_core.cpuregs.regs[2]$25578 ($dff) from module user_proj_example (D = \softshell.cpus[2].core.cpu.picorv32_core.cpuregs.wdata, Q = \softshell.cpus[2].core.cpu.picorv32_core.cpuregs.regs[2]).
+Adding EN signal on $memory\softshell.cpus[2].core.cpu.picorv32_core.cpuregs.regs[29]$25632 ($dff) from module user_proj_example (D = \softshell.cpus[2].core.cpu.picorv32_core.cpuregs.wdata, Q = \softshell.cpus[2].core.cpu.picorv32_core.cpuregs.regs[29]).
+Adding EN signal on $memory\softshell.cpus[2].core.cpu.picorv32_core.cpuregs.regs[28]$25630 ($dff) from module user_proj_example (D = \softshell.cpus[2].core.cpu.picorv32_core.cpuregs.wdata, Q = \softshell.cpus[2].core.cpu.picorv32_core.cpuregs.regs[28]).
+Adding EN signal on $memory\softshell.cpus[2].core.cpu.picorv32_core.cpuregs.regs[27]$25628 ($dff) from module user_proj_example (D = \softshell.cpus[2].core.cpu.picorv32_core.cpuregs.wdata, Q = \softshell.cpus[2].core.cpu.picorv32_core.cpuregs.regs[27]).
+Adding EN signal on $memory\softshell.cpus[2].core.cpu.picorv32_core.cpuregs.regs[26]$25626 ($dff) from module user_proj_example (D = \softshell.cpus[2].core.cpu.picorv32_core.cpuregs.wdata, Q = \softshell.cpus[2].core.cpu.picorv32_core.cpuregs.regs[26]).
+Adding EN signal on $memory\softshell.cpus[2].core.cpu.picorv32_core.cpuregs.regs[25]$25624 ($dff) from module user_proj_example (D = \softshell.cpus[2].core.cpu.picorv32_core.cpuregs.wdata, Q = \softshell.cpus[2].core.cpu.picorv32_core.cpuregs.regs[25]).
+Adding EN signal on $memory\softshell.cpus[2].core.cpu.picorv32_core.cpuregs.regs[24]$25622 ($dff) from module user_proj_example (D = \softshell.cpus[2].core.cpu.picorv32_core.cpuregs.wdata, Q = \softshell.cpus[2].core.cpu.picorv32_core.cpuregs.regs[24]).
+Adding EN signal on $memory\softshell.cpus[2].core.cpu.picorv32_core.cpuregs.regs[23]$25620 ($dff) from module user_proj_example (D = \softshell.cpus[2].core.cpu.picorv32_core.cpuregs.wdata, Q = \softshell.cpus[2].core.cpu.picorv32_core.cpuregs.regs[23]).
+Adding EN signal on $memory\softshell.cpus[2].core.cpu.picorv32_core.cpuregs.regs[22]$25618 ($dff) from module user_proj_example (D = \softshell.cpus[2].core.cpu.picorv32_core.cpuregs.wdata, Q = \softshell.cpus[2].core.cpu.picorv32_core.cpuregs.regs[22]).
+Adding EN signal on $memory\softshell.cpus[2].core.cpu.picorv32_core.cpuregs.regs[21]$25616 ($dff) from module user_proj_example (D = \softshell.cpus[2].core.cpu.picorv32_core.cpuregs.wdata, Q = \softshell.cpus[2].core.cpu.picorv32_core.cpuregs.regs[21]).
+Adding EN signal on $memory\softshell.cpus[2].core.cpu.picorv32_core.cpuregs.regs[20]$25614 ($dff) from module user_proj_example (D = \softshell.cpus[2].core.cpu.picorv32_core.cpuregs.wdata, Q = \softshell.cpus[2].core.cpu.picorv32_core.cpuregs.regs[20]).
+Adding EN signal on $memory\softshell.cpus[2].core.cpu.picorv32_core.cpuregs.regs[1]$25576 ($dff) from module user_proj_example (D = \softshell.cpus[2].core.cpu.picorv32_core.cpuregs.wdata, Q = \softshell.cpus[2].core.cpu.picorv32_core.cpuregs.regs[1]).
+Adding EN signal on $memory\softshell.cpus[2].core.cpu.picorv32_core.cpuregs.regs[19]$25612 ($dff) from module user_proj_example (D = \softshell.cpus[2].core.cpu.picorv32_core.cpuregs.wdata, Q = \softshell.cpus[2].core.cpu.picorv32_core.cpuregs.regs[19]).
+Adding EN signal on $memory\softshell.cpus[2].core.cpu.picorv32_core.cpuregs.regs[18]$25610 ($dff) from module user_proj_example (D = \softshell.cpus[2].core.cpu.picorv32_core.cpuregs.wdata, Q = \softshell.cpus[2].core.cpu.picorv32_core.cpuregs.regs[18]).
+Adding EN signal on $memory\softshell.cpus[2].core.cpu.picorv32_core.cpuregs.regs[17]$25608 ($dff) from module user_proj_example (D = \softshell.cpus[2].core.cpu.picorv32_core.cpuregs.wdata, Q = \softshell.cpus[2].core.cpu.picorv32_core.cpuregs.regs[17]).
+Adding EN signal on $memory\softshell.cpus[2].core.cpu.picorv32_core.cpuregs.regs[16]$25606 ($dff) from module user_proj_example (D = \softshell.cpus[2].core.cpu.picorv32_core.cpuregs.wdata, Q = \softshell.cpus[2].core.cpu.picorv32_core.cpuregs.regs[16]).
+Adding EN signal on $memory\softshell.cpus[2].core.cpu.picorv32_core.cpuregs.regs[15]$25604 ($dff) from module user_proj_example (D = \softshell.cpus[2].core.cpu.picorv32_core.cpuregs.wdata, Q = \softshell.cpus[2].core.cpu.picorv32_core.cpuregs.regs[15]).
+Adding EN signal on $memory\softshell.cpus[2].core.cpu.picorv32_core.cpuregs.regs[14]$25602 ($dff) from module user_proj_example (D = \softshell.cpus[2].core.cpu.picorv32_core.cpuregs.wdata, Q = \softshell.cpus[2].core.cpu.picorv32_core.cpuregs.regs[14]).
+Adding EN signal on $memory\softshell.cpus[2].core.cpu.picorv32_core.cpuregs.regs[13]$25600 ($dff) from module user_proj_example (D = \softshell.cpus[2].core.cpu.picorv32_core.cpuregs.wdata, Q = \softshell.cpus[2].core.cpu.picorv32_core.cpuregs.regs[13]).
+Adding EN signal on $memory\softshell.cpus[2].core.cpu.picorv32_core.cpuregs.regs[12]$25598 ($dff) from module user_proj_example (D = \softshell.cpus[2].core.cpu.picorv32_core.cpuregs.wdata, Q = \softshell.cpus[2].core.cpu.picorv32_core.cpuregs.regs[12]).
+Adding EN signal on $memory\softshell.cpus[2].core.cpu.picorv32_core.cpuregs.regs[11]$25596 ($dff) from module user_proj_example (D = \softshell.cpus[2].core.cpu.picorv32_core.cpuregs.wdata, Q = \softshell.cpus[2].core.cpu.picorv32_core.cpuregs.regs[11]).
+Adding EN signal on $memory\softshell.cpus[2].core.cpu.picorv32_core.cpuregs.regs[10]$25594 ($dff) from module user_proj_example (D = \softshell.cpus[2].core.cpu.picorv32_core.cpuregs.wdata, Q = \softshell.cpus[2].core.cpu.picorv32_core.cpuregs.regs[10]).
+Adding EN signal on $memory\softshell.cpus[2].core.cpu.picorv32_core.cpuregs.regs[0]$25574 ($dff) from module user_proj_example (D = \softshell.cpus[2].core.cpu.picorv32_core.cpuregs.wdata, Q = \softshell.cpus[2].core.cpu.picorv32_core.cpuregs.regs[0]).
+Adding EN signal on $memory\softshell.cpus[1].core.soc_mem.ram.ram3[9]$25303 ($dff) from module user_proj_example (D = \softshell.cpus[1].core.cpu.wbm_dat_o [31:24], Q = \softshell.cpus[1].core.soc_mem.ram.ram3[9]).
+Adding EN signal on $memory\softshell.cpus[1].core.soc_mem.ram.ram3[8]$25301 ($dff) from module user_proj_example (D = \softshell.cpus[1].core.cpu.wbm_dat_o [31:24], Q = \softshell.cpus[1].core.soc_mem.ram.ram3[8]).
+Adding EN signal on $memory\softshell.cpus[1].core.soc_mem.ram.ram3[7]$25299 ($dff) from module user_proj_example (D = \softshell.cpus[1].core.cpu.wbm_dat_o [31:24], Q = \softshell.cpus[1].core.soc_mem.ram.ram3[7]).
+Adding EN signal on $memory\softshell.cpus[1].core.soc_mem.ram.ram3[6]$25297 ($dff) from module user_proj_example (D = \softshell.cpus[1].core.cpu.wbm_dat_o [31:24], Q = \softshell.cpus[1].core.soc_mem.ram.ram3[6]).
+Adding EN signal on $memory\softshell.cpus[1].core.soc_mem.ram.ram3[5]$25295 ($dff) from module user_proj_example (D = \softshell.cpus[1].core.cpu.wbm_dat_o [31:24], Q = \softshell.cpus[1].core.soc_mem.ram.ram3[5]).
+Adding EN signal on $memory\softshell.cpus[1].core.soc_mem.ram.ram3[4]$25293 ($dff) from module user_proj_example (D = \softshell.cpus[1].core.cpu.wbm_dat_o [31:24], Q = \softshell.cpus[1].core.soc_mem.ram.ram3[4]).
+Adding EN signal on $memory\softshell.cpus[1].core.soc_mem.ram.ram3[3]$25291 ($dff) from module user_proj_example (D = \softshell.cpus[1].core.cpu.wbm_dat_o [31:24], Q = \softshell.cpus[1].core.soc_mem.ram.ram3[3]).
+Adding EN signal on $memory\softshell.cpus[1].core.soc_mem.ram.ram3[31]$25347 ($dff) from module user_proj_example (D = \softshell.cpus[1].core.cpu.wbm_dat_o [31:24], Q = \softshell.cpus[1].core.soc_mem.ram.ram3[31]).
+Adding EN signal on $memory\softshell.cpus[1].core.soc_mem.ram.ram3[30]$25345 ($dff) from module user_proj_example (D = \softshell.cpus[1].core.cpu.wbm_dat_o [31:24], Q = \softshell.cpus[1].core.soc_mem.ram.ram3[30]).
+Adding EN signal on $memory\softshell.cpus[1].core.soc_mem.ram.ram3[2]$25289 ($dff) from module user_proj_example (D = \softshell.cpus[1].core.cpu.wbm_dat_o [31:24], Q = \softshell.cpus[1].core.soc_mem.ram.ram3[2]).
+Adding EN signal on $memory\softshell.cpus[1].core.soc_mem.ram.ram3[29]$25343 ($dff) from module user_proj_example (D = \softshell.cpus[1].core.cpu.wbm_dat_o [31:24], Q = \softshell.cpus[1].core.soc_mem.ram.ram3[29]).
+Adding EN signal on $memory\softshell.cpus[1].core.soc_mem.ram.ram3[28]$25341 ($dff) from module user_proj_example (D = \softshell.cpus[1].core.cpu.wbm_dat_o [31:24], Q = \softshell.cpus[1].core.soc_mem.ram.ram3[28]).
+Adding EN signal on $memory\softshell.cpus[1].core.soc_mem.ram.ram3[27]$25339 ($dff) from module user_proj_example (D = \softshell.cpus[1].core.cpu.wbm_dat_o [31:24], Q = \softshell.cpus[1].core.soc_mem.ram.ram3[27]).
+Adding EN signal on $memory\softshell.cpus[1].core.soc_mem.ram.ram3[26]$25337 ($dff) from module user_proj_example (D = \softshell.cpus[1].core.cpu.wbm_dat_o [31:24], Q = \softshell.cpus[1].core.soc_mem.ram.ram3[26]).
+Adding EN signal on $memory\softshell.cpus[1].core.soc_mem.ram.ram3[25]$25335 ($dff) from module user_proj_example (D = \softshell.cpus[1].core.cpu.wbm_dat_o [31:24], Q = \softshell.cpus[1].core.soc_mem.ram.ram3[25]).
+Adding EN signal on $memory\softshell.cpus[1].core.soc_mem.ram.ram3[24]$25333 ($dff) from module user_proj_example (D = \softshell.cpus[1].core.cpu.wbm_dat_o [31:24], Q = \softshell.cpus[1].core.soc_mem.ram.ram3[24]).
+Adding EN signal on $memory\softshell.cpus[1].core.soc_mem.ram.ram3[23]$25331 ($dff) from module user_proj_example (D = \softshell.cpus[1].core.cpu.wbm_dat_o [31:24], Q = \softshell.cpus[1].core.soc_mem.ram.ram3[23]).
+Adding EN signal on $memory\softshell.cpus[1].core.soc_mem.ram.ram3[22]$25329 ($dff) from module user_proj_example (D = \softshell.cpus[1].core.cpu.wbm_dat_o [31:24], Q = \softshell.cpus[1].core.soc_mem.ram.ram3[22]).
+Adding EN signal on $memory\softshell.cpus[1].core.soc_mem.ram.ram3[21]$25327 ($dff) from module user_proj_example (D = \softshell.cpus[1].core.cpu.wbm_dat_o [31:24], Q = \softshell.cpus[1].core.soc_mem.ram.ram3[21]).
+Adding EN signal on $memory\softshell.cpus[1].core.soc_mem.ram.ram3[20]$25325 ($dff) from module user_proj_example (D = \softshell.cpus[1].core.cpu.wbm_dat_o [31:24], Q = \softshell.cpus[1].core.soc_mem.ram.ram3[20]).
+Adding EN signal on $memory\softshell.cpus[1].core.soc_mem.ram.ram3[1]$25287 ($dff) from module user_proj_example (D = \softshell.cpus[1].core.cpu.wbm_dat_o [31:24], Q = \softshell.cpus[1].core.soc_mem.ram.ram3[1]).
+Adding EN signal on $memory\softshell.cpus[1].core.soc_mem.ram.ram3[19]$25323 ($dff) from module user_proj_example (D = \softshell.cpus[1].core.cpu.wbm_dat_o [31:24], Q = \softshell.cpus[1].core.soc_mem.ram.ram3[19]).
+Adding EN signal on $memory\softshell.cpus[1].core.soc_mem.ram.ram3[18]$25321 ($dff) from module user_proj_example (D = \softshell.cpus[1].core.cpu.wbm_dat_o [31:24], Q = \softshell.cpus[1].core.soc_mem.ram.ram3[18]).
+Adding EN signal on $memory\softshell.cpus[1].core.soc_mem.ram.ram3[17]$25319 ($dff) from module user_proj_example (D = \softshell.cpus[1].core.cpu.wbm_dat_o [31:24], Q = \softshell.cpus[1].core.soc_mem.ram.ram3[17]).
+Adding EN signal on $memory\softshell.cpus[1].core.soc_mem.ram.ram3[16]$25317 ($dff) from module user_proj_example (D = \softshell.cpus[1].core.cpu.wbm_dat_o [31:24], Q = \softshell.cpus[1].core.soc_mem.ram.ram3[16]).
+Adding EN signal on $memory\softshell.cpus[1].core.soc_mem.ram.ram3[15]$25315 ($dff) from module user_proj_example (D = \softshell.cpus[1].core.cpu.wbm_dat_o [31:24], Q = \softshell.cpus[1].core.soc_mem.ram.ram3[15]).
+Adding EN signal on $memory\softshell.cpus[1].core.soc_mem.ram.ram3[14]$25313 ($dff) from module user_proj_example (D = \softshell.cpus[1].core.cpu.wbm_dat_o [31:24], Q = \softshell.cpus[1].core.soc_mem.ram.ram3[14]).
+Adding EN signal on $memory\softshell.cpus[1].core.soc_mem.ram.ram3[13]$25311 ($dff) from module user_proj_example (D = \softshell.cpus[1].core.cpu.wbm_dat_o [31:24], Q = \softshell.cpus[1].core.soc_mem.ram.ram3[13]).
+Adding EN signal on $memory\softshell.cpus[1].core.soc_mem.ram.ram3[12]$25309 ($dff) from module user_proj_example (D = \softshell.cpus[1].core.cpu.wbm_dat_o [31:24], Q = \softshell.cpus[1].core.soc_mem.ram.ram3[12]).
+Adding EN signal on $memory\softshell.cpus[1].core.soc_mem.ram.ram3[11]$25307 ($dff) from module user_proj_example (D = \softshell.cpus[1].core.cpu.wbm_dat_o [31:24], Q = \softshell.cpus[1].core.soc_mem.ram.ram3[11]).
+Adding EN signal on $memory\softshell.cpus[1].core.soc_mem.ram.ram3[10]$25305 ($dff) from module user_proj_example (D = \softshell.cpus[1].core.cpu.wbm_dat_o [31:24], Q = \softshell.cpus[1].core.soc_mem.ram.ram3[10]).
+Adding EN signal on $memory\softshell.cpus[1].core.soc_mem.ram.ram3[0]$25285 ($dff) from module user_proj_example (D = \softshell.cpus[1].core.cpu.wbm_dat_o [31:24], Q = \softshell.cpus[1].core.soc_mem.ram.ram3[0]).
+Adding EN signal on $memory\softshell.cpus[1].core.soc_mem.ram.ram2[9]$25014 ($dff) from module user_proj_example (D = \softshell.cpus[1].core.cpu.wbm_dat_o [23:16], Q = \softshell.cpus[1].core.soc_mem.ram.ram2[9]).
+Adding EN signal on $memory\softshell.cpus[1].core.soc_mem.ram.ram2[8]$25012 ($dff) from module user_proj_example (D = \softshell.cpus[1].core.cpu.wbm_dat_o [23:16], Q = \softshell.cpus[1].core.soc_mem.ram.ram2[8]).
+Adding EN signal on $memory\softshell.cpus[1].core.soc_mem.ram.ram2[7]$25010 ($dff) from module user_proj_example (D = \softshell.cpus[1].core.cpu.wbm_dat_o [23:16], Q = \softshell.cpus[1].core.soc_mem.ram.ram2[7]).
+Adding EN signal on $memory\softshell.cpus[1].core.soc_mem.ram.ram2[6]$25008 ($dff) from module user_proj_example (D = \softshell.cpus[1].core.cpu.wbm_dat_o [23:16], Q = \softshell.cpus[1].core.soc_mem.ram.ram2[6]).
+Adding EN signal on $memory\softshell.cpus[1].core.soc_mem.ram.ram2[5]$25006 ($dff) from module user_proj_example (D = \softshell.cpus[1].core.cpu.wbm_dat_o [23:16], Q = \softshell.cpus[1].core.soc_mem.ram.ram2[5]).
+Adding EN signal on $memory\softshell.cpus[1].core.soc_mem.ram.ram2[4]$25004 ($dff) from module user_proj_example (D = \softshell.cpus[1].core.cpu.wbm_dat_o [23:16], Q = \softshell.cpus[1].core.soc_mem.ram.ram2[4]).
+Adding EN signal on $memory\softshell.cpus[1].core.soc_mem.ram.ram2[3]$25002 ($dff) from module user_proj_example (D = \softshell.cpus[1].core.cpu.wbm_dat_o [23:16], Q = \softshell.cpus[1].core.soc_mem.ram.ram2[3]).
+Adding EN signal on $memory\softshell.cpus[1].core.soc_mem.ram.ram2[31]$25058 ($dff) from module user_proj_example (D = \softshell.cpus[1].core.cpu.wbm_dat_o [23:16], Q = \softshell.cpus[1].core.soc_mem.ram.ram2[31]).
+Adding EN signal on $memory\softshell.cpus[1].core.soc_mem.ram.ram2[30]$25056 ($dff) from module user_proj_example (D = \softshell.cpus[1].core.cpu.wbm_dat_o [23:16], Q = \softshell.cpus[1].core.soc_mem.ram.ram2[30]).
+Adding EN signal on $memory\softshell.cpus[1].core.soc_mem.ram.ram2[2]$25000 ($dff) from module user_proj_example (D = \softshell.cpus[1].core.cpu.wbm_dat_o [23:16], Q = \softshell.cpus[1].core.soc_mem.ram.ram2[2]).
+Adding EN signal on $memory\softshell.cpus[1].core.soc_mem.ram.ram2[29]$25054 ($dff) from module user_proj_example (D = \softshell.cpus[1].core.cpu.wbm_dat_o [23:16], Q = \softshell.cpus[1].core.soc_mem.ram.ram2[29]).
+Adding EN signal on $memory\softshell.cpus[1].core.soc_mem.ram.ram2[28]$25052 ($dff) from module user_proj_example (D = \softshell.cpus[1].core.cpu.wbm_dat_o [23:16], Q = \softshell.cpus[1].core.soc_mem.ram.ram2[28]).
+Adding EN signal on $memory\softshell.cpus[1].core.soc_mem.ram.ram2[27]$25050 ($dff) from module user_proj_example (D = \softshell.cpus[1].core.cpu.wbm_dat_o [23:16], Q = \softshell.cpus[1].core.soc_mem.ram.ram2[27]).
+Adding EN signal on $memory\softshell.cpus[1].core.soc_mem.ram.ram2[26]$25048 ($dff) from module user_proj_example (D = \softshell.cpus[1].core.cpu.wbm_dat_o [23:16], Q = \softshell.cpus[1].core.soc_mem.ram.ram2[26]).
+Adding EN signal on $memory\softshell.cpus[1].core.soc_mem.ram.ram2[25]$25046 ($dff) from module user_proj_example (D = \softshell.cpus[1].core.cpu.wbm_dat_o [23:16], Q = \softshell.cpus[1].core.soc_mem.ram.ram2[25]).
+Adding EN signal on $memory\softshell.cpus[1].core.soc_mem.ram.ram2[24]$25044 ($dff) from module user_proj_example (D = \softshell.cpus[1].core.cpu.wbm_dat_o [23:16], Q = \softshell.cpus[1].core.soc_mem.ram.ram2[24]).
+Adding EN signal on $memory\softshell.cpus[1].core.soc_mem.ram.ram2[23]$25042 ($dff) from module user_proj_example (D = \softshell.cpus[1].core.cpu.wbm_dat_o [23:16], Q = \softshell.cpus[1].core.soc_mem.ram.ram2[23]).
+Adding EN signal on $memory\softshell.cpus[1].core.soc_mem.ram.ram2[22]$25040 ($dff) from module user_proj_example (D = \softshell.cpus[1].core.cpu.wbm_dat_o [23:16], Q = \softshell.cpus[1].core.soc_mem.ram.ram2[22]).
+Adding EN signal on $memory\softshell.cpus[1].core.soc_mem.ram.ram2[21]$25038 ($dff) from module user_proj_example (D = \softshell.cpus[1].core.cpu.wbm_dat_o [23:16], Q = \softshell.cpus[1].core.soc_mem.ram.ram2[21]).
+Adding EN signal on $memory\softshell.cpus[1].core.soc_mem.ram.ram2[20]$25036 ($dff) from module user_proj_example (D = \softshell.cpus[1].core.cpu.wbm_dat_o [23:16], Q = \softshell.cpus[1].core.soc_mem.ram.ram2[20]).
+Adding EN signal on $memory\softshell.cpus[1].core.soc_mem.ram.ram2[1]$24998 ($dff) from module user_proj_example (D = \softshell.cpus[1].core.cpu.wbm_dat_o [23:16], Q = \softshell.cpus[1].core.soc_mem.ram.ram2[1]).
+Adding EN signal on $memory\softshell.cpus[1].core.soc_mem.ram.ram2[19]$25034 ($dff) from module user_proj_example (D = \softshell.cpus[1].core.cpu.wbm_dat_o [23:16], Q = \softshell.cpus[1].core.soc_mem.ram.ram2[19]).
+Adding EN signal on $memory\softshell.cpus[1].core.soc_mem.ram.ram2[18]$25032 ($dff) from module user_proj_example (D = \softshell.cpus[1].core.cpu.wbm_dat_o [23:16], Q = \softshell.cpus[1].core.soc_mem.ram.ram2[18]).
+Adding EN signal on $memory\softshell.cpus[1].core.soc_mem.ram.ram2[17]$25030 ($dff) from module user_proj_example (D = \softshell.cpus[1].core.cpu.wbm_dat_o [23:16], Q = \softshell.cpus[1].core.soc_mem.ram.ram2[17]).
+Adding EN signal on $memory\softshell.cpus[1].core.soc_mem.ram.ram2[16]$25028 ($dff) from module user_proj_example (D = \softshell.cpus[1].core.cpu.wbm_dat_o [23:16], Q = \softshell.cpus[1].core.soc_mem.ram.ram2[16]).
+Adding EN signal on $memory\softshell.cpus[1].core.soc_mem.ram.ram2[15]$25026 ($dff) from module user_proj_example (D = \softshell.cpus[1].core.cpu.wbm_dat_o [23:16], Q = \softshell.cpus[1].core.soc_mem.ram.ram2[15]).
+Adding EN signal on $memory\softshell.cpus[1].core.soc_mem.ram.ram2[14]$25024 ($dff) from module user_proj_example (D = \softshell.cpus[1].core.cpu.wbm_dat_o [23:16], Q = \softshell.cpus[1].core.soc_mem.ram.ram2[14]).
+Adding EN signal on $memory\softshell.cpus[1].core.soc_mem.ram.ram2[13]$25022 ($dff) from module user_proj_example (D = \softshell.cpus[1].core.cpu.wbm_dat_o [23:16], Q = \softshell.cpus[1].core.soc_mem.ram.ram2[13]).
+Adding EN signal on $memory\softshell.cpus[1].core.soc_mem.ram.ram2[12]$25020 ($dff) from module user_proj_example (D = \softshell.cpus[1].core.cpu.wbm_dat_o [23:16], Q = \softshell.cpus[1].core.soc_mem.ram.ram2[12]).
+Adding EN signal on $memory\softshell.cpus[1].core.soc_mem.ram.ram2[11]$25018 ($dff) from module user_proj_example (D = \softshell.cpus[1].core.cpu.wbm_dat_o [23:16], Q = \softshell.cpus[1].core.soc_mem.ram.ram2[11]).
+Adding EN signal on $memory\softshell.cpus[1].core.soc_mem.ram.ram2[10]$25016 ($dff) from module user_proj_example (D = \softshell.cpus[1].core.cpu.wbm_dat_o [23:16], Q = \softshell.cpus[1].core.soc_mem.ram.ram2[10]).
+Adding EN signal on $memory\softshell.cpus[1].core.soc_mem.ram.ram2[0]$24996 ($dff) from module user_proj_example (D = \softshell.cpus[1].core.cpu.wbm_dat_o [23:16], Q = \softshell.cpus[1].core.soc_mem.ram.ram2[0]).
+Adding EN signal on $memory\softshell.cpus[1].core.soc_mem.ram.ram1[9]$24725 ($dff) from module user_proj_example (D = \softshell.cpus[1].core.cpu.wbm_dat_o [15:8], Q = \softshell.cpus[1].core.soc_mem.ram.ram1[9]).
+Adding EN signal on $memory\softshell.cpus[1].core.soc_mem.ram.ram1[8]$24723 ($dff) from module user_proj_example (D = \softshell.cpus[1].core.cpu.wbm_dat_o [15:8], Q = \softshell.cpus[1].core.soc_mem.ram.ram1[8]).
+Adding EN signal on $memory\softshell.cpus[1].core.soc_mem.ram.ram1[7]$24721 ($dff) from module user_proj_example (D = \softshell.cpus[1].core.cpu.wbm_dat_o [15:8], Q = \softshell.cpus[1].core.soc_mem.ram.ram1[7]).
+Adding EN signal on $memory\softshell.cpus[1].core.soc_mem.ram.ram1[6]$24719 ($dff) from module user_proj_example (D = \softshell.cpus[1].core.cpu.wbm_dat_o [15:8], Q = \softshell.cpus[1].core.soc_mem.ram.ram1[6]).
+Adding EN signal on $memory\softshell.cpus[1].core.soc_mem.ram.ram1[5]$24717 ($dff) from module user_proj_example (D = \softshell.cpus[1].core.cpu.wbm_dat_o [15:8], Q = \softshell.cpus[1].core.soc_mem.ram.ram1[5]).
+Adding EN signal on $memory\softshell.cpus[1].core.soc_mem.ram.ram1[4]$24715 ($dff) from module user_proj_example (D = \softshell.cpus[1].core.cpu.wbm_dat_o [15:8], Q = \softshell.cpus[1].core.soc_mem.ram.ram1[4]).
+Adding EN signal on $memory\softshell.cpus[1].core.soc_mem.ram.ram1[3]$24713 ($dff) from module user_proj_example (D = \softshell.cpus[1].core.cpu.wbm_dat_o [15:8], Q = \softshell.cpus[1].core.soc_mem.ram.ram1[3]).
+Adding EN signal on $memory\softshell.cpus[1].core.soc_mem.ram.ram1[31]$24769 ($dff) from module user_proj_example (D = \softshell.cpus[1].core.cpu.wbm_dat_o [15:8], Q = \softshell.cpus[1].core.soc_mem.ram.ram1[31]).
+Adding EN signal on $memory\softshell.cpus[1].core.soc_mem.ram.ram1[30]$24767 ($dff) from module user_proj_example (D = \softshell.cpus[1].core.cpu.wbm_dat_o [15:8], Q = \softshell.cpus[1].core.soc_mem.ram.ram1[30]).
+Adding EN signal on $memory\softshell.cpus[1].core.soc_mem.ram.ram1[2]$24711 ($dff) from module user_proj_example (D = \softshell.cpus[1].core.cpu.wbm_dat_o [15:8], Q = \softshell.cpus[1].core.soc_mem.ram.ram1[2]).
+Adding EN signal on $memory\softshell.cpus[1].core.soc_mem.ram.ram1[29]$24765 ($dff) from module user_proj_example (D = \softshell.cpus[1].core.cpu.wbm_dat_o [15:8], Q = \softshell.cpus[1].core.soc_mem.ram.ram1[29]).
+Adding EN signal on $memory\softshell.cpus[1].core.soc_mem.ram.ram1[28]$24763 ($dff) from module user_proj_example (D = \softshell.cpus[1].core.cpu.wbm_dat_o [15:8], Q = \softshell.cpus[1].core.soc_mem.ram.ram1[28]).
+Adding EN signal on $memory\softshell.cpus[1].core.soc_mem.ram.ram1[27]$24761 ($dff) from module user_proj_example (D = \softshell.cpus[1].core.cpu.wbm_dat_o [15:8], Q = \softshell.cpus[1].core.soc_mem.ram.ram1[27]).
+Adding EN signal on $memory\softshell.cpus[1].core.soc_mem.ram.ram1[26]$24759 ($dff) from module user_proj_example (D = \softshell.cpus[1].core.cpu.wbm_dat_o [15:8], Q = \softshell.cpus[1].core.soc_mem.ram.ram1[26]).
+Adding EN signal on $memory\softshell.cpus[1].core.soc_mem.ram.ram1[25]$24757 ($dff) from module user_proj_example (D = \softshell.cpus[1].core.cpu.wbm_dat_o [15:8], Q = \softshell.cpus[1].core.soc_mem.ram.ram1[25]).
+Adding EN signal on $memory\softshell.cpus[1].core.soc_mem.ram.ram1[24]$24755 ($dff) from module user_proj_example (D = \softshell.cpus[1].core.cpu.wbm_dat_o [15:8], Q = \softshell.cpus[1].core.soc_mem.ram.ram1[24]).
+Adding EN signal on $memory\softshell.cpus[1].core.soc_mem.ram.ram1[23]$24753 ($dff) from module user_proj_example (D = \softshell.cpus[1].core.cpu.wbm_dat_o [15:8], Q = \softshell.cpus[1].core.soc_mem.ram.ram1[23]).
+Adding EN signal on $memory\softshell.cpus[1].core.soc_mem.ram.ram1[22]$24751 ($dff) from module user_proj_example (D = \softshell.cpus[1].core.cpu.wbm_dat_o [15:8], Q = \softshell.cpus[1].core.soc_mem.ram.ram1[22]).
+Adding EN signal on $memory\softshell.cpus[1].core.soc_mem.ram.ram1[21]$24749 ($dff) from module user_proj_example (D = \softshell.cpus[1].core.cpu.wbm_dat_o [15:8], Q = \softshell.cpus[1].core.soc_mem.ram.ram1[21]).
+Adding EN signal on $memory\softshell.cpus[1].core.soc_mem.ram.ram1[20]$24747 ($dff) from module user_proj_example (D = \softshell.cpus[1].core.cpu.wbm_dat_o [15:8], Q = \softshell.cpus[1].core.soc_mem.ram.ram1[20]).
+Adding EN signal on $memory\softshell.cpus[1].core.soc_mem.ram.ram1[1]$24709 ($dff) from module user_proj_example (D = \softshell.cpus[1].core.cpu.wbm_dat_o [15:8], Q = \softshell.cpus[1].core.soc_mem.ram.ram1[1]).
+Adding EN signal on $memory\softshell.cpus[1].core.soc_mem.ram.ram1[19]$24745 ($dff) from module user_proj_example (D = \softshell.cpus[1].core.cpu.wbm_dat_o [15:8], Q = \softshell.cpus[1].core.soc_mem.ram.ram1[19]).
+Adding EN signal on $memory\softshell.cpus[1].core.soc_mem.ram.ram1[18]$24743 ($dff) from module user_proj_example (D = \softshell.cpus[1].core.cpu.wbm_dat_o [15:8], Q = \softshell.cpus[1].core.soc_mem.ram.ram1[18]).
+Adding EN signal on $memory\softshell.cpus[1].core.soc_mem.ram.ram1[17]$24741 ($dff) from module user_proj_example (D = \softshell.cpus[1].core.cpu.wbm_dat_o [15:8], Q = \softshell.cpus[1].core.soc_mem.ram.ram1[17]).
+Adding EN signal on $memory\softshell.cpus[1].core.soc_mem.ram.ram1[16]$24739 ($dff) from module user_proj_example (D = \softshell.cpus[1].core.cpu.wbm_dat_o [15:8], Q = \softshell.cpus[1].core.soc_mem.ram.ram1[16]).
+Adding EN signal on $memory\softshell.cpus[1].core.soc_mem.ram.ram1[15]$24737 ($dff) from module user_proj_example (D = \softshell.cpus[1].core.cpu.wbm_dat_o [15:8], Q = \softshell.cpus[1].core.soc_mem.ram.ram1[15]).
+Adding EN signal on $memory\softshell.cpus[1].core.soc_mem.ram.ram1[14]$24735 ($dff) from module user_proj_example (D = \softshell.cpus[1].core.cpu.wbm_dat_o [15:8], Q = \softshell.cpus[1].core.soc_mem.ram.ram1[14]).
+Adding EN signal on $memory\softshell.cpus[1].core.soc_mem.ram.ram1[13]$24733 ($dff) from module user_proj_example (D = \softshell.cpus[1].core.cpu.wbm_dat_o [15:8], Q = \softshell.cpus[1].core.soc_mem.ram.ram1[13]).
+Adding EN signal on $memory\softshell.cpus[1].core.soc_mem.ram.ram1[12]$24731 ($dff) from module user_proj_example (D = \softshell.cpus[1].core.cpu.wbm_dat_o [15:8], Q = \softshell.cpus[1].core.soc_mem.ram.ram1[12]).
+Adding EN signal on $memory\softshell.cpus[1].core.soc_mem.ram.ram1[11]$24729 ($dff) from module user_proj_example (D = \softshell.cpus[1].core.cpu.wbm_dat_o [15:8], Q = \softshell.cpus[1].core.soc_mem.ram.ram1[11]).
+Adding EN signal on $memory\softshell.cpus[1].core.soc_mem.ram.ram1[10]$24727 ($dff) from module user_proj_example (D = \softshell.cpus[1].core.cpu.wbm_dat_o [15:8], Q = \softshell.cpus[1].core.soc_mem.ram.ram1[10]).
+Adding EN signal on $memory\softshell.cpus[1].core.soc_mem.ram.ram1[0]$24707 ($dff) from module user_proj_example (D = \softshell.cpus[1].core.cpu.wbm_dat_o [15:8], Q = \softshell.cpus[1].core.soc_mem.ram.ram1[0]).
+Adding EN signal on $memory\softshell.cpus[1].core.soc_mem.ram.ram0[9]$24320 ($dff) from module user_proj_example (D = \softshell.cpus[1].core.cpu.wbm_dat_o [7:0], Q = \softshell.cpus[1].core.soc_mem.ram.ram0[9]).
+Adding EN signal on $memory\softshell.cpus[1].core.soc_mem.ram.ram0[8]$24318 ($dff) from module user_proj_example (D = \softshell.cpus[1].core.cpu.wbm_dat_o [7:0], Q = \softshell.cpus[1].core.soc_mem.ram.ram0[8]).
+Adding EN signal on $memory\softshell.cpus[1].core.soc_mem.ram.ram0[7]$24316 ($dff) from module user_proj_example (D = \softshell.cpus[1].core.cpu.wbm_dat_o [7:0], Q = \softshell.cpus[1].core.soc_mem.ram.ram0[7]).
+Adding EN signal on $memory\softshell.cpus[1].core.soc_mem.ram.ram0[6]$24314 ($dff) from module user_proj_example (D = \softshell.cpus[1].core.cpu.wbm_dat_o [7:0], Q = \softshell.cpus[1].core.soc_mem.ram.ram0[6]).
+Adding EN signal on $memory\softshell.cpus[1].core.soc_mem.ram.ram0[5]$24312 ($dff) from module user_proj_example (D = \softshell.cpus[1].core.cpu.wbm_dat_o [7:0], Q = \softshell.cpus[1].core.soc_mem.ram.ram0[5]).
+Adding EN signal on $memory\softshell.cpus[1].core.soc_mem.ram.ram0[4]$24310 ($dff) from module user_proj_example (D = \softshell.cpus[1].core.cpu.wbm_dat_o [7:0], Q = \softshell.cpus[1].core.soc_mem.ram.ram0[4]).
+Adding EN signal on $memory\softshell.cpus[1].core.soc_mem.ram.ram0[3]$24308 ($dff) from module user_proj_example (D = \softshell.cpus[1].core.cpu.wbm_dat_o [7:0], Q = \softshell.cpus[1].core.soc_mem.ram.ram0[3]).
+Adding EN signal on $memory\softshell.cpus[1].core.soc_mem.ram.ram0[31]$24364 ($dff) from module user_proj_example (D = \softshell.cpus[1].core.cpu.wbm_dat_o [7:0], Q = \softshell.cpus[1].core.soc_mem.ram.ram0[31]).
+Adding EN signal on $memory\softshell.cpus[1].core.soc_mem.ram.ram0[30]$24362 ($dff) from module user_proj_example (D = \softshell.cpus[1].core.cpu.wbm_dat_o [7:0], Q = \softshell.cpus[1].core.soc_mem.ram.ram0[30]).
+Adding EN signal on $memory\softshell.cpus[1].core.soc_mem.ram.ram0[2]$24306 ($dff) from module user_proj_example (D = \softshell.cpus[1].core.cpu.wbm_dat_o [7:0], Q = \softshell.cpus[1].core.soc_mem.ram.ram0[2]).
+Adding EN signal on $memory\softshell.cpus[1].core.soc_mem.ram.ram0[29]$24360 ($dff) from module user_proj_example (D = \softshell.cpus[1].core.cpu.wbm_dat_o [7:0], Q = \softshell.cpus[1].core.soc_mem.ram.ram0[29]).
+Adding EN signal on $memory\softshell.cpus[1].core.soc_mem.ram.ram0[28]$24358 ($dff) from module user_proj_example (D = \softshell.cpus[1].core.cpu.wbm_dat_o [7:0], Q = \softshell.cpus[1].core.soc_mem.ram.ram0[28]).
+Adding EN signal on $memory\softshell.cpus[1].core.soc_mem.ram.ram0[27]$24356 ($dff) from module user_proj_example (D = \softshell.cpus[1].core.cpu.wbm_dat_o [7:0], Q = \softshell.cpus[1].core.soc_mem.ram.ram0[27]).
+Adding EN signal on $memory\softshell.cpus[1].core.soc_mem.ram.ram0[26]$24354 ($dff) from module user_proj_example (D = \softshell.cpus[1].core.cpu.wbm_dat_o [7:0], Q = \softshell.cpus[1].core.soc_mem.ram.ram0[26]).
+Adding EN signal on $memory\softshell.cpus[1].core.soc_mem.ram.ram0[25]$24352 ($dff) from module user_proj_example (D = \softshell.cpus[1].core.cpu.wbm_dat_o [7:0], Q = \softshell.cpus[1].core.soc_mem.ram.ram0[25]).
+Adding EN signal on $memory\softshell.cpus[1].core.soc_mem.ram.ram0[24]$24350 ($dff) from module user_proj_example (D = \softshell.cpus[1].core.cpu.wbm_dat_o [7:0], Q = \softshell.cpus[1].core.soc_mem.ram.ram0[24]).
+Adding EN signal on $memory\softshell.cpus[1].core.soc_mem.ram.ram0[23]$24348 ($dff) from module user_proj_example (D = \softshell.cpus[1].core.cpu.wbm_dat_o [7:0], Q = \softshell.cpus[1].core.soc_mem.ram.ram0[23]).
+Adding EN signal on $memory\softshell.cpus[1].core.soc_mem.ram.ram0[22]$24346 ($dff) from module user_proj_example (D = \softshell.cpus[1].core.cpu.wbm_dat_o [7:0], Q = \softshell.cpus[1].core.soc_mem.ram.ram0[22]).
+Adding EN signal on $memory\softshell.cpus[1].core.soc_mem.ram.ram0[21]$24344 ($dff) from module user_proj_example (D = \softshell.cpus[1].core.cpu.wbm_dat_o [7:0], Q = \softshell.cpus[1].core.soc_mem.ram.ram0[21]).
+Adding EN signal on $memory\softshell.cpus[1].core.soc_mem.ram.ram0[20]$24342 ($dff) from module user_proj_example (D = \softshell.cpus[1].core.cpu.wbm_dat_o [7:0], Q = \softshell.cpus[1].core.soc_mem.ram.ram0[20]).
+Adding EN signal on $memory\softshell.cpus[1].core.soc_mem.ram.ram0[1]$24304 ($dff) from module user_proj_example (D = \softshell.cpus[1].core.cpu.wbm_dat_o [7:0], Q = \softshell.cpus[1].core.soc_mem.ram.ram0[1]).
+Adding EN signal on $memory\softshell.cpus[1].core.soc_mem.ram.ram0[19]$24340 ($dff) from module user_proj_example (D = \softshell.cpus[1].core.cpu.wbm_dat_o [7:0], Q = \softshell.cpus[1].core.soc_mem.ram.ram0[19]).
+Adding EN signal on $memory\softshell.cpus[1].core.soc_mem.ram.ram0[18]$24338 ($dff) from module user_proj_example (D = \softshell.cpus[1].core.cpu.wbm_dat_o [7:0], Q = \softshell.cpus[1].core.soc_mem.ram.ram0[18]).
+Adding EN signal on $memory\softshell.cpus[1].core.soc_mem.ram.ram0[17]$24336 ($dff) from module user_proj_example (D = \softshell.cpus[1].core.cpu.wbm_dat_o [7:0], Q = \softshell.cpus[1].core.soc_mem.ram.ram0[17]).
+Adding EN signal on $memory\softshell.cpus[1].core.soc_mem.ram.ram0[16]$24334 ($dff) from module user_proj_example (D = \softshell.cpus[1].core.cpu.wbm_dat_o [7:0], Q = \softshell.cpus[1].core.soc_mem.ram.ram0[16]).
+Adding EN signal on $memory\softshell.cpus[1].core.soc_mem.ram.ram0[15]$24332 ($dff) from module user_proj_example (D = \softshell.cpus[1].core.cpu.wbm_dat_o [7:0], Q = \softshell.cpus[1].core.soc_mem.ram.ram0[15]).
+Adding EN signal on $memory\softshell.cpus[1].core.soc_mem.ram.ram0[14]$24330 ($dff) from module user_proj_example (D = \softshell.cpus[1].core.cpu.wbm_dat_o [7:0], Q = \softshell.cpus[1].core.soc_mem.ram.ram0[14]).
+Adding EN signal on $memory\softshell.cpus[1].core.soc_mem.ram.ram0[13]$24328 ($dff) from module user_proj_example (D = \softshell.cpus[1].core.cpu.wbm_dat_o [7:0], Q = \softshell.cpus[1].core.soc_mem.ram.ram0[13]).
+Adding EN signal on $memory\softshell.cpus[1].core.soc_mem.ram.ram0[12]$24326 ($dff) from module user_proj_example (D = \softshell.cpus[1].core.cpu.wbm_dat_o [7:0], Q = \softshell.cpus[1].core.soc_mem.ram.ram0[12]).
+Adding EN signal on $memory\softshell.cpus[1].core.soc_mem.ram.ram0[11]$24324 ($dff) from module user_proj_example (D = \softshell.cpus[1].core.cpu.wbm_dat_o [7:0], Q = \softshell.cpus[1].core.soc_mem.ram.ram0[11]).
+Adding EN signal on $memory\softshell.cpus[1].core.soc_mem.ram.ram0[10]$24322 ($dff) from module user_proj_example (D = \softshell.cpus[1].core.cpu.wbm_dat_o [7:0], Q = \softshell.cpus[1].core.soc_mem.ram.ram0[10]).
+Adding EN signal on $memory\softshell.cpus[1].core.soc_mem.ram.ram0[0]$24302 ($dff) from module user_proj_example (D = \softshell.cpus[1].core.cpu.wbm_dat_o [7:0], Q = \softshell.cpus[1].core.soc_mem.ram.ram0[0]).
+Adding EN signal on $memory\softshell.cpus[1].core.flexio.out_fifo.mem[3]$24259 ($dff) from module user_proj_example (D = \softshell.cpus[1].core.flexio.out_wr_data, Q = \softshell.cpus[1].core.flexio.out_fifo.mem[3]).
+Adding EN signal on $memory\softshell.cpus[1].core.flexio.out_fifo.mem[2]$24257 ($dff) from module user_proj_example (D = \softshell.cpus[1].core.flexio.out_wr_data, Q = \softshell.cpus[1].core.flexio.out_fifo.mem[2]).
+Adding EN signal on $memory\softshell.cpus[1].core.flexio.out_fifo.mem[1]$24255 ($dff) from module user_proj_example (D = \softshell.cpus[1].core.flexio.out_wr_data, Q = \softshell.cpus[1].core.flexio.out_fifo.mem[1]).
+Adding EN signal on $memory\softshell.cpus[1].core.flexio.out_fifo.mem[0]$24253 ($dff) from module user_proj_example (D = \softshell.cpus[1].core.flexio.out_wr_data, Q = \softshell.cpus[1].core.flexio.out_fifo.mem[0]).
+Adding EN signal on $memory\softshell.cpus[1].core.cpu.picorv32_core.cpuregs.regs[9]$23773 ($dff) from module user_proj_example (D = \softshell.cpus[1].core.cpu.picorv32_core.cpuregs.wdata, Q = \softshell.cpus[1].core.cpu.picorv32_core.cpuregs.regs[9]).
+Adding EN signal on $memory\softshell.cpus[1].core.cpu.picorv32_core.cpuregs.regs[8]$23771 ($dff) from module user_proj_example (D = \softshell.cpus[1].core.cpu.picorv32_core.cpuregs.wdata, Q = \softshell.cpus[1].core.cpu.picorv32_core.cpuregs.regs[8]).
+Adding EN signal on $memory\softshell.cpus[1].core.cpu.picorv32_core.cpuregs.regs[7]$23769 ($dff) from module user_proj_example (D = \softshell.cpus[1].core.cpu.picorv32_core.cpuregs.wdata, Q = \softshell.cpus[1].core.cpu.picorv32_core.cpuregs.regs[7]).
+Adding EN signal on $memory\softshell.cpus[1].core.cpu.picorv32_core.cpuregs.regs[6]$23767 ($dff) from module user_proj_example (D = \softshell.cpus[1].core.cpu.picorv32_core.cpuregs.wdata, Q = \softshell.cpus[1].core.cpu.picorv32_core.cpuregs.regs[6]).
+Adding EN signal on $memory\softshell.cpus[1].core.cpu.picorv32_core.cpuregs.regs[5]$23765 ($dff) from module user_proj_example (D = \softshell.cpus[1].core.cpu.picorv32_core.cpuregs.wdata, Q = \softshell.cpus[1].core.cpu.picorv32_core.cpuregs.regs[5]).
+Adding EN signal on $memory\softshell.cpus[1].core.cpu.picorv32_core.cpuregs.regs[4]$23763 ($dff) from module user_proj_example (D = \softshell.cpus[1].core.cpu.picorv32_core.cpuregs.wdata, Q = \softshell.cpus[1].core.cpu.picorv32_core.cpuregs.regs[4]).
+Adding EN signal on $memory\softshell.cpus[1].core.cpu.picorv32_core.cpuregs.regs[3]$23761 ($dff) from module user_proj_example (D = \softshell.cpus[1].core.cpu.picorv32_core.cpuregs.wdata, Q = \softshell.cpus[1].core.cpu.picorv32_core.cpuregs.regs[3]).
+Adding EN signal on $memory\softshell.cpus[1].core.cpu.picorv32_core.cpuregs.regs[31]$23817 ($dff) from module user_proj_example (D = \softshell.cpus[1].core.cpu.picorv32_core.cpuregs.wdata, Q = \softshell.cpus[1].core.cpu.picorv32_core.cpuregs.regs[31]).
+Adding EN signal on $memory\softshell.cpus[1].core.cpu.picorv32_core.cpuregs.regs[30]$23815 ($dff) from module user_proj_example (D = \softshell.cpus[1].core.cpu.picorv32_core.cpuregs.wdata, Q = \softshell.cpus[1].core.cpu.picorv32_core.cpuregs.regs[30]).
+Adding EN signal on $memory\softshell.cpus[1].core.cpu.picorv32_core.cpuregs.regs[2]$23759 ($dff) from module user_proj_example (D = \softshell.cpus[1].core.cpu.picorv32_core.cpuregs.wdata, Q = \softshell.cpus[1].core.cpu.picorv32_core.cpuregs.regs[2]).
+Adding EN signal on $memory\softshell.cpus[1].core.cpu.picorv32_core.cpuregs.regs[29]$23813 ($dff) from module user_proj_example (D = \softshell.cpus[1].core.cpu.picorv32_core.cpuregs.wdata, Q = \softshell.cpus[1].core.cpu.picorv32_core.cpuregs.regs[29]).
+Adding EN signal on $memory\softshell.cpus[1].core.cpu.picorv32_core.cpuregs.regs[28]$23811 ($dff) from module user_proj_example (D = \softshell.cpus[1].core.cpu.picorv32_core.cpuregs.wdata, Q = \softshell.cpus[1].core.cpu.picorv32_core.cpuregs.regs[28]).
+Adding EN signal on $memory\softshell.cpus[1].core.cpu.picorv32_core.cpuregs.regs[27]$23809 ($dff) from module user_proj_example (D = \softshell.cpus[1].core.cpu.picorv32_core.cpuregs.wdata, Q = \softshell.cpus[1].core.cpu.picorv32_core.cpuregs.regs[27]).
+Adding EN signal on $memory\softshell.cpus[1].core.cpu.picorv32_core.cpuregs.regs[26]$23807 ($dff) from module user_proj_example (D = \softshell.cpus[1].core.cpu.picorv32_core.cpuregs.wdata, Q = \softshell.cpus[1].core.cpu.picorv32_core.cpuregs.regs[26]).
+Adding EN signal on $memory\softshell.cpus[1].core.cpu.picorv32_core.cpuregs.regs[25]$23805 ($dff) from module user_proj_example (D = \softshell.cpus[1].core.cpu.picorv32_core.cpuregs.wdata, Q = \softshell.cpus[1].core.cpu.picorv32_core.cpuregs.regs[25]).
+Adding EN signal on $memory\softshell.cpus[1].core.cpu.picorv32_core.cpuregs.regs[24]$23803 ($dff) from module user_proj_example (D = \softshell.cpus[1].core.cpu.picorv32_core.cpuregs.wdata, Q = \softshell.cpus[1].core.cpu.picorv32_core.cpuregs.regs[24]).
+Adding EN signal on $memory\softshell.cpus[1].core.cpu.picorv32_core.cpuregs.regs[23]$23801 ($dff) from module user_proj_example (D = \softshell.cpus[1].core.cpu.picorv32_core.cpuregs.wdata, Q = \softshell.cpus[1].core.cpu.picorv32_core.cpuregs.regs[23]).
+Adding EN signal on $memory\softshell.cpus[1].core.cpu.picorv32_core.cpuregs.regs[22]$23799 ($dff) from module user_proj_example (D = \softshell.cpus[1].core.cpu.picorv32_core.cpuregs.wdata, Q = \softshell.cpus[1].core.cpu.picorv32_core.cpuregs.regs[22]).
+Adding EN signal on $memory\softshell.cpus[1].core.cpu.picorv32_core.cpuregs.regs[21]$23797 ($dff) from module user_proj_example (D = \softshell.cpus[1].core.cpu.picorv32_core.cpuregs.wdata, Q = \softshell.cpus[1].core.cpu.picorv32_core.cpuregs.regs[21]).
+Adding EN signal on $memory\softshell.cpus[1].core.cpu.picorv32_core.cpuregs.regs[20]$23795 ($dff) from module user_proj_example (D = \softshell.cpus[1].core.cpu.picorv32_core.cpuregs.wdata, Q = \softshell.cpus[1].core.cpu.picorv32_core.cpuregs.regs[20]).
+Adding EN signal on $memory\softshell.cpus[1].core.cpu.picorv32_core.cpuregs.regs[1]$23757 ($dff) from module user_proj_example (D = \softshell.cpus[1].core.cpu.picorv32_core.cpuregs.wdata, Q = \softshell.cpus[1].core.cpu.picorv32_core.cpuregs.regs[1]).
+Adding EN signal on $memory\softshell.cpus[1].core.cpu.picorv32_core.cpuregs.regs[19]$23793 ($dff) from module user_proj_example (D = \softshell.cpus[1].core.cpu.picorv32_core.cpuregs.wdata, Q = \softshell.cpus[1].core.cpu.picorv32_core.cpuregs.regs[19]).
+Adding EN signal on $memory\softshell.cpus[1].core.cpu.picorv32_core.cpuregs.regs[18]$23791 ($dff) from module user_proj_example (D = \softshell.cpus[1].core.cpu.picorv32_core.cpuregs.wdata, Q = \softshell.cpus[1].core.cpu.picorv32_core.cpuregs.regs[18]).
+Adding EN signal on $memory\softshell.cpus[1].core.cpu.picorv32_core.cpuregs.regs[17]$23789 ($dff) from module user_proj_example (D = \softshell.cpus[1].core.cpu.picorv32_core.cpuregs.wdata, Q = \softshell.cpus[1].core.cpu.picorv32_core.cpuregs.regs[17]).
+Adding EN signal on $memory\softshell.cpus[1].core.cpu.picorv32_core.cpuregs.regs[16]$23787 ($dff) from module user_proj_example (D = \softshell.cpus[1].core.cpu.picorv32_core.cpuregs.wdata, Q = \softshell.cpus[1].core.cpu.picorv32_core.cpuregs.regs[16]).
+Adding EN signal on $memory\softshell.cpus[1].core.cpu.picorv32_core.cpuregs.regs[15]$23785 ($dff) from module user_proj_example (D = \softshell.cpus[1].core.cpu.picorv32_core.cpuregs.wdata, Q = \softshell.cpus[1].core.cpu.picorv32_core.cpuregs.regs[15]).
+Adding EN signal on $memory\softshell.cpus[1].core.cpu.picorv32_core.cpuregs.regs[14]$23783 ($dff) from module user_proj_example (D = \softshell.cpus[1].core.cpu.picorv32_core.cpuregs.wdata, Q = \softshell.cpus[1].core.cpu.picorv32_core.cpuregs.regs[14]).
+Adding EN signal on $memory\softshell.cpus[1].core.cpu.picorv32_core.cpuregs.regs[13]$23781 ($dff) from module user_proj_example (D = \softshell.cpus[1].core.cpu.picorv32_core.cpuregs.wdata, Q = \softshell.cpus[1].core.cpu.picorv32_core.cpuregs.regs[13]).
+Adding EN signal on $memory\softshell.cpus[1].core.cpu.picorv32_core.cpuregs.regs[12]$23779 ($dff) from module user_proj_example (D = \softshell.cpus[1].core.cpu.picorv32_core.cpuregs.wdata, Q = \softshell.cpus[1].core.cpu.picorv32_core.cpuregs.regs[12]).
+Adding EN signal on $memory\softshell.cpus[1].core.cpu.picorv32_core.cpuregs.regs[11]$23777 ($dff) from module user_proj_example (D = \softshell.cpus[1].core.cpu.picorv32_core.cpuregs.wdata, Q = \softshell.cpus[1].core.cpu.picorv32_core.cpuregs.regs[11]).
+Adding EN signal on $memory\softshell.cpus[1].core.cpu.picorv32_core.cpuregs.regs[10]$23775 ($dff) from module user_proj_example (D = \softshell.cpus[1].core.cpu.picorv32_core.cpuregs.wdata, Q = \softshell.cpus[1].core.cpu.picorv32_core.cpuregs.regs[10]).
+Adding EN signal on $memory\softshell.cpus[1].core.cpu.picorv32_core.cpuregs.regs[0]$23755 ($dff) from module user_proj_example (D = \softshell.cpus[1].core.cpu.picorv32_core.cpuregs.wdata, Q = \softshell.cpus[1].core.cpu.picorv32_core.cpuregs.regs[0]).
+Adding EN signal on $memory\softshell.cpus[0].core.soc_mem.ram.ram3[9]$23484 ($dff) from module user_proj_example (D = \softshell.cpus[0].core.cpu.wbm_dat_o [31:24], Q = \softshell.cpus[0].core.soc_mem.ram.ram3[9]).
+Adding EN signal on $memory\softshell.cpus[0].core.soc_mem.ram.ram3[8]$23482 ($dff) from module user_proj_example (D = \softshell.cpus[0].core.cpu.wbm_dat_o [31:24], Q = \softshell.cpus[0].core.soc_mem.ram.ram3[8]).
+Adding EN signal on $memory\softshell.cpus[0].core.soc_mem.ram.ram3[7]$23480 ($dff) from module user_proj_example (D = \softshell.cpus[0].core.cpu.wbm_dat_o [31:24], Q = \softshell.cpus[0].core.soc_mem.ram.ram3[7]).
+Adding EN signal on $memory\softshell.cpus[0].core.soc_mem.ram.ram3[6]$23478 ($dff) from module user_proj_example (D = \softshell.cpus[0].core.cpu.wbm_dat_o [31:24], Q = \softshell.cpus[0].core.soc_mem.ram.ram3[6]).
+Adding EN signal on $memory\softshell.cpus[0].core.soc_mem.ram.ram3[5]$23476 ($dff) from module user_proj_example (D = \softshell.cpus[0].core.cpu.wbm_dat_o [31:24], Q = \softshell.cpus[0].core.soc_mem.ram.ram3[5]).
+Adding EN signal on $memory\softshell.cpus[0].core.soc_mem.ram.ram3[4]$23474 ($dff) from module user_proj_example (D = \softshell.cpus[0].core.cpu.wbm_dat_o [31:24], Q = \softshell.cpus[0].core.soc_mem.ram.ram3[4]).
+Adding EN signal on $memory\softshell.cpus[0].core.soc_mem.ram.ram3[3]$23472 ($dff) from module user_proj_example (D = \softshell.cpus[0].core.cpu.wbm_dat_o [31:24], Q = \softshell.cpus[0].core.soc_mem.ram.ram3[3]).
+Adding EN signal on $memory\softshell.cpus[0].core.soc_mem.ram.ram3[31]$23528 ($dff) from module user_proj_example (D = \softshell.cpus[0].core.cpu.wbm_dat_o [31:24], Q = \softshell.cpus[0].core.soc_mem.ram.ram3[31]).
+Adding EN signal on $memory\softshell.cpus[0].core.soc_mem.ram.ram3[30]$23526 ($dff) from module user_proj_example (D = \softshell.cpus[0].core.cpu.wbm_dat_o [31:24], Q = \softshell.cpus[0].core.soc_mem.ram.ram3[30]).
+Adding EN signal on $memory\softshell.cpus[0].core.soc_mem.ram.ram3[2]$23470 ($dff) from module user_proj_example (D = \softshell.cpus[0].core.cpu.wbm_dat_o [31:24], Q = \softshell.cpus[0].core.soc_mem.ram.ram3[2]).
+Adding EN signal on $memory\softshell.cpus[0].core.soc_mem.ram.ram3[29]$23524 ($dff) from module user_proj_example (D = \softshell.cpus[0].core.cpu.wbm_dat_o [31:24], Q = \softshell.cpus[0].core.soc_mem.ram.ram3[29]).
+Adding EN signal on $memory\softshell.cpus[0].core.soc_mem.ram.ram3[28]$23522 ($dff) from module user_proj_example (D = \softshell.cpus[0].core.cpu.wbm_dat_o [31:24], Q = \softshell.cpus[0].core.soc_mem.ram.ram3[28]).
+Adding EN signal on $memory\softshell.cpus[0].core.soc_mem.ram.ram3[27]$23520 ($dff) from module user_proj_example (D = \softshell.cpus[0].core.cpu.wbm_dat_o [31:24], Q = \softshell.cpus[0].core.soc_mem.ram.ram3[27]).
+Adding EN signal on $memory\softshell.cpus[0].core.soc_mem.ram.ram3[26]$23518 ($dff) from module user_proj_example (D = \softshell.cpus[0].core.cpu.wbm_dat_o [31:24], Q = \softshell.cpus[0].core.soc_mem.ram.ram3[26]).
+Adding EN signal on $memory\softshell.cpus[0].core.soc_mem.ram.ram3[25]$23516 ($dff) from module user_proj_example (D = \softshell.cpus[0].core.cpu.wbm_dat_o [31:24], Q = \softshell.cpus[0].core.soc_mem.ram.ram3[25]).
+Adding EN signal on $memory\softshell.cpus[0].core.soc_mem.ram.ram3[24]$23514 ($dff) from module user_proj_example (D = \softshell.cpus[0].core.cpu.wbm_dat_o [31:24], Q = \softshell.cpus[0].core.soc_mem.ram.ram3[24]).
+Adding EN signal on $memory\softshell.cpus[0].core.soc_mem.ram.ram3[23]$23512 ($dff) from module user_proj_example (D = \softshell.cpus[0].core.cpu.wbm_dat_o [31:24], Q = \softshell.cpus[0].core.soc_mem.ram.ram3[23]).
+Adding EN signal on $memory\softshell.cpus[0].core.soc_mem.ram.ram3[22]$23510 ($dff) from module user_proj_example (D = \softshell.cpus[0].core.cpu.wbm_dat_o [31:24], Q = \softshell.cpus[0].core.soc_mem.ram.ram3[22]).
+Adding EN signal on $memory\softshell.cpus[0].core.soc_mem.ram.ram3[21]$23508 ($dff) from module user_proj_example (D = \softshell.cpus[0].core.cpu.wbm_dat_o [31:24], Q = \softshell.cpus[0].core.soc_mem.ram.ram3[21]).
+Adding EN signal on $memory\softshell.cpus[0].core.soc_mem.ram.ram3[20]$23506 ($dff) from module user_proj_example (D = \softshell.cpus[0].core.cpu.wbm_dat_o [31:24], Q = \softshell.cpus[0].core.soc_mem.ram.ram3[20]).
+Adding EN signal on $memory\softshell.cpus[0].core.soc_mem.ram.ram3[1]$23468 ($dff) from module user_proj_example (D = \softshell.cpus[0].core.cpu.wbm_dat_o [31:24], Q = \softshell.cpus[0].core.soc_mem.ram.ram3[1]).
+Adding EN signal on $memory\softshell.cpus[0].core.soc_mem.ram.ram3[19]$23504 ($dff) from module user_proj_example (D = \softshell.cpus[0].core.cpu.wbm_dat_o [31:24], Q = \softshell.cpus[0].core.soc_mem.ram.ram3[19]).
+Adding EN signal on $memory\softshell.cpus[0].core.soc_mem.ram.ram3[18]$23502 ($dff) from module user_proj_example (D = \softshell.cpus[0].core.cpu.wbm_dat_o [31:24], Q = \softshell.cpus[0].core.soc_mem.ram.ram3[18]).
+Adding EN signal on $memory\softshell.cpus[0].core.soc_mem.ram.ram3[17]$23500 ($dff) from module user_proj_example (D = \softshell.cpus[0].core.cpu.wbm_dat_o [31:24], Q = \softshell.cpus[0].core.soc_mem.ram.ram3[17]).
+Adding EN signal on $memory\softshell.cpus[0].core.soc_mem.ram.ram3[16]$23498 ($dff) from module user_proj_example (D = \softshell.cpus[0].core.cpu.wbm_dat_o [31:24], Q = \softshell.cpus[0].core.soc_mem.ram.ram3[16]).
+Adding EN signal on $memory\softshell.cpus[0].core.soc_mem.ram.ram3[15]$23496 ($dff) from module user_proj_example (D = \softshell.cpus[0].core.cpu.wbm_dat_o [31:24], Q = \softshell.cpus[0].core.soc_mem.ram.ram3[15]).
+Adding EN signal on $memory\softshell.cpus[0].core.soc_mem.ram.ram3[14]$23494 ($dff) from module user_proj_example (D = \softshell.cpus[0].core.cpu.wbm_dat_o [31:24], Q = \softshell.cpus[0].core.soc_mem.ram.ram3[14]).
+Adding EN signal on $memory\softshell.cpus[0].core.soc_mem.ram.ram3[13]$23492 ($dff) from module user_proj_example (D = \softshell.cpus[0].core.cpu.wbm_dat_o [31:24], Q = \softshell.cpus[0].core.soc_mem.ram.ram3[13]).
+Adding EN signal on $memory\softshell.cpus[0].core.soc_mem.ram.ram3[12]$23490 ($dff) from module user_proj_example (D = \softshell.cpus[0].core.cpu.wbm_dat_o [31:24], Q = \softshell.cpus[0].core.soc_mem.ram.ram3[12]).
+Adding EN signal on $memory\softshell.cpus[0].core.soc_mem.ram.ram3[11]$23488 ($dff) from module user_proj_example (D = \softshell.cpus[0].core.cpu.wbm_dat_o [31:24], Q = \softshell.cpus[0].core.soc_mem.ram.ram3[11]).
+Adding EN signal on $memory\softshell.cpus[0].core.soc_mem.ram.ram3[10]$23486 ($dff) from module user_proj_example (D = \softshell.cpus[0].core.cpu.wbm_dat_o [31:24], Q = \softshell.cpus[0].core.soc_mem.ram.ram3[10]).
+Adding EN signal on $memory\softshell.cpus[0].core.soc_mem.ram.ram3[0]$23466 ($dff) from module user_proj_example (D = \softshell.cpus[0].core.cpu.wbm_dat_o [31:24], Q = \softshell.cpus[0].core.soc_mem.ram.ram3[0]).
+Adding EN signal on $memory\softshell.cpus[0].core.soc_mem.ram.ram2[9]$23195 ($dff) from module user_proj_example (D = \softshell.cpus[0].core.cpu.wbm_dat_o [23:16], Q = \softshell.cpus[0].core.soc_mem.ram.ram2[9]).
+Adding EN signal on $memory\softshell.cpus[0].core.soc_mem.ram.ram2[8]$23193 ($dff) from module user_proj_example (D = \softshell.cpus[0].core.cpu.wbm_dat_o [23:16], Q = \softshell.cpus[0].core.soc_mem.ram.ram2[8]).
+Adding EN signal on $memory\softshell.cpus[0].core.soc_mem.ram.ram2[7]$23191 ($dff) from module user_proj_example (D = \softshell.cpus[0].core.cpu.wbm_dat_o [23:16], Q = \softshell.cpus[0].core.soc_mem.ram.ram2[7]).
+Adding EN signal on $memory\softshell.cpus[0].core.soc_mem.ram.ram2[6]$23189 ($dff) from module user_proj_example (D = \softshell.cpus[0].core.cpu.wbm_dat_o [23:16], Q = \softshell.cpus[0].core.soc_mem.ram.ram2[6]).
+Adding EN signal on $memory\softshell.cpus[0].core.soc_mem.ram.ram2[5]$23187 ($dff) from module user_proj_example (D = \softshell.cpus[0].core.cpu.wbm_dat_o [23:16], Q = \softshell.cpus[0].core.soc_mem.ram.ram2[5]).
+Adding EN signal on $memory\softshell.cpus[0].core.soc_mem.ram.ram2[4]$23185 ($dff) from module user_proj_example (D = \softshell.cpus[0].core.cpu.wbm_dat_o [23:16], Q = \softshell.cpus[0].core.soc_mem.ram.ram2[4]).
+Adding EN signal on $memory\softshell.cpus[0].core.soc_mem.ram.ram2[3]$23183 ($dff) from module user_proj_example (D = \softshell.cpus[0].core.cpu.wbm_dat_o [23:16], Q = \softshell.cpus[0].core.soc_mem.ram.ram2[3]).
+Adding EN signal on $memory\softshell.cpus[0].core.soc_mem.ram.ram2[31]$23239 ($dff) from module user_proj_example (D = \softshell.cpus[0].core.cpu.wbm_dat_o [23:16], Q = \softshell.cpus[0].core.soc_mem.ram.ram2[31]).
+Adding EN signal on $memory\softshell.cpus[0].core.soc_mem.ram.ram2[30]$23237 ($dff) from module user_proj_example (D = \softshell.cpus[0].core.cpu.wbm_dat_o [23:16], Q = \softshell.cpus[0].core.soc_mem.ram.ram2[30]).
+Adding EN signal on $memory\softshell.cpus[0].core.soc_mem.ram.ram2[2]$23181 ($dff) from module user_proj_example (D = \softshell.cpus[0].core.cpu.wbm_dat_o [23:16], Q = \softshell.cpus[0].core.soc_mem.ram.ram2[2]).
+Adding EN signal on $memory\softshell.cpus[0].core.soc_mem.ram.ram2[29]$23235 ($dff) from module user_proj_example (D = \softshell.cpus[0].core.cpu.wbm_dat_o [23:16], Q = \softshell.cpus[0].core.soc_mem.ram.ram2[29]).
+Adding EN signal on $memory\softshell.cpus[0].core.soc_mem.ram.ram2[28]$23233 ($dff) from module user_proj_example (D = \softshell.cpus[0].core.cpu.wbm_dat_o [23:16], Q = \softshell.cpus[0].core.soc_mem.ram.ram2[28]).
+Adding EN signal on $memory\softshell.cpus[0].core.soc_mem.ram.ram2[27]$23231 ($dff) from module user_proj_example (D = \softshell.cpus[0].core.cpu.wbm_dat_o [23:16], Q = \softshell.cpus[0].core.soc_mem.ram.ram2[27]).
+Adding EN signal on $memory\softshell.cpus[0].core.soc_mem.ram.ram2[26]$23229 ($dff) from module user_proj_example (D = \softshell.cpus[0].core.cpu.wbm_dat_o [23:16], Q = \softshell.cpus[0].core.soc_mem.ram.ram2[26]).
+Adding EN signal on $memory\softshell.cpus[0].core.soc_mem.ram.ram2[25]$23227 ($dff) from module user_proj_example (D = \softshell.cpus[0].core.cpu.wbm_dat_o [23:16], Q = \softshell.cpus[0].core.soc_mem.ram.ram2[25]).
+Adding EN signal on $memory\softshell.cpus[0].core.soc_mem.ram.ram2[24]$23225 ($dff) from module user_proj_example (D = \softshell.cpus[0].core.cpu.wbm_dat_o [23:16], Q = \softshell.cpus[0].core.soc_mem.ram.ram2[24]).
+Adding EN signal on $memory\softshell.cpus[0].core.soc_mem.ram.ram2[23]$23223 ($dff) from module user_proj_example (D = \softshell.cpus[0].core.cpu.wbm_dat_o [23:16], Q = \softshell.cpus[0].core.soc_mem.ram.ram2[23]).
+Adding EN signal on $memory\softshell.cpus[0].core.soc_mem.ram.ram2[22]$23221 ($dff) from module user_proj_example (D = \softshell.cpus[0].core.cpu.wbm_dat_o [23:16], Q = \softshell.cpus[0].core.soc_mem.ram.ram2[22]).
+Adding EN signal on $memory\softshell.cpus[0].core.soc_mem.ram.ram2[21]$23219 ($dff) from module user_proj_example (D = \softshell.cpus[0].core.cpu.wbm_dat_o [23:16], Q = \softshell.cpus[0].core.soc_mem.ram.ram2[21]).
+Adding EN signal on $memory\softshell.cpus[0].core.soc_mem.ram.ram2[20]$23217 ($dff) from module user_proj_example (D = \softshell.cpus[0].core.cpu.wbm_dat_o [23:16], Q = \softshell.cpus[0].core.soc_mem.ram.ram2[20]).
+Adding EN signal on $memory\softshell.cpus[0].core.soc_mem.ram.ram2[1]$23179 ($dff) from module user_proj_example (D = \softshell.cpus[0].core.cpu.wbm_dat_o [23:16], Q = \softshell.cpus[0].core.soc_mem.ram.ram2[1]).
+Adding EN signal on $memory\softshell.cpus[0].core.soc_mem.ram.ram2[19]$23215 ($dff) from module user_proj_example (D = \softshell.cpus[0].core.cpu.wbm_dat_o [23:16], Q = \softshell.cpus[0].core.soc_mem.ram.ram2[19]).
+Adding EN signal on $memory\softshell.cpus[0].core.soc_mem.ram.ram2[18]$23213 ($dff) from module user_proj_example (D = \softshell.cpus[0].core.cpu.wbm_dat_o [23:16], Q = \softshell.cpus[0].core.soc_mem.ram.ram2[18]).
+Adding EN signal on $memory\softshell.cpus[0].core.soc_mem.ram.ram2[17]$23211 ($dff) from module user_proj_example (D = \softshell.cpus[0].core.cpu.wbm_dat_o [23:16], Q = \softshell.cpus[0].core.soc_mem.ram.ram2[17]).
+Adding EN signal on $memory\softshell.cpus[0].core.soc_mem.ram.ram2[16]$23209 ($dff) from module user_proj_example (D = \softshell.cpus[0].core.cpu.wbm_dat_o [23:16], Q = \softshell.cpus[0].core.soc_mem.ram.ram2[16]).
+Adding EN signal on $memory\softshell.cpus[0].core.soc_mem.ram.ram2[15]$23207 ($dff) from module user_proj_example (D = \softshell.cpus[0].core.cpu.wbm_dat_o [23:16], Q = \softshell.cpus[0].core.soc_mem.ram.ram2[15]).
+Adding EN signal on $memory\softshell.cpus[0].core.soc_mem.ram.ram2[14]$23205 ($dff) from module user_proj_example (D = \softshell.cpus[0].core.cpu.wbm_dat_o [23:16], Q = \softshell.cpus[0].core.soc_mem.ram.ram2[14]).
+Adding EN signal on $memory\softshell.cpus[0].core.soc_mem.ram.ram2[13]$23203 ($dff) from module user_proj_example (D = \softshell.cpus[0].core.cpu.wbm_dat_o [23:16], Q = \softshell.cpus[0].core.soc_mem.ram.ram2[13]).
+Adding EN signal on $memory\softshell.cpus[0].core.soc_mem.ram.ram2[12]$23201 ($dff) from module user_proj_example (D = \softshell.cpus[0].core.cpu.wbm_dat_o [23:16], Q = \softshell.cpus[0].core.soc_mem.ram.ram2[12]).
+Adding EN signal on $memory\softshell.cpus[0].core.soc_mem.ram.ram2[11]$23199 ($dff) from module user_proj_example (D = \softshell.cpus[0].core.cpu.wbm_dat_o [23:16], Q = \softshell.cpus[0].core.soc_mem.ram.ram2[11]).
+Adding EN signal on $memory\softshell.cpus[0].core.soc_mem.ram.ram2[10]$23197 ($dff) from module user_proj_example (D = \softshell.cpus[0].core.cpu.wbm_dat_o [23:16], Q = \softshell.cpus[0].core.soc_mem.ram.ram2[10]).
+Adding EN signal on $memory\softshell.cpus[0].core.soc_mem.ram.ram2[0]$23177 ($dff) from module user_proj_example (D = \softshell.cpus[0].core.cpu.wbm_dat_o [23:16], Q = \softshell.cpus[0].core.soc_mem.ram.ram2[0]).
+Adding EN signal on $memory\softshell.cpus[0].core.soc_mem.ram.ram1[9]$22906 ($dff) from module user_proj_example (D = \softshell.cpus[0].core.cpu.wbm_dat_o [15:8], Q = \softshell.cpus[0].core.soc_mem.ram.ram1[9]).
+Adding EN signal on $memory\softshell.cpus[0].core.soc_mem.ram.ram1[8]$22904 ($dff) from module user_proj_example (D = \softshell.cpus[0].core.cpu.wbm_dat_o [15:8], Q = \softshell.cpus[0].core.soc_mem.ram.ram1[8]).
+Adding EN signal on $memory\softshell.cpus[0].core.soc_mem.ram.ram1[7]$22902 ($dff) from module user_proj_example (D = \softshell.cpus[0].core.cpu.wbm_dat_o [15:8], Q = \softshell.cpus[0].core.soc_mem.ram.ram1[7]).
+Adding EN signal on $memory\softshell.cpus[0].core.soc_mem.ram.ram1[6]$22900 ($dff) from module user_proj_example (D = \softshell.cpus[0].core.cpu.wbm_dat_o [15:8], Q = \softshell.cpus[0].core.soc_mem.ram.ram1[6]).
+Adding EN signal on $memory\softshell.cpus[0].core.soc_mem.ram.ram1[5]$22898 ($dff) from module user_proj_example (D = \softshell.cpus[0].core.cpu.wbm_dat_o [15:8], Q = \softshell.cpus[0].core.soc_mem.ram.ram1[5]).
+Adding EN signal on $memory\softshell.cpus[0].core.soc_mem.ram.ram1[4]$22896 ($dff) from module user_proj_example (D = \softshell.cpus[0].core.cpu.wbm_dat_o [15:8], Q = \softshell.cpus[0].core.soc_mem.ram.ram1[4]).
+Adding EN signal on $memory\softshell.cpus[0].core.soc_mem.ram.ram1[3]$22894 ($dff) from module user_proj_example (D = \softshell.cpus[0].core.cpu.wbm_dat_o [15:8], Q = \softshell.cpus[0].core.soc_mem.ram.ram1[3]).
+Adding EN signal on $memory\softshell.cpus[0].core.soc_mem.ram.ram1[31]$22950 ($dff) from module user_proj_example (D = \softshell.cpus[0].core.cpu.wbm_dat_o [15:8], Q = \softshell.cpus[0].core.soc_mem.ram.ram1[31]).
+Adding EN signal on $memory\softshell.cpus[0].core.soc_mem.ram.ram1[30]$22948 ($dff) from module user_proj_example (D = \softshell.cpus[0].core.cpu.wbm_dat_o [15:8], Q = \softshell.cpus[0].core.soc_mem.ram.ram1[30]).
+Adding EN signal on $memory\softshell.cpus[0].core.soc_mem.ram.ram1[2]$22892 ($dff) from module user_proj_example (D = \softshell.cpus[0].core.cpu.wbm_dat_o [15:8], Q = \softshell.cpus[0].core.soc_mem.ram.ram1[2]).
+Adding EN signal on $memory\softshell.cpus[0].core.soc_mem.ram.ram1[29]$22946 ($dff) from module user_proj_example (D = \softshell.cpus[0].core.cpu.wbm_dat_o [15:8], Q = \softshell.cpus[0].core.soc_mem.ram.ram1[29]).
+Adding EN signal on $memory\softshell.cpus[0].core.soc_mem.ram.ram1[28]$22944 ($dff) from module user_proj_example (D = \softshell.cpus[0].core.cpu.wbm_dat_o [15:8], Q = \softshell.cpus[0].core.soc_mem.ram.ram1[28]).
+Adding EN signal on $memory\softshell.cpus[0].core.soc_mem.ram.ram1[27]$22942 ($dff) from module user_proj_example (D = \softshell.cpus[0].core.cpu.wbm_dat_o [15:8], Q = \softshell.cpus[0].core.soc_mem.ram.ram1[27]).
+Adding EN signal on $memory\softshell.cpus[0].core.soc_mem.ram.ram1[26]$22940 ($dff) from module user_proj_example (D = \softshell.cpus[0].core.cpu.wbm_dat_o [15:8], Q = \softshell.cpus[0].core.soc_mem.ram.ram1[26]).
+Adding EN signal on $memory\softshell.cpus[0].core.soc_mem.ram.ram1[25]$22938 ($dff) from module user_proj_example (D = \softshell.cpus[0].core.cpu.wbm_dat_o [15:8], Q = \softshell.cpus[0].core.soc_mem.ram.ram1[25]).
+Adding EN signal on $memory\softshell.cpus[0].core.soc_mem.ram.ram1[24]$22936 ($dff) from module user_proj_example (D = \softshell.cpus[0].core.cpu.wbm_dat_o [15:8], Q = \softshell.cpus[0].core.soc_mem.ram.ram1[24]).
+Adding EN signal on $memory\softshell.cpus[0].core.soc_mem.ram.ram1[23]$22934 ($dff) from module user_proj_example (D = \softshell.cpus[0].core.cpu.wbm_dat_o [15:8], Q = \softshell.cpus[0].core.soc_mem.ram.ram1[23]).
+Adding EN signal on $memory\softshell.cpus[0].core.soc_mem.ram.ram1[22]$22932 ($dff) from module user_proj_example (D = \softshell.cpus[0].core.cpu.wbm_dat_o [15:8], Q = \softshell.cpus[0].core.soc_mem.ram.ram1[22]).
+Adding EN signal on $memory\softshell.cpus[0].core.soc_mem.ram.ram1[21]$22930 ($dff) from module user_proj_example (D = \softshell.cpus[0].core.cpu.wbm_dat_o [15:8], Q = \softshell.cpus[0].core.soc_mem.ram.ram1[21]).
+Adding EN signal on $memory\softshell.cpus[0].core.soc_mem.ram.ram1[20]$22928 ($dff) from module user_proj_example (D = \softshell.cpus[0].core.cpu.wbm_dat_o [15:8], Q = \softshell.cpus[0].core.soc_mem.ram.ram1[20]).
+Adding EN signal on $memory\softshell.cpus[0].core.soc_mem.ram.ram1[1]$22890 ($dff) from module user_proj_example (D = \softshell.cpus[0].core.cpu.wbm_dat_o [15:8], Q = \softshell.cpus[0].core.soc_mem.ram.ram1[1]).
+Adding EN signal on $memory\softshell.cpus[0].core.soc_mem.ram.ram1[19]$22926 ($dff) from module user_proj_example (D = \softshell.cpus[0].core.cpu.wbm_dat_o [15:8], Q = \softshell.cpus[0].core.soc_mem.ram.ram1[19]).
+Adding EN signal on $memory\softshell.cpus[0].core.soc_mem.ram.ram1[18]$22924 ($dff) from module user_proj_example (D = \softshell.cpus[0].core.cpu.wbm_dat_o [15:8], Q = \softshell.cpus[0].core.soc_mem.ram.ram1[18]).
+Adding EN signal on $memory\softshell.cpus[0].core.soc_mem.ram.ram1[17]$22922 ($dff) from module user_proj_example (D = \softshell.cpus[0].core.cpu.wbm_dat_o [15:8], Q = \softshell.cpus[0].core.soc_mem.ram.ram1[17]).
+Adding EN signal on $memory\softshell.cpus[0].core.soc_mem.ram.ram1[16]$22920 ($dff) from module user_proj_example (D = \softshell.cpus[0].core.cpu.wbm_dat_o [15:8], Q = \softshell.cpus[0].core.soc_mem.ram.ram1[16]).
+Adding EN signal on $memory\softshell.cpus[0].core.soc_mem.ram.ram1[15]$22918 ($dff) from module user_proj_example (D = \softshell.cpus[0].core.cpu.wbm_dat_o [15:8], Q = \softshell.cpus[0].core.soc_mem.ram.ram1[15]).
+Adding EN signal on $memory\softshell.cpus[0].core.soc_mem.ram.ram1[14]$22916 ($dff) from module user_proj_example (D = \softshell.cpus[0].core.cpu.wbm_dat_o [15:8], Q = \softshell.cpus[0].core.soc_mem.ram.ram1[14]).
+Adding EN signal on $memory\softshell.cpus[0].core.soc_mem.ram.ram1[13]$22914 ($dff) from module user_proj_example (D = \softshell.cpus[0].core.cpu.wbm_dat_o [15:8], Q = \softshell.cpus[0].core.soc_mem.ram.ram1[13]).
+Adding EN signal on $memory\softshell.cpus[0].core.soc_mem.ram.ram1[12]$22912 ($dff) from module user_proj_example (D = \softshell.cpus[0].core.cpu.wbm_dat_o [15:8], Q = \softshell.cpus[0].core.soc_mem.ram.ram1[12]).
+Adding EN signal on $memory\softshell.cpus[0].core.soc_mem.ram.ram1[11]$22910 ($dff) from module user_proj_example (D = \softshell.cpus[0].core.cpu.wbm_dat_o [15:8], Q = \softshell.cpus[0].core.soc_mem.ram.ram1[11]).
+Adding EN signal on $memory\softshell.cpus[0].core.soc_mem.ram.ram1[10]$22908 ($dff) from module user_proj_example (D = \softshell.cpus[0].core.cpu.wbm_dat_o [15:8], Q = \softshell.cpus[0].core.soc_mem.ram.ram1[10]).
+Adding EN signal on $memory\softshell.cpus[0].core.soc_mem.ram.ram1[0]$22888 ($dff) from module user_proj_example (D = \softshell.cpus[0].core.cpu.wbm_dat_o [15:8], Q = \softshell.cpus[0].core.soc_mem.ram.ram1[0]).
+Adding EN signal on $memory\softshell.cpus[0].core.soc_mem.ram.ram0[9]$22501 ($dff) from module user_proj_example (D = \softshell.cpus[0].core.cpu.wbm_dat_o [7:0], Q = \softshell.cpus[0].core.soc_mem.ram.ram0[9]).
+Adding EN signal on $memory\softshell.cpus[0].core.soc_mem.ram.ram0[8]$22499 ($dff) from module user_proj_example (D = \softshell.cpus[0].core.cpu.wbm_dat_o [7:0], Q = \softshell.cpus[0].core.soc_mem.ram.ram0[8]).
+Adding EN signal on $memory\softshell.cpus[0].core.soc_mem.ram.ram0[7]$22497 ($dff) from module user_proj_example (D = \softshell.cpus[0].core.cpu.wbm_dat_o [7:0], Q = \softshell.cpus[0].core.soc_mem.ram.ram0[7]).
+Adding EN signal on $memory\softshell.cpus[0].core.soc_mem.ram.ram0[6]$22495 ($dff) from module user_proj_example (D = \softshell.cpus[0].core.cpu.wbm_dat_o [7:0], Q = \softshell.cpus[0].core.soc_mem.ram.ram0[6]).
+Adding EN signal on $memory\softshell.cpus[0].core.soc_mem.ram.ram0[5]$22493 ($dff) from module user_proj_example (D = \softshell.cpus[0].core.cpu.wbm_dat_o [7:0], Q = \softshell.cpus[0].core.soc_mem.ram.ram0[5]).
+Adding EN signal on $memory\softshell.cpus[0].core.soc_mem.ram.ram0[4]$22491 ($dff) from module user_proj_example (D = \softshell.cpus[0].core.cpu.wbm_dat_o [7:0], Q = \softshell.cpus[0].core.soc_mem.ram.ram0[4]).
+Adding EN signal on $memory\softshell.cpus[0].core.soc_mem.ram.ram0[3]$22489 ($dff) from module user_proj_example (D = \softshell.cpus[0].core.cpu.wbm_dat_o [7:0], Q = \softshell.cpus[0].core.soc_mem.ram.ram0[3]).
+Adding EN signal on $memory\softshell.cpus[0].core.soc_mem.ram.ram0[31]$22545 ($dff) from module user_proj_example (D = \softshell.cpus[0].core.cpu.wbm_dat_o [7:0], Q = \softshell.cpus[0].core.soc_mem.ram.ram0[31]).
+Adding EN signal on $memory\softshell.cpus[0].core.soc_mem.ram.ram0[30]$22543 ($dff) from module user_proj_example (D = \softshell.cpus[0].core.cpu.wbm_dat_o [7:0], Q = \softshell.cpus[0].core.soc_mem.ram.ram0[30]).
+Adding EN signal on $memory\softshell.cpus[0].core.soc_mem.ram.ram0[2]$22487 ($dff) from module user_proj_example (D = \softshell.cpus[0].core.cpu.wbm_dat_o [7:0], Q = \softshell.cpus[0].core.soc_mem.ram.ram0[2]).
+Adding EN signal on $memory\softshell.cpus[0].core.soc_mem.ram.ram0[29]$22541 ($dff) from module user_proj_example (D = \softshell.cpus[0].core.cpu.wbm_dat_o [7:0], Q = \softshell.cpus[0].core.soc_mem.ram.ram0[29]).
+Adding EN signal on $memory\softshell.cpus[0].core.soc_mem.ram.ram0[28]$22539 ($dff) from module user_proj_example (D = \softshell.cpus[0].core.cpu.wbm_dat_o [7:0], Q = \softshell.cpus[0].core.soc_mem.ram.ram0[28]).
+Adding EN signal on $memory\softshell.cpus[0].core.soc_mem.ram.ram0[27]$22537 ($dff) from module user_proj_example (D = \softshell.cpus[0].core.cpu.wbm_dat_o [7:0], Q = \softshell.cpus[0].core.soc_mem.ram.ram0[27]).
+Adding EN signal on $memory\softshell.cpus[0].core.soc_mem.ram.ram0[26]$22535 ($dff) from module user_proj_example (D = \softshell.cpus[0].core.cpu.wbm_dat_o [7:0], Q = \softshell.cpus[0].core.soc_mem.ram.ram0[26]).
+Adding EN signal on $memory\softshell.cpus[0].core.soc_mem.ram.ram0[25]$22533 ($dff) from module user_proj_example (D = \softshell.cpus[0].core.cpu.wbm_dat_o [7:0], Q = \softshell.cpus[0].core.soc_mem.ram.ram0[25]).
+Adding EN signal on $memory\softshell.cpus[0].core.soc_mem.ram.ram0[24]$22531 ($dff) from module user_proj_example (D = \softshell.cpus[0].core.cpu.wbm_dat_o [7:0], Q = \softshell.cpus[0].core.soc_mem.ram.ram0[24]).
+Adding EN signal on $memory\softshell.cpus[0].core.soc_mem.ram.ram0[23]$22529 ($dff) from module user_proj_example (D = \softshell.cpus[0].core.cpu.wbm_dat_o [7:0], Q = \softshell.cpus[0].core.soc_mem.ram.ram0[23]).
+Adding EN signal on $memory\softshell.cpus[0].core.soc_mem.ram.ram0[22]$22527 ($dff) from module user_proj_example (D = \softshell.cpus[0].core.cpu.wbm_dat_o [7:0], Q = \softshell.cpus[0].core.soc_mem.ram.ram0[22]).
+Adding EN signal on $memory\softshell.cpus[0].core.soc_mem.ram.ram0[21]$22525 ($dff) from module user_proj_example (D = \softshell.cpus[0].core.cpu.wbm_dat_o [7:0], Q = \softshell.cpus[0].core.soc_mem.ram.ram0[21]).
+Adding EN signal on $memory\softshell.cpus[0].core.soc_mem.ram.ram0[20]$22523 ($dff) from module user_proj_example (D = \softshell.cpus[0].core.cpu.wbm_dat_o [7:0], Q = \softshell.cpus[0].core.soc_mem.ram.ram0[20]).
+Adding EN signal on $memory\softshell.cpus[0].core.soc_mem.ram.ram0[1]$22485 ($dff) from module user_proj_example (D = \softshell.cpus[0].core.cpu.wbm_dat_o [7:0], Q = \softshell.cpus[0].core.soc_mem.ram.ram0[1]).
+Adding EN signal on $memory\softshell.cpus[0].core.soc_mem.ram.ram0[19]$22521 ($dff) from module user_proj_example (D = \softshell.cpus[0].core.cpu.wbm_dat_o [7:0], Q = \softshell.cpus[0].core.soc_mem.ram.ram0[19]).
+Adding EN signal on $memory\softshell.cpus[0].core.soc_mem.ram.ram0[18]$22519 ($dff) from module user_proj_example (D = \softshell.cpus[0].core.cpu.wbm_dat_o [7:0], Q = \softshell.cpus[0].core.soc_mem.ram.ram0[18]).
+Adding EN signal on $memory\softshell.cpus[0].core.soc_mem.ram.ram0[17]$22517 ($dff) from module user_proj_example (D = \softshell.cpus[0].core.cpu.wbm_dat_o [7:0], Q = \softshell.cpus[0].core.soc_mem.ram.ram0[17]).
+Adding EN signal on $memory\softshell.cpus[0].core.soc_mem.ram.ram0[16]$22515 ($dff) from module user_proj_example (D = \softshell.cpus[0].core.cpu.wbm_dat_o [7:0], Q = \softshell.cpus[0].core.soc_mem.ram.ram0[16]).
+Adding EN signal on $memory\softshell.cpus[0].core.soc_mem.ram.ram0[15]$22513 ($dff) from module user_proj_example (D = \softshell.cpus[0].core.cpu.wbm_dat_o [7:0], Q = \softshell.cpus[0].core.soc_mem.ram.ram0[15]).
+Adding EN signal on $memory\softshell.cpus[0].core.soc_mem.ram.ram0[14]$22511 ($dff) from module user_proj_example (D = \softshell.cpus[0].core.cpu.wbm_dat_o [7:0], Q = \softshell.cpus[0].core.soc_mem.ram.ram0[14]).
+Adding EN signal on $memory\softshell.cpus[0].core.soc_mem.ram.ram0[13]$22509 ($dff) from module user_proj_example (D = \softshell.cpus[0].core.cpu.wbm_dat_o [7:0], Q = \softshell.cpus[0].core.soc_mem.ram.ram0[13]).
+Adding EN signal on $memory\softshell.cpus[0].core.soc_mem.ram.ram0[12]$22507 ($dff) from module user_proj_example (D = \softshell.cpus[0].core.cpu.wbm_dat_o [7:0], Q = \softshell.cpus[0].core.soc_mem.ram.ram0[12]).
+Adding EN signal on $memory\softshell.cpus[0].core.soc_mem.ram.ram0[11]$22505 ($dff) from module user_proj_example (D = \softshell.cpus[0].core.cpu.wbm_dat_o [7:0], Q = \softshell.cpus[0].core.soc_mem.ram.ram0[11]).
+Adding EN signal on $memory\softshell.cpus[0].core.soc_mem.ram.ram0[10]$22503 ($dff) from module user_proj_example (D = \softshell.cpus[0].core.cpu.wbm_dat_o [7:0], Q = \softshell.cpus[0].core.soc_mem.ram.ram0[10]).
+Adding EN signal on $memory\softshell.cpus[0].core.soc_mem.ram.ram0[0]$22483 ($dff) from module user_proj_example (D = \softshell.cpus[0].core.cpu.wbm_dat_o [7:0], Q = \softshell.cpus[0].core.soc_mem.ram.ram0[0]).
+Adding EN signal on $memory\softshell.cpus[0].core.flexio.out_fifo.mem[3]$22440 ($dff) from module user_proj_example (D = \softshell.cpus[0].core.flexio.out_wr_data, Q = \softshell.cpus[0].core.flexio.out_fifo.mem[3]).
+Adding EN signal on $memory\softshell.cpus[0].core.flexio.out_fifo.mem[2]$22438 ($dff) from module user_proj_example (D = \softshell.cpus[0].core.flexio.out_wr_data, Q = \softshell.cpus[0].core.flexio.out_fifo.mem[2]).
+Adding EN signal on $memory\softshell.cpus[0].core.flexio.out_fifo.mem[1]$22436 ($dff) from module user_proj_example (D = \softshell.cpus[0].core.flexio.out_wr_data, Q = \softshell.cpus[0].core.flexio.out_fifo.mem[1]).
+Adding EN signal on $memory\softshell.cpus[0].core.flexio.out_fifo.mem[0]$22434 ($dff) from module user_proj_example (D = \softshell.cpus[0].core.flexio.out_wr_data, Q = \softshell.cpus[0].core.flexio.out_fifo.mem[0]).
+Adding EN signal on $memory\softshell.cpus[0].core.cpu.picorv32_core.cpuregs.regs[9]$21954 ($dff) from module user_proj_example (D = \softshell.cpus[0].core.cpu.picorv32_core.cpuregs.wdata, Q = \softshell.cpus[0].core.cpu.picorv32_core.cpuregs.regs[9]).
+Adding EN signal on $memory\softshell.cpus[0].core.cpu.picorv32_core.cpuregs.regs[8]$21952 ($dff) from module user_proj_example (D = \softshell.cpus[0].core.cpu.picorv32_core.cpuregs.wdata, Q = \softshell.cpus[0].core.cpu.picorv32_core.cpuregs.regs[8]).
+Adding EN signal on $memory\softshell.cpus[0].core.cpu.picorv32_core.cpuregs.regs[7]$21950 ($dff) from module user_proj_example (D = \softshell.cpus[0].core.cpu.picorv32_core.cpuregs.wdata, Q = \softshell.cpus[0].core.cpu.picorv32_core.cpuregs.regs[7]).
+Adding EN signal on $memory\softshell.cpus[0].core.cpu.picorv32_core.cpuregs.regs[6]$21948 ($dff) from module user_proj_example (D = \softshell.cpus[0].core.cpu.picorv32_core.cpuregs.wdata, Q = \softshell.cpus[0].core.cpu.picorv32_core.cpuregs.regs[6]).
+Adding EN signal on $memory\softshell.cpus[0].core.cpu.picorv32_core.cpuregs.regs[5]$21946 ($dff) from module user_proj_example (D = \softshell.cpus[0].core.cpu.picorv32_core.cpuregs.wdata, Q = \softshell.cpus[0].core.cpu.picorv32_core.cpuregs.regs[5]).
+Adding EN signal on $memory\softshell.cpus[0].core.cpu.picorv32_core.cpuregs.regs[4]$21944 ($dff) from module user_proj_example (D = \softshell.cpus[0].core.cpu.picorv32_core.cpuregs.wdata, Q = \softshell.cpus[0].core.cpu.picorv32_core.cpuregs.regs[4]).
+Adding EN signal on $memory\softshell.cpus[0].core.cpu.picorv32_core.cpuregs.regs[3]$21942 ($dff) from module user_proj_example (D = \softshell.cpus[0].core.cpu.picorv32_core.cpuregs.wdata, Q = \softshell.cpus[0].core.cpu.picorv32_core.cpuregs.regs[3]).
+Adding EN signal on $memory\softshell.cpus[0].core.cpu.picorv32_core.cpuregs.regs[31]$21998 ($dff) from module user_proj_example (D = \softshell.cpus[0].core.cpu.picorv32_core.cpuregs.wdata, Q = \softshell.cpus[0].core.cpu.picorv32_core.cpuregs.regs[31]).
+Adding EN signal on $memory\softshell.cpus[0].core.cpu.picorv32_core.cpuregs.regs[30]$21996 ($dff) from module user_proj_example (D = \softshell.cpus[0].core.cpu.picorv32_core.cpuregs.wdata, Q = \softshell.cpus[0].core.cpu.picorv32_core.cpuregs.regs[30]).
+Adding EN signal on $memory\softshell.cpus[0].core.cpu.picorv32_core.cpuregs.regs[2]$21940 ($dff) from module user_proj_example (D = \softshell.cpus[0].core.cpu.picorv32_core.cpuregs.wdata, Q = \softshell.cpus[0].core.cpu.picorv32_core.cpuregs.regs[2]).
+Adding EN signal on $memory\softshell.cpus[0].core.cpu.picorv32_core.cpuregs.regs[29]$21994 ($dff) from module user_proj_example (D = \softshell.cpus[0].core.cpu.picorv32_core.cpuregs.wdata, Q = \softshell.cpus[0].core.cpu.picorv32_core.cpuregs.regs[29]).
+Adding EN signal on $memory\softshell.cpus[0].core.cpu.picorv32_core.cpuregs.regs[28]$21992 ($dff) from module user_proj_example (D = \softshell.cpus[0].core.cpu.picorv32_core.cpuregs.wdata, Q = \softshell.cpus[0].core.cpu.picorv32_core.cpuregs.regs[28]).
+Adding EN signal on $memory\softshell.cpus[0].core.cpu.picorv32_core.cpuregs.regs[27]$21990 ($dff) from module user_proj_example (D = \softshell.cpus[0].core.cpu.picorv32_core.cpuregs.wdata, Q = \softshell.cpus[0].core.cpu.picorv32_core.cpuregs.regs[27]).
+Adding EN signal on $memory\softshell.cpus[0].core.cpu.picorv32_core.cpuregs.regs[26]$21988 ($dff) from module user_proj_example (D = \softshell.cpus[0].core.cpu.picorv32_core.cpuregs.wdata, Q = \softshell.cpus[0].core.cpu.picorv32_core.cpuregs.regs[26]).
+Adding EN signal on $memory\softshell.cpus[0].core.cpu.picorv32_core.cpuregs.regs[25]$21986 ($dff) from module user_proj_example (D = \softshell.cpus[0].core.cpu.picorv32_core.cpuregs.wdata, Q = \softshell.cpus[0].core.cpu.picorv32_core.cpuregs.regs[25]).
+Adding EN signal on $memory\softshell.cpus[0].core.cpu.picorv32_core.cpuregs.regs[24]$21984 ($dff) from module user_proj_example (D = \softshell.cpus[0].core.cpu.picorv32_core.cpuregs.wdata, Q = \softshell.cpus[0].core.cpu.picorv32_core.cpuregs.regs[24]).
+Adding EN signal on $memory\softshell.cpus[0].core.cpu.picorv32_core.cpuregs.regs[23]$21982 ($dff) from module user_proj_example (D = \softshell.cpus[0].core.cpu.picorv32_core.cpuregs.wdata, Q = \softshell.cpus[0].core.cpu.picorv32_core.cpuregs.regs[23]).
+Adding EN signal on $memory\softshell.cpus[0].core.cpu.picorv32_core.cpuregs.regs[22]$21980 ($dff) from module user_proj_example (D = \softshell.cpus[0].core.cpu.picorv32_core.cpuregs.wdata, Q = \softshell.cpus[0].core.cpu.picorv32_core.cpuregs.regs[22]).
+Adding EN signal on $memory\softshell.cpus[0].core.cpu.picorv32_core.cpuregs.regs[21]$21978 ($dff) from module user_proj_example (D = \softshell.cpus[0].core.cpu.picorv32_core.cpuregs.wdata, Q = \softshell.cpus[0].core.cpu.picorv32_core.cpuregs.regs[21]).
+Adding EN signal on $memory\softshell.cpus[0].core.cpu.picorv32_core.cpuregs.regs[20]$21976 ($dff) from module user_proj_example (D = \softshell.cpus[0].core.cpu.picorv32_core.cpuregs.wdata, Q = \softshell.cpus[0].core.cpu.picorv32_core.cpuregs.regs[20]).
+Adding EN signal on $memory\softshell.cpus[0].core.cpu.picorv32_core.cpuregs.regs[1]$21938 ($dff) from module user_proj_example (D = \softshell.cpus[0].core.cpu.picorv32_core.cpuregs.wdata, Q = \softshell.cpus[0].core.cpu.picorv32_core.cpuregs.regs[1]).
+Adding EN signal on $memory\softshell.cpus[0].core.cpu.picorv32_core.cpuregs.regs[19]$21974 ($dff) from module user_proj_example (D = \softshell.cpus[0].core.cpu.picorv32_core.cpuregs.wdata, Q = \softshell.cpus[0].core.cpu.picorv32_core.cpuregs.regs[19]).
+Adding EN signal on $memory\softshell.cpus[0].core.cpu.picorv32_core.cpuregs.regs[18]$21972 ($dff) from module user_proj_example (D = \softshell.cpus[0].core.cpu.picorv32_core.cpuregs.wdata, Q = \softshell.cpus[0].core.cpu.picorv32_core.cpuregs.regs[18]).
+Adding EN signal on $memory\softshell.cpus[0].core.cpu.picorv32_core.cpuregs.regs[17]$21970 ($dff) from module user_proj_example (D = \softshell.cpus[0].core.cpu.picorv32_core.cpuregs.wdata, Q = \softshell.cpus[0].core.cpu.picorv32_core.cpuregs.regs[17]).
+Adding EN signal on $memory\softshell.cpus[0].core.cpu.picorv32_core.cpuregs.regs[16]$21968 ($dff) from module user_proj_example (D = \softshell.cpus[0].core.cpu.picorv32_core.cpuregs.wdata, Q = \softshell.cpus[0].core.cpu.picorv32_core.cpuregs.regs[16]).
+Adding EN signal on $memory\softshell.cpus[0].core.cpu.picorv32_core.cpuregs.regs[15]$21966 ($dff) from module user_proj_example (D = \softshell.cpus[0].core.cpu.picorv32_core.cpuregs.wdata, Q = \softshell.cpus[0].core.cpu.picorv32_core.cpuregs.regs[15]).
+Adding EN signal on $memory\softshell.cpus[0].core.cpu.picorv32_core.cpuregs.regs[14]$21964 ($dff) from module user_proj_example (D = \softshell.cpus[0].core.cpu.picorv32_core.cpuregs.wdata, Q = \softshell.cpus[0].core.cpu.picorv32_core.cpuregs.regs[14]).
+Adding EN signal on $memory\softshell.cpus[0].core.cpu.picorv32_core.cpuregs.regs[13]$21962 ($dff) from module user_proj_example (D = \softshell.cpus[0].core.cpu.picorv32_core.cpuregs.wdata, Q = \softshell.cpus[0].core.cpu.picorv32_core.cpuregs.regs[13]).
+Adding EN signal on $memory\softshell.cpus[0].core.cpu.picorv32_core.cpuregs.regs[12]$21960 ($dff) from module user_proj_example (D = \softshell.cpus[0].core.cpu.picorv32_core.cpuregs.wdata, Q = \softshell.cpus[0].core.cpu.picorv32_core.cpuregs.regs[12]).
+Adding EN signal on $memory\softshell.cpus[0].core.cpu.picorv32_core.cpuregs.regs[11]$21958 ($dff) from module user_proj_example (D = \softshell.cpus[0].core.cpu.picorv32_core.cpuregs.wdata, Q = \softshell.cpus[0].core.cpu.picorv32_core.cpuregs.regs[11]).
+Adding EN signal on $memory\softshell.cpus[0].core.cpu.picorv32_core.cpuregs.regs[10]$21956 ($dff) from module user_proj_example (D = \softshell.cpus[0].core.cpu.picorv32_core.cpuregs.wdata, Q = \softshell.cpus[0].core.cpu.picorv32_core.cpuregs.regs[10]).
+Adding EN signal on $memory\softshell.cpus[0].core.cpu.picorv32_core.cpuregs.regs[0]$21936 ($dff) from module user_proj_example (D = \softshell.cpus[0].core.cpu.picorv32_core.cpuregs.wdata, Q = \softshell.cpus[0].core.cpu.picorv32_core.cpuregs.regs[0]).
+Setting constant 0-bit at position 0 on $auto$opt_dff.cc:764:run$20725 ($dffe) from module user_proj_example.
+Setting constant 0-bit at position 1 on $auto$opt_dff.cc:764:run$20725 ($dffe) from module user_proj_example.
+Setting constant 0-bit at position 0 on $auto$opt_dff.cc:764:run$20266 ($dffe) from module user_proj_example.
+Setting constant 0-bit at position 1 on $auto$opt_dff.cc:764:run$20266 ($dffe) from module user_proj_example.
+Setting constant 0-bit at position 0 on $auto$opt_dff.cc:764:run$19807 ($dffe) from module user_proj_example.
+Setting constant 0-bit at position 1 on $auto$opt_dff.cc:764:run$19807 ($dffe) from module user_proj_example.
+Setting constant 0-bit at position 3 on $auto$opt_dff.cc:764:run$19658 ($sdffe) from module user_proj_example.
+Adding SRST signal on $auto$opt_dff.cc:764:run$19567 ($dffe) from module user_proj_example (D = \softshell.flash.spimemio.din_data [0], Q = \softshell.flash.spimemio.xfer.obuffer [0], rval = 1'0).
+
+23.20.16. Executing OPT_CLEAN pass (remove unused cells and wires).
+Finding unused cells or wires in module \user_proj_example..
+Removed 2540 unused cells and 2560 unused wires.
+<suppressed ~2541 debug messages>
+
+23.20.17. Executing OPT_EXPR pass (perform const folding).
+Optimizing module user_proj_example.
+<suppressed ~1 debug messages>
+
+23.20.18. Rerunning OPT passes. (Maybe there is more to do..)
+
+23.20.19. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
+Running muxtree optimizer on module \user_proj_example..
+ Creating internal representation of mux trees.
+ Evaluating internal representation of mux trees.
+ Analyzing evaluation results.
+Removed 0 multiplexer ports.
+<suppressed ~383 debug messages>
+
+23.20.20. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
+ Optimizing cells in module \user_proj_example.
+Performed a total of 0 changes.
+
+23.20.21. Executing OPT_MERGE pass (detect identical cells).
+Finding identical cells in module `\user_proj_example'.
+<suppressed ~3 debug messages>
+Removed a total of 1 cells.
+
+23.20.22. Executing OPT_SHARE pass.
+
+23.20.23. Executing OPT_DFF pass (perform DFF optimizations).
+Setting constant 0-bit at position 0 on $auto$opt_dff.cc:764:run$21049 ($sdffe) from module user_proj_example.
+Setting constant 0-bit at position 1 on $auto$opt_dff.cc:764:run$21049 ($sdffe) from module user_proj_example.
+Setting constant 0-bit at position 0 on $auto$opt_dff.cc:764:run$20590 ($sdffe) from module user_proj_example.
+Setting constant 0-bit at position 1 on $auto$opt_dff.cc:764:run$20590 ($sdffe) from module user_proj_example.
+Setting constant 0-bit at position 0 on $auto$opt_dff.cc:764:run$20131 ($sdffe) from module user_proj_example.
+Setting constant 0-bit at position 1 on $auto$opt_dff.cc:764:run$20131 ($sdffe) from module user_proj_example.
+Setting constant 0-bit at position 3 on $auto$opt_dff.cc:764:run$19503 ($sdffe) from module user_proj_example.
+
+23.20.24. Executing OPT_CLEAN pass (remove unused cells and wires).
+Finding unused cells or wires in module \user_proj_example..
+Removed 0 unused cells and 2 unused wires.
+<suppressed ~1 debug messages>
+
+23.20.25. Executing OPT_EXPR pass (perform const folding).
+Optimizing module user_proj_example.
+<suppressed ~39 debug messages>
+
+23.20.26. Rerunning OPT passes. (Maybe there is more to do..)
+
+23.20.27. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
+Running muxtree optimizer on module \user_proj_example..
+ Creating internal representation of mux trees.
+ Evaluating internal representation of mux trees.
+ Analyzing evaluation results.
+Removed 0 multiplexer ports.
+<suppressed ~380 debug messages>
+
+23.20.28. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
+ Optimizing cells in module \user_proj_example.
+ Consolidated identical input bits for $mux cell $flatten\softshell.\arbiter.$ternary$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/verilog-wishbone/rtl/wb_arbiter_4.v:156$1693:
+ Old ports: A=0, B={ \softshell.cpus[2].core.cpu.wbm_adr_o [31:2] 2'00 }, Y=$flatten\softshell.\arbiter.$ternary$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/verilog-wishbone/rtl/wb_arbiter_4.v:156$1693_Y
+ New ports: A=30'000000000000000000000000000000, B=\softshell.cpus[2].core.cpu.wbm_adr_o [31:2], Y=$flatten\softshell.\arbiter.$ternary$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/verilog-wishbone/rtl/wb_arbiter_4.v:156$1693_Y [31:2]
+ New connections: $flatten\softshell.\arbiter.$ternary$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/verilog-wishbone/rtl/wb_arbiter_4.v:156$1693_Y [1:0] = 2'00
+ Optimizing cells in module \user_proj_example.
+ Consolidated identical input bits for $mux cell $flatten\softshell.\arbiter.$ternary$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/verilog-wishbone/rtl/wb_arbiter_4.v:155$1694:
+ Old ports: A=$flatten\softshell.\arbiter.$ternary$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/verilog-wishbone/rtl/wb_arbiter_4.v:156$1693_Y, B={ \softshell.cpus[1].core.cpu.wbm_adr_o [31:2] 2'00 }, Y=$flatten\softshell.\arbiter.$ternary$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/verilog-wishbone/rtl/wb_arbiter_4.v:155$1694_Y
+ New ports: A=$flatten\softshell.\arbiter.$ternary$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/verilog-wishbone/rtl/wb_arbiter_4.v:156$1693_Y [31:2], B=\softshell.cpus[1].core.cpu.wbm_adr_o [31:2], Y=$flatten\softshell.\arbiter.$ternary$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/verilog-wishbone/rtl/wb_arbiter_4.v:155$1694_Y [31:2]
+ New connections: $flatten\softshell.\arbiter.$ternary$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/verilog-wishbone/rtl/wb_arbiter_4.v:155$1694_Y [1:0] = 2'00
+ Optimizing cells in module \user_proj_example.
+ Consolidated identical input bits for $mux cell $flatten\softshell.\arbiter.$ternary$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/verilog-wishbone/rtl/wb_arbiter_4.v:154$1695:
+ Old ports: A=$flatten\softshell.\arbiter.$ternary$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/verilog-wishbone/rtl/wb_arbiter_4.v:155$1694_Y, B={ \softshell.cpus[0].core.cpu.wbm_adr_o [31:2] 2'00 }, Y=$flatten\softshell.\arbiter.$ternary$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/verilog-wishbone/rtl/wb_arbiter_4.v:154$1695_Y
+ New ports: A=$flatten\softshell.\arbiter.$ternary$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/verilog-wishbone/rtl/wb_arbiter_4.v:155$1694_Y [31:2], B=\softshell.cpus[0].core.cpu.wbm_adr_o [31:2], Y=$flatten\softshell.\arbiter.$ternary$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/verilog-wishbone/rtl/wb_arbiter_4.v:154$1695_Y [31:2]
+ New connections: $flatten\softshell.\arbiter.$ternary$/project/openlane/user_proj_example/../../verilog/rtl/softshell/third_party/verilog-wishbone/rtl/wb_arbiter_4.v:154$1695_Y [1:0] = 2'00
+ Optimizing cells in module \user_proj_example.
+Performed a total of 3 changes.
+
+23.20.29. Executing OPT_MERGE pass (detect identical cells).
+Finding identical cells in module `\user_proj_example'.
+<suppressed ~9 debug messages>
+Removed a total of 3 cells.
+
+23.20.30. Executing OPT_SHARE pass.
+
+23.20.31. Executing OPT_DFF pass (perform DFF optimizations).
+Setting constant 0-bit at position 3 on $flatten\softshell.\flash.\spimemio.\xfer.$procdff$16495 ($dff) from module user_proj_example.
+
+23.20.32. Executing OPT_CLEAN pass (remove unused cells and wires).
+Finding unused cells or wires in module \user_proj_example..
+Removed 0 unused cells and 30 unused wires.
+<suppressed ~1 debug messages>
+
+23.20.33. Executing OPT_EXPR pass (perform const folding).
+Optimizing module user_proj_example.
+
+23.20.34. Rerunning OPT passes. (Maybe there is more to do..)
+
+23.20.35. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
+Running muxtree optimizer on module \user_proj_example..
+ Creating internal representation of mux trees.
+ Evaluating internal representation of mux trees.
+ Analyzing evaluation results.
+Removed 0 multiplexer ports.
+<suppressed ~380 debug messages>
+
+23.20.36. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
+ Optimizing cells in module \user_proj_example.
+Performed a total of 0 changes.
+
+23.20.37. Executing OPT_MERGE pass (detect identical cells).
+Finding identical cells in module `\user_proj_example'.
+Removed a total of 0 cells.
+
+23.20.38. Executing OPT_SHARE pass.
+
+23.20.39. Executing OPT_DFF pass (perform DFF optimizations).
+
+23.20.40. Executing OPT_CLEAN pass (remove unused cells and wires).
+Finding unused cells or wires in module \user_proj_example..
+
+23.20.41. Executing OPT_EXPR pass (perform const folding).
+Optimizing module user_proj_example.
+
+23.20.42. Finished OPT passes. (There is nothing left to do.)
+
+23.21. Executing TECHMAP pass (map to technology primitives).
+
+23.21.1. Executing Verilog-2005 frontend: /build/bin/../share/yosys/techmap.v
+Parsing Verilog input from `/build/bin/../share/yosys/techmap.v' to AST representation.
+Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
+Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
+Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
+Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
+Generating RTLIL representation for module `\_90_simplemap_various'.
+Generating RTLIL representation for module `\_90_simplemap_registers'.
+Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
+Generating RTLIL representation for module `\_90_shift_shiftx'.
+Generating RTLIL representation for module `\_90_fa'.
+Generating RTLIL representation for module `\_90_lcu'.
+Generating RTLIL representation for module `\_90_alu'.
+Generating RTLIL representation for module `\_90_macc'.
+Generating RTLIL representation for module `\_90_alumacc'.
+Generating RTLIL representation for module `\$__div_mod_u'.
+Generating RTLIL representation for module `\$__div_mod_trunc'.
+Generating RTLIL representation for module `\_90_div'.
+Generating RTLIL representation for module `\_90_mod'.
+Generating RTLIL representation for module `\$__div_mod_floor'.
+Generating RTLIL representation for module `\_90_divfloor'.
+Generating RTLIL representation for module `\_90_modfloor'.
+Generating RTLIL representation for module `\_90_pow'.
+Generating RTLIL representation for module `\_90_pmux'.
+Generating RTLIL representation for module `\_90_lut'.
+Successfully finished Verilog frontend.
+
+23.21.2. Continuing TECHMAP pass.
+Using extmapper simplemap for cells of type $and.
+Using extmapper simplemap for cells of type $mux.
+Using extmapper simplemap for cells of type $dffe.
+Using extmapper simplemap for cells of type $sdffe.
+Using extmapper simplemap for cells of type $reduce_or.
+Using extmapper simplemap for cells of type $not.
+Using extmapper simplemap for cells of type $ne.
+Using extmapper simplemap for cells of type $reduce_and.
+Using extmapper simplemap for cells of type $reduce_bool.
+Using extmapper simplemap for cells of type $eq.
+Using extmapper simplemap for cells of type $adffe.
+Using extmapper simplemap for cells of type $logic_not.
+Using extmapper simplemap for cells of type $dff.
+Using extmapper simplemap for cells of type $sdff.
+Using extmapper simplemap for cells of type $or.
+Using extmapper simplemap for cells of type $xor.
+Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=32\B_WIDTH=32\Y_WIDTH=32 for cells of type $alu.
+Using extmapper simplemap for cells of type $sdffce.
+Using extmapper simplemap for cells of type $logic_and.
+Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=22\Y_WIDTH=23 for cells of type $alu.
+Using extmapper simplemap for cells of type $adff.
+Using template $paramod\_90_pmux\WIDTH=31\S_WIDTH=3 for cells of type $pmux.
+Using template $paramod\_90_pmux\WIDTH=3\S_WIDTH=3 for cells of type $pmux.
+Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=3\Y_WIDTH=3 for cells of type $alu.
+Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=5\Y_WIDTH=5 for cells of type $alu.
+Using extmapper simplemap for cells of type $logic_or.
+Using template $paramod$constmap:66d421c313e4e958be776b99540ac2de3b59fdbc$paramod$9b74a473ccd678a23e1df4cc12019cbbece20051\_90_shift_ops_shr_shl_sshl_sshr for cells of type $shl.
+Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=32\Y_WIDTH=32 for cells of type $alu.
+Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=32\B_WIDTH=1\Y_WIDTH=32 for cells of type $alu.
+Using template $paramod\_90_pmux\WIDTH=32\S_WIDTH=2 for cells of type $pmux.
+Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=2\B_WIDTH=31\Y_WIDTH=31 for cells of type $alu.
+Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=24\Y_WIDTH=24 for cells of type $alu.
+Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=31\B_WIDTH=31\Y_WIDTH=31 for cells of type $alu.
+Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=30\Y_WIDTH=30 for cells of type $alu.
+Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=4\B_WIDTH=1\Y_WIDTH=4 for cells of type $alu.
+Using template $paramod\_90_alu\A_SIGNED=1\B_SIGNED=1\A_WIDTH=32\B_WIDTH=32\Y_WIDTH=32 for cells of type $alu.
+Using template $paramod$constmap:4621fcf06a436d1e2a4080e2ed9866a7d07a6e07$paramod$887c9fe2c55be14c90171bd2ff359c086a0858d7\_90_shift_ops_shr_shl_sshl_sshr for cells of type $shl.
+Using template $paramod$constmap:87f69c0bea22f84de4bcd0314b57cb19e61b5eb7$paramod$88abf4b792300efa328894e6936be740fdc22f6d\_90_shift_ops_shr_shl_sshl_sshr for cells of type $sshr.
+Using template $paramod\_90_pmux\WIDTH=1\S_WIDTH=2 for cells of type $pmux.
+Using template $paramod\_90_pmux\WIDTH=8\S_WIDTH=3 for cells of type $pmux.
+Using template $paramod\_90_pmux\WIDTH=24\S_WIDTH=2 for cells of type $pmux.
+Using template $paramod\_90_pmux\WIDTH=32\S_WIDTH=4 for cells of type $pmux.
+Using template $paramod\_90_pmux\WIDTH=32\S_WIDTH=3 for cells of type $pmux.
+Using template $paramod\_90_pmux\WIDTH=1\S_WIDTH=3 for cells of type $pmux.
+Using template $paramod\_90_pmux\WIDTH=1\S_WIDTH=5 for cells of type $pmux.
+Using template $paramod\_90_pmux\WIDTH=32\S_WIDTH=6 for cells of type $pmux.
+Using template $paramod\_90_pmux\WIDTH=4\S_WIDTH=4 for cells of type $pmux.
+Using template $paramod\_90_pmux\WIDTH=4\S_WIDTH=2 for cells of type $pmux.
+Using template $paramod\_90_pmux\WIDTH=4\S_WIDTH=3 for cells of type $pmux.
+Using template $paramod\_90_pmux\WIDTH=32\S_WIDTH=5 for cells of type $pmux.
+Using template $paramod\_90_pmux\WIDTH=5\S_WIDTH=3 for cells of type $pmux.
+Using template $paramod\_90_pmux\WIDTH=5\S_WIDTH=4 for cells of type $pmux.
+Using template $paramod\_90_pmux\WIDTH=2\S_WIDTH=2 for cells of type $pmux.
+Using template $paramod\_90_pmux\WIDTH=5\S_WIDTH=2 for cells of type $pmux.
+Using template $paramod\_90_pmux\WIDTH=3\S_WIDTH=4 for cells of type $pmux.
+Using template $paramod\_90_pmux\WIDTH=3\S_WIDTH=2 for cells of type $pmux.
+Using template $paramod\_90_pmux\WIDTH=6\S_WIDTH=4 for cells of type $pmux.
+Using template $paramod\_90_pmux\WIDTH=6\S_WIDTH=2 for cells of type $pmux.
+Using template $paramod\_90_pmux\WIDTH=6\S_WIDTH=3 for cells of type $pmux.
+Running "alumacc" on wrapper $extern:wrap:$neg:A_SIGNED=0:A_WIDTH=32:Y_WIDTH=32:394426c56d1a028ba8fdd5469b163e04011def47.
+Using template $extern:wrap:$neg:A_SIGNED=0:A_WIDTH=32:Y_WIDTH=32:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$neg:A_SIGNED=0:A_WIDTH=32:Y_WIDTH=32:394426c56d1a028ba8fdd5469b163e04011def47.
+Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=2\Y_WIDTH=3 for cells of type $alu.
+Using template $paramod$constmap:98306f291cbeead448f2b1445fc6248d857878d0$paramod$2327a0ba7bfb192984705bf224423f1e02391c1d\_90_shift_ops_shr_shl_sshl_sshr for cells of type $shl.
+Using template $paramod$constmap:4edb66e0d088a61c7edd1b98fbc82bc43943c3a9$paramod$5d172ccbeb3c362c32df416f9b456bae59d0c474\_90_shift_ops_shr_shl_sshl_sshr for cells of type $shl.
+Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=2\B_WIDTH=1\Y_WIDTH=2 for cells of type $alu.
+Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=3\B_WIDTH=1\Y_WIDTH=3 for cells of type $alu.
+Using template $paramod\_90_pmux\WIDTH=8\S_WIDTH=2 for cells of type $pmux.
+Using template $paramod\_90_pmux\WIDTH=7\S_WIDTH=2 for cells of type $pmux.
+Using template $paramod\_90_pmux\WIDTH=8\S_WIDTH=7 for cells of type $pmux.
+Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=4\Y_WIDTH=4 for cells of type $alu.
+Using template $paramod$constmap:0ea6f06af49e4bc4bf4868604ebc0338941df994$paramod$2d95cf61ad19e9896278b268da9e969a13e3cdc2\_90_shift_shiftx for cells of type $shiftx.
+Using template $paramod$constmap:78a20c368e8b333966e5d11dde40dce34e51c121$paramod$0230804b9689e36f62115cd713799e3f644bc5c9\_90_shift_shiftx for cells of type $shiftx.
+Analyzing pattern of constant bits for this cell:
+ Constant input on bit 0 of port A: 1'1
+ Constant input on bit 1 of port A: 1'0
+Creating constmapped module `$paramod$constmap:b0f6d672d8ec96f47bd26361fd90550a8c81341b$paramod$0230804b9689e36f62115cd713799e3f644bc5c9\_90_shift_shiftx'.
+
+23.21.126. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
+Running muxtree optimizer on module $paramod$constmap:b0f6d672d8ec96f47bd26361fd90550a8c81341b$paramod$0230804b9689e36f62115cd713799e3f644bc5c9\_90_shift_shiftx..
+ Creating internal representation of mux trees.
+ Evaluating internal representation of mux trees.
+ Analyzing evaluation results.
+ dead port 2/2 on $mux $procmux$130820.
+ dead port 2/2 on $mux $procmux$130814.
+ dead port 2/2 on $mux $procmux$130808.
+ dead port 2/2 on $mux $procmux$130802.
+ dead port 2/2 on $mux $procmux$130796.
+Removed 5 multiplexer ports.
+<suppressed ~14897 debug messages>
+
+23.21.127. Executing OPT_EXPR pass (perform const folding).
+Optimizing module $paramod$constmap:b0f6d672d8ec96f47bd26361fd90550a8c81341b$paramod$0230804b9689e36f62115cd713799e3f644bc5c9\_90_shift_shiftx.
+<suppressed ~3 debug messages>
+Removed 0 unused cells and 11 unused wires.
+Using template $paramod$constmap:b0f6d672d8ec96f47bd26361fd90550a8c81341b$paramod$0230804b9689e36f62115cd713799e3f644bc5c9\_90_shift_shiftx for cells of type $shiftx.
+Using template $paramod\_90_pmux\WIDTH=5\S_WIDTH=31 for cells of type $pmux.
+Using extmapper simplemap for cells of type $pos.
+Using template $paramod\_90_lcu\WIDTH=3 for cells of type $lcu.
+Using template $paramod\_90_lcu\WIDTH=30 for cells of type $lcu.
+Using template $paramod\_90_lcu\WIDTH=5 for cells of type $lcu.
+Using template $paramod\_90_lcu\WIDTH=32 for cells of type $lcu.
+Using template $paramod\_90_lcu\WIDTH=31 for cells of type $lcu.
+Using template $paramod\_90_lcu\WIDTH=24 for cells of type $lcu.
+Using template $paramod\_90_lcu\WIDTH=23 for cells of type $lcu.
+Using template $paramod\_90_lcu\WIDTH=4 for cells of type $lcu.
+Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=0\B_WIDTH=32\Y_WIDTH=32 for cells of type $alu.
+Using template $paramod\_90_lcu\WIDTH=2 for cells of type $lcu.
+No more expansions possible.
+<suppressed ~11135 debug messages>
+
+23.22. Executing OPT pass (performing simple optimizations).
+
+23.22.1. Executing OPT_EXPR pass (perform const folding).
+Optimizing module user_proj_example.
+<suppressed ~11953 debug messages>
+
+23.22.2. Executing OPT_MERGE pass (detect identical cells).
+Finding identical cells in module `\user_proj_example'.
+<suppressed ~16350 debug messages>
+Removed a total of 5450 cells.
+
+23.22.3. Executing OPT_DFF pass (perform DFF optimizations).
+
+23.22.4. Executing OPT_CLEAN pass (remove unused cells and wires).
+Finding unused cells or wires in module \user_proj_example..
+Removed 8308 unused cells and 15508 unused wires.
+<suppressed ~8318 debug messages>
+
+23.22.5. Finished fast OPT passes.
+
+23.23. Executing ABC pass (technology mapping using ABC).
+
+23.23.1. Extracting gate netlist of module `\user_proj_example' to `<abc-temp-dir>/input.blif'..
+Extracted 58620 gates and 85166 wires to a netlist network with 26543 inputs and 5700 outputs.
+
+23.23.1.1. Executing ABC.
+Running ABC command: <yosys-exe-dir>/yosys-abc -s -f <abc-temp-dir>/abc.script 2>&1
+ABC: ABC command line: "source <abc-temp-dir>/abc.script".
+ABC:
+ABC: + read_blif <abc-temp-dir>/input.blif
+ABC: + read_library <abc-temp-dir>/stdcells.genlib
+ABC: Entered genlib library with 13 gates from file "<abc-temp-dir>/stdcells.genlib".
+ABC: + strash
+ABC: + dretime
+ABC: + map
+ABC: + write_blif <abc-temp-dir>/output.blif
+
+23.23.1.2. Re-integrating ABC results.
+ABC RESULTS: AND cells: 2081
+ABC RESULTS: ANDNOT cells: 9426
+ABC RESULTS: MUX cells: 32798
+ABC RESULTS: NAND cells: 1235
+ABC RESULTS: NOR cells: 1847
+ABC RESULTS: NOT cells: 1638
+ABC RESULTS: OR cells: 5943
+ABC RESULTS: ORNOT cells: 876
+ABC RESULTS: XNOR cells: 455
+ABC RESULTS: XOR cells: 1481
+ABC RESULTS: internal signals: 52923
+ABC RESULTS: input signals: 26543
+ABC RESULTS: output signals: 5700
+Removing temp directory.
+
+23.24. Executing OPT pass (performing simple optimizations).
+
+23.24.1. Executing OPT_EXPR pass (perform const folding).
+Optimizing module user_proj_example.
+<suppressed ~14802 debug messages>
+
+23.24.2. Executing OPT_MERGE pass (detect identical cells).
+Finding identical cells in module `\user_proj_example'.
+<suppressed ~327 debug messages>
+Removed a total of 109 cells.
+
+23.24.3. Executing OPT_DFF pass (perform DFF optimizations).
+
+23.24.4. Executing OPT_CLEAN pass (remove unused cells and wires).
+Finding unused cells or wires in module \user_proj_example..
+Removed 76 unused cells and 44359 unused wires.
+<suppressed ~549 debug messages>
+
+23.24.5. Finished fast OPT passes.
+
+23.25. Executing HIERARCHY pass (managing design hierarchy).
+
+23.25.1. Analyzing design hierarchy..
+Top module: \user_proj_example
+
+23.25.2. Analyzing design hierarchy..
+Top module: \user_proj_example
+Removed 0 unused modules.
+
+23.26. Printing statistics.
+
+=== user_proj_example ===
+
+ Number of wires: 60133
+ Number of wire bits: 97406
+ Number of public wires: 3907
+ Number of public wire bits: 40194
+ Number of memories: 0
+ Number of memory bits: 0
+ Number of processes: 0
+ Number of cells: 84371
+ $_ANDNOT_ 9406
+ $_AND_ 2081
+ $_DFFE_PN_ 28
+ $_DFFE_PP0P_ 502
+ $_DFFE_PP1P_ 15
+ $_DFFE_PP_ 24293
+ $_DFF_N_ 4
+ $_DFF_PP0_ 124
+ $_DFF_PP1_ 3
+ $_DFF_P_ 365
+ $_MUX_ 32785
+ $_NAND_ 1229
+ $_NOR_ 1791
+ $_NOT_ 1562
+ $_ORNOT_ 867
+ $_OR_ 5938
+ $_SDFFCE_PN0P_ 11
+ $_SDFFCE_PP0P_ 5
+ $_SDFFE_PN0P_ 5
+ $_SDFFE_PN1N_ 12
+ $_SDFFE_PP0N_ 9
+ $_SDFFE_PP0P_ 764
+ $_SDFFE_PP1P_ 247
+ $_SDFF_PN0_ 3
+ $_SDFF_PP0_ 380
+ $_SDFF_PP1_ 6
+ $_XNOR_ 455
+ $_XOR_ 1481
+
+23.27. Executing CHECK pass (checking for obvious problems).
+checking module user_proj_example..
+found and reported 0 problems.
+
+24. Executing SHARE pass (SAT-based resource sharing).
+
+25. Executing OPT pass (performing simple optimizations).
+
+25.1. Executing OPT_EXPR pass (perform const folding).
+Optimizing module user_proj_example.
+
+25.2. Executing OPT_MERGE pass (detect identical cells).
+Finding identical cells in module `\user_proj_example'.
+Removed a total of 0 cells.
+
+25.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
+Running muxtree optimizer on module \user_proj_example..
+ Creating internal representation of mux trees.
+ No muxes found in this module.
+Removed 0 multiplexer ports.
+
+25.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
+ Optimizing cells in module \user_proj_example.
+Performed a total of 0 changes.
+
+25.5. Executing OPT_MERGE pass (detect identical cells).
+Finding identical cells in module `\user_proj_example'.
+Removed a total of 0 cells.
+
+25.6. Executing OPT_DFF pass (perform DFF optimizations).
+Adding EN signal on $auto$simplemap.cc:559:simplemap_adffe_sdffe_sdffce$77013 ($_SDFFE_PP0P_) from module user_proj_example (D = $abc$173061$new_n64822_, Q = \softshell.flash.spimemio.xfer.count [0]).
+Adding EN signal on $auto$simplemap.cc:559:simplemap_adffe_sdffe_sdffce$126020 ($_SDFFE_PP0P_) from module user_proj_example (D = $abc$173061$new_n62428_, Q = \softshell.cpus[0].core.cpu.picorv32_core.reg_next_pc [0]).
+Adding EN signal on $auto$simplemap.cc:559:simplemap_adffe_sdffe_sdffce$116415 ($_SDFFE_PP0P_) from module user_proj_example (D = $abc$173061$new_n58371_, Q = \softshell.cpus[1].core.cpu.picorv32_core.reg_next_pc [0]).
+Adding EN signal on $auto$simplemap.cc:559:simplemap_adffe_sdffe_sdffce$108155 ($_SDFFE_PP0P_) from module user_proj_example (D = $abc$173061$new_n58361_, Q = \softshell.cpus[2].core.cpu.picorv32_core.reg_next_pc [0]).
+
+25.7. Executing OPT_CLEAN pass (remove unused cells and wires).
+Finding unused cells or wires in module \user_proj_example..
+Removed 4 unused cells and 7 unused wires.
+<suppressed ~5 debug messages>
+
+25.8. Executing OPT_EXPR pass (perform const folding).
+Optimizing module user_proj_example.
+
+25.9. Rerunning OPT passes. (Maybe there is more to do..)
+
+25.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
+Running muxtree optimizer on module \user_proj_example..
+ Creating internal representation of mux trees.
+ No muxes found in this module.
+Removed 0 multiplexer ports.
+
+25.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
+ Optimizing cells in module \user_proj_example.
+Performed a total of 0 changes.
+
+25.12. Executing OPT_MERGE pass (detect identical cells).
+Finding identical cells in module `\user_proj_example'.
+Removed a total of 0 cells.
+
+25.13. Executing OPT_DFF pass (perform DFF optimizations).
+
+25.14. Executing OPT_CLEAN pass (remove unused cells and wires).
+Finding unused cells or wires in module \user_proj_example..
+
+25.15. Executing OPT_EXPR pass (perform const folding).
+Optimizing module user_proj_example.
+
+25.16. Finished OPT passes. (There is nothing left to do.)
+
+26. Executing OPT_CLEAN pass (remove unused cells and wires).
+Finding unused cells or wires in module \user_proj_example..
+Removed 0 unused cells and 760 unused wires.
+<suppressed ~760 debug messages>
+
+27. Printing statistics.
+
+=== user_proj_example ===
+
+ Number of wires: 59378
+ Number of wire bits: 85625
+ Number of public wires: 3147
+ Number of public wire bits: 28501
+ Number of memories: 0
+ Number of memory bits: 0
+ Number of processes: 0
+ Number of cells: 84375
+ $_ANDNOT_ 9406
+ $_AND_ 2085
+ $_DFFE_PN_ 28
+ $_DFFE_PP0P_ 502
+ $_DFFE_PP1P_ 15
+ $_DFFE_PP_ 24293
+ $_DFF_N_ 4
+ $_DFF_PP0_ 124
+ $_DFF_PP1_ 3
+ $_DFF_P_ 365
+ $_MUX_ 32781
+ $_NAND_ 1229
+ $_NOR_ 1791
+ $_NOT_ 1566
+ $_ORNOT_ 867
+ $_OR_ 5938
+ $_SDFFCE_PN0P_ 11
+ $_SDFFCE_PP0P_ 5
+ $_SDFFE_PN0P_ 5
+ $_SDFFE_PN1N_ 12
+ $_SDFFE_PP0N_ 9
+ $_SDFFE_PP0P_ 764
+ $_SDFFE_PP1P_ 247
+ $_SDFF_PN0_ 3
+ $_SDFF_PP0_ 380
+ $_SDFF_PP1_ 6
+ $_XNOR_ 455
+ $_XOR_ 1481
+
+28. Executing TECHMAP pass (map to technology primitives).
+
+28.1. Executing Verilog-2005 frontend: /mnt/data/workspace/pdk/sky130A/libs.tech/openlane/sky130_fd_sc_hd/tribuff_map.v
+Parsing Verilog input from `/mnt/data/workspace/pdk/sky130A/libs.tech/openlane/sky130_fd_sc_hd/tribuff_map.v' to AST representation.
+Generating RTLIL representation for module `\$_TBUF_'.
+Successfully finished Verilog frontend.
+
+28.2. Continuing TECHMAP pass.
+No more expansions possible.
+<suppressed ~3 debug messages>
+
+29. Executing SIMPLEMAP pass (map simple cells to gate primitives).
+
+30. Executing DFFLIBMAP pass (mapping DFF cells to sequential cells from liberty file).
+ cell sky130_fd_sc_hd__dfxtp_4 (noninv, pins=3, area=23.77) is a direct match for cell type $_DFF_P_.
+ cell sky130_fd_sc_hd__dfrtp_4 (noninv, pins=4, area=28.78) is a direct match for cell type $_DFF_PN0_.
+ cell sky130_fd_sc_hd__dfstp_4 (noninv, pins=4, area=30.03) is a direct match for cell type $_DFF_PN1_.
+ cell sky130_fd_sc_hd__dfbbn_2 (noninv, pins=6, area=35.03) is a direct match for cell type $_DFFSR_NNN_.
+ final dff cell mappings:
+ unmapped dff cell: $_DFF_N_
+ \sky130_fd_sc_hd__dfxtp_4 _DFF_P_ (.CLK( C), .D( D), .Q( Q));
+ unmapped dff cell: $_DFF_NN0_
+ unmapped dff cell: $_DFF_NN1_
+ unmapped dff cell: $_DFF_NP0_
+ unmapped dff cell: $_DFF_NP1_
+ \sky130_fd_sc_hd__dfrtp_4 _DFF_PN0_ (.CLK( C), .D( D), .Q( Q), .RESET_B( R));
+ \sky130_fd_sc_hd__dfstp_4 _DFF_PN1_ (.CLK( C), .D( D), .Q( Q), .SET_B( R));
+ unmapped dff cell: $_DFF_PP0_
+ unmapped dff cell: $_DFF_PP1_
+ \sky130_fd_sc_hd__dfbbn_2 _DFFSR_NNN_ (.CLK_N( C), .D( D), .Q( Q), .Q_N(~Q), .RESET_B( R), .SET_B( S));
+ unmapped dff cell: $_DFFSR_NNP_
+ unmapped dff cell: $_DFFSR_NPN_
+ unmapped dff cell: $_DFFSR_NPP_
+ unmapped dff cell: $_DFFSR_PNN_
+ unmapped dff cell: $_DFFSR_PNP_
+ unmapped dff cell: $_DFFSR_PPN_
+ unmapped dff cell: $_DFFSR_PPP_
+
+30.1. Executing DFFLEGALIZE pass (convert FFs to types supported by the target).
+Mapping DFF cells in module `\user_proj_example':
+ mapped 626 $_DFF_PN0_ cells to \sky130_fd_sc_hd__dfrtp_4 cells.
+ mapped 18 $_DFF_PN1_ cells to \sky130_fd_sc_hd__dfstp_4 cells.
+ mapped 26132 $_DFF_P_ cells to \sky130_fd_sc_hd__dfxtp_4 cells.
+
+31. Printing statistics.
+
+=== user_proj_example ===
+
+ Number of wires: 87359
+ Number of wire bits: 113606
+ Number of public wires: 3147
+ Number of public wire bits: 28501
+ Number of memories: 0
+ Number of memory bits: 0
+ Number of processes: 0
+ Number of cells: 112356
+ $_ANDNOT_ 9406
+ $_AND_ 2085
+ $_MUX_ 60114
+ $_NAND_ 1229
+ $_NOR_ 1791
+ $_NOT_ 2214
+ $_ORNOT_ 867
+ $_OR_ 5938
+ $_XNOR_ 455
+ $_XOR_ 1481
+ sky130_fd_sc_hd__dfrtp_4 626
+ sky130_fd_sc_hd__dfstp_4 18
+ sky130_fd_sc_hd__dfxtp_4 26132
+
+32. Executing ABC pass (technology mapping using ABC).
+
+32.1. Extracting gate netlist of module `\user_proj_example' to `/tmp/yosys-abc-H4u2I0/input.blif'..
+Extracted 85580 gates and 112447 wires to a netlist network with 26865 inputs and 27478 outputs.
+
+32.1.1. Executing ABC.
+Running ABC command: /build/bin/yosys-abc -s -f /tmp/yosys-abc-H4u2I0/abc.script 2>&1
+ABC: ABC command line: "source /tmp/yosys-abc-H4u2I0/abc.script".
+ABC:
+ABC: + read_blif /tmp/yosys-abc-H4u2I0/input.blif
+ABC: + read_lib -w /project/openlane/user_proj_example/runs/16-12_10-43/tmp/trimmed.lib
+ABC: Parsing finished successfully. Parsing time = 0.02 sec
+ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfbbn_2".
+ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfrbp_2".
+ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfrtp_4".
+ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfstp_4".
+ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfxbp_2".
+ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfxtp_4".
+ABC: Library "sky130_fd_sc_hd__tt_025C_1v80" from "/project/openlane/user_proj_example/runs/16-12_10-43/tmp/trimmed.lib" has 43 cells (6 skipped: 6 seq; 0 tri-state; 0 no func; 0 dont_use). Time = 0.03 sec
+ABC: Memory = 1.82 MB. Time = 0.03 sec
+ABC: + read_constr -v /project/openlane/user_proj_example/runs/16-12_10-43/tmp/synthesis/yosys.sdc
+ABC: Setting driving cell to be "sky130_fd_sc_hd__inv_8".
+ABC: Setting output load to be 17.650000.
+ABC: + read_constr /project/openlane/user_proj_example/runs/16-12_10-43/tmp/synthesis/yosys.sdc
+ABC: + fx
+ABC: Abc_NtkFastExtract: Nodes have duplicated fanins. FX is not performed.
+ABC: + mfs
+ABC: + strash
+ABC: + refactor
+ABC: + balance
+ABC: + rewrite
+ABC: + refactor
+ABC: + balance
+ABC: + rewrite
+ABC: + rewrite -z
+ABC: + balance
+ABC: + refactor -z
+ABC: + rewrite -z
+ABC: + balance
+ABC: + retime -D -D 20000 -M 5
+ABC: + scleanup
+ABC: Error: The network is combinational.
+ABC: + amap -m -Q 0.1 -F 20 -A 20 -C 5000
+ABC: + retime -D -D 20000
+ABC: + buffer -N 5 -S 2000.0
+ABC: Node 77089 has dup fanin 1252.
+ABC: Node 77089 has dup fanin 26285.
+ABC: Node 77089 has dup fanin 1252.
+ABC: Node 77089 has dup fanin 26285.
+ABC: Node 77105 has dup fanin 54347.
+ABC: Node 77105 has dup fanin 26289.
+ABC: Node 77105 has dup fanin 54347.
+ABC: Node 77105 has dup fanin 26289.
+ABC: Node 77289 has dup fanin 56493.
+ABC: Node 77289 has dup fanin 77257.
+ABC: Node 77289 has dup fanin 56493.
+ABC: Node 77289 has dup fanin 77257.
+ABC: Node 77319 has dup fanin 77316.
+ABC: Node 77319 has dup fanin 77318.
+ABC: Node 77319 has dup fanin 77316.
+ABC: Node 77319 has dup fanin 77318.
+ABC: Node 77335 has dup fanin 77332.
+ABC: Node 77335 has dup fanin 77334.
+ABC: Node 77335 has dup fanin 77332.
+ABC: Node 77335 has dup fanin 77334.
+ABC: Node 77402 has dup fanin 22953.
+ABC: Node 77402 has dup fanin 77401.
+ABC: Node 77402 has dup fanin 22953.
+ABC: Node 77402 has dup fanin 77401.
+ABC: Node 77404 has dup fanin 22954.
+ABC: Node 77404 has dup fanin 77403.
+ABC: Node 77404 has dup fanin 22954.
+ABC: Node 77404 has dup fanin 77403.
+ABC: Node 77424 has dup fanin 77422.
+ABC: Node 77424 has dup fanin 77423.
+ABC: Node 77424 has dup fanin 77422.
+ABC: Node 77424 has dup fanin 77423.
+ABC: Node 77432 has dup fanin 77429.
+ABC: Node 77432 has dup fanin 77431.
+ABC: Node 77432 has dup fanin 77429.
+ABC: Node 77432 has dup fanin 77431.
+ABC: Node 77462 has dup fanin 77270.
+ABC: Node 77462 has dup fanin 77270.
+ABC: Node 77497 has dup fanin 2638.
+ABC: Node 77497 has dup fanin 77295.
+ABC: Node 77497 has dup fanin 2638.
+ABC: Node 77497 has dup fanin 77295.
+ABC: Node 77934 has dup fanin 77933.
+ABC: Node 77934 has dup fanin 77933.
+ABC: Node 77935 has dup fanin 77933.
+ABC: Node 77935 has dup fanin 77933.
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+ABC: + upsize -D 20000
+ABC: Current delay (8219.26 ps) does not exceed the target delay (20000.00 ps). Upsizing is not performed.
+ABC: + dnsize -D 20000
+ABC: + stime -p
+ABC: WireLoad = "none" Gates = 160412 ( 38.5 %) Cap = 9.1 ff ( 0.0 %) Area = 1573948.25 (100.0 %) Delay = 8237.40 ps ( 0.3 %)
+ABC: Path 0 -- 1345 : 0 3 pi A = 0.00 Df = 17.1 -11.3 ps S = 31.6 ps Cin = 0.0 ff Cout = 14.2 ff Cmax = 0.0 ff G = 0
+ABC: Path 1 -- 71048 : 1 5 sky130_fd_sc_hd__inv_2 A = 3.75 Df = 87.9 -21.3 ps S = 98.1 ps Cin = 4.5 ff Cout = 20.2 ff Cmax = 331.4 ff G = 431
+ABC: Path 2 -- 127930 : 2 3 sky130_fd_sc_hd__and2_4 A = 8.76 Df = 251.8 -42.1 ps S = 56.8 ps Cin = 2.4 ff Cout = 12.3 ff Cmax = 539.3 ff G = 487
+ABC: Path 3 -- 127931 : 2 2 sky130_fd_sc_hd__or2_4 A = 8.76 Df = 435.9 -71.7 ps S = 50.3 ps Cin = 2.4 ff Cout = 7.2 ff Cmax = 514.5 ff G = 285
+ABC: Path 4 -- 127932 : 2 3 sky130_fd_sc_hd__or2_4 A = 8.76 Df = 681.4 -194.6 ps S = 60.3 ps Cin = 2.4 ff Cout = 14.4 ff Cmax = 514.5 ff G = 572
+ABC: Path 5 -- 127933 : 2 3 sky130_fd_sc_hd__or2_4 A = 8.76 Df = 930.6 -314.0 ps S = 60.1 ps Cin = 2.4 ff Cout = 14.4 ff Cmax = 514.5 ff G = 572
+ABC: Path 6 -- 127934 : 2 3 sky130_fd_sc_hd__or2_4 A = 8.76 Df =1179.7 -433.4 ps S = 60.1 ps Cin = 2.4 ff Cout = 14.4 ff Cmax = 514.5 ff G = 572
+ABC: Path 7 -- 127935 : 2 3 sky130_fd_sc_hd__or2_4 A = 8.76 Df =1428.8 -552.7 ps S = 60.1 ps Cin = 2.4 ff Cout = 14.4 ff Cmax = 514.5 ff G = 572
+ABC: Path 8 -- 127936 : 2 3 sky130_fd_sc_hd__or2_4 A = 8.76 Df =1678.0 -672.1 ps S = 60.2 ps Cin = 2.4 ff Cout = 14.4 ff Cmax = 514.5 ff G = 572
+ABC: Path 9 -- 127937 : 2 3 sky130_fd_sc_hd__or2_4 A = 8.76 Df =1927.1 -791.5 ps S = 60.0 ps Cin = 2.4 ff Cout = 14.4 ff Cmax = 514.5 ff G = 572
+ABC: Path 10 -- 127938 : 2 3 sky130_fd_sc_hd__or2_4 A = 8.76 Df =2176.2 -910.8 ps S = 60.0 ps Cin = 2.4 ff Cout = 14.4 ff Cmax = 514.5 ff G = 572
+ABC: Path 11 -- 127939 : 2 3 sky130_fd_sc_hd__or2_4 A = 8.76 Df =2425.3-1030.1 ps S = 60.3 ps Cin = 2.4 ff Cout = 14.4 ff Cmax = 514.5 ff G = 572
+ABC: Path 12 -- 127940 : 2 3 sky130_fd_sc_hd__or2_4 A = 8.76 Df =2674.6-1149.5 ps S = 60.2 ps Cin = 2.4 ff Cout = 14.4 ff Cmax = 514.5 ff G = 572
+ABC: Path 13 -- 127941 : 2 3 sky130_fd_sc_hd__or2_4 A = 8.76 Df =2923.7-1268.9 ps S = 60.3 ps Cin = 2.4 ff Cout = 14.4 ff Cmax = 514.5 ff G = 572
+ABC: Path 14 -- 127942 : 2 3 sky130_fd_sc_hd__or2_4 A = 8.76 Df =3172.9-1388.4 ps S = 60.2 ps Cin = 2.4 ff Cout = 14.4 ff Cmax = 514.5 ff G = 572
+ABC: Path 15 -- 127943 : 2 3 sky130_fd_sc_hd__or2_4 A = 8.76 Df =3422.1-1507.7 ps S = 60.3 ps Cin = 2.4 ff Cout = 14.4 ff Cmax = 514.5 ff G = 572
+ABC: Path 16 -- 127944 : 2 3 sky130_fd_sc_hd__or2_4 A = 8.76 Df =3671.3-1627.2 ps S = 60.2 ps Cin = 2.4 ff Cout = 14.4 ff Cmax = 514.5 ff G = 572
+ABC: Path 17 -- 127945 : 2 3 sky130_fd_sc_hd__or2_4 A = 8.76 Df =3920.5-1746.5 ps S = 60.2 ps Cin = 2.4 ff Cout = 14.4 ff Cmax = 514.5 ff G = 572
+ABC: Path 18 -- 127946 : 2 3 sky130_fd_sc_hd__or2_4 A = 8.76 Df =4169.6-1865.9 ps S = 60.2 ps Cin = 2.4 ff Cout = 14.4 ff Cmax = 514.5 ff G = 572
+ABC: Path 19 -- 127947 : 2 3 sky130_fd_sc_hd__or2_4 A = 8.76 Df =4418.8-1985.3 ps S = 60.1 ps Cin = 2.4 ff Cout = 14.4 ff Cmax = 514.5 ff G = 572
+ABC: Path 20 -- 127948 : 2 3 sky130_fd_sc_hd__or2_4 A = 8.76 Df =4667.9-2104.6 ps S = 60.2 ps Cin = 2.4 ff Cout = 14.4 ff Cmax = 514.5 ff G = 572
+ABC: Path 21 -- 127949 : 2 3 sky130_fd_sc_hd__or2_4 A = 8.76 Df =4917.1-2224.0 ps S = 60.1 ps Cin = 2.4 ff Cout = 14.4 ff Cmax = 514.5 ff G = 572
+ABC: Path 22 -- 127950 : 2 4 sky130_fd_sc_hd__or2_4 A = 8.76 Df =5171.7-2343.0 ps S = 65.7 ps Cin = 2.4 ff Cout = 17.0 ff Cmax = 514.5 ff G = 674
+ABC: Path 23 -- 127951 : 4 2 sky130_fd_sc_hd__or4_4 A = 11.26 Df =5691.5-2736.3 ps S = 89.3 ps Cin = 2.4 ff Cout = 7.6 ff Cmax = 534.7 ff G = 299
+ABC: Path 24 -- 127952 : 2 2 sky130_fd_sc_hd__or2_4 A = 8.76 Df =5936.4-2874.9 ps S = 50.0 ps Cin = 2.4 ff Cout = 7.2 ff Cmax = 514.5 ff G = 285
+ABC: Path 25 -- 127953 : 2 3 sky130_fd_sc_hd__or2_4 A = 8.76 Df =6181.8-2997.7 ps S = 60.1 ps Cin = 2.4 ff Cout = 14.4 ff Cmax = 514.5 ff G = 572
+ABC: Path 26 -- 127954 : 2 3 sky130_fd_sc_hd__or2_4 A = 8.76 Df =6430.9-3117.1 ps S = 60.2 ps Cin = 2.4 ff Cout = 14.4 ff Cmax = 514.5 ff G = 572
+ABC: Path 27 -- 127955 : 2 3 sky130_fd_sc_hd__or2_4 A = 8.76 Df =6680.1-3236.5 ps S = 60.1 ps Cin = 2.4 ff Cout = 14.4 ff Cmax = 514.5 ff G = 572
+ABC: Path 28 -- 127956 : 2 3 sky130_fd_sc_hd__or2_4 A = 8.76 Df =6929.2-3355.8 ps S = 60.1 ps Cin = 2.4 ff Cout = 14.4 ff Cmax = 514.5 ff G = 572
+ABC: Path 29 -- 127957 : 2 3 sky130_fd_sc_hd__or2_4 A = 8.76 Df =7183.9-3474.7 ps S = 65.9 ps Cin = 2.4 ff Cout = 17.0 ff Cmax = 514.5 ff G = 675
+ABC: Path 30 -- 127961 : 3 1 sky130_fd_sc_hd__o21a_4 A = 15.01 Df =7451.4 -74.4 ps S = 34.0 ps Cin = 4.6 ff Cout = 4.8 ff Cmax = 510.0 ff G = 96
+ABC: Path 31 -- 127962 : 4 1 sky130_fd_sc_hd__a211o_4 A = 17.52 Df =7631.6 -98.7 ps S = 49.1 ps Cin = 4.6 ff Cout = 4.6 ff Cmax = 559.4 ff G = 96
+ABC: Path 32 -- 127963 : 1 3 sky130_fd_sc_hd__inv_2 A = 3.75 Df =7682.4 -122.0 ps S = 34.0 ps Cin = 4.5 ff Cout = 5.4 ff Cmax = 331.4 ff G = 116
+ABC: Path 33 -- 127964 : 1 5 sky130_fd_sc_hd__buf_2 A = 5.00 Df =7804.0 -118.8 ps S = 70.4 ps Cin = 1.7 ff Cout = 12.4 ff Cmax = 315.9 ff G = 683
+ABC: Path 34 -- 184388 : 1 5 sky130_fd_sc_hd__buf_2 A = 5.00 Df =7983.5 -139.2 ps S = 132.7 ps Cin = 1.7 ff Cout = 25.7 ff Cmax = 315.9 ff G = 1418
+ABC: Path 35 -- 184393 : 4 1 sky130_fd_sc_hd__a2bb2o_4 A = 20.02 Df =8237.4 -145.7 ps S = 70.0 ps Cin = 4.6 ff Cout = 17.6 ff Cmax = 502.6 ff G = 382
+ABC: Start-point = pi1344 (\softshell.cpus[2].core.cpu.picorv32_core.reg_pc [1]). End-point = po21733 ($auto$rtlil.cc:2290:MuxGate$241270).
+ABC: + print_stats -m
+ABC: netlist : i/o =26865/27478 lat = 0 nd =160412 edge = 354446 area =1573739.00 delay =44.00 lev = 44
+ABC: + write_blif /tmp/yosys-abc-H4u2I0/output.blif
+
+32.1.2. Re-integrating ABC results.
+ABC RESULTS: sky130_fd_sc_hd__a2111o_4 cells: 35
+ABC RESULTS: sky130_fd_sc_hd__a211o_4 cells: 1593
+ABC RESULTS: sky130_fd_sc_hd__a21bo_4 cells: 68
+ABC RESULTS: sky130_fd_sc_hd__a21o_4 cells: 203
+ABC RESULTS: sky130_fd_sc_hd__a21oi_4 cells: 173
+ABC RESULTS: sky130_fd_sc_hd__a22oi_4 cells: 163
+ABC RESULTS: sky130_fd_sc_hd__a2bb2o_4 cells: 24546
+ABC RESULTS: sky130_fd_sc_hd__a32o_4 cells: 1198
+ABC RESULTS: sky130_fd_sc_hd__a41o_4 cells: 2
+ABC RESULTS: sky130_fd_sc_hd__and2_4 cells: 2003
+ABC RESULTS: sky130_fd_sc_hd__and3_4 cells: 18762
+ABC RESULTS: sky130_fd_sc_hd__and4_4 cells: 265
+ABC RESULTS: sky130_fd_sc_hd__buf_2 cells: 36020
+ABC RESULTS: sky130_fd_sc_hd__inv_2 cells: 25679
+ABC RESULTS: sky130_fd_sc_hd__nand2_4 cells: 558
+ABC RESULTS: sky130_fd_sc_hd__nor2_4 cells: 3469
+ABC RESULTS: sky130_fd_sc_hd__o21a_4 cells: 1178
+ABC RESULTS: sky130_fd_sc_hd__o21ai_4 cells: 305
+ABC RESULTS: sky130_fd_sc_hd__o22a_4 cells: 2992
+ABC RESULTS: sky130_fd_sc_hd__o32a_4 cells: 231
+ABC RESULTS: sky130_fd_sc_hd__o41a_4 cells: 6
+ABC RESULTS: sky130_fd_sc_hd__or2_4 cells: 30981
+ABC RESULTS: sky130_fd_sc_hd__or3_4 cells: 8866
+ABC RESULTS: sky130_fd_sc_hd__or4_4 cells: 1116
+ABC RESULTS: internal signals: 58104
+ABC RESULTS: input signals: 26865
+ABC RESULTS: output signals: 27478
+Removing temp directory.
+
+33. Executing SETUNDEF pass (replace undef values with defined constants).
+
+34. Executing HILOMAP pass (mapping to constant drivers).
+
+35. Executing SPLITNETS pass (splitting up multi-bit signals).
+
+36. Executing OPT_CLEAN pass (remove unused cells and wires).
+Finding unused cells or wires in module \user_proj_example..
+Removed 266 unused cells and 113530 unused wires.
+<suppressed ~1315 debug messages>
+
+37. Executing INSBUF pass (insert buffer cells for connected wires).
+Added user_proj_example.$auto$insbuf.cc:79:execute$447932: \io_out [6] -> \la_data_out [0]
+Added user_proj_example.$auto$insbuf.cc:79:execute$447933: \io_out [7] -> \la_data_out [1]
+Added user_proj_example.$auto$insbuf.cc:79:execute$447934: \io_out [8] -> \la_data_out [2]
+Added user_proj_example.$auto$insbuf.cc:79:execute$447935: \io_out [9] -> \la_data_out [3]
+Added user_proj_example.$auto$insbuf.cc:79:execute$447936: \io_out [10] -> \la_data_out [4]
+Added user_proj_example.$auto$insbuf.cc:79:execute$447937: \io_out [11] -> \la_data_out [5]
+Added user_proj_example.$auto$insbuf.cc:79:execute$447938: \io_out [12] -> \la_data_out [6]
+Added user_proj_example.$auto$insbuf.cc:79:execute$447939: \io_out [13] -> \la_data_out [7]
+Added user_proj_example.$auto$insbuf.cc:79:execute$447940: \io_out [14] -> \la_data_out [8]
+Added user_proj_example.$auto$insbuf.cc:79:execute$447941: \io_out [15] -> \la_data_out [9]
+Added user_proj_example.$auto$insbuf.cc:79:execute$447942: \io_out [16] -> \la_data_out [10]
+Added user_proj_example.$auto$insbuf.cc:79:execute$447943: \io_out [17] -> \la_data_out [11]
+Added user_proj_example.$auto$insbuf.cc:79:execute$447944: \io_out [18] -> \la_data_out [12]
+Added user_proj_example.$auto$insbuf.cc:79:execute$447945: \io_out [19] -> \la_data_out [13]
+Added user_proj_example.$auto$insbuf.cc:79:execute$447946: \io_out [20] -> \la_data_out [14]
+Added user_proj_example.$auto$insbuf.cc:79:execute$447947: \io_out [21] -> \la_data_out [15]
+Added user_proj_example.$auto$insbuf.cc:79:execute$447948: \io_out [22] -> \la_data_out [16]
+Added user_proj_example.$auto$insbuf.cc:79:execute$447949: \io_out [23] -> \la_data_out [17]
+Added user_proj_example.$auto$insbuf.cc:79:execute$447950: \io_out [24] -> \la_data_out [18]
+Added user_proj_example.$auto$insbuf.cc:79:execute$447951: \io_out [25] -> \la_data_out [19]
+Added user_proj_example.$auto$insbuf.cc:79:execute$447952: \io_out [26] -> \la_data_out [20]
+Added user_proj_example.$auto$insbuf.cc:79:execute$447953: \io_out [27] -> \la_data_out [21]
+Added user_proj_example.$auto$insbuf.cc:79:execute$447954: \io_out [28] -> \la_data_out [22]
+Added user_proj_example.$auto$insbuf.cc:79:execute$447955: \io_out [29] -> \la_data_out [23]
+Added user_proj_example.$auto$insbuf.cc:79:execute$447956: \io_out [30] -> \la_data_out [24]
+Added user_proj_example.$auto$insbuf.cc:79:execute$447957: \io_out [31] -> \la_data_out [25]
+Added user_proj_example.$auto$insbuf.cc:79:execute$447958: \io_out [32] -> \la_data_out [26]
+Added user_proj_example.$auto$insbuf.cc:79:execute$447959: \io_out [33] -> \la_data_out [27]
+Added user_proj_example.$auto$insbuf.cc:79:execute$447960: \io_out [34] -> \la_data_out [28]
+Added user_proj_example.$auto$insbuf.cc:79:execute$447961: \io_out [35] -> \la_data_out [29]
+Added user_proj_example.$auto$insbuf.cc:79:execute$447962: \io_out [36] -> \la_data_out [30]
+Added user_proj_example.$auto$insbuf.cc:79:execute$447963: \io_out [37] -> \la_data_out [31]
+Added user_proj_example.$auto$insbuf.cc:79:execute$447964: \io_oeb [6] -> \la_data_out [32]
+Added user_proj_example.$auto$insbuf.cc:79:execute$447965: \io_oeb [7] -> \la_data_out [33]
+Added user_proj_example.$auto$insbuf.cc:79:execute$447966: \io_oeb [8] -> \la_data_out [34]
+Added user_proj_example.$auto$insbuf.cc:79:execute$447967: \io_oeb [9] -> \la_data_out [35]
+Added user_proj_example.$auto$insbuf.cc:79:execute$447968: \io_oeb [10] -> \la_data_out [36]
+Added user_proj_example.$auto$insbuf.cc:79:execute$447969: \io_oeb [11] -> \la_data_out [37]
+Added user_proj_example.$auto$insbuf.cc:79:execute$447970: \io_oeb [12] -> \la_data_out [38]
+Added user_proj_example.$auto$insbuf.cc:79:execute$447971: \io_oeb [13] -> \la_data_out [39]
+Added user_proj_example.$auto$insbuf.cc:79:execute$447972: \io_oeb [14] -> \la_data_out [40]
+Added user_proj_example.$auto$insbuf.cc:79:execute$447973: \io_oeb [15] -> \la_data_out [41]
+Added user_proj_example.$auto$insbuf.cc:79:execute$447974: \io_oeb [16] -> \la_data_out [42]
+Added user_proj_example.$auto$insbuf.cc:79:execute$447975: \io_oeb [17] -> \la_data_out [43]
+Added user_proj_example.$auto$insbuf.cc:79:execute$447976: \io_oeb [18] -> \la_data_out [44]
+Added user_proj_example.$auto$insbuf.cc:79:execute$447977: \io_oeb [19] -> \la_data_out [45]
+Added user_proj_example.$auto$insbuf.cc:79:execute$447978: \io_oeb [20] -> \la_data_out [46]
+Added user_proj_example.$auto$insbuf.cc:79:execute$447979: \io_oeb [21] -> \la_data_out [47]
+Added user_proj_example.$auto$insbuf.cc:79:execute$447980: \io_oeb [22] -> \la_data_out [48]
+Added user_proj_example.$auto$insbuf.cc:79:execute$447981: \io_oeb [23] -> \la_data_out [49]
+Added user_proj_example.$auto$insbuf.cc:79:execute$447982: \io_oeb [24] -> \la_data_out [50]
+Added user_proj_example.$auto$insbuf.cc:79:execute$447983: \io_oeb [25] -> \la_data_out [51]
+Added user_proj_example.$auto$insbuf.cc:79:execute$447984: \io_oeb [26] -> \la_data_out [52]
+Added user_proj_example.$auto$insbuf.cc:79:execute$447985: \io_oeb [27] -> \la_data_out [53]
+Added user_proj_example.$auto$insbuf.cc:79:execute$447986: \io_oeb [28] -> \la_data_out [54]
+Added user_proj_example.$auto$insbuf.cc:79:execute$447987: \io_oeb [29] -> \la_data_out [55]
+Added user_proj_example.$auto$insbuf.cc:79:execute$447988: \io_oeb [30] -> \la_data_out [56]
+Added user_proj_example.$auto$insbuf.cc:79:execute$447989: \io_oeb [31] -> \la_data_out [57]
+Added user_proj_example.$auto$insbuf.cc:79:execute$447990: \io_oeb [32] -> \la_data_out [58]
+Added user_proj_example.$auto$insbuf.cc:79:execute$447991: \io_oeb [33] -> \la_data_out [59]
+Added user_proj_example.$auto$insbuf.cc:79:execute$447992: \io_oeb [34] -> \la_data_out [60]
+Added user_proj_example.$auto$insbuf.cc:79:execute$447993: \io_oeb [35] -> \la_data_out [61]
+Added user_proj_example.$auto$insbuf.cc:79:execute$447994: \io_oeb [36] -> \la_data_out [62]
+Added user_proj_example.$auto$insbuf.cc:79:execute$447995: \io_oeb [37] -> \la_data_out [63]
+
+38. Executing CHECK pass (checking for obvious problems).
+checking module user_proj_example..
+Warning: Wire user_proj_example.\wbs_dat_o [31] is used but has no driver.
+Warning: Wire user_proj_example.\wbs_dat_o [30] is used but has no driver.
+Warning: Wire user_proj_example.\wbs_dat_o [29] is used but has no driver.
+Warning: Wire user_proj_example.\wbs_dat_o [28] is used but has no driver.
+Warning: Wire user_proj_example.\wbs_dat_o [27] is used but has no driver.
+Warning: Wire user_proj_example.\wbs_dat_o [26] is used but has no driver.
+Warning: Wire user_proj_example.\wbs_dat_o [25] is used but has no driver.
+Warning: Wire user_proj_example.\wbs_dat_o [24] is used but has no driver.
+Warning: Wire user_proj_example.\wbs_dat_o [23] is used but has no driver.
+Warning: Wire user_proj_example.\wbs_dat_o [22] is used but has no driver.
+Warning: Wire user_proj_example.\wbs_dat_o [21] is used but has no driver.
+Warning: Wire user_proj_example.\wbs_dat_o [20] is used but has no driver.
+Warning: Wire user_proj_example.\wbs_dat_o [19] is used but has no driver.
+Warning: Wire user_proj_example.\wbs_dat_o [18] is used but has no driver.
+Warning: Wire user_proj_example.\wbs_dat_o [17] is used but has no driver.
+Warning: Wire user_proj_example.\wbs_dat_o [16] is used but has no driver.
+Warning: Wire user_proj_example.\wbs_dat_o [15] is used but has no driver.
+Warning: Wire user_proj_example.\wbs_dat_o [14] is used but has no driver.
+Warning: Wire user_proj_example.\wbs_dat_o [13] is used but has no driver.
+Warning: Wire user_proj_example.\wbs_dat_o [12] is used but has no driver.
+Warning: Wire user_proj_example.\wbs_dat_o [11] is used but has no driver.
+Warning: Wire user_proj_example.\wbs_dat_o [10] is used but has no driver.
+Warning: Wire user_proj_example.\wbs_dat_o [9] is used but has no driver.
+Warning: Wire user_proj_example.\wbs_dat_o [8] is used but has no driver.
+Warning: Wire user_proj_example.\wbs_dat_o [7] is used but has no driver.
+Warning: Wire user_proj_example.\wbs_dat_o [6] is used but has no driver.
+Warning: Wire user_proj_example.\wbs_dat_o [5] is used but has no driver.
+Warning: Wire user_proj_example.\wbs_dat_o [4] is used but has no driver.
+Warning: Wire user_proj_example.\wbs_dat_o [3] is used but has no driver.
+Warning: Wire user_proj_example.\wbs_dat_o [2] is used but has no driver.
+Warning: Wire user_proj_example.\wbs_dat_o [1] is used but has no driver.
+Warning: Wire user_proj_example.\wbs_dat_o [0] is used but has no driver.
+Warning: Wire user_proj_example.\wbs_ack_o is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [127] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [126] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [125] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [124] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [123] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [122] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [121] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [120] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [119] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [118] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [117] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [116] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [115] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [114] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [113] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [112] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [111] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [110] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [109] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [108] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [107] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [106] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [105] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [104] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [103] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [102] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [101] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [100] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [99] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [98] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [97] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [96] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [95] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [94] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [93] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [92] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [91] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [90] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [89] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [88] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [87] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [86] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [85] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [84] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [83] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [82] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [81] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [80] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [79] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [78] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [77] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [76] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [75] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [74] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [73] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [72] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [71] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [70] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [69] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [68] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [67] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [66] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [65] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [64] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [63] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [62] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [61] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [60] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [59] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [58] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [57] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [56] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [55] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [54] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [53] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [52] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [51] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [50] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [49] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [48] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [47] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [46] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [45] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [44] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [43] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [42] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [41] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [40] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [39] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [38] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [37] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [36] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [35] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [34] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [33] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [32] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [31] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [30] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [29] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [28] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [27] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [26] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [25] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [24] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [23] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [22] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [21] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [20] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [19] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [18] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [17] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [16] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [15] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [14] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [13] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [12] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [11] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [10] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [9] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [8] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [7] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [6] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [5] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [4] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [3] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [2] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [1] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [0] is used but has no driver.
+Warning: Wire user_proj_example.\io_out [37] is used but has no driver.
+Warning: Wire user_proj_example.\io_out [36] is used but has no driver.
+Warning: Wire user_proj_example.\io_out [35] is used but has no driver.
+Warning: Wire user_proj_example.\io_out [34] is used but has no driver.
+Warning: Wire user_proj_example.\io_out [33] is used but has no driver.
+Warning: Wire user_proj_example.\io_out [32] is used but has no driver.
+Warning: Wire user_proj_example.\io_out [31] is used but has no driver.
+Warning: Wire user_proj_example.\io_out [30] is used but has no driver.
+Warning: Wire user_proj_example.\io_out [29] is used but has no driver.
+Warning: Wire user_proj_example.\io_out [28] is used but has no driver.
+Warning: Wire user_proj_example.\io_out [27] is used but has no driver.
+Warning: Wire user_proj_example.\io_out [26] is used but has no driver.
+Warning: Wire user_proj_example.\io_out [25] is used but has no driver.
+Warning: Wire user_proj_example.\io_out [24] is used but has no driver.
+Warning: Wire user_proj_example.\io_out [23] is used but has no driver.
+Warning: Wire user_proj_example.\io_out [22] is used but has no driver.
+Warning: Wire user_proj_example.\io_out [21] is used but has no driver.
+Warning: Wire user_proj_example.\io_out [20] is used but has no driver.
+Warning: Wire user_proj_example.\io_out [19] is used but has no driver.
+Warning: Wire user_proj_example.\io_out [18] is used but has no driver.
+Warning: Wire user_proj_example.\io_out [17] is used but has no driver.
+Warning: Wire user_proj_example.\io_out [16] is used but has no driver.
+Warning: Wire user_proj_example.\io_out [15] is used but has no driver.
+Warning: Wire user_proj_example.\io_out [14] is used but has no driver.
+Warning: Wire user_proj_example.\io_out [13] is used but has no driver.
+Warning: Wire user_proj_example.\io_out [12] is used but has no driver.
+Warning: Wire user_proj_example.\io_out [11] is used but has no driver.
+Warning: Wire user_proj_example.\io_out [10] is used but has no driver.
+Warning: Wire user_proj_example.\io_out [9] is used but has no driver.
+Warning: Wire user_proj_example.\io_out [8] is used but has no driver.
+Warning: Wire user_proj_example.\io_out [7] is used but has no driver.
+Warning: Wire user_proj_example.\io_out [6] is used but has no driver.
+Warning: Wire user_proj_example.\io_out [5] is used but has no driver.
+Warning: Wire user_proj_example.\io_out [4] is used but has no driver.
+Warning: Wire user_proj_example.\io_out [3] is used but has no driver.
+Warning: Wire user_proj_example.\io_out [2] is used but has no driver.
+Warning: Wire user_proj_example.\io_out [1] is used but has no driver.
+Warning: Wire user_proj_example.\io_out [0] is used but has no driver.
+Warning: Wire user_proj_example.\io_oeb [37] is used but has no driver.
+Warning: Wire user_proj_example.\io_oeb [36] is used but has no driver.
+Warning: Wire user_proj_example.\io_oeb [35] is used but has no driver.
+Warning: Wire user_proj_example.\io_oeb [34] is used but has no driver.
+Warning: Wire user_proj_example.\io_oeb [33] is used but has no driver.
+Warning: Wire user_proj_example.\io_oeb [32] is used but has no driver.
+Warning: Wire user_proj_example.\io_oeb [31] is used but has no driver.
+Warning: Wire user_proj_example.\io_oeb [30] is used but has no driver.
+Warning: Wire user_proj_example.\io_oeb [29] is used but has no driver.
+Warning: Wire user_proj_example.\io_oeb [28] is used but has no driver.
+Warning: Wire user_proj_example.\io_oeb [27] is used but has no driver.
+Warning: Wire user_proj_example.\io_oeb [26] is used but has no driver.
+Warning: Wire user_proj_example.\io_oeb [25] is used but has no driver.
+Warning: Wire user_proj_example.\io_oeb [24] is used but has no driver.
+Warning: Wire user_proj_example.\io_oeb [23] is used but has no driver.
+Warning: Wire user_proj_example.\io_oeb [22] is used but has no driver.
+Warning: Wire user_proj_example.\io_oeb [21] is used but has no driver.
+Warning: Wire user_proj_example.\io_oeb [20] is used but has no driver.
+Warning: Wire user_proj_example.\io_oeb [19] is used but has no driver.
+Warning: Wire user_proj_example.\io_oeb [18] is used but has no driver.
+Warning: Wire user_proj_example.\io_oeb [17] is used but has no driver.
+Warning: Wire user_proj_example.\io_oeb [16] is used but has no driver.
+Warning: Wire user_proj_example.\io_oeb [15] is used but has no driver.
+Warning: Wire user_proj_example.\io_oeb [14] is used but has no driver.
+Warning: Wire user_proj_example.\io_oeb [13] is used but has no driver.
+Warning: Wire user_proj_example.\io_oeb [12] is used but has no driver.
+Warning: Wire user_proj_example.\io_oeb [11] is used but has no driver.
+Warning: Wire user_proj_example.\io_oeb [10] is used but has no driver.
+Warning: Wire user_proj_example.\io_oeb [9] is used but has no driver.
+Warning: Wire user_proj_example.\io_oeb [8] is used but has no driver.
+Warning: Wire user_proj_example.\io_oeb [7] is used but has no driver.
+Warning: Wire user_proj_example.\io_oeb [6] is used but has no driver.
+Warning: Wire user_proj_example.\io_oeb [5] is used but has no driver.
+Warning: Wire user_proj_example.\io_oeb [4] is used but has no driver.
+Warning: Wire user_proj_example.\io_oeb [3] is used but has no driver.
+Warning: Wire user_proj_example.\io_oeb [2] is used but has no driver.
+Warning: Wire user_proj_example.\io_oeb [1] is used but has no driver.
+Warning: Wire user_proj_example.\io_oeb [0] is used but has no driver.
+found and reported 237 problems.
+
+39. Printing statistics.
+
+=== user_proj_example ===
+
+ Number of wires: 187108
+ Number of wire bits: 187696
+ Number of public wires: 26865
+ Number of public wire bits: 27453
+ Number of memories: 0
+ Number of memory bits: 0
+ Number of processes: 0
+ Number of cells: 187329
+ sky130_fd_sc_hd__a2111o_4 35
+ sky130_fd_sc_hd__a211o_4 1593
+ sky130_fd_sc_hd__a21bo_4 68
+ sky130_fd_sc_hd__a21o_4 203
+ sky130_fd_sc_hd__a21oi_4 173
+ sky130_fd_sc_hd__a22oi_4 163
+ sky130_fd_sc_hd__a2bb2o_4 24546
+ sky130_fd_sc_hd__a32o_4 1198
+ sky130_fd_sc_hd__a41o_4 2
+ sky130_fd_sc_hd__and2_4 2003
+ sky130_fd_sc_hd__and3_4 18762
+ sky130_fd_sc_hd__and4_4 265
+ sky130_fd_sc_hd__buf_2 36084
+ sky130_fd_sc_hd__conb_1 77
+ sky130_fd_sc_hd__dfrtp_4 626
+ sky130_fd_sc_hd__dfstp_4 18
+ sky130_fd_sc_hd__dfxtp_4 26132
+ sky130_fd_sc_hd__inv_2 25679
+ sky130_fd_sc_hd__nand2_4 558
+ sky130_fd_sc_hd__nor2_4 3469
+ sky130_fd_sc_hd__o21a_4 1178
+ sky130_fd_sc_hd__o21ai_4 305
+ sky130_fd_sc_hd__o22a_4 2992
+ sky130_fd_sc_hd__o32a_4 231
+ sky130_fd_sc_hd__o41a_4 6
+ sky130_fd_sc_hd__or2_4 30981
+ sky130_fd_sc_hd__or3_4 8866
+ sky130_fd_sc_hd__or4_4 1116
+
+ Chip area for module '\user_proj_example': 2214343.731198
+
+40. Executing Verilog backend.
+Dumping module `\user_proj_example'.
+
+Warnings: 272 unique messages, 277 total
+End of script. Logfile hash: 68764362a3, CPU: user 224.83s system 0.84s, MEM: 574.65 MB peak
+Yosys 0.9+3621 (git sha1 84e9fa7, gcc 8.3.1 -fPIC -Os)
+Time spent: 58% 2x abc (303 sec), 11% 2x write_verilog (61 sec), ...
diff --git a/openlane/user_proj_example/results/logs/synthesis/yosys_rewrite_verilog.log b/openlane/user_proj_example/results/logs/synthesis/yosys_rewrite_verilog.log
new file mode 100644
index 0000000..75f421f
--- /dev/null
+++ b/openlane/user_proj_example/results/logs/synthesis/yosys_rewrite_verilog.log
@@ -0,0 +1,191576 @@
+
+ /----------------------------------------------------------------------------\
+ | |
+ | yosys -- Yosys Open SYnthesis Suite |
+ | |
+ | Copyright (C) 2012 - 2020 Claire Wolf <claire@symbioticeda.com> |
+ | |
+ | Permission to use, copy, modify, and/or distribute this software for any |
+ | purpose with or without fee is hereby granted, provided that the above |
+ | copyright notice and this permission notice appear in all copies. |
+ | |
+ | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES |
+ | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF |
+ | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR |
+ | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES |
+ | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN |
+ | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF |
+ | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. |
+ | |
+ \----------------------------------------------------------------------------/
+
+ Yosys 0.9+3621 (git sha1 84e9fa7, gcc 8.3.1 -fPIC -Os)
+
+[TCL: yosys -import] Command name collision: found pre-existing command `cd' -> skip.
+[TCL: yosys -import] Command name collision: found pre-existing command `eval' -> skip.
+[TCL: yosys -import] Command name collision: found pre-existing command `exec' -> skip.
+[TCL: yosys -import] Command name collision: found pre-existing command `read' -> skip.
+[TCL: yosys -import] Command name collision: found pre-existing command `trace' -> skip.
+
+1. Executing Verilog-2005 frontend: /project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v
+Parsing Verilog input from `/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v' to AST representation.
+Generating RTLIL representation for module `\user_proj_example'.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:38: Warning: Identifier `\softshell.cpus[2].core.flexio.out_fifo.wr_addr[1]' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:39: Warning: Identifier `\_119029_' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:45: Warning: Identifier `\_119030_' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:50: Warning: Identifier `\softshell.cpus[2].core.flexio.out_fifo.wr_addr[0]' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:51: Warning: Identifier `\_119031_' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:56: Warning: Identifier `\softshell.cpus[2].core.flexio.out_fifo.wgray[2]' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:57: Warning: Identifier `\softshell.cpus[2].core.flexio.out_fifo.wr_rgray[2]' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:58: Warning: Identifier `\_119032_' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:63: Warning: Identifier `\softshell.cpus[2].core.flexio.out_fifo.wr_rgray[0]' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:64: Warning: Identifier `\_119033_' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:69: Warning: Identifier `\softshell.cpus[2].core.flexio.out_fifo.wgray[0]' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:71: Warning: Identifier `\_119034_' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:76: Warning: Identifier `\softshell.cpus[2].core.flexio.out_fifo.wgray[1]' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:77: Warning: Identifier `\softshell.cpus[2].core.flexio.out_fifo.wr_rgray[1]' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:80: Warning: Identifier `\_119035_' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:89: Warning: Identifier `\_119036_' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:95: Warning: Identifier `\_119037_' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:104: Warning: Identifier `\_119038_' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:109: Warning: Identifier `\softshell.cpus[2].core.flexio.out_fifo.i_wr' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:111: Warning: Identifier `\_119039_' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:117: Warning: Identifier `\_119040_' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:124: Warning: Identifier `\_119041_' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:131: Warning: Identifier `\_119042_' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:137: Warning: Identifier `\_119043_' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:143: Warning: Identifier `\_119044_' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:151: Warning: Identifier `\_027307_' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:156: Warning: Identifier `\softshell.arbiter.arb_inst.rst' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:158: Warning: Identifier `\_119045_' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:164: Warning: Identifier `\_119046_' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:170: Warning: Identifier `\_119047_' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:176: Warning: Identifier `\_119048_' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:182: Warning: Identifier `\_119049_' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:188: Warning: Identifier `\_119050_' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:194: Warning: Identifier `\_119051_' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:200: Warning: Identifier `\_001026_' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:208: Warning: Identifier `\_027306_' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:214: Warning: Identifier `\_001025_' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:219: Warning: Identifier `\softshell.cpus[2].core.flexio.out_fifo.rd_addr[2]' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:220: Warning: Identifier `\_119052_' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:226: Warning: Identifier `\softshell.cpus[2].core.flexio.out_fifo.rd_wgray[2]' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:227: Warning: Identifier `\_119053_' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:232: Warning: Identifier `\softshell.cpus[2].core.flexio.out_fifo.rd_wgray[0]' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:233: Warning: Identifier `\_119054_' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:238: Warning: Identifier `\softshell.cpus[2].core.flexio.out_fifo.rgray[0]' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:240: Warning: Identifier `\_119055_' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:245: Warning: Identifier `\softshell.cpus[2].core.flexio.out_fifo.rgray[1]' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:246: Warning: Identifier `\_119056_' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:252: Warning: Identifier `\softshell.cpus[2].core.flexio.out_fifo.rd_wgray[1]' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:255: Warning: Identifier `\_119057_' is implicitly declared.
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+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1032625: Warning: Identifier `\softshell.cpus[0].core.gpio.gpio_ctrl.gpio_pu[31]' is implicitly declared.
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+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1032667: Warning: Identifier `\softshell.cpus[0].core.gpio.gpio_ctrl.gpio_pu[30]' is implicitly declared.
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+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1032719: Warning: Identifier `\_002532_' is implicitly declared.
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+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1032725: Warning: Identifier `\_104272_' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1032734: Warning: Identifier `\_002531_' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1032739: Warning: Identifier `\softshell.cpus[0].core.gpio.gpio_ctrl.gpio_pu[26]' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1032740: Warning: Identifier `\_104273_' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1032746: Warning: Identifier `\_104274_' is implicitly declared.
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+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1032766: Warning: Identifier `\softshell.cpus[0].core.gpio.gpio_ctrl.gpio_pu[25]' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1032767: Warning: Identifier `\_104276_' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1032776: Warning: Identifier `\_002529_' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1032781: Warning: Identifier `\softshell.cpus[0].core.gpio.gpio_ctrl.gpio_pu[24]' is implicitly declared.
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+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1032802: Warning: Identifier `\softshell.cpus[0].core.gpio.gpio_ctrl.gpio_pu[23]' is implicitly declared.
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+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1032817: Warning: Identifier `\softshell.cpus[0].core.gpio.gpio_ctrl.gpio_pu[22]' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1032818: Warning: Identifier `\_104280_' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1032827: Warning: Identifier `\_002526_' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1032832: Warning: Identifier `\softshell.cpus[0].core.gpio.gpio_ctrl.gpio_pu[21]' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1032833: Warning: Identifier `\_104281_' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1032839: Warning: Identifier `\_104282_' is implicitly declared.
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+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1032853: Warning: Identifier `\softshell.cpus[0].core.gpio.gpio_ctrl.gpio_pu[20]' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1032854: Warning: Identifier `\_104283_' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1032863: Warning: Identifier `\_002524_' is implicitly declared.
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+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1032940: Warning: Identifier `\softshell.cpus[0].core.gpio.gpio_ctrl.gpio_pu[15]' is implicitly declared.
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+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1157315: Warning: Identifier `\clknet_11_473_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1157322: Warning: Identifier `\clknet_11_61_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1157329: Warning: Identifier `\clknet_11_1390_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1157336: Warning: Identifier `\clknet_11_1068_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1157343: Warning: Identifier `\clknet_11_1081_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1157350: Warning: Identifier `\clknet_11_1069_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1157357: Warning: Identifier `\clknet_11_1064_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1157399: Warning: Identifier `\clknet_11_1080_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1157406: Warning: Identifier `\clknet_11_1063_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1157427: Warning: Identifier `\clknet_11_1074_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1157476: Warning: Identifier `\clknet_11_1078_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1157497: Warning: Identifier `\clknet_11_1075_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1157567: Warning: Identifier `\clknet_11_382_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1157574: Warning: Identifier `\clknet_11_1152_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1157588: Warning: Identifier `\clknet_11_1066_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1157616: Warning: Identifier `\clknet_11_1067_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1157623: Warning: Identifier `\clknet_11_1153_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1157637: Warning: Identifier `\clknet_11_1070_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1157658: Warning: Identifier `\clknet_11_1082_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1157693: Warning: Identifier `\clknet_11_1083_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1157707: Warning: Identifier `\clknet_11_1086_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1157784: Warning: Identifier `\clknet_11_1168_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1157798: Warning: Identifier `\clknet_11_468_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1157812: Warning: Identifier `\clknet_11_471_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1157826: Warning: Identifier `\clknet_11_379_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1157833: Warning: Identifier `\clknet_11_376_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1157854: Warning: Identifier `\clknet_11_377_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1157868: Warning: Identifier `\clknet_11_365_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1157917: Warning: Identifier `\clknet_11_378_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1158001: Warning: Identifier `\clknet_11_1407_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1158008: Warning: Identifier `\clknet_11_1398_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1158015: Warning: Identifier `\clknet_11_1386_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1158148: Warning: Identifier `\clknet_11_1395_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1158169: Warning: Identifier `\clknet_11_1401_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1158197: Warning: Identifier `\clknet_11_1402_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1158225: Warning: Identifier `\clknet_11_1385_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1158232: Warning: Identifier `\clknet_11_1530_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1158281: Warning: Identifier `\clknet_11_1529_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1158288: Warning: Identifier `\clknet_11_1531_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1158302: Warning: Identifier `\clknet_11_1534_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1158316: Warning: Identifier `\clknet_11_1535_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1158358: Warning: Identifier `\clknet_opt_26_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1158372: Warning: Identifier `\clknet_11_1533_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1158421: Warning: Identifier `\clknet_11_1532_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1158456: Warning: Identifier `\clknet_11_1503_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1158463: Warning: Identifier `\clknet_11_1524_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1158470: Warning: Identifier `\clknet_11_1517_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1158491: Warning: Identifier `\clknet_11_1509_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1158498: Warning: Identifier `\clknet_11_1508_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1158512: Warning: Identifier `\clknet_11_1310_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1158519: Warning: Identifier `\clknet_11_1495_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1158596: Warning: Identifier `\clknet_11_1501_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1158659: Warning: Identifier `\clknet_11_372_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1158666: Warning: Identifier `\clknet_11_373_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1158694: Warning: Identifier `\clknet_11_374_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1158701: Warning: Identifier `\clknet_11_375_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1158729: Warning: Identifier `\clknet_11_55_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1158743: Warning: Identifier `\clknet_11_111_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1158750: Warning: Identifier `\clknet_11_54_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1158757: Warning: Identifier `\clknet_11_50_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1158764: Warning: Identifier `\clknet_11_56_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1158771: Warning: Identifier `\clknet_11_39_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1158869: Warning: Identifier `\clknet_11_57_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1158897: Warning: Identifier `\clknet_11_51_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1158904: Warning: Identifier `\clknet_11_60_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1158953: Warning: Identifier `\clknet_11_108_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1158960: Warning: Identifier `\clknet_11_58_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1158967: Warning: Identifier `\clknet_11_46_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1158981: Warning: Identifier `\clknet_11_43_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1158988: Warning: Identifier `\clknet_11_42_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1159058: Warning: Identifier `\clknet_11_47_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1159107: Warning: Identifier `\clknet_11_59_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1159149: Warning: Identifier `\clknet_11_62_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1159156: Warning: Identifier `\clknet_11_145_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1159184: Warning: Identifier `\clknet_11_124_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1159191: Warning: Identifier `\clknet_11_103_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1159198: Warning: Identifier `\clknet_11_126_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1159212: Warning: Identifier `\clknet_11_119_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1159254: Warning: Identifier `\clknet_11_290_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1159282: Warning: Identifier `\clknet_11_125_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1159303: Warning: Identifier `\clknet_11_117_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1159373: Warning: Identifier `\clknet_11_296_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1159394: Warning: Identifier `\clknet_11_1155_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1159408: Warning: Identifier `\clknet_11_1156_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1159464: Warning: Identifier `\clknet_11_453_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1159485: Warning: Identifier `\clknet_11_1157_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1159576: Warning: Identifier `\clknet_11_1311_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1159583: Warning: Identifier `\clknet_11_1377_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1159597: Warning: Identifier `\clknet_11_1383_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1159611: Warning: Identifier `\clknet_11_1511_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1159632: Warning: Identifier `\clknet_11_1497_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1159646: Warning: Identifier `\clknet_11_1496_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1159674: Warning: Identifier `\clknet_11_383_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1159695: Warning: Identifier `\clknet_11_120_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1159716: Warning: Identifier `\clknet_11_298_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1159730: Warning: Identifier `\clknet_11_127_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1159744: Warning: Identifier `\clknet_11_1384_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1159758: Warning: Identifier `\clknet_11_1525_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1159779: Warning: Identifier `\clknet_11_113_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1159800: Warning: Identifier `\clknet_11_112_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1159835: Warning: Identifier `\clknet_11_109_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1159877: Warning: Identifier `\clknet_11_1378_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1159926: Warning: Identifier `\clknet_11_1628_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1159947: Warning: Identifier `\clknet_11_1629_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1159982: Warning: Identifier `\clknet_11_1630_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1160003: Warning: Identifier `\clknet_11_1631_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1160038: Warning: Identifier `\clknet_11_1561_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1160045: Warning: Identifier `\clknet_11_1563_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1160052: Warning: Identifier `\clknet_11_1566_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1160094: Warning: Identifier `\clknet_11_847_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1160101: Warning: Identifier `\clknet_11_846_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1160115: Warning: Identifier `\clknet_11_858_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1160150: Warning: Identifier `\clknet_11_857_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1160164: Warning: Identifier `\clknet_11_859_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1160192: Warning: Identifier `\clknet_11_862_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1160206: Warning: Identifier `\clknet_11_856_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1160318: Warning: Identifier `\clknet_11_1560_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1160332: Warning: Identifier `\clknet_11_1562_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1160374: Warning: Identifier `\clknet_11_1551_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1160486: Warning: Identifier `\clknet_11_1548_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1160493: Warning: Identifier `\clknet_11_1550_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1160598: Warning: Identifier `\clknet_11_842_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1160619: Warning: Identifier `\clknet_11_799_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1160654: Warning: Identifier `\clknet_11_844_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1160717: Warning: Identifier `\clknet_11_841_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1160731: Warning: Identifier `\clknet_11_843_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1160843: Warning: Identifier `\clknet_11_840_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1160934: Warning: Identifier `\clknet_11_594_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1160941: Warning: Identifier `\clknet_11_583_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1160948: Warning: Identifier `\clknet_11_600_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1160983: Warning: Identifier `\clknet_11_602_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1160997: Warning: Identifier `\clknet_11_589_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1161158: Warning: Identifier `\clknet_11_531_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1161179: Warning: Identifier `\clknet_11_588_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1161214: Warning: Identifier `\clknet_11_530_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1161221: Warning: Identifier `\clknet_11_536_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1161291: Warning: Identifier `\clknet_11_584_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1161298: Warning: Identifier `\clknet_11_585_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1161431: Warning: Identifier `\clknet_11_586_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1161438: Warning: Identifier `\clknet_11_540_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1161445: Warning: Identifier `\clknet_11_537_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1161515: Warning: Identifier `\clknet_11_541_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1161627: Warning: Identifier `\clknet_11_590_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1161648: Warning: Identifier `\clknet_11_587_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1161662: Warning: Identifier `\clknet_11_606_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1161774: Warning: Identifier `\clknet_11_603_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1161865: Warning: Identifier `\clknet_11_591_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1161886: Warning: Identifier `\clknet_11_519_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1161998: Warning: Identifier `\clknet_11_525_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1162054: Warning: Identifier `\clknet_11_524_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1162145: Warning: Identifier `\clknet_11_538_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1162180: Warning: Identifier `\clknet_11_526_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1162208: Warning: Identifier `\clknet_11_539_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1162243: Warning: Identifier `\clknet_11_527_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1162334: Warning: Identifier `\clknet_11_143_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1162362: Warning: Identifier `\clknet_11_141_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1162390: Warning: Identifier `\clknet_11_520_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1162446: Warning: Identifier `\clknet_11_549_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1162558: Warning: Identifier `\clknet_11_548_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1162656: Warning: Identifier `\clknet_11_561_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1162677: Warning: Identifier `\clknet_11_132_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1162712: Warning: Identifier `\clknet_11_134_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1162733: Warning: Identifier `\clknet_11_299_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1162894: Warning: Identifier `\clknet_11_297_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1162957: Warning: Identifier `\clknet_11_106_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1162971: Warning: Identifier `\clknet_11_63_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1163069: Warning: Identifier `\clknet_11_107_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1163083: Warning: Identifier `\clknet_11_105_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1163097: Warning: Identifier `\clknet_11_104_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1163153: Warning: Identifier `\clknet_11_148_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1163223: Warning: Identifier `\clknet_11_542_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1163237: Warning: Identifier `\clknet_11_550_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1163258: Warning: Identifier `\clknet_11_551_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1163265: Warning: Identifier `\clknet_11_562_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1163440: Warning: Identifier `\clknet_11_196_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1163601: Warning: Identifier `\clknet_11_560_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1163629: Warning: Identifier `\clknet_11_802_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1163650: Warning: Identifier `\clknet_11_637_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1163671: Warning: Identifier `\clknet_11_639_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1163706: Warning: Identifier `\clknet_11_563_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1163734: Warning: Identifier `\clknet_11_566_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1163825: Warning: Identifier `\clknet_11_636_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1163846: Warning: Identifier `\clknet_11_638_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1164014: Warning: Identifier `\clknet_11_564_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1164042: Warning: Identifier `\clknet_11_569_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1164161: Warning: Identifier `\clknet_11_572_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1164196: Warning: Identifier `\clknet_11_573_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1164210: Warning: Identifier `\clknet_11_567_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1164357: Warning: Identifier `\clknet_11_619_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1164378: Warning: Identifier `\clknet_11_623_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1164413: Warning: Identifier `\clknet_11_628_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1164434: Warning: Identifier `\clknet_11_630_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1164469: Warning: Identifier `\clknet_11_618_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1164553: Warning: Identifier `\clknet_11_140_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1164581: Warning: Identifier `\clknet_11_138_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1164602: Warning: Identifier `\clknet_11_136_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1164623: Warning: Identifier `\clknet_11_137_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1164693: Warning: Identifier `\clknet_11_601_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1164756: Warning: Identifier `\clknet_11_622_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1164798: Warning: Identifier `\clknet_11_634_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1164882: Warning: Identifier `\clknet_11_581_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1164917: Warning: Identifier `\clknet_11_1236_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1164931: Warning: Identifier `\clknet_11_1237_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1164966: Warning: Identifier `\clknet_11_1480_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1164973: Warning: Identifier `\clknet_11_661_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1164994: Warning: Identifier `\clknet_11_705_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1165015: Warning: Identifier `\clknet_11_720_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1165022: Warning: Identifier `\clknet_11_709_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1165029: Warning: Identifier `\clknet_11_1490_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1165036: Warning: Identifier `\clknet_11_1491_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1165057: Warning: Identifier `\clknet_11_1479_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1165211: Warning: Identifier `\clknet_11_704_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1165225: Warning: Identifier `\clknet_11_721_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1165239: Warning: Identifier `\clknet_11_724_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1165295: Warning: Identifier `\clknet_11_635_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1165316: Warning: Identifier `\clknet_11_1500_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1165372: Warning: Identifier `\clknet_11_1502_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1165407: Warning: Identifier `\clknet_11_1478_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1165421: Warning: Identifier `\clknet_11_633_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1165477: Warning: Identifier `\clknet_11_795_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1165519: Warning: Identifier `\clknet_11_794_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1165540: Warning: Identifier `\clknet_11_621_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1165547: Warning: Identifier `\clknet_11_632_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1165701: Warning: Identifier `\clknet_11_492_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1165715: Warning: Identifier `\clknet_11_493_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1165736: Warning: Identifier `\clknet_11_494_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1165967: Warning: Identifier `\clknet_11_495_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1166079: Warning: Identifier `\clknet_11_725_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1166086: Warning: Identifier `\clknet_11_727_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1166149: Warning: Identifier `\clknet_11_1589_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1166205: Warning: Identifier `\clknet_11_1576_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1166212: Warning: Identifier `\clknet_11_1577_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1166226: Warning: Identifier `\clknet_11_885_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1166261: Warning: Identifier `\clknet_11_1806_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1166282: Warning: Identifier `\clknet_11_1819_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1166289: Warning: Identifier `\clknet_11_1818_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1166317: Warning: Identifier `\clknet_11_1485_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1166338: Warning: Identifier `\clknet_11_1484_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1166373: Warning: Identifier `\clknet_11_1807_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1166394: Warning: Identifier `\clknet_11_1817_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1166408: Warning: Identifier `\clknet_11_1816_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1166583: Warning: Identifier `\clknet_11_1584_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1166597: Warning: Identifier `\clknet_11_1585_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1166653: Warning: Identifier `\clknet_11_1588_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1166765: Warning: Identifier `\clknet_11_1486_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1166835: Warning: Identifier `\clknet_11_1487_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1166870: Warning: Identifier `\clknet_11_1481_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1166905: Warning: Identifier `\clknet_11_1475_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1166989: Warning: Identifier `\clknet_11_1573_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1167031: Warning: Identifier `\clknet_11_1572_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1167101: Warning: Identifier `\clknet_11_1477_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1167213: Warning: Identifier `\clknet_11_1488_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1167234: Warning: Identifier `\clknet_11_1489_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1167255: Warning: Identifier `\clknet_11_1338_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1167269: Warning: Identifier `\clknet_11_1571_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1167283: Warning: Identifier `\clknet_11_1574_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1167311: Warning: Identifier `\clknet_11_1570_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1167346: Warning: Identifier `\clknet_11_1575_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1167458: Warning: Identifier `\clknet_11_1569_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1167486: Warning: Identifier `\clknet_11_1568_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1167738: Warning: Identifier `\clknet_11_863_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1167766: Warning: Identifier `\clknet_11_881_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1167773: Warning: Identifier `\clknet_11_1492_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1167822: Warning: Identifier `\clknet_11_1336_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1167920: Warning: Identifier `\clknet_11_1339_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1168032: Warning: Identifier `\clknet_11_880_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1168039: Warning: Identifier `\clknet_11_869_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1168095: Warning: Identifier `\clknet_11_868_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1168382: Warning: Identifier `\clknet_11_1331_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1168396: Warning: Identifier `\clknet_11_1330_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1168473: Warning: Identifier `\clknet_11_1335_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1168487: Warning: Identifier `\clknet_11_1334_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1168557: Warning: Identifier `\clknet_11_1332_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1168564: Warning: Identifier `\clknet_11_1328_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1168606: Warning: Identifier `\clknet_11_1329_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1168676: Warning: Identifier `\clknet_11_1343_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1168683: Warning: Identifier `\clknet_11_1306_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1168697: Warning: Identifier `\clknet_11_1341_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1168725: Warning: Identifier `\clknet_11_1340_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1168732: Warning: Identifier `\clknet_11_208_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1168739: Warning: Identifier `\clknet_11_210_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1168753: Warning: Identifier `\clknet_11_197_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1168774: Warning: Identifier `\clknet_11_122_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1168816: Warning: Identifier `\clknet_11_123_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1169040: Warning: Identifier `\clknet_11_865_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1169047: Warning: Identifier `\clknet_11_864_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1169145: Warning: Identifier `\clknet_11_1342_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1169152: Warning: Identifier `\clknet_11_1337_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1169327: Warning: Identifier `\clknet_11_209_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1169453: Warning: Identifier `\clknet_11_1493_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1169558: Warning: Identifier `\clknet_11_1494_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1169873: Warning: Identifier `\clknet_11_1327_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1169922: Warning: Identifier `\clknet_11_300_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1170006: Warning: Identifier `\clknet_11_222_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1170020: Warning: Identifier `\clknet_11_212_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1170062: Warning: Identifier `\clknet_11_219_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1170069: Warning: Identifier `\clknet_11_217_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1170097: Warning: Identifier `\clknet_11_220_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1170160: Warning: Identifier `\clknet_11_245_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1170174: Warning: Identifier `\clknet_11_244_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1170195: Warning: Identifier `\clknet_11_223_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1170230: Warning: Identifier `\clknet_11_218_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1170265: Warning: Identifier `\clknet_11_207_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1170279: Warning: Identifier `\clknet_11_205_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1170314: Warning: Identifier `\clknet_11_216_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1170370: Warning: Identifier `\clknet_11_241_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1170391: Warning: Identifier `\clknet_11_240_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1170475: Warning: Identifier `\clknet_11_129_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1170734: Warning: Identifier `\clknet_11_778_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1170741: Warning: Identifier `\clknet_11_629_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1170755: Warning: Identifier `\clknet_11_607_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1170811: Warning: Identifier `\clknet_11_798_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1170846: Warning: Identifier `\clknet_11_154_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1170867: Warning: Identifier `\clknet_11_152_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1170937: Warning: Identifier `\clknet_11_452_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1171028: Warning: Identifier `\clknet_11_469_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1171126: Warning: Identifier `\clknet_11_380_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1171133: Warning: Identifier `\clknet_11_1084_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1171147: Warning: Identifier `\clknet_11_1085_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1171294: Warning: Identifier `\clknet_11_1065_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1171455: Warning: Identifier `\clknet_11_1071_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1171483: Warning: Identifier `\clknet_11_381_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1171602: Warning: Identifier `\clknet_11_371_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1171672: Warning: Identifier `\clknet_11_142_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1171728: Warning: Identifier `\clknet_11_455_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1171735: Warning: Identifier `\clknet_11_464_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1171770: Warning: Identifier `\clknet_11_367_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1171805: Warning: Identifier `\clknet_11_96_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1171812: Warning: Identifier `\clknet_11_53_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1171819: Warning: Identifier `\clknet_11_49_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1171847: Warning: Identifier `\clknet_11_30_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1171854: Warning: Identifier `\clknet_11_27_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1171868: Warning: Identifier `\clknet_11_25_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1171875: Warning: Identifier `\clknet_11_19_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1171910: Warning: Identifier `\clknet_11_22_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1171917: Warning: Identifier `\clknet_11_20_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1171924: Warning: Identifier `\clknet_11_65_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1171938: Warning: Identifier `\clknet_11_84_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1171952: Warning: Identifier `\clknet_11_85_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1171959: Warning: Identifier `\clknet_11_256_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1171966: Warning: Identifier `\clknet_11_258_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1172001: Warning: Identifier `\clknet_11_93_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1172008: Warning: Identifier `\clknet_11_264_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1172015: Warning: Identifier `\clknet_11_95_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1172029: Warning: Identifier `\clknet_11_159_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1172085: Warning: Identifier `\clknet_11_195_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1172092: Warning: Identifier `\clknet_11_194_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1172113: Warning: Identifier `\clknet_11_151_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1172120: Warning: Identifier `\clknet_11_149_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1172155: Warning: Identifier `\clknet_11_150_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1172183: Warning: Identifier `\clknet_11_157_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1172204: Warning: Identifier `\clknet_11_200_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1172218: Warning: Identifier `\clknet_11_201_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1172225: Warning: Identifier `\clknet_11_204_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1172260: Warning: Identifier `\clknet_11_199_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1172323: Warning: Identifier `\clknet_11_52_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1172330: Warning: Identifier `\clknet_11_48_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1172344: Warning: Identifier `\clknet_11_15_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1172358: Warning: Identifier `\clknet_11_13_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1172379: Warning: Identifier `\clknet_11_7_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1172393: Warning: Identifier `\clknet_11_5_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1172407: Warning: Identifier `\clknet_11_16_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1172421: Warning: Identifier `\clknet_11_17_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1172428: Warning: Identifier `\clknet_11_69_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1172463: Warning: Identifier `\clknet_11_82_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1172477: Warning: Identifier `\clknet_11_71_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1172484: Warning: Identifier `\clknet_11_88_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1172526: Warning: Identifier `\clknet_11_90_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1172533: Warning: Identifier `\clknet_11_75_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1172547: Warning: Identifier `\clknet_11_32_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1172568: Warning: Identifier `\clknet_11_11_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1172582: Warning: Identifier `\clknet_11_9_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1172617: Warning: Identifier `\clknet_11_4_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1172652: Warning: Identifier `\clknet_11_21_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1172666: Warning: Identifier `\clknet_11_64_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1172687: Warning: Identifier `\clknet_11_29_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1172708: Warning: Identifier `\clknet_11_72_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1172729: Warning: Identifier `\clknet_11_74_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1172876: Warning: Identifier `\clknet_11_81_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1172918: Warning: Identifier `\clknet_11_89_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1172925: Warning: Identifier `\clknet_11_92_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1173058: Warning: Identifier `\clknet_11_2_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1173072: Warning: Identifier `\clknet_11_6_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1173135: Warning: Identifier `\clknet_11_66_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1173464: Warning: Identifier `\clknet_11_882_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1173492: Warning: Identifier `\clknet_11_1632_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1173548: Warning: Identifier `\clknet_11_1614_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1173569: Warning: Identifier `\clknet_11_1611_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1173583: Warning: Identifier `\clknet_11_1633_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1173590: Warning: Identifier `\clknet_11_1636_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1173674: Warning: Identifier `\clknet_11_1637_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1173681: Warning: Identifier `\clknet_11_1610_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1173772: Warning: Identifier `\clknet_11_1652_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1173793: Warning: Identifier `\clknet_11_1802_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1173814: Warning: Identifier `\clknet_11_1824_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1173926: Warning: Identifier `\clknet_11_1653_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1174038: Warning: Identifier `\clknet_11_1825_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1174052: Warning: Identifier `\clknet_11_1626_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1174059: Warning: Identifier `\clknet_11_1627_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1174087: Warning: Identifier `\clknet_11_1648_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1174129: Warning: Identifier `\clknet_11_1615_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1174220: Warning: Identifier `\clknet_11_1036_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1174227: Warning: Identifier `\clknet_11_1032_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1174234: Warning: Identifier `\clknet_11_339_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1174248: Warning: Identifier `\clknet_11_342_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1174255: Warning: Identifier `\clknet_11_343_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1174262: Warning: Identifier `\clknet_11_340_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1174269: Warning: Identifier `\clknet_11_1024_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1174276: Warning: Identifier `\clknet_11_341_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1174283: Warning: Identifier `\clknet_11_1025_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1174290: Warning: Identifier `\clknet_11_1028_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1174304: Warning: Identifier `\clknet_11_1029_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1174311: Warning: Identifier `\clknet_11_1040_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1174318: Warning: Identifier `\clknet_11_1041_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1174325: Warning: Identifier `\clknet_11_1044_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1174332: Warning: Identifier `\clknet_11_1045_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1174339: Warning: Identifier `\clknet_11_1089_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1174346: Warning: Identifier `\clknet_11_1091_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1174353: Warning: Identifier `\clknet_11_1092_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1174367: Warning: Identifier `\clknet_11_1093_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1174374: Warning: Identifier `\clknet_11_1095_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1174409: Warning: Identifier `\clknet_11_1047_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1174416: Warning: Identifier `\clknet_11_1046_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1174430: Warning: Identifier `\clknet_11_1052_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1174444: Warning: Identifier `\clknet_11_1034_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1174458: Warning: Identifier `\clknet_11_345_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1174472: Warning: Identifier `\clknet_11_348_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1174486: Warning: Identifier `\clknet_11_349_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1174507: Warning: Identifier `\clknet_11_1035_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1174521: Warning: Identifier `\clknet_11_1038_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1174528: Warning: Identifier `\clknet_11_1054_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1174549: Warning: Identifier `\clknet_11_1053_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1174556: Warning: Identifier `\clknet_11_1055_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1174584: Warning: Identifier `\clknet_11_1098_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1174591: Warning: Identifier `\clknet_11_1096_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1174598: Warning: Identifier `\clknet_11_1113_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1174605: Warning: Identifier `\clknet_11_1112_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1174612: Warning: Identifier `\clknet_11_1097_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1174633: Warning: Identifier `\clknet_11_1050_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1174640: Warning: Identifier `\clknet_11_1039_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1174752: Warning: Identifier `\clknet_11_1051_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1175130: Warning: Identifier `\clknet_11_350_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1175144: Warning: Identifier `\clknet_11_351_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1175263: Warning: Identifier `\clknet_11_1099_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1175613: Warning: Identifier `\clknet_11_1056_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1175634: Warning: Identifier `\clknet_11_1057_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1175641: Warning: Identifier `\clknet_11_1060_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1175648: Warning: Identifier `\clknet_11_1072_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1175655: Warning: Identifier `\clknet_11_1073_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1175669: Warning: Identifier `\clknet_11_1076_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1175676: Warning: Identifier `\clknet_11_1077_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1175683: Warning: Identifier `\clknet_11_1120_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1175704: Warning: Identifier `\clknet_11_1124_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1175718: Warning: Identifier `\clknet_11_1114_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1175739: Warning: Identifier `\clknet_11_1125_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1175767: Warning: Identifier `\clknet_11_1061_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1176131: Warning: Identifier `\clknet_11_1121_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1176166: Warning: Identifier `\clknet_11_1115_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1176628: Warning: Identifier `\clknet_11_1094_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1176642: Warning: Identifier `\clknet_11_1100_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1176908: Warning: Identifier `\clknet_11_1033_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1177083: Warning: Identifier `\clknet_11_1108_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1177251: Warning: Identifier `\clknet_11_1088_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1177286: Warning: Identifier `\clknet_11_1109_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1177370: Warning: Identifier `\clknet_11_344_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1178084: Warning: Identifier `\clknet_11_1027_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1178091: Warning: Identifier `\clknet_11_1026_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1178098: Warning: Identifier `\clknet_11_338_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1178112: Warning: Identifier `\clknet_11_337_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1178161: Warning: Identifier `\clknet_11_1030_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1178175: Warning: Identifier `\clknet_11_1042_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1178203: Warning: Identifier `\clknet_11_1090_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1178238: Warning: Identifier `\clknet_11_1110_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1178245: Warning: Identifier `\clknet_11_1105_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1178259: Warning: Identifier `\clknet_11_1104_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1178266: Warning: Identifier `\clknet_11_1101_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1178273: Warning: Identifier `\clknet_11_1049_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1178308: Warning: Identifier `\clknet_11_1649_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1178364: Warning: Identifier `\clknet_11_1803_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1178406: Warning: Identifier `\clknet_11_1829_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1178462: Warning: Identifier `\clknet_11_1828_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1178686: Warning: Identifier `\clknet_11_1106_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1178728: Warning: Identifier `\clknet_11_1048_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1178742: Warning: Identifier `\clknet_11_1037_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1178847: Warning: Identifier `\clknet_11_1043_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1179148: Warning: Identifier `\clknet_11_1844_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1179204: Warning: Identifier `\clknet_11_91_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1179218: Warning: Identifier `\clknet_11_37_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1179225: Warning: Identifier `\clknet_11_36_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1179239: Warning: Identifier `\clknet_11_26_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1179267: Warning: Identifier `\clknet_11_24_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1179365: Warning: Identifier `\clknet_11_86_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1179414: Warning: Identifier `\clknet_11_94_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1179484: Warning: Identifier `\clknet_11_1822_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1179491: Warning: Identifier `\clknet_11_1823_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1179638: Warning: Identifier `\clknet_11_1845_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1179652: Warning: Identifier `\clknet_11_1868_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1179673: Warning: Identifier `\clknet_11_1865_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1179694: Warning: Identifier `\clknet_11_1866_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1179701: Warning: Identifier `\clknet_11_1864_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1179820: Warning: Identifier `\clknet_11_1858_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1179876: Warning: Identifier `\clknet_11_1884_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1179897: Warning: Identifier `\clknet_11_1880_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1179918: Warning: Identifier `\clknet_11_1862_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1179925: Warning: Identifier `\clknet_11_1859_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1179932: Warning: Identifier `\clknet_11_1886_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1179939: Warning: Identifier `\clknet_11_1887_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1179946: Warning: Identifier `\clknet_11_1885_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1179953: Warning: Identifier `\clknet_11_1881_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1180044: Warning: Identifier `\clknet_11_1883_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1180093: Warning: Identifier `\clknet_11_1882_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1180107: Warning: Identifier `\clknet_11_1893_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1180198: Warning: Identifier `\clknet_11_1871_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1180212: Warning: Identifier `\clknet_11_1892_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1180219: Warning: Identifier `\clknet_11_1895_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1180233: Warning: Identifier `\clknet_11_1894_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1180373: Warning: Identifier `\clknet_11_1891_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1180380: Warning: Identifier `\clknet_11_1143_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1180401: Warning: Identifier `\clknet_11_1322_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1180408: Warning: Identifier `\clknet_11_1323_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1180422: Warning: Identifier `\clknet_11_1326_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1180436: Warning: Identifier `\clknet_11_1140_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1180443: Warning: Identifier `\clknet_11_1141_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1180457: Warning: Identifier `\clknet_11_1320_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1180464: Warning: Identifier `\clknet_11_1321_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1180604: Warning: Identifier `\clknet_11_1142_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1180660: Warning: Identifier `\clknet_11_1139_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1180716: Warning: Identifier `\clknet_11_1241_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1180723: Warning: Identifier `\clknet_11_1244_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1180730: Warning: Identifier `\clknet_11_1223_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1180737: Warning: Identifier `\clknet_11_1222_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1180758: Warning: Identifier `\clknet_11_1219_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1180765: Warning: Identifier `\clknet_11_1234_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1180814: Warning: Identifier `\clknet_11_1217_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1180821: Warning: Identifier `\clknet_11_1220_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1180835: Warning: Identifier `\clknet_11_1482_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1180849: Warning: Identifier `\clknet_11_1239_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1180877: Warning: Identifier `\clknet_11_1235_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1180905: Warning: Identifier `\clknet_11_1238_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1181038: Warning: Identifier `\clknet_11_1473_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1181045: Warning: Identifier `\clknet_11_1476_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1181052: Warning: Identifier `\clknet_11_139_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1181073: Warning: Identifier `\clknet_11_131_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1181143: Warning: Identifier `\clknet_11_1472_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1181353: Warning: Identifier `\clknet_11_1245_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1181500: Warning: Identifier `\clknet_11_1164_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1181528: Warning: Identifier `\clknet_11_1148_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1181612: Warning: Identifier `\clknet_11_1870_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1181619: Warning: Identifier `\clknet_11_1889_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1181647: Warning: Identifier `\clknet_11_1149_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1181682: Warning: Identifier `\clknet_11_1901_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1181696: Warning: Identifier `\clknet_11_1900_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1181794: Warning: Identifier `\clknet_11_1902_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1181815: Warning: Identifier `\clknet_11_1899_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1181822: Warning: Identifier `\clknet_11_1897_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1181836: Warning: Identifier `\clknet_11_1896_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1181857: Warning: Identifier `\clknet_11_1145_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1181976: Warning: Identifier `\clknet_11_1150_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1181983: Warning: Identifier `\clknet_11_1474_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1182032: Warning: Identifier `\clknet_11_1151_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1182130: Warning: Identifier `\clknet_11_97_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1182144: Warning: Identifier `\clknet_11_34_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1182151: Warning: Identifier `\clknet_11_33_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1182165: Warning: Identifier `\clknet_11_14_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1182179: Warning: Identifier `\clknet_11_12_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1182200: Warning: Identifier `\clknet_11_3_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1182263: Warning: Identifier `\clknet_11_68_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1182284: Warning: Identifier `\clknet_11_70_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1182305: Warning: Identifier `\clknet_11_76_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1182319: Warning: Identifier `\clknet_11_78_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1182340: Warning: Identifier `\clknet_11_79_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1182410: Warning: Identifier `\clknet_11_1835_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1182431: Warning: Identifier `\clknet_11_1834_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1182480: Warning: Identifier `\clknet_11_477_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1182564: Warning: Identifier `\clknet_11_1169_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1182571: Warning: Identifier `\clknet_11_1171_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1182585: Warning: Identifier `\clknet_11_1173_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1182599: Warning: Identifier `\clknet_11_1172_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1182690: Warning: Identifier `\clknet_11_1986_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1182711: Warning: Identifier `\clknet_11_1941_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1182823: Warning: Identifier `\clknet_11_1943_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1182914: Warning: Identifier `\clknet_11_1898_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1182956: Warning: Identifier `\clknet_11_1855_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1182970: Warning: Identifier `\clknet_11_1820_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1183110: Warning: Identifier `\clknet_11_1853_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1183250: Warning: Identifier `\clknet_11_1890_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1183257: Warning: Identifier `\clknet_11_1888_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1183292: Warning: Identifier `\clknet_11_1852_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1183418: Warning: Identifier `\clknet_11_1662_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1183439: Warning: Identifier `\clknet_11_1749_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1183572: Warning: Identifier `\clknet_11_206_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1183789: Warning: Identifier `\clknet_11_1867_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1184090: Warning: Identifier `\clknet_11_1985_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1184111: Warning: Identifier `\clknet_11_1987_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1184146: Warning: Identifier `\clknet_11_1995_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1184167: Warning: Identifier `\clknet_11_2018_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1184188: Warning: Identifier `\clknet_11_2024_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1184202: Warning: Identifier `\clknet_11_1878_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1184209: Warning: Identifier `\clknet_11_1874_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1184223: Warning: Identifier `\clknet_11_1876_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1184230: Warning: Identifier `\clknet_11_1879_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1184314: Warning: Identifier `\clknet_11_1993_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1184335: Warning: Identifier `\clknet_11_2025_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1184391: Warning: Identifier `\clknet_11_2019_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1184447: Warning: Identifier `\clknet_11_2026_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1184559: Warning: Identifier `\clknet_11_2027_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1184608: Warning: Identifier `\clknet_11_2028_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1184783: Warning: Identifier `\clknet_11_1087_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1184986: Warning: Identifier `\clknet_11_2017_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1185007: Warning: Identifier `\clknet_11_2016_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1185014: Warning: Identifier `\clknet_11_1951_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1185105: Warning: Identifier `\clknet_11_1920_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1185154: Warning: Identifier `\clknet_11_1591_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1185231: Warning: Identifier `\clknet_11_1994_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1185259: Warning: Identifier `\clknet_11_1949_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1185567: Warning: Identifier `\clknet_11_1973_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1185595: Warning: Identifier `\clknet_11_1972_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1185658: Warning: Identifier `\clknet_11_1863_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1185756: Warning: Identifier `\clknet_11_1950_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1185826: Warning: Identifier `\clknet_11_1746_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1185868: Warning: Identifier `\clknet_11_1733_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1185938: Warning: Identifier `\clknet_11_1992_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1186050: Warning: Identifier `\clknet_11_1984_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1186162: Warning: Identifier `\clknet_11_203_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1186442: Warning: Identifier `\clknet_11_1934_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1186449: Warning: Identifier `\clknet_11_1935_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1186470: Warning: Identifier `\clknet_11_1932_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1186589: Warning: Identifier `\clknet_11_1933_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1186610: Warning: Identifier `\clknet_11_1841_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1186624: Warning: Identifier `\clknet_11_1846_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1186631: Warning: Identifier `\clknet_11_1843_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1186666: Warning: Identifier `\clknet_11_1838_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1186778: Warning: Identifier `\clknet_11_1931_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1186834: Warning: Identifier `\clknet_11_1930_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1186869: Warning: Identifier `\clknet_11_1928_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1186925: Warning: Identifier `\clknet_11_1929_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1187058: Warning: Identifier `\clknet_11_911_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1187079: Warning: Identifier `\clknet_11_933_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1187107: Warning: Identifier `\clknet_11_922_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1187282: Warning: Identifier `\clknet_11_1147_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1187310: Warning: Identifier `\clknet_11_1146_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1187366: Warning: Identifier `\clknet_11_1144_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1187527: Warning: Identifier `\clknet_11_1233_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1187534: Warning: Identifier `\clknet_11_1232_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1187604: Warning: Identifier `\clknet_11_1221_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1187709: Warning: Identifier `\clknet_11_1317_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1187786: Warning: Identifier `\clknet_11_1333_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1187814: Warning: Identifier `\clknet_11_1296_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1187891: Warning: Identifier `\clknet_11_1319_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1187919: Warning: Identifier `\clknet_11_1318_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1187926: Warning: Identifier `\clknet_11_1315_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1187954: Warning: Identifier `\clknet_11_1316_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1187989: Warning: Identifier `\clknet_11_1313_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1188171: Warning: Identifier `\clknet_11_1312_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1188276: Warning: Identifier `\clknet_11_1314_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1188374: Warning: Identifier `\clknet_11_1324_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1188528: Warning: Identifier `\clknet_11_1325_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1188843: Warning: Identifier `\clknet_11_1138_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1189018: Warning: Identifier `\clknet_11_362_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1189032: Warning: Identifier `\clknet_11_363_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1189067: Warning: Identifier `\clknet_11_315_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1189935: Warning: Identifier `\clknet_11_1744_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1189970: Warning: Identifier `\clknet_11_1748_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1190054: Warning: Identifier `\clknet_11_128_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1190082: Warning: Identifier `\clknet_11_1510_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1190089: Warning: Identifier `\clknet_11_1507_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1190096: Warning: Identifier `\clknet_11_1506_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1190145: Warning: Identifier `\clknet_11_1505_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1190208: Warning: Identifier `\clknet_11_1526_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1190257: Warning: Identifier `\clknet_11_1527_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1190271: Warning: Identifier `\clknet_11_1521_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1190390: Warning: Identifier `\clknet_11_1307_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1190481: Warning: Identifier `\clknet_11_1387_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1190502: Warning: Identifier `\clknet_11_1528_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1190523: Warning: Identifier `\clknet_11_1391_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1190551: Warning: Identifier `\clknet_11_1400_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1190691: Warning: Identifier `\clknet_11_1379_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1190873: Warning: Identifier `\clknet_11_130_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1190908: Warning: Identifier `\clknet_11_1504_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1191104: Warning: Identifier `\clknet_11_1102_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1191167: Warning: Identifier `\clknet_11_1103_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1191552: Warning: Identifier `\clknet_11_83_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1191559: Warning: Identifier `\clknet_11_80_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1191867: Warning: Identifier `\clknet_11_1031_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1192105: Warning: Identifier `\clknet_11_193_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1192119: Warning: Identifier `\clknet_11_192_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1192189: Warning: Identifier `\clknet_11_156_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1192308: Warning: Identifier `\clknet_11_198_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1192371: Warning: Identifier `\clknet_11_31_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1192553: Warning: Identifier `\clknet_11_100_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1192700: Warning: Identifier `\clknet_11_67_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1192777: Warning: Identifier `\clknet_11_1780_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1192791: Warning: Identifier `\clknet_11_1759_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1192826: Warning: Identifier `\clknet_11_1757_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1192861: Warning: Identifier `\clknet_11_1758_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1192910: Warning: Identifier `\clknet_11_336_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1193120: Warning: Identifier `\clknet_11_1781_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1193512: Warning: Identifier `\clknet_11_1952_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1193680: Warning: Identifier `\clknet_11_1777_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1193764: Warning: Identifier `\clknet_11_1755_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1193869: Warning: Identifier `\clknet_11_1776_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1193883: Warning: Identifier `\clknet_11_1754_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1194023: Warning: Identifier `\clknet_11_1765_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1194051: Warning: Identifier `\clknet_11_1743_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1194072: Warning: Identifier `\clknet_11_1761_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1194107: Warning: Identifier `\clknet_11_1739_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1194184: Warning: Identifier `\clknet_11_1764_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1194191: Warning: Identifier `\clknet_11_1763_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1194282: Warning: Identifier `\clknet_11_1742_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1194576: Warning: Identifier `\clknet_11_988_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1194618: Warning: Identifier `\clknet_11_989_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1194807: Warning: Identifier `\clknet_11_77_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1194856: Warning: Identifier `\clknet_11_1713_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1194870: Warning: Identifier `\clknet_11_1712_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1194891: Warning: Identifier `\clknet_11_1690_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1194968: Warning: Identifier `\clknet_11_1717_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1194982: Warning: Identifier `\clknet_11_1716_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1194996: Warning: Identifier `\clknet_11_1691_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1195010: Warning: Identifier `\clknet_11_1694_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1195024: Warning: Identifier `\clknet_11_1719_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1195031: Warning: Identifier `\clknet_11_1718_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1195192: Warning: Identifier `\clknet_11_1760_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1195220: Warning: Identifier `\clknet_11_1738_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1195227: Warning: Identifier `\clknet_11_1695_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1195304: Warning: Identifier `\clknet_11_972_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1195346: Warning: Identifier `\clknet_11_969_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1195360: Warning: Identifier `\clknet_11_985_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1195367: Warning: Identifier `\clknet_11_984_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1195402: Warning: Identifier `\clknet_11_978_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1195724: Warning: Identifier `\clknet_11_1679_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1195752: Warning: Identifier `\clknet_11_1701_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1195808: Warning: Identifier `\clknet_11_1498_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1195836: Warning: Identifier `\clknet_11_1408_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1195892: Warning: Identifier `\clknet_11_1413_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1195913: Warning: Identifier `\clknet_11_1499_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1195920: Warning: Identifier `\clknet_11_1424_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1196284: Warning: Identifier `\clknet_11_1678_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1196298: Warning: Identifier `\clknet_11_1697_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1196305: Warning: Identifier `\clknet_11_1699_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1196340: Warning: Identifier `\clknet_11_1675_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1196354: Warning: Identifier `\clknet_11_1696_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1196389: Warning: Identifier `\clknet_11_1674_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1196802: Warning: Identifier `\clknet_11_1700_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1196914: Warning: Identifier `\clknet_11_990_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1196970: Warning: Identifier `\clknet_11_991_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1197047: Warning: Identifier `\clknet_11_987_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1197138: Warning: Identifier `\clknet_11_1008_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1197180: Warning: Identifier `\clknet_11_986_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1197194: Warning: Identifier `\clknet_11_979_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1197250: Warning: Identifier `\clknet_11_1009_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1197404: Warning: Identifier `\clknet_11_997_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1197474: Warning: Identifier `\clknet_11_999_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1197558: Warning: Identifier `\clknet_11_996_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1197656: Warning: Identifier `\clknet_11_1013_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1197698: Warning: Identifier `\clknet_11_998_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1197761: Warning: Identifier `\clknet_11_971_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1197824: Warning: Identifier `\clknet_11_995_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1197831: Warning: Identifier `\clknet_11_993_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1197880: Warning: Identifier `\clknet_11_211_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1198083: Warning: Identifier `\clknet_11_970_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1198258: Warning: Identifier `\clknet_11_992_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1198300: Warning: Identifier `\clknet_11_949_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1198314: Warning: Identifier `\clknet_11_1012_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1198426: Warning: Identifier `\clknet_11_944_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1198433: Warning: Identifier `\clknet_11_935_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1198594: Warning: Identifier `\clknet_11_1714_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1198601: Warning: Identifier `\clknet_11_1703_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1198664: Warning: Identifier `\clknet_11_932_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1198706: Warning: Identifier `\clknet_11_1698_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1198762: Warning: Identifier `\clknet_11_934_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1198874: Warning: Identifier `\clknet_11_952_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1198888: Warning: Identifier `\clknet_11_946_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1198923: Warning: Identifier `\clknet_11_947_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1198958: Warning: Identifier `\clknet_11_975_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1198972: Warning: Identifier `\clknet_11_974_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1199098: Warning: Identifier `\clknet_11_953_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1199140: Warning: Identifier `\clknet_11_950_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1199238: Warning: Identifier `\clknet_11_956_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1199434: Warning: Identifier `\clknet_11_765_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1199455: Warning: Identifier `\clknet_11_936_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1199490: Warning: Identifier `\clknet_11_937_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1199511: Warning: Identifier `\clknet_11_940_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1199532: Warning: Identifier `\clknet_11_941_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1199602: Warning: Identifier `\clknet_11_764_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1199609: Warning: Identifier `\clknet_11_761_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1199672: Warning: Identifier `\clknet_11_759_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1199693: Warning: Identifier `\clknet_11_930_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1199735: Warning: Identifier `\clknet_11_758_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1199770: Warning: Identifier `\clknet_11_754_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1199784: Warning: Identifier `\clknet_11_755_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1199924: Warning: Identifier `\clknet_11_756_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1199973: Warning: Identifier `\clknet_11_753_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1200036: Warning: Identifier `\clknet_11_910_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1200099: Warning: Identifier `\clknet_11_757_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1200162: Warning: Identifier `\clknet_11_752_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1200344: Warning: Identifier `\clknet_11_719_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1200351: Warning: Identifier `\clknet_11_734_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1200372: Warning: Identifier `\clknet_11_735_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1200498: Warning: Identifier `\clknet_11_732_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1200519: Warning: Identifier `\clknet_11_733_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1200547: Warning: Identifier `\clknet_11_904_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1200617: Warning: Identifier `\clknet_11_928_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1200652: Warning: Identifier `\clknet_11_906_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1200666: Warning: Identifier `\clknet_11_730_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1200687: Warning: Identifier `\clknet_11_731_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1200715: Warning: Identifier `\clknet_11_898_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1200813: Warning: Identifier `\clknet_11_920_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1200883: Warning: Identifier `\clknet_11_909_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1201268: Warning: Identifier `\clknet_11_1111_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1202171: Warning: Identifier `\clknet_11_118_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1202220: Warning: Identifier `\clknet_11_116_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1202262: Warning: Identifier `\clknet_11_121_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1202367: Warning: Identifier `\clknet_11_114_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1202381: Warning: Identifier `\clknet_11_115_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1202500: Warning: Identifier `\clknet_11_102_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1202528: Warning: Identifier `\clknet_11_99_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1202661: Warning: Identifier `\clknet_11_110_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1202990: Warning: Identifier `\clknet_11_291_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1203095: Warning: Identifier `\clknet_11_147_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1203284: Warning: Identifier `\clknet_11_10_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1203312: Warning: Identifier `\clknet_11_8_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1203333: Warning: Identifier `\clknet_11_1_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1203438: Warning: Identifier `\clknet_11_73_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1203571: Warning: Identifier `\clknet_11_23_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1203606: Warning: Identifier `\clknet_11_87_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1203893: Warning: Identifier `\clknet_11_0_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1203984: Warning: Identifier `\clknet_11_28_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1204124: Warning: Identifier `\clknet_11_905_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1204173: Warning: Identifier `\clknet_11_907_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1204187: Warning: Identifier `\clknet_11_908_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1204376: Warning: Identifier `\clknet_11_899_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1204453: Warning: Identifier `\clknet_11_902_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1204600: Warning: Identifier `\clknet_11_964_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1204621: Warning: Identifier `\clknet_11_963_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1204628: Warning: Identifier `\clknet_11_961_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1204642: Warning: Identifier `\clknet_11_960_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1204677: Warning: Identifier `\clknet_11_903_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1204691: Warning: Identifier `\clknet_11_914_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1204754: Warning: Identifier `\clknet_11_962_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1205055: Warning: Identifier `\clknet_11_808_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1205237: Warning: Identifier `\clknet_11_366_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1205258: Warning: Identifier `\clknet_11_449_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1205307: Warning: Identifier `\clknet_11_448_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1205363: Warning: Identifier `\clknet_11_319_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1205377: Warning: Identifier `\clknet_11_318_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1205671: Warning: Identifier `\clknet_11_146_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1205713: Warning: Identifier `\clknet_11_135_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1205804: Warning: Identifier `\clknet_11_1129_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1205811: Warning: Identifier `\clknet_11_1131_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1205881: Warning: Identifier `\clknet_11_1133_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1205937: Warning: Identifier `\clknet_11_1130_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1206084: Warning: Identifier `\clknet_11_1216_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1206119: Warning: Identifier `\clknet_11_1523_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1206126: Warning: Identifier `\clknet_11_1522_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1206637: Warning: Identifier `\clknet_11_1117_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1206658: Warning: Identifier `\clknet_11_1119_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1207085: Warning: Identifier `\clknet_11_1116_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1207239: Warning: Identifier `\clknet_11_1107_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1207351: Warning: Identifier `\clknet_11_810_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1207358: Warning: Identifier `\clknet_11_897_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1207463: Warning: Identifier `\clknet_11_813_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1207470: Warning: Identifier `\clknet_11_812_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1207484: Warning: Identifier `\clknet_11_815_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1207540: Warning: Identifier `\clknet_11_823_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1207659: Warning: Identifier `\clknet_11_814_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1207694: Warning: Identifier `\clknet_11_806_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1207715: Warning: Identifier `\clknet_11_803_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1207778: Warning: Identifier `\clknet_11_821_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1207883: Warning: Identifier `\clknet_11_1118_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1207995: Warning: Identifier `\clknet_11_1137_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1208072: Warning: Identifier `\clknet_11_1513_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1208079: Warning: Identifier `\clknet_11_1512_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1208107: Warning: Identifier `\clknet_11_1429_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1208114: Warning: Identifier `\clknet_11_1428_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1208205: Warning: Identifier `\clknet_11_1409_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1208345: Warning: Identifier `\clknet_11_1136_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1208478: Warning: Identifier `\clknet_11_1127_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1208492: Warning: Identifier `\clknet_11_1126_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1208555: Warning: Identifier `\clknet_11_1123_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1208583: Warning: Identifier `\clknet_11_1122_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1208632: Warning: Identifier `\clknet_11_809_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1209178: Warning: Identifier `\clknet_11_1135_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1209325: Warning: Identifier `\clknet_11_1415_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1209332: Warning: Identifier `\clknet_11_1421_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1209339: Warning: Identifier `\clknet_11_1427_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1209346: Warning: Identifier `\clknet_11_1430_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1209360: Warning: Identifier `\clknet_11_1431_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1209374: Warning: Identifier `\clknet_11_1433_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1209381: Warning: Identifier `\clknet_11_1426_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1209388: Warning: Identifier `\clknet_11_1436_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1209409: Warning: Identifier `\clknet_11_1435_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1209423: Warning: Identifier `\clknet_11_1434_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1209430: Warning: Identifier `\clknet_11_1423_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1209451: Warning: Identifier `\clknet_11_1422_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1209465: Warning: Identifier `\clknet_11_1418_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1209500: Warning: Identifier `\clknet_11_1416_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1209521: Warning: Identifier `\clknet_11_1410_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1209535: Warning: Identifier `\clknet_11_1411_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1209619: Warning: Identifier `\clknet_11_1432_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1209703: Warning: Identifier `\clknet_11_1419_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1209808: Warning: Identifier `\clknet_11_1437_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1209927: Warning: Identifier `\clknet_11_1420_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1209941: Warning: Identifier `\clknet_11_1417_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1210011: Warning: Identifier `\clknet_11_158_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1210039: Warning: Identifier `\clknet_11_153_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1210214: Warning: Identifier `\clknet_11_155_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1210445: Warning: Identifier `\clknet_11_176_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1210578: Warning: Identifier `\clknet_11_202_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1210837: Warning: Identifier `\clknet_11_163_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1210851: Warning: Identifier `\clknet_11_169_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1210893: Warning: Identifier `\clknet_11_818_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1210900: Warning: Identifier `\clknet_11_819_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1210914: Warning: Identifier `\clknet_11_807_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1210921: Warning: Identifier `\clknet_11_805_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1210928: Warning: Identifier `\clknet_11_804_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1210942: Warning: Identifier `\clknet_11_783_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1211026: Warning: Identifier `\clknet_11_782_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1211061: Warning: Identifier `\clknet_11_780_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1211075: Warning: Identifier `\clknet_11_781_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1211082: Warning: Identifier `\clknet_11_777_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1211089: Warning: Identifier `\clknet_11_776_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1211110: Warning: Identifier `\clknet_11_605_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1211173: Warning: Identifier `\clknet_11_792_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1211229: Warning: Identifier `\clknet_11_775_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1211250: Warning: Identifier `\clknet_11_771_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1211271: Warning: Identifier `\clknet_11_599_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1211285: Warning: Identifier `\clknet_11_774_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1211327: Warning: Identifier `\clknet_11_770_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1211698: Warning: Identifier `\clknet_11_779_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1211789: Warning: Identifier `\clknet_11_772_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1211845: Warning: Identifier `\clknet_11_773_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1211852: Warning: Identifier `\clknet_11_786_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1211866: Warning: Identifier `\clknet_11_769_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1211957: Warning: Identifier `\clknet_11_784_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1212069: Warning: Identifier `\clknet_11_796_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1212090: Warning: Identifier `\clknet_11_793_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1212125: Warning: Identifier `\clknet_11_790_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1212146: Warning: Identifier `\clknet_11_787_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1212405: Warning: Identifier `\clknet_11_791_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1212629: Warning: Identifier `\clknet_11_447_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1212664: Warning: Identifier `\clknet_11_445_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1212685: Warning: Identifier `\clknet_11_431_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1212692: Warning: Identifier `\clknet_11_442_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1212727: Warning: Identifier `\clknet_11_429_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1212881: Warning: Identifier `\clknet_11_440_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1212909: Warning: Identifier `\clknet_11_443_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1213000: Warning: Identifier `\clknet_11_441_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1213077: Warning: Identifier `\clknet_11_446_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1213112: Warning: Identifier `\clknet_11_444_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1213301: Warning: Identifier `\clknet_11_491_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1213336: Warning: Identifier `\clknet_11_490_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1213525: Warning: Identifier `\clknet_11_511_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1213567: Warning: Identifier `\clknet_11_510_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1213588: Warning: Identifier `\clknet_11_1194_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1213602: Warning: Identifier `\clknet_11_1192_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1213749: Warning: Identifier `\clknet_11_506_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1213770: Warning: Identifier `\clknet_11_507_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1213980: Warning: Identifier `\clknet_11_1193_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1214029: Warning: Identifier `\clknet_11_1195_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1214092: Warning: Identifier `\clknet_11_1198_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1214106: Warning: Identifier `\clknet_11_1196_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1214127: Warning: Identifier `\clknet_11_1190_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1214197: Warning: Identifier `\clknet_11_1199_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1214218: Warning: Identifier `\clknet_11_1197_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1214309: Warning: Identifier `\clknet_11_1208_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1214351: Warning: Identifier `\clknet_11_1202_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1214365: Warning: Identifier `\clknet_11_1210_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1214421: Warning: Identifier `\clknet_11_1203_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1214463: Warning: Identifier `\clknet_11_1206_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1214526: Warning: Identifier `\clknet_11_1204_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1214589: Warning: Identifier `\clknet_11_1209_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1214631: Warning: Identifier `\clknet_11_1207_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1214673: Warning: Identifier `\clknet_11_1212_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1214687: Warning: Identifier `\clknet_11_1213_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1214869: Warning: Identifier `\clknet_11_1215_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1214890: Warning: Identifier `\clknet_11_1259_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1214911: Warning: Identifier `\clknet_11_1262_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1214946: Warning: Identifier `\clknet_11_1263_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1214967: Warning: Identifier `\clknet_11_1274_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1215002: Warning: Identifier `\clknet_11_1260_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1215016: Warning: Identifier `\clknet_11_1261_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1215023: Warning: Identifier `\clknet_11_1272_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1215030: Warning: Identifier `\clknet_11_1273_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1215205: Warning: Identifier `\clknet_11_1256_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1215212: Warning: Identifier `\clknet_11_1250_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1215226: Warning: Identifier `\clknet_11_1254_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1215254: Warning: Identifier `\clknet_11_1267_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1215289: Warning: Identifier `\clknet_11_1257_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1215450: Warning: Identifier `\clknet_11_1258_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1215597: Warning: Identifier `\clknet_11_1600_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1215604: Warning: Identifier `\clknet_11_1601_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1215688: Warning: Identifier `\clknet_11_1604_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1215765: Warning: Identifier `\clknet_11_1602_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1215786: Warning: Identifier `\clknet_11_1603_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1215800: Warning: Identifier `\clknet_11_1606_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1215814: Warning: Identifier `\clknet_11_1607_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1215989: Warning: Identifier `\clknet_11_1554_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1215996: Warning: Identifier `\clknet_11_1543_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1216031: Warning: Identifier `\clknet_11_1555_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1216045: Warning: Identifier `\clknet_11_1552_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1216052: Warning: Identifier `\clknet_11_1541_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1216087: Warning: Identifier `\clknet_11_1553_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1216311: Warning: Identifier `\clknet_11_1558_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1216332: Warning: Identifier `\clknet_11_1549_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1216416: Warning: Identifier `\clknet_11_1564_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1216437: Warning: Identifier `\clknet_11_1559_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1216528: Warning: Identifier `\clknet_11_1608_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1216829: Warning: Identifier `\clknet_11_1557_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1216843: Warning: Identifier `\clknet_11_1556_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1217109: Warning: Identifier `\clknet_11_839_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1217144: Warning: Identifier `\clknet_11_850_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1217158: Warning: Identifier `\clknet_11_851_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1217165: Warning: Identifier `\clknet_11_834_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1217172: Warning: Identifier `\clknet_11_835_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1217186: Warning: Identifier `\clknet_11_838_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1217242: Warning: Identifier `\clknet_11_837_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1217256: Warning: Identifier `\clknet_11_848_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1217263: Warning: Identifier `\clknet_11_849_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1217333: Warning: Identifier `\clknet_11_1536_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1217340: Warning: Identifier `\clknet_11_855_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1217368: Warning: Identifier `\clknet_11_1537_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1217403: Warning: Identifier `\clknet_11_1538_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1217438: Warning: Identifier `\clknet_11_1539_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1217648: Warning: Identifier `\clknet_11_1545_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1217669: Warning: Identifier `\clknet_11_797_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1217949: Warning: Identifier `\clknet_11_580_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1217991: Warning: Identifier `\clknet_11_582_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1218005: Warning: Identifier `\clknet_11_577_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1218026: Warning: Identifier `\clknet_11_234_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1218117: Warning: Identifier `\clknet_11_576_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1218215: Warning: Identifier `\clknet_11_533_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1218285: Warning: Identifier `\clknet_11_578_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1218292: Warning: Identifier `\clknet_11_579_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1218327: Warning: Identifier `\clknet_11_532_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1218467: Warning: Identifier `\clknet_11_535_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1218481: Warning: Identifier `\clknet_11_534_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1218901: Warning: Identifier `\clknet_11_559_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1218915: Warning: Identifier `\clknet_11_570_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1219006: Warning: Identifier `\clknet_11_568_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1219069: Warning: Identifier `\clknet_11_558_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1219146: Warning: Identifier `\clknet_11_554_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1219188: Warning: Identifier `\clknet_11_555_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1219230: Warning: Identifier `\clknet_11_552_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1219391: Warning: Identifier `\clknet_11_553_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1219405: Warning: Identifier `\clknet_11_556_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1219804: Warning: Identifier `\clknet_11_640_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1219860: Warning: Identifier `\clknet_11_641_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1219972: Warning: Identifier `\clknet_11_642_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1220028: Warning: Identifier `\clknet_11_643_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1220301: Warning: Identifier `\clknet_11_644_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1220308: Warning: Identifier `\clknet_11_646_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1220469: Warning: Identifier `\clknet_11_665_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1220490: Warning: Identifier `\clknet_11_649_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1220525: Warning: Identifier `\clknet_11_666_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1220539: Warning: Identifier `\clknet_11_653_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1220546: Warning: Identifier `\clknet_11_650_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1220553: Warning: Identifier `\clknet_11_647_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1220581: Warning: Identifier `\clknet_11_664_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1220616: Warning: Identifier `\clknet_11_645_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1220693: Warning: Identifier `\clknet_11_667_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1220707: Warning: Identifier `\clknet_11_688_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1220742: Warning: Identifier `\clknet_11_651_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1220777: Warning: Identifier `\clknet_11_655_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1220791: Warning: Identifier `\clknet_11_652_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1220840: Warning: Identifier `\clknet_11_654_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1220861: Warning: Identifier `\clknet_11_677_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1221029: Warning: Identifier `\clknet_11_659_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1221064: Warning: Identifier `\clknet_11_648_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1221141: Warning: Identifier `\clknet_11_656_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1221183: Warning: Identifier `\clknet_11_658_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1221309: Warning: Identifier `\clknet_11_670_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1221330: Warning: Identifier `\clknet_11_668_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1221414: Warning: Identifier `\clknet_11_669_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1221477: Warning: Identifier `\clknet_11_671_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1221589: Warning: Identifier `\clknet_11_1666_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1221596: Warning: Identifier `\clknet_11_1667_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1221624: Warning: Identifier `\clknet_11_1665_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1221645: Warning: Identifier `\clknet_11_1728_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1221652: Warning: Identifier `\clknet_11_1730_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1221708: Warning: Identifier `\clknet_11_1731_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1221729: Warning: Identifier `\clknet_11_1729_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1221750: Warning: Identifier `\clknet_11_1599_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1221813: Warning: Identifier `\clknet_11_1687_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1221834: Warning: Identifier `\clknet_11_1685_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1221925: Warning: Identifier `\clknet_11_1686_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1221946: Warning: Identifier `\clknet_11_1684_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1222044: Warning: Identifier `\clknet_11_1683_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1222093: Warning: Identifier `\clknet_11_1681_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1222177: Warning: Identifier `\clknet_11_1670_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1222184: Warning: Identifier `\clknet_11_1668_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1222205: Warning: Identifier `\clknet_11_1671_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1222226: Warning: Identifier `\clknet_11_1669_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1222233: Warning: Identifier `\clknet_11_1680_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1222485: Warning: Identifier `\clknet_11_1664_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1222597: Warning: Identifier `\clknet_11_895_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1222604: Warning: Identifier `\clknet_11_981_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1222709: Warning: Identifier `\clknet_11_893_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1222786: Warning: Identifier `\clknet_11_1579_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1222842: Warning: Identifier `\clknet_11_1578_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1222954: Warning: Identifier `\clknet_11_1582_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1223010: Warning: Identifier `\clknet_11_1583_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1223045: Warning: Identifier `\clknet_11_1594_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1223157: Warning: Identifier `\clknet_11_1598_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1223178: Warning: Identifier `\clknet_11_1595_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1223381: Warning: Identifier `\clknet_11_1596_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1223423: Warning: Identifier `\clknet_11_1640_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1223479: Warning: Identifier `\clknet_11_1597_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1223591: Warning: Identifier `\clknet_11_1641_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1223738: Warning: Identifier `\clknet_11_1634_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1223759: Warning: Identifier `\clknet_11_1635_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1223836: Warning: Identifier `\clknet_11_1745_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1223857: Warning: Identifier `\clknet_11_1658_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1223885: Warning: Identifier `\clknet_11_1642_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1223906: Warning: Identifier `\clknet_11_1643_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1223920: Warning: Identifier `\clknet_11_1646_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1223934: Warning: Identifier `\clknet_11_1644_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1224039: Warning: Identifier `\clknet_11_1647_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1224277: Warning: Identifier `\clknet_11_1732_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1224431: Warning: Identifier `\clknet_11_1659_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1224648: Warning: Identifier `\clknet_11_1663_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1224662: Warning: Identifier `\clknet_11_1832_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1224753: Warning: Identifier `\clknet_11_1821_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1224879: Warning: Identifier `\clknet_11_1856_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1224886: Warning: Identifier `\clknet_11_1857_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1224949: Warning: Identifier `\clknet_11_1869_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1225215: Warning: Identifier `\clknet_11_1905_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1225236: Warning: Identifier `\clknet_11_1904_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1225397: Warning: Identifier `\clknet_11_1906_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1225425: Warning: Identifier `\clknet_11_1907_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1225565: Warning: Identifier `\clknet_11_1912_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1225621: Warning: Identifier `\clknet_11_1989_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1225635: Warning: Identifier `\clknet_11_2000_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1225649: Warning: Identifier `\clknet_11_2001_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1225670: Warning: Identifier `\clknet_11_1914_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1225789: Warning: Identifier `\clknet_11_1996_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1225803: Warning: Identifier `\clknet_11_1997_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1225810: Warning: Identifier `\clknet_11_2002_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1225845: Warning: Identifier `\clknet_11_1999_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1225852: Warning: Identifier `\clknet_11_1998_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1225880: Warning: Identifier `\clknet_11_2010_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1226083: Warning: Identifier `\clknet_11_1990_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1226090: Warning: Identifier `\clknet_11_1991_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1226426: Warning: Identifier `\clknet_11_1988_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1226454: Warning: Identifier `\clknet_11_1903_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1227098: Warning: Identifier `\clknet_11_2003_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1227126: Warning: Identifier `\clknet_11_2006_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1227259: Warning: Identifier `\clknet_11_2011_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1227308: Warning: Identifier `\clknet_11_2008_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1227322: Warning: Identifier `\clknet_11_2009_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1227469: Warning: Identifier `\clknet_11_2032_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1227511: Warning: Identifier `\clknet_11_2033_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1227581: Warning: Identifier `\clknet_11_2034_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1227623: Warning: Identifier `\clknet_11_2035_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1227679: Warning: Identifier `\clknet_11_2041_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1227707: Warning: Identifier `\clknet_11_2040_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1227749: Warning: Identifier `\clknet_11_2021_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1227861: Warning: Identifier `\clknet_11_2030_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1227889: Warning: Identifier `\clknet_11_2031_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1228015: Warning: Identifier `\clknet_11_2042_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1228092: Warning: Identifier `\clknet_11_2029_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1228225: Warning: Identifier `\clknet_11_2043_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1228365: Warning: Identifier `\clknet_11_2020_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1228386: Warning: Identifier `\clknet_11_2022_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1228393: Warning: Identifier `\clknet_11_2023_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1228757: Warning: Identifier `\clknet_11_1957_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1228764: Warning: Identifier `\clknet_11_1968_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1228925: Warning: Identifier `\clknet_11_1970_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1228981: Warning: Identifier `\clknet_11_1956_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1229002: Warning: Identifier `\clknet_11_1958_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1229093: Warning: Identifier `\clknet_11_1953_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1229114: Warning: Identifier `\clknet_11_1955_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1229149: Warning: Identifier `\clknet_11_1961_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1229170: Warning: Identifier `\clknet_11_1964_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1229205: Warning: Identifier `\clknet_11_1965_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1229226: Warning: Identifier `\clknet_11_1967_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1229247: Warning: Identifier `\clknet_11_1966_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1229317: Warning: Identifier `\clknet_11_1978_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1229429: Warning: Identifier `\clknet_11_1959_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1229485: Warning: Identifier `\clknet_11_1976_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1229709: Warning: Identifier `\clknet_11_1977_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1229765: Warning: Identifier `\clknet_11_1979_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1229989: Warning: Identifier `\clknet_11_1783_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1230101: Warning: Identifier `\clknet_11_1779_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1230122: Warning: Identifier `\clknet_11_1778_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1230143: Warning: Identifier `\clknet_11_1784_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1230255: Warning: Identifier `\clknet_11_1785_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1230346: Warning: Identifier `\clknet_11_1782_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1230374: Warning: Identifier `\clknet_11_1788_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1230605: Warning: Identifier `\clknet_11_1702_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1230633: Warning: Identifier `\clknet_11_1708_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1230661: Warning: Identifier `\clknet_11_1715_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1230703: Warning: Identifier `\clknet_11_1721_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1230773: Warning: Identifier `\clknet_11_1762_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1230808: Warning: Identifier `\clknet_11_1768_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1230920: Warning: Identifier `\clknet_11_1769_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1230997: Warning: Identifier `\clknet_11_1767_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1231200: Warning: Identifier `\clknet_11_1773_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1231221: Warning: Identifier `\clknet_11_1766_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1231319: Warning: Identifier `\clknet_11_1772_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1231480: Warning: Identifier `\clknet_11_1724_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1231592: Warning: Identifier `\clknet_11_1725_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1231711: Warning: Identifier `\clknet_11_1014_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1231718: Warning: Identifier `\clknet_11_1011_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1231746: Warning: Identifier `\clknet_11_1709_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1231921: Warning: Identifier `\clknet_11_1704_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1231970: Warning: Identifier `\clknet_11_1015_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1232054: Warning: Identifier `\clknet_11_1021_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1232341: Warning: Identifier `\clknet_11_1010_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1232376: Warning: Identifier `\clknet_11_1017_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1232432: Warning: Identifier `\clknet_11_1016_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1232537: Warning: Identifier `\clknet_11_1005_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1232593: Warning: Identifier `\clknet_11_1004_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1232789: Warning: Identifier `\clknet_11_994_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1232810: Warning: Identifier `\clknet_11_1000_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1232873: Warning: Identifier `\clknet_11_1001_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1233069: Warning: Identifier `\clknet_11_957_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1233181: Warning: Identifier `\clknet_11_951_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1233265: Warning: Identifier `\clknet_11_766_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1233335: Warning: Identifier `\clknet_11_763_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1233391: Warning: Identifier `\clknet_11_939_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1233398: Warning: Identifier `\clknet_11_938_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1233503: Warning: Identifier `\clknet_11_767_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1233909: Warning: Identifier `\clknet_11_760_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1234028: Warning: Identifier `\clknet_11_762_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1234161: Warning: Identifier `\clknet_11_749_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1234168: Warning: Identifier `\clknet_11_748_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1234294: Warning: Identifier `\clknet_11_747_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1234343: Warning: Identifier `\clknet_11_745_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1234413: Warning: Identifier `\clknet_11_743_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1234427: Warning: Identifier `\clknet_11_742_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1234511: Warning: Identifier `\clknet_11_739_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1234623: Warning: Identifier `\clknet_11_738_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1234637: Warning: Identifier `\clknet_11_741_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1234700: Warning: Identifier `\clknet_11_740_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1234714: Warning: Identifier `\clknet_11_737_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1234791: Warning: Identifier `\clknet_11_736_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1234805: Warning: Identifier `\clknet_11_713_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1234812: Warning: Identifier `\clknet_11_712_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1234826: Warning: Identifier `\clknet_11_693_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1234840: Warning: Identifier `\clknet_11_695_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1234847: Warning: Identifier `\clknet_11_694_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1234882: Warning: Identifier `\clknet_11_714_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1234917: Warning: Identifier `\clknet_11_715_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1235001: Warning: Identifier `\clknet_11_692_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1235029: Warning: Identifier `\clknet_11_706_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1235309: Warning: Identifier `\clknet_11_716_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1235330: Warning: Identifier `\clknet_11_718_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1235372: Warning: Identifier `\clknet_11_717_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1235589: Warning: Identifier `\clknet_11_728_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1235610: Warning: Identifier `\clknet_11_711_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1235624: Warning: Identifier `\clknet_11_710_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1235631: Warning: Identifier `\clknet_11_707_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1235869: Warning: Identifier `\clknet_11_976_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1235883: Warning: Identifier `\clknet_11_965_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1235925: Warning: Identifier `\clknet_11_980_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1235953: Warning: Identifier `\clknet_11_982_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1236037: Warning: Identifier `\clknet_11_977_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1236149: Warning: Identifier `\clknet_11_826_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1236205: Warning: Identifier `\clknet_11_830_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1236226: Warning: Identifier `\clknet_11_827_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1236240: Warning: Identifier `\clknet_11_825_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1236373: Warning: Identifier `\clknet_11_824_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1236429: Warning: Identifier `\clknet_11_817_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1236471: Warning: Identifier `\clknet_11_816_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1236485: Warning: Identifier `\clknet_11_820_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1236821: Warning: Identifier `\clknet_11_788_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1237101: Warning: Identifier `\clknet_11_1214_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1237234: Warning: Identifier `\clknet_11_1540_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1237283: Warning: Identifier `\clknet_11_845_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1237773: Warning: Identifier `\clknet_11_874_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1237794: Warning: Identifier `\clknet_11_875_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1237808: Warning: Identifier `\clknet_11_878_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1238508: Warning: Identifier `\clknet_11_1971_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1238704: Warning: Identifier `\clknet_11_1705_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1238746: Warning: Identifier `\clknet_11_1720_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1239257: Warning: Identifier `\clknet_11_828_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1239285: Warning: Identifier `\clknet_11_822_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1239397: Warning: Identifier `\clknet_11_894_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1239509: Warning: Identifier `\clknet_11_484_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1239516: Warning: Identifier `\clknet_11_485_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1239523: Warning: Identifier `\clknet_11_496_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1239537: Warning: Identifier `\clknet_11_497_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1239586: Warning: Identifier `\clknet_11_801_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1239614: Warning: Identifier `\clknet_11_800_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1239677: Warning: Identifier `\clknet_11_768_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1239698: Warning: Identifier `\clknet_11_597_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1239712: Warning: Identifier `\clknet_11_596_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1239719: Warning: Identifier `\clknet_11_426_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1239789: Warning: Identifier `\clknet_11_427_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1239866: Warning: Identifier `\clknet_11_424_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1239957: Warning: Identifier `\clknet_11_421_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1239964: Warning: Identifier `\clknet_11_394_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1239978: Warning: Identifier `\clknet_11_393_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1239985: Warning: Identifier `\clknet_11_420_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1239992: Warning: Identifier `\clknet_11_417_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1239999: Warning: Identifier `\clknet_11_416_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1240020: Warning: Identifier `\clknet_11_395_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1240181: Warning: Identifier `\clknet_11_422_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1240188: Warning: Identifier `\clknet_11_423_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1240496: Warning: Identifier `\clknet_11_425_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1240524: Warning: Identifier `\clknet_11_430_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1240650: Warning: Identifier `\clknet_11_428_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1240818: Warning: Identifier `\clknet_11_419_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1240881: Warning: Identifier `\clknet_11_418_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1240902: Warning: Identifier `\clknet_11_247_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1241014: Warning: Identifier `\clknet_11_253_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1241357: Warning: Identifier `\clknet_11_398_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1241371: Warning: Identifier `\clknet_11_399_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1241378: Warning: Identifier `\clknet_11_397_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1241469: Warning: Identifier `\clknet_11_411_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1241476: Warning: Identifier `\clknet_11_410_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1241511: Warning: Identifier `\clknet_11_408_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1241637: Warning: Identifier `\clknet_11_432_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1241644: Warning: Identifier `\clknet_11_435_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1241651: Warning: Identifier `\clknet_11_409_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1241770: Warning: Identifier `\clknet_11_414_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1241784: Warning: Identifier `\clknet_11_436_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1241861: Warning: Identifier `\clknet_11_438_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1241917: Warning: Identifier `\clknet_11_439_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1241931: Warning: Identifier `\clknet_11_437_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1241973: Warning: Identifier `\clknet_11_483_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1242008: Warning: Identifier `\clknet_11_486_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1242015: Warning: Identifier `\clknet_11_487_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1242029: Warning: Identifier `\clknet_11_488_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1242078: Warning: Identifier `\clknet_11_489_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1242106: Warning: Identifier `\clknet_11_482_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1242197: Warning: Identifier `\clknet_11_1186_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1242204: Warning: Identifier `\clknet_11_1184_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1242232: Warning: Identifier `\clknet_11_1163_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1242260: Warning: Identifier `\clknet_11_1185_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1242330: Warning: Identifier `\clknet_11_503_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1242351: Warning: Identifier `\clknet_11_1162_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1242372: Warning: Identifier `\clknet_11_509_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1242477: Warning: Identifier `\clknet_11_505_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1242484: Warning: Identifier `\clknet_11_504_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1242498: Warning: Identifier `\clknet_11_499_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1242547: Warning: Identifier `\clknet_11_508_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1242554: Warning: Identifier `\clknet_11_502_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1242666: Warning: Identifier `\clknet_11_1166_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1242708: Warning: Identifier `\clknet_11_1188_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1242778: Warning: Identifier `\clknet_11_1167_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1242813: Warning: Identifier `\clknet_11_1189_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1242869: Warning: Identifier `\clknet_11_1200_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1243037: Warning: Identifier `\clknet_11_1201_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1243107: Warning: Identifier `\clknet_11_1205_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1243170: Warning: Identifier `\clknet_11_1248_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1243198: Warning: Identifier `\clknet_11_1251_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1243226: Warning: Identifier `\clknet_11_1249_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1243338: Warning: Identifier `\clknet_11_1268_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1243359: Warning: Identifier `\clknet_11_1265_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1243429: Warning: Identifier `\clknet_11_1266_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1243534: Warning: Identifier `\clknet_11_1264_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1243555: Warning: Identifier `\clknet_11_1270_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1243576: Warning: Identifier `\clknet_11_1269_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1243597: Warning: Identifier `\clknet_11_1276_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1243618: Warning: Identifier `\clknet_11_1277_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1243639: Warning: Identifier `\clknet_11_1442_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1243653: Warning: Identifier `\clknet_11_1444_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1243667: Warning: Identifier `\clknet_11_1445_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1243674: Warning: Identifier `\clknet_11_1446_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1243688: Warning: Identifier `\clknet_11_1447_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1243695: Warning: Identifier `\clknet_11_1464_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1243702: Warning: Identifier `\clknet_11_1453_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1243709: Warning: Identifier `\clknet_11_1443_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1243779: Warning: Identifier `\clknet_11_1271_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1243800: Warning: Identifier `\clknet_11_1440_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1243807: Warning: Identifier `\clknet_11_1441_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1244017: Warning: Identifier `\clknet_11_1456_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1244031: Warning: Identifier `\clknet_11_1465_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1244157: Warning: Identifier `\clknet_11_1466_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1244178: Warning: Identifier `\clknet_11_1467_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1244213: Warning: Identifier `\clknet_11_1457_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1244234: Warning: Identifier `\clknet_11_1468_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1244248: Warning: Identifier `\clknet_11_1461_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1244255: Warning: Identifier `\clknet_11_1460_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1244262: Warning: Identifier `\clknet_11_1470_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1244290: Warning: Identifier `\clknet_11_1469_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1244318: Warning: Identifier `\clknet_11_1471_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1244437: Warning: Identifier `\clknet_11_1809_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1244444: Warning: Identifier `\clknet_11_1812_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1244458: Warning: Identifier `\clknet_11_1860_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1244479: Warning: Identifier `\clknet_11_1861_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1244500: Warning: Identifier `\clknet_11_1813_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1244535: Warning: Identifier `\clknet_11_1872_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1244556: Warning: Identifier `\clknet_11_1463_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1244661: Warning: Identifier `\clknet_11_1808_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1244717: Warning: Identifier `\clknet_11_1796_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1244724: Warning: Identifier `\clknet_11_1454_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1244738: Warning: Identifier `\clknet_11_1797_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1244745: Warning: Identifier `\clknet_11_1458_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1244913: Warning: Identifier `\clknet_11_1799_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1244934: Warning: Identifier `\clknet_11_1810_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1244997: Warning: Identifier `\clknet_11_1794_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1245011: Warning: Identifier `\clknet_11_1795_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1245018: Warning: Identifier `\clknet_11_1798_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1245109: Warning: Identifier `\clknet_11_1792_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1245221: Warning: Identifier `\clknet_11_1793_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1245382: Warning: Identifier `\clknet_11_1815_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1245557: Warning: Identifier `\clknet_11_1619_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1245564: Warning: Identifier `\clknet_11_1622_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1245578: Warning: Identifier `\clknet_11_1623_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1245620: Warning: Identifier `\clknet_11_1617_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1245669: Warning: Identifier `\clknet_11_1618_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1245732: Warning: Identifier `\clknet_11_1616_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1245879: Warning: Identifier `\clknet_11_860_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1245900: Warning: Identifier `\clknet_11_854_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1246005: Warning: Identifier `\clknet_11_1542_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1246229: Warning: Identifier `\clknet_11_1544_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1246677: Warning: Identifier `\clknet_11_191_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1246803: Warning: Identifier `\clknet_11_190_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1246810: Warning: Identifier `\clknet_11_528_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1246817: Warning: Identifier `\clknet_11_529_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1246957: Warning: Identifier `\clknet_11_512_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1246978: Warning: Identifier `\clknet_11_514_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1247013: Warning: Identifier `\clknet_11_513_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1247041: Warning: Identifier `\clknet_11_515_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1247062: Warning: Identifier `\clknet_11_518_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1247160: Warning: Identifier `\clknet_11_516_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1247356: Warning: Identifier `\clknet_11_517_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1247629: Warning: Identifier `\clknet_11_521_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1247797: Warning: Identifier `\clknet_11_544_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1247811: Warning: Identifier `\clknet_11_546_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1247902: Warning: Identifier `\clknet_11_545_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1248077: Warning: Identifier `\clknet_11_522_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1248133: Warning: Identifier `\clknet_11_523_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1248469: Warning: Identifier `\clknet_11_547_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1248917: Warning: Identifier `\clknet_11_557_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1249218: Warning: Identifier `\clknet_11_571_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1249386: Warning: Identifier `\clknet_11_574_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1249400: Warning: Identifier `\clknet_11_575_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1249939: Warning: Identifier `\clknet_11_657_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1250037: Warning: Identifier `\clknet_11_663_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1250044: Warning: Identifier `\clknet_11_662_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1250072: Warning: Identifier `\clknet_11_660_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1250408: Warning: Identifier `\clknet_11_1590_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1250485: Warning: Identifier `\clknet_11_1593_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1250506: Warning: Identifier `\clknet_11_1587_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1250695: Warning: Identifier `\clknet_11_1586_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1250730: Warning: Identifier `\clknet_11_1592_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1250877: Warning: Identifier `\clknet_11_1581_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1250989: Warning: Identifier `\clknet_11_1580_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1251241: Warning: Identifier `\clknet_11_887_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1251297: Warning: Identifier `\clknet_11_884_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1251381: Warning: Identifier `\clknet_11_886_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1252130: Warning: Identifier `\clknet_11_1638_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1252277: Warning: Identifier `\clknet_11_1639_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1252298: Warning: Identifier `\clknet_11_1654_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1252501: Warning: Identifier `\clknet_11_1655_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1252578: Warning: Identifier `\clknet_11_1650_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1252634: Warning: Identifier `\clknet_11_1651_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1252949: Warning: Identifier `\clknet_11_1827_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1253061: Warning: Identifier `\clknet_11_1826_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1253138: Warning: Identifier `\clknet_11_1831_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1253173: Warning: Identifier `\clknet_11_1830_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1253299: Warning: Identifier `\clknet_11_1840_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1253404: Warning: Identifier `\clknet_11_1873_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1253411: Warning: Identifier `\clknet_11_1875_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1253593: Warning: Identifier `\clknet_11_1877_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1253852: Warning: Identifier `\clknet_11_1908_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1253978: Warning: Identifier `\clknet_11_1909_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1254041: Warning: Identifier `\clknet_11_1911_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1254069: Warning: Identifier `\clknet_11_1910_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1254237: Warning: Identifier `\clknet_11_1917_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1254251: Warning: Identifier `\clknet_11_1916_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1254293: Warning: Identifier `\clknet_11_1919_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1254356: Warning: Identifier `\clknet_11_1918_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1254517: Warning: Identifier `\clknet_11_2004_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1254559: Warning: Identifier `\clknet_11_2005_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1254776: Warning: Identifier `\clknet_11_1915_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1254853: Warning: Identifier `\clknet_11_2007_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1255357: Warning: Identifier `\clknet_11_1913_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1255917: Warning: Identifier `\clknet_11_2014_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1255924: Warning: Identifier `\clknet_11_2015_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1255973: Warning: Identifier `\clknet_11_2012_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1255980: Warning: Identifier `\clknet_11_2013_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1256183: Warning: Identifier `\clknet_11_2037_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1256197: Warning: Identifier `\clknet_11_2036_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1256309: Warning: Identifier `\clknet_11_2038_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1256330: Warning: Identifier `\clknet_11_2039_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1256533: Warning: Identifier `\clknet_11_2046_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1256540: Warning: Identifier `\clknet_11_2047_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1256554: Warning: Identifier `\clknet_11_2044_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1256757: Warning: Identifier `\clknet_11_2045_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1257541: Warning: Identifier `\clknet_11_1751_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1257548: Warning: Identifier `\clknet_11_1750_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1257674: Warning: Identifier `\clknet_11_1954_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1257772: Warning: Identifier `\clknet_11_1960_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1257912: Warning: Identifier `\clknet_11_1789_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1257996: Warning: Identifier `\clknet_11_1962_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1258073: Warning: Identifier `\clknet_11_1791_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1258248: Warning: Identifier `\clknet_11_1963_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1258486: Warning: Identifier `\clknet_11_1790_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1258738: Warning: Identifier `\clknet_11_1787_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1258794: Warning: Identifier `\clknet_11_1786_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1258815: Warning: Identifier `\clknet_11_1775_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1259018: Warning: Identifier `\clknet_11_1726_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1259130: Warning: Identifier `\clknet_11_1727_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1259186: Warning: Identifier `\clknet_11_1770_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1259242: Warning: Identifier `\clknet_11_1020_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1259277: Warning: Identifier `\clknet_11_1723_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1259354: Warning: Identifier `\clknet_11_1722_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1259578: Warning: Identifier `\clknet_11_1771_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1259704: Warning: Identifier `\clknet_11_1774_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1260250: Warning: Identifier `\clknet_11_1710_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1260299: Warning: Identifier `\clknet_11_1711_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1260432: Warning: Identifier `\clknet_11_1707_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1260565: Warning: Identifier `\clknet_11_1023_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1260586: Warning: Identifier `\clknet_11_1706_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1260789: Warning: Identifier `\clknet_11_1022_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1260957: Warning: Identifier `\clknet_11_1019_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1261013: Warning: Identifier `\clknet_11_1018_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1261237: Warning: Identifier `\clknet_11_1006_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1261258: Warning: Identifier `\clknet_11_1007_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1261524: Warning: Identifier `\clknet_11_1003_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1261538: Warning: Identifier `\clknet_11_1002_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1261706: Warning: Identifier `\clknet_11_959_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1261797: Warning: Identifier `\clknet_11_958_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1261909: Warning: Identifier `\clknet_11_942_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1261923: Warning: Identifier `\clknet_11_943_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1261930: Warning: Identifier `\clknet_11_954_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1261944: Warning: Identifier `\clknet_11_955_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1262637: Warning: Identifier `\clknet_11_751_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1262658: Warning: Identifier `\clknet_11_750_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1262833: Warning: Identifier `\clknet_11_699_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1262840: Warning: Identifier `\clknet_11_746_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1262980: Warning: Identifier `\clknet_11_744_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1262994: Warning: Identifier `\clknet_11_698_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1263197: Warning: Identifier `\clknet_11_697_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1263218: Warning: Identifier `\clknet_11_686_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1263253: Warning: Identifier `\clknet_11_696_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1263260: Warning: Identifier `\clknet_11_685_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1263274: Warning: Identifier `\clknet_11_687_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1263288: Warning: Identifier `\clknet_11_684_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1263393: Warning: Identifier `\clknet_11_683_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1263407: Warning: Identifier `\clknet_11_682_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1263421: Warning: Identifier `\clknet_11_702_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1263428: Warning: Identifier `\clknet_11_681_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1263442: Warning: Identifier `\clknet_11_680_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1263477: Warning: Identifier `\clknet_11_679_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1263498: Warning: Identifier `\clknet_11_672_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1263519: Warning: Identifier `\clknet_11_673_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1263603: Warning: Identifier `\clknet_11_678_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1263645: Warning: Identifier `\clknet_11_676_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1263708: Warning: Identifier `\clknet_11_689_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1263757: Warning: Identifier `\clknet_11_700_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1263813: Warning: Identifier `\clknet_11_675_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1263834: Warning: Identifier `\clknet_11_674_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1264058: Warning: Identifier `\clknet_11_703_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1264100: Warning: Identifier `\clknet_11_701_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1264317: Warning: Identifier `\clknet_11_691_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1264408: Warning: Identifier `\clknet_11_690_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1264618: Warning: Identifier `\clknet_11_891_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1264625: Warning: Identifier `\clknet_11_890_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1264786: Warning: Identifier `\clknet_11_879_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1264842: Warning: Identifier `\clknet_11_831_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1265829: Warning: Identifier `\clknet_11_1452_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1265885: Warning: Identifier `\clknet_11_1451_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1265906: Warning: Identifier `\clknet_11_1455_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1266053: Warning: Identifier `\clknet_11_861_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1267901: Warning: Identifier `\clknet_11_913_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1268314: Warning: Identifier `\clknet_11_631_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1268440: Warning: Identifier `\clknet_11_255_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1268482: Warning: Identifier `\clknet_11_252_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1268503: Warning: Identifier `\clknet_11_254_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1268615: Warning: Identifier `\clknet_11_249_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1268657: Warning: Identifier `\clknet_11_246_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1268853: Warning: Identifier `\clknet_11_604_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1268965: Warning: Identifier `\clknet_11_595_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1269154: Warning: Identifier `\clknet_11_248_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1269182: Warning: Identifier `\clknet_11_250_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1269210: Warning: Identifier `\clknet_11_236_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1269238: Warning: Identifier `\clknet_11_238_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1269245: Warning: Identifier `\clknet_11_237_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1269294: Warning: Identifier `\clknet_11_239_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1269322: Warning: Identifier `\clknet_11_233_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1269525: Warning: Identifier `\clknet_11_242_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1269532: Warning: Identifier `\clknet_11_231_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1269693: Warning: Identifier `\clknet_11_243_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1269973: Warning: Identifier `\clknet_11_434_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1270309: Warning: Identifier `\clknet_11_433_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1271387: Warning: Identifier `\clknet_11_1187_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1271541: Warning: Identifier `\clknet_11_1191_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1271933: Warning: Identifier `\clknet_11_1252_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1272031: Warning: Identifier `\clknet_11_1255_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1272045: Warning: Identifier `\clknet_11_1253_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1272213: Warning: Identifier `\clknet_11_1450_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1272248: Warning: Identifier `\clknet_11_1279_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1272325: Warning: Identifier `\clknet_11_1449_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1272437: Warning: Identifier `\clknet_11_1448_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1272920: Warning: Identifier `\clknet_11_1462_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1272927: Warning: Identifier `\clknet_11_1459_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1273130: Warning: Identifier `\clknet_11_1814_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1273144: Warning: Identifier `\clknet_11_1811_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1273452: Warning: Identifier `\clknet_11_1805_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1273473: Warning: Identifier `\clknet_11_1804_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1273564: Warning: Identifier `\clknet_11_1801_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1273578: Warning: Identifier `\clknet_11_1800_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1274005: Warning: Identifier `\clknet_11_165_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1274040: Warning: Identifier `\clknet_11_164_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1274845: Warning: Identifier `\clknet_11_1290_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1274852: Warning: Identifier `\clknet_11_1288_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1274859: Warning: Identifier `\clknet_11_1281_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1274873: Warning: Identifier `\clknet_11_1284_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1274880: Warning: Identifier `\clknet_opt_3_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1274887: Warning: Identifier `\clknet_11_1346_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1274894: Warning: Identifier `\clknet_11_1349_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1274908: Warning: Identifier `\clknet_11_1360_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1274922: Warning: Identifier `\clknet_11_1361_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1274929: Warning: Identifier `\clknet_11_1364_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1274936: Warning: Identifier `\clknet_11_1367_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1274950: Warning: Identifier `\clknet_11_1366_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1274957: Warning: Identifier `\clknet_11_1372_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1274964: Warning: Identifier `\clknet_11_1396_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1274999: Warning: Identifier `\clknet_11_1380_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1275034: Warning: Identifier `\clknet_11_1308_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1275041: Warning: Identifier `\clknet_11_1304_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1275055: Warning: Identifier `\clknet_11_1305_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1275083: Warning: Identifier `\clknet_11_1425_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1275230: Warning: Identifier `\clknet_11_1247_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1275349: Warning: Identifier `\clknet_11_293_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1275363: Warning: Identifier `\clknet_11_282_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1275370: Warning: Identifier `\clknet_11_271_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1275405: Warning: Identifier `\clknet_11_304_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1275426: Warning: Identifier `\clknet_11_305_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1275454: Warning: Identifier `\clknet_11_308_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1275461: Warning: Identifier `\clknet_11_326_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1275475: Warning: Identifier `\clknet_11_332_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1275573: Warning: Identifier `\clknet_11_360_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1275594: Warning: Identifier `\clknet_11_317_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1275601: Warning: Identifier `\clknet_11_311_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1275615: Warning: Identifier `\clknet_11_316_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1275643: Warning: Identifier `\clknet_11_347_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1275853: Warning: Identifier `\clknet_11_1175_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1275860: Warning: Identifier `\clknet_11_1226_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1275881: Warning: Identifier `\clknet_11_1218_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1275909: Warning: Identifier `\clknet_11_1225_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1275916: Warning: Identifier `\clknet_11_1227_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1275923: Warning: Identifier `\clknet_11_1229_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1275951: Warning: Identifier `\clknet_11_1228_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1275993: Warning: Identifier `\clknet_11_1181_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1276014: Warning: Identifier `\clknet_11_1180_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1276028: Warning: Identifier `\clknet_11_1177_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1276049: Warning: Identifier `\clknet_11_1174_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1276133: Warning: Identifier `\clknet_11_226_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1276140: Warning: Identifier `\clknet_11_189_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1276154: Warning: Identifier `\clknet_11_227_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1276161: Warning: Identifier `\clknet_11_230_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1276301: Warning: Identifier `\clknet_11_916_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1276343: Warning: Identifier `\clknet_11_919_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1276357: Warning: Identifier `\clknet_11_180_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1276511: Warning: Identifier `\clknet_11_18_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1276637: Warning: Identifier `\clknet_11_1291_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1276721: Warning: Identifier `\clknet_11_1365_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1276742: Warning: Identifier `\clknet_11_1373_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1276756: Warning: Identifier `\clknet_11_1375_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1276784: Warning: Identifier `\clknet_11_1374_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1276791: Warning: Identifier `\clknet_11_1359_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1276812: Warning: Identifier `\clknet_11_1358_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1276826: Warning: Identifier `\clknet_11_1303_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1276833: Warning: Identifier `\clknet_11_1302_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1276847: Warning: Identifier `\clknet_11_1297_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1276903: Warning: Identifier `\clknet_11_1347_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1276952: Warning: Identifier `\clknet_11_1363_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1276966: Warning: Identifier `\clknet_11_1369_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1276980: Warning: Identifier `\clknet_11_1371_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1277015: Warning: Identifier `\clknet_11_1355_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1277022: Warning: Identifier `\clknet_11_1354_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1277029: Warning: Identifier `\clknet_11_1376_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1277050: Warning: Identifier `\clknet_11_1309_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1277057: Warning: Identifier `\clknet_11_1299_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1277078: Warning: Identifier `\clknet_11_1298_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1277085: Warning: Identifier `\clknet_11_1294_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1277092: Warning: Identifier `\clknet_11_1292_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1277099: Warning: Identifier `\clknet_11_1282_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1277113: Warning: Identifier `\clknet_11_1286_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1277148: Warning: Identifier `\clknet_11_1362_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1277323: Warning: Identifier `\clknet_11_1289_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1277337: Warning: Identifier `\clknet_11_1287_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1277358: Warning: Identifier `\clknet_11_1351_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1277365: Warning: Identifier `\clknet_11_1350_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1277428: Warning: Identifier `\clknet_11_1370_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1277652: Warning: Identifier `\clknet_11_1392_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1277673: Warning: Identifier `\clknet_11_1393_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1277904: Warning: Identifier `\clknet_11_1394_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1277981: Warning: Identifier `\clknet_11_1300_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1278086: Warning: Identifier `\clknet_11_1357_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1278219: Warning: Identifier `\clknet_11_1280_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1278254: Warning: Identifier `\clknet_11_1345_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1278359: Warning: Identifier `\clknet_11_1382_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1278457: Warning: Identifier `\clknet_11_1285_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1278464: Warning: Identifier `\clknet_11_1344_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1278702: Warning: Identifier `\clknet_11_1348_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1278765: Warning: Identifier `\clknet_11_1368_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1279136: Warning: Identifier `\clknet_opt_2_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1279220: Warning: Identifier `\clknet_11_1397_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1279255: Warning: Identifier `\clknet_11_1381_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1279556: Warning: Identifier `\clknet_11_1283_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1279780: Warning: Identifier `\clknet_11_1293_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1280410: Warning: Identifier `\clknet_11_1352_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1280445: Warning: Identifier `\clknet_11_1295_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1280872: Warning: Identifier `\clknet_11_1301_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1281292: Warning: Identifier `\clknet_11_1356_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1281649: Warning: Identifier `\clknet_opt_4_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1281754: Warning: Identifier `\clknet_11_1353_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1283581: Warning: Identifier `\clknet_11_181_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1284085: Warning: Identifier `\clknet_11_479_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1284092: Warning: Identifier `\clknet_11_478_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1284120: Warning: Identifier `\clknet_11_500_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1284148: Warning: Identifier `\clknet_11_161_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1284225: Warning: Identifier `\clknet_11_1224_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1284281: Warning: Identifier `\clknet_11_1231_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1284302: Warning: Identifier `\clknet_11_1230_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1284337: Warning: Identifier `\clknet_11_1183_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1284351: Warning: Identifier `\clknet_11_1182_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1284372: Warning: Identifier `\clknet_11_1179_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1284421: Warning: Identifier `\clknet_11_183_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1284463: Warning: Identifier `\clknet_11_225_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1284554: Warning: Identifier `\clknet_11_232_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1284757: Warning: Identifier `\clknet_11_188_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1284869: Warning: Identifier `\clknet_11_175_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1284876: Warning: Identifier `\clknet_11_174_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1284890: Warning: Identifier `\clknet_11_186_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1284946: Warning: Identifier `\clknet_11_187_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1285282: Warning: Identifier `\clknet_11_185_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1285702: Warning: Identifier `\clknet_11_182_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1285758: Warning: Identifier `\clknet_11_224_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1285835: Warning: Identifier `\clknet_11_38_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1286269: Warning: Identifier `\clknet_11_229_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1286437: Warning: Identifier `\clknet_11_228_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1287018: Warning: Identifier `\clknet_11_160_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1287207: Warning: Identifier `\clknet_11_257_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1287277: Warning: Identifier `\clknet_11_162_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1287893: Warning: Identifier `\clknet_11_592_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1287907: Warning: Identifier `\clknet_11_593_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1287942: Warning: Identifier `\clknet_11_598_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1289013: Warning: Identifier `\clknet_11_235_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1289454: Warning: Identifier `\clknet_11_251_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1289706: Warning: Identifier `\clknet_11_833_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1289720: Warning: Identifier `\clknet_11_832_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1289916: Warning: Identifier `\clknet_11_785_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1290168: Warning: Identifier `\clknet_11_789_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1290476: Warning: Identifier `\clknet_11_836_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1290651: Warning: Identifier `\clknet_11_852_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1290924: Warning: Identifier `\clknet_11_853_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1291701: Warning: Identifier `\clknet_11_1211_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1291981: Warning: Identifier `\clknet_11_1620_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1292009: Warning: Identifier `\clknet_11_1605_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1292149: Warning: Identifier `\clknet_11_1278_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1292156: Warning: Identifier `\clknet_11_1621_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1292170: Warning: Identifier `\clknet_11_1275_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1292338: Warning: Identifier `\clknet_11_171_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1292380: Warning: Identifier `\clknet_11_168_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1292485: Warning: Identifier `\clknet_11_184_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1292562: Warning: Identifier `\clknet_11_172_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1292597: Warning: Identifier `\clknet_11_178_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1292709: Warning: Identifier `\clknet_11_166_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1292793: Warning: Identifier `\clknet_11_173_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1292842: Warning: Identifier `\clknet_11_170_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1293101: Warning: Identifier `\clknet_11_167_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1294186: Warning: Identifier `\clknet_11_1624_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1294193: Warning: Identifier `\clknet_11_1613_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1294277: Warning: Identifier `\clknet_11_1625_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1294298: Warning: Identifier `\clknet_11_1612_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1294319: Warning: Identifier `\clknet_11_1609_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1294508: Warning: Identifier `\clknet_11_1567_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1295194: Warning: Identifier `\clknet_11_1565_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1295572: Warning: Identifier `\clknet_11_1546_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1295789: Warning: Identifier `\clknet_11_177_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1295831: Warning: Identifier `\clknet_11_179_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1296069: Warning: Identifier `\clknet_11_1547_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1296874: Warning: Identifier `\clknet_11_625_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1296972: Warning: Identifier `\clknet_11_627_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1297042: Warning: Identifier `\clknet_11_624_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1297119: Warning: Identifier `\clknet_11_626_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1297161: Warning: Identifier `\clknet_11_613_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1297217: Warning: Identifier `\clknet_11_609_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1297231: Warning: Identifier `\clknet_11_612_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1297259: Warning: Identifier `\clknet_11_608_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1297518: Warning: Identifier `\clknet_11_615_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1297805: Warning: Identifier `\clknet_11_614_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1297861: Warning: Identifier `\clknet_11_610_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1297868: Warning: Identifier `\clknet_11_565_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1297882: Warning: Identifier `\clknet_11_620_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1298057: Warning: Identifier `\clknet_11_611_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1298141: Warning: Identifier `\clknet_11_543_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1298673: Warning: Identifier `\clknet_11_617_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1298722: Warning: Identifier `\clknet_11_616_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1299233: Warning: Identifier `\clknet_11_726_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1299471: Warning: Identifier `\clknet_11_722_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1299576: Warning: Identifier `\clknet_11_729_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1299590: Warning: Identifier `\clknet_11_723_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1299646: Warning: Identifier `\clknet_11_896_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1299954: Warning: Identifier `\clknet_11_708_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1300325: Warning: Identifier `\clknet_11_889_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1300332: Warning: Identifier `\clknet_11_888_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1300346: Warning: Identifier `\clknet_11_876_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1300381: Warning: Identifier `\clknet_11_892_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1300710: Warning: Identifier `\clknet_11_877_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1300955: Warning: Identifier `\clknet_11_873_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1300976: Warning: Identifier `\clknet_11_872_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1301207: Warning: Identifier `\clknet_11_829_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1301221: Warning: Identifier `\clknet_11_871_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1301235: Warning: Identifier `\clknet_11_870_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1301354: Warning: Identifier `\clknet_11_866_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1301410: Warning: Identifier `\clknet_11_867_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1301893: Warning: Identifier `\clknet_11_883_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1302159: Warning: Identifier `\clknet_11_1645_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1302341: Warning: Identifier `\clknet_11_1656_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1302565: Warning: Identifier `\clknet_11_1660_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1302572: Warning: Identifier `\clknet_11_1661_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1302677: Warning: Identifier `\clknet_11_1657_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1303188: Warning: Identifier `\clknet_11_1833_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1303314: Warning: Identifier `\clknet_11_1836_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1303349: Warning: Identifier `\clknet_11_1842_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1303356: Warning: Identifier `\clknet_11_1837_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1303573: Warning: Identifier `\clknet_11_1847_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1303762: Warning: Identifier `\clknet_11_1848_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1303916: Warning: Identifier `\clknet_11_1849_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1303944: Warning: Identifier `\clknet_11_1850_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1304042: Warning: Identifier `\clknet_11_1851_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1304070: Warning: Identifier `\clknet_11_1839_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1304140: Warning: Identifier `\clknet_11_1854_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1304364: Warning: Identifier `\clknet_11_1940_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1304399: Warning: Identifier `\clknet_11_1942_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1304567: Warning: Identifier `\clknet_11_1939_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1304581: Warning: Identifier `\clknet_11_1948_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1304595: Warning: Identifier `\clknet_11_1945_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1304609: Warning: Identifier `\clknet_11_1944_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1304721: Warning: Identifier `\clknet_11_1938_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1304735: Warning: Identifier `\clknet_11_1927_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1304805: Warning: Identifier `\clknet_11_1921_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1304868: Warning: Identifier `\clknet_11_1937_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1305106: Warning: Identifier `\clknet_11_1936_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1305127: Warning: Identifier `\clknet_11_1926_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1305169: Warning: Identifier `\clknet_11_1925_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1305183: Warning: Identifier `\clknet_11_1924_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1306072: Warning: Identifier `\clknet_11_1975_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1306226: Warning: Identifier `\clknet_11_1981_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1306282: Warning: Identifier `\clknet_11_1983_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1306373: Warning: Identifier `\clknet_11_1974_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1306422: Warning: Identifier `\clknet_11_1982_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1306485: Warning: Identifier `\clknet_11_1969_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1306681: Warning: Identifier `\clknet_11_1980_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1307045: Warning: Identifier `\clknet_11_1946_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1307101: Warning: Identifier `\clknet_11_1947_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1307626: Warning: Identifier `\clknet_11_1747_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1307675: Warning: Identifier `\clknet_11_1923_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1307801: Warning: Identifier `\clknet_11_1922_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1308053: Warning: Identifier `\clknet_11_1756_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1308165: Warning: Identifier `\clknet_11_1753_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1308613: Warning: Identifier `\clknet_11_1752_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1308858: Warning: Identifier `\clknet_11_1741_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1308865: Warning: Identifier `\clknet_11_1735_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1309068: Warning: Identifier `\clknet_11_1740_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1309082: Warning: Identifier `\clknet_11_1734_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1309124: Warning: Identifier `\clknet_11_1737_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1309425: Warning: Identifier `\clknet_11_1736_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1309509: Warning: Identifier `\clknet_11_983_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1309565: Warning: Identifier `\clknet_11_1673_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1309621: Warning: Identifier `\clknet_11_1688_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1309635: Warning: Identifier `\clknet_11_1677_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1309712: Warning: Identifier `\clknet_11_1682_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1309733: Warning: Identifier `\clknet_11_1692_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1309789: Warning: Identifier `\clknet_11_1689_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1309957: Warning: Identifier `\clknet_11_1693_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1310741: Warning: Identifier `\clknet_11_1676_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1310923: Warning: Identifier `\clknet_11_1672_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1311210: Warning: Identifier `\clknet_11_967_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1311413: Warning: Identifier `\clknet_11_973_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1311616: Warning: Identifier `\clknet_11_966_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1311756: Warning: Identifier `\clknet_11_968_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1311931: Warning: Identifier `\clknet_11_927_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1311966: Warning: Identifier `\clknet_11_925_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1312092: Warning: Identifier `\clknet_11_926_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1312120: Warning: Identifier `\clknet_11_924_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1312197: Warning: Identifier `\clknet_11_923_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1312218: Warning: Identifier `\clknet_11_921_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1312477: Warning: Identifier `\clknet_11_945_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1312554: Warning: Identifier `\clknet_11_948_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1313163: Warning: Identifier `\clknet_11_931_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1313331: Warning: Identifier `\clknet_11_929_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1313450: Warning: Identifier `\clknet_11_918_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1313989: Warning: Identifier `\clknet_11_901_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1314017: Warning: Identifier `\clknet_11_912_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1314101: Warning: Identifier `\clknet_11_900_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1314458: Warning: Identifier `\clknet_11_915_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1314892: Warning: Identifier `\clknet_11_917_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1315130: Warning: Identifier `\clknet_11_811_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1315529: Warning: Identifier `\clknet_opt_1_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1319190: Warning: Identifier `\clknet_11_259_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1319645: Warning: Identifier `\clknet_11_295_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1319652: Warning: Identifier `\clknet_11_294_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1319736: Warning: Identifier `\clknet_11_270_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1319778: Warning: Identifier `\clknet_11_289_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1319813: Warning: Identifier `\clknet_11_288_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1319834: Warning: Identifier `\clknet_11_267_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1319890: Warning: Identifier `\clknet_11_266_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1319904: Warning: Identifier `\clknet_11_292_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1320093: Warning: Identifier `\clknet_11_269_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1320107: Warning: Identifier `\clknet_11_268_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1320121: Warning: Identifier `\clknet_11_265_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1320240: Warning: Identifier `\clknet_11_262_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1320282: Warning: Identifier `\clknet_11_263_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1320373: Warning: Identifier `\clknet_11_274_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1320485: Warning: Identifier `\clknet_11_272_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1320506: Warning: Identifier `\clknet_11_260_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1320520: Warning: Identifier `\clknet_11_261_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1320821: Warning: Identifier `\clknet_11_280_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1321213: Warning: Identifier `\clknet_11_301_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1321381: Warning: Identifier `\clknet_11_303_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1321388: Warning: Identifier `\clknet_11_302_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1321409: Warning: Identifier `\clknet_11_314_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1321451: Warning: Identifier `\clknet_11_312_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1321472: Warning: Identifier `\clknet_11_313_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1321549: Warning: Identifier `\clknet_11_306_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1321633: Warning: Identifier `\clknet_11_307_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1321647: Warning: Identifier `\clknet_11_310_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1321829: Warning: Identifier `\clknet_11_1160_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1321850: Warning: Identifier `\clknet_11_501_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1322298: Warning: Identifier `\clknet_11_281_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1322319: Warning: Identifier `\clknet_11_286_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1322361: Warning: Identifier `\clknet_11_284_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1322382: Warning: Identifier `\clknet_11_285_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1322501: Warning: Identifier `\clknet_11_283_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1322557: Warning: Identifier `\clknet_11_275_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1322634: Warning: Identifier `\clknet_11_278_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1322669: Warning: Identifier `\clknet_11_273_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1322690: Warning: Identifier `\clknet_11_276_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1322711: Warning: Identifier `\clknet_11_277_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1322935: Warning: Identifier `\clknet_11_279_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1323166: Warning: Identifier `\clknet_11_287_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1323397: Warning: Identifier `\clknet_11_1154_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1323915: Warning: Identifier `\clknet_11_364_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1324090: Warning: Identifier `\clknet_11_133_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1324174: Warning: Identifier `\clknet_11_361_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1324447: Warning: Identifier `\clknet_11_405_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1324454: Warning: Identifier `\clknet_11_404_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1324860: Warning: Identifier `\clknet_11_1161_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1325105: Warning: Identifier `\clknet_11_358_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1325112: Warning: Identifier `\clknet_11_355_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1325161: Warning: Identifier `\clknet_11_370_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1325259: Warning: Identifier `\clknet_11_359_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1325700: Warning: Identifier `\clknet_11_368_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1325707: Warning: Identifier `\clknet_11_369_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1325735: Warning: Identifier `\clknet_11_346_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1325798: Warning: Identifier `\clknet_11_335_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1325924: Warning: Identifier `\clknet_11_331_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1325938: Warning: Identifier `\clknet_11_334_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1326036: Warning: Identifier `\clknet_11_329_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1326078: Warning: Identifier `\clknet_11_333_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1326204: Warning: Identifier `\clknet_11_321_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1326218: Warning: Identifier `\clknet_11_324_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1326232: Warning: Identifier `\clknet_11_327_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1326281: Warning: Identifier `\clknet_11_325_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1326372: Warning: Identifier `\clknet_11_323_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1326491: Warning: Identifier `\clknet_11_461_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1326505: Warning: Identifier `\clknet_11_466_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1326526: Warning: Identifier `\clknet_11_460_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1326624: Warning: Identifier `\clknet_11_467_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1326659: Warning: Identifier `\clknet_11_454_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1326932: Warning: Identifier `\clknet_11_356_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1326953: Warning: Identifier `\clknet_11_357_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1326988: Warning: Identifier `\clknet_11_353_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1327380: Warning: Identifier `\clknet_11_354_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1327401: Warning: Identifier `\clknet_11_309_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1327737: Warning: Identifier `\clknet_11_352_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1327849: Warning: Identifier `\clknet_11_330_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1327961: Warning: Identifier `\clknet_11_328_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1328073: Warning: Identifier `\clknet_11_322_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1328241: Warning: Identifier `\clknet_11_320_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1328444: Warning: Identifier `\clknet_11_470_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1328549: Warning: Identifier `\clknet_11_476_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1328612: Warning: Identifier `\clknet_11_465_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1330180: Warning: Identifier `\clknet_11_463_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1330320: Warning: Identifier `\clknet_11_1128_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1330348: Warning: Identifier `\clknet_11_1134_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1330355: Warning: Identifier `\clknet_11_1132_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1330775: Warning: Identifier `\clknet_11_1079_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1330913: Warning: Identifier `\softshell.cpus[1].core.flexio.out_fifo.wgray_cross[0]' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1330916: Warning: Identifier `\clknet_11_1414_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1330921: Warning: Identifier `\softshell.cpus[1].core.flexio.out_fifo.wgray_cross[1]' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1330929: Warning: Identifier `\softshell.cpus[1].core.flexio.out_fifo.wgray_cross[2]' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1330961: Warning: Identifier `\softshell.cpus[1].core.flexio.out_fifo.rgray_cross[0]' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1330969: Warning: Identifier `\softshell.cpus[1].core.flexio.out_fifo.rgray_cross[1]' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1330977: Warning: Identifier `\softshell.cpus[1].core.flexio.out_fifo.rgray_cross[2]' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1331036: Warning: Identifier `\clknet_11_1514_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1331044: Warning: Identifier `\clknet_11_1439_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1331052: Warning: Identifier `\clknet_11_1438_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1331108: Warning: Identifier `\clknet_11_1519_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1331124: Warning: Identifier `\clknet_11_1518_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1331164: Warning: Identifier `\clknet_11_1516_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1331196: Warning: Identifier `\clknet_11_1515_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1331257: Warning: Identifier `\clknet_11_1406_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1331264: Warning: Identifier `\clknet_11_1404_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1331299: Warning: Identifier `\clknet_11_1405_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1331306: Warning: Identifier `\clknet_11_1403_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1331334: Warning: Identifier `\clknet_opt_25_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1331341: Warning: Identifier `\clknet_opt_5_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1331348: Warning: Identifier `\clknet_opt_20_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1331355: Warning: Identifier `\clknet_opt_24_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1331362: Warning: Identifier `\clknet_opt_19_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1331831: Warning: Identifier `\clknet_opt_12_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1331838: Warning: Identifier `\clknet_opt_18_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1331845: Warning: Identifier `\clknet_opt_17_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1331852: Warning: Identifier `\clknet_opt_16_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1331955: Warning: Identifier `\softshell.cpus[0].core.flexio.out_fifo.wgray_cross[0]' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1331963: Warning: Identifier `\softshell.cpus[0].core.flexio.out_fifo.wgray_cross[1]' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1331971: Warning: Identifier `\softshell.cpus[0].core.flexio.out_fifo.wgray_cross[2]' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1332003: Warning: Identifier `\softshell.cpus[0].core.flexio.out_fifo.rgray_cross[0]' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1332011: Warning: Identifier `\softshell.cpus[0].core.flexio.out_fifo.rgray_cross[1]' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1332019: Warning: Identifier `\softshell.cpus[0].core.flexio.out_fifo.rgray_cross[2]' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1332174: Warning: Identifier `\clknet_11_144_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1332292: Warning: Identifier `\clknet_11_481_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1332404: Warning: Identifier `\clknet_11_498_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1332481: Warning: Identifier `\clknet_11_415_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1332670: Warning: Identifier `\clknet_11_101_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1332768: Warning: Identifier `\clknet_11_44_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1332971: Warning: Identifier `\clknet_11_98_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1333251: Warning: Identifier `\clknet_11_480_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1333482: Warning: Identifier `\clknet_11_1388_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1333490: Warning: Identifier `\clknet_11_474_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1333510: Warning: Identifier `\softshell.reset_pipe[0]' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1333512: Warning: Identifier `\clknet_11_40_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1333518: Warning: Identifier `\softshell.reset_pipe[1]' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1333575: Warning: Identifier `\softshell.cpus[2].core.flexio.out_fifo.wgray_cross[0]' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1333583: Warning: Identifier `\softshell.cpus[2].core.flexio.out_fifo.wgray_cross[1]' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1333591: Warning: Identifier `\softshell.cpus[2].core.flexio.out_fifo.wgray_cross[2]' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1333623: Warning: Identifier `\softshell.cpus[2].core.flexio.out_fifo.rgray_cross[0]' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1333631: Warning: Identifier `\softshell.cpus[2].core.flexio.out_fifo.rgray_cross[1]' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1333639: Warning: Identifier `\softshell.cpus[2].core.flexio.out_fifo.rgray_cross[2]' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1333706: Warning: Identifier `\clknet_11_1176_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1333714: Warning: Identifier `\clknet_11_1170_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1333722: Warning: Identifier `\clknet_11_1159_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1333754: Warning: Identifier `\clknet_11_1165_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1333818: Warning: Identifier `\clknet_11_1178_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1333919: Warning: Identifier `\clknet_11_1412_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1334248: Warning: Identifier `\clknet_11_384_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1334262: Warning: Identifier `\clknet_11_385_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1334283: Warning: Identifier `\clknet_opt_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1334290: Warning: Identifier `\clknet_11_213_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1334696: Warning: Identifier `\clknet_11_459_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1334724: Warning: Identifier `\clknet_11_462_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1335563: Warning: Identifier `\clknet_11_214_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1335667: Warning: Identifier `\clknet_11_389_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1335675: Warning: Identifier `\clknet_11_390_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1336243: Warning: Identifier `\clknet_11_215_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1336285: Warning: Identifier `\clknet_11_221_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1336313: Warning: Identifier `\clknet_11_386_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1336852: Warning: Identifier `\clknet_11_1483_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1337195: Warning: Identifier `\clknet_11_1062_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1337307: Warning: Identifier `\clknet_11_1058_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1337349: Warning: Identifier `\clknet_11_1059_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1337821: Warning: Identifier `\clknet_11_457_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1337842: Warning: Identifier `\clknet_11_451_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1338178: Warning: Identifier `\clknet_11_472_0_wb_clk_i' is implicitly declared.
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+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1555788: Warning: Identifier `\clknet_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1555794: Warning: Identifier `\clknet_1_0_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1555800: Warning: Identifier `\clknet_1_0_1_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1555806: Warning: Identifier `\clknet_1_0_2_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1555812: Warning: Identifier `\clknet_1_0_3_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1555818: Warning: Identifier `\clknet_1_0_4_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1555824: Warning: Identifier `\clknet_1_0_5_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1555830: Warning: Identifier `\clknet_1_0_6_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1555836: Warning: Identifier `\clknet_1_1_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1555842: Warning: Identifier `\clknet_1_1_1_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1555848: Warning: Identifier `\clknet_1_1_2_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1555854: Warning: Identifier `\clknet_1_1_3_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1555860: Warning: Identifier `\clknet_1_1_4_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1555866: Warning: Identifier `\clknet_1_1_5_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1555872: Warning: Identifier `\clknet_1_1_6_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1555878: Warning: Identifier `\clknet_2_0_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1555884: Warning: Identifier `\clknet_2_0_1_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1555890: Warning: Identifier `\clknet_2_0_2_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1555896: Warning: Identifier `\clknet_2_0_3_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1555902: Warning: Identifier `\clknet_2_0_4_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1555908: Warning: Identifier `\clknet_2_0_5_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1555914: Warning: Identifier `\clknet_2_1_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1555920: Warning: Identifier `\clknet_2_1_1_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1555926: Warning: Identifier `\clknet_2_1_2_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1555932: Warning: Identifier `\clknet_2_1_3_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1555938: Warning: Identifier `\clknet_2_1_4_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1555944: Warning: Identifier `\clknet_2_1_5_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1555950: Warning: Identifier `\clknet_2_2_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1555956: Warning: Identifier `\clknet_2_2_1_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1555962: Warning: Identifier `\clknet_2_2_2_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1555968: Warning: Identifier `\clknet_2_2_3_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1555974: Warning: Identifier `\clknet_2_2_4_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1555980: Warning: Identifier `\clknet_2_2_5_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1555986: Warning: Identifier `\clknet_2_3_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1555992: Warning: Identifier `\clknet_2_3_1_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1555998: Warning: Identifier `\clknet_2_3_2_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1556004: Warning: Identifier `\clknet_2_3_3_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1556010: Warning: Identifier `\clknet_2_3_4_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1556016: Warning: Identifier `\clknet_2_3_5_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1556022: Warning: Identifier `\clknet_3_0_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1556028: Warning: Identifier `\clknet_3_0_1_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1556034: Warning: Identifier `\clknet_3_0_2_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1556040: Warning: Identifier `\clknet_3_0_3_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1556046: Warning: Identifier `\clknet_3_1_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1556052: Warning: Identifier `\clknet_3_1_1_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1556058: Warning: Identifier `\clknet_3_1_2_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1556064: Warning: Identifier `\clknet_3_1_3_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1556070: Warning: Identifier `\clknet_3_2_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1556076: Warning: Identifier `\clknet_3_2_1_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1556082: Warning: Identifier `\clknet_3_2_2_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1556088: Warning: Identifier `\clknet_3_2_3_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1556094: Warning: Identifier `\clknet_3_3_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1556100: Warning: Identifier `\clknet_3_3_1_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1556106: Warning: Identifier `\clknet_3_3_2_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1556112: Warning: Identifier `\clknet_3_3_3_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1556118: Warning: Identifier `\clknet_3_4_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1556124: Warning: Identifier `\clknet_3_4_1_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1556130: Warning: Identifier `\clknet_3_4_2_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1556136: Warning: Identifier `\clknet_3_4_3_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1556142: Warning: Identifier `\clknet_3_5_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1556148: Warning: Identifier `\clknet_3_5_1_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1556154: Warning: Identifier `\clknet_3_5_2_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1556160: Warning: Identifier `\clknet_3_5_3_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1556166: Warning: Identifier `\clknet_3_6_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1556172: Warning: Identifier `\clknet_3_6_1_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1556178: Warning: Identifier `\clknet_3_6_2_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1556184: Warning: Identifier `\clknet_3_6_3_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1556190: Warning: Identifier `\clknet_3_7_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1556196: Warning: Identifier `\clknet_3_7_1_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1556202: Warning: Identifier `\clknet_3_7_2_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1556208: Warning: Identifier `\clknet_3_7_3_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1556214: Warning: Identifier `\clknet_4_0_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1556220: Warning: Identifier `\clknet_4_0_1_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1556226: Warning: Identifier `\clknet_4_0_2_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1556232: Warning: Identifier `\clknet_4_1_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1556238: Warning: Identifier `\clknet_4_1_1_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1556244: Warning: Identifier `\clknet_4_1_2_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1556250: Warning: Identifier `\clknet_4_2_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1556256: Warning: Identifier `\clknet_4_2_1_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1556262: Warning: Identifier `\clknet_4_2_2_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1556268: Warning: Identifier `\clknet_4_3_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1556274: Warning: Identifier `\clknet_4_3_1_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1556280: Warning: Identifier `\clknet_4_3_2_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1556286: Warning: Identifier `\clknet_4_4_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1556292: Warning: Identifier `\clknet_4_4_1_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1556298: Warning: Identifier `\clknet_4_4_2_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1556304: Warning: Identifier `\clknet_4_5_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1556310: Warning: Identifier `\clknet_4_5_1_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1556316: Warning: Identifier `\clknet_4_5_2_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1556322: Warning: Identifier `\clknet_4_6_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1556328: Warning: Identifier `\clknet_4_6_1_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1556334: Warning: Identifier `\clknet_4_6_2_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1556340: Warning: Identifier `\clknet_4_7_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1556346: Warning: Identifier `\clknet_4_7_1_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1556352: Warning: Identifier `\clknet_4_7_2_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1556358: Warning: Identifier `\clknet_4_8_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1556364: Warning: Identifier `\clknet_4_8_1_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1556370: Warning: Identifier `\clknet_4_8_2_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1556376: Warning: Identifier `\clknet_4_9_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1556382: Warning: Identifier `\clknet_4_9_1_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1556388: Warning: Identifier `\clknet_4_9_2_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1556394: Warning: Identifier `\clknet_4_10_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1556400: Warning: Identifier `\clknet_4_10_1_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1556406: Warning: Identifier `\clknet_4_10_2_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1556412: Warning: Identifier `\clknet_4_11_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1556418: Warning: Identifier `\clknet_4_11_1_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1556424: Warning: Identifier `\clknet_4_11_2_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1556430: Warning: Identifier `\clknet_4_12_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1556436: Warning: Identifier `\clknet_4_12_1_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1556442: Warning: Identifier `\clknet_4_12_2_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1556448: Warning: Identifier `\clknet_4_13_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1556454: Warning: Identifier `\clknet_4_13_1_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1556460: Warning: Identifier `\clknet_4_13_2_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1556466: Warning: Identifier `\clknet_4_14_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1556472: Warning: Identifier `\clknet_4_14_1_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1556478: Warning: Identifier `\clknet_4_14_2_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1556484: Warning: Identifier `\clknet_4_15_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1556490: Warning: Identifier `\clknet_4_15_1_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1556496: Warning: Identifier `\clknet_4_15_2_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1556502: Warning: Identifier `\clknet_5_0_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1556508: Warning: Identifier `\clknet_5_0_1_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1556514: Warning: Identifier `\clknet_5_1_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1556520: Warning: Identifier `\clknet_5_1_1_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1556526: Warning: Identifier `\clknet_5_2_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1556532: Warning: Identifier `\clknet_5_2_1_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1556538: Warning: Identifier `\clknet_5_3_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1556544: Warning: Identifier `\clknet_5_3_1_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1556550: Warning: Identifier `\clknet_5_4_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1556556: Warning: Identifier `\clknet_5_4_1_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1556562: Warning: Identifier `\clknet_5_5_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1556568: Warning: Identifier `\clknet_5_5_1_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1556574: Warning: Identifier `\clknet_5_6_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1556580: Warning: Identifier `\clknet_5_6_1_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1556586: Warning: Identifier `\clknet_5_7_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1556592: Warning: Identifier `\clknet_5_7_1_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1556598: Warning: Identifier `\clknet_5_8_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1556604: Warning: Identifier `\clknet_5_8_1_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1556610: Warning: Identifier `\clknet_5_9_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1556616: Warning: Identifier `\clknet_5_9_1_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1556622: Warning: Identifier `\clknet_5_10_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1556628: Warning: Identifier `\clknet_5_10_1_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1556634: Warning: Identifier `\clknet_5_11_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1556640: Warning: Identifier `\clknet_5_11_1_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1556646: Warning: Identifier `\clknet_5_12_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1556652: Warning: Identifier `\clknet_5_12_1_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1556658: Warning: Identifier `\clknet_5_13_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1556664: Warning: Identifier `\clknet_5_13_1_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1556670: Warning: Identifier `\clknet_5_14_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1556676: Warning: Identifier `\clknet_5_14_1_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1556682: Warning: Identifier `\clknet_5_15_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1556688: Warning: Identifier `\clknet_5_15_1_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1556694: Warning: Identifier `\clknet_5_16_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1556700: Warning: Identifier `\clknet_5_16_1_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1556706: Warning: Identifier `\clknet_5_17_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1556712: Warning: Identifier `\clknet_5_17_1_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1556718: Warning: Identifier `\clknet_5_18_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1556724: Warning: Identifier `\clknet_5_18_1_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1556730: Warning: Identifier `\clknet_5_19_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1556736: Warning: Identifier `\clknet_5_19_1_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1556742: Warning: Identifier `\clknet_5_20_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1556748: Warning: Identifier `\clknet_5_20_1_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1556754: Warning: Identifier `\clknet_5_21_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1556760: Warning: Identifier `\clknet_5_21_1_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1556766: Warning: Identifier `\clknet_5_22_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1556772: Warning: Identifier `\clknet_5_22_1_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1556778: Warning: Identifier `\clknet_5_23_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1556784: Warning: Identifier `\clknet_5_23_1_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1556790: Warning: Identifier `\clknet_5_24_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1556796: Warning: Identifier `\clknet_5_24_1_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1556802: Warning: Identifier `\clknet_5_25_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1556808: Warning: Identifier `\clknet_5_25_1_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1556814: Warning: Identifier `\clknet_5_26_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1556820: Warning: Identifier `\clknet_5_26_1_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1556826: Warning: Identifier `\clknet_5_27_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1556832: Warning: Identifier `\clknet_5_27_1_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1556838: Warning: Identifier `\clknet_5_28_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1556844: Warning: Identifier `\clknet_5_28_1_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1556850: Warning: Identifier `\clknet_5_29_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1556856: Warning: Identifier `\clknet_5_29_1_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1556862: Warning: Identifier `\clknet_5_30_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1556868: Warning: Identifier `\clknet_5_30_1_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1556874: Warning: Identifier `\clknet_5_31_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1556880: Warning: Identifier `\clknet_5_31_1_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1556886: Warning: Identifier `\clknet_6_0_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1556892: Warning: Identifier `\clknet_6_0_1_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1556898: Warning: Identifier `\clknet_6_1_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1556904: Warning: Identifier `\clknet_6_1_1_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1556910: Warning: Identifier `\clknet_6_2_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1556916: Warning: Identifier `\clknet_6_2_1_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1556922: Warning: Identifier `\clknet_6_3_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1556928: Warning: Identifier `\clknet_6_3_1_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1556934: Warning: Identifier `\clknet_6_4_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1556940: Warning: Identifier `\clknet_6_4_1_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1556946: Warning: Identifier `\clknet_6_5_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1556952: Warning: Identifier `\clknet_6_5_1_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1556958: Warning: Identifier `\clknet_6_6_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1556964: Warning: Identifier `\clknet_6_6_1_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1556970: Warning: Identifier `\clknet_6_7_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1556976: Warning: Identifier `\clknet_6_7_1_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1556982: Warning: Identifier `\clknet_6_8_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1556988: Warning: Identifier `\clknet_6_8_1_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1556994: Warning: Identifier `\clknet_6_9_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1557000: Warning: Identifier `\clknet_6_9_1_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1557006: Warning: Identifier `\clknet_6_10_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1557012: Warning: Identifier `\clknet_6_10_1_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1557018: Warning: Identifier `\clknet_6_11_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1557024: Warning: Identifier `\clknet_6_11_1_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1557030: Warning: Identifier `\clknet_6_12_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1557036: Warning: Identifier `\clknet_6_12_1_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1557042: Warning: Identifier `\clknet_6_13_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1557048: Warning: Identifier `\clknet_6_13_1_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1557054: Warning: Identifier `\clknet_6_14_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1557060: Warning: Identifier `\clknet_6_14_1_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1557066: Warning: Identifier `\clknet_6_15_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1557072: Warning: Identifier `\clknet_6_15_1_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1557078: Warning: Identifier `\clknet_6_16_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1557084: Warning: Identifier `\clknet_6_16_1_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1557090: Warning: Identifier `\clknet_6_17_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1557096: Warning: Identifier `\clknet_6_17_1_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1557102: Warning: Identifier `\clknet_6_18_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1557108: Warning: Identifier `\clknet_6_18_1_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1557114: Warning: Identifier `\clknet_6_19_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1557120: Warning: Identifier `\clknet_6_19_1_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1557126: Warning: Identifier `\clknet_6_20_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1557132: Warning: Identifier `\clknet_6_20_1_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1557138: Warning: Identifier `\clknet_6_21_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1557144: Warning: Identifier `\clknet_6_21_1_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1557150: Warning: Identifier `\clknet_6_22_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1557156: Warning: Identifier `\clknet_6_22_1_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1557162: Warning: Identifier `\clknet_6_23_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1557168: Warning: Identifier `\clknet_6_23_1_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1557174: Warning: Identifier `\clknet_6_24_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1557180: Warning: Identifier `\clknet_6_24_1_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1557186: Warning: Identifier `\clknet_6_25_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1557192: Warning: Identifier `\clknet_6_25_1_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1557198: Warning: Identifier `\clknet_6_26_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1557204: Warning: Identifier `\clknet_6_26_1_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1557210: Warning: Identifier `\clknet_6_27_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1557216: Warning: Identifier `\clknet_6_27_1_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1557222: Warning: Identifier `\clknet_6_28_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1557228: Warning: Identifier `\clknet_6_28_1_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1557234: Warning: Identifier `\clknet_6_29_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1557240: Warning: Identifier `\clknet_6_29_1_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1557246: Warning: Identifier `\clknet_6_30_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1557252: Warning: Identifier `\clknet_6_30_1_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1557258: Warning: Identifier `\clknet_6_31_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1557264: Warning: Identifier `\clknet_6_31_1_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1557270: Warning: Identifier `\clknet_6_32_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1557276: Warning: Identifier `\clknet_6_32_1_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1557282: Warning: Identifier `\clknet_6_33_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1557288: Warning: Identifier `\clknet_6_33_1_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1557294: Warning: Identifier `\clknet_6_34_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1557300: Warning: Identifier `\clknet_6_34_1_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1557306: Warning: Identifier `\clknet_6_35_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1557312: Warning: Identifier `\clknet_6_35_1_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1557318: Warning: Identifier `\clknet_6_36_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1557324: Warning: Identifier `\clknet_6_36_1_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1557330: Warning: Identifier `\clknet_6_37_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1557336: Warning: Identifier `\clknet_6_37_1_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1557342: Warning: Identifier `\clknet_6_38_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1557348: Warning: Identifier `\clknet_6_38_1_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1557354: Warning: Identifier `\clknet_6_39_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1557360: Warning: Identifier `\clknet_6_39_1_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1557366: Warning: Identifier `\clknet_6_40_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1557372: Warning: Identifier `\clknet_6_40_1_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1557378: Warning: Identifier `\clknet_6_41_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1557384: Warning: Identifier `\clknet_6_41_1_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1557390: Warning: Identifier `\clknet_6_42_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1557396: Warning: Identifier `\clknet_6_42_1_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1557402: Warning: Identifier `\clknet_6_43_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1557408: Warning: Identifier `\clknet_6_43_1_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1557414: Warning: Identifier `\clknet_6_44_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1557420: Warning: Identifier `\clknet_6_44_1_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1557426: Warning: Identifier `\clknet_6_45_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1557432: Warning: Identifier `\clknet_6_45_1_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1557438: Warning: Identifier `\clknet_6_46_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1557444: Warning: Identifier `\clknet_6_46_1_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1557450: Warning: Identifier `\clknet_6_47_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1557456: Warning: Identifier `\clknet_6_47_1_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1557462: Warning: Identifier `\clknet_6_48_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1557468: Warning: Identifier `\clknet_6_48_1_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1557474: Warning: Identifier `\clknet_6_49_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1557480: Warning: Identifier `\clknet_6_49_1_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1557486: Warning: Identifier `\clknet_6_50_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1557492: Warning: Identifier `\clknet_6_50_1_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1557498: Warning: Identifier `\clknet_6_51_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1557504: Warning: Identifier `\clknet_6_51_1_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1557510: Warning: Identifier `\clknet_6_52_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1557516: Warning: Identifier `\clknet_6_52_1_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1557522: Warning: Identifier `\clknet_6_53_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1557528: Warning: Identifier `\clknet_6_53_1_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1557534: Warning: Identifier `\clknet_6_54_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1557540: Warning: Identifier `\clknet_6_54_1_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1557546: Warning: Identifier `\clknet_6_55_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1557552: Warning: Identifier `\clknet_6_55_1_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1557558: Warning: Identifier `\clknet_6_56_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1557564: Warning: Identifier `\clknet_6_56_1_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1557570: Warning: Identifier `\clknet_6_57_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1557576: Warning: Identifier `\clknet_6_57_1_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1557582: Warning: Identifier `\clknet_6_58_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1557588: Warning: Identifier `\clknet_6_58_1_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1557594: Warning: Identifier `\clknet_6_59_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1557600: Warning: Identifier `\clknet_6_59_1_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1557606: Warning: Identifier `\clknet_6_60_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1557612: Warning: Identifier `\clknet_6_60_1_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1557618: Warning: Identifier `\clknet_6_61_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1557624: Warning: Identifier `\clknet_6_61_1_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1557630: Warning: Identifier `\clknet_6_62_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1557636: Warning: Identifier `\clknet_6_62_1_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1557642: Warning: Identifier `\clknet_6_63_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1557648: Warning: Identifier `\clknet_6_63_1_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1557654: Warning: Identifier `\clknet_7_0_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1557660: Warning: Identifier `\clknet_7_1_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1557666: Warning: Identifier `\clknet_7_2_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1557672: Warning: Identifier `\clknet_7_3_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1557678: Warning: Identifier `\clknet_7_4_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1557684: Warning: Identifier `\clknet_7_5_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1557690: Warning: Identifier `\clknet_7_6_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1557696: Warning: Identifier `\clknet_7_7_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1557702: Warning: Identifier `\clknet_7_8_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1557708: Warning: Identifier `\clknet_7_9_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1557714: Warning: Identifier `\clknet_7_10_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1557720: Warning: Identifier `\clknet_7_11_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1557726: Warning: Identifier `\clknet_7_12_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1557732: Warning: Identifier `\clknet_7_13_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1557738: Warning: Identifier `\clknet_7_14_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1557744: Warning: Identifier `\clknet_7_15_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1557750: Warning: Identifier `\clknet_7_16_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1557756: Warning: Identifier `\clknet_7_17_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1557762: Warning: Identifier `\clknet_7_18_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1557768: Warning: Identifier `\clknet_7_19_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1557774: Warning: Identifier `\clknet_7_20_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1557780: Warning: Identifier `\clknet_7_21_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1557786: Warning: Identifier `\clknet_7_22_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1557792: Warning: Identifier `\clknet_7_23_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1557798: Warning: Identifier `\clknet_7_24_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1557804: Warning: Identifier `\clknet_7_25_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1557810: Warning: Identifier `\clknet_7_26_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1557816: Warning: Identifier `\clknet_7_27_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1557822: Warning: Identifier `\clknet_7_28_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1557828: Warning: Identifier `\clknet_7_29_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1557834: Warning: Identifier `\clknet_7_30_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1557840: Warning: Identifier `\clknet_7_31_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1557846: Warning: Identifier `\clknet_7_32_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1557852: Warning: Identifier `\clknet_7_33_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1557858: Warning: Identifier `\clknet_7_34_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1557864: Warning: Identifier `\clknet_7_35_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1557870: Warning: Identifier `\clknet_7_36_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1557876: Warning: Identifier `\clknet_7_37_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1557882: Warning: Identifier `\clknet_7_38_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1557888: Warning: Identifier `\clknet_7_39_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1557894: Warning: Identifier `\clknet_7_40_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1557900: Warning: Identifier `\clknet_7_41_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1557906: Warning: Identifier `\clknet_7_42_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1557912: Warning: Identifier `\clknet_7_43_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1557918: Warning: Identifier `\clknet_7_44_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1557924: Warning: Identifier `\clknet_7_45_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1557930: Warning: Identifier `\clknet_7_46_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1557936: Warning: Identifier `\clknet_7_47_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1557942: Warning: Identifier `\clknet_7_48_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1557948: Warning: Identifier `\clknet_7_49_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1557954: Warning: Identifier `\clknet_7_50_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1557960: Warning: Identifier `\clknet_7_51_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1557966: Warning: Identifier `\clknet_7_52_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1557972: Warning: Identifier `\clknet_7_53_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1557978: Warning: Identifier `\clknet_7_54_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1557984: Warning: Identifier `\clknet_7_55_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1557990: Warning: Identifier `\clknet_7_56_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1557996: Warning: Identifier `\clknet_7_57_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1558002: Warning: Identifier `\clknet_7_58_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1558008: Warning: Identifier `\clknet_7_59_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1558014: Warning: Identifier `\clknet_7_60_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1558020: Warning: Identifier `\clknet_7_61_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1558026: Warning: Identifier `\clknet_7_62_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1558032: Warning: Identifier `\clknet_7_63_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1558038: Warning: Identifier `\clknet_7_64_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1558044: Warning: Identifier `\clknet_7_65_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1558050: Warning: Identifier `\clknet_7_66_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1558056: Warning: Identifier `\clknet_7_67_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1558062: Warning: Identifier `\clknet_7_68_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1558068: Warning: Identifier `\clknet_7_69_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1558074: Warning: Identifier `\clknet_7_70_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1558080: Warning: Identifier `\clknet_7_71_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1558086: Warning: Identifier `\clknet_7_72_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1558092: Warning: Identifier `\clknet_7_73_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1558098: Warning: Identifier `\clknet_7_74_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1558104: Warning: Identifier `\clknet_7_75_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1558110: Warning: Identifier `\clknet_7_76_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1558116: Warning: Identifier `\clknet_7_77_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1558122: Warning: Identifier `\clknet_7_78_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1558128: Warning: Identifier `\clknet_7_79_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1558134: Warning: Identifier `\clknet_7_80_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1558140: Warning: Identifier `\clknet_7_81_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1558146: Warning: Identifier `\clknet_7_82_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1558152: Warning: Identifier `\clknet_7_83_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1558158: Warning: Identifier `\clknet_7_84_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1558164: Warning: Identifier `\clknet_7_85_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1558170: Warning: Identifier `\clknet_7_86_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1558176: Warning: Identifier `\clknet_7_87_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1558182: Warning: Identifier `\clknet_7_88_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1558188: Warning: Identifier `\clknet_7_89_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1558194: Warning: Identifier `\clknet_7_90_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1558200: Warning: Identifier `\clknet_7_91_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1558206: Warning: Identifier `\clknet_7_92_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1558212: Warning: Identifier `\clknet_7_93_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1558218: Warning: Identifier `\clknet_7_94_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1558224: Warning: Identifier `\clknet_7_95_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1558230: Warning: Identifier `\clknet_7_96_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1558236: Warning: Identifier `\clknet_7_97_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1558242: Warning: Identifier `\clknet_7_98_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1558248: Warning: Identifier `\clknet_7_99_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1558254: Warning: Identifier `\clknet_7_100_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1558260: Warning: Identifier `\clknet_7_101_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1558266: Warning: Identifier `\clknet_7_102_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1558272: Warning: Identifier `\clknet_7_103_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1558278: Warning: Identifier `\clknet_7_104_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1558284: Warning: Identifier `\clknet_7_105_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1558290: Warning: Identifier `\clknet_7_106_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1558296: Warning: Identifier `\clknet_7_107_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1558302: Warning: Identifier `\clknet_7_108_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1558308: Warning: Identifier `\clknet_7_109_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1558314: Warning: Identifier `\clknet_7_110_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1558320: Warning: Identifier `\clknet_7_111_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1558326: Warning: Identifier `\clknet_7_112_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1558332: Warning: Identifier `\clknet_7_113_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1558338: Warning: Identifier `\clknet_7_114_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1558344: Warning: Identifier `\clknet_7_115_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1558350: Warning: Identifier `\clknet_7_116_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1558356: Warning: Identifier `\clknet_7_117_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1558362: Warning: Identifier `\clknet_7_118_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1558368: Warning: Identifier `\clknet_7_119_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1558374: Warning: Identifier `\clknet_7_120_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1558380: Warning: Identifier `\clknet_7_121_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1558386: Warning: Identifier `\clknet_7_122_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1558392: Warning: Identifier `\clknet_7_123_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1558398: Warning: Identifier `\clknet_7_124_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1558404: Warning: Identifier `\clknet_7_125_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1558410: Warning: Identifier `\clknet_7_126_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1558416: Warning: Identifier `\clknet_7_127_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1558422: Warning: Identifier `\clknet_8_0_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1558428: Warning: Identifier `\clknet_8_1_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1558434: Warning: Identifier `\clknet_8_2_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1558440: Warning: Identifier `\clknet_8_3_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1558446: Warning: Identifier `\clknet_8_4_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1558452: Warning: Identifier `\clknet_8_5_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1558458: Warning: Identifier `\clknet_8_6_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1558464: Warning: Identifier `\clknet_8_7_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1558470: Warning: Identifier `\clknet_8_8_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1558476: Warning: Identifier `\clknet_8_9_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1558482: Warning: Identifier `\clknet_8_10_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1558488: Warning: Identifier `\clknet_8_11_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1558494: Warning: Identifier `\clknet_8_12_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1558500: Warning: Identifier `\clknet_8_13_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1558506: Warning: Identifier `\clknet_8_14_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1558512: Warning: Identifier `\clknet_8_15_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1558518: Warning: Identifier `\clknet_8_16_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1558524: Warning: Identifier `\clknet_8_17_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1558530: Warning: Identifier `\clknet_8_18_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1558536: Warning: Identifier `\clknet_8_19_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1558542: Warning: Identifier `\clknet_8_20_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1558548: Warning: Identifier `\clknet_8_21_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1558554: Warning: Identifier `\clknet_8_22_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1558560: Warning: Identifier `\clknet_8_23_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1558566: Warning: Identifier `\clknet_8_24_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1558572: Warning: Identifier `\clknet_8_25_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1558578: Warning: Identifier `\clknet_8_26_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1558584: Warning: Identifier `\clknet_8_27_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1558590: Warning: Identifier `\clknet_8_28_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1558596: Warning: Identifier `\clknet_8_29_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1558602: Warning: Identifier `\clknet_8_30_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1558608: Warning: Identifier `\clknet_8_31_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1558614: Warning: Identifier `\clknet_8_32_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1558620: Warning: Identifier `\clknet_8_33_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1558626: Warning: Identifier `\clknet_8_34_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1558632: Warning: Identifier `\clknet_8_35_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1558638: Warning: Identifier `\clknet_8_36_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1558644: Warning: Identifier `\clknet_8_37_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1558650: Warning: Identifier `\clknet_8_38_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1558656: Warning: Identifier `\clknet_8_39_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1558662: Warning: Identifier `\clknet_8_40_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1558668: Warning: Identifier `\clknet_8_41_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1558674: Warning: Identifier `\clknet_8_42_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1558680: Warning: Identifier `\clknet_8_43_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1558686: Warning: Identifier `\clknet_8_44_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1558692: Warning: Identifier `\clknet_8_45_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1558698: Warning: Identifier `\clknet_8_46_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1558704: Warning: Identifier `\clknet_8_47_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1558710: Warning: Identifier `\clknet_8_48_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1558716: Warning: Identifier `\clknet_8_49_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1558722: Warning: Identifier `\clknet_8_50_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1558728: Warning: Identifier `\clknet_8_51_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1558734: Warning: Identifier `\clknet_8_52_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1558740: Warning: Identifier `\clknet_8_53_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1558746: Warning: Identifier `\clknet_8_54_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1558752: Warning: Identifier `\clknet_8_55_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1558758: Warning: Identifier `\clknet_8_56_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1558764: Warning: Identifier `\clknet_8_57_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1558770: Warning: Identifier `\clknet_8_58_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1558776: Warning: Identifier `\clknet_8_59_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1558782: Warning: Identifier `\clknet_8_60_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1558788: Warning: Identifier `\clknet_8_61_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1558794: Warning: Identifier `\clknet_8_62_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1558800: Warning: Identifier `\clknet_8_63_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1558806: Warning: Identifier `\clknet_8_64_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1558812: Warning: Identifier `\clknet_8_65_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1558818: Warning: Identifier `\clknet_8_66_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1558824: Warning: Identifier `\clknet_8_67_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1558830: Warning: Identifier `\clknet_8_68_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1558836: Warning: Identifier `\clknet_8_69_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1558842: Warning: Identifier `\clknet_8_70_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1558848: Warning: Identifier `\clknet_8_71_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1558854: Warning: Identifier `\clknet_8_72_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1558860: Warning: Identifier `\clknet_8_73_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1558866: Warning: Identifier `\clknet_8_74_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1558872: Warning: Identifier `\clknet_8_75_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1558878: Warning: Identifier `\clknet_8_76_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1558884: Warning: Identifier `\clknet_8_77_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1558890: Warning: Identifier `\clknet_8_78_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1558896: Warning: Identifier `\clknet_8_79_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1558902: Warning: Identifier `\clknet_8_80_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1558908: Warning: Identifier `\clknet_8_81_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1558914: Warning: Identifier `\clknet_8_82_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1558920: Warning: Identifier `\clknet_8_83_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1558926: Warning: Identifier `\clknet_8_84_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1558932: Warning: Identifier `\clknet_8_85_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1558938: Warning: Identifier `\clknet_8_86_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1558944: Warning: Identifier `\clknet_8_87_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1558950: Warning: Identifier `\clknet_8_88_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1558956: Warning: Identifier `\clknet_8_89_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1558962: Warning: Identifier `\clknet_8_90_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1558968: Warning: Identifier `\clknet_8_91_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1558974: Warning: Identifier `\clknet_8_92_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1558980: Warning: Identifier `\clknet_8_93_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1558986: Warning: Identifier `\clknet_8_94_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1558992: Warning: Identifier `\clknet_8_95_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1558998: Warning: Identifier `\clknet_8_96_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1559004: Warning: Identifier `\clknet_8_97_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1559010: Warning: Identifier `\clknet_8_98_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1559016: Warning: Identifier `\clknet_8_99_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1559022: Warning: Identifier `\clknet_8_100_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1559028: Warning: Identifier `\clknet_8_101_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1559034: Warning: Identifier `\clknet_8_102_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1559040: Warning: Identifier `\clknet_8_103_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1559046: Warning: Identifier `\clknet_8_104_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1559052: Warning: Identifier `\clknet_8_105_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1559058: Warning: Identifier `\clknet_8_106_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1559064: Warning: Identifier `\clknet_8_107_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1559070: Warning: Identifier `\clknet_8_108_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1559076: Warning: Identifier `\clknet_8_109_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1559082: Warning: Identifier `\clknet_8_110_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1559088: Warning: Identifier `\clknet_8_111_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1559094: Warning: Identifier `\clknet_8_112_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1559100: Warning: Identifier `\clknet_8_113_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1559106: Warning: Identifier `\clknet_8_114_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1559112: Warning: Identifier `\clknet_8_115_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1559118: Warning: Identifier `\clknet_8_116_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1559124: Warning: Identifier `\clknet_8_117_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1559130: Warning: Identifier `\clknet_8_118_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1559136: Warning: Identifier `\clknet_8_119_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1559142: Warning: Identifier `\clknet_8_120_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1559148: Warning: Identifier `\clknet_8_121_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1559154: Warning: Identifier `\clknet_8_122_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1559160: Warning: Identifier `\clknet_8_123_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1559166: Warning: Identifier `\clknet_8_124_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1559172: Warning: Identifier `\clknet_8_125_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1559178: Warning: Identifier `\clknet_8_126_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1559184: Warning: Identifier `\clknet_8_127_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1559190: Warning: Identifier `\clknet_8_128_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1559196: Warning: Identifier `\clknet_8_129_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1559202: Warning: Identifier `\clknet_8_130_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1559208: Warning: Identifier `\clknet_8_131_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1559214: Warning: Identifier `\clknet_8_132_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1559220: Warning: Identifier `\clknet_8_133_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1559226: Warning: Identifier `\clknet_8_134_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1559232: Warning: Identifier `\clknet_8_135_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1559238: Warning: Identifier `\clknet_8_136_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1559244: Warning: Identifier `\clknet_8_137_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1559250: Warning: Identifier `\clknet_8_138_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1559256: Warning: Identifier `\clknet_8_139_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1559262: Warning: Identifier `\clknet_8_140_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1559268: Warning: Identifier `\clknet_8_141_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1559274: Warning: Identifier `\clknet_8_142_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1559280: Warning: Identifier `\clknet_8_143_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1559286: Warning: Identifier `\clknet_8_144_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1559292: Warning: Identifier `\clknet_8_145_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1559298: Warning: Identifier `\clknet_8_146_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1559304: Warning: Identifier `\clknet_8_147_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1559310: Warning: Identifier `\clknet_8_148_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1559316: Warning: Identifier `\clknet_8_149_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1559322: Warning: Identifier `\clknet_8_150_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1559328: Warning: Identifier `\clknet_8_151_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1559334: Warning: Identifier `\clknet_8_152_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1559340: Warning: Identifier `\clknet_8_153_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1559346: Warning: Identifier `\clknet_8_154_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1559352: Warning: Identifier `\clknet_8_155_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1559358: Warning: Identifier `\clknet_8_156_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1559364: Warning: Identifier `\clknet_8_157_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1559370: Warning: Identifier `\clknet_8_158_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1559376: Warning: Identifier `\clknet_8_159_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1559382: Warning: Identifier `\clknet_8_160_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1559388: Warning: Identifier `\clknet_8_161_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1559394: Warning: Identifier `\clknet_8_162_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1559400: Warning: Identifier `\clknet_8_163_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1559406: Warning: Identifier `\clknet_8_164_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1559412: Warning: Identifier `\clknet_8_165_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1559418: Warning: Identifier `\clknet_8_166_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1559424: Warning: Identifier `\clknet_8_167_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1559430: Warning: Identifier `\clknet_8_168_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1559436: Warning: Identifier `\clknet_8_169_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1559442: Warning: Identifier `\clknet_8_170_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1559448: Warning: Identifier `\clknet_8_171_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1559454: Warning: Identifier `\clknet_8_172_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1559460: Warning: Identifier `\clknet_8_173_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1559466: Warning: Identifier `\clknet_8_174_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1559472: Warning: Identifier `\clknet_8_175_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1559478: Warning: Identifier `\clknet_8_176_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1559484: Warning: Identifier `\clknet_8_177_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1559490: Warning: Identifier `\clknet_8_178_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1559496: Warning: Identifier `\clknet_8_179_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1559502: Warning: Identifier `\clknet_8_180_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1559508: Warning: Identifier `\clknet_8_181_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1559514: Warning: Identifier `\clknet_8_182_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1559520: Warning: Identifier `\clknet_8_183_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1559526: Warning: Identifier `\clknet_8_184_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1559532: Warning: Identifier `\clknet_8_185_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1559538: Warning: Identifier `\clknet_8_186_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1559544: Warning: Identifier `\clknet_8_187_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1559550: Warning: Identifier `\clknet_8_188_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1559556: Warning: Identifier `\clknet_8_189_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1559562: Warning: Identifier `\clknet_8_190_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1559568: Warning: Identifier `\clknet_8_191_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1559574: Warning: Identifier `\clknet_8_192_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1559580: Warning: Identifier `\clknet_8_193_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1559586: Warning: Identifier `\clknet_8_194_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1559592: Warning: Identifier `\clknet_8_195_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1559598: Warning: Identifier `\clknet_8_196_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1559604: Warning: Identifier `\clknet_8_197_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1559610: Warning: Identifier `\clknet_8_198_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1559616: Warning: Identifier `\clknet_8_199_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1559622: Warning: Identifier `\clknet_8_200_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1559628: Warning: Identifier `\clknet_8_201_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1559634: Warning: Identifier `\clknet_8_202_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1559640: Warning: Identifier `\clknet_8_203_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1559646: Warning: Identifier `\clknet_8_204_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1559652: Warning: Identifier `\clknet_8_205_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1559658: Warning: Identifier `\clknet_8_206_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1559664: Warning: Identifier `\clknet_8_207_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1559670: Warning: Identifier `\clknet_8_208_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1559676: Warning: Identifier `\clknet_8_209_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1559682: Warning: Identifier `\clknet_8_210_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1559688: Warning: Identifier `\clknet_8_211_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1559694: Warning: Identifier `\clknet_8_212_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1559700: Warning: Identifier `\clknet_8_213_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1559706: Warning: Identifier `\clknet_8_214_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1559712: Warning: Identifier `\clknet_8_215_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1559718: Warning: Identifier `\clknet_8_216_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1559724: Warning: Identifier `\clknet_8_217_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1559730: Warning: Identifier `\clknet_8_218_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1559736: Warning: Identifier `\clknet_8_219_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1559742: Warning: Identifier `\clknet_8_220_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1559748: Warning: Identifier `\clknet_8_221_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1559754: Warning: Identifier `\clknet_8_222_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1559760: Warning: Identifier `\clknet_8_223_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1559766: Warning: Identifier `\clknet_8_224_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1559772: Warning: Identifier `\clknet_8_225_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1559778: Warning: Identifier `\clknet_8_226_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1559784: Warning: Identifier `\clknet_8_227_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1559790: Warning: Identifier `\clknet_8_228_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1559796: Warning: Identifier `\clknet_8_229_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1559802: Warning: Identifier `\clknet_8_230_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1559808: Warning: Identifier `\clknet_8_231_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1559814: Warning: Identifier `\clknet_8_232_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1559820: Warning: Identifier `\clknet_8_233_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1559826: Warning: Identifier `\clknet_8_234_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1559832: Warning: Identifier `\clknet_8_235_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1559838: Warning: Identifier `\clknet_8_236_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1559844: Warning: Identifier `\clknet_8_237_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1559850: Warning: Identifier `\clknet_8_238_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1559856: Warning: Identifier `\clknet_8_239_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1559862: Warning: Identifier `\clknet_8_240_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1559868: Warning: Identifier `\clknet_8_241_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1559874: Warning: Identifier `\clknet_8_242_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1559880: Warning: Identifier `\clknet_8_243_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1559886: Warning: Identifier `\clknet_8_244_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1559892: Warning: Identifier `\clknet_8_245_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1559898: Warning: Identifier `\clknet_8_246_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1559904: Warning: Identifier `\clknet_8_247_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1559910: Warning: Identifier `\clknet_8_248_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1559916: Warning: Identifier `\clknet_8_249_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1559922: Warning: Identifier `\clknet_8_250_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1559928: Warning: Identifier `\clknet_8_251_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1559934: Warning: Identifier `\clknet_8_252_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1559940: Warning: Identifier `\clknet_8_253_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1559946: Warning: Identifier `\clknet_8_254_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1559952: Warning: Identifier `\clknet_8_255_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1559958: Warning: Identifier `\clknet_9_0_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1559964: Warning: Identifier `\clknet_9_1_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1559970: Warning: Identifier `\clknet_9_2_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1559976: Warning: Identifier `\clknet_9_3_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1559982: Warning: Identifier `\clknet_9_4_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1559988: Warning: Identifier `\clknet_9_5_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1559994: Warning: Identifier `\clknet_9_6_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1560000: Warning: Identifier `\clknet_9_7_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1560006: Warning: Identifier `\clknet_9_8_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1560012: Warning: Identifier `\clknet_9_9_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1560018: Warning: Identifier `\clknet_9_10_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1560024: Warning: Identifier `\clknet_9_11_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1560030: Warning: Identifier `\clknet_9_12_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1560036: Warning: Identifier `\clknet_9_13_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1560042: Warning: Identifier `\clknet_9_14_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1560048: Warning: Identifier `\clknet_9_15_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1560054: Warning: Identifier `\clknet_9_16_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1560060: Warning: Identifier `\clknet_9_17_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1560066: Warning: Identifier `\clknet_9_18_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1560072: Warning: Identifier `\clknet_9_19_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1560078: Warning: Identifier `\clknet_9_20_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1560084: Warning: Identifier `\clknet_9_21_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1560090: Warning: Identifier `\clknet_9_22_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1560096: Warning: Identifier `\clknet_9_23_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1560102: Warning: Identifier `\clknet_9_24_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1560108: Warning: Identifier `\clknet_9_25_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1560114: Warning: Identifier `\clknet_9_26_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1560120: Warning: Identifier `\clknet_9_27_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1560126: Warning: Identifier `\clknet_9_28_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1560132: Warning: Identifier `\clknet_9_29_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1560138: Warning: Identifier `\clknet_9_30_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1560144: Warning: Identifier `\clknet_9_31_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1560150: Warning: Identifier `\clknet_9_32_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1560156: Warning: Identifier `\clknet_9_33_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1560162: Warning: Identifier `\clknet_9_34_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1560168: Warning: Identifier `\clknet_9_35_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1560174: Warning: Identifier `\clknet_9_36_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1560180: Warning: Identifier `\clknet_9_37_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1560186: Warning: Identifier `\clknet_9_38_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1560192: Warning: Identifier `\clknet_9_39_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1560198: Warning: Identifier `\clknet_9_40_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1560204: Warning: Identifier `\clknet_9_41_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1560210: Warning: Identifier `\clknet_9_42_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1560216: Warning: Identifier `\clknet_9_43_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1560222: Warning: Identifier `\clknet_9_44_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1560228: Warning: Identifier `\clknet_9_45_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1560234: Warning: Identifier `\clknet_9_46_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1560240: Warning: Identifier `\clknet_9_47_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1560246: Warning: Identifier `\clknet_9_48_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1560252: Warning: Identifier `\clknet_9_49_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1560258: Warning: Identifier `\clknet_9_50_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1560264: Warning: Identifier `\clknet_9_51_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1560270: Warning: Identifier `\clknet_9_52_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1560276: Warning: Identifier `\clknet_9_53_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1560282: Warning: Identifier `\clknet_9_54_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1560288: Warning: Identifier `\clknet_9_55_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1560294: Warning: Identifier `\clknet_9_56_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1560300: Warning: Identifier `\clknet_9_57_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1560306: Warning: Identifier `\clknet_9_58_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1560312: Warning: Identifier `\clknet_9_59_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1560318: Warning: Identifier `\clknet_9_60_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1560324: Warning: Identifier `\clknet_9_61_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1560330: Warning: Identifier `\clknet_9_62_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1560336: Warning: Identifier `\clknet_9_63_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1560342: Warning: Identifier `\clknet_9_64_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1560348: Warning: Identifier `\clknet_9_65_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1560354: Warning: Identifier `\clknet_9_66_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1560360: Warning: Identifier `\clknet_9_67_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1560366: Warning: Identifier `\clknet_9_68_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1560372: Warning: Identifier `\clknet_9_69_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1560378: Warning: Identifier `\clknet_9_70_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1560384: Warning: Identifier `\clknet_9_71_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1560390: Warning: Identifier `\clknet_9_72_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1560396: Warning: Identifier `\clknet_9_73_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1560402: Warning: Identifier `\clknet_9_74_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1560408: Warning: Identifier `\clknet_9_75_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1560414: Warning: Identifier `\clknet_9_76_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1560420: Warning: Identifier `\clknet_9_77_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1560426: Warning: Identifier `\clknet_9_78_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1560432: Warning: Identifier `\clknet_9_79_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1560438: Warning: Identifier `\clknet_9_80_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1560444: Warning: Identifier `\clknet_9_81_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1560450: Warning: Identifier `\clknet_9_82_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1560456: Warning: Identifier `\clknet_9_83_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1560462: Warning: Identifier `\clknet_9_84_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1560468: Warning: Identifier `\clknet_9_85_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1560474: Warning: Identifier `\clknet_9_86_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1560480: Warning: Identifier `\clknet_9_87_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1560486: Warning: Identifier `\clknet_9_88_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1560492: Warning: Identifier `\clknet_9_89_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1560498: Warning: Identifier `\clknet_9_90_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1560504: Warning: Identifier `\clknet_9_91_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1560510: Warning: Identifier `\clknet_9_92_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1560516: Warning: Identifier `\clknet_9_93_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1560522: Warning: Identifier `\clknet_9_94_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1560528: Warning: Identifier `\clknet_9_95_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1560534: Warning: Identifier `\clknet_9_96_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1560540: Warning: Identifier `\clknet_9_97_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1560546: Warning: Identifier `\clknet_9_98_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1560552: Warning: Identifier `\clknet_9_99_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1560558: Warning: Identifier `\clknet_9_100_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1560564: Warning: Identifier `\clknet_9_101_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1560570: Warning: Identifier `\clknet_9_102_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1560576: Warning: Identifier `\clknet_9_103_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1560582: Warning: Identifier `\clknet_9_104_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1560588: Warning: Identifier `\clknet_9_105_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1560594: Warning: Identifier `\clknet_9_106_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1560600: Warning: Identifier `\clknet_9_107_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1560606: Warning: Identifier `\clknet_9_108_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1560612: Warning: Identifier `\clknet_9_109_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1560618: Warning: Identifier `\clknet_9_110_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1560624: Warning: Identifier `\clknet_9_111_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1560630: Warning: Identifier `\clknet_9_112_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1560636: Warning: Identifier `\clknet_9_113_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1560642: Warning: Identifier `\clknet_9_114_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1560648: Warning: Identifier `\clknet_9_115_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1560654: Warning: Identifier `\clknet_9_116_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1560660: Warning: Identifier `\clknet_9_117_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1560666: Warning: Identifier `\clknet_9_118_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1560672: Warning: Identifier `\clknet_9_119_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1560678: Warning: Identifier `\clknet_9_120_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1560684: Warning: Identifier `\clknet_9_121_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1560690: Warning: Identifier `\clknet_9_122_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1560696: Warning: Identifier `\clknet_9_123_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1560702: Warning: Identifier `\clknet_9_124_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1560708: Warning: Identifier `\clknet_9_125_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1560714: Warning: Identifier `\clknet_9_126_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1560720: Warning: Identifier `\clknet_9_127_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1560726: Warning: Identifier `\clknet_9_128_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1560732: Warning: Identifier `\clknet_9_129_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1560738: Warning: Identifier `\clknet_9_130_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1560744: Warning: Identifier `\clknet_9_131_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1560750: Warning: Identifier `\clknet_9_132_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1560756: Warning: Identifier `\clknet_9_133_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1560762: Warning: Identifier `\clknet_9_134_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1560768: Warning: Identifier `\clknet_9_135_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1560774: Warning: Identifier `\clknet_9_136_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1560780: Warning: Identifier `\clknet_9_137_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1560786: Warning: Identifier `\clknet_9_138_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1560792: Warning: Identifier `\clknet_9_139_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1560798: Warning: Identifier `\clknet_9_140_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1560804: Warning: Identifier `\clknet_9_141_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1560810: Warning: Identifier `\clknet_9_142_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1560816: Warning: Identifier `\clknet_9_143_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1560822: Warning: Identifier `\clknet_9_144_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1560828: Warning: Identifier `\clknet_9_145_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1560834: Warning: Identifier `\clknet_9_146_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1560840: Warning: Identifier `\clknet_9_147_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1560846: Warning: Identifier `\clknet_9_148_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1560852: Warning: Identifier `\clknet_9_149_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1560858: Warning: Identifier `\clknet_9_150_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1560864: Warning: Identifier `\clknet_9_151_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1560870: Warning: Identifier `\clknet_9_152_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1560876: Warning: Identifier `\clknet_9_153_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1560882: Warning: Identifier `\clknet_9_154_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1560888: Warning: Identifier `\clknet_9_155_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1560894: Warning: Identifier `\clknet_9_156_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1560900: Warning: Identifier `\clknet_9_157_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1560906: Warning: Identifier `\clknet_9_158_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1560912: Warning: Identifier `\clknet_9_159_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1560918: Warning: Identifier `\clknet_9_160_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1560924: Warning: Identifier `\clknet_9_161_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1560930: Warning: Identifier `\clknet_9_162_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1560936: Warning: Identifier `\clknet_9_163_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1560942: Warning: Identifier `\clknet_9_164_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1560948: Warning: Identifier `\clknet_9_165_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1560954: Warning: Identifier `\clknet_9_166_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1560960: Warning: Identifier `\clknet_9_167_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1560966: Warning: Identifier `\clknet_9_168_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1560972: Warning: Identifier `\clknet_9_169_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1560978: Warning: Identifier `\clknet_9_170_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1560984: Warning: Identifier `\clknet_9_171_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1560990: Warning: Identifier `\clknet_9_172_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1560996: Warning: Identifier `\clknet_9_173_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1561002: Warning: Identifier `\clknet_9_174_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1561008: Warning: Identifier `\clknet_9_175_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1561014: Warning: Identifier `\clknet_9_176_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1561020: Warning: Identifier `\clknet_9_177_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1561026: Warning: Identifier `\clknet_9_178_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1561032: Warning: Identifier `\clknet_9_179_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1561038: Warning: Identifier `\clknet_9_180_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1561044: Warning: Identifier `\clknet_9_181_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1561050: Warning: Identifier `\clknet_9_182_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1561056: Warning: Identifier `\clknet_9_183_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1561062: Warning: Identifier `\clknet_9_184_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1561068: Warning: Identifier `\clknet_9_185_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1561074: Warning: Identifier `\clknet_9_186_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1561080: Warning: Identifier `\clknet_9_187_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1561086: Warning: Identifier `\clknet_9_188_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1561092: Warning: Identifier `\clknet_9_189_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1561098: Warning: Identifier `\clknet_9_190_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1561104: Warning: Identifier `\clknet_9_191_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1561110: Warning: Identifier `\clknet_9_192_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1561116: Warning: Identifier `\clknet_9_193_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1561122: Warning: Identifier `\clknet_9_194_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1561128: Warning: Identifier `\clknet_9_195_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1561134: Warning: Identifier `\clknet_9_196_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1561140: Warning: Identifier `\clknet_9_197_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1561146: Warning: Identifier `\clknet_9_198_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1561152: Warning: Identifier `\clknet_9_199_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1561158: Warning: Identifier `\clknet_9_200_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1561164: Warning: Identifier `\clknet_9_201_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1561170: Warning: Identifier `\clknet_9_202_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1561176: Warning: Identifier `\clknet_9_203_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1561182: Warning: Identifier `\clknet_9_204_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1561188: Warning: Identifier `\clknet_9_205_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1561194: Warning: Identifier `\clknet_9_206_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1561200: Warning: Identifier `\clknet_9_207_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1561206: Warning: Identifier `\clknet_9_208_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1561212: Warning: Identifier `\clknet_9_209_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1561218: Warning: Identifier `\clknet_9_210_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1561224: Warning: Identifier `\clknet_9_211_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1561230: Warning: Identifier `\clknet_9_212_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1561236: Warning: Identifier `\clknet_9_213_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1561242: Warning: Identifier `\clknet_9_214_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1561248: Warning: Identifier `\clknet_9_215_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1561254: Warning: Identifier `\clknet_9_216_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1561260: Warning: Identifier `\clknet_9_217_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1561266: Warning: Identifier `\clknet_9_218_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1561272: Warning: Identifier `\clknet_9_219_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1561278: Warning: Identifier `\clknet_9_220_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1561284: Warning: Identifier `\clknet_9_221_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1561290: Warning: Identifier `\clknet_9_222_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1561296: Warning: Identifier `\clknet_9_223_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1561302: Warning: Identifier `\clknet_9_224_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1561308: Warning: Identifier `\clknet_9_225_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1561314: Warning: Identifier `\clknet_9_226_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1561320: Warning: Identifier `\clknet_9_227_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1561326: Warning: Identifier `\clknet_9_228_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1561332: Warning: Identifier `\clknet_9_229_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1561338: Warning: Identifier `\clknet_9_230_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1561344: Warning: Identifier `\clknet_9_231_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1561350: Warning: Identifier `\clknet_9_232_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1561356: Warning: Identifier `\clknet_9_233_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1561362: Warning: Identifier `\clknet_9_234_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1561368: Warning: Identifier `\clknet_9_235_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1561374: Warning: Identifier `\clknet_9_236_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1561380: Warning: Identifier `\clknet_9_237_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1561386: Warning: Identifier `\clknet_9_238_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1561392: Warning: Identifier `\clknet_9_239_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1561398: Warning: Identifier `\clknet_9_240_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1561404: Warning: Identifier `\clknet_9_241_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1561410: Warning: Identifier `\clknet_9_242_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1561416: Warning: Identifier `\clknet_9_243_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1561422: Warning: Identifier `\clknet_9_244_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1561428: Warning: Identifier `\clknet_9_245_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1561434: Warning: Identifier `\clknet_9_246_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1561440: Warning: Identifier `\clknet_9_247_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1561446: Warning: Identifier `\clknet_9_248_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1561452: Warning: Identifier `\clknet_9_249_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1561458: Warning: Identifier `\clknet_9_250_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1561464: Warning: Identifier `\clknet_9_251_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1561470: Warning: Identifier `\clknet_9_252_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1561476: Warning: Identifier `\clknet_9_253_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1561482: Warning: Identifier `\clknet_9_254_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1561488: Warning: Identifier `\clknet_9_255_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1561494: Warning: Identifier `\clknet_9_256_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1561500: Warning: Identifier `\clknet_9_257_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1561506: Warning: Identifier `\clknet_9_258_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1561512: Warning: Identifier `\clknet_9_259_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1561518: Warning: Identifier `\clknet_9_260_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1561524: Warning: Identifier `\clknet_9_261_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1561530: Warning: Identifier `\clknet_9_262_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1561536: Warning: Identifier `\clknet_9_263_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1561542: Warning: Identifier `\clknet_9_264_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1561548: Warning: Identifier `\clknet_9_265_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1561554: Warning: Identifier `\clknet_9_266_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1561560: Warning: Identifier `\clknet_9_267_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1561566: Warning: Identifier `\clknet_9_268_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1561572: Warning: Identifier `\clknet_9_269_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1561578: Warning: Identifier `\clknet_9_270_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1561584: Warning: Identifier `\clknet_9_271_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1561590: Warning: Identifier `\clknet_9_272_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1561596: Warning: Identifier `\clknet_9_273_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1561602: Warning: Identifier `\clknet_9_274_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1561608: Warning: Identifier `\clknet_9_275_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1561614: Warning: Identifier `\clknet_9_276_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1561620: Warning: Identifier `\clknet_9_277_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1561626: Warning: Identifier `\clknet_9_278_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1561632: Warning: Identifier `\clknet_9_279_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1561638: Warning: Identifier `\clknet_9_280_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1561644: Warning: Identifier `\clknet_9_281_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1561650: Warning: Identifier `\clknet_9_282_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1561656: Warning: Identifier `\clknet_9_283_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1561662: Warning: Identifier `\clknet_9_284_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1561668: Warning: Identifier `\clknet_9_285_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1561674: Warning: Identifier `\clknet_9_286_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1561680: Warning: Identifier `\clknet_9_287_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1561686: Warning: Identifier `\clknet_9_288_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1561692: Warning: Identifier `\clknet_9_289_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1561698: Warning: Identifier `\clknet_9_290_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1561704: Warning: Identifier `\clknet_9_291_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1561710: Warning: Identifier `\clknet_9_292_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1561716: Warning: Identifier `\clknet_9_293_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1561722: Warning: Identifier `\clknet_9_294_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1561728: Warning: Identifier `\clknet_9_295_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1561734: Warning: Identifier `\clknet_9_296_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1561740: Warning: Identifier `\clknet_9_297_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1561746: Warning: Identifier `\clknet_9_298_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1561752: Warning: Identifier `\clknet_9_299_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1561758: Warning: Identifier `\clknet_9_300_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1561764: Warning: Identifier `\clknet_9_301_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1561770: Warning: Identifier `\clknet_9_302_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1561776: Warning: Identifier `\clknet_9_303_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1561782: Warning: Identifier `\clknet_9_304_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1561788: Warning: Identifier `\clknet_9_305_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1561794: Warning: Identifier `\clknet_9_306_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1561800: Warning: Identifier `\clknet_9_307_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1561806: Warning: Identifier `\clknet_9_308_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1561812: Warning: Identifier `\clknet_9_309_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1561818: Warning: Identifier `\clknet_9_310_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1561824: Warning: Identifier `\clknet_9_311_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1561830: Warning: Identifier `\clknet_9_312_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1561836: Warning: Identifier `\clknet_9_313_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1561842: Warning: Identifier `\clknet_9_314_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1561848: Warning: Identifier `\clknet_9_315_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1561854: Warning: Identifier `\clknet_9_316_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1561860: Warning: Identifier `\clknet_9_317_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1561866: Warning: Identifier `\clknet_9_318_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1561872: Warning: Identifier `\clknet_9_319_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1561878: Warning: Identifier `\clknet_9_320_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1561884: Warning: Identifier `\clknet_9_321_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1561890: Warning: Identifier `\clknet_9_322_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1561896: Warning: Identifier `\clknet_9_323_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1561902: Warning: Identifier `\clknet_9_324_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1561908: Warning: Identifier `\clknet_9_325_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1561914: Warning: Identifier `\clknet_9_326_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1561920: Warning: Identifier `\clknet_9_327_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1561926: Warning: Identifier `\clknet_9_328_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1561932: Warning: Identifier `\clknet_9_329_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1561938: Warning: Identifier `\clknet_9_330_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1561944: Warning: Identifier `\clknet_9_331_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1561950: Warning: Identifier `\clknet_9_332_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1561956: Warning: Identifier `\clknet_9_333_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1561962: Warning: Identifier `\clknet_9_334_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1561968: Warning: Identifier `\clknet_9_335_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1561974: Warning: Identifier `\clknet_9_336_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1561980: Warning: Identifier `\clknet_9_337_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1561986: Warning: Identifier `\clknet_9_338_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1561992: Warning: Identifier `\clknet_9_339_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1561998: Warning: Identifier `\clknet_9_340_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1562004: Warning: Identifier `\clknet_9_341_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1562010: Warning: Identifier `\clknet_9_342_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1562016: Warning: Identifier `\clknet_9_343_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1562022: Warning: Identifier `\clknet_9_344_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1562028: Warning: Identifier `\clknet_9_345_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1562034: Warning: Identifier `\clknet_9_346_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1562040: Warning: Identifier `\clknet_9_347_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1562046: Warning: Identifier `\clknet_9_348_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1562052: Warning: Identifier `\clknet_9_349_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1562058: Warning: Identifier `\clknet_9_350_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1562064: Warning: Identifier `\clknet_9_351_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1562070: Warning: Identifier `\clknet_9_352_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1562076: Warning: Identifier `\clknet_9_353_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1562082: Warning: Identifier `\clknet_9_354_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1562088: Warning: Identifier `\clknet_9_355_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1562094: Warning: Identifier `\clknet_9_356_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1562100: Warning: Identifier `\clknet_9_357_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1562106: Warning: Identifier `\clknet_9_358_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1562112: Warning: Identifier `\clknet_9_359_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1562118: Warning: Identifier `\clknet_9_360_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1562124: Warning: Identifier `\clknet_9_361_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1562130: Warning: Identifier `\clknet_9_362_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1562136: Warning: Identifier `\clknet_9_363_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1562142: Warning: Identifier `\clknet_9_364_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1562148: Warning: Identifier `\clknet_9_365_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1562154: Warning: Identifier `\clknet_9_366_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1562160: Warning: Identifier `\clknet_9_367_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1562166: Warning: Identifier `\clknet_9_368_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1562172: Warning: Identifier `\clknet_9_369_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1562178: Warning: Identifier `\clknet_9_370_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1562184: Warning: Identifier `\clknet_9_371_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1562190: Warning: Identifier `\clknet_9_372_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1562196: Warning: Identifier `\clknet_9_373_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1562202: Warning: Identifier `\clknet_9_374_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1562208: Warning: Identifier `\clknet_9_375_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1562214: Warning: Identifier `\clknet_9_376_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1562220: Warning: Identifier `\clknet_9_377_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1562226: Warning: Identifier `\clknet_9_378_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1562232: Warning: Identifier `\clknet_9_379_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1562238: Warning: Identifier `\clknet_9_380_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1562244: Warning: Identifier `\clknet_9_381_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1562250: Warning: Identifier `\clknet_9_382_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1562256: Warning: Identifier `\clknet_9_383_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1562262: Warning: Identifier `\clknet_9_384_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1562268: Warning: Identifier `\clknet_9_385_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1562274: Warning: Identifier `\clknet_9_386_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1562280: Warning: Identifier `\clknet_9_387_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1562286: Warning: Identifier `\clknet_9_388_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1562292: Warning: Identifier `\clknet_9_389_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1562298: Warning: Identifier `\clknet_9_390_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1562304: Warning: Identifier `\clknet_9_391_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1562310: Warning: Identifier `\clknet_9_392_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1562316: Warning: Identifier `\clknet_9_393_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1562322: Warning: Identifier `\clknet_9_394_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1562328: Warning: Identifier `\clknet_9_395_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1562334: Warning: Identifier `\clknet_9_396_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1562340: Warning: Identifier `\clknet_9_397_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1562346: Warning: Identifier `\clknet_9_398_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1562352: Warning: Identifier `\clknet_9_399_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1562358: Warning: Identifier `\clknet_9_400_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1562364: Warning: Identifier `\clknet_9_401_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1562370: Warning: Identifier `\clknet_9_402_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1562376: Warning: Identifier `\clknet_9_403_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1562382: Warning: Identifier `\clknet_9_404_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1562388: Warning: Identifier `\clknet_9_405_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1562394: Warning: Identifier `\clknet_9_406_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1562400: Warning: Identifier `\clknet_9_407_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1562406: Warning: Identifier `\clknet_9_408_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1562412: Warning: Identifier `\clknet_9_409_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1562418: Warning: Identifier `\clknet_9_410_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1562424: Warning: Identifier `\clknet_9_411_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1562430: Warning: Identifier `\clknet_9_412_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1562436: Warning: Identifier `\clknet_9_413_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1562442: Warning: Identifier `\clknet_9_414_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1562448: Warning: Identifier `\clknet_9_415_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1562454: Warning: Identifier `\clknet_9_416_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1562460: Warning: Identifier `\clknet_9_417_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1562466: Warning: Identifier `\clknet_9_418_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1562472: Warning: Identifier `\clknet_9_419_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1562478: Warning: Identifier `\clknet_9_420_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1562484: Warning: Identifier `\clknet_9_421_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1562490: Warning: Identifier `\clknet_9_422_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1562496: Warning: Identifier `\clknet_9_423_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1562502: Warning: Identifier `\clknet_9_424_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1562508: Warning: Identifier `\clknet_9_425_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1562514: Warning: Identifier `\clknet_9_426_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1562520: Warning: Identifier `\clknet_9_427_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1562526: Warning: Identifier `\clknet_9_428_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1562532: Warning: Identifier `\clknet_9_429_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1562538: Warning: Identifier `\clknet_9_430_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1562544: Warning: Identifier `\clknet_9_431_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1562550: Warning: Identifier `\clknet_9_432_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1562556: Warning: Identifier `\clknet_9_433_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1562562: Warning: Identifier `\clknet_9_434_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1562568: Warning: Identifier `\clknet_9_435_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1562574: Warning: Identifier `\clknet_9_436_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1562580: Warning: Identifier `\clknet_9_437_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1562586: Warning: Identifier `\clknet_9_438_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1562592: Warning: Identifier `\clknet_9_439_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1562598: Warning: Identifier `\clknet_9_440_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1562604: Warning: Identifier `\clknet_9_441_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1562610: Warning: Identifier `\clknet_9_442_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1562616: Warning: Identifier `\clknet_9_443_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1562622: Warning: Identifier `\clknet_9_444_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1562628: Warning: Identifier `\clknet_9_445_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1562634: Warning: Identifier `\clknet_9_446_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1562640: Warning: Identifier `\clknet_9_447_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1562646: Warning: Identifier `\clknet_9_448_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1562652: Warning: Identifier `\clknet_9_449_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1562658: Warning: Identifier `\clknet_9_450_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1562664: Warning: Identifier `\clknet_9_451_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1562670: Warning: Identifier `\clknet_9_452_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1562676: Warning: Identifier `\clknet_9_453_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1562682: Warning: Identifier `\clknet_9_454_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1562688: Warning: Identifier `\clknet_9_455_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1562694: Warning: Identifier `\clknet_9_456_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1562700: Warning: Identifier `\clknet_9_457_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1562706: Warning: Identifier `\clknet_9_458_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1562712: Warning: Identifier `\clknet_9_459_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1562718: Warning: Identifier `\clknet_9_460_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1562724: Warning: Identifier `\clknet_9_461_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1562730: Warning: Identifier `\clknet_9_462_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1562736: Warning: Identifier `\clknet_9_463_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1562742: Warning: Identifier `\clknet_9_464_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1562748: Warning: Identifier `\clknet_9_465_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1562754: Warning: Identifier `\clknet_9_466_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1562760: Warning: Identifier `\clknet_9_467_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1562766: Warning: Identifier `\clknet_9_468_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1562772: Warning: Identifier `\clknet_9_469_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1562778: Warning: Identifier `\clknet_9_470_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1562784: Warning: Identifier `\clknet_9_471_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1562790: Warning: Identifier `\clknet_9_472_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1562796: Warning: Identifier `\clknet_9_473_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1562802: Warning: Identifier `\clknet_9_474_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1562808: Warning: Identifier `\clknet_9_475_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1562814: Warning: Identifier `\clknet_9_476_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1562820: Warning: Identifier `\clknet_9_477_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1562826: Warning: Identifier `\clknet_9_478_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1562832: Warning: Identifier `\clknet_9_479_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1562838: Warning: Identifier `\clknet_9_480_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1562844: Warning: Identifier `\clknet_9_481_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1562850: Warning: Identifier `\clknet_9_482_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1562856: Warning: Identifier `\clknet_9_483_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1562862: Warning: Identifier `\clknet_9_484_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1562868: Warning: Identifier `\clknet_9_485_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1562874: Warning: Identifier `\clknet_9_486_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1562880: Warning: Identifier `\clknet_9_487_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1562886: Warning: Identifier `\clknet_9_488_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1562892: Warning: Identifier `\clknet_9_489_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1562898: Warning: Identifier `\clknet_9_490_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1562904: Warning: Identifier `\clknet_9_491_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1562910: Warning: Identifier `\clknet_9_492_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1562916: Warning: Identifier `\clknet_9_493_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1562922: Warning: Identifier `\clknet_9_494_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1562928: Warning: Identifier `\clknet_9_495_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1562934: Warning: Identifier `\clknet_9_496_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1562940: Warning: Identifier `\clknet_9_497_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1562946: Warning: Identifier `\clknet_9_498_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1562952: Warning: Identifier `\clknet_9_499_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1562958: Warning: Identifier `\clknet_9_500_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1562964: Warning: Identifier `\clknet_9_501_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1562970: Warning: Identifier `\clknet_9_502_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1562976: Warning: Identifier `\clknet_9_503_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1562982: Warning: Identifier `\clknet_9_504_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1562988: Warning: Identifier `\clknet_9_505_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1562994: Warning: Identifier `\clknet_9_506_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1563000: Warning: Identifier `\clknet_9_507_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1563006: Warning: Identifier `\clknet_9_508_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1563012: Warning: Identifier `\clknet_9_509_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1563018: Warning: Identifier `\clknet_9_510_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1563024: Warning: Identifier `\clknet_9_511_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1563030: Warning: Identifier `\clknet_10_0_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1563036: Warning: Identifier `\clknet_10_1_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1563042: Warning: Identifier `\clknet_10_2_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1563048: Warning: Identifier `\clknet_10_3_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1563054: Warning: Identifier `\clknet_10_4_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1563060: Warning: Identifier `\clknet_10_5_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1563066: Warning: Identifier `\clknet_10_6_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1563072: Warning: Identifier `\clknet_10_7_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1563078: Warning: Identifier `\clknet_10_8_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1563084: Warning: Identifier `\clknet_10_9_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1563090: Warning: Identifier `\clknet_10_10_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1563096: Warning: Identifier `\clknet_10_11_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1563102: Warning: Identifier `\clknet_10_12_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1563108: Warning: Identifier `\clknet_10_13_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1563114: Warning: Identifier `\clknet_10_14_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1563120: Warning: Identifier `\clknet_10_15_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1563126: Warning: Identifier `\clknet_10_16_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1563132: Warning: Identifier `\clknet_10_17_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1563138: Warning: Identifier `\clknet_10_18_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1563144: Warning: Identifier `\clknet_10_19_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1563150: Warning: Identifier `\clknet_10_20_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1563156: Warning: Identifier `\clknet_10_21_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1563162: Warning: Identifier `\clknet_10_22_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1563168: Warning: Identifier `\clknet_10_23_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1563174: Warning: Identifier `\clknet_10_24_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1563180: Warning: Identifier `\clknet_10_25_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1563186: Warning: Identifier `\clknet_10_26_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1563192: Warning: Identifier `\clknet_10_27_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1563198: Warning: Identifier `\clknet_10_28_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1563204: Warning: Identifier `\clknet_10_29_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1563210: Warning: Identifier `\clknet_10_30_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1563216: Warning: Identifier `\clknet_10_31_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1563222: Warning: Identifier `\clknet_10_32_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1563228: Warning: Identifier `\clknet_10_33_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1563234: Warning: Identifier `\clknet_10_34_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1563240: Warning: Identifier `\clknet_10_35_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1563246: Warning: Identifier `\clknet_10_36_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1563252: Warning: Identifier `\clknet_10_37_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1563258: Warning: Identifier `\clknet_10_38_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1563264: Warning: Identifier `\clknet_10_39_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1563270: Warning: Identifier `\clknet_10_40_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1563276: Warning: Identifier `\clknet_10_41_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1563282: Warning: Identifier `\clknet_10_42_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1563288: Warning: Identifier `\clknet_10_43_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1563294: Warning: Identifier `\clknet_10_44_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1563300: Warning: Identifier `\clknet_10_45_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1563306: Warning: Identifier `\clknet_10_46_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1563312: Warning: Identifier `\clknet_10_47_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1563318: Warning: Identifier `\clknet_10_48_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1563324: Warning: Identifier `\clknet_10_49_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1563330: Warning: Identifier `\clknet_10_50_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1563336: Warning: Identifier `\clknet_10_51_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1563342: Warning: Identifier `\clknet_10_52_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1563348: Warning: Identifier `\clknet_10_53_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1563354: Warning: Identifier `\clknet_10_54_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1563360: Warning: Identifier `\clknet_10_55_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1563366: Warning: Identifier `\clknet_10_56_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1563372: Warning: Identifier `\clknet_10_57_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1563378: Warning: Identifier `\clknet_10_58_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1563384: Warning: Identifier `\clknet_10_59_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1563390: Warning: Identifier `\clknet_10_60_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1563396: Warning: Identifier `\clknet_10_61_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1563402: Warning: Identifier `\clknet_10_62_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1563408: Warning: Identifier `\clknet_10_63_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1563414: Warning: Identifier `\clknet_10_64_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1563420: Warning: Identifier `\clknet_10_65_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1563426: Warning: Identifier `\clknet_10_66_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1563432: Warning: Identifier `\clknet_10_67_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1563438: Warning: Identifier `\clknet_10_68_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1563444: Warning: Identifier `\clknet_10_69_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1563450: Warning: Identifier `\clknet_10_70_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1563456: Warning: Identifier `\clknet_10_71_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1563462: Warning: Identifier `\clknet_10_72_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1563468: Warning: Identifier `\clknet_10_73_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1563474: Warning: Identifier `\clknet_10_74_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1563480: Warning: Identifier `\clknet_10_75_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1563486: Warning: Identifier `\clknet_10_76_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1563492: Warning: Identifier `\clknet_10_77_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1563498: Warning: Identifier `\clknet_10_78_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1563504: Warning: Identifier `\clknet_10_79_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1563510: Warning: Identifier `\clknet_10_80_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1563516: Warning: Identifier `\clknet_10_81_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1563522: Warning: Identifier `\clknet_10_82_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1563528: Warning: Identifier `\clknet_10_83_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1563534: Warning: Identifier `\clknet_10_84_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1563540: Warning: Identifier `\clknet_10_85_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1563546: Warning: Identifier `\clknet_10_86_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1563552: Warning: Identifier `\clknet_10_87_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1563558: Warning: Identifier `\clknet_10_88_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1563564: Warning: Identifier `\clknet_10_89_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1563570: Warning: Identifier `\clknet_10_90_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1563576: Warning: Identifier `\clknet_10_91_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1563582: Warning: Identifier `\clknet_10_92_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1563588: Warning: Identifier `\clknet_10_93_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1563594: Warning: Identifier `\clknet_10_94_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1563600: Warning: Identifier `\clknet_10_95_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1563606: Warning: Identifier `\clknet_10_96_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1563612: Warning: Identifier `\clknet_10_97_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1563618: Warning: Identifier `\clknet_10_98_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1563624: Warning: Identifier `\clknet_10_99_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1563630: Warning: Identifier `\clknet_10_100_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1563636: Warning: Identifier `\clknet_10_101_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1563642: Warning: Identifier `\clknet_10_102_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1563648: Warning: Identifier `\clknet_10_103_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1563654: Warning: Identifier `\clknet_10_104_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1563660: Warning: Identifier `\clknet_10_105_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1563666: Warning: Identifier `\clknet_10_106_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1563672: Warning: Identifier `\clknet_10_107_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1563678: Warning: Identifier `\clknet_10_108_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1563684: Warning: Identifier `\clknet_10_109_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1563690: Warning: Identifier `\clknet_10_110_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1563696: Warning: Identifier `\clknet_10_111_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1563702: Warning: Identifier `\clknet_10_112_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1563708: Warning: Identifier `\clknet_10_113_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1563714: Warning: Identifier `\clknet_10_114_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1563720: Warning: Identifier `\clknet_10_115_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1563726: Warning: Identifier `\clknet_10_116_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1563732: Warning: Identifier `\clknet_10_117_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1563738: Warning: Identifier `\clknet_10_118_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1563744: Warning: Identifier `\clknet_10_119_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1563750: Warning: Identifier `\clknet_10_120_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1563756: Warning: Identifier `\clknet_10_121_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1563762: Warning: Identifier `\clknet_10_122_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1563768: Warning: Identifier `\clknet_10_123_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1563774: Warning: Identifier `\clknet_10_124_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1563780: Warning: Identifier `\clknet_10_125_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1563786: Warning: Identifier `\clknet_10_126_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1563792: Warning: Identifier `\clknet_10_127_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1563798: Warning: Identifier `\clknet_10_128_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1563804: Warning: Identifier `\clknet_10_129_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1563810: Warning: Identifier `\clknet_10_130_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1563816: Warning: Identifier `\clknet_10_131_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1563822: Warning: Identifier `\clknet_10_132_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1563828: Warning: Identifier `\clknet_10_133_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1563834: Warning: Identifier `\clknet_10_134_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1563840: Warning: Identifier `\clknet_10_135_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1563846: Warning: Identifier `\clknet_10_136_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1563852: Warning: Identifier `\clknet_10_137_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1563858: Warning: Identifier `\clknet_10_138_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1563864: Warning: Identifier `\clknet_10_139_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1563870: Warning: Identifier `\clknet_10_140_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1563876: Warning: Identifier `\clknet_10_141_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1563882: Warning: Identifier `\clknet_10_142_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1563888: Warning: Identifier `\clknet_10_143_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1563894: Warning: Identifier `\clknet_10_144_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1563900: Warning: Identifier `\clknet_10_145_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1563906: Warning: Identifier `\clknet_10_146_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1563912: Warning: Identifier `\clknet_10_147_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1563918: Warning: Identifier `\clknet_10_148_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1563924: Warning: Identifier `\clknet_10_149_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1563930: Warning: Identifier `\clknet_10_150_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1563936: Warning: Identifier `\clknet_10_151_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1563942: Warning: Identifier `\clknet_10_152_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1563948: Warning: Identifier `\clknet_10_153_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1563954: Warning: Identifier `\clknet_10_154_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1563960: Warning: Identifier `\clknet_10_155_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1563966: Warning: Identifier `\clknet_10_156_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1563972: Warning: Identifier `\clknet_10_157_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1563978: Warning: Identifier `\clknet_10_158_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1563984: Warning: Identifier `\clknet_10_159_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1563990: Warning: Identifier `\clknet_10_160_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1563996: Warning: Identifier `\clknet_10_161_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1564002: Warning: Identifier `\clknet_10_162_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1564008: Warning: Identifier `\clknet_10_163_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1564014: Warning: Identifier `\clknet_10_164_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1564020: Warning: Identifier `\clknet_10_165_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1564026: Warning: Identifier `\clknet_10_166_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1564032: Warning: Identifier `\clknet_10_167_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1564038: Warning: Identifier `\clknet_10_168_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1564044: Warning: Identifier `\clknet_10_169_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1564050: Warning: Identifier `\clknet_10_170_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1564056: Warning: Identifier `\clknet_10_171_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1564062: Warning: Identifier `\clknet_10_172_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1564068: Warning: Identifier `\clknet_10_173_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1564074: Warning: Identifier `\clknet_10_174_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1564080: Warning: Identifier `\clknet_10_175_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1564086: Warning: Identifier `\clknet_10_176_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1564092: Warning: Identifier `\clknet_10_177_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1564098: Warning: Identifier `\clknet_10_178_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1564104: Warning: Identifier `\clknet_10_179_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1564110: Warning: Identifier `\clknet_10_180_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1564116: Warning: Identifier `\clknet_10_181_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1564122: Warning: Identifier `\clknet_10_182_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1564128: Warning: Identifier `\clknet_10_183_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1564134: Warning: Identifier `\clknet_10_184_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1564140: Warning: Identifier `\clknet_10_185_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1564146: Warning: Identifier `\clknet_10_186_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1564152: Warning: Identifier `\clknet_10_187_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1564158: Warning: Identifier `\clknet_10_188_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1564164: Warning: Identifier `\clknet_10_189_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1564170: Warning: Identifier `\clknet_10_190_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1564176: Warning: Identifier `\clknet_10_191_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1564182: Warning: Identifier `\clknet_10_192_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1564188: Warning: Identifier `\clknet_10_193_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1564194: Warning: Identifier `\clknet_10_194_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1564200: Warning: Identifier `\clknet_10_195_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1564206: Warning: Identifier `\clknet_10_196_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1564212: Warning: Identifier `\clknet_10_197_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1564218: Warning: Identifier `\clknet_10_198_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1564224: Warning: Identifier `\clknet_10_199_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1564230: Warning: Identifier `\clknet_10_200_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1564236: Warning: Identifier `\clknet_10_201_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1564242: Warning: Identifier `\clknet_10_202_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1564248: Warning: Identifier `\clknet_10_203_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1564254: Warning: Identifier `\clknet_10_204_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1564260: Warning: Identifier `\clknet_10_205_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1564266: Warning: Identifier `\clknet_10_206_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1564272: Warning: Identifier `\clknet_10_207_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1564278: Warning: Identifier `\clknet_10_208_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1564284: Warning: Identifier `\clknet_10_209_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1564290: Warning: Identifier `\clknet_10_210_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1564296: Warning: Identifier `\clknet_10_211_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1564302: Warning: Identifier `\clknet_10_212_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1564308: Warning: Identifier `\clknet_10_213_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1564314: Warning: Identifier `\clknet_10_214_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1564320: Warning: Identifier `\clknet_10_215_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1564326: Warning: Identifier `\clknet_10_216_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1564332: Warning: Identifier `\clknet_10_217_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1564338: Warning: Identifier `\clknet_10_218_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1564344: Warning: Identifier `\clknet_10_219_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1564350: Warning: Identifier `\clknet_10_220_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1564356: Warning: Identifier `\clknet_10_221_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1564362: Warning: Identifier `\clknet_10_222_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1564368: Warning: Identifier `\clknet_10_223_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1564374: Warning: Identifier `\clknet_10_224_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1564380: Warning: Identifier `\clknet_10_225_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1564386: Warning: Identifier `\clknet_10_226_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1564392: Warning: Identifier `\clknet_10_227_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1564398: Warning: Identifier `\clknet_10_228_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1564404: Warning: Identifier `\clknet_10_229_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1564410: Warning: Identifier `\clknet_10_230_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1564416: Warning: Identifier `\clknet_10_231_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1564422: Warning: Identifier `\clknet_10_232_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1564428: Warning: Identifier `\clknet_10_233_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1564434: Warning: Identifier `\clknet_10_234_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1564440: Warning: Identifier `\clknet_10_235_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1564446: Warning: Identifier `\clknet_10_236_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1564452: Warning: Identifier `\clknet_10_237_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1564458: Warning: Identifier `\clknet_10_238_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1564464: Warning: Identifier `\clknet_10_239_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1564470: Warning: Identifier `\clknet_10_240_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1564476: Warning: Identifier `\clknet_10_241_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1564482: Warning: Identifier `\clknet_10_242_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1564488: Warning: Identifier `\clknet_10_243_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1564494: Warning: Identifier `\clknet_10_244_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1564500: Warning: Identifier `\clknet_10_245_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1564506: Warning: Identifier `\clknet_10_246_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1564512: Warning: Identifier `\clknet_10_247_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1564518: Warning: Identifier `\clknet_10_248_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1564524: Warning: Identifier `\clknet_10_249_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1564530: Warning: Identifier `\clknet_10_250_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1564536: Warning: Identifier `\clknet_10_251_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1564542: Warning: Identifier `\clknet_10_252_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1564548: Warning: Identifier `\clknet_10_253_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1564554: Warning: Identifier `\clknet_10_254_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1564560: Warning: Identifier `\clknet_10_255_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1564566: Warning: Identifier `\clknet_10_256_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1564572: Warning: Identifier `\clknet_10_257_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1564578: Warning: Identifier `\clknet_10_258_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1564584: Warning: Identifier `\clknet_10_259_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1564590: Warning: Identifier `\clknet_10_260_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1564596: Warning: Identifier `\clknet_10_261_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1564602: Warning: Identifier `\clknet_10_262_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1564608: Warning: Identifier `\clknet_10_263_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1564614: Warning: Identifier `\clknet_10_264_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1564620: Warning: Identifier `\clknet_10_265_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1564626: Warning: Identifier `\clknet_10_266_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1564632: Warning: Identifier `\clknet_10_267_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1564638: Warning: Identifier `\clknet_10_268_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1564644: Warning: Identifier `\clknet_10_269_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1564650: Warning: Identifier `\clknet_10_270_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1564656: Warning: Identifier `\clknet_10_271_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1564662: Warning: Identifier `\clknet_10_272_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1564668: Warning: Identifier `\clknet_10_273_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1564674: Warning: Identifier `\clknet_10_274_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1564680: Warning: Identifier `\clknet_10_275_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1564686: Warning: Identifier `\clknet_10_276_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1564692: Warning: Identifier `\clknet_10_277_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1564698: Warning: Identifier `\clknet_10_278_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1564704: Warning: Identifier `\clknet_10_279_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1564710: Warning: Identifier `\clknet_10_280_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1564716: Warning: Identifier `\clknet_10_281_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1564722: Warning: Identifier `\clknet_10_282_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1564728: Warning: Identifier `\clknet_10_283_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1564734: Warning: Identifier `\clknet_10_284_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1564740: Warning: Identifier `\clknet_10_285_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1564746: Warning: Identifier `\clknet_10_286_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1564752: Warning: Identifier `\clknet_10_287_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1564758: Warning: Identifier `\clknet_10_288_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1564764: Warning: Identifier `\clknet_10_289_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1564770: Warning: Identifier `\clknet_10_290_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1564776: Warning: Identifier `\clknet_10_291_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1564782: Warning: Identifier `\clknet_10_292_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1564788: Warning: Identifier `\clknet_10_293_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1564794: Warning: Identifier `\clknet_10_294_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1564800: Warning: Identifier `\clknet_10_295_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1564806: Warning: Identifier `\clknet_10_296_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1564812: Warning: Identifier `\clknet_10_297_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1564818: Warning: Identifier `\clknet_10_298_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1564824: Warning: Identifier `\clknet_10_299_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1564830: Warning: Identifier `\clknet_10_300_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1564836: Warning: Identifier `\clknet_10_301_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1564842: Warning: Identifier `\clknet_10_302_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1564848: Warning: Identifier `\clknet_10_303_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1564854: Warning: Identifier `\clknet_10_304_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1564860: Warning: Identifier `\clknet_10_305_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1564866: Warning: Identifier `\clknet_10_306_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1564872: Warning: Identifier `\clknet_10_307_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1564878: Warning: Identifier `\clknet_10_308_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1564884: Warning: Identifier `\clknet_10_309_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1564890: Warning: Identifier `\clknet_10_310_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1564896: Warning: Identifier `\clknet_10_311_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1564902: Warning: Identifier `\clknet_10_312_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1564908: Warning: Identifier `\clknet_10_313_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1564914: Warning: Identifier `\clknet_10_314_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1564920: Warning: Identifier `\clknet_10_315_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1564926: Warning: Identifier `\clknet_10_316_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1564932: Warning: Identifier `\clknet_10_317_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1564938: Warning: Identifier `\clknet_10_318_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1564944: Warning: Identifier `\clknet_10_319_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1564950: Warning: Identifier `\clknet_10_320_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1564956: Warning: Identifier `\clknet_10_321_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1564962: Warning: Identifier `\clknet_10_322_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1564968: Warning: Identifier `\clknet_10_323_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1564974: Warning: Identifier `\clknet_10_324_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1564980: Warning: Identifier `\clknet_10_325_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1564986: Warning: Identifier `\clknet_10_326_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1564992: Warning: Identifier `\clknet_10_327_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1564998: Warning: Identifier `\clknet_10_328_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1565004: Warning: Identifier `\clknet_10_329_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1565010: Warning: Identifier `\clknet_10_330_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1565016: Warning: Identifier `\clknet_10_331_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1565022: Warning: Identifier `\clknet_10_332_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1565028: Warning: Identifier `\clknet_10_333_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1565034: Warning: Identifier `\clknet_10_334_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1565040: Warning: Identifier `\clknet_10_335_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1565046: Warning: Identifier `\clknet_10_336_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1565052: Warning: Identifier `\clknet_10_337_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1565058: Warning: Identifier `\clknet_10_338_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1565064: Warning: Identifier `\clknet_10_339_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1565070: Warning: Identifier `\clknet_10_340_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1565076: Warning: Identifier `\clknet_10_341_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1565082: Warning: Identifier `\clknet_10_342_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1565088: Warning: Identifier `\clknet_10_343_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1565094: Warning: Identifier `\clknet_10_344_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1565100: Warning: Identifier `\clknet_10_345_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1565106: Warning: Identifier `\clknet_10_346_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1565112: Warning: Identifier `\clknet_10_347_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1565118: Warning: Identifier `\clknet_10_348_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1565124: Warning: Identifier `\clknet_10_349_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1565130: Warning: Identifier `\clknet_10_350_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1565136: Warning: Identifier `\clknet_10_351_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1565142: Warning: Identifier `\clknet_10_352_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1565148: Warning: Identifier `\clknet_10_353_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1565154: Warning: Identifier `\clknet_10_354_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1565160: Warning: Identifier `\clknet_10_355_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1565166: Warning: Identifier `\clknet_10_356_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1565172: Warning: Identifier `\clknet_10_357_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1565178: Warning: Identifier `\clknet_10_358_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1565184: Warning: Identifier `\clknet_10_359_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1565190: Warning: Identifier `\clknet_10_360_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1565196: Warning: Identifier `\clknet_10_361_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1565202: Warning: Identifier `\clknet_10_362_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1565208: Warning: Identifier `\clknet_10_363_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1565214: Warning: Identifier `\clknet_10_364_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1565220: Warning: Identifier `\clknet_10_365_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1565226: Warning: Identifier `\clknet_10_366_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1565232: Warning: Identifier `\clknet_10_367_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1565238: Warning: Identifier `\clknet_10_368_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1565244: Warning: Identifier `\clknet_10_369_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1565250: Warning: Identifier `\clknet_10_370_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1565256: Warning: Identifier `\clknet_10_371_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1565262: Warning: Identifier `\clknet_10_372_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1565268: Warning: Identifier `\clknet_10_373_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1565274: Warning: Identifier `\clknet_10_374_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1565280: Warning: Identifier `\clknet_10_375_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1565286: Warning: Identifier `\clknet_10_376_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1565292: Warning: Identifier `\clknet_10_377_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1565298: Warning: Identifier `\clknet_10_378_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1565304: Warning: Identifier `\clknet_10_379_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1565310: Warning: Identifier `\clknet_10_380_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1565316: Warning: Identifier `\clknet_10_381_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1565322: Warning: Identifier `\clknet_10_382_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1565328: Warning: Identifier `\clknet_10_383_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1565334: Warning: Identifier `\clknet_10_384_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1565340: Warning: Identifier `\clknet_10_385_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1565346: Warning: Identifier `\clknet_10_386_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1565352: Warning: Identifier `\clknet_10_387_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1565358: Warning: Identifier `\clknet_10_388_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1565364: Warning: Identifier `\clknet_10_389_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1565370: Warning: Identifier `\clknet_10_390_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1565376: Warning: Identifier `\clknet_10_391_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1565382: Warning: Identifier `\clknet_10_392_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1565388: Warning: Identifier `\clknet_10_393_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1565394: Warning: Identifier `\clknet_10_394_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1565400: Warning: Identifier `\clknet_10_395_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1565406: Warning: Identifier `\clknet_10_396_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1565412: Warning: Identifier `\clknet_10_397_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1565418: Warning: Identifier `\clknet_10_398_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1565424: Warning: Identifier `\clknet_10_399_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1565430: Warning: Identifier `\clknet_10_400_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1565436: Warning: Identifier `\clknet_10_401_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1565442: Warning: Identifier `\clknet_10_402_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1565448: Warning: Identifier `\clknet_10_403_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1565454: Warning: Identifier `\clknet_10_404_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1565460: Warning: Identifier `\clknet_10_405_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1565466: Warning: Identifier `\clknet_10_406_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1565472: Warning: Identifier `\clknet_10_407_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1565478: Warning: Identifier `\clknet_10_408_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1565484: Warning: Identifier `\clknet_10_409_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1565490: Warning: Identifier `\clknet_10_410_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1565496: Warning: Identifier `\clknet_10_411_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1565502: Warning: Identifier `\clknet_10_412_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1565508: Warning: Identifier `\clknet_10_413_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1565514: Warning: Identifier `\clknet_10_414_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1565520: Warning: Identifier `\clknet_10_415_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1565526: Warning: Identifier `\clknet_10_416_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1565532: Warning: Identifier `\clknet_10_417_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1565538: Warning: Identifier `\clknet_10_418_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1565544: Warning: Identifier `\clknet_10_419_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1565550: Warning: Identifier `\clknet_10_420_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1565556: Warning: Identifier `\clknet_10_421_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1565562: Warning: Identifier `\clknet_10_422_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1565568: Warning: Identifier `\clknet_10_423_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1565574: Warning: Identifier `\clknet_10_424_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1565580: Warning: Identifier `\clknet_10_425_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1565586: Warning: Identifier `\clknet_10_426_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1565592: Warning: Identifier `\clknet_10_427_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1565598: Warning: Identifier `\clknet_10_428_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1565604: Warning: Identifier `\clknet_10_429_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1565610: Warning: Identifier `\clknet_10_430_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1565616: Warning: Identifier `\clknet_10_431_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1565622: Warning: Identifier `\clknet_10_432_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1565628: Warning: Identifier `\clknet_10_433_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1565634: Warning: Identifier `\clknet_10_434_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1565640: Warning: Identifier `\clknet_10_435_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1565646: Warning: Identifier `\clknet_10_436_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1565652: Warning: Identifier `\clknet_10_437_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1565658: Warning: Identifier `\clknet_10_438_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1565664: Warning: Identifier `\clknet_10_439_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1565670: Warning: Identifier `\clknet_10_440_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1565676: Warning: Identifier `\clknet_10_441_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1565682: Warning: Identifier `\clknet_10_442_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1565688: Warning: Identifier `\clknet_10_443_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1565694: Warning: Identifier `\clknet_10_444_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1565700: Warning: Identifier `\clknet_10_445_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1565706: Warning: Identifier `\clknet_10_446_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1565712: Warning: Identifier `\clknet_10_447_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1565718: Warning: Identifier `\clknet_10_448_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1565724: Warning: Identifier `\clknet_10_449_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1565730: Warning: Identifier `\clknet_10_450_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1565736: Warning: Identifier `\clknet_10_451_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1565742: Warning: Identifier `\clknet_10_452_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1565748: Warning: Identifier `\clknet_10_453_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1565754: Warning: Identifier `\clknet_10_454_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1565760: Warning: Identifier `\clknet_10_455_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1565766: Warning: Identifier `\clknet_10_456_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1565772: Warning: Identifier `\clknet_10_457_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1565778: Warning: Identifier `\clknet_10_458_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1565784: Warning: Identifier `\clknet_10_459_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1565790: Warning: Identifier `\clknet_10_460_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1565796: Warning: Identifier `\clknet_10_461_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1565802: Warning: Identifier `\clknet_10_462_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1565808: Warning: Identifier `\clknet_10_463_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1565814: Warning: Identifier `\clknet_10_464_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1565820: Warning: Identifier `\clknet_10_465_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1565826: Warning: Identifier `\clknet_10_466_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1565832: Warning: Identifier `\clknet_10_467_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1565838: Warning: Identifier `\clknet_10_468_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1565844: Warning: Identifier `\clknet_10_469_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1565850: Warning: Identifier `\clknet_10_470_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1565856: Warning: Identifier `\clknet_10_471_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1565862: Warning: Identifier `\clknet_10_472_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1565868: Warning: Identifier `\clknet_10_473_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1565874: Warning: Identifier `\clknet_10_474_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1565880: Warning: Identifier `\clknet_10_475_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1565886: Warning: Identifier `\clknet_10_476_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1565892: Warning: Identifier `\clknet_10_477_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1565898: Warning: Identifier `\clknet_10_478_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1565904: Warning: Identifier `\clknet_10_479_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1565910: Warning: Identifier `\clknet_10_480_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1565916: Warning: Identifier `\clknet_10_481_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1565922: Warning: Identifier `\clknet_10_482_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1565928: Warning: Identifier `\clknet_10_483_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1565934: Warning: Identifier `\clknet_10_484_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1565940: Warning: Identifier `\clknet_10_485_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1565946: Warning: Identifier `\clknet_10_486_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1565952: Warning: Identifier `\clknet_10_487_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1565958: Warning: Identifier `\clknet_10_488_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1565964: Warning: Identifier `\clknet_10_489_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1565970: Warning: Identifier `\clknet_10_490_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1565976: Warning: Identifier `\clknet_10_491_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1565982: Warning: Identifier `\clknet_10_492_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1565988: Warning: Identifier `\clknet_10_493_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1565994: Warning: Identifier `\clknet_10_494_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1566000: Warning: Identifier `\clknet_10_495_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1566006: Warning: Identifier `\clknet_10_496_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1566012: Warning: Identifier `\clknet_10_497_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1566018: Warning: Identifier `\clknet_10_498_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1566024: Warning: Identifier `\clknet_10_499_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1566030: Warning: Identifier `\clknet_10_500_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1566036: Warning: Identifier `\clknet_10_501_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1566042: Warning: Identifier `\clknet_10_502_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1566048: Warning: Identifier `\clknet_10_503_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1566054: Warning: Identifier `\clknet_10_504_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1566060: Warning: Identifier `\clknet_10_505_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1566066: Warning: Identifier `\clknet_10_506_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1566072: Warning: Identifier `\clknet_10_507_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1566078: Warning: Identifier `\clknet_10_508_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1566084: Warning: Identifier `\clknet_10_509_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1566090: Warning: Identifier `\clknet_10_510_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1566096: Warning: Identifier `\clknet_10_511_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1566102: Warning: Identifier `\clknet_10_512_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1566108: Warning: Identifier `\clknet_10_513_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1566114: Warning: Identifier `\clknet_10_514_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1566120: Warning: Identifier `\clknet_10_515_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1566126: Warning: Identifier `\clknet_10_516_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1566132: Warning: Identifier `\clknet_10_517_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1566138: Warning: Identifier `\clknet_10_518_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1566144: Warning: Identifier `\clknet_10_519_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1566150: Warning: Identifier `\clknet_10_520_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1566156: Warning: Identifier `\clknet_10_521_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1566162: Warning: Identifier `\clknet_10_522_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1566168: Warning: Identifier `\clknet_10_523_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1566174: Warning: Identifier `\clknet_10_524_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1566180: Warning: Identifier `\clknet_10_525_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1566186: Warning: Identifier `\clknet_10_526_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1566192: Warning: Identifier `\clknet_10_527_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1566198: Warning: Identifier `\clknet_10_528_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1566204: Warning: Identifier `\clknet_10_529_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1566210: Warning: Identifier `\clknet_10_530_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1566216: Warning: Identifier `\clknet_10_531_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1566222: Warning: Identifier `\clknet_10_532_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1566228: Warning: Identifier `\clknet_10_533_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1566234: Warning: Identifier `\clknet_10_534_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1566240: Warning: Identifier `\clknet_10_535_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1566246: Warning: Identifier `\clknet_10_536_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1566252: Warning: Identifier `\clknet_10_537_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1566258: Warning: Identifier `\clknet_10_538_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1566264: Warning: Identifier `\clknet_10_539_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1566270: Warning: Identifier `\clknet_10_540_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1566276: Warning: Identifier `\clknet_10_541_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1566282: Warning: Identifier `\clknet_10_542_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1566288: Warning: Identifier `\clknet_10_543_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1566294: Warning: Identifier `\clknet_10_544_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1566300: Warning: Identifier `\clknet_10_545_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1566306: Warning: Identifier `\clknet_10_546_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1566312: Warning: Identifier `\clknet_10_547_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1566318: Warning: Identifier `\clknet_10_548_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1566324: Warning: Identifier `\clknet_10_549_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1566330: Warning: Identifier `\clknet_10_550_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1566336: Warning: Identifier `\clknet_10_551_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1566342: Warning: Identifier `\clknet_10_552_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1566348: Warning: Identifier `\clknet_10_553_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1566354: Warning: Identifier `\clknet_10_554_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1566360: Warning: Identifier `\clknet_10_555_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1566366: Warning: Identifier `\clknet_10_556_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1566372: Warning: Identifier `\clknet_10_557_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1566378: Warning: Identifier `\clknet_10_558_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1566384: Warning: Identifier `\clknet_10_559_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1566390: Warning: Identifier `\clknet_10_560_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1566396: Warning: Identifier `\clknet_10_561_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1566402: Warning: Identifier `\clknet_10_562_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1566408: Warning: Identifier `\clknet_10_563_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1566414: Warning: Identifier `\clknet_10_564_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1566420: Warning: Identifier `\clknet_10_565_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1566426: Warning: Identifier `\clknet_10_566_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1566432: Warning: Identifier `\clknet_10_567_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1566438: Warning: Identifier `\clknet_10_568_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1566444: Warning: Identifier `\clknet_10_569_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1566450: Warning: Identifier `\clknet_10_570_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1566456: Warning: Identifier `\clknet_10_571_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1566462: Warning: Identifier `\clknet_10_572_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1566468: Warning: Identifier `\clknet_10_573_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1566474: Warning: Identifier `\clknet_10_574_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1566480: Warning: Identifier `\clknet_10_575_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1566486: Warning: Identifier `\clknet_10_576_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1566492: Warning: Identifier `\clknet_10_577_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1566498: Warning: Identifier `\clknet_10_578_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1566504: Warning: Identifier `\clknet_10_579_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1566510: Warning: Identifier `\clknet_10_580_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1566516: Warning: Identifier `\clknet_10_581_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1566522: Warning: Identifier `\clknet_10_582_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1566528: Warning: Identifier `\clknet_10_583_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1566534: Warning: Identifier `\clknet_10_584_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1566540: Warning: Identifier `\clknet_10_585_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1566546: Warning: Identifier `\clknet_10_586_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1566552: Warning: Identifier `\clknet_10_587_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1566558: Warning: Identifier `\clknet_10_588_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1566564: Warning: Identifier `\clknet_10_589_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1566570: Warning: Identifier `\clknet_10_590_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1566576: Warning: Identifier `\clknet_10_591_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1566582: Warning: Identifier `\clknet_10_592_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1566588: Warning: Identifier `\clknet_10_593_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1566594: Warning: Identifier `\clknet_10_594_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1566600: Warning: Identifier `\clknet_10_595_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1566606: Warning: Identifier `\clknet_10_596_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1566612: Warning: Identifier `\clknet_10_597_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1566618: Warning: Identifier `\clknet_10_598_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1566624: Warning: Identifier `\clknet_10_599_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1566630: Warning: Identifier `\clknet_10_600_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1566636: Warning: Identifier `\clknet_10_601_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1566642: Warning: Identifier `\clknet_10_602_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1566648: Warning: Identifier `\clknet_10_603_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1566654: Warning: Identifier `\clknet_10_604_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1566660: Warning: Identifier `\clknet_10_605_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1566666: Warning: Identifier `\clknet_10_606_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1566672: Warning: Identifier `\clknet_10_607_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1566678: Warning: Identifier `\clknet_10_608_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1566684: Warning: Identifier `\clknet_10_609_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1566690: Warning: Identifier `\clknet_10_610_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1566696: Warning: Identifier `\clknet_10_611_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1566702: Warning: Identifier `\clknet_10_612_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1566708: Warning: Identifier `\clknet_10_613_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1566714: Warning: Identifier `\clknet_10_614_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1566720: Warning: Identifier `\clknet_10_615_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1566726: Warning: Identifier `\clknet_10_616_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1566732: Warning: Identifier `\clknet_10_617_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1566738: Warning: Identifier `\clknet_10_618_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1566744: Warning: Identifier `\clknet_10_619_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1566750: Warning: Identifier `\clknet_10_620_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1566756: Warning: Identifier `\clknet_10_621_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1566762: Warning: Identifier `\clknet_10_622_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1566768: Warning: Identifier `\clknet_10_623_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1566774: Warning: Identifier `\clknet_10_624_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1566780: Warning: Identifier `\clknet_10_625_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1566786: Warning: Identifier `\clknet_10_626_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1566792: Warning: Identifier `\clknet_10_627_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1566798: Warning: Identifier `\clknet_10_628_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1566804: Warning: Identifier `\clknet_10_629_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1566810: Warning: Identifier `\clknet_10_630_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1566816: Warning: Identifier `\clknet_10_631_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1566822: Warning: Identifier `\clknet_10_632_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1566828: Warning: Identifier `\clknet_10_633_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1566834: Warning: Identifier `\clknet_10_634_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1566840: Warning: Identifier `\clknet_10_635_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1566846: Warning: Identifier `\clknet_10_636_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1566852: Warning: Identifier `\clknet_10_637_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1566858: Warning: Identifier `\clknet_10_638_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1566864: Warning: Identifier `\clknet_10_639_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1566870: Warning: Identifier `\clknet_10_640_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1566876: Warning: Identifier `\clknet_10_641_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1566882: Warning: Identifier `\clknet_10_642_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1566888: Warning: Identifier `\clknet_10_643_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1566894: Warning: Identifier `\clknet_10_644_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1566900: Warning: Identifier `\clknet_10_645_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1566906: Warning: Identifier `\clknet_10_646_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1566912: Warning: Identifier `\clknet_10_647_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1566918: Warning: Identifier `\clknet_10_648_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1566924: Warning: Identifier `\clknet_10_649_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1566930: Warning: Identifier `\clknet_10_650_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1566936: Warning: Identifier `\clknet_10_651_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1566942: Warning: Identifier `\clknet_10_652_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1566948: Warning: Identifier `\clknet_10_653_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1566954: Warning: Identifier `\clknet_10_654_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1566960: Warning: Identifier `\clknet_10_655_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1566966: Warning: Identifier `\clknet_10_656_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1566972: Warning: Identifier `\clknet_10_657_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1566978: Warning: Identifier `\clknet_10_658_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1566984: Warning: Identifier `\clknet_10_659_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1566990: Warning: Identifier `\clknet_10_660_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1566996: Warning: Identifier `\clknet_10_661_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1567002: Warning: Identifier `\clknet_10_662_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1567008: Warning: Identifier `\clknet_10_663_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1567014: Warning: Identifier `\clknet_10_664_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1567020: Warning: Identifier `\clknet_10_665_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1567026: Warning: Identifier `\clknet_10_666_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1567032: Warning: Identifier `\clknet_10_667_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1567038: Warning: Identifier `\clknet_10_668_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1567044: Warning: Identifier `\clknet_10_669_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1567050: Warning: Identifier `\clknet_10_670_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1567056: Warning: Identifier `\clknet_10_671_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1567062: Warning: Identifier `\clknet_10_672_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1567068: Warning: Identifier `\clknet_10_673_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1567074: Warning: Identifier `\clknet_10_674_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1567080: Warning: Identifier `\clknet_10_675_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1567086: Warning: Identifier `\clknet_10_676_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1567092: Warning: Identifier `\clknet_10_677_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1567098: Warning: Identifier `\clknet_10_678_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1567104: Warning: Identifier `\clknet_10_679_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1567110: Warning: Identifier `\clknet_10_680_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1567116: Warning: Identifier `\clknet_10_681_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1567122: Warning: Identifier `\clknet_10_682_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1567128: Warning: Identifier `\clknet_10_683_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1567134: Warning: Identifier `\clknet_10_684_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1567140: Warning: Identifier `\clknet_10_685_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1567146: Warning: Identifier `\clknet_10_686_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1567152: Warning: Identifier `\clknet_10_687_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1567158: Warning: Identifier `\clknet_10_688_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1567164: Warning: Identifier `\clknet_10_689_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1567170: Warning: Identifier `\clknet_10_690_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1567176: Warning: Identifier `\clknet_10_691_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1567182: Warning: Identifier `\clknet_10_692_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1567188: Warning: Identifier `\clknet_10_693_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1567194: Warning: Identifier `\clknet_10_694_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1567200: Warning: Identifier `\clknet_10_695_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1567206: Warning: Identifier `\clknet_10_696_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1567212: Warning: Identifier `\clknet_10_697_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1567218: Warning: Identifier `\clknet_10_698_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1567224: Warning: Identifier `\clknet_10_699_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1567230: Warning: Identifier `\clknet_10_700_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1567236: Warning: Identifier `\clknet_10_701_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1567242: Warning: Identifier `\clknet_10_702_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1567248: Warning: Identifier `\clknet_10_703_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1567254: Warning: Identifier `\clknet_10_704_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1567260: Warning: Identifier `\clknet_10_705_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1567266: Warning: Identifier `\clknet_10_706_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1567272: Warning: Identifier `\clknet_10_707_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1567278: Warning: Identifier `\clknet_10_708_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1567284: Warning: Identifier `\clknet_10_709_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1567290: Warning: Identifier `\clknet_10_710_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1567296: Warning: Identifier `\clknet_10_711_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1567302: Warning: Identifier `\clknet_10_712_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1567308: Warning: Identifier `\clknet_10_713_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1567314: Warning: Identifier `\clknet_10_714_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1567320: Warning: Identifier `\clknet_10_715_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1567326: Warning: Identifier `\clknet_10_716_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1567332: Warning: Identifier `\clknet_10_717_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1567338: Warning: Identifier `\clknet_10_718_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1567344: Warning: Identifier `\clknet_10_719_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1567350: Warning: Identifier `\clknet_10_720_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1567356: Warning: Identifier `\clknet_10_721_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1567362: Warning: Identifier `\clknet_10_722_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1567368: Warning: Identifier `\clknet_10_723_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1567374: Warning: Identifier `\clknet_10_724_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1567380: Warning: Identifier `\clknet_10_725_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1567386: Warning: Identifier `\clknet_10_726_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1567392: Warning: Identifier `\clknet_10_727_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1567398: Warning: Identifier `\clknet_10_728_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1567404: Warning: Identifier `\clknet_10_729_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1567410: Warning: Identifier `\clknet_10_730_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1567416: Warning: Identifier `\clknet_10_731_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1567422: Warning: Identifier `\clknet_10_732_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1567428: Warning: Identifier `\clknet_10_733_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1567434: Warning: Identifier `\clknet_10_734_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1567440: Warning: Identifier `\clknet_10_735_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1567446: Warning: Identifier `\clknet_10_736_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1567452: Warning: Identifier `\clknet_10_737_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1567458: Warning: Identifier `\clknet_10_738_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1567464: Warning: Identifier `\clknet_10_739_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1567470: Warning: Identifier `\clknet_10_740_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1567476: Warning: Identifier `\clknet_10_741_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1567482: Warning: Identifier `\clknet_10_742_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1567488: Warning: Identifier `\clknet_10_743_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1567494: Warning: Identifier `\clknet_10_744_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1567500: Warning: Identifier `\clknet_10_745_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1567506: Warning: Identifier `\clknet_10_746_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1567512: Warning: Identifier `\clknet_10_747_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1567518: Warning: Identifier `\clknet_10_748_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1567524: Warning: Identifier `\clknet_10_749_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1567530: Warning: Identifier `\clknet_10_750_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1567536: Warning: Identifier `\clknet_10_751_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1567542: Warning: Identifier `\clknet_10_752_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1567548: Warning: Identifier `\clknet_10_753_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1567554: Warning: Identifier `\clknet_10_754_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1567560: Warning: Identifier `\clknet_10_755_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1567566: Warning: Identifier `\clknet_10_756_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1567572: Warning: Identifier `\clknet_10_757_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1567578: Warning: Identifier `\clknet_10_758_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1567584: Warning: Identifier `\clknet_10_759_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1567590: Warning: Identifier `\clknet_10_760_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1567596: Warning: Identifier `\clknet_10_761_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1567602: Warning: Identifier `\clknet_10_762_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1567608: Warning: Identifier `\clknet_10_763_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1567614: Warning: Identifier `\clknet_10_764_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1567620: Warning: Identifier `\clknet_10_765_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1567626: Warning: Identifier `\clknet_10_766_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1567632: Warning: Identifier `\clknet_10_767_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1567638: Warning: Identifier `\clknet_10_768_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1567644: Warning: Identifier `\clknet_10_769_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1567650: Warning: Identifier `\clknet_10_770_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1567656: Warning: Identifier `\clknet_10_771_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1567662: Warning: Identifier `\clknet_10_772_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1567668: Warning: Identifier `\clknet_10_773_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1567674: Warning: Identifier `\clknet_10_774_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1567680: Warning: Identifier `\clknet_10_775_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1567686: Warning: Identifier `\clknet_10_776_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1567692: Warning: Identifier `\clknet_10_777_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1567698: Warning: Identifier `\clknet_10_778_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1567704: Warning: Identifier `\clknet_10_779_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1567710: Warning: Identifier `\clknet_10_780_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1567716: Warning: Identifier `\clknet_10_781_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1567722: Warning: Identifier `\clknet_10_782_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1567728: Warning: Identifier `\clknet_10_783_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1567734: Warning: Identifier `\clknet_10_784_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1567740: Warning: Identifier `\clknet_10_785_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1567746: Warning: Identifier `\clknet_10_786_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1567752: Warning: Identifier `\clknet_10_787_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1567758: Warning: Identifier `\clknet_10_788_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1567764: Warning: Identifier `\clknet_10_789_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1567770: Warning: Identifier `\clknet_10_790_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1567776: Warning: Identifier `\clknet_10_791_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1567782: Warning: Identifier `\clknet_10_792_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1567788: Warning: Identifier `\clknet_10_793_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1567794: Warning: Identifier `\clknet_10_794_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1567800: Warning: Identifier `\clknet_10_795_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1567806: Warning: Identifier `\clknet_10_796_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1567812: Warning: Identifier `\clknet_10_797_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1567818: Warning: Identifier `\clknet_10_798_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1567824: Warning: Identifier `\clknet_10_799_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1567830: Warning: Identifier `\clknet_10_800_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1567836: Warning: Identifier `\clknet_10_801_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1567842: Warning: Identifier `\clknet_10_802_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1567848: Warning: Identifier `\clknet_10_803_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1567854: Warning: Identifier `\clknet_10_804_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1567860: Warning: Identifier `\clknet_10_805_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1567866: Warning: Identifier `\clknet_10_806_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1567872: Warning: Identifier `\clknet_10_807_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1567878: Warning: Identifier `\clknet_10_808_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1567884: Warning: Identifier `\clknet_10_809_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1567890: Warning: Identifier `\clknet_10_810_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1567896: Warning: Identifier `\clknet_10_811_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1567902: Warning: Identifier `\clknet_10_812_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1567908: Warning: Identifier `\clknet_10_813_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1567914: Warning: Identifier `\clknet_10_814_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1567920: Warning: Identifier `\clknet_10_815_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1567926: Warning: Identifier `\clknet_10_816_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1567932: Warning: Identifier `\clknet_10_817_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1567938: Warning: Identifier `\clknet_10_818_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1567944: Warning: Identifier `\clknet_10_819_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1567950: Warning: Identifier `\clknet_10_820_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1567956: Warning: Identifier `\clknet_10_821_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1567962: Warning: Identifier `\clknet_10_822_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1567968: Warning: Identifier `\clknet_10_823_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1567974: Warning: Identifier `\clknet_10_824_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1567980: Warning: Identifier `\clknet_10_825_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1567986: Warning: Identifier `\clknet_10_826_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1567992: Warning: Identifier `\clknet_10_827_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1567998: Warning: Identifier `\clknet_10_828_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1568004: Warning: Identifier `\clknet_10_829_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1568010: Warning: Identifier `\clknet_10_830_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1568016: Warning: Identifier `\clknet_10_831_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1568022: Warning: Identifier `\clknet_10_832_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1568028: Warning: Identifier `\clknet_10_833_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1568034: Warning: Identifier `\clknet_10_834_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1568040: Warning: Identifier `\clknet_10_835_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1568046: Warning: Identifier `\clknet_10_836_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1568052: Warning: Identifier `\clknet_10_837_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1568058: Warning: Identifier `\clknet_10_838_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1568064: Warning: Identifier `\clknet_10_839_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1568070: Warning: Identifier `\clknet_10_840_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1568076: Warning: Identifier `\clknet_10_841_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1568082: Warning: Identifier `\clknet_10_842_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1568088: Warning: Identifier `\clknet_10_843_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1568094: Warning: Identifier `\clknet_10_844_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1568100: Warning: Identifier `\clknet_10_845_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1568106: Warning: Identifier `\clknet_10_846_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1568112: Warning: Identifier `\clknet_10_847_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1568118: Warning: Identifier `\clknet_10_848_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1568124: Warning: Identifier `\clknet_10_849_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1568130: Warning: Identifier `\clknet_10_850_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1568136: Warning: Identifier `\clknet_10_851_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1568142: Warning: Identifier `\clknet_10_852_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1568148: Warning: Identifier `\clknet_10_853_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1568154: Warning: Identifier `\clknet_10_854_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1568160: Warning: Identifier `\clknet_10_855_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1568166: Warning: Identifier `\clknet_10_856_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1568172: Warning: Identifier `\clknet_10_857_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1568178: Warning: Identifier `\clknet_10_858_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1568184: Warning: Identifier `\clknet_10_859_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1568190: Warning: Identifier `\clknet_10_860_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1568196: Warning: Identifier `\clknet_10_861_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1568202: Warning: Identifier `\clknet_10_862_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1568208: Warning: Identifier `\clknet_10_863_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1568214: Warning: Identifier `\clknet_10_864_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1568220: Warning: Identifier `\clknet_10_865_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1568226: Warning: Identifier `\clknet_10_866_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1568232: Warning: Identifier `\clknet_10_867_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1568238: Warning: Identifier `\clknet_10_868_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1568244: Warning: Identifier `\clknet_10_869_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1568250: Warning: Identifier `\clknet_10_870_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1568256: Warning: Identifier `\clknet_10_871_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1568262: Warning: Identifier `\clknet_10_872_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1568268: Warning: Identifier `\clknet_10_873_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1568274: Warning: Identifier `\clknet_10_874_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1568280: Warning: Identifier `\clknet_10_875_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1568286: Warning: Identifier `\clknet_10_876_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1568292: Warning: Identifier `\clknet_10_877_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1568298: Warning: Identifier `\clknet_10_878_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1568304: Warning: Identifier `\clknet_10_879_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1568310: Warning: Identifier `\clknet_10_880_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1568316: Warning: Identifier `\clknet_10_881_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1568322: Warning: Identifier `\clknet_10_882_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1568328: Warning: Identifier `\clknet_10_883_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1568334: Warning: Identifier `\clknet_10_884_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1568340: Warning: Identifier `\clknet_10_885_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1568346: Warning: Identifier `\clknet_10_886_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1568352: Warning: Identifier `\clknet_10_887_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1568358: Warning: Identifier `\clknet_10_888_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1568364: Warning: Identifier `\clknet_10_889_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1568370: Warning: Identifier `\clknet_10_890_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1568376: Warning: Identifier `\clknet_10_891_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1568382: Warning: Identifier `\clknet_10_892_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1568388: Warning: Identifier `\clknet_10_893_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1568394: Warning: Identifier `\clknet_10_894_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1568400: Warning: Identifier `\clknet_10_895_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1568406: Warning: Identifier `\clknet_10_896_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1568412: Warning: Identifier `\clknet_10_897_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1568418: Warning: Identifier `\clknet_10_898_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1568424: Warning: Identifier `\clknet_10_899_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1568430: Warning: Identifier `\clknet_10_900_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1568436: Warning: Identifier `\clknet_10_901_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1568442: Warning: Identifier `\clknet_10_902_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1568448: Warning: Identifier `\clknet_10_903_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1568454: Warning: Identifier `\clknet_10_904_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1568460: Warning: Identifier `\clknet_10_905_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1568466: Warning: Identifier `\clknet_10_906_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1568472: Warning: Identifier `\clknet_10_907_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1568478: Warning: Identifier `\clknet_10_908_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1568484: Warning: Identifier `\clknet_10_909_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1568490: Warning: Identifier `\clknet_10_910_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1568496: Warning: Identifier `\clknet_10_911_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1568502: Warning: Identifier `\clknet_10_912_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1568508: Warning: Identifier `\clknet_10_913_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1568514: Warning: Identifier `\clknet_10_914_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1568520: Warning: Identifier `\clknet_10_915_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1568526: Warning: Identifier `\clknet_10_916_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1568532: Warning: Identifier `\clknet_10_917_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1568538: Warning: Identifier `\clknet_10_918_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1568544: Warning: Identifier `\clknet_10_919_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1568550: Warning: Identifier `\clknet_10_920_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1568556: Warning: Identifier `\clknet_10_921_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1568562: Warning: Identifier `\clknet_10_922_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1568568: Warning: Identifier `\clknet_10_923_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1568574: Warning: Identifier `\clknet_10_924_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1568580: Warning: Identifier `\clknet_10_925_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1568586: Warning: Identifier `\clknet_10_926_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1568592: Warning: Identifier `\clknet_10_927_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1568598: Warning: Identifier `\clknet_10_928_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1568604: Warning: Identifier `\clknet_10_929_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1568610: Warning: Identifier `\clknet_10_930_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1568616: Warning: Identifier `\clknet_10_931_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1568622: Warning: Identifier `\clknet_10_932_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1568628: Warning: Identifier `\clknet_10_933_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1568634: Warning: Identifier `\clknet_10_934_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1568640: Warning: Identifier `\clknet_10_935_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1568646: Warning: Identifier `\clknet_10_936_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1568652: Warning: Identifier `\clknet_10_937_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1568658: Warning: Identifier `\clknet_10_938_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1568664: Warning: Identifier `\clknet_10_939_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1568670: Warning: Identifier `\clknet_10_940_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1568676: Warning: Identifier `\clknet_10_941_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1568682: Warning: Identifier `\clknet_10_942_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1568688: Warning: Identifier `\clknet_10_943_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1568694: Warning: Identifier `\clknet_10_944_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1568700: Warning: Identifier `\clknet_10_945_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1568706: Warning: Identifier `\clknet_10_946_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1568712: Warning: Identifier `\clknet_10_947_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1568718: Warning: Identifier `\clknet_10_948_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1568724: Warning: Identifier `\clknet_10_949_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1568730: Warning: Identifier `\clknet_10_950_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1568736: Warning: Identifier `\clknet_10_951_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1568742: Warning: Identifier `\clknet_10_952_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1568748: Warning: Identifier `\clknet_10_953_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1568754: Warning: Identifier `\clknet_10_954_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1568760: Warning: Identifier `\clknet_10_955_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1568766: Warning: Identifier `\clknet_10_956_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1568772: Warning: Identifier `\clknet_10_957_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1568778: Warning: Identifier `\clknet_10_958_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1568784: Warning: Identifier `\clknet_10_959_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1568790: Warning: Identifier `\clknet_10_960_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1568796: Warning: Identifier `\clknet_10_961_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1568802: Warning: Identifier `\clknet_10_962_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1568808: Warning: Identifier `\clknet_10_963_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1568814: Warning: Identifier `\clknet_10_964_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1568820: Warning: Identifier `\clknet_10_965_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1568826: Warning: Identifier `\clknet_10_966_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1568832: Warning: Identifier `\clknet_10_967_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1568838: Warning: Identifier `\clknet_10_968_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1568844: Warning: Identifier `\clknet_10_969_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1568850: Warning: Identifier `\clknet_10_970_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1568856: Warning: Identifier `\clknet_10_971_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1568862: Warning: Identifier `\clknet_10_972_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1568868: Warning: Identifier `\clknet_10_973_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1568874: Warning: Identifier `\clknet_10_974_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1568880: Warning: Identifier `\clknet_10_975_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1568886: Warning: Identifier `\clknet_10_976_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1568892: Warning: Identifier `\clknet_10_977_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1568898: Warning: Identifier `\clknet_10_978_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1568904: Warning: Identifier `\clknet_10_979_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1568910: Warning: Identifier `\clknet_10_980_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1568916: Warning: Identifier `\clknet_10_981_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1568922: Warning: Identifier `\clknet_10_982_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1568928: Warning: Identifier `\clknet_10_983_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1568934: Warning: Identifier `\clknet_10_984_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1568940: Warning: Identifier `\clknet_10_985_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1568946: Warning: Identifier `\clknet_10_986_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1568952: Warning: Identifier `\clknet_10_987_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1568958: Warning: Identifier `\clknet_10_988_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1568964: Warning: Identifier `\clknet_10_989_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1568970: Warning: Identifier `\clknet_10_990_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1568976: Warning: Identifier `\clknet_10_991_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1568982: Warning: Identifier `\clknet_10_992_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1568988: Warning: Identifier `\clknet_10_993_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1568994: Warning: Identifier `\clknet_10_994_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1569000: Warning: Identifier `\clknet_10_995_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1569006: Warning: Identifier `\clknet_10_996_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1569012: Warning: Identifier `\clknet_10_997_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1569018: Warning: Identifier `\clknet_10_998_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1569024: Warning: Identifier `\clknet_10_999_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1569030: Warning: Identifier `\clknet_10_1000_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1569036: Warning: Identifier `\clknet_10_1001_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1569042: Warning: Identifier `\clknet_10_1002_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1569048: Warning: Identifier `\clknet_10_1003_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1569054: Warning: Identifier `\clknet_10_1004_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1569060: Warning: Identifier `\clknet_10_1005_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1569066: Warning: Identifier `\clknet_10_1006_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1569072: Warning: Identifier `\clknet_10_1007_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1569078: Warning: Identifier `\clknet_10_1008_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1569084: Warning: Identifier `\clknet_10_1009_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1569090: Warning: Identifier `\clknet_10_1010_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1569096: Warning: Identifier `\clknet_10_1011_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1569102: Warning: Identifier `\clknet_10_1012_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1569108: Warning: Identifier `\clknet_10_1013_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1569114: Warning: Identifier `\clknet_10_1014_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1569120: Warning: Identifier `\clknet_10_1015_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1569126: Warning: Identifier `\clknet_10_1016_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1569132: Warning: Identifier `\clknet_10_1017_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1569138: Warning: Identifier `\clknet_10_1018_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1569144: Warning: Identifier `\clknet_10_1019_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1569150: Warning: Identifier `\clknet_10_1020_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1569156: Warning: Identifier `\clknet_10_1021_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1569162: Warning: Identifier `\clknet_10_1022_0_wb_clk_i' is implicitly declared.
+/project/openlane/user_proj_example/runs/16-12_10-43/results/lvs/user_proj_example.lvs.powered.v:1569168: Warning: Identifier `\clknet_10_1023_0_wb_clk_i' is implicitly declared.
+Successfully finished Verilog frontend.
+
+2. Executing Verilog backend.
+Dumping module `\user_proj_example'.
+
+Warnings: 191535 unique messages, 191535 total
+End of script. Logfile hash: d90d680d96, CPU: user 4351.49s system 3.79s, MEM: 9025.24 MB peak
+Yosys 0.9+3621 (git sha1 84e9fa7, gcc 8.3.1 -fPIC -Os)
+Time spent: 88% 2x read_verilog (3852 sec), 11% 2x write_verilog (502 sec)
diff --git a/openlane/user_proj_example/results/logs/synthesis/yosys_runtime.txt b/openlane/user_proj_example/results/logs/synthesis/yosys_runtime.txt
new file mode 100644
index 0000000..119ffe0
--- /dev/null
+++ b/openlane/user_proj_example/results/logs/synthesis/yosys_runtime.txt
@@ -0,0 +1 @@
+0h8m46s353ms
diff --git a/openlane/user_proj_example/results/logs/write_verilog.log b/openlane/user_proj_example/results/logs/write_verilog.log
new file mode 100644
index 0000000..8850dea
--- /dev/null
+++ b/openlane/user_proj_example/results/logs/write_verilog.log
@@ -0,0 +1,27 @@
+OpenROAD 0.9.0 d03ebfc244
+This program is licensed under the BSD-3 license. See the LICENSE file for details.
+Components of this program may be licensed under more restrictive licenses which must be honored.
+Error: cannot open '/.openroad'.
+Notice 0: Reading LEF file: /project/openlane/user_proj_example/runs/16-12_10-43/tmp/merged_unpadded.lef
+Notice 0: Created 13 technology layers
+Notice 0: Created 25 technology vias
+Notice 0: Created 439 library cells
+Notice 0: Finished LEF file: /project/openlane/user_proj_example/runs/16-12_10-43/tmp/merged_unpadded.lef
+Notice 0:
+Reading DEF file: /project/openlane/user_proj_example/runs/16-12_10-43/tmp/routing/user_proj_example.powered.def
+Notice 0: Design: user_proj_example
+Notice 0: Created 100000 Insts
+Notice 0: Created 200000 Insts
+Notice 0: Created 300000 Insts
+Notice 0: Created 400000 Insts
+Notice 0: Created 500000 Insts
+Notice 0: Created 600000 Insts
+Notice 0: Created 700000 Insts
+Notice 0: Created 800000 Insts
+Notice 0: Created 900000 Insts
+Notice 0: Created 100000 Nets
+Notice 0: Created 606 pins.
+Notice 0: Created 927490 components and 4240852 component-terminals.
+Notice 0: Created 2 special nets and 0 connections.
+Notice 0: Created 192141 nets and 4240775 connections.
+Notice 0: Finished DEF file: /project/openlane/user_proj_example/runs/16-12_10-43/tmp/routing/user_proj_example.powered.def
diff --git a/openlane/user_proj_example/final_summary_report.csv b/openlane/user_proj_example/results/reports/final_summary_report.csv
similarity index 100%
rename from openlane/user_proj_example/final_summary_report.csv
rename to openlane/user_proj_example/results/reports/final_summary_report.csv
diff --git a/openlane/user_proj_example/results/reports/floorplan/verilog2def.core_area.rpt b/openlane/user_proj_example/results/reports/floorplan/verilog2def.core_area.rpt
new file mode 100644
index 0000000..7fedd1e
--- /dev/null
+++ b/openlane/user_proj_example/results/reports/floorplan/verilog2def.core_area.rpt
@@ -0,0 +1 @@
+5.5200000000000005 10.88 2494.48 3089.12
diff --git a/openlane/user_proj_example/results/reports/floorplan/verilog2def.die_area.rpt b/openlane/user_proj_example/results/reports/floorplan/verilog2def.die_area.rpt
new file mode 100644
index 0000000..9be469a
--- /dev/null
+++ b/openlane/user_proj_example/results/reports/floorplan/verilog2def.die_area.rpt
@@ -0,0 +1 @@
+0 0 2500 3100
diff --git a/openlane/user_proj_example/results/reports/magic/magic.antenna_violators.rpt b/openlane/user_proj_example/results/reports/magic/magic.antenna_violators.rpt
new file mode 100644
index 0000000..37e93bd
--- /dev/null
+++ b/openlane/user_proj_example/results/reports/magic/magic.antenna_violators.rpt
@@ -0,0 +1,13 @@
+_346161_
+_287770_
+_177104_
+_327273_
+_247758_
+_194512_
+_205026_
+_321052_
+_203246_
+_345548_
+_345865_
+_345495_
+_321049_
diff --git a/openlane/user_proj_example/results/reports/placement/openphysyn_allchecks.rpt b/openlane/user_proj_example/results/reports/placement/openphysyn_allchecks.rpt
new file mode 100644
index 0000000..5cad44c
--- /dev/null
+++ b/openlane/user_proj_example/results/reports/placement/openphysyn_allchecks.rpt
@@ -0,0 +1,82 @@
+Startpoint: la_data_in[2] (input port clocked by wb_clk_i)
+Endpoint: _346788_ (recovery check against rising-edge clock wb_clk_i)
+Path Group: **async_default**
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (ideal)
+ 4.00 4.00 v input external delay
+ 0.48 4.48 v la_data_in[2] (in)
+ 0.59 5.07 v _163808_/X (sky130_fd_sc_hd__or2_4)
+ 0.40 5.47 v _163809_/X (sky130_fd_sc_hd__buf_2)
+ 0.39 5.86 v _163810_/X (sky130_fd_sc_hd__buf_2)
+ 0.11 5.97 ^ _163811_/Y (sky130_fd_sc_hd__inv_2)
+ 0.41 6.38 ^ _163812_/X (sky130_fd_sc_hd__buf_2)
+ 0.39 6.77 ^ _163813_/X (sky130_fd_sc_hd__buf_2)
+ 0.57 7.34 ^ _163814_/X (sky130_fd_sc_hd__buf_2)
+ 0.93 8.27 ^ _172814_/X (sky130_fd_sc_hd__buf_2)
+ 0.55 8.82 ^ _172921_/X (sky130_fd_sc_hd__buf_2)
+ 0.20 9.02 ^ _172927_/X (sky130_fd_sc_hd__buf_2)
+ 0.00 9.02 ^ _346788_/SET_B (sky130_fd_sc_hd__dfstp_4)
+ 9.02 data arrival time
+
+ 20.00 20.00 clock wb_clk_i (rise edge)
+ 0.00 20.00 clock network delay (ideal)
+ 0.00 20.00 clock reconvergence pessimism
+ 20.00 ^ _346788_/CLK (sky130_fd_sc_hd__dfstp_4)
+ 0.25 20.25 library recovery time
+ 20.25 data required time
+---------------------------------------------------------
+ 20.25 data required time
+ -9.02 data arrival time
+---------------------------------------------------------
+ 11.22 slack (MET)
+
+
+Startpoint: wbs_adr_i[2] (input port clocked by wb_clk_i)
+Endpoint: _336470_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (ideal)
+ 4.00 4.00 v input external delay
+ 0.16 4.16 v wbs_adr_i[2] (in)
+ 0.81 4.97 v _160705_/X (sky130_fd_sc_hd__a32o_4)
+ 0.45 5.42 ^ _160706_/Y (sky130_fd_sc_hd__inv_2)
+ 0.62 6.04 ^ _162316_/X (sky130_fd_sc_hd__buf_2)
+ 0.73 6.77 ^ _162317_/X (sky130_fd_sc_hd__buf_2)
+ 1.10 7.86 ^ _162318_/X (sky130_fd_sc_hd__buf_2)
+ 1.51 9.38 ^ _162319_/X (sky130_fd_sc_hd__buf_2)
+ 1.35 10.72 ^ _162320_/X (sky130_fd_sc_hd__buf_2)
+ 0.84 11.57 ^ _162321_/X (sky130_fd_sc_hd__buf_2)
+ 0.70 12.27 ^ _162322_/X (sky130_fd_sc_hd__buf_2)
+ 0.38 12.65 ^ _162616_/X (sky130_fd_sc_hd__or4_4)
+ 0.69 13.34 ^ _163118_/X (sky130_fd_sc_hd__buf_2)
+ 1.03 14.38 ^ _205464_/X (sky130_fd_sc_hd__buf_2)
+ 1.17 15.55 ^ _205465_/X (sky130_fd_sc_hd__buf_2)
+ 0.56 16.11 ^ _205892_/X (sky130_fd_sc_hd__or2_4)
+ 0.96 17.07 ^ _205893_/X (sky130_fd_sc_hd__buf_2)
+ 0.56 17.63 v _247364_/Y (sky130_fd_sc_hd__nor2_4)
+ 0.43 18.06 v _247370_/X (sky130_fd_sc_hd__buf_2)
+ 0.38 18.44 v _247373_/X (sky130_fd_sc_hd__a2bb2o_4)
+ 0.00 18.44 v _336470_/D (sky130_fd_sc_hd__dfxtp_4)
+ 18.44 data arrival time
+
+ 20.00 20.00 clock wb_clk_i (rise edge)
+ 0.00 20.00 clock network delay (ideal)
+ 0.00 20.00 clock reconvergence pessimism
+ 20.00 ^ _336470_/CLK (sky130_fd_sc_hd__dfxtp_4)
+ -0.28 19.72 library setup time
+ 19.72 data required time
+---------------------------------------------------------
+ 19.72 data required time
+ -18.44 data arrival time
+---------------------------------------------------------
+ 1.28 slack (MET)
+
+
diff --git a/openlane/user_proj_example/results/reports/placement/openphysyn_tns.rpt b/openlane/user_proj_example/results/reports/placement/openphysyn_tns.rpt
new file mode 100644
index 0000000..53df237
--- /dev/null
+++ b/openlane/user_proj_example/results/reports/placement/openphysyn_tns.rpt
@@ -0,0 +1 @@
+tns 0.00
diff --git a/openlane/user_proj_example/results/reports/placement/openphysyn_violators.rpt b/openlane/user_proj_example/results/reports/placement/openphysyn_violators.rpt
new file mode 100644
index 0000000..f303bee
--- /dev/null
+++ b/openlane/user_proj_example/results/reports/placement/openphysyn_violators.rpt
@@ -0,0 +1,125 @@
+max slew
+
+Pin Limit Slew Slack
+------------------------------------------------------------
+_197601_/A 1.50 1.98 -0.48 (VIOLATED)
+_203967_/A 1.50 1.98 -0.48 (VIOLATED)
+_240878_/A 1.50 1.98 -0.48 (VIOLATED)
+_258390_/A 1.50 1.98 -0.48 (VIOLATED)
+_193765_/A 1.50 1.97 -0.47 (VIOLATED)
+_193764_/X 1.51 1.97 -0.46 (VIOLATED)
+_225969_/A 1.50 1.91 -0.41 (VIOLATED)
+_219757_/A 1.50 1.91 -0.41 (VIOLATED)
+_198854_/A 1.50 1.91 -0.41 (VIOLATED)
+_259592_/A 1.50 1.90 -0.40 (VIOLATED)
+_193741_/A 1.50 1.90 -0.40 (VIOLATED)
+_196295_/A 1.50 1.90 -0.40 (VIOLATED)
+_202679_/A 1.50 1.90 -0.40 (VIOLATED)
+_193726_/A 1.50 1.90 -0.40 (VIOLATED)
+_239580_/A 1.50 1.90 -0.40 (VIOLATED)
+_245778_/A 1.50 1.90 -0.40 (VIOLATED)
+_247236_/A 1.50 1.90 -0.40 (VIOLATED)
+_247348_/A 1.50 1.89 -0.39 (VIOLATED)
+_247457_/A 1.50 1.89 -0.39 (VIOLATED)
+_193740_/X 1.51 1.90 -0.39 (VIOLATED)
+_259594_/A 1.50 1.89 -0.39 (VIOLATED)
+_242094_/A 1.50 1.89 -0.39 (VIOLATED)
+_228298_/A 1.50 1.89 -0.39 (VIOLATED)
+_245815_/A 1.50 1.89 -0.39 (VIOLATED)
+_193725_/X 1.51 1.90 -0.39 (VIOLATED)
+_193744_/A 1.50 1.88 -0.38 (VIOLATED)
+_198856_/A 1.50 1.88 -0.38 (VIOLATED)
+_193749_/A 1.50 1.88 -0.38 (VIOLATED)
+_247566_/A 1.50 1.88 -0.38 (VIOLATED)
+_247675_/A 1.50 1.87 -0.37 (VIOLATED)
+_193743_/X 1.51 1.88 -0.37 (VIOLATED)
+_223491_/A 1.50 1.87 -0.37 (VIOLATED)
+_202688_/A 1.50 1.87 -0.37 (VIOLATED)
+_196304_/A 1.50 1.87 -0.37 (VIOLATED)
+_247235_/X 1.51 1.87 -0.36 (VIOLATED)
+_193748_/X 1.51 1.87 -0.36 (VIOLATED)
+_163115_/A 1.50 1.85 -0.35 (VIOLATED)
+_193691_/A 1.50 1.85 -0.35 (VIOLATED)
+_162509_/A 1.50 1.85 -0.35 (VIOLATED)
+_266315_/A 1.50 1.82 -0.32 (VIOLATED)
+_267342_/A 1.50 1.82 -0.32 (VIOLATED)
+_162508_/X 1.51 1.82 -0.31 (VIOLATED)
+_193660_/A 1.50 1.78 -0.28 (VIOLATED)
+_162320_/A 1.50 1.78 -0.28 (VIOLATED)
+_193373_/A 1.50 1.78 -0.28 (VIOLATED)
+_162921_/B 1.50 1.77 -0.27 (VIOLATED)
+_243513_/A 1.50 1.76 -0.26 (VIOLATED)
+_261008_/A 1.50 1.76 -0.26 (VIOLATED)
+_193274_/A 1.50 1.76 -0.26 (VIOLATED)
+_220807_/A 1.50 1.75 -0.25 (VIOLATED)
+_199931_/A 1.50 1.75 -0.25 (VIOLATED)
+_267319_/B 1.50 1.75 -0.25 (VIOLATED)
+_193273_/X 1.51 1.75 -0.24 (VIOLATED)
+_162319_/X 1.51 1.75 -0.24 (VIOLATED)
+_225708_/A 1.50 1.74 -0.24 (VIOLATED)
+_201154_/A 1.50 1.74 -0.24 (VIOLATED)
+_193100_/A 1.50 1.73 -0.23 (VIOLATED)
+_199979_/A 1.50 1.73 -0.23 (VIOLATED)
+_193761_/A 1.50 1.71 -0.21 (VIOLATED)
+_193099_/X 1.51 1.71 -0.20 (VIOLATED)
+_267398_/B 1.50 1.67 -0.17 (VIOLATED)
+_267338_/B 1.50 1.67 -0.17 (VIOLATED)
+_267386_/B 1.50 1.67 -0.17 (VIOLATED)
+_200631_/A 1.50 1.67 -0.17 (VIOLATED)
+_194950_/A 1.50 1.67 -0.17 (VIOLATED)
+_194949_/X 1.51 1.67 -0.16 (VIOLATED)
+_198531_/A 1.50 1.61 -0.11 (VIOLATED)
+_194173_/A 1.50 1.61 -0.11 (VIOLATED)
+_193909_/A 1.50 1.61 -0.11 (VIOLATED)
+_193819_/A 1.50 1.61 -0.11 (VIOLATED)
+_195979_/A 1.50 1.60 -0.10 (VIOLATED)
+_193818_/X 1.51 1.60 -0.09 (VIOLATED)
+_193609_/A 1.50 1.59 -0.09 (VIOLATED)
+_193312_/A 1.50 1.59 -0.09 (VIOLATED)
+_203718_/A 1.50 1.59 -0.09 (VIOLATED)
+_194790_/A 1.50 1.59 -0.09 (VIOLATED)
+_193196_/A 1.50 1.59 -0.09 (VIOLATED)
+_193195_/X 1.51 1.59 -0.08 (VIOLATED)
+_201848_/A 1.50 1.58 -0.08 (VIOLATED)
+_194776_/A 1.50 1.58 -0.08 (VIOLATED)
+_196830_/A 1.50 1.57 -0.07 (VIOLATED)
+_194953_/A 1.50 1.57 -0.07 (VIOLATED)
+_195149_/A 1.50 1.57 -0.07 (VIOLATED)
+_291120_/A 1.50 1.57 -0.07 (VIOLATED)
+_186551_/A 1.50 1.57 -0.07 (VIOLATED)
+_194775_/X 1.51 1.57 -0.06 (VIOLATED)
+_240282_/A 1.50 1.56 -0.06 (VIOLATED)
+_246473_/A 1.50 1.56 -0.06 (VIOLATED)
+_227786_/A 1.50 1.56 -0.06 (VIOLATED)
+_241589_/A 1.50 1.56 -0.06 (VIOLATED)
+_259094_/A 1.50 1.56 -0.06 (VIOLATED)
+_196887_/A 1.50 1.55 -0.05 (VIOLATED)
+_203268_/A 1.50 1.55 -0.05 (VIOLATED)
+_195156_/A 1.50 1.55 -0.05 (VIOLATED)
+_196687_/A 1.50 1.55 -0.05 (VIOLATED)
+_194660_/A 1.50 1.55 -0.05 (VIOLATED)
+_195155_/X 1.51 1.55 -0.04 (VIOLATED)
+_194659_/X 1.51 1.55 -0.04 (VIOLATED)
+_178875_/A 1.50 1.54 -0.04 (VIOLATED)
+_280589_/A 1.50 1.53 -0.03 (VIOLATED)
+_186545_/A 1.50 1.52 -0.02 (VIOLATED)
+_291114_/A 1.50 1.52 -0.02 (VIOLATED)
+_301013_/A 1.50 1.51 -0.01 (VIOLATED)
+_291141_/A 1.50 1.51 -0.01 (VIOLATED)
+_291136_/A 1.50 1.51 -0.01 (VIOLATED)
+_174139_/A 1.50 1.50 -0.00 (VIOLATED)
+_164158_/A 1.50 1.50 -0.00 (VIOLATED)
+
+max capacitance
+
+Pin Limit Cap Slack
+------------------------------------------------------------
+_193764_/X 0.20 0.23 -0.03 (VIOLATED)
+_193740_/X 0.20 0.22 -0.02 (VIOLATED)
+_193725_/X 0.20 0.22 -0.02 (VIOLATED)
+_193743_/X 0.20 0.22 -0.02 (VIOLATED)
+_193748_/X 0.20 0.21 -0.01 (VIOLATED)
+_247235_/X 0.20 0.21 -0.01 (VIOLATED)
+_162508_/X 0.20 0.20 -0.01 (VIOLATED)
+_193273_/X 0.20 0.20 -0.00 (VIOLATED)
+
diff --git a/openlane/user_proj_example/results/reports/placement/openphysyn_wns.rpt b/openlane/user_proj_example/results/reports/placement/openphysyn_wns.rpt
new file mode 100644
index 0000000..3196164
--- /dev/null
+++ b/openlane/user_proj_example/results/reports/placement/openphysyn_wns.rpt
@@ -0,0 +1 @@
+wns 0.00
diff --git a/openlane/user_proj_example/results/reports/placement/replace.min_max.rpt b/openlane/user_proj_example/results/reports/placement/replace.min_max.rpt
new file mode 100644
index 0000000..e75c822
--- /dev/null
+++ b/openlane/user_proj_example/results/reports/placement/replace.min_max.rpt
@@ -0,0 +1,143 @@
+Startpoint: _345957_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _346223_ (removal check against rising-edge clock wb_clk_i)
+Path Group: **async_default**
+Path Type: min
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (ideal)
+ 0.00 0.00 ^ _345957_/CLK (sky130_fd_sc_hd__dfstp_4)
+ 0.34 0.34 v _345957_/Q (sky130_fd_sc_hd__dfstp_4)
+ 0.35 0.69 v _167854_/X (sky130_fd_sc_hd__or2_4)
+ 0.11 0.80 v _167855_/X (sky130_fd_sc_hd__buf_2)
+ 0.08 0.88 ^ _167856_/Y (sky130_fd_sc_hd__inv_2)
+ 0.14 1.02 ^ _167857_/X (sky130_fd_sc_hd__buf_2)
+ 0.15 1.17 ^ _167858_/X (sky130_fd_sc_hd__buf_2)
+ 0.13 1.30 ^ _167859_/X (sky130_fd_sc_hd__buf_2)
+ 0.13 1.44 ^ _177983_/X (sky130_fd_sc_hd__buf_2)
+ 0.10 1.53 ^ _178320_/X (sky130_fd_sc_hd__buf_2)
+ 0.07 1.60 ^ _178365_/X (sky130_fd_sc_hd__buf_2)
+ 0.00 1.60 ^ _346223_/RESET_B (sky130_fd_sc_hd__dfrtp_4)
+ 1.60 data arrival time
+
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (ideal)
+ 0.00 0.00 clock reconvergence pessimism
+ 0.00 ^ _346223_/CLK (sky130_fd_sc_hd__dfrtp_4)
+ 0.19 0.19 library removal time
+ 0.19 data required time
+---------------------------------------------------------
+ 0.19 data required time
+ -1.60 data arrival time
+---------------------------------------------------------
+ 1.41 slack (MET)
+
+
+Startpoint: _347131_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _321095_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (ideal)
+ 0.00 0.00 ^ _347131_/CLK (sky130_fd_sc_hd__dfxtp_4)
+ 0.21 0.21 ^ _347131_/Q (sky130_fd_sc_hd__dfxtp_4)
+ 0.00 0.21 ^ _321095_/D (sky130_fd_sc_hd__dfxtp_4)
+ 0.21 data arrival time
+
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (ideal)
+ 0.00 0.00 clock reconvergence pessimism
+ 0.00 ^ _321095_/CLK (sky130_fd_sc_hd__dfxtp_4)
+ -0.02 -0.02 library hold time
+ -0.02 data required time
+---------------------------------------------------------
+ -0.02 data required time
+ -0.21 data arrival time
+---------------------------------------------------------
+ 0.22 slack (MET)
+
+
+Startpoint: la_data_in[2] (input port clocked by wb_clk_i)
+Endpoint: _346788_ (recovery check against rising-edge clock wb_clk_i)
+Path Group: **async_default**
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (ideal)
+ 4.00 4.00 v input external delay
+ 0.01 4.01 v la_data_in[2] (in)
+ 0.49 4.50 v _163808_/X (sky130_fd_sc_hd__or2_4)
+ 0.39 4.89 v _163809_/X (sky130_fd_sc_hd__buf_2)
+ 0.38 5.27 v _163810_/X (sky130_fd_sc_hd__buf_2)
+ 0.10 5.38 ^ _163811_/Y (sky130_fd_sc_hd__inv_2)
+ 0.41 5.79 ^ _163812_/X (sky130_fd_sc_hd__buf_2)
+ 0.37 6.16 ^ _163813_/X (sky130_fd_sc_hd__buf_2)
+ 0.56 6.72 ^ _163814_/X (sky130_fd_sc_hd__buf_2)
+ 0.91 7.63 ^ _172814_/X (sky130_fd_sc_hd__buf_2)
+ 0.52 8.15 ^ _172921_/X (sky130_fd_sc_hd__buf_2)
+ 0.20 8.34 ^ _172927_/X (sky130_fd_sc_hd__buf_2)
+ 0.00 8.34 ^ _346788_/SET_B (sky130_fd_sc_hd__dfstp_4)
+ 8.34 data arrival time
+
+ 20.00 20.00 clock wb_clk_i (rise edge)
+ 0.00 20.00 clock network delay (ideal)
+ 0.00 20.00 clock reconvergence pessimism
+ 20.00 ^ _346788_/CLK (sky130_fd_sc_hd__dfstp_4)
+ 0.25 20.25 library recovery time
+ 20.25 data required time
+---------------------------------------------------------
+ 20.25 data required time
+ -8.34 data arrival time
+---------------------------------------------------------
+ 11.91 slack (MET)
+
+
+Startpoint: wbs_adr_i[2] (input port clocked by wb_clk_i)
+Endpoint: wbs_dat_o[7] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (ideal)
+ 4.00 4.00 ^ input external delay
+ 0.01 4.01 ^ wbs_adr_i[2] (in)
+ 0.78 4.78 ^ _160705_/X (sky130_fd_sc_hd__a32o_4)
+ 1.01 5.80 ^ _160712_/X (sky130_fd_sc_hd__buf_2)
+ 0.52 6.32 ^ _162471_/X (sky130_fd_sc_hd__buf_2)
+ 1.19 7.51 ^ _162472_/X (sky130_fd_sc_hd__buf_2)
+ 1.16 8.67 ^ _162473_/X (sky130_fd_sc_hd__buf_2)
+ 0.91 9.58 ^ _162474_/X (sky130_fd_sc_hd__buf_2)
+ 0.81 10.39 ^ _163102_/X (sky130_fd_sc_hd__or4_4)
+ 0.46 10.85 ^ _164092_/X (sky130_fd_sc_hd__or4_4)
+ 0.30 11.16 ^ _164093_/X (sky130_fd_sc_hd__buf_2)
+ 0.10 11.26 v _164094_/Y (sky130_fd_sc_hd__inv_2)
+ 0.41 11.67 v _280957_/X (sky130_fd_sc_hd__or2_4)
+ 0.34 12.01 v _280958_/X (sky130_fd_sc_hd__buf_2)
+ 0.34 12.35 v _281237_/X (sky130_fd_sc_hd__buf_2)
+ 0.46 12.81 v _281238_/X (sky130_fd_sc_hd__or2_4)
+ 0.56 13.37 v _281240_/X (sky130_fd_sc_hd__a32o_4)
+ 2.04 15.41 ^ _281241_/Y (sky130_fd_sc_hd__a22oi_4)
+ 0.85 16.26 v _312746_/Y (sky130_fd_sc_hd__inv_2)
+ 0.00 16.26 v wbs_dat_o[7] (out)
+ 16.26 data arrival time
+
+ 20.00 20.00 clock wb_clk_i (rise edge)
+ 0.00 20.00 clock network delay (ideal)
+ 0.00 20.00 clock reconvergence pessimism
+ -4.00 16.00 output external delay
+ 16.00 data required time
+---------------------------------------------------------
+ 16.00 data required time
+ -16.26 data arrival time
+---------------------------------------------------------
+ -0.26 slack (VIOLATED)
+
+
diff --git a/openlane/user_proj_example/results/reports/placement/replace.rpt b/openlane/user_proj_example/results/reports/placement/replace.rpt
new file mode 100644
index 0000000..6a6e7f1
--- /dev/null
+++ b/openlane/user_proj_example/results/reports/placement/replace.rpt
@@ -0,0 +1,86 @@
+Startpoint: wbs_adr_i[2] (input port clocked by wb_clk_i)
+Endpoint: wbs_dat_o[7] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (ideal)
+ 4.00 4.00 ^ input external delay
+ 0.01 4.01 ^ wbs_adr_i[2] (in)
+ 0.78 4.78 ^ _160705_/X (sky130_fd_sc_hd__a32o_4)
+ 1.01 5.80 ^ _160712_/X (sky130_fd_sc_hd__buf_2)
+ 0.52 6.32 ^ _162471_/X (sky130_fd_sc_hd__buf_2)
+ 1.19 7.51 ^ _162472_/X (sky130_fd_sc_hd__buf_2)
+ 1.16 8.67 ^ _162473_/X (sky130_fd_sc_hd__buf_2)
+ 0.91 9.58 ^ _162474_/X (sky130_fd_sc_hd__buf_2)
+ 0.81 10.39 ^ _163102_/X (sky130_fd_sc_hd__or4_4)
+ 0.46 10.85 ^ _164092_/X (sky130_fd_sc_hd__or4_4)
+ 0.30 11.16 ^ _164093_/X (sky130_fd_sc_hd__buf_2)
+ 0.10 11.26 v _164094_/Y (sky130_fd_sc_hd__inv_2)
+ 0.41 11.67 v _280957_/X (sky130_fd_sc_hd__or2_4)
+ 0.34 12.01 v _280958_/X (sky130_fd_sc_hd__buf_2)
+ 0.34 12.35 v _281237_/X (sky130_fd_sc_hd__buf_2)
+ 0.46 12.81 v _281238_/X (sky130_fd_sc_hd__or2_4)
+ 0.56 13.37 v _281240_/X (sky130_fd_sc_hd__a32o_4)
+ 2.04 15.41 ^ _281241_/Y (sky130_fd_sc_hd__a22oi_4)
+ 0.85 16.26 v _312746_/Y (sky130_fd_sc_hd__inv_2)
+ 0.00 16.26 v wbs_dat_o[7] (out)
+ 16.26 data arrival time
+
+ 20.00 20.00 clock wb_clk_i (rise edge)
+ 0.00 20.00 clock network delay (ideal)
+ 0.00 20.00 clock reconvergence pessimism
+ -4.00 16.00 output external delay
+ 16.00 data required time
+---------------------------------------------------------
+ 16.00 data required time
+ -16.26 data arrival time
+---------------------------------------------------------
+ -0.26 slack (VIOLATED)
+
+
+Startpoint: wbs_adr_i[2] (input port clocked by wb_clk_i)
+Endpoint: wbs_dat_o[6] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (ideal)
+ 4.00 4.00 ^ input external delay
+ 0.01 4.01 ^ wbs_adr_i[2] (in)
+ 0.78 4.78 ^ _160705_/X (sky130_fd_sc_hd__a32o_4)
+ 1.01 5.80 ^ _160712_/X (sky130_fd_sc_hd__buf_2)
+ 0.52 6.32 ^ _162471_/X (sky130_fd_sc_hd__buf_2)
+ 1.19 7.51 ^ _162472_/X (sky130_fd_sc_hd__buf_2)
+ 1.16 8.67 ^ _162473_/X (sky130_fd_sc_hd__buf_2)
+ 0.91 9.58 ^ _162474_/X (sky130_fd_sc_hd__buf_2)
+ 0.81 10.39 ^ _163102_/X (sky130_fd_sc_hd__or4_4)
+ 0.46 10.85 ^ _164092_/X (sky130_fd_sc_hd__or4_4)
+ 0.30 11.16 ^ _164093_/X (sky130_fd_sc_hd__buf_2)
+ 0.10 11.26 v _164094_/Y (sky130_fd_sc_hd__inv_2)
+ 0.41 11.67 v _280957_/X (sky130_fd_sc_hd__or2_4)
+ 0.34 12.01 v _280958_/X (sky130_fd_sc_hd__buf_2)
+ 0.34 12.35 v _281237_/X (sky130_fd_sc_hd__buf_2)
+ 0.46 12.81 v _281254_/X (sky130_fd_sc_hd__or2_4)
+ 0.56 13.37 v _281255_/X (sky130_fd_sc_hd__a32o_4)
+ 2.02 15.39 ^ _281256_/Y (sky130_fd_sc_hd__a22oi_4)
+ 0.85 16.24 v _312745_/Y (sky130_fd_sc_hd__inv_2)
+ 0.00 16.24 v wbs_dat_o[6] (out)
+ 16.24 data arrival time
+
+ 20.00 20.00 clock wb_clk_i (rise edge)
+ 0.00 20.00 clock network delay (ideal)
+ 0.00 20.00 clock reconvergence pessimism
+ -4.00 16.00 output external delay
+ 16.00 data required time
+---------------------------------------------------------
+ 16.00 data required time
+ -16.24 data arrival time
+---------------------------------------------------------
+ -0.24 slack (VIOLATED)
+
+
diff --git a/openlane/user_proj_example/results/reports/placement/replace.timing.rpt b/openlane/user_proj_example/results/reports/placement/replace.timing.rpt
new file mode 100644
index 0000000..6a6e7f1
--- /dev/null
+++ b/openlane/user_proj_example/results/reports/placement/replace.timing.rpt
@@ -0,0 +1,86 @@
+Startpoint: wbs_adr_i[2] (input port clocked by wb_clk_i)
+Endpoint: wbs_dat_o[7] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (ideal)
+ 4.00 4.00 ^ input external delay
+ 0.01 4.01 ^ wbs_adr_i[2] (in)
+ 0.78 4.78 ^ _160705_/X (sky130_fd_sc_hd__a32o_4)
+ 1.01 5.80 ^ _160712_/X (sky130_fd_sc_hd__buf_2)
+ 0.52 6.32 ^ _162471_/X (sky130_fd_sc_hd__buf_2)
+ 1.19 7.51 ^ _162472_/X (sky130_fd_sc_hd__buf_2)
+ 1.16 8.67 ^ _162473_/X (sky130_fd_sc_hd__buf_2)
+ 0.91 9.58 ^ _162474_/X (sky130_fd_sc_hd__buf_2)
+ 0.81 10.39 ^ _163102_/X (sky130_fd_sc_hd__or4_4)
+ 0.46 10.85 ^ _164092_/X (sky130_fd_sc_hd__or4_4)
+ 0.30 11.16 ^ _164093_/X (sky130_fd_sc_hd__buf_2)
+ 0.10 11.26 v _164094_/Y (sky130_fd_sc_hd__inv_2)
+ 0.41 11.67 v _280957_/X (sky130_fd_sc_hd__or2_4)
+ 0.34 12.01 v _280958_/X (sky130_fd_sc_hd__buf_2)
+ 0.34 12.35 v _281237_/X (sky130_fd_sc_hd__buf_2)
+ 0.46 12.81 v _281238_/X (sky130_fd_sc_hd__or2_4)
+ 0.56 13.37 v _281240_/X (sky130_fd_sc_hd__a32o_4)
+ 2.04 15.41 ^ _281241_/Y (sky130_fd_sc_hd__a22oi_4)
+ 0.85 16.26 v _312746_/Y (sky130_fd_sc_hd__inv_2)
+ 0.00 16.26 v wbs_dat_o[7] (out)
+ 16.26 data arrival time
+
+ 20.00 20.00 clock wb_clk_i (rise edge)
+ 0.00 20.00 clock network delay (ideal)
+ 0.00 20.00 clock reconvergence pessimism
+ -4.00 16.00 output external delay
+ 16.00 data required time
+---------------------------------------------------------
+ 16.00 data required time
+ -16.26 data arrival time
+---------------------------------------------------------
+ -0.26 slack (VIOLATED)
+
+
+Startpoint: wbs_adr_i[2] (input port clocked by wb_clk_i)
+Endpoint: wbs_dat_o[6] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (ideal)
+ 4.00 4.00 ^ input external delay
+ 0.01 4.01 ^ wbs_adr_i[2] (in)
+ 0.78 4.78 ^ _160705_/X (sky130_fd_sc_hd__a32o_4)
+ 1.01 5.80 ^ _160712_/X (sky130_fd_sc_hd__buf_2)
+ 0.52 6.32 ^ _162471_/X (sky130_fd_sc_hd__buf_2)
+ 1.19 7.51 ^ _162472_/X (sky130_fd_sc_hd__buf_2)
+ 1.16 8.67 ^ _162473_/X (sky130_fd_sc_hd__buf_2)
+ 0.91 9.58 ^ _162474_/X (sky130_fd_sc_hd__buf_2)
+ 0.81 10.39 ^ _163102_/X (sky130_fd_sc_hd__or4_4)
+ 0.46 10.85 ^ _164092_/X (sky130_fd_sc_hd__or4_4)
+ 0.30 11.16 ^ _164093_/X (sky130_fd_sc_hd__buf_2)
+ 0.10 11.26 v _164094_/Y (sky130_fd_sc_hd__inv_2)
+ 0.41 11.67 v _280957_/X (sky130_fd_sc_hd__or2_4)
+ 0.34 12.01 v _280958_/X (sky130_fd_sc_hd__buf_2)
+ 0.34 12.35 v _281237_/X (sky130_fd_sc_hd__buf_2)
+ 0.46 12.81 v _281254_/X (sky130_fd_sc_hd__or2_4)
+ 0.56 13.37 v _281255_/X (sky130_fd_sc_hd__a32o_4)
+ 2.02 15.39 ^ _281256_/Y (sky130_fd_sc_hd__a22oi_4)
+ 0.85 16.24 v _312745_/Y (sky130_fd_sc_hd__inv_2)
+ 0.00 16.24 v wbs_dat_o[6] (out)
+ 16.24 data arrival time
+
+ 20.00 20.00 clock wb_clk_i (rise edge)
+ 0.00 20.00 clock network delay (ideal)
+ 0.00 20.00 clock reconvergence pessimism
+ -4.00 16.00 output external delay
+ 16.00 data required time
+---------------------------------------------------------
+ 16.00 data required time
+ -16.24 data arrival time
+---------------------------------------------------------
+ -0.24 slack (VIOLATED)
+
+
diff --git a/openlane/user_proj_example/results/reports/placement/replace_tns.rpt b/openlane/user_proj_example/results/reports/placement/replace_tns.rpt
new file mode 100644
index 0000000..8bcc779
--- /dev/null
+++ b/openlane/user_proj_example/results/reports/placement/replace_tns.rpt
@@ -0,0 +1 @@
+tns -0.50
diff --git a/openlane/user_proj_example/results/reports/placement/replace_wns.rpt b/openlane/user_proj_example/results/reports/placement/replace_wns.rpt
new file mode 100644
index 0000000..187545a
--- /dev/null
+++ b/openlane/user_proj_example/results/reports/placement/replace_wns.rpt
@@ -0,0 +1 @@
+wns -0.26
diff --git a/openlane/user_proj_example/results/reports/routing/antenna.rpt.gz b/openlane/user_proj_example/results/reports/routing/antenna.rpt.gz
new file mode 100644
index 0000000..86478ba
--- /dev/null
+++ b/openlane/user_proj_example/results/reports/routing/antenna.rpt.gz
Binary files differ
diff --git a/openlane/user_proj_example/results/reports/routing/fastroute.min_max.rpt b/openlane/user_proj_example/results/reports/routing/fastroute.min_max.rpt
new file mode 100644
index 0000000..7d805ae
--- /dev/null
+++ b/openlane/user_proj_example/results/reports/routing/fastroute.min_max.rpt
@@ -0,0 +1,145 @@
+Startpoint: _345957_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _346223_ (removal check against rising-edge clock wb_clk_i)
+Path Group: **async_default**
+Path Type: min
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (ideal)
+ 0.00 0.00 ^ _345957_/CLK (sky130_fd_sc_hd__dfstp_4)
+ 0.39 0.39 v _345957_/Q (sky130_fd_sc_hd__dfstp_4)
+ 0.38 0.77 v _167854_/X (sky130_fd_sc_hd__or2_4)
+ 0.12 0.89 v _167855_/X (sky130_fd_sc_hd__buf_2)
+ 0.10 0.99 ^ _167856_/Y (sky130_fd_sc_hd__inv_2)
+ 0.16 1.15 ^ _167857_/X (sky130_fd_sc_hd__buf_2)
+ 0.17 1.32 ^ _167858_/X (sky130_fd_sc_hd__buf_2)
+ 0.15 1.47 ^ _167859_/X (sky130_fd_sc_hd__buf_2)
+ 0.16 1.64 ^ _177983_/X (sky130_fd_sc_hd__buf_2)
+ 0.12 1.75 ^ _178320_/X (sky130_fd_sc_hd__buf_2)
+ 0.07 1.83 ^ _178365_/X (sky130_fd_sc_hd__buf_2)
+ 0.00 1.83 ^ _346223_/RESET_B (sky130_fd_sc_hd__dfrtp_4)
+ 1.83 data arrival time
+
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (ideal)
+ 0.00 0.00 clock reconvergence pessimism
+ 0.00 ^ _346223_/CLK (sky130_fd_sc_hd__dfrtp_4)
+ 0.27 0.27 library removal time
+ 0.27 data required time
+---------------------------------------------------------
+ 0.27 data required time
+ -1.83 data arrival time
+---------------------------------------------------------
+ 1.56 slack (MET)
+
+
+Startpoint: _347129_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _321093_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (ideal)
+ 0.00 0.00 ^ _347129_/CLK (sky130_fd_sc_hd__dfxtp_4)
+ 0.24 0.24 v _347129_/Q (sky130_fd_sc_hd__dfxtp_4)
+ 0.00 0.25 v _321093_/D (sky130_fd_sc_hd__dfxtp_4)
+ 0.25 data arrival time
+
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (ideal)
+ 0.00 0.00 clock reconvergence pessimism
+ 0.00 ^ _321093_/CLK (sky130_fd_sc_hd__dfxtp_4)
+ 0.00 0.00 library hold time
+ 0.00 data required time
+---------------------------------------------------------
+ 0.00 data required time
+ -0.25 data arrival time
+---------------------------------------------------------
+ 0.25 slack (MET)
+
+
+Startpoint: la_data_in[2] (input port clocked by wb_clk_i)
+Endpoint: _346785_ (recovery check against rising-edge clock wb_clk_i)
+Path Group: **async_default**
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (ideal)
+ 4.00 4.00 v input external delay
+ 0.21 4.21 v la_data_in[2] (in)
+ 0.62 4.83 v _163808_/X (sky130_fd_sc_hd__or2_4)
+ 0.41 5.24 v _163809_/X (sky130_fd_sc_hd__buf_2)
+ 0.42 5.66 v _163810_/X (sky130_fd_sc_hd__buf_2)
+ 0.14 5.80 ^ _163811_/Y (sky130_fd_sc_hd__inv_2)
+ 0.45 6.26 ^ _163812_/X (sky130_fd_sc_hd__buf_2)
+ 0.41 6.66 ^ _163813_/X (sky130_fd_sc_hd__buf_2)
+ 0.59 7.25 ^ _163814_/X (sky130_fd_sc_hd__buf_2)
+ 0.93 8.18 ^ _172814_/X (sky130_fd_sc_hd__buf_2)
+ 0.57 8.75 ^ _172921_/X (sky130_fd_sc_hd__buf_2)
+ 0.22 8.97 ^ _172981_/X (sky130_fd_sc_hd__buf_2)
+ 0.00 8.97 ^ _346785_/SET_B (sky130_fd_sc_hd__dfstp_4)
+ 8.97 data arrival time
+
+ 20.00 20.00 clock wb_clk_i (rise edge)
+ 0.00 20.00 clock network delay (ideal)
+ 0.00 20.00 clock reconvergence pessimism
+ 20.00 ^ _346785_/CLK (sky130_fd_sc_hd__dfstp_4)
+ 0.31 20.31 library recovery time
+ 20.31 data required time
+---------------------------------------------------------
+ 20.31 data required time
+ -8.97 data arrival time
+---------------------------------------------------------
+ 11.35 slack (MET)
+
+
+Startpoint: wbs_adr_i[2] (input port clocked by wb_clk_i)
+Endpoint: _332376_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (ideal)
+ 4.00 4.00 v input external delay
+ 0.14 4.14 v wbs_adr_i[2] (in)
+ 0.86 5.00 v _160705_/X (sky130_fd_sc_hd__a32o_4)
+ 0.29 5.29 ^ _160706_/Y (sky130_fd_sc_hd__inv_2)
+ 0.64 5.92 ^ _162316_/X (sky130_fd_sc_hd__buf_2)
+ 0.75 6.68 ^ _162317_/X (sky130_fd_sc_hd__buf_2)
+ 1.11 7.79 ^ _162318_/X (sky130_fd_sc_hd__buf_2)
+ 1.63 9.42 ^ _162319_/X (sky130_fd_sc_hd__buf_2)
+ 1.30 10.72 ^ _162320_/X (sky130_fd_sc_hd__buf_2)
+ 0.87 11.59 ^ _162321_/X (sky130_fd_sc_hd__buf_2)
+ 0.76 12.35 ^ _162322_/X (sky130_fd_sc_hd__buf_2)
+ 0.39 12.74 ^ _162616_/X (sky130_fd_sc_hd__or4_4)
+ 0.70 13.44 ^ _163118_/X (sky130_fd_sc_hd__buf_2)
+ 1.05 14.50 ^ _205464_/X (sky130_fd_sc_hd__buf_2)
+ 1.18 15.67 ^ _205465_/X (sky130_fd_sc_hd__buf_2)
+ 0.67 16.35 ^ _205892_/X (sky130_fd_sc_hd__or2_4)
+ 0.91 17.26 ^ _205893_/X (sky130_fd_sc_hd__buf_2)
+ 0.52 17.77 v _267880_/Y (sky130_fd_sc_hd__nor2_4)
+ 0.40 18.17 v _267881_/X (sky130_fd_sc_hd__buf_2)
+ 0.40 18.57 v _267886_/X (sky130_fd_sc_hd__a2bb2o_4)
+ 0.00 18.57 v _332376_/D (sky130_fd_sc_hd__dfxtp_4)
+ 18.57 data arrival time
+
+ 20.00 20.00 clock wb_clk_i (rise edge)
+ 0.00 20.00 clock network delay (ideal)
+ 0.00 20.00 clock reconvergence pessimism
+ 20.00 ^ _332376_/CLK (sky130_fd_sc_hd__dfxtp_4)
+ -0.20 19.80 library setup time
+ 19.80 data required time
+---------------------------------------------------------
+ 19.80 data required time
+ -18.57 data arrival time
+---------------------------------------------------------
+ 1.23 slack (MET)
+
+
diff --git a/openlane/user_proj_example/results/reports/routing/fastroute.rpt b/openlane/user_proj_example/results/reports/routing/fastroute.rpt
new file mode 100644
index 0000000..804fb12
--- /dev/null
+++ b/openlane/user_proj_example/results/reports/routing/fastroute.rpt
@@ -0,0 +1 @@
+No paths found.
diff --git a/openlane/user_proj_example/results/reports/routing/fastroute.timing.rpt b/openlane/user_proj_example/results/reports/routing/fastroute.timing.rpt
new file mode 100644
index 0000000..804fb12
--- /dev/null
+++ b/openlane/user_proj_example/results/reports/routing/fastroute.timing.rpt
@@ -0,0 +1 @@
+No paths found.
diff --git a/openlane/user_proj_example/results/reports/routing/fastroute_tns.rpt b/openlane/user_proj_example/results/reports/routing/fastroute_tns.rpt
new file mode 100644
index 0000000..53df237
--- /dev/null
+++ b/openlane/user_proj_example/results/reports/routing/fastroute_tns.rpt
@@ -0,0 +1 @@
+tns 0.00
diff --git a/openlane/user_proj_example/results/reports/routing/fastroute_wns.rpt b/openlane/user_proj_example/results/reports/routing/fastroute_wns.rpt
new file mode 100644
index 0000000..3196164
--- /dev/null
+++ b/openlane/user_proj_example/results/reports/routing/fastroute_wns.rpt
@@ -0,0 +1 @@
+wns 0.00
diff --git a/openlane/user_proj_example/results/reports/routing/tritonRoute.drc b/openlane/user_proj_example/results/reports/routing/tritonRoute.drc
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/openlane/user_proj_example/results/reports/routing/tritonRoute.drc
diff --git a/openlane/user_proj_example/results/reports/runtime.txt b/openlane/user_proj_example/results/reports/runtime.txt
new file mode 100644
index 0000000..52b4ad3
--- /dev/null
+++ b/openlane/user_proj_example/results/reports/runtime.txt
@@ -0,0 +1 @@
+Routing completed for user_proj_example/16-12_10-43 in 2h52m33s
diff --git a/openlane/user_proj_example/results/reports/synthesis/opensta.min_max.rpt b/openlane/user_proj_example/results/reports/synthesis/opensta.min_max.rpt
new file mode 100644
index 0000000..bf8a59c
--- /dev/null
+++ b/openlane/user_proj_example/results/reports/synthesis/opensta.min_max.rpt
@@ -0,0 +1,158 @@
+Startpoint: _345957_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _347384_ (removal check against rising-edge clock wb_clk_i)
+Path Group: **async_default**
+Path Type: min
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (ideal)
+ 0.00 0.00 ^ _345957_/CLK (sky130_fd_sc_hd__dfstp_4)
+ 0.28 0.28 v _345957_/Q (sky130_fd_sc_hd__dfstp_4)
+ 0.10 0.37 v _160465_/X (sky130_fd_sc_hd__buf_2)
+ 0.09 0.47 v _160466_/X (sky130_fd_sc_hd__buf_2)
+ 0.03 0.50 ^ _162288_/Y (sky130_fd_sc_hd__inv_2)
+ 0.08 0.58 ^ _162289_/X (sky130_fd_sc_hd__buf_2)
+ 0.08 0.66 ^ _162290_/X (sky130_fd_sc_hd__buf_2)
+ 0.08 0.74 ^ _162291_/X (sky130_fd_sc_hd__buf_2)
+ 0.12 0.85 ^ _162292_/X (sky130_fd_sc_hd__buf_2)
+ 0.00 0.85 ^ _347384_/RESET_B (sky130_fd_sc_hd__dfrtp_4)
+ 0.85 data arrival time
+
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (ideal)
+ 0.00 0.00 clock reconvergence pessimism
+ 0.00 ^ _347384_/CLK (sky130_fd_sc_hd__dfrtp_4)
+ 0.21 0.21 library removal time
+ 0.21 data required time
+---------------------------------------------------------
+ 0.21 data required time
+ -0.85 data arrival time
+---------------------------------------------------------
+ 0.64 slack (MET)
+
+
+Startpoint: _347129_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _321093_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (ideal)
+ 0.00 0.00 ^ _347129_/CLK (sky130_fd_sc_hd__dfxtp_4)
+ 0.21 0.21 ^ _347129_/Q (sky130_fd_sc_hd__dfxtp_4)
+ 0.00 0.21 ^ _321093_/D (sky130_fd_sc_hd__dfxtp_4)
+ 0.21 data arrival time
+
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (ideal)
+ 0.00 0.00 clock reconvergence pessimism
+ 0.00 ^ _321093_/CLK (sky130_fd_sc_hd__dfxtp_4)
+ -0.02 -0.02 library hold time
+ -0.02 data required time
+---------------------------------------------------------
+ -0.02 data required time
+ -0.21 data arrival time
+---------------------------------------------------------
+ 0.22 slack (MET)
+
+
+Startpoint: la_data_in[2] (input port clocked by wb_clk_i)
+Endpoint: _346784_ (recovery check against rising-edge clock wb_clk_i)
+Path Group: **async_default**
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (ideal)
+ 4.00 4.00 v input external delay
+ 0.01 4.01 v la_data_in[2] (in)
+ 0.43 4.44 v _163808_/X (sky130_fd_sc_hd__or2_4)
+ 0.27 4.71 v _163809_/X (sky130_fd_sc_hd__buf_2)
+ 0.27 4.98 v _163810_/X (sky130_fd_sc_hd__buf_2)
+ 0.08 5.06 ^ _163811_/Y (sky130_fd_sc_hd__inv_2)
+ 0.21 5.26 ^ _163812_/X (sky130_fd_sc_hd__buf_2)
+ 0.24 5.51 ^ _163813_/X (sky130_fd_sc_hd__buf_2)
+ 0.23 5.73 ^ _163814_/X (sky130_fd_sc_hd__buf_2)
+ 0.21 5.95 ^ _172984_/X (sky130_fd_sc_hd__buf_2)
+ 0.21 6.16 ^ _172985_/X (sky130_fd_sc_hd__buf_2)
+ 0.18 6.34 ^ _172986_/X (sky130_fd_sc_hd__buf_2)
+ 0.00 6.34 ^ _346784_/SET_B (sky130_fd_sc_hd__dfstp_4)
+ 6.34 data arrival time
+
+ 20.00 20.00 clock wb_clk_i (rise edge)
+ 0.00 20.00 clock network delay (ideal)
+ 0.00 20.00 clock reconvergence pessimism
+ 20.00 ^ _346784_/CLK (sky130_fd_sc_hd__dfstp_4)
+ 0.25 20.25 library recovery time
+ 20.25 data required time
+---------------------------------------------------------
+ 20.25 data required time
+ -6.34 data arrival time
+---------------------------------------------------------
+ 13.91 slack (MET)
+
+
+Startpoint: la_data_in[3] (input port clocked by wb_clk_i)
+Endpoint: _345272_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (ideal)
+ 4.00 4.00 v input external delay
+ 0.01 4.01 v la_data_in[3] (in)
+ 0.45 4.46 v _160260_/X (sky130_fd_sc_hd__or2_4)
+ 0.93 5.39 v _160332_/X (sky130_fd_sc_hd__or4_4)
+ 0.28 5.66 v _160333_/X (sky130_fd_sc_hd__buf_2)
+ 0.75 6.42 v _160344_/X (sky130_fd_sc_hd__or3_4)
+ 0.46 6.87 v _160347_/X (sky130_fd_sc_hd__o22a_4)
+ 0.49 7.36 v _160403_/X (sky130_fd_sc_hd__or2_4)
+ 0.12 7.48 ^ _187177_/Y (sky130_fd_sc_hd__inv_2)
+ 0.33 7.81 ^ _187179_/X (sky130_fd_sc_hd__and2_4)
+ 0.34 8.14 ^ _187181_/X (sky130_fd_sc_hd__and2_4)
+ 0.34 8.48 ^ _187183_/X (sky130_fd_sc_hd__and2_4)
+ 0.35 8.83 ^ _187185_/X (sky130_fd_sc_hd__and2_4)
+ 0.47 9.30 ^ _187186_/X (sky130_fd_sc_hd__and3_4)
+ 0.32 9.62 ^ _187188_/X (sky130_fd_sc_hd__and2_4)
+ 0.29 9.91 ^ _187190_/X (sky130_fd_sc_hd__and2_4)
+ 0.08 9.99 v _187191_/Y (sky130_fd_sc_hd__inv_2)
+ 0.83 10.81 v _187192_/X (sky130_fd_sc_hd__or4_4)
+ 0.16 10.97 ^ _187193_/Y (sky130_fd_sc_hd__inv_2)
+ 0.48 11.46 ^ _187194_/X (sky130_fd_sc_hd__and3_4)
+ 0.49 11.95 ^ _187195_/X (sky130_fd_sc_hd__and3_4)
+ 0.48 12.43 ^ _187196_/X (sky130_fd_sc_hd__and3_4)
+ 0.35 12.78 ^ _187198_/X (sky130_fd_sc_hd__and2_4)
+ 0.34 13.11 ^ _187200_/X (sky130_fd_sc_hd__and2_4)
+ 0.34 13.45 ^ _187202_/X (sky130_fd_sc_hd__and2_4)
+ 0.35 13.79 ^ _187204_/X (sky130_fd_sc_hd__and2_4)
+ 0.47 14.27 ^ _187205_/X (sky130_fd_sc_hd__and3_4)
+ 0.35 14.61 ^ _187207_/X (sky130_fd_sc_hd__and2_4)
+ 0.34 14.95 ^ _187210_/X (sky130_fd_sc_hd__and2_4)
+ 0.34 15.29 ^ _187212_/X (sky130_fd_sc_hd__and2_4)
+ 0.34 15.62 ^ _187215_/X (sky130_fd_sc_hd__and2_4)
+ 0.12 15.74 v _187217_/Y (sky130_fd_sc_hd__nand2_4)
+ 0.41 16.15 v _187219_/X (sky130_fd_sc_hd__a2bb2o_4)
+ 0.29 16.43 ^ _187222_/Y (sky130_fd_sc_hd__a22oi_4)
+ 0.42 16.85 v _187223_/X (sky130_fd_sc_hd__a2bb2o_4)
+ 0.00 16.85 v _345272_/D (sky130_fd_sc_hd__dfxtp_4)
+ 16.85 data arrival time
+
+ 20.00 20.00 clock wb_clk_i (rise edge)
+ 0.00 20.00 clock network delay (ideal)
+ 0.00 20.00 clock reconvergence pessimism
+ 20.00 ^ _345272_/CLK (sky130_fd_sc_hd__dfxtp_4)
+ -0.28 19.72 library setup time
+ 19.72 data required time
+---------------------------------------------------------
+ 19.72 data required time
+ -16.85 data arrival time
+---------------------------------------------------------
+ 2.87 slack (MET)
+
+
diff --git a/openlane/user_proj_example/results/reports/synthesis/opensta.rpt b/openlane/user_proj_example/results/reports/synthesis/opensta.rpt
new file mode 100644
index 0000000..804fb12
--- /dev/null
+++ b/openlane/user_proj_example/results/reports/synthesis/opensta.rpt
@@ -0,0 +1 @@
+No paths found.
diff --git a/openlane/user_proj_example/results/reports/synthesis/opensta.timing.rpt b/openlane/user_proj_example/results/reports/synthesis/opensta.timing.rpt
new file mode 100644
index 0000000..804fb12
--- /dev/null
+++ b/openlane/user_proj_example/results/reports/synthesis/opensta.timing.rpt
@@ -0,0 +1 @@
+No paths found.
diff --git a/openlane/user_proj_example/results/reports/synthesis/opensta_post_openphysyn.min_max.rpt b/openlane/user_proj_example/results/reports/synthesis/opensta_post_openphysyn.min_max.rpt
new file mode 100644
index 0000000..3bc2e82
--- /dev/null
+++ b/openlane/user_proj_example/results/reports/synthesis/opensta_post_openphysyn.min_max.rpt
@@ -0,0 +1,158 @@
+Startpoint: _345957_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _347384_ (removal check against rising-edge clock wb_clk_i)
+Path Group: **async_default**
+Path Type: min
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (ideal)
+ 0.00 0.00 ^ _345957_/CLK (sky130_fd_sc_hd__dfstp_4)
+ 0.28 0.28 v _345957_/Q (sky130_fd_sc_hd__dfstp_4)
+ 0.10 0.38 v _160465_/X (sky130_fd_sc_hd__buf_4)
+ 0.09 0.47 v _160466_/X (sky130_fd_sc_hd__buf_2)
+ 0.03 0.50 ^ _162288_/Y (sky130_fd_sc_hd__inv_2)
+ 0.08 0.58 ^ _162289_/X (sky130_fd_sc_hd__buf_2)
+ 0.08 0.66 ^ _162290_/X (sky130_fd_sc_hd__buf_2)
+ 0.08 0.74 ^ _162291_/X (sky130_fd_sc_hd__buf_2)
+ 0.12 0.86 ^ _162292_/X (sky130_fd_sc_hd__buf_2)
+ 0.00 0.86 ^ _347384_/RESET_B (sky130_fd_sc_hd__dfrtp_4)
+ 0.86 data arrival time
+
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (ideal)
+ 0.00 0.00 clock reconvergence pessimism
+ 0.00 ^ _347384_/CLK (sky130_fd_sc_hd__dfrtp_4)
+ 0.21 0.21 library removal time
+ 0.21 data required time
+---------------------------------------------------------
+ 0.21 data required time
+ -0.86 data arrival time
+---------------------------------------------------------
+ 0.65 slack (MET)
+
+
+Startpoint: _347129_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _321093_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (ideal)
+ 0.00 0.00 ^ _347129_/CLK (sky130_fd_sc_hd__dfxtp_4)
+ 0.21 0.21 ^ _347129_/Q (sky130_fd_sc_hd__dfxtp_4)
+ 0.00 0.21 ^ _321093_/D (sky130_fd_sc_hd__dfxtp_4)
+ 0.21 data arrival time
+
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (ideal)
+ 0.00 0.00 clock reconvergence pessimism
+ 0.00 ^ _321093_/CLK (sky130_fd_sc_hd__dfxtp_4)
+ -0.02 -0.02 library hold time
+ -0.02 data required time
+---------------------------------------------------------
+ -0.02 data required time
+ -0.21 data arrival time
+---------------------------------------------------------
+ 0.22 slack (MET)
+
+
+Startpoint: la_data_in[2] (input port clocked by wb_clk_i)
+Endpoint: _346784_ (recovery check against rising-edge clock wb_clk_i)
+Path Group: **async_default**
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (ideal)
+ 4.00 4.00 v input external delay
+ 0.01 4.01 v la_data_in[2] (in)
+ 0.43 4.44 v _163808_/X (sky130_fd_sc_hd__or2_4)
+ 0.27 4.71 v _163809_/X (sky130_fd_sc_hd__buf_2)
+ 0.27 4.98 v _163810_/X (sky130_fd_sc_hd__buf_2)
+ 0.08 5.06 ^ _163811_/Y (sky130_fd_sc_hd__inv_2)
+ 0.21 5.26 ^ _163812_/X (sky130_fd_sc_hd__buf_2)
+ 0.24 5.51 ^ _163813_/X (sky130_fd_sc_hd__buf_2)
+ 0.23 5.73 ^ _163814_/X (sky130_fd_sc_hd__buf_2)
+ 0.21 5.95 ^ _172984_/X (sky130_fd_sc_hd__buf_2)
+ 0.21 6.16 ^ _172985_/X (sky130_fd_sc_hd__buf_2)
+ 0.18 6.34 ^ _172986_/X (sky130_fd_sc_hd__buf_2)
+ 0.00 6.34 ^ _346784_/SET_B (sky130_fd_sc_hd__dfstp_4)
+ 6.34 data arrival time
+
+ 20.00 20.00 clock wb_clk_i (rise edge)
+ 0.00 20.00 clock network delay (ideal)
+ 0.00 20.00 clock reconvergence pessimism
+ 20.00 ^ _346784_/CLK (sky130_fd_sc_hd__dfstp_4)
+ 0.25 20.25 library recovery time
+ 20.25 data required time
+---------------------------------------------------------
+ 20.25 data required time
+ -6.34 data arrival time
+---------------------------------------------------------
+ 13.91 slack (MET)
+
+
+Startpoint: la_data_in[3] (input port clocked by wb_clk_i)
+Endpoint: _345272_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (ideal)
+ 4.00 4.00 v input external delay
+ 0.01 4.01 v la_data_in[3] (in)
+ 0.45 4.46 v _160260_/X (sky130_fd_sc_hd__or2_4)
+ 0.93 5.39 v _160332_/X (sky130_fd_sc_hd__or4_4)
+ 0.28 5.66 v _160333_/X (sky130_fd_sc_hd__buf_2)
+ 0.75 6.42 v _160344_/X (sky130_fd_sc_hd__or3_4)
+ 0.46 6.87 v _160347_/X (sky130_fd_sc_hd__o22a_4)
+ 0.49 7.36 v _160403_/X (sky130_fd_sc_hd__or2_4)
+ 0.12 7.48 ^ _187177_/Y (sky130_fd_sc_hd__inv_2)
+ 0.33 7.81 ^ _187179_/X (sky130_fd_sc_hd__and2_4)
+ 0.34 8.14 ^ _187181_/X (sky130_fd_sc_hd__and2_4)
+ 0.34 8.48 ^ _187183_/X (sky130_fd_sc_hd__and2_4)
+ 0.35 8.83 ^ _187185_/X (sky130_fd_sc_hd__and2_4)
+ 0.47 9.30 ^ _187186_/X (sky130_fd_sc_hd__and3_4)
+ 0.32 9.62 ^ _187188_/X (sky130_fd_sc_hd__and2_4)
+ 0.29 9.91 ^ _187190_/X (sky130_fd_sc_hd__and2_4)
+ 0.08 9.99 v _187191_/Y (sky130_fd_sc_hd__inv_2)
+ 0.83 10.81 v _187192_/X (sky130_fd_sc_hd__or4_4)
+ 0.16 10.97 ^ _187193_/Y (sky130_fd_sc_hd__inv_2)
+ 0.48 11.46 ^ _187194_/X (sky130_fd_sc_hd__and3_4)
+ 0.49 11.95 ^ _187195_/X (sky130_fd_sc_hd__and3_4)
+ 0.48 12.43 ^ _187196_/X (sky130_fd_sc_hd__and3_4)
+ 0.35 12.78 ^ _187198_/X (sky130_fd_sc_hd__and2_4)
+ 0.34 13.11 ^ _187200_/X (sky130_fd_sc_hd__and2_4)
+ 0.34 13.45 ^ _187202_/X (sky130_fd_sc_hd__and2_4)
+ 0.35 13.79 ^ _187204_/X (sky130_fd_sc_hd__and2_4)
+ 0.47 14.27 ^ _187205_/X (sky130_fd_sc_hd__and3_4)
+ 0.35 14.61 ^ _187207_/X (sky130_fd_sc_hd__and2_4)
+ 0.34 14.95 ^ _187210_/X (sky130_fd_sc_hd__and2_4)
+ 0.34 15.29 ^ _187212_/X (sky130_fd_sc_hd__and2_4)
+ 0.34 15.62 ^ _187215_/X (sky130_fd_sc_hd__and2_4)
+ 0.12 15.74 v _187217_/Y (sky130_fd_sc_hd__nand2_4)
+ 0.41 16.15 v _187219_/X (sky130_fd_sc_hd__a2bb2o_4)
+ 0.29 16.43 ^ _187222_/Y (sky130_fd_sc_hd__a22oi_4)
+ 0.42 16.85 v _187223_/X (sky130_fd_sc_hd__a2bb2o_4)
+ 0.00 16.85 v _345272_/D (sky130_fd_sc_hd__dfxtp_4)
+ 16.85 data arrival time
+
+ 20.00 20.00 clock wb_clk_i (rise edge)
+ 0.00 20.00 clock network delay (ideal)
+ 0.00 20.00 clock reconvergence pessimism
+ 20.00 ^ _345272_/CLK (sky130_fd_sc_hd__dfxtp_4)
+ -0.28 19.72 library setup time
+ 19.72 data required time
+---------------------------------------------------------
+ 19.72 data required time
+ -16.85 data arrival time
+---------------------------------------------------------
+ 2.87 slack (MET)
+
+
diff --git a/openlane/user_proj_example/results/reports/synthesis/opensta_post_openphysyn.rpt b/openlane/user_proj_example/results/reports/synthesis/opensta_post_openphysyn.rpt
new file mode 100644
index 0000000..804fb12
--- /dev/null
+++ b/openlane/user_proj_example/results/reports/synthesis/opensta_post_openphysyn.rpt
@@ -0,0 +1 @@
+No paths found.
diff --git a/openlane/user_proj_example/results/reports/synthesis/opensta_post_openphysyn.timing.rpt b/openlane/user_proj_example/results/reports/synthesis/opensta_post_openphysyn.timing.rpt
new file mode 100644
index 0000000..804fb12
--- /dev/null
+++ b/openlane/user_proj_example/results/reports/synthesis/opensta_post_openphysyn.timing.rpt
@@ -0,0 +1 @@
+No paths found.
diff --git a/openlane/user_proj_example/results/reports/synthesis/opensta_post_openphysyn_tns.rpt b/openlane/user_proj_example/results/reports/synthesis/opensta_post_openphysyn_tns.rpt
new file mode 100644
index 0000000..53df237
--- /dev/null
+++ b/openlane/user_proj_example/results/reports/synthesis/opensta_post_openphysyn_tns.rpt
@@ -0,0 +1 @@
+tns 0.00
diff --git a/openlane/user_proj_example/results/reports/synthesis/opensta_post_openphysyn_wns.rpt b/openlane/user_proj_example/results/reports/synthesis/opensta_post_openphysyn_wns.rpt
new file mode 100644
index 0000000..3196164
--- /dev/null
+++ b/openlane/user_proj_example/results/reports/synthesis/opensta_post_openphysyn_wns.rpt
@@ -0,0 +1 @@
+wns 0.00
diff --git a/openlane/user_proj_example/results/reports/synthesis/opensta_spef.min_max.rpt b/openlane/user_proj_example/results/reports/synthesis/opensta_spef.min_max.rpt
new file mode 100644
index 0000000..a5034aa
--- /dev/null
+++ b/openlane/user_proj_example/results/reports/synthesis/opensta_spef.min_max.rpt
@@ -0,0 +1,158 @@
+Startpoint: _345957_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _347241_ (removal check against rising-edge clock wb_clk_i)
+Path Group: **async_default**
+Path Type: min
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (ideal)
+ 0.00 0.00 ^ _345957_/CLK (sky130_fd_sc_hd__dfstp_4)
+ 0.34 0.34 v _345957_/Q (sky130_fd_sc_hd__dfstp_4)
+ 0.19 0.53 v _160465_/X (sky130_fd_sc_hd__buf_4)
+ 0.14 0.66 v _160466_/X (sky130_fd_sc_hd__buf_2)
+ 0.03 0.69 ^ _162288_/Y (sky130_fd_sc_hd__inv_2)
+ 0.08 0.78 ^ _162289_/X (sky130_fd_sc_hd__buf_2)
+ 0.06 0.83 ^ _162290_/X (sky130_fd_sc_hd__buf_2)
+ 0.05 0.88 ^ _163596_/X (sky130_fd_sc_hd__buf_2)
+ 0.05 0.92 ^ _163647_/X (sky130_fd_sc_hd__buf_2)
+ 0.06 0.98 ^ _163648_/X (sky130_fd_sc_hd__buf_2)
+ 0.00 0.98 ^ _347241_/RESET_B (sky130_fd_sc_hd__dfrtp_4)
+ 0.98 data arrival time
+
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (ideal)
+ 0.00 0.00 clock reconvergence pessimism
+ 0.00 ^ _347241_/CLK (sky130_fd_sc_hd__dfrtp_4)
+ 0.19 0.19 library removal time
+ 0.19 data required time
+---------------------------------------------------------
+ 0.19 data required time
+ -0.98 data arrival time
+---------------------------------------------------------
+ 0.79 slack (MET)
+
+
+Startpoint: _347126_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _321092_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (ideal)
+ 0.00 0.00 ^ _347126_/CLK (sky130_fd_sc_hd__dfxtp_4)
+ 0.20 0.20 ^ _347126_/Q (sky130_fd_sc_hd__dfxtp_4)
+ 0.00 0.20 ^ _321092_/D (sky130_fd_sc_hd__dfxtp_4)
+ 0.20 data arrival time
+
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (ideal)
+ 0.00 0.00 clock reconvergence pessimism
+ 0.00 ^ _321092_/CLK (sky130_fd_sc_hd__dfxtp_4)
+ -0.02 -0.02 library hold time
+ -0.02 data required time
+---------------------------------------------------------
+ -0.02 data required time
+ -0.20 data arrival time
+---------------------------------------------------------
+ 0.22 slack (MET)
+
+
+Startpoint: la_data_in[1] (input port clocked by wb_clk_i)
+Endpoint: _347074_ (recovery check against rising-edge clock wb_clk_i)
+Path Group: **async_default**
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (ideal)
+ 4.00 4.00 v input external delay
+ 0.01 4.01 v la_data_in[1] (in)
+ 0.48 4.50 v _167854_/X (sky130_fd_sc_hd__or2_4)
+ 0.34 4.84 v _167855_/X (sky130_fd_sc_hd__buf_2)
+ 0.18 5.02 ^ _167856_/Y (sky130_fd_sc_hd__inv_2)
+ 0.33 5.35 ^ _167857_/X (sky130_fd_sc_hd__buf_2)
+ 0.42 5.76 ^ _167858_/X (sky130_fd_sc_hd__buf_2)
+ 0.39 6.15 ^ _167859_/X (sky130_fd_sc_hd__buf_2)
+ 0.54 6.69 ^ _167860_/X (sky130_fd_sc_hd__buf_2)
+ 0.62 7.32 ^ _167861_/X (sky130_fd_sc_hd__buf_2)
+ 0.00 7.32 ^ _347074_/RESET_B (sky130_fd_sc_hd__dfrtp_4)
+ 7.32 data arrival time
+
+ 20.00 20.00 clock wb_clk_i (rise edge)
+ 0.00 20.00 clock network delay (ideal)
+ 0.00 20.00 clock reconvergence pessimism
+ 20.00 ^ _347074_/CLK (sky130_fd_sc_hd__dfrtp_4)
+ 0.25 20.25 library recovery time
+ 20.25 data required time
+---------------------------------------------------------
+ 20.25 data required time
+ -7.32 data arrival time
+---------------------------------------------------------
+ 12.93 slack (MET)
+
+
+Startpoint: la_data_in[1] (input port clocked by wb_clk_i)
+Endpoint: _322520_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+
+ Delay Time Description
+---------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (ideal)
+ 4.00 4.00 v input external delay
+ 0.01 4.01 v la_data_in[1] (in)
+ 0.48 4.50 v _167854_/X (sky130_fd_sc_hd__or2_4)
+ 0.95 5.45 v _167938_/X (sky130_fd_sc_hd__or4_4)
+ 0.30 5.75 v _167939_/X (sky130_fd_sc_hd__buf_2)
+ 0.69 6.44 v _167949_/X (sky130_fd_sc_hd__or3_4)
+ 0.36 6.80 v _167950_/X (sky130_fd_sc_hd__buf_2)
+ 0.41 7.21 ^ _167951_/X (sky130_fd_sc_hd__a2bb2o_4)
+ 0.10 7.31 v _167965_/Y (sky130_fd_sc_hd__inv_2)
+ 0.51 7.81 ^ _167970_/Y (sky130_fd_sc_hd__nor2_4)
+ 0.55 8.37 ^ _304448_/X (sky130_fd_sc_hd__and2_4)
+ 0.35 8.72 ^ _304450_/X (sky130_fd_sc_hd__and2_4)
+ 0.34 9.06 ^ _304452_/X (sky130_fd_sc_hd__and2_4)
+ 0.29 9.35 ^ _304454_/X (sky130_fd_sc_hd__and2_4)
+ 0.46 9.81 ^ _304455_/X (sky130_fd_sc_hd__and3_4)
+ 0.30 10.11 ^ _304457_/X (sky130_fd_sc_hd__and2_4)
+ 0.29 10.39 ^ _304459_/X (sky130_fd_sc_hd__and2_4)
+ 0.09 10.48 v _304460_/Y (sky130_fd_sc_hd__inv_2)
+ 0.84 11.31 v _304461_/X (sky130_fd_sc_hd__or4_4)
+ 0.14 11.45 ^ _304462_/Y (sky130_fd_sc_hd__inv_2)
+ 0.40 11.86 ^ _304463_/X (sky130_fd_sc_hd__and3_4)
+ 0.48 12.34 ^ _304464_/X (sky130_fd_sc_hd__and3_4)
+ 0.49 12.83 ^ _304465_/X (sky130_fd_sc_hd__and3_4)
+ 0.36 13.19 ^ _304467_/X (sky130_fd_sc_hd__and2_4)
+ 0.35 13.54 ^ _304469_/X (sky130_fd_sc_hd__and2_4)
+ 0.35 13.89 ^ _304471_/X (sky130_fd_sc_hd__and2_4)
+ 0.29 14.18 ^ _304473_/X (sky130_fd_sc_hd__and2_4)
+ 0.47 14.65 ^ _304474_/X (sky130_fd_sc_hd__and3_4)
+ 0.36 15.01 ^ _304476_/X (sky130_fd_sc_hd__and2_4)
+ 0.34 15.36 ^ _304479_/X (sky130_fd_sc_hd__and2_4)
+ 0.34 15.70 ^ _304481_/X (sky130_fd_sc_hd__and2_4)
+ 0.31 16.01 ^ _304484_/X (sky130_fd_sc_hd__and2_4)
+ 0.06 16.07 v _304486_/Y (sky130_fd_sc_hd__nand2_4)
+ 0.39 16.46 v _304488_/X (sky130_fd_sc_hd__a2bb2o_4)
+ 0.48 16.94 ^ _304491_/Y (sky130_fd_sc_hd__a22oi_4)
+ 0.48 17.42 v _304492_/X (sky130_fd_sc_hd__a2bb2o_4)
+ 0.00 17.42 v _322520_/D (sky130_fd_sc_hd__dfxtp_4)
+ 17.42 data arrival time
+
+ 20.00 20.00 clock wb_clk_i (rise edge)
+ 0.00 20.00 clock network delay (ideal)
+ 0.00 20.00 clock reconvergence pessimism
+ 20.00 ^ _322520_/CLK (sky130_fd_sc_hd__dfxtp_4)
+ -0.28 19.72 library setup time
+ 19.72 data required time
+---------------------------------------------------------
+ 19.72 data required time
+ -17.42 data arrival time
+---------------------------------------------------------
+ 2.30 slack (MET)
+
+
diff --git a/openlane/user_proj_example/results/reports/synthesis/opensta_spef.rpt b/openlane/user_proj_example/results/reports/synthesis/opensta_spef.rpt
new file mode 100644
index 0000000..804fb12
--- /dev/null
+++ b/openlane/user_proj_example/results/reports/synthesis/opensta_spef.rpt
@@ -0,0 +1 @@
+No paths found.
diff --git a/openlane/user_proj_example/results/reports/synthesis/opensta_spef.timing.rpt b/openlane/user_proj_example/results/reports/synthesis/opensta_spef.timing.rpt
new file mode 100644
index 0000000..804fb12
--- /dev/null
+++ b/openlane/user_proj_example/results/reports/synthesis/opensta_spef.timing.rpt
@@ -0,0 +1 @@
+No paths found.
diff --git a/openlane/user_proj_example/results/reports/synthesis/opensta_spef_tns.rpt b/openlane/user_proj_example/results/reports/synthesis/opensta_spef_tns.rpt
new file mode 100644
index 0000000..53df237
--- /dev/null
+++ b/openlane/user_proj_example/results/reports/synthesis/opensta_spef_tns.rpt
@@ -0,0 +1 @@
+tns 0.00
diff --git a/openlane/user_proj_example/results/reports/synthesis/opensta_spef_wns.rpt b/openlane/user_proj_example/results/reports/synthesis/opensta_spef_wns.rpt
new file mode 100644
index 0000000..3196164
--- /dev/null
+++ b/openlane/user_proj_example/results/reports/synthesis/opensta_spef_wns.rpt
@@ -0,0 +1 @@
+wns 0.00
diff --git a/openlane/user_proj_example/results/reports/synthesis/opensta_tns.rpt b/openlane/user_proj_example/results/reports/synthesis/opensta_tns.rpt
new file mode 100644
index 0000000..53df237
--- /dev/null
+++ b/openlane/user_proj_example/results/reports/synthesis/opensta_tns.rpt
@@ -0,0 +1 @@
+tns 0.00
diff --git a/openlane/user_proj_example/results/reports/synthesis/opensta_wns.rpt b/openlane/user_proj_example/results/reports/synthesis/opensta_wns.rpt
new file mode 100644
index 0000000..3196164
--- /dev/null
+++ b/openlane/user_proj_example/results/reports/synthesis/opensta_wns.rpt
@@ -0,0 +1 @@
+wns 0.00
diff --git a/openlane/user_proj_example/results/reports/synthesis/yosys_2.chk.rpt b/openlane/user_proj_example/results/reports/synthesis/yosys_2.chk.rpt
new file mode 100644
index 0000000..169cedf
--- /dev/null
+++ b/openlane/user_proj_example/results/reports/synthesis/yosys_2.chk.rpt
@@ -0,0 +1,241 @@
+
+38. Executing CHECK pass (checking for obvious problems).
+checking module user_proj_example..
+Warning: Wire user_proj_example.\wbs_dat_o [31] is used but has no driver.
+Warning: Wire user_proj_example.\wbs_dat_o [30] is used but has no driver.
+Warning: Wire user_proj_example.\wbs_dat_o [29] is used but has no driver.
+Warning: Wire user_proj_example.\wbs_dat_o [28] is used but has no driver.
+Warning: Wire user_proj_example.\wbs_dat_o [27] is used but has no driver.
+Warning: Wire user_proj_example.\wbs_dat_o [26] is used but has no driver.
+Warning: Wire user_proj_example.\wbs_dat_o [25] is used but has no driver.
+Warning: Wire user_proj_example.\wbs_dat_o [24] is used but has no driver.
+Warning: Wire user_proj_example.\wbs_dat_o [23] is used but has no driver.
+Warning: Wire user_proj_example.\wbs_dat_o [22] is used but has no driver.
+Warning: Wire user_proj_example.\wbs_dat_o [21] is used but has no driver.
+Warning: Wire user_proj_example.\wbs_dat_o [20] is used but has no driver.
+Warning: Wire user_proj_example.\wbs_dat_o [19] is used but has no driver.
+Warning: Wire user_proj_example.\wbs_dat_o [18] is used but has no driver.
+Warning: Wire user_proj_example.\wbs_dat_o [17] is used but has no driver.
+Warning: Wire user_proj_example.\wbs_dat_o [16] is used but has no driver.
+Warning: Wire user_proj_example.\wbs_dat_o [15] is used but has no driver.
+Warning: Wire user_proj_example.\wbs_dat_o [14] is used but has no driver.
+Warning: Wire user_proj_example.\wbs_dat_o [13] is used but has no driver.
+Warning: Wire user_proj_example.\wbs_dat_o [12] is used but has no driver.
+Warning: Wire user_proj_example.\wbs_dat_o [11] is used but has no driver.
+Warning: Wire user_proj_example.\wbs_dat_o [10] is used but has no driver.
+Warning: Wire user_proj_example.\wbs_dat_o [9] is used but has no driver.
+Warning: Wire user_proj_example.\wbs_dat_o [8] is used but has no driver.
+Warning: Wire user_proj_example.\wbs_dat_o [7] is used but has no driver.
+Warning: Wire user_proj_example.\wbs_dat_o [6] is used but has no driver.
+Warning: Wire user_proj_example.\wbs_dat_o [5] is used but has no driver.
+Warning: Wire user_proj_example.\wbs_dat_o [4] is used but has no driver.
+Warning: Wire user_proj_example.\wbs_dat_o [3] is used but has no driver.
+Warning: Wire user_proj_example.\wbs_dat_o [2] is used but has no driver.
+Warning: Wire user_proj_example.\wbs_dat_o [1] is used but has no driver.
+Warning: Wire user_proj_example.\wbs_dat_o [0] is used but has no driver.
+Warning: Wire user_proj_example.\wbs_ack_o is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [127] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [126] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [125] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [124] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [123] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [122] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [121] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [120] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [119] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [118] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [117] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [116] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [115] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [114] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [113] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [112] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [111] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [110] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [109] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [108] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [107] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [106] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [105] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [104] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [103] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [102] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [101] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [100] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [99] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [98] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [97] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [96] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [95] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [94] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [93] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [92] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [91] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [90] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [89] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [88] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [87] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [86] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [85] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [84] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [83] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [82] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [81] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [80] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [79] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [78] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [77] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [76] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [75] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [74] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [73] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [72] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [71] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [70] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [69] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [68] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [67] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [66] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [65] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [64] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [63] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [62] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [61] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [60] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [59] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [58] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [57] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [56] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [55] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [54] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [53] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [52] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [51] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [50] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [49] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [48] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [47] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [46] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [45] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [44] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [43] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [42] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [41] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [40] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [39] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [38] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [37] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [36] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [35] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [34] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [33] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [32] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [31] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [30] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [29] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [28] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [27] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [26] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [25] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [24] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [23] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [22] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [21] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [20] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [19] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [18] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [17] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [16] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [15] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [14] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [13] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [12] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [11] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [10] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [9] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [8] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [7] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [6] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [5] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [4] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [3] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [2] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [1] is used but has no driver.
+Warning: Wire user_proj_example.\la_data_out [0] is used but has no driver.
+Warning: Wire user_proj_example.\io_out [37] is used but has no driver.
+Warning: Wire user_proj_example.\io_out [36] is used but has no driver.
+Warning: Wire user_proj_example.\io_out [35] is used but has no driver.
+Warning: Wire user_proj_example.\io_out [34] is used but has no driver.
+Warning: Wire user_proj_example.\io_out [33] is used but has no driver.
+Warning: Wire user_proj_example.\io_out [32] is used but has no driver.
+Warning: Wire user_proj_example.\io_out [31] is used but has no driver.
+Warning: Wire user_proj_example.\io_out [30] is used but has no driver.
+Warning: Wire user_proj_example.\io_out [29] is used but has no driver.
+Warning: Wire user_proj_example.\io_out [28] is used but has no driver.
+Warning: Wire user_proj_example.\io_out [27] is used but has no driver.
+Warning: Wire user_proj_example.\io_out [26] is used but has no driver.
+Warning: Wire user_proj_example.\io_out [25] is used but has no driver.
+Warning: Wire user_proj_example.\io_out [24] is used but has no driver.
+Warning: Wire user_proj_example.\io_out [23] is used but has no driver.
+Warning: Wire user_proj_example.\io_out [22] is used but has no driver.
+Warning: Wire user_proj_example.\io_out [21] is used but has no driver.
+Warning: Wire user_proj_example.\io_out [20] is used but has no driver.
+Warning: Wire user_proj_example.\io_out [19] is used but has no driver.
+Warning: Wire user_proj_example.\io_out [18] is used but has no driver.
+Warning: Wire user_proj_example.\io_out [17] is used but has no driver.
+Warning: Wire user_proj_example.\io_out [16] is used but has no driver.
+Warning: Wire user_proj_example.\io_out [15] is used but has no driver.
+Warning: Wire user_proj_example.\io_out [14] is used but has no driver.
+Warning: Wire user_proj_example.\io_out [13] is used but has no driver.
+Warning: Wire user_proj_example.\io_out [12] is used but has no driver.
+Warning: Wire user_proj_example.\io_out [11] is used but has no driver.
+Warning: Wire user_proj_example.\io_out [10] is used but has no driver.
+Warning: Wire user_proj_example.\io_out [9] is used but has no driver.
+Warning: Wire user_proj_example.\io_out [8] is used but has no driver.
+Warning: Wire user_proj_example.\io_out [7] is used but has no driver.
+Warning: Wire user_proj_example.\io_out [6] is used but has no driver.
+Warning: Wire user_proj_example.\io_out [5] is used but has no driver.
+Warning: Wire user_proj_example.\io_out [4] is used but has no driver.
+Warning: Wire user_proj_example.\io_out [3] is used but has no driver.
+Warning: Wire user_proj_example.\io_out [2] is used but has no driver.
+Warning: Wire user_proj_example.\io_out [1] is used but has no driver.
+Warning: Wire user_proj_example.\io_out [0] is used but has no driver.
+Warning: Wire user_proj_example.\io_oeb [37] is used but has no driver.
+Warning: Wire user_proj_example.\io_oeb [36] is used but has no driver.
+Warning: Wire user_proj_example.\io_oeb [35] is used but has no driver.
+Warning: Wire user_proj_example.\io_oeb [34] is used but has no driver.
+Warning: Wire user_proj_example.\io_oeb [33] is used but has no driver.
+Warning: Wire user_proj_example.\io_oeb [32] is used but has no driver.
+Warning: Wire user_proj_example.\io_oeb [31] is used but has no driver.
+Warning: Wire user_proj_example.\io_oeb [30] is used but has no driver.
+Warning: Wire user_proj_example.\io_oeb [29] is used but has no driver.
+Warning: Wire user_proj_example.\io_oeb [28] is used but has no driver.
+Warning: Wire user_proj_example.\io_oeb [27] is used but has no driver.
+Warning: Wire user_proj_example.\io_oeb [26] is used but has no driver.
+Warning: Wire user_proj_example.\io_oeb [25] is used but has no driver.
+Warning: Wire user_proj_example.\io_oeb [24] is used but has no driver.
+Warning: Wire user_proj_example.\io_oeb [23] is used but has no driver.
+Warning: Wire user_proj_example.\io_oeb [22] is used but has no driver.
+Warning: Wire user_proj_example.\io_oeb [21] is used but has no driver.
+Warning: Wire user_proj_example.\io_oeb [20] is used but has no driver.
+Warning: Wire user_proj_example.\io_oeb [19] is used but has no driver.
+Warning: Wire user_proj_example.\io_oeb [18] is used but has no driver.
+Warning: Wire user_proj_example.\io_oeb [17] is used but has no driver.
+Warning: Wire user_proj_example.\io_oeb [16] is used but has no driver.
+Warning: Wire user_proj_example.\io_oeb [15] is used but has no driver.
+Warning: Wire user_proj_example.\io_oeb [14] is used but has no driver.
+Warning: Wire user_proj_example.\io_oeb [13] is used but has no driver.
+Warning: Wire user_proj_example.\io_oeb [12] is used but has no driver.
+Warning: Wire user_proj_example.\io_oeb [11] is used but has no driver.
+Warning: Wire user_proj_example.\io_oeb [10] is used but has no driver.
+Warning: Wire user_proj_example.\io_oeb [9] is used but has no driver.
+Warning: Wire user_proj_example.\io_oeb [8] is used but has no driver.
+Warning: Wire user_proj_example.\io_oeb [7] is used but has no driver.
+Warning: Wire user_proj_example.\io_oeb [6] is used but has no driver.
+Warning: Wire user_proj_example.\io_oeb [5] is used but has no driver.
+Warning: Wire user_proj_example.\io_oeb [4] is used but has no driver.
+Warning: Wire user_proj_example.\io_oeb [3] is used but has no driver.
+Warning: Wire user_proj_example.\io_oeb [2] is used but has no driver.
+Warning: Wire user_proj_example.\io_oeb [1] is used but has no driver.
+Warning: Wire user_proj_example.\io_oeb [0] is used but has no driver.
+found and reported 237 problems.
diff --git a/openlane/user_proj_example/results/reports/synthesis/yosys_2.stat.rpt b/openlane/user_proj_example/results/reports/synthesis/yosys_2.stat.rpt
new file mode 100644
index 0000000..9d72553
--- /dev/null
+++ b/openlane/user_proj_example/results/reports/synthesis/yosys_2.stat.rpt
@@ -0,0 +1,44 @@
+
+39. Printing statistics.
+
+=== user_proj_example ===
+
+ Number of wires: 187108
+ Number of wire bits: 187696
+ Number of public wires: 26865
+ Number of public wire bits: 27453
+ Number of memories: 0
+ Number of memory bits: 0
+ Number of processes: 0
+ Number of cells: 187329
+ sky130_fd_sc_hd__a2111o_4 35
+ sky130_fd_sc_hd__a211o_4 1593
+ sky130_fd_sc_hd__a21bo_4 68
+ sky130_fd_sc_hd__a21o_4 203
+ sky130_fd_sc_hd__a21oi_4 173
+ sky130_fd_sc_hd__a22oi_4 163
+ sky130_fd_sc_hd__a2bb2o_4 24546
+ sky130_fd_sc_hd__a32o_4 1198
+ sky130_fd_sc_hd__a41o_4 2
+ sky130_fd_sc_hd__and2_4 2003
+ sky130_fd_sc_hd__and3_4 18762
+ sky130_fd_sc_hd__and4_4 265
+ sky130_fd_sc_hd__buf_2 36084
+ sky130_fd_sc_hd__conb_1 77
+ sky130_fd_sc_hd__dfrtp_4 626
+ sky130_fd_sc_hd__dfstp_4 18
+ sky130_fd_sc_hd__dfxtp_4 26132
+ sky130_fd_sc_hd__inv_2 25679
+ sky130_fd_sc_hd__nand2_4 558
+ sky130_fd_sc_hd__nor2_4 3469
+ sky130_fd_sc_hd__o21a_4 1178
+ sky130_fd_sc_hd__o21ai_4 305
+ sky130_fd_sc_hd__o22a_4 2992
+ sky130_fd_sc_hd__o32a_4 231
+ sky130_fd_sc_hd__o41a_4 6
+ sky130_fd_sc_hd__or2_4 30981
+ sky130_fd_sc_hd__or3_4 8866
+ sky130_fd_sc_hd__or4_4 1116
+
+ Chip area for module '\user_proj_example': 2214343.731198
+
diff --git a/openlane/user_proj_example/results/results/lvs/user_proj_example.lvs.log b/openlane/user_proj_example/results/results/lvs/user_proj_example.lvs.log
new file mode 100644
index 0000000..181dccb
--- /dev/null
+++ b/openlane/user_proj_example/results/results/lvs/user_proj_example.lvs.log
@@ -0,0 +1,1787 @@
+
+Cell sky130_fd_sc_hd__or2_4 disconnected node: A
+Cell sky130_fd_sc_hd__or2_4 disconnected node: B
+Cell sky130_fd_sc_hd__or2_4 disconnected node: VGND
+Cell sky130_fd_sc_hd__or2_4 disconnected node: VNB
+Cell sky130_fd_sc_hd__or2_4 disconnected node: VPB
+Cell sky130_fd_sc_hd__or2_4 disconnected node: VPWR
+Cell sky130_fd_sc_hd__or2_4 disconnected node: X
+Warning: Equate pins: cell sky130_fd_sc_hd__or2_4 has no definition, treated as a black box.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__or2_4 |Circuit 2: sky130_fd_sc_hd__or2_4
+-------------------------------------------|-------------------------------------------
+A |A
+B |B
+VGND |VGND
+VNB |VNB
+VPB |VPB
+VPWR |VPWR
+X |X
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__or2_4 and sky130_fd_sc_hd__or2_4 are equivalent.
+
+Cell sky130_fd_sc_hd__dfxtp_4 disconnected node: CLK
+Cell sky130_fd_sc_hd__dfxtp_4 disconnected node: D
+Cell sky130_fd_sc_hd__dfxtp_4 disconnected node: VGND
+Cell sky130_fd_sc_hd__dfxtp_4 disconnected node: VNB
+Cell sky130_fd_sc_hd__dfxtp_4 disconnected node: VPB
+Cell sky130_fd_sc_hd__dfxtp_4 disconnected node: VPWR
+Cell sky130_fd_sc_hd__dfxtp_4 disconnected node: Q
+Warning: Equate pins: cell sky130_fd_sc_hd__dfxtp_4 has no definition, treated as a black box.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__dfxtp_4 |Circuit 2: sky130_fd_sc_hd__dfxtp_4
+-------------------------------------------|-------------------------------------------
+CLK |CLK
+D |D
+VGND |VGND
+VNB |VNB
+VPB |VPB
+VPWR |VPWR
+Q |Q
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__dfxtp_4 and sky130_fd_sc_hd__dfxtp_4 are equivalent.
+
+Cell sky130_fd_sc_hd__diode_2 disconnected node: DIODE
+Cell sky130_fd_sc_hd__diode_2 disconnected node: VGND
+Cell sky130_fd_sc_hd__diode_2 disconnected node: VNB
+Cell sky130_fd_sc_hd__diode_2 disconnected node: VPB
+Cell sky130_fd_sc_hd__diode_2 disconnected node: VPWR
+Warning: Equate pins: cell sky130_fd_sc_hd__diode_2 has no definition, treated as a black box.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__diode_2 |Circuit 2: sky130_fd_sc_hd__diode_2
+-------------------------------------------|-------------------------------------------
+DIODE |DIODE
+VGND |VGND
+VNB |VNB
+VPB |VPB
+VPWR |VPWR
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__diode_2 and sky130_fd_sc_hd__diode_2 are equivalent.
+
+Cell sky130_fd_sc_hd__buf_2 disconnected node: A
+Cell sky130_fd_sc_hd__buf_2 disconnected node: VGND
+Cell sky130_fd_sc_hd__buf_2 disconnected node: VNB
+Cell sky130_fd_sc_hd__buf_2 disconnected node: VPB
+Cell sky130_fd_sc_hd__buf_2 disconnected node: VPWR
+Cell sky130_fd_sc_hd__buf_2 disconnected node: X
+Warning: Equate pins: cell sky130_fd_sc_hd__buf_2 has no definition, treated as a black box.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__buf_2 |Circuit 2: sky130_fd_sc_hd__buf_2
+-------------------------------------------|-------------------------------------------
+A |A
+VGND |VGND
+VNB |VNB
+VPB |VPB
+VPWR |VPWR
+X |X
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__buf_2 and sky130_fd_sc_hd__buf_2 are equivalent.
+
+Cell sky130_fd_sc_hd__or3_4 disconnected node: A
+Cell sky130_fd_sc_hd__or3_4 disconnected node: B
+Cell sky130_fd_sc_hd__or3_4 disconnected node: C
+Cell sky130_fd_sc_hd__or3_4 disconnected node: VGND
+Cell sky130_fd_sc_hd__or3_4 disconnected node: VNB
+Cell sky130_fd_sc_hd__or3_4 disconnected node: VPB
+Cell sky130_fd_sc_hd__or3_4 disconnected node: VPWR
+Cell sky130_fd_sc_hd__or3_4 disconnected node: X
+Warning: Equate pins: cell sky130_fd_sc_hd__or3_4 has no definition, treated as a black box.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__or3_4 |Circuit 2: sky130_fd_sc_hd__or3_4
+-------------------------------------------|-------------------------------------------
+A |A
+B |B
+C |C
+VGND |VGND
+VNB |VNB
+VPB |VPB
+VPWR |VPWR
+X |X
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__or3_4 and sky130_fd_sc_hd__or3_4 are equivalent.
+
+Cell sky130_fd_sc_hd__tapvpwrvgnd_1 disconnected node: VGND
+Cell sky130_fd_sc_hd__tapvpwrvgnd_1 disconnected node: VPWR
+Warning: Equate pins: cell sky130_fd_sc_hd__tapvpwrvgnd_1 has no definition, treated as a black box.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__tapvpwrvgnd_1 |Circuit 2: sky130_fd_sc_hd__tapvpwrvgnd_1
+-------------------------------------------|-------------------------------------------
+VGND |VGND
+VPWR |VPWR
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__tapvpwrvgnd_1 and sky130_fd_sc_hd__tapvpwrvgnd_1 are equivalent.
+
+Cell sky130_fd_sc_hd__and2_4 disconnected node: A
+Cell sky130_fd_sc_hd__and2_4 disconnected node: B
+Cell sky130_fd_sc_hd__and2_4 disconnected node: VGND
+Cell sky130_fd_sc_hd__and2_4 disconnected node: VNB
+Cell sky130_fd_sc_hd__and2_4 disconnected node: VPB
+Cell sky130_fd_sc_hd__and2_4 disconnected node: VPWR
+Cell sky130_fd_sc_hd__and2_4 disconnected node: X
+Warning: Equate pins: cell sky130_fd_sc_hd__and2_4 has no definition, treated as a black box.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__and2_4 |Circuit 2: sky130_fd_sc_hd__and2_4
+-------------------------------------------|-------------------------------------------
+A |A
+B |B
+VGND |VGND
+VNB |VNB
+VPB |VPB
+VPWR |VPWR
+X |X
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__and2_4 and sky130_fd_sc_hd__and2_4 are equivalent.
+
+Cell sky130_fd_sc_hd__and3_4 disconnected node: A
+Cell sky130_fd_sc_hd__and3_4 disconnected node: B
+Cell sky130_fd_sc_hd__and3_4 disconnected node: C
+Cell sky130_fd_sc_hd__and3_4 disconnected node: VGND
+Cell sky130_fd_sc_hd__and3_4 disconnected node: VNB
+Cell sky130_fd_sc_hd__and3_4 disconnected node: VPB
+Cell sky130_fd_sc_hd__and3_4 disconnected node: VPWR
+Cell sky130_fd_sc_hd__and3_4 disconnected node: X
+Warning: Equate pins: cell sky130_fd_sc_hd__and3_4 has no definition, treated as a black box.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__and3_4 |Circuit 2: sky130_fd_sc_hd__and3_4
+-------------------------------------------|-------------------------------------------
+A |A
+B |B
+C |C
+VGND |VGND
+VNB |VNB
+VPB |VPB
+VPWR |VPWR
+X |X
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__and3_4 and sky130_fd_sc_hd__and3_4 are equivalent.
+
+Cell sky130_fd_sc_hd__inv_2 disconnected node: A
+Cell sky130_fd_sc_hd__inv_2 disconnected node: VGND
+Cell sky130_fd_sc_hd__inv_2 disconnected node: VNB
+Cell sky130_fd_sc_hd__inv_2 disconnected node: VPB
+Cell sky130_fd_sc_hd__inv_2 disconnected node: VPWR
+Cell sky130_fd_sc_hd__inv_2 disconnected node: Y
+Warning: Equate pins: cell sky130_fd_sc_hd__inv_2 has no definition, treated as a black box.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__inv_2 |Circuit 2: sky130_fd_sc_hd__inv_2
+-------------------------------------------|-------------------------------------------
+A |A
+VGND |VGND
+VNB |VNB
+VPB |VPB
+VPWR |VPWR
+Y |Y
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__inv_2 and sky130_fd_sc_hd__inv_2 are equivalent.
+
+Cell sky130_fd_sc_hd__a2bb2o_4 disconnected node: A1_N
+Cell sky130_fd_sc_hd__a2bb2o_4 disconnected node: A2_N
+Cell sky130_fd_sc_hd__a2bb2o_4 disconnected node: B1
+Cell sky130_fd_sc_hd__a2bb2o_4 disconnected node: B2
+Cell sky130_fd_sc_hd__a2bb2o_4 disconnected node: VGND
+Cell sky130_fd_sc_hd__a2bb2o_4 disconnected node: VNB
+Cell sky130_fd_sc_hd__a2bb2o_4 disconnected node: VPB
+Cell sky130_fd_sc_hd__a2bb2o_4 disconnected node: VPWR
+Cell sky130_fd_sc_hd__a2bb2o_4 disconnected node: X
+Warning: Equate pins: cell sky130_fd_sc_hd__a2bb2o_4 has no definition, treated as a black box.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__a2bb2o_4 |Circuit 2: sky130_fd_sc_hd__a2bb2o_4
+-------------------------------------------|-------------------------------------------
+A1_N |A1_N
+A2_N |A2_N
+B1 |B1
+B2 |B2
+VGND |VGND
+VNB |VNB
+VPB |VPB
+VPWR |VPWR
+X |X
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__a2bb2o_4 and sky130_fd_sc_hd__a2bb2o_4 are equivalent.
+
+Cell sky130_fd_sc_hd__a32o_4 disconnected node: A1
+Cell sky130_fd_sc_hd__a32o_4 disconnected node: A2
+Cell sky130_fd_sc_hd__a32o_4 disconnected node: A3
+Cell sky130_fd_sc_hd__a32o_4 disconnected node: B1
+Cell sky130_fd_sc_hd__a32o_4 disconnected node: B2
+Cell sky130_fd_sc_hd__a32o_4 disconnected node: VGND
+Cell sky130_fd_sc_hd__a32o_4 disconnected node: VNB
+Cell sky130_fd_sc_hd__a32o_4 disconnected node: VPB
+Cell sky130_fd_sc_hd__a32o_4 disconnected node: VPWR
+Cell sky130_fd_sc_hd__a32o_4 disconnected node: X
+Warning: Equate pins: cell sky130_fd_sc_hd__a32o_4 has no definition, treated as a black box.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__a32o_4 |Circuit 2: sky130_fd_sc_hd__a32o_4
+-------------------------------------------|-------------------------------------------
+A1 |A1
+A2 |A2
+A3 |A3
+B1 |B1
+B2 |B2
+VGND |VGND
+VNB |VNB
+VPB |VPB
+VPWR |VPWR
+X |X
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__a32o_4 and sky130_fd_sc_hd__a32o_4 are equivalent.
+
+Cell sky130_fd_sc_hd__dfrtp_4 disconnected node: CLK
+Cell sky130_fd_sc_hd__dfrtp_4 disconnected node: D
+Cell sky130_fd_sc_hd__dfrtp_4 disconnected node: RESET_B
+Cell sky130_fd_sc_hd__dfrtp_4 disconnected node: VGND
+Cell sky130_fd_sc_hd__dfrtp_4 disconnected node: VNB
+Cell sky130_fd_sc_hd__dfrtp_4 disconnected node: VPB
+Cell sky130_fd_sc_hd__dfrtp_4 disconnected node: VPWR
+Cell sky130_fd_sc_hd__dfrtp_4 disconnected node: Q
+Warning: Equate pins: cell sky130_fd_sc_hd__dfrtp_4 has no definition, treated as a black box.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__dfrtp_4 |Circuit 2: sky130_fd_sc_hd__dfrtp_4
+-------------------------------------------|-------------------------------------------
+CLK |CLK
+D |D
+RESET_B |RESET_B
+VGND |VGND
+VNB |VNB
+VPB |VPB
+VPWR |VPWR
+Q |Q
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__dfrtp_4 and sky130_fd_sc_hd__dfrtp_4 are equivalent.
+
+Cell sky130_fd_sc_hd__clkbuf_1 disconnected node: A
+Cell sky130_fd_sc_hd__clkbuf_1 disconnected node: VGND
+Cell sky130_fd_sc_hd__clkbuf_1 disconnected node: VNB
+Cell sky130_fd_sc_hd__clkbuf_1 disconnected node: VPB
+Cell sky130_fd_sc_hd__clkbuf_1 disconnected node: VPWR
+Cell sky130_fd_sc_hd__clkbuf_1 disconnected node: X
+Warning: Equate pins: cell sky130_fd_sc_hd__clkbuf_1 has no definition, treated as a black box.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__clkbuf_1 |Circuit 2: sky130_fd_sc_hd__clkbuf_1
+-------------------------------------------|-------------------------------------------
+A |A
+VGND |VGND
+VNB |VNB
+VPB |VPB
+VPWR |VPWR
+X |X
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__clkbuf_1 and sky130_fd_sc_hd__clkbuf_1 are equivalent.
+
+Cell sky130_fd_sc_hd__or4_4 disconnected node: A
+Cell sky130_fd_sc_hd__or4_4 disconnected node: B
+Cell sky130_fd_sc_hd__or4_4 disconnected node: C
+Cell sky130_fd_sc_hd__or4_4 disconnected node: D
+Cell sky130_fd_sc_hd__or4_4 disconnected node: VGND
+Cell sky130_fd_sc_hd__or4_4 disconnected node: VNB
+Cell sky130_fd_sc_hd__or4_4 disconnected node: VPB
+Cell sky130_fd_sc_hd__or4_4 disconnected node: VPWR
+Cell sky130_fd_sc_hd__or4_4 disconnected node: X
+Warning: Equate pins: cell sky130_fd_sc_hd__or4_4 has no definition, treated as a black box.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__or4_4 |Circuit 2: sky130_fd_sc_hd__or4_4
+-------------------------------------------|-------------------------------------------
+A |A
+B |B
+C |C
+D |D
+VGND |VGND
+VNB |VNB
+VPB |VPB
+VPWR |VPWR
+X |X
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__or4_4 and sky130_fd_sc_hd__or4_4 are equivalent.
+
+Cell sky130_fd_sc_hd__o22a_4 disconnected node: A1
+Cell sky130_fd_sc_hd__o22a_4 disconnected node: A2
+Cell sky130_fd_sc_hd__o22a_4 disconnected node: B1
+Cell sky130_fd_sc_hd__o22a_4 disconnected node: B2
+Cell sky130_fd_sc_hd__o22a_4 disconnected node: VGND
+Cell sky130_fd_sc_hd__o22a_4 disconnected node: VNB
+Cell sky130_fd_sc_hd__o22a_4 disconnected node: VPB
+Cell sky130_fd_sc_hd__o22a_4 disconnected node: VPWR
+Cell sky130_fd_sc_hd__o22a_4 disconnected node: X
+Warning: Equate pins: cell sky130_fd_sc_hd__o22a_4 has no definition, treated as a black box.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__o22a_4 |Circuit 2: sky130_fd_sc_hd__o22a_4
+-------------------------------------------|-------------------------------------------
+A1 |A1
+A2 |A2
+B1 |B1
+B2 |B2
+VGND |VGND
+VNB |VNB
+VPB |VPB
+VPWR |VPWR
+X |X
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__o22a_4 and sky130_fd_sc_hd__o22a_4 are equivalent.
+
+Cell sky130_fd_sc_hd__nor2_4 disconnected node: A
+Cell sky130_fd_sc_hd__nor2_4 disconnected node: B
+Cell sky130_fd_sc_hd__nor2_4 disconnected node: VGND
+Cell sky130_fd_sc_hd__nor2_4 disconnected node: VNB
+Cell sky130_fd_sc_hd__nor2_4 disconnected node: VPB
+Cell sky130_fd_sc_hd__nor2_4 disconnected node: VPWR
+Cell sky130_fd_sc_hd__nor2_4 disconnected node: Y
+Warning: Equate pins: cell sky130_fd_sc_hd__nor2_4 has no definition, treated as a black box.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__nor2_4 |Circuit 2: sky130_fd_sc_hd__nor2_4
+-------------------------------------------|-------------------------------------------
+A |A
+B |B
+VGND |VGND
+VNB |VNB
+VPB |VPB
+VPWR |VPWR
+Y |Y
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__nor2_4 and sky130_fd_sc_hd__nor2_4 are equivalent.
+
+Cell sky130_fd_sc_hd__o21a_4 disconnected node: A1
+Cell sky130_fd_sc_hd__o21a_4 disconnected node: A2
+Cell sky130_fd_sc_hd__o21a_4 disconnected node: B1
+Cell sky130_fd_sc_hd__o21a_4 disconnected node: VGND
+Cell sky130_fd_sc_hd__o21a_4 disconnected node: VNB
+Cell sky130_fd_sc_hd__o21a_4 disconnected node: VPB
+Cell sky130_fd_sc_hd__o21a_4 disconnected node: VPWR
+Cell sky130_fd_sc_hd__o21a_4 disconnected node: X
+Warning: Equate pins: cell sky130_fd_sc_hd__o21a_4 has no definition, treated as a black box.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__o21a_4 |Circuit 2: sky130_fd_sc_hd__o21a_4
+-------------------------------------------|-------------------------------------------
+A1 |A1
+A2 |A2
+B1 |B1
+VGND |VGND
+VNB |VNB
+VPB |VPB
+VPWR |VPWR
+X |X
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__o21a_4 and sky130_fd_sc_hd__o21a_4 are equivalent.
+
+Cell sky130_fd_sc_hd__a211o_4 disconnected node: A1
+Cell sky130_fd_sc_hd__a211o_4 disconnected node: A2
+Cell sky130_fd_sc_hd__a211o_4 disconnected node: B1
+Cell sky130_fd_sc_hd__a211o_4 disconnected node: C1
+Cell sky130_fd_sc_hd__a211o_4 disconnected node: VGND
+Cell sky130_fd_sc_hd__a211o_4 disconnected node: VNB
+Cell sky130_fd_sc_hd__a211o_4 disconnected node: VPB
+Cell sky130_fd_sc_hd__a211o_4 disconnected node: VPWR
+Cell sky130_fd_sc_hd__a211o_4 disconnected node: X
+Warning: Equate pins: cell sky130_fd_sc_hd__a211o_4 has no definition, treated as a black box.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__a211o_4 |Circuit 2: sky130_fd_sc_hd__a211o_4
+-------------------------------------------|-------------------------------------------
+A1 |A1
+A2 |A2
+B1 |B1
+C1 |C1
+VGND |VGND
+VNB |VNB
+VPB |VPB
+VPWR |VPWR
+X |X
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__a211o_4 and sky130_fd_sc_hd__a211o_4 are equivalent.
+
+Cell sky130_fd_sc_hd__a22oi_4 disconnected node: A1
+Cell sky130_fd_sc_hd__a22oi_4 disconnected node: A2
+Cell sky130_fd_sc_hd__a22oi_4 disconnected node: B1
+Cell sky130_fd_sc_hd__a22oi_4 disconnected node: B2
+Cell sky130_fd_sc_hd__a22oi_4 disconnected node: VGND
+Cell sky130_fd_sc_hd__a22oi_4 disconnected node: VNB
+Cell sky130_fd_sc_hd__a22oi_4 disconnected node: VPB
+Cell sky130_fd_sc_hd__a22oi_4 disconnected node: VPWR
+Cell sky130_fd_sc_hd__a22oi_4 disconnected node: Y
+Warning: Equate pins: cell sky130_fd_sc_hd__a22oi_4 has no definition, treated as a black box.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__a22oi_4 |Circuit 2: sky130_fd_sc_hd__a22oi_4
+-------------------------------------------|-------------------------------------------
+A1 |A1
+A2 |A2
+B1 |B1
+B2 |B2
+VGND |VGND
+VNB |VNB
+VPB |VPB
+VPWR |VPWR
+Y |Y
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__a22oi_4 and sky130_fd_sc_hd__a22oi_4 are equivalent.
+
+Cell sky130_fd_sc_hd__nand2_4 disconnected node: A
+Cell sky130_fd_sc_hd__nand2_4 disconnected node: B
+Cell sky130_fd_sc_hd__nand2_4 disconnected node: VGND
+Cell sky130_fd_sc_hd__nand2_4 disconnected node: VNB
+Cell sky130_fd_sc_hd__nand2_4 disconnected node: VPB
+Cell sky130_fd_sc_hd__nand2_4 disconnected node: VPWR
+Cell sky130_fd_sc_hd__nand2_4 disconnected node: Y
+Warning: Equate pins: cell sky130_fd_sc_hd__nand2_4 has no definition, treated as a black box.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__nand2_4 |Circuit 2: sky130_fd_sc_hd__nand2_4
+-------------------------------------------|-------------------------------------------
+A |A
+B |B
+VGND |VGND
+VNB |VNB
+VPB |VPB
+VPWR |VPWR
+Y |Y
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__nand2_4 and sky130_fd_sc_hd__nand2_4 are equivalent.
+
+Cell sky130_fd_sc_hd__o21ai_4 disconnected node: A1
+Cell sky130_fd_sc_hd__o21ai_4 disconnected node: A2
+Cell sky130_fd_sc_hd__o21ai_4 disconnected node: B1
+Cell sky130_fd_sc_hd__o21ai_4 disconnected node: VGND
+Cell sky130_fd_sc_hd__o21ai_4 disconnected node: VNB
+Cell sky130_fd_sc_hd__o21ai_4 disconnected node: VPB
+Cell sky130_fd_sc_hd__o21ai_4 disconnected node: VPWR
+Cell sky130_fd_sc_hd__o21ai_4 disconnected node: Y
+Warning: Equate pins: cell sky130_fd_sc_hd__o21ai_4 has no definition, treated as a black box.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__o21ai_4 |Circuit 2: sky130_fd_sc_hd__o21ai_4
+-------------------------------------------|-------------------------------------------
+A1 |A1
+A2 |A2
+B1 |B1
+VGND |VGND
+VNB |VNB
+VPB |VPB
+VPWR |VPWR
+Y |Y
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__o21ai_4 and sky130_fd_sc_hd__o21ai_4 are equivalent.
+
+Cell sky130_fd_sc_hd__o32a_4 disconnected node: A1
+Cell sky130_fd_sc_hd__o32a_4 disconnected node: A2
+Cell sky130_fd_sc_hd__o32a_4 disconnected node: A3
+Cell sky130_fd_sc_hd__o32a_4 disconnected node: B1
+Cell sky130_fd_sc_hd__o32a_4 disconnected node: B2
+Cell sky130_fd_sc_hd__o32a_4 disconnected node: VGND
+Cell sky130_fd_sc_hd__o32a_4 disconnected node: VNB
+Cell sky130_fd_sc_hd__o32a_4 disconnected node: VPB
+Cell sky130_fd_sc_hd__o32a_4 disconnected node: VPWR
+Cell sky130_fd_sc_hd__o32a_4 disconnected node: X
+Warning: Equate pins: cell sky130_fd_sc_hd__o32a_4 has no definition, treated as a black box.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__o32a_4 |Circuit 2: sky130_fd_sc_hd__o32a_4
+-------------------------------------------|-------------------------------------------
+A1 |A1
+A2 |A2
+A3 |A3
+B1 |B1
+B2 |B2
+VGND |VGND
+VNB |VNB
+VPB |VPB
+VPWR |VPWR
+X |X
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__o32a_4 and sky130_fd_sc_hd__o32a_4 are equivalent.
+
+Cell sky130_fd_sc_hd__a21bo_4 disconnected node: A1
+Cell sky130_fd_sc_hd__a21bo_4 disconnected node: A2
+Cell sky130_fd_sc_hd__a21bo_4 disconnected node: B1_N
+Cell sky130_fd_sc_hd__a21bo_4 disconnected node: VGND
+Cell sky130_fd_sc_hd__a21bo_4 disconnected node: VNB
+Cell sky130_fd_sc_hd__a21bo_4 disconnected node: VPB
+Cell sky130_fd_sc_hd__a21bo_4 disconnected node: VPWR
+Cell sky130_fd_sc_hd__a21bo_4 disconnected node: X
+Warning: Equate pins: cell sky130_fd_sc_hd__a21bo_4 has no definition, treated as a black box.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__a21bo_4 |Circuit 2: sky130_fd_sc_hd__a21bo_4
+-------------------------------------------|-------------------------------------------
+A1 |A1
+A2 |A2
+B1_N |B1_N
+VGND |VGND
+VNB |VNB
+VPB |VPB
+VPWR |VPWR
+X |X
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__a21bo_4 and sky130_fd_sc_hd__a21bo_4 are equivalent.
+
+Cell sky130_fd_sc_hd__and4_4 disconnected node: A
+Cell sky130_fd_sc_hd__and4_4 disconnected node: B
+Cell sky130_fd_sc_hd__and4_4 disconnected node: C
+Cell sky130_fd_sc_hd__and4_4 disconnected node: D
+Cell sky130_fd_sc_hd__and4_4 disconnected node: VGND
+Cell sky130_fd_sc_hd__and4_4 disconnected node: VNB
+Cell sky130_fd_sc_hd__and4_4 disconnected node: VPB
+Cell sky130_fd_sc_hd__and4_4 disconnected node: VPWR
+Cell sky130_fd_sc_hd__and4_4 disconnected node: X
+Warning: Equate pins: cell sky130_fd_sc_hd__and4_4 has no definition, treated as a black box.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__and4_4 |Circuit 2: sky130_fd_sc_hd__and4_4
+-------------------------------------------|-------------------------------------------
+A |A
+B |B
+C |C
+D |D
+VGND |VGND
+VNB |VNB
+VPB |VPB
+VPWR |VPWR
+X |X
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__and4_4 and sky130_fd_sc_hd__and4_4 are equivalent.
+
+Cell sky130_fd_sc_hd__conb_1 disconnected node: VGND
+Cell sky130_fd_sc_hd__conb_1 disconnected node: VNB
+Cell sky130_fd_sc_hd__conb_1 disconnected node: VPB
+Cell sky130_fd_sc_hd__conb_1 disconnected node: VPWR
+Cell sky130_fd_sc_hd__conb_1 disconnected node: HI
+Cell sky130_fd_sc_hd__conb_1 disconnected node: LO
+Warning: Equate pins: cell sky130_fd_sc_hd__conb_1 has no definition, treated as a black box.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__conb_1 |Circuit 2: sky130_fd_sc_hd__conb_1
+-------------------------------------------|-------------------------------------------
+VGND |VGND
+VNB |VNB
+VPB |VPB
+VPWR |VPWR
+HI |HI
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__conb_1 and sky130_fd_sc_hd__conb_1 are equivalent.
+
+Cell sky130_fd_sc_hd__a21o_4 disconnected node: A1
+Cell sky130_fd_sc_hd__a21o_4 disconnected node: A2
+Cell sky130_fd_sc_hd__a21o_4 disconnected node: B1
+Cell sky130_fd_sc_hd__a21o_4 disconnected node: VGND
+Cell sky130_fd_sc_hd__a21o_4 disconnected node: VNB
+Cell sky130_fd_sc_hd__a21o_4 disconnected node: VPB
+Cell sky130_fd_sc_hd__a21o_4 disconnected node: VPWR
+Cell sky130_fd_sc_hd__a21o_4 disconnected node: X
+Warning: Equate pins: cell sky130_fd_sc_hd__a21o_4 has no definition, treated as a black box.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__a21o_4 |Circuit 2: sky130_fd_sc_hd__a21o_4
+-------------------------------------------|-------------------------------------------
+A1 |A1
+A2 |A2
+B1 |B1
+VGND |VGND
+VNB |VNB
+VPB |VPB
+VPWR |VPWR
+X |X
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__a21o_4 and sky130_fd_sc_hd__a21o_4 are equivalent.
+
+Cell sky130_fd_sc_hd__a21oi_4 disconnected node: A1
+Cell sky130_fd_sc_hd__a21oi_4 disconnected node: A2
+Cell sky130_fd_sc_hd__a21oi_4 disconnected node: B1
+Cell sky130_fd_sc_hd__a21oi_4 disconnected node: VGND
+Cell sky130_fd_sc_hd__a21oi_4 disconnected node: VNB
+Cell sky130_fd_sc_hd__a21oi_4 disconnected node: VPB
+Cell sky130_fd_sc_hd__a21oi_4 disconnected node: VPWR
+Cell sky130_fd_sc_hd__a21oi_4 disconnected node: Y
+Warning: Equate pins: cell sky130_fd_sc_hd__a21oi_4 has no definition, treated as a black box.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__a21oi_4 |Circuit 2: sky130_fd_sc_hd__a21oi_4
+-------------------------------------------|-------------------------------------------
+A1 |A1
+A2 |A2
+B1 |B1
+VGND |VGND
+VNB |VNB
+VPB |VPB
+VPWR |VPWR
+Y |Y
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__a21oi_4 and sky130_fd_sc_hd__a21oi_4 are equivalent.
+
+Cell sky130_fd_sc_hd__buf_4 disconnected node: A
+Cell sky130_fd_sc_hd__buf_4 disconnected node: VGND
+Cell sky130_fd_sc_hd__buf_4 disconnected node: VNB
+Cell sky130_fd_sc_hd__buf_4 disconnected node: VPB
+Cell sky130_fd_sc_hd__buf_4 disconnected node: VPWR
+Cell sky130_fd_sc_hd__buf_4 disconnected node: X
+Warning: Equate pins: cell sky130_fd_sc_hd__buf_4 has no definition, treated as a black box.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__buf_4 |Circuit 2: sky130_fd_sc_hd__buf_4
+-------------------------------------------|-------------------------------------------
+A |A
+VGND |VGND
+VNB |VNB
+VPB |VPB
+VPWR |VPWR
+X |X
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__buf_4 and sky130_fd_sc_hd__buf_4 are equivalent.
+
+Cell sky130_fd_sc_hd__buf_8 disconnected node: A
+Cell sky130_fd_sc_hd__buf_8 disconnected node: VGND
+Cell sky130_fd_sc_hd__buf_8 disconnected node: VNB
+Cell sky130_fd_sc_hd__buf_8 disconnected node: VPB
+Cell sky130_fd_sc_hd__buf_8 disconnected node: VPWR
+Cell sky130_fd_sc_hd__buf_8 disconnected node: X
+Warning: Equate pins: cell sky130_fd_sc_hd__buf_8 has no definition, treated as a black box.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__buf_8 |Circuit 2: sky130_fd_sc_hd__buf_8
+-------------------------------------------|-------------------------------------------
+A |A
+VGND |VGND
+VNB |VNB
+VPB |VPB
+VPWR |VPWR
+X |X
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__buf_8 and sky130_fd_sc_hd__buf_8 are equivalent.
+
+Cell sky130_fd_sc_hd__o41a_4 disconnected node: A1
+Cell sky130_fd_sc_hd__o41a_4 disconnected node: A2
+Cell sky130_fd_sc_hd__o41a_4 disconnected node: A3
+Cell sky130_fd_sc_hd__o41a_4 disconnected node: A4
+Cell sky130_fd_sc_hd__o41a_4 disconnected node: B1
+Cell sky130_fd_sc_hd__o41a_4 disconnected node: VGND
+Cell sky130_fd_sc_hd__o41a_4 disconnected node: VNB
+Cell sky130_fd_sc_hd__o41a_4 disconnected node: VPB
+Cell sky130_fd_sc_hd__o41a_4 disconnected node: VPWR
+Cell sky130_fd_sc_hd__o41a_4 disconnected node: X
+Warning: Equate pins: cell sky130_fd_sc_hd__o41a_4 has no definition, treated as a black box.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__o41a_4 |Circuit 2: sky130_fd_sc_hd__o41a_4
+-------------------------------------------|-------------------------------------------
+A1 |A1
+A2 |A2
+A3 |A3
+A4 |A4
+B1 |B1
+VGND |VGND
+VNB |VNB
+VPB |VPB
+VPWR |VPWR
+X |X
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__o41a_4 and sky130_fd_sc_hd__o41a_4 are equivalent.
+
+Cell sky130_fd_sc_hd__clkbuf_16 disconnected node: A
+Cell sky130_fd_sc_hd__clkbuf_16 disconnected node: VGND
+Cell sky130_fd_sc_hd__clkbuf_16 disconnected node: VNB
+Cell sky130_fd_sc_hd__clkbuf_16 disconnected node: VPB
+Cell sky130_fd_sc_hd__clkbuf_16 disconnected node: VPWR
+Cell sky130_fd_sc_hd__clkbuf_16 disconnected node: X
+Warning: Equate pins: cell sky130_fd_sc_hd__clkbuf_16 has no definition, treated as a black box.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__clkbuf_16 |Circuit 2: sky130_fd_sc_hd__clkbuf_16
+-------------------------------------------|-------------------------------------------
+A |A
+VGND |VGND
+VNB |VNB
+VPB |VPB
+VPWR |VPWR
+X |X
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__clkbuf_16 and sky130_fd_sc_hd__clkbuf_16 are equivalent.
+
+Cell sky130_fd_sc_hd__inv_8 disconnected node: A
+Cell sky130_fd_sc_hd__inv_8 disconnected node: VGND
+Cell sky130_fd_sc_hd__inv_8 disconnected node: VNB
+Cell sky130_fd_sc_hd__inv_8 disconnected node: VPB
+Cell sky130_fd_sc_hd__inv_8 disconnected node: VPWR
+Cell sky130_fd_sc_hd__inv_8 disconnected node: Y
+Warning: Equate pins: cell sky130_fd_sc_hd__inv_8 has no definition, treated as a black box.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__inv_8 |Circuit 2: sky130_fd_sc_hd__inv_8
+-------------------------------------------|-------------------------------------------
+A |A
+VGND |VGND
+VNB |VNB
+VPB |VPB
+VPWR |VPWR
+Y |Y
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__inv_8 and sky130_fd_sc_hd__inv_8 are equivalent.
+
+Cell sky130_fd_sc_hd__a2111o_4 disconnected node: A1
+Cell sky130_fd_sc_hd__a2111o_4 disconnected node: A2
+Cell sky130_fd_sc_hd__a2111o_4 disconnected node: B1
+Cell sky130_fd_sc_hd__a2111o_4 disconnected node: C1
+Cell sky130_fd_sc_hd__a2111o_4 disconnected node: D1
+Cell sky130_fd_sc_hd__a2111o_4 disconnected node: VGND
+Cell sky130_fd_sc_hd__a2111o_4 disconnected node: VNB
+Cell sky130_fd_sc_hd__a2111o_4 disconnected node: VPB
+Cell sky130_fd_sc_hd__a2111o_4 disconnected node: VPWR
+Cell sky130_fd_sc_hd__a2111o_4 disconnected node: X
+Warning: Equate pins: cell sky130_fd_sc_hd__a2111o_4 has no definition, treated as a black box.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__a2111o_4 |Circuit 2: sky130_fd_sc_hd__a2111o_4
+-------------------------------------------|-------------------------------------------
+A1 |A1
+A2 |A2
+B1 |B1
+C1 |C1
+D1 |D1
+VGND |VGND
+VNB |VNB
+VPB |VPB
+VPWR |VPWR
+X |X
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__a2111o_4 and sky130_fd_sc_hd__a2111o_4 are equivalent.
+
+Cell sky130_fd_sc_hd__dfstp_4 disconnected node: CLK
+Cell sky130_fd_sc_hd__dfstp_4 disconnected node: D
+Cell sky130_fd_sc_hd__dfstp_4 disconnected node: SET_B
+Cell sky130_fd_sc_hd__dfstp_4 disconnected node: VGND
+Cell sky130_fd_sc_hd__dfstp_4 disconnected node: VNB
+Cell sky130_fd_sc_hd__dfstp_4 disconnected node: VPB
+Cell sky130_fd_sc_hd__dfstp_4 disconnected node: VPWR
+Cell sky130_fd_sc_hd__dfstp_4 disconnected node: Q
+Warning: Equate pins: cell sky130_fd_sc_hd__dfstp_4 has no definition, treated as a black box.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__dfstp_4 |Circuit 2: sky130_fd_sc_hd__dfstp_4
+-------------------------------------------|-------------------------------------------
+CLK |CLK
+D |D
+SET_B |SET_B
+VGND |VGND
+VNB |VNB
+VPB |VPB
+VPWR |VPWR
+Q |Q
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__dfstp_4 and sky130_fd_sc_hd__dfstp_4 are equivalent.
+
+Cell sky130_fd_sc_hd__inv_4 disconnected node: A
+Cell sky130_fd_sc_hd__inv_4 disconnected node: VGND
+Cell sky130_fd_sc_hd__inv_4 disconnected node: VNB
+Cell sky130_fd_sc_hd__inv_4 disconnected node: VPB
+Cell sky130_fd_sc_hd__inv_4 disconnected node: VPWR
+Cell sky130_fd_sc_hd__inv_4 disconnected node: Y
+Warning: Equate pins: cell sky130_fd_sc_hd__inv_4 has no definition, treated as a black box.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__inv_4 |Circuit 2: sky130_fd_sc_hd__inv_4
+-------------------------------------------|-------------------------------------------
+A |A
+VGND |VGND
+VNB |VNB
+VPB |VPB
+VPWR |VPWR
+Y |Y
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__inv_4 and sky130_fd_sc_hd__inv_4 are equivalent.
+
+Cell sky130_fd_sc_hd__a41o_4 disconnected node: A1
+Cell sky130_fd_sc_hd__a41o_4 disconnected node: A2
+Cell sky130_fd_sc_hd__a41o_4 disconnected node: A3
+Cell sky130_fd_sc_hd__a41o_4 disconnected node: A4
+Cell sky130_fd_sc_hd__a41o_4 disconnected node: B1
+Cell sky130_fd_sc_hd__a41o_4 disconnected node: VGND
+Cell sky130_fd_sc_hd__a41o_4 disconnected node: VNB
+Cell sky130_fd_sc_hd__a41o_4 disconnected node: VPB
+Cell sky130_fd_sc_hd__a41o_4 disconnected node: VPWR
+Cell sky130_fd_sc_hd__a41o_4 disconnected node: X
+Warning: Equate pins: cell sky130_fd_sc_hd__a41o_4 has no definition, treated as a black box.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__a41o_4 |Circuit 2: sky130_fd_sc_hd__a41o_4
+-------------------------------------------|-------------------------------------------
+A1 |A1
+A2 |A2
+A3 |A3
+A4 |A4
+B1 |B1
+VGND |VGND
+VNB |VNB
+VPB |VPB
+VPWR |VPWR
+X |X
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__a41o_4 and sky130_fd_sc_hd__a41o_4 are equivalent.
+
+Cell user_proj_example disconnected node: io_in[0]
+Cell user_proj_example disconnected node: io_in[1]
+Cell user_proj_example disconnected node: io_in[2]
+Cell user_proj_example disconnected node: io_in[3]
+Cell user_proj_example disconnected node: io_in[4]
+Cell user_proj_example disconnected node: io_in[5]
+Cell user_proj_example disconnected node: la_data_in[100]
+Cell user_proj_example disconnected node: la_data_in[101]
+Cell user_proj_example disconnected node: la_data_in[102]
+Cell user_proj_example disconnected node: la_data_in[103]
+Cell user_proj_example disconnected node: la_data_in[104]
+Cell user_proj_example disconnected node: la_data_in[105]
+Cell user_proj_example disconnected node: la_data_in[106]
+Cell user_proj_example disconnected node: la_data_in[107]
+Cell user_proj_example disconnected node: la_data_in[108]
+Cell user_proj_example disconnected node: la_data_in[109]
+Cell user_proj_example disconnected node: la_data_in[10]
+Cell user_proj_example disconnected node: la_data_in[110]
+Cell user_proj_example disconnected node: la_data_in[111]
+Cell user_proj_example disconnected node: la_data_in[112]
+Cell user_proj_example disconnected node: la_data_in[113]
+Cell user_proj_example disconnected node: la_data_in[114]
+Cell user_proj_example disconnected node: la_data_in[115]
+Cell user_proj_example disconnected node: la_data_in[116]
+Cell user_proj_example disconnected node: la_data_in[117]
+Cell user_proj_example disconnected node: la_data_in[118]
+Cell user_proj_example disconnected node: la_data_in[119]
+Cell user_proj_example disconnected node: la_data_in[11]
+Cell user_proj_example disconnected node: la_data_in[120]
+Cell user_proj_example disconnected node: la_data_in[121]
+Cell user_proj_example disconnected node: la_data_in[122]
+Cell user_proj_example disconnected node: la_data_in[123]
+Cell user_proj_example disconnected node: la_data_in[124]
+Cell user_proj_example disconnected node: la_data_in[125]
+Cell user_proj_example disconnected node: la_data_in[126]
+Cell user_proj_example disconnected node: la_data_in[127]
+Cell user_proj_example disconnected node: la_data_in[12]
+Cell user_proj_example disconnected node: la_data_in[13]
+Cell user_proj_example disconnected node: la_data_in[14]
+Cell user_proj_example disconnected node: la_data_in[15]
+Cell user_proj_example disconnected node: la_data_in[16]
+Cell user_proj_example disconnected node: la_data_in[17]
+Cell user_proj_example disconnected node: la_data_in[18]
+Cell user_proj_example disconnected node: la_data_in[19]
+Cell user_proj_example disconnected node: la_data_in[20]
+Cell user_proj_example disconnected node: la_data_in[21]
+Cell user_proj_example disconnected node: la_data_in[22]
+Cell user_proj_example disconnected node: la_data_in[23]
+Cell user_proj_example disconnected node: la_data_in[24]
+Cell user_proj_example disconnected node: la_data_in[25]
+Cell user_proj_example disconnected node: la_data_in[26]
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+Cell user_proj_example disconnected node: la_data_in[28]
+Cell user_proj_example disconnected node: la_data_in[29]
+Cell user_proj_example disconnected node: la_data_in[30]
+Cell user_proj_example disconnected node: la_data_in[31]
+Cell user_proj_example disconnected node: la_data_in[32]
+Cell user_proj_example disconnected node: la_data_in[33]
+Cell user_proj_example disconnected node: la_data_in[34]
+Cell user_proj_example disconnected node: la_data_in[35]
+Cell user_proj_example disconnected node: la_data_in[36]
+Cell user_proj_example disconnected node: la_data_in[37]
+Cell user_proj_example disconnected node: la_data_in[38]
+Cell user_proj_example disconnected node: la_data_in[39]
+Cell user_proj_example disconnected node: la_data_in[40]
+Cell user_proj_example disconnected node: la_data_in[41]
+Cell user_proj_example disconnected node: la_data_in[42]
+Cell user_proj_example disconnected node: la_data_in[43]
+Cell user_proj_example disconnected node: la_data_in[44]
+Cell user_proj_example disconnected node: la_data_in[45]
+Cell user_proj_example disconnected node: la_data_in[46]
+Cell user_proj_example disconnected node: la_data_in[47]
+Cell user_proj_example disconnected node: la_data_in[48]
+Cell user_proj_example disconnected node: la_data_in[49]
+Cell user_proj_example disconnected node: la_data_in[4]
+Cell user_proj_example disconnected node: la_data_in[50]
+Cell user_proj_example disconnected node: la_data_in[51]
+Cell user_proj_example disconnected node: la_data_in[52]
+Cell user_proj_example disconnected node: la_data_in[53]
+Cell user_proj_example disconnected node: la_data_in[54]
+Cell user_proj_example disconnected node: la_data_in[55]
+Cell user_proj_example disconnected node: la_data_in[56]
+Cell user_proj_example disconnected node: la_data_in[57]
+Cell user_proj_example disconnected node: la_data_in[58]
+Cell user_proj_example disconnected node: la_data_in[59]
+Cell user_proj_example disconnected node: la_data_in[5]
+Cell user_proj_example disconnected node: la_data_in[60]
+Cell user_proj_example disconnected node: la_data_in[61]
+Cell user_proj_example disconnected node: la_data_in[62]
+Cell user_proj_example disconnected node: la_data_in[63]
+Cell user_proj_example disconnected node: la_data_in[64]
+Cell user_proj_example disconnected node: la_data_in[65]
+Cell user_proj_example disconnected node: la_data_in[66]
+Cell user_proj_example disconnected node: la_data_in[67]
+Cell user_proj_example disconnected node: la_data_in[68]
+Cell user_proj_example disconnected node: la_data_in[69]
+Cell user_proj_example disconnected node: la_data_in[6]
+Cell user_proj_example disconnected node: la_data_in[70]
+Cell user_proj_example disconnected node: la_data_in[71]
+Cell user_proj_example disconnected node: la_data_in[72]
+Cell user_proj_example disconnected node: la_data_in[73]
+Cell user_proj_example disconnected node: la_data_in[74]
+Cell user_proj_example disconnected node: la_data_in[75]
+Cell user_proj_example disconnected node: la_data_in[76]
+Cell user_proj_example disconnected node: la_data_in[77]
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+Cell user_proj_example disconnected node: la_data_in[79]
+Cell user_proj_example disconnected node: la_data_in[7]
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+Cell user_proj_example disconnected node: la_data_in[81]
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+Cell user_proj_example disconnected node: la_data_in[83]
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+Cell user_proj_example disconnected node: la_data_in[85]
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+Cell user_proj_example disconnected node: la_data_in[89]
+Cell user_proj_example disconnected node: la_data_in[8]
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+Cell user_proj_example disconnected node: la_data_in[93]
+Cell user_proj_example disconnected node: la_data_in[94]
+Cell user_proj_example disconnected node: la_data_in[95]
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+Cell user_proj_example disconnected node: la_data_in[97]
+Cell user_proj_example disconnected node: la_data_in[98]
+Cell user_proj_example disconnected node: la_data_in[99]
+Cell user_proj_example disconnected node: la_data_in[9]
+Cell user_proj_example disconnected node: la_oen[0]
+Cell user_proj_example disconnected node: la_oen[100]
+Cell user_proj_example disconnected node: la_oen[101]
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+Cell user_proj_example disconnected node: la_oen[119]
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+Cell user_proj_example disconnected node: la_oen[121]
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+
+Cell user_proj_example disconnected node: io_in[5]
+Cell user_proj_example disconnected node: io_in[4]
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+Cell user_proj_example disconnected node: io_in[2]
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+Cell user_proj_example disconnected node: io_out[4]
+Cell user_proj_example disconnected node: io_out[3]
+Cell user_proj_example disconnected node: io_out[2]
+Cell user_proj_example disconnected node: io_out[1]
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+Cell user_proj_example disconnected node: la_data_out[122]
+Cell user_proj_example disconnected node: la_data_out[121]
+Cell user_proj_example disconnected node: la_data_out[120]
+Cell user_proj_example disconnected node: la_data_out[119]
+Cell user_proj_example disconnected node: la_data_out[118]
+Cell user_proj_example disconnected node: la_data_out[117]
+Cell user_proj_example disconnected node: la_data_out[116]
+Cell user_proj_example disconnected node: la_data_out[115]
+Cell user_proj_example disconnected node: la_data_out[114]
+Cell user_proj_example disconnected node: la_data_out[113]
+Cell user_proj_example disconnected node: la_data_out[112]
+Cell user_proj_example disconnected node: la_data_out[111]
+Cell user_proj_example disconnected node: la_data_out[110]
+Cell user_proj_example disconnected node: la_data_out[109]
+Cell user_proj_example disconnected node: la_data_out[108]
+Cell user_proj_example disconnected node: la_data_out[107]
+Cell user_proj_example disconnected node: la_data_out[106]
+Cell user_proj_example disconnected node: la_data_out[105]
+Cell user_proj_example disconnected node: la_data_out[104]
+Cell user_proj_example disconnected node: la_data_out[103]
+Cell user_proj_example disconnected node: la_data_out[102]
+Cell user_proj_example disconnected node: la_data_out[101]
+Cell user_proj_example disconnected node: la_data_out[100]
+Cell user_proj_example disconnected node: la_data_out[99]
+Cell user_proj_example disconnected node: la_data_out[98]
+Cell user_proj_example disconnected node: la_data_out[97]
+Cell user_proj_example disconnected node: la_data_out[96]
+Cell user_proj_example disconnected node: la_data_out[95]
+Cell user_proj_example disconnected node: la_data_out[94]
+Cell user_proj_example disconnected node: la_data_out[93]
+Cell user_proj_example disconnected node: la_data_out[92]
+Cell user_proj_example disconnected node: la_data_out[91]
+Cell user_proj_example disconnected node: la_data_out[90]
+Cell user_proj_example disconnected node: la_data_out[89]
+Cell user_proj_example disconnected node: la_data_out[88]
+Cell user_proj_example disconnected node: la_data_out[87]
+Cell user_proj_example disconnected node: la_data_out[86]
+Cell user_proj_example disconnected node: la_data_out[85]
+Cell user_proj_example disconnected node: la_data_out[84]
+Cell user_proj_example disconnected node: la_data_out[83]
+Cell user_proj_example disconnected node: la_data_out[82]
+Cell user_proj_example disconnected node: la_data_out[81]
+Cell user_proj_example disconnected node: la_data_out[80]
+Cell user_proj_example disconnected node: la_data_out[79]
+Cell user_proj_example disconnected node: la_data_out[78]
+Cell user_proj_example disconnected node: la_data_out[77]
+Cell user_proj_example disconnected node: la_data_out[76]
+Cell user_proj_example disconnected node: la_data_out[75]
+Cell user_proj_example disconnected node: la_data_out[74]
+Cell user_proj_example disconnected node: la_data_out[73]
+Cell user_proj_example disconnected node: la_data_out[72]
+Cell user_proj_example disconnected node: la_data_out[71]
+Cell user_proj_example disconnected node: la_data_out[70]
+Cell user_proj_example disconnected node: la_data_out[69]
+Cell user_proj_example disconnected node: la_data_out[68]
+Cell user_proj_example disconnected node: la_data_out[67]
+Cell user_proj_example disconnected node: la_data_out[66]
+Cell user_proj_example disconnected node: la_data_out[65]
+Cell user_proj_example disconnected node: la_data_out[64]
+Cell user_proj_example disconnected node: la_oen[127]
+Cell user_proj_example disconnected node: la_oen[126]
+Cell user_proj_example disconnected node: la_oen[125]
+Cell user_proj_example disconnected node: la_oen[124]
+Cell user_proj_example disconnected node: la_oen[123]
+Cell user_proj_example disconnected node: la_oen[122]
+Cell user_proj_example disconnected node: la_oen[121]
+Cell user_proj_example disconnected node: la_oen[120]
+Cell user_proj_example disconnected node: la_oen[119]
+Cell user_proj_example disconnected node: la_oen[118]
+Cell user_proj_example disconnected node: la_oen[117]
+Cell user_proj_example disconnected node: la_oen[116]
+Cell user_proj_example disconnected node: la_oen[115]
+Cell user_proj_example disconnected node: la_oen[114]
+Cell user_proj_example disconnected node: la_oen[113]
+Cell user_proj_example disconnected node: la_oen[112]
+Cell user_proj_example disconnected node: la_oen[111]
+Cell user_proj_example disconnected node: la_oen[110]
+Cell user_proj_example disconnected node: la_oen[109]
+Cell user_proj_example disconnected node: la_oen[108]
+Cell user_proj_example disconnected node: la_oen[107]
+Cell user_proj_example disconnected node: la_oen[106]
+Cell user_proj_example disconnected node: la_oen[105]
+Cell user_proj_example disconnected node: la_oen[104]
+Cell user_proj_example disconnected node: la_oen[103]
+Cell user_proj_example disconnected node: la_oen[102]
+Cell user_proj_example disconnected node: la_oen[101]
+Cell user_proj_example disconnected node: la_oen[100]
+Cell user_proj_example disconnected node: la_oen[99]
+Cell user_proj_example disconnected node: la_oen[98]
+Cell user_proj_example disconnected node: la_oen[97]
+Cell user_proj_example disconnected node: la_oen[96]
+Cell user_proj_example disconnected node: la_oen[95]
+Cell user_proj_example disconnected node: la_oen[94]
+Cell user_proj_example disconnected node: la_oen[93]
+Cell user_proj_example disconnected node: la_oen[92]
+Cell user_proj_example disconnected node: la_oen[91]
+Cell user_proj_example disconnected node: la_oen[90]
+Cell user_proj_example disconnected node: la_oen[89]
+Cell user_proj_example disconnected node: la_oen[88]
+Cell user_proj_example disconnected node: la_oen[87]
+Cell user_proj_example disconnected node: la_oen[86]
+Cell user_proj_example disconnected node: la_oen[85]
+Cell user_proj_example disconnected node: la_oen[84]
+Cell user_proj_example disconnected node: la_oen[83]
+Cell user_proj_example disconnected node: la_oen[82]
+Cell user_proj_example disconnected node: la_oen[81]
+Cell user_proj_example disconnected node: la_oen[80]
+Cell user_proj_example disconnected node: la_oen[79]
+Cell user_proj_example disconnected node: la_oen[78]
+Cell user_proj_example disconnected node: la_oen[77]
+Cell user_proj_example disconnected node: la_oen[76]
+Cell user_proj_example disconnected node: la_oen[75]
+Cell user_proj_example disconnected node: la_oen[74]
+Cell user_proj_example disconnected node: la_oen[73]
+Cell user_proj_example disconnected node: la_oen[72]
+Cell user_proj_example disconnected node: la_oen[71]
+Cell user_proj_example disconnected node: la_oen[70]
+Cell user_proj_example disconnected node: la_oen[69]
+Cell user_proj_example disconnected node: la_oen[68]
+Cell user_proj_example disconnected node: la_oen[67]
+Cell user_proj_example disconnected node: la_oen[66]
+Cell user_proj_example disconnected node: la_oen[65]
+Cell user_proj_example disconnected node: la_oen[64]
+Cell user_proj_example disconnected node: la_oen[63]
+Cell user_proj_example disconnected node: la_oen[62]
+Cell user_proj_example disconnected node: la_oen[61]
+Cell user_proj_example disconnected node: la_oen[60]
+Cell user_proj_example disconnected node: la_oen[59]
+Cell user_proj_example disconnected node: la_oen[58]
+Cell user_proj_example disconnected node: la_oen[57]
+Cell user_proj_example disconnected node: la_oen[56]
+Cell user_proj_example disconnected node: la_oen[55]
+Cell user_proj_example disconnected node: la_oen[54]
+Cell user_proj_example disconnected node: la_oen[53]
+Cell user_proj_example disconnected node: la_oen[52]
+Cell user_proj_example disconnected node: la_oen[51]
+Cell user_proj_example disconnected node: la_oen[50]
+Cell user_proj_example disconnected node: la_oen[49]
+Cell user_proj_example disconnected node: la_oen[48]
+Cell user_proj_example disconnected node: la_oen[47]
+Cell user_proj_example disconnected node: la_oen[46]
+Cell user_proj_example disconnected node: la_oen[45]
+Cell user_proj_example disconnected node: la_oen[44]
+Cell user_proj_example disconnected node: la_oen[43]
+Cell user_proj_example disconnected node: la_oen[42]
+Cell user_proj_example disconnected node: la_oen[41]
+Cell user_proj_example disconnected node: la_oen[40]
+Cell user_proj_example disconnected node: la_oen[39]
+Cell user_proj_example disconnected node: la_oen[38]
+Cell user_proj_example disconnected node: la_oen[37]
+Cell user_proj_example disconnected node: la_oen[36]
+Cell user_proj_example disconnected node: la_oen[35]
+Cell user_proj_example disconnected node: la_oen[34]
+Cell user_proj_example disconnected node: la_oen[33]
+Cell user_proj_example disconnected node: la_oen[32]
+Cell user_proj_example disconnected node: la_oen[31]
+Cell user_proj_example disconnected node: la_oen[30]
+Cell user_proj_example disconnected node: la_oen[29]
+Cell user_proj_example disconnected node: la_oen[28]
+Cell user_proj_example disconnected node: la_oen[27]
+Cell user_proj_example disconnected node: la_oen[26]
+Cell user_proj_example disconnected node: la_oen[25]
+Cell user_proj_example disconnected node: la_oen[24]
+Cell user_proj_example disconnected node: la_oen[23]
+Cell user_proj_example disconnected node: la_oen[22]
+Cell user_proj_example disconnected node: la_oen[21]
+Cell user_proj_example disconnected node: la_oen[20]
+Cell user_proj_example disconnected node: la_oen[19]
+Cell user_proj_example disconnected node: la_oen[18]
+Cell user_proj_example disconnected node: la_oen[17]
+Cell user_proj_example disconnected node: la_oen[16]
+Cell user_proj_example disconnected node: la_oen[15]
+Cell user_proj_example disconnected node: la_oen[14]
+Cell user_proj_example disconnected node: la_oen[13]
+Cell user_proj_example disconnected node: la_oen[12]
+Cell user_proj_example disconnected node: la_oen[11]
+Cell user_proj_example disconnected node: la_oen[10]
+Cell user_proj_example disconnected node: la_oen[9]
+Cell user_proj_example disconnected node: la_oen[8]
+Cell user_proj_example disconnected node: la_oen[7]
+Cell user_proj_example disconnected node: la_oen[6]
+Cell user_proj_example disconnected node: la_oen[5]
+Cell user_proj_example disconnected node: la_oen[4]
+Cell user_proj_example disconnected node: la_oen[3]
+Cell user_proj_example disconnected node: la_oen[2]
+Cell user_proj_example disconnected node: la_oen[1]
+Cell user_proj_example disconnected node: la_oen[0]
+
+Subcircuit summary:
+Circuit 1: user_proj_example |Circuit 2: user_proj_example
+-------------------------------------------|-------------------------------------------
+sky130_fd_sc_hd__or2_4 (30981) |sky130_fd_sc_hd__or2_4 (30981)
+sky130_fd_sc_hd__dfxtp_4 (26132) |sky130_fd_sc_hd__dfxtp_4 (26132)
+sky130_fd_sc_hd__diode_2 (126422) |sky130_fd_sc_hd__diode_2 (126422)
+sky130_fd_sc_hd__buf_2 (35952) |sky130_fd_sc_hd__buf_2 (35952)
+sky130_fd_sc_hd__or3_4 (8866) |sky130_fd_sc_hd__or3_4 (8866)
+sky130_fd_sc_hd__tapvpwrvgnd_1 (100264) |sky130_fd_sc_hd__tapvpwrvgnd_1 (100264)
+sky130_fd_sc_hd__and2_4 (2003) |sky130_fd_sc_hd__and2_4 (2003)
+sky130_fd_sc_hd__and3_4 (18762) |sky130_fd_sc_hd__and3_4 (18762)
+sky130_fd_sc_hd__inv_2 (25672) |sky130_fd_sc_hd__inv_2 (25672)
+sky130_fd_sc_hd__a2bb2o_4 (24546) |sky130_fd_sc_hd__a2bb2o_4 (24546)
+sky130_fd_sc_hd__a32o_4 (1198) |sky130_fd_sc_hd__a32o_4 (1198)
+sky130_fd_sc_hd__dfrtp_4 (626) |sky130_fd_sc_hd__dfrtp_4 (626)
+sky130_fd_sc_hd__clkbuf_1 (4278) |sky130_fd_sc_hd__clkbuf_1 (4278)
+sky130_fd_sc_hd__or4_4 (1116) |sky130_fd_sc_hd__or4_4 (1116)
+sky130_fd_sc_hd__o22a_4 (2992) |sky130_fd_sc_hd__o22a_4 (2992)
+sky130_fd_sc_hd__nor2_4 (3469) |sky130_fd_sc_hd__nor2_4 (3469)
+sky130_fd_sc_hd__o21a_4 (1178) |sky130_fd_sc_hd__o21a_4 (1178)
+sky130_fd_sc_hd__a211o_4 (1593) |sky130_fd_sc_hd__a211o_4 (1593)
+sky130_fd_sc_hd__a22oi_4 (163) |sky130_fd_sc_hd__a22oi_4 (163)
+sky130_fd_sc_hd__nand2_4 (558) |sky130_fd_sc_hd__nand2_4 (558)
+sky130_fd_sc_hd__o21ai_4 (305) |sky130_fd_sc_hd__o21ai_4 (305)
+sky130_fd_sc_hd__o32a_4 (231) |sky130_fd_sc_hd__o32a_4 (231)
+sky130_fd_sc_hd__a21bo_4 (68) |sky130_fd_sc_hd__a21bo_4 (68)
+sky130_fd_sc_hd__and4_4 (265) |sky130_fd_sc_hd__and4_4 (265)
+sky130_fd_sc_hd__conb_1 (77) |sky130_fd_sc_hd__conb_1 (77)
+sky130_fd_sc_hd__a21o_4 (203) |sky130_fd_sc_hd__a21o_4 (203)
+sky130_fd_sc_hd__a21oi_4 (173) |sky130_fd_sc_hd__a21oi_4 (173)
+sky130_fd_sc_hd__buf_4 (167) |sky130_fd_sc_hd__buf_4 (167)
+sky130_fd_sc_hd__buf_8 (102) |sky130_fd_sc_hd__buf_8 (102)
+sky130_fd_sc_hd__o41a_4 (6) |sky130_fd_sc_hd__o41a_4 (6)
+sky130_fd_sc_hd__clkbuf_16 (28) |sky130_fd_sc_hd__clkbuf_16 (28)
+sky130_fd_sc_hd__inv_8 (5) |sky130_fd_sc_hd__inv_8 (5)
+sky130_fd_sc_hd__a2111o_4 (35) |sky130_fd_sc_hd__a2111o_4 (35)
+sky130_fd_sc_hd__dfstp_4 (18) |sky130_fd_sc_hd__dfstp_4 (18)
+sky130_fd_sc_hd__inv_4 (2) |sky130_fd_sc_hd__inv_4 (2)
+sky130_fd_sc_hd__a41o_4 (2) |sky130_fd_sc_hd__a41o_4 (2)
+Number of devices: 418458 |Number of devices: 418458
+Number of nets: 191884 |Number of nets: 191884
+---------------------------------------------------------------------------------------
+Resolving automorphisms by property value.
+Resolving automorphisms by pin name.
+Netlists match with 24127 symmetries.
+Circuits match correctly.
+
+Subcircuit pins:
+Circuit 1: user_proj_example |Circuit 2: user_proj_example
+-------------------------------------------|-------------------------------------------
+wbs_dat_o[6] |wbs_dat_o[6]
+wbs_dat_o[7] |wbs_dat_o[7]
+wbs_ack_o |wbs_ack_o
+io_oeb[0] |io_oeb[0]
+io_oeb[1] |io_oeb[1]
+io_oeb[2] |io_oeb[2]
+io_oeb[3] |io_oeb[3]
+io_oeb[4] |io_oeb[4]
+io_oeb[5] |io_oeb[5]
+la_data_out[35] |la_data_out[35]
+la_data_out[36] |la_data_out[36]
+la_data_out[37] |la_data_out[37]
+la_data_out[39] |la_data_out[39]
+la_data_out[34] |la_data_out[34]
+la_data_out[10] |la_data_out[10]
+la_data_out[13] |la_data_out[13]
+la_data_out[14] |la_data_out[14]
+la_data_out[15] |la_data_out[15]
+la_data_out[16] |la_data_out[16]
+la_data_out[17] |la_data_out[17]
+la_data_out[18] |la_data_out[18]
+la_data_out[19] |la_data_out[19]
+la_data_out[20] |la_data_out[20]
+la_data_out[21] |la_data_out[21]
+la_data_out[38] |la_data_out[38]
+la_data_out[4] |la_data_out[4]
+la_data_out[5] |la_data_out[5]
+la_data_out[23] |la_data_out[23]
+la_data_out[22] |la_data_out[22]
+la_data_out[24] |la_data_out[24]
+la_data_out[25] |la_data_out[25]
+la_data_out[26] |la_data_out[26]
+la_data_out[28] |la_data_out[28]
+la_data_out[27] |la_data_out[27]
+la_data_out[29] |la_data_out[29]
+la_data_out[30] |la_data_out[30]
+la_data_out[31] |la_data_out[31]
+la_data_out[6] |la_data_out[6]
+la_data_out[7] |la_data_out[7]
+la_data_out[32] |la_data_out[32]
+la_data_out[40] |la_data_out[40]
+la_data_out[41] |la_data_out[41]
+la_data_out[42] |la_data_out[42]
+la_data_out[43] |la_data_out[43]
+la_data_out[44] |la_data_out[44]
+la_data_out[45] |la_data_out[45]
+la_data_out[46] |la_data_out[46]
+la_data_out[47] |la_data_out[47]
+la_data_out[33] |la_data_out[33]
+la_data_out[58] |la_data_out[58]
+la_data_out[59] |la_data_out[59]
+la_data_out[61] |la_data_out[61]
+la_data_out[48] |la_data_out[48]
+la_data_out[49] |la_data_out[49]
+la_data_out[50] |la_data_out[50]
+la_data_out[51] |la_data_out[51]
+la_data_out[54] |la_data_out[54]
+la_data_out[55] |la_data_out[55]
+la_data_out[56] |la_data_out[56]
+la_data_out[53] |la_data_out[53]
+la_data_out[57] |la_data_out[57]
+la_data_out[60] |la_data_out[60]
+la_data_out[62] |la_data_out[62]
+la_data_out[63] |la_data_out[63]
+la_data_out[52] |la_data_out[52]
+la_data_out[0] |la_data_out[0]
+la_data_out[1] |la_data_out[1]
+la_data_out[8] |la_data_out[8]
+la_data_out[9] |la_data_out[9]
+la_data_out[11] |la_data_out[11]
+la_data_out[12] |la_data_out[12]
+la_data_out[2] |la_data_out[2]
+la_data_out[3] |la_data_out[3]
+io_out[27] |(no matching pin)
+io_out[29] |(no matching pin)
+io_out[25] |(no matching pin)
+io_out[30] |(no matching pin)
+io_out[28] |(no matching pin)
+io_out[26] |(no matching pin)
+io_out[23] |(no matching pin)
+io_out[24] |(no matching pin)
+io_out[22] |(no matching pin)
+io_out[21] |(no matching pin)
+io_out[20] |(no matching pin)
+io_oeb[6] |(no matching pin)
+io_oeb[21] |(no matching pin)
+io_oeb[19] |(no matching pin)
+io_oeb[20] |(no matching pin)
+io_oeb[18] |(no matching pin)
+io_oeb[7] |(no matching pin)
+io_oeb[17] |(no matching pin)
+io_oeb[16] |(no matching pin)
+io_oeb[15] |(no matching pin)
+io_oeb[14] |(no matching pin)
+io_out[19] |(no matching pin)
+io_out[16] |(no matching pin)
+io_out[6] |(no matching pin)
+io_out[34] |(no matching pin)
+io_out[9] |(no matching pin)
+io_out[8] |(no matching pin)
+io_out[13] |(no matching pin)
+io_out[12] |(no matching pin)
+io_out[31] |(no matching pin)
+io_out[32] |(no matching pin)
+io_out[37] |(no matching pin)
+io_out[36] |(no matching pin)
+io_out[35] |(no matching pin)
+io_out[33] |(no matching pin)
+io_out[18] |(no matching pin)
+io_out[17] |(no matching pin)
+io_out[14] |(no matching pin)
+io_out[15] |(no matching pin)
+io_out[7] |(no matching pin)
+io_oeb[36] |(no matching pin)
+io_oeb[26] |(no matching pin)
+io_oeb[37] |(no matching pin)
+io_oeb[34] |(no matching pin)
+io_oeb[22] |(no matching pin)
+io_oeb[23] |(no matching pin)
+io_oeb[24] |(no matching pin)
+io_oeb[35] |(no matching pin)
+io_oeb[30] |(no matching pin)
+io_oeb[25] |(no matching pin)
+io_oeb[32] |(no matching pin)
+io_oeb[31] |(no matching pin)
+io_oeb[27] |(no matching pin)
+io_oeb[33] |(no matching pin)
+io_oeb[28] |(no matching pin)
+io_oeb[29] |(no matching pin)
+io_in[7] |io_in[7]
+io_in[6] |io_in[6]
+io_in[9] |io_in[9]
+io_in[16] |io_in[16]
+io_in[20] |io_in[20]
+io_in[22] |io_in[22]
+io_in[29] |io_in[29]
+io_in[8] |io_in[8]
+io_in[19] |io_in[19]
+io_in[25] |io_in[25]
+io_in[28] |io_in[28]
+io_in[34] |io_in[34]
+io_in[32] |io_in[32]
+io_in[30] |io_in[30]
+io_in[17] |io_in[17]
+io_in[31] |io_in[31]
+io_in[15] |io_in[15]
+io_in[18] |io_in[18]
+io_in[23] |io_in[23]
+io_in[27] |io_in[27]
+io_in[36] |io_in[36]
+io_in[14] |io_in[14]
+io_in[21] |io_in[21]
+io_in[24] |io_in[24]
+io_in[26] |io_in[26]
+io_in[33] |io_in[33]
+io_in[35] |io_in[35]
+io_in[37] |io_in[37]
+la_data_in[2] |la_data_in[2]
+la_data_in[1] |la_data_in[1]
+io_in[12] |io_in[12]
+la_data_in[3] |la_data_in[3]
+io_in[11] |io_in[11]
+wbs_dat_o[30] |wbs_dat_o[30]
+wbs_dat_o[29] |wbs_dat_o[29]
+wbs_dat_o[15] |wbs_dat_o[15]
+wbs_dat_o[26] |wbs_dat_o[26]
+wbs_dat_o[27] |wbs_dat_o[27]
+wbs_dat_o[24] |wbs_dat_o[24]
+wbs_dat_o[13] |wbs_dat_o[13]
+wbs_dat_o[25] |wbs_dat_o[25]
+wbs_dat_o[12] |wbs_dat_o[12]
+wbs_dat_o[14] |wbs_dat_o[14]
+wbs_dat_o[28] |wbs_dat_o[28]
+wbs_dat_o[23] |wbs_dat_o[23]
+wbs_dat_o[20] |wbs_dat_o[20]
+wbs_dat_o[10] |wbs_dat_o[10]
+wbs_dat_o[11] |wbs_dat_o[11]
+wbs_dat_o[21] |wbs_dat_o[21]
+wbs_dat_o[22] |wbs_dat_o[22]
+wbs_dat_o[31] |wbs_dat_o[31]
+wbs_dat_o[19] |wbs_dat_o[19]
+wbs_dat_o[18] |wbs_dat_o[18]
+wbs_dat_o[1] |wbs_dat_o[1]
+wbs_dat_o[3] |wbs_dat_o[3]
+wbs_dat_o[2] |wbs_dat_o[2]
+wbs_dat_o[8] |wbs_dat_o[8]
+wbs_dat_o[9] |wbs_dat_o[9]
+wbs_dat_o[5] |wbs_dat_o[5]
+wbs_dat_o[4] |wbs_dat_o[4]
+wbs_dat_o[0] |wbs_dat_o[0]
+wbs_dat_o[17] |wbs_dat_o[17]
+wbs_dat_o[16] |wbs_dat_o[16]
+io_out[10] |io_out[10]
+io_out[11] |io_out[11]
+io_oeb[12] |io_oeb[12]
+io_oeb[11] |io_oeb[11]
+io_oeb[8] |io_oeb[8]
+io_oeb[13] |io_oeb[13]
+io_oeb[9] |io_oeb[9]
+io_oeb[10] |io_oeb[10]
+wbs_adr_i[22] |wbs_adr_i[22]
+wbs_adr_i[20] |wbs_adr_i[20]
+wbs_adr_i[21] |wbs_adr_i[21]
+wbs_adr_i[29] |wbs_adr_i[29]
+wbs_adr_i[28] |wbs_adr_i[28]
+wbs_adr_i[25] |wbs_adr_i[25]
+wbs_adr_i[24] |wbs_adr_i[24]
+wbs_adr_i[31] |wbs_adr_i[31]
+wbs_adr_i[27] |wbs_adr_i[27]
+wbs_adr_i[30] |wbs_adr_i[30]
+wbs_adr_i[26] |wbs_adr_i[26]
+wbs_stb_i |wbs_stb_i
+wbs_adr_i[2] |wbs_adr_i[2]
+wbs_adr_i[0] |wbs_adr_i[0]
+wbs_adr_i[1] |wbs_adr_i[1]
+wbs_adr_i[12] |wbs_adr_i[12]
+wbs_adr_i[4] |wbs_adr_i[4]
+wbs_we_i |wbs_we_i
+wbs_adr_i[18] |wbs_adr_i[18]
+wbs_adr_i[11] |wbs_adr_i[11]
+wbs_dat_i[1] |wbs_dat_i[1]
+wbs_dat_i[5] |wbs_dat_i[5]
+wbs_dat_i[2] |wbs_dat_i[2]
+wbs_dat_i[4] |wbs_dat_i[4]
+wbs_dat_i[3] |wbs_dat_i[3]
+wbs_adr_i[17] |wbs_adr_i[17]
+wbs_sel_i[0] |wbs_sel_i[0]
+wbs_dat_i[6] |wbs_dat_i[6]
+wbs_dat_i[31] |wbs_dat_i[31]
+wbs_adr_i[9] |wbs_adr_i[9]
+wbs_dat_i[7] |wbs_dat_i[7]
+wbs_sel_i[3] |wbs_sel_i[3]
+wbs_adr_i[16] |wbs_adr_i[16]
+wbs_dat_i[19] |wbs_dat_i[19]
+wbs_sel_i[1] |wbs_sel_i[1]
+wbs_sel_i[2] |wbs_sel_i[2]
+wbs_adr_i[23] |wbs_adr_i[23]
+wbs_cyc_i |wbs_cyc_i
+wbs_dat_i[14] |wbs_dat_i[14]
+wbs_dat_i[15] |wbs_dat_i[15]
+wbs_dat_i[9] |wbs_dat_i[9]
+wbs_dat_i[13] |wbs_dat_i[13]
+wbs_dat_i[12] |wbs_dat_i[12]
+wbs_dat_i[8] |wbs_dat_i[8]
+wbs_adr_i[10] |wbs_adr_i[10]
+wbs_adr_i[14] |wbs_adr_i[14]
+wbs_adr_i[13] |wbs_adr_i[13]
+wbs_adr_i[7] |wbs_adr_i[7]
+wbs_adr_i[3] |wbs_adr_i[3]
+wbs_adr_i[15] |wbs_adr_i[15]
+wbs_adr_i[5] |wbs_adr_i[5]
+wbs_dat_i[17] |wbs_dat_i[17]
+wbs_dat_i[11] |wbs_dat_i[11]
+wbs_dat_i[10] |wbs_dat_i[10]
+wbs_adr_i[6] |wbs_adr_i[6]
+wbs_dat_i[28] |wbs_dat_i[28]
+wbs_dat_i[16] |wbs_dat_i[16]
+wbs_dat_i[26] |wbs_dat_i[26]
+wbs_adr_i[8] |wbs_adr_i[8]
+wbs_dat_i[21] |wbs_dat_i[21]
+wbs_dat_i[22] |wbs_dat_i[22]
+wbs_dat_i[20] |wbs_dat_i[20]
+wbs_dat_i[18] |wbs_dat_i[18]
+wbs_dat_i[30] |wbs_dat_i[30]
+wbs_dat_i[29] |wbs_dat_i[29]
+wbs_dat_i[27] |wbs_dat_i[27]
+wbs_dat_i[0] |wbs_dat_i[0]
+wbs_dat_i[25] |wbs_dat_i[25]
+wbs_dat_i[24] |wbs_dat_i[24]
+wbs_dat_i[23] |wbs_dat_i[23]
+wbs_adr_i[19] |wbs_adr_i[19]
+la_data_in[0] |la_data_in[0]
+wb_rst_i |wb_rst_i
+wb_clk_i |wb_clk_i
+VGND |VGND
+VPWR |VPWR
+io_in[10] |io_in[10]
+io_in[13] |io_in[13]
+---------------------------------------------------------------------------------------
+Cell pin lists for user_proj_example and user_proj_example altered to match.
+The top level cell failed pin matching.
diff --git a/openlane/user_proj_example/results/results/lvs/user_proj_example.lvs_parsed.log b/openlane/user_proj_example/results/results/lvs/user_proj_example.lvs_parsed.log
new file mode 100644
index 0000000..67ccf39
--- /dev/null
+++ b/openlane/user_proj_example/results/results/lvs/user_proj_example.lvs_parsed.log
@@ -0,0 +1,9 @@
+LVS reports:
+ net count difference = 0
+ device count difference = 0
+ unmatched nets = 0
+ unmatched devices = 0
+ unmatched pins = 56
+ property failures = 0
+
+Total errors = 56
diff --git a/openlane/user_proj_example/results/tmp/magic_antenna.tcl b/openlane/user_proj_example/results/tmp/magic_antenna.tcl
new file mode 100644
index 0000000..6babf2f
--- /dev/null
+++ b/openlane/user_proj_example/results/tmp/magic_antenna.tcl
@@ -0,0 +1,28 @@
+
+lef read $::env(TECH_LEF)
+if { [info exist ::env(EXTRA_LEFS)] } {
+ set lefs_in $::env(EXTRA_LEFS)
+ foreach lef_file $lefs_in {
+ lef read $lef_file
+ }
+}
+def read $::env(CURRENT_DEF)
+load $::env(DESIGN_NAME) -dereference
+cd $::env(TMP_DIR)/magic/
+select top cell
+
+# for now, do extraction anyway; can be optimized by reading the maglef ext
+# but getting many warnings
+if { ! [file exists $::env(DESIGN_NAME).ext] } {
+ extract do local
+ extract no capacitance
+ extract no coupling
+ extract no resistance
+ extract no adjust
+ # extract warn all
+ extract
+ feedback save /project/openlane/user_proj_example/runs/16-12_10-43/logs/magic/magic_ext2spice.antenna.feedback.txt
+}
+antennacheck debug
+antennacheck
+
diff --git a/openlane/user_proj_example/results/tmp/magic_spice.tcl b/openlane/user_proj_example/results/tmp/magic_spice.tcl
new file mode 100644
index 0000000..a241483
--- /dev/null
+++ b/openlane/user_proj_example/results/tmp/magic_spice.tcl
@@ -0,0 +1,24 @@
+
+lef read /mnt/data/workspace/pdk/sky130A/libs.ref/sky130_fd_sc_hd/techlef/sky130_fd_sc_hd.tlef
+if { [info exist ::env(EXTRA_LEFS)] } {
+ set lefs_in $::env(EXTRA_LEFS)
+ foreach lef_file $lefs_in {
+ lef read $lef_file
+ }
+}
+def read /project/openlane/user_proj_example/runs/16-12_10-43/results/routing/user_proj_example.def
+load user_proj_example -dereference
+cd /project/openlane/user_proj_example/runs/16-12_10-43/results/magic/
+extract do local
+extract no capacitance
+extract no coupling
+extract no resistance
+extract no adjust
+# extract warn all
+extract
+
+ext2spice lvs
+ext2spice user_proj_example.ext
+feedback save /project/openlane/user_proj_example/runs/16-12_10-43/logs/magic/magic_ext2spice.feedback.txt
+# exec cp user_proj_example.spice /project/openlane/user_proj_example/runs/16-12_10-43/results/magic/user_proj_example.spice
+
