Split the main power supply into managment and two user areas. Mostly
put back together again from phase2, although only the gpio testbench
has been updated, and the gpio tesbench is currently not passing although
most signals seem to be right. Modified the memory map to allow for an
additional word in the management I/O GPIO read/write data, and rewrote
the code to handle any number of I/Os in the user space, expanding the
memory map by one word for every 32 user GPIO pads (there are currently
37 user GPIO pads specified, so this change resolves issues with the
upper 5 pads; the last phase2 design defined only 32 user I/O pads).
diff --git a/verilog/rtl/mgmt_soc.v b/verilog/rtl/mgmt_soc.v
index 0de30f2..f6cf0f6 100644
--- a/verilog/rtl/mgmt_soc.v
+++ b/verilog/rtl/mgmt_soc.v
@@ -42,7 +42,10 @@
`include "mprj_ctrl.v"
`include "convert_gpio_sigs.v"
-module mgmt_soc (
+module mgmt_soc #(
+ parameter MPRJ_IO_PADS = 32,
+ parameter MPRJ_PWR_PADS = 32
+) (
`ifdef LVS
inout vdd1v8, /* 1.8V domain */
inout vss,
@@ -194,10 +197,6 @@
parameter LA_ENA_2 = 8'h18;
parameter LA_ENA_3 = 8'h1c;
- // Mega-Project Control
- parameter MPRJ_IO_PADS = 32;
- parameter MPRJ_PWR_PADS = 32;
-
// System Control Registers
parameter PLL_OUT = 8'h00;
parameter TRAP_OUT = 8'h04;
@@ -639,7 +638,7 @@
wire mprj_ctrl_stb_i;
wire mprj_ctrl_ack_o;
wire [31:0] mprj_ctrl_dat_o;
- wire [31:0] mgmt_out_pre;
+ wire [MPRJ_IO_PADS-1:0] mgmt_out_pre;
// Bits assigned to specific functions as outputs prevent the
// mprj GPIO-as-output from applying data when that function
