In spite of many errors that still need fixing, this is a major advance
over the previous commit. All verilog modules are in place more or less
as intended, with various functions such as the housekeeping SPI placed
on user area pads, with the ability to switch to user control from the
configuration. The pad control bits are local to the pads and loaded
via serial shift register, so that there are not hundreds of control wires
feeding into the user space. The user has three basic controls over each
pad: in, out, and outenb. Two timer/counters and an SPI master have been
added to the SoC. The SPI master shares I/O with the housekeeping SPI, so
that all housekeeping SPI registers can be accessed from the SoC directly.
diff --git a/verilog/rtl/mgmt_soc.v b/verilog/rtl/mgmt_soc.v
index 5162a9b..ce43250 100644
--- a/verilog/rtl/mgmt_soc.v
+++ b/verilog/rtl/mgmt_soc.v
@@ -76,12 +76,17 @@
output mprj_io_loader_data,
// Mega-Project pad data (when management SoC controls the pad)
- inout [MPRJ_IO_PADS-1:0] mgmt_io_data,
+ // inout [MPRJ_IO_PADS-1:0] mgmt_io_data,
+ input [MPRJ_IO_PADS-1:0] mgmt_in_data,
+ output [MPRJ_IO_PADS-1:0] mgmt_out_data,
+ output [MPRJ_IO_PADS-1:0] mgmt_outz_data,
+ output [MPRJ_IO_PADS-1:0] mgmt_oeb_data,
// SPI master
output spi_csb,
output spi_sck,
output spi_sdo,
+ output spi_sdoenb,
input spi_sdi,
// UART
@@ -209,9 +214,9 @@
parameter MPRJ_PWR_PADS = 32;
// System Control Registers
- parameter PLL_OUT = 8'h0c;
- parameter TRAP_OUT = 8'h10;
- parameter IRQ7_SRC = 8'h14;
+ parameter PLL_OUT = 8'h00;
+ parameter TRAP_OUT = 8'h04;
+ parameter IRQ7_SRC = 8'h08;
// Wishbone Interconnect
localparam ADR_WIDTH = 32;
@@ -477,6 +482,7 @@
.sck(spi_sck),
.sdi(spi_sdi),
.sdo(spi_sdo),
+ .sdoenb(spi_sdoenb),
.irq(irq_spi_master)
);
@@ -650,7 +656,11 @@
.serial_clock(mprj_io_loader_clock),
.serial_resetn(mprj_io_loader_resetn),
.serial_data_out(mprj_io_loader_data),
- .mgmt_gpio_io(mgmt_io_data)
+ // .mgmt_gpio_io(mgmt_io_data)
+ .mgmt_gpio_in(mgmt_in_data),
+ .mgmt_gpio_out(mgmt_out_data),
+ .mgmt_gpio_outz(mgmt_outz_data),
+ .mgmt_gpio_oeb(mgmt_oeb_data)
);
// Wishbone Slave RAM
