commit 336e082659fb914bf7224732383dff5c0dae0178
author Matt Venn <matt@mattvenn.net> Mon Nov 16 12:03:29 2020 +0100
committer Matt Venn <matt@mattvenn.net> Mon Nov 16 12:03:29 2020 +0100
tree dae97d1a06287d1301ba5e609c15dfa780d5fc2a
parent 08cd6eba30b5b59bbd33a808a9173203d7a7175b

add missing signals

verilog/rtl/simpleuart.v

diff --git a/verilog/rtl/simpleuart.v b/verilog/rtl/simpleuart.v
index 62a3ea6..66e1915 100644
--- a/verilog/rtl/simpleuart.v
+++ b/verilog/rtl/simpleuart.v
@@ -45,6 +45,7 @@
     wire [31:0] simpleuart_reg_div_do;
     wire [31:0] simpleuart_reg_dat_do;
     wire [31:0] simpleuart_reg_cfg_do;
+    wire reg_dat_wait;
 
     wire resetn = ~wb_rst_i;
     wire valid = wb_stb_i && wb_cyc_i; 
@@ -126,6 +127,8 @@
     reg [31:0] send_divcnt;
     reg send_dummy;
 
+    wire reg_ena_do;
+
     assign reg_div_do = cfg_divider;
     assign reg_ena_do = {31'd0, enabled};