Testbench simulations are now all working correctly with the pre-release
version of sky130_fd_io.
diff --git a/verilog/dv/caravel/mgmt_soc/gpio/gpio_tb.v b/verilog/dv/caravel/mgmt_soc/gpio/gpio_tb.v
index 01dc63e..7932cbd 100644
--- a/verilog/dv/caravel/mgmt_soc/gpio/gpio_tb.v
+++ b/verilog/dv/caravel/mgmt_soc/gpio/gpio_tb.v
@@ -24,10 +24,10 @@
`include "spiflash.v"
module gpio_tb;
- wire VDD3V3;
- assign VDD3V3 = 1'b1;
reg clock;
+ reg power1;
+ reg power2;
always #10 clock <= (clock === 1'b0);
@@ -106,16 +106,28 @@
#2000;
end
+ initial begin // Power-up
+ power1 <= 1'b0;
+ power2 <= 1'b0;
+ #200;
+ power1 <= 1'b1;
+ #200;
+ power2 <= 1'b1;
+ end
+
+
always @(checkbits) begin
#1 $display("GPIO state = %b (%d - %d)", checkbits,
checkbits_hi, checkbits_lo);
end
+ wire VDD3V3;
wire VDD1V8;
wire VSS;
+ assign VDD3V3 = power1;
+ assign VDD1V8 = power2;
assign VSS = 1'b0;
- assign VDD1V8 = 1'b1;
// These are the mappings of mprj_io GPIO pads that are set to
// specific functions on startup:
diff --git a/verilog/dv/caravel/mgmt_soc/hkspi/hkspi_tb.v b/verilog/dv/caravel/mgmt_soc/hkspi/hkspi_tb.v
index c08aa6f..dd1aca2 100644
--- a/verilog/dv/caravel/mgmt_soc/hkspi/hkspi_tb.v
+++ b/verilog/dv/caravel/mgmt_soc/hkspi/hkspi_tb.v
@@ -11,6 +11,7 @@
module hkspi_tb;
reg clock;
reg SDI, CSB, SCK, RSTB;
+ reg power1, power2;
wire gpio;
wire [15:0] checkbits;
@@ -33,6 +34,15 @@
clock = 0;
end
+ initial begin // Power-up sequence
+ power1 <= 1'b0;
+ power2 <= 1'b0;
+ #200;
+ power1 <= 1'b1;
+ #200;
+ power2 <= 1'b1;
+ end
+
// The main testbench is here. Put the housekeeping SPI into
// pass-thru mode and read several bytes from the flash SPI.
@@ -204,8 +214,8 @@
$display("Read register 16 = 0x%02x (should be 0x03)", tbdata);
if(tbdata !== 8'h03) begin $display("Monitor: Test HK SPI (RTL) Failed"); $finish; end
read_byte(tbdata);
- $display("Read register 17 = 0x%02x (should be 0x02)", tbdata);
- if(tbdata !== 8'h02) begin $display("Monitor: Test HK SPI (RTL) Failed"); $finish; end
+ $display("Read register 17 = 0x%02x (should be 0x12)", tbdata);
+ if(tbdata !== 8'h12) begin $display("Monitor: Test HK SPI (RTL) Failed"); $finish; end
read_byte(tbdata);
$display("Read register 18 = 0x%02x (should be 0x04)", tbdata);
if(tbdata !== 8'h04) begin $display("Monitor: Test HK SPI (RTL) Failed"); $finish; end
@@ -222,9 +232,9 @@
wire VDD1V8;
wire VSS;
- assign VDD3V3 = 1'b1;
+ assign VDD3V3 = power1;
+ assign VDD1V8 = power2;
assign VSS = 1'b0;
- assign VDD1V8 = 1'b1;
wire hk_sck;
wire hk_csb;
diff --git a/verilog/dv/caravel/mgmt_soc/mem/mem_tb.v b/verilog/dv/caravel/mgmt_soc/mem/mem_tb.v
index c3afb8b..f0fbcae 100644
--- a/verilog/dv/caravel/mgmt_soc/mem/mem_tb.v
+++ b/verilog/dv/caravel/mgmt_soc/mem/mem_tb.v
@@ -26,6 +26,7 @@
module mem_tb;
reg clock;
reg RSTB;
+ reg power1, power2;
wire gpio;
wire [15:0] checkbits;
@@ -69,6 +70,15 @@
#2000;
end
+ initial begin // Power-up sequence
+ power1 <= 1'b0;
+ power2 <= 1'b0;
+ #200;
+ power1 <= 1'b1;
+ #200;
+ power2 <= 1'b1;
+ end
+
always @(checkbits) begin
if(checkbits == 16'hA040) begin
$display("Mem Test (word rw) started");
@@ -115,8 +125,8 @@
wire VSS;
assign VSS = 1'b0;
- assign VDD3V3 = 1'b1;
- assign VDD1V8 = 1'b1;
+ assign VDD3V3 = power1;
+ assign VDD1V8 = power2;
caravel uut (
.vddio (VDD3V3),
diff --git a/verilog/dv/caravel/mgmt_soc/mprj_ctrl/mprj_ctrl_tb.v b/verilog/dv/caravel/mgmt_soc/mprj_ctrl/mprj_ctrl_tb.v
index c248521..85f0c48 100644
--- a/verilog/dv/caravel/mgmt_soc/mprj_ctrl/mprj_ctrl_tb.v
+++ b/verilog/dv/caravel/mgmt_soc/mprj_ctrl/mprj_ctrl_tb.v
@@ -7,6 +7,7 @@
module mprj_ctrl_tb;
reg clock;
reg RSTB;
+ reg power1, power2;
wire gpio;
wire flash_csb;
@@ -86,6 +87,15 @@
#2000;
end
+ initial begin
+ power1 <= 1'b0;
+ power2 <= 1'b0;
+ #200;
+ power1 <= 1'b1;
+ #200;
+ power2 <= 1'b1;
+ end
+
always @(gpio) begin
#1 $display("GPIO state = %b ", gpio);
end
@@ -94,9 +104,9 @@
wire VDD1V8;
wire VSS;
+ assign VDD3V3 = power1;
+ assign VDD1V8 = power2;
assign VSS = 1'b0;
- assign VDD1V8 = 1'b1;
- assign VDD3V3 = 1'b1;
caravel uut (
.vddio (VDD3V3),
diff --git a/verilog/dv/caravel/mgmt_soc/pass_thru/pass_thru_tb.v b/verilog/dv/caravel/mgmt_soc/pass_thru/pass_thru_tb.v
index dbe5322..e741a29 100644
--- a/verilog/dv/caravel/mgmt_soc/pass_thru/pass_thru_tb.v
+++ b/verilog/dv/caravel/mgmt_soc/pass_thru/pass_thru_tb.v
@@ -11,6 +11,7 @@
module pass_thru_tb;
reg clock;
reg SDI, CSB, SCK, RSTB;
+ reg power1, power2;
wire gpio;
wire [15:0] checkbits;
@@ -33,6 +34,15 @@
clock = 0;
end
+ initial begin // Power-up sequence
+ power1 <= 1'b0;
+ power2 <= 1'b0;
+ #200;
+ power1 <= 1'b1;
+ #200;
+ power2 <= 1'b1;
+ end
+
// The main testbench is here. Put the housekeeping SPI into
// pass-thru mode and read several bytes from the flash SPI.
@@ -195,9 +205,9 @@
wire VDD1V8;
wire VSS;
- assign VDD3V3 = 1'b1;
+ assign VDD3V3 = power1;
+ assign VDD1V8 = power2;
assign VSS = 1'b0;
- assign VDD1V8 = 1'b1;
wire hk_sck;
wire hk_csb;
diff --git a/verilog/dv/caravel/mgmt_soc/perf/perf_tb.v b/verilog/dv/caravel/mgmt_soc/perf/perf_tb.v
index 3323480..c5721f9 100644
--- a/verilog/dv/caravel/mgmt_soc/perf/perf_tb.v
+++ b/verilog/dv/caravel/mgmt_soc/perf/perf_tb.v
@@ -26,6 +26,7 @@
module perf_tb;
reg clock;
reg RSTB;
+ reg power1, power2;
wire gpio;
wire [15:0] checkbits;
@@ -73,6 +74,15 @@
#2000;
end
+ initial begin // Power-up sequence
+ power1 <= 1'b0;
+ power2 <= 1'b0;
+ #200;
+ power1 <= 1'b1;
+ #200;
+ power2 <= 1'b1;
+ end
+
always @(checkbits) begin
//#1 $display("GPIO state = %X ", gpio);
if(checkbits == 16'hA000) begin
@@ -90,9 +100,9 @@
wire VDD1V8;
wire VSS;
+ assign VDD3V3 = power1;
+ assign VDD1V8 = power2;
assign VSS = 1'b0;
- assign VDD1V8 = 1'b1;
- assign VDD3V3 = 1'b1;
caravel uut (
.vddio (VDD3V3),
diff --git a/verilog/dv/caravel/mgmt_soc/pll/pll_tb.v b/verilog/dv/caravel/mgmt_soc/pll/pll_tb.v
index 5921a03..613364b 100644
--- a/verilog/dv/caravel/mgmt_soc/pll/pll_tb.v
+++ b/verilog/dv/caravel/mgmt_soc/pll/pll_tb.v
@@ -6,6 +6,8 @@
module pll_tb;
reg clock;
+ reg power1;
+ reg power2;
reg RSTB;
wire gpio;
@@ -74,6 +76,15 @@
#2000;
end
+ initial begin
+ power1 <= 1'b0;
+ power2 <= 1'b0;
+ #200;
+ power1 <= 1'b1;
+ #200;
+ power2 <= 1'b1;
+ end
+
always @(checkbits) begin
#1 $display("GPIO state = %b ", checkbits);
end
@@ -82,9 +93,9 @@
wire VDD1V8;
wire VSS;
+ assign VDD3V3 = power1;
+ assign VDD1V8 = power2;
assign VSS = 1'b0;
- assign VDD1V8 = 1'b1;
- assign VDD3V3 = 1'b1;
caravel uut (
.vddio (VDD3V3),
diff --git a/verilog/dv/caravel/mgmt_soc/sysctrl/sysctrl_tb.v b/verilog/dv/caravel/mgmt_soc/sysctrl/sysctrl_tb.v
index 06362c8..6fb2f69 100644
--- a/verilog/dv/caravel/mgmt_soc/sysctrl/sysctrl_tb.v
+++ b/verilog/dv/caravel/mgmt_soc/sysctrl/sysctrl_tb.v
@@ -7,6 +7,7 @@
module sysctrl_tb;
reg clock;
reg RSTB;
+ reg power1, power2;
wire gpio;
wire [15:0] checkbits;
@@ -104,8 +105,8 @@
$finish;
end
wait(checkbits == 16'hA04a);
- $display(" SPI value = 0x%x (should be 0x02)", spivalue);
- if(spivalue !== 32'h02) begin
+ $display(" SPI value = 0x%x (should be 0x12)", spivalue);
+ if(spivalue !== 32'h12) begin
$display("Monitor: Test Sysctrl (RTL) Failed");
$finish;
end
@@ -128,6 +129,15 @@
#2000;
end
+ initial begin // Power-up sequence
+ power1 <= 1'b0;
+ power2 <= 1'b0;
+ #200;
+ power1 <= 1'b1;
+ #200;
+ power2 <= 1'b1;
+ end
+
always @(checkbits) begin
#1 $display("GPIO state = %b ", checkbits);
end
@@ -136,9 +146,9 @@
wire VDD1V8;
wire VSS;
+ assign VDD3V3 = power1;
+ assign VDD1V8 = power2;
assign VSS = 1'b0;
- assign VDD1V8 = 1'b1;
- assign VDD3V3 = 1'b1;
caravel uut (
.vddio (VDD3V3),
diff --git a/verilog/dv/caravel/mgmt_soc/timer/timer_tb.v b/verilog/dv/caravel/mgmt_soc/timer/timer_tb.v
index 44b50db..c41fb6d 100644
--- a/verilog/dv/caravel/mgmt_soc/timer/timer_tb.v
+++ b/verilog/dv/caravel/mgmt_soc/timer/timer_tb.v
@@ -24,10 +24,10 @@
`include "spiflash.v"
module timer_tb;
- wire VDD3V3;
- assign VDD3V3 = 1'b1;
+ reg RSTB;
reg clock;
+ reg power1, power2;
always #10 clock <= (clock === 1'b0);
@@ -62,8 +62,6 @@
wire flash_io0;
wire flash_io1;
- reg RSTB;
-
// Monitor
initial begin
wait(checkbits == 5'h0a);
@@ -107,21 +105,30 @@
initial begin
RSTB <= 1'b0;
-
#1000;
RSTB <= 1'b1; // Release reset
- #2000;
+ end
+
+ initial begin // Power-up sequence
+ power1 <= 1'b0;
+ power2 <= 1'b0;
+ #200;
+ power1 <= 1'b1;
+ #200;
+ power2 <= 1'b1;
end
always @(checkbits) begin
#1 $display("Timer state = %b (%d)", countbits, countbits);
end
+ wire VDD3V3;
wire VDD1V8;
wire VSS;
+ assign VDD3V3 = power1;
+ assign VDD1V8 = power2;
assign VSS = 1'b0;
- assign VDD1V8 = 1'b1;
// These are the mappings of mprj_io GPIO pads that are set to
// specific functions on startup:
diff --git a/verilog/dv/caravel/mgmt_soc/timer2/timer2_tb.v b/verilog/dv/caravel/mgmt_soc/timer2/timer2_tb.v
index 4baea92..cd04097 100644
--- a/verilog/dv/caravel/mgmt_soc/timer2/timer2_tb.v
+++ b/verilog/dv/caravel/mgmt_soc/timer2/timer2_tb.v
@@ -24,10 +24,10 @@
`include "spiflash.v"
module timer2_tb;
- wire VDD3V3;
- assign VDD3V3 = 1'b1;
reg clock;
+ reg RSTB;
+ reg power1, power2;
always #10 clock <= (clock === 1'b0);
@@ -62,8 +62,6 @@
wire flash_io0;
wire flash_io1;
- reg RSTB;
-
// Monitor
initial begin
wait(checkbits == 5'h0a);
@@ -107,21 +105,30 @@
initial begin
RSTB <= 1'b0;
-
#1000;
RSTB <= 1'b1; // Release reset
- #2000;
+ end
+
+ initial begin // Power-up sequence
+ power1 <= 1'b0;
+ power2 <= 1'b0;
+ #200;
+ power1 <= 1'b1;
+ #200;
+ power2 <= 1'b1;
end
always @(checkbits) begin
#1 $display("Timer state = %b (%d)", countbits, countbits);
end
+ wire VDD3V3;
wire VDD1V8;
wire VSS;
+ assign VDD3V3 = power1;
+ assign VDD1V8 = power2;
assign VSS = 1'b0;
- assign VDD1V8 = 1'b1;
// These are the mappings of mprj_io GPIO pads that are set to
// specific functions on startup:
diff --git a/verilog/dv/caravel/mgmt_soc/uart/uart_tb.v b/verilog/dv/caravel/mgmt_soc/uart/uart_tb.v
index b3f8bd3..6907155 100644
--- a/verilog/dv/caravel/mgmt_soc/uart/uart_tb.v
+++ b/verilog/dv/caravel/mgmt_soc/uart/uart_tb.v
@@ -27,6 +27,7 @@
module uart_tb;
reg clock;
reg RSTB;
+ reg power1, power2;
wire gpio;
wire flash_csb;
@@ -66,6 +67,15 @@
#2000;
end
+ initial begin // Power-up sequence
+ power1 <= 1'b0;
+ power2 <= 1'b0;
+ #200;
+ power1 <= 1'b1;
+ #200;
+ power2 <= 1'b1;
+ end
+
always @(checkbits) begin
if(checkbits == 16'hA000) begin
$display("UART Test started");
@@ -80,9 +90,9 @@
wire VDD1V8;
wire VSS;
+ assign VDD3V3 = power1;
+ assign VDD1V8 = power2;
assign VSS = 1'b0;
- assign VDD1V8 = 1'b1;
- assign VDD3V3 = 1'b1;
caravel uut (
.vddio (VDD3V3),
diff --git a/verilog/dv/caravel/user_proj_example/io_ports/io_ports_tb.v b/verilog/dv/caravel/user_proj_example/io_ports/io_ports_tb.v
index a83b64f..741a982 100644
--- a/verilog/dv/caravel/user_proj_example/io_ports/io_ports_tb.v
+++ b/verilog/dv/caravel/user_proj_example/io_ports/io_ports_tb.v
@@ -7,7 +7,8 @@
module io_ports_tb;
reg clock;
reg RSTB;
- wire SDO;
+ reg power1, power2;
+ reg power3, power4;
wire gpio;
wire [36:0] mprj_io;
@@ -61,27 +62,43 @@
initial begin
RSTB <= 1'b0;
- #1000;
- RSTB <= 1'b1; // Release reset
#2000;
+ RSTB <= 1'b1; // Release reset
+ end
+
+ initial begin // Power-up sequence
+ power1 <= 1'b0;
+ power2 <= 1'b0;
+ power3 <= 1'b0;
+ power4 <= 1'b0;
+ #200;
+ power1 <= 1'b1;
+ #200;
+ power2 <= 1'b1;
+ #200;
+ power3 <= 1'b1;
+ #200;
+ power4 <= 1'b1;
end
always @(mprj_io) begin
#1 $display("MPRJ-IO state = %b ", mprj_io[7:0]);
end
- wire VDD1V8;
- wire VDD3V3;
- wire VSS;
-
wire flash_csb;
wire flash_clk;
wire flash_io0;
wire flash_io1;
+ wire VDD1V8;
+ wire VDD3V3;
+ wire VSS;
+
+ assign VDD3V3 = power1;
+ assign VDD1V8 = power2;
+ assign USER_VDD3V3 = power3;
+ assign USER_VDD1V8 = power4;
assign VSS = 1'b0;
- assign VDD1V8 = 1'b1;
- assign VDD3V3 = 1'b1;
caravel uut (
.vddio (VDD3V3),
@@ -90,12 +107,12 @@
.vssa (VSS),
.vccd (VDD1V8),
.vssd (VSS),
- .vdda1 (VDD3V3),
- .vdda2 (VDD3V3),
+ .vdda1 (USER_VDD3V3),
+ .vdda2 (USER_VDD3V3),
.vssa1 (VSS),
.vssa2 (VSS),
- .vccd1 (VDD1V8),
- .vccd2 (VDD1V8),
+ .vccd1 (USER_VDD1V8),
+ .vccd2 (USER_VDD1V8),
.vssd1 (VSS),
.vssd2 (VSS),
.clock (clock),
diff --git a/verilog/dv/caravel/user_proj_example/la_test1/la_test1_tb.v b/verilog/dv/caravel/user_proj_example/la_test1/la_test1_tb.v
index df9bfaf..9bee0a6 100644
--- a/verilog/dv/caravel/user_proj_example/la_test1/la_test1_tb.v
+++ b/verilog/dv/caravel/user_proj_example/la_test1/la_test1_tb.v
@@ -8,7 +8,7 @@
module la_test1_tb;
reg clock;
reg RSTB;
- wire SDO;
+ reg power1, power2;
wire gpio;
wire uart_tx;
@@ -55,18 +55,27 @@
#2000;
end
- wire VDD1V8;
- wire VDD3V3;
- wire VSS;
-
+ initial begin // Power-up sequence
+ power1 <= 1'b0;
+ power2 <= 1'b0;
+ #200;
+ power1 <= 1'b1;
+ #200;
+ power2 <= 1'b1;
+ end
+
wire flash_csb;
wire flash_clk;
wire flash_io0;
wire flash_io1;
+ wire VDD1V8;
+ wire VDD3V3;
+ wire VSS;
+
+ assign VDD3V3 = power1;
+ assign VDD1V8 = power2;
assign VSS = 1'b0;
- assign VDD1V8 = 1'b1;
- assign VDD3V3 = 1'b1;
caravel uut (
.vddio (VDD3V3),
diff --git a/verilog/dv/caravel/user_proj_example/la_test2/la_test2_tb.v b/verilog/dv/caravel/user_proj_example/la_test2/la_test2_tb.v
index fff6e2e..54b671f 100644
--- a/verilog/dv/caravel/user_proj_example/la_test2/la_test2_tb.v
+++ b/verilog/dv/caravel/user_proj_example/la_test2/la_test2_tb.v
@@ -7,7 +7,7 @@
module la_test2_tb;
reg clock;
reg RSTB;
- wire SDO;
+ reg power1, power2;
wire gpio;
wire [36:0] mprj_io;
@@ -51,18 +51,27 @@
#2000;
end
- wire VDD1V8;
- wire VDD3V3;
- wire VSS;
-
+ initial begin // Power-up sequence
+ power1 <= 1'b0;
+ power2 <= 1'b0;
+ #200;
+ power1 <= 1'b1;
+ #200;
+ power2 <= 1'b1;
+ end
+
wire flash_csb;
wire flash_clk;
wire flash_io0;
wire flash_io1;
+ wire VDD1V8;
+ wire VDD3V3;
+ wire VSS;
+
+ assign VDD3V3 = power1;
+ assign VDD1V8 = power2;
assign VSS = 1'b0;
- assign VDD1V8 = 1'b1;
- assign VDD3V3 = 1'b1;
caravel uut (
.vddio (VDD3V3),
diff --git a/verilog/rtl/caravel.v b/verilog/rtl/caravel.v
index 10bcde8..433dd91 100644
--- a/verilog/rtl/caravel.v
+++ b/verilog/rtl/caravel.v
@@ -390,12 +390,11 @@
wire [31:0] mprj_dat_o_user;
mgmt_protect mgmt_buffers (
- `ifdef LVS
.vccd(vccd),
.vssd(vssd),
.vccd1(vccd1),
.vssd1(vssd1),
- `endif
+
.caravel_clk(caravel_clk),
.caravel_clk2(caravel_clk2),
.caravel_rstn(caravel_rstn),
@@ -429,16 +428,15 @@
.IO_PADS(`MPRJ_IO_PADS),
.PWR_PADS(`MPRJ_PWR_PADS)
) mprj (
- `ifdef LVS
- vdda1, // User area 1 3.3V power
- vdda2, // User area 2 3.3V power
- vssa1, // User area 1 analog ground
- vssa2, // User area 2 analog ground
- vccd1, // User area 1 1.8V power
- vccd2, // User area 2 1.8V power
- vssa1, // User area 1 digital ground
- vssa2, // User area 2 digital ground
- `endif
+ .vdda1(vdda1), // User area 1 3.3V power
+ .vdda2(vdda2), // User area 2 3.3V power
+ .vssa1(vssa1), // User area 1 analog ground
+ .vssa2(vssa2), // User area 2 analog ground
+ .vccd1(vccd1), // User area 1 1.8V power
+ .vccd2(vccd2), // User area 2 1.8V power
+ .vssd1(vssd1), // User area 1 digital ground
+ .vssd2(vssd2), // User area 2 digital ground
+
.wb_clk_i(mprj_clock),
.wb_rst_i(!mprj_resetn),
// MGMT SoC Wishbone Slave
@@ -564,13 +562,11 @@
);
sky130_fd_sc_hvl__lsbufhv2lv porb_level (
- `ifdef LVS
- .vpwr(vddio),
- .vpb(vddio),
- .lvpwr(vccd),
- .vnb(vssio),
- .vgnd(vssio),
- `endif
+ .VPWR(vddio),
+ .VPB(vddio),
+ .LVPWR(vccd),
+ .VNB(vssio),
+ .VGND(vssio),
.A(porb_h),
.X(porb_l)
);
@@ -578,6 +574,8 @@
user_id_programming #(
.USER_PROJECT_ID(USER_PROJECT_ID)
) user_id_value (
+ .vdd1v8(vccd),
+ .vss(vssd),
.mask_rev(mask_rev)
);
@@ -590,13 +588,11 @@
// XRES (chip input pin reset) reset level converter
sky130_fd_sc_hvl__lsbufhv2lv rstb_level (
- `ifdef LVS
- .vpwr(vddio),
- .vpb(vddio),
- .lvpwr(vdd1v8),
- .vnb(vssio),
- .vgnd(vssio),
- `endif
+ .VPWR(vddio),
+ .VPB(vddio),
+ .LVPWR(vccd),
+ .VNB(vssio),
+ .VGND(vssio),
.A(rstb_h),
.X(rstb_l)
);
diff --git a/verilog/rtl/gpio_control_block.v b/verilog/rtl/gpio_control_block.v
index ab08e46..681da94 100644
--- a/verilog/rtl/gpio_control_block.v
+++ b/verilog/rtl/gpio_control_block.v
@@ -208,23 +208,19 @@
/* Buffer user_gpio_in with an enable that is set by the user domain vccd */
sky130_fd_sc_hd__conb_1 gpio_logic_high (
- `ifdef LVS
.VPWR(vccd1),
.VGND(vssd1),
.VPB(vccd1),
.VNB(vssd1),
- `endif
.HI(gpio_logic1),
.LO()
);
sky130_fd_sc_hd__einvp_8 gpio_in_buf (
- `ifdef LVS
.VPWR(vccd),
.VGND(vssd),
.VPB(vccd),
.VNB(vssd),
- `endif
.Z(user_gpio_in),
.A(~gpio_in_unbuf),
.TE(gpio_logic1)
diff --git a/verilog/rtl/mgmt_protect.v b/verilog/rtl/mgmt_protect.v
index 1b04731..8865ee4 100644
--- a/verilog/rtl/mgmt_protect.v
+++ b/verilog/rtl/mgmt_protect.v
@@ -14,12 +14,10 @@
/*----------------------------------------------------------------------*/
module mgmt_protect (
-`ifdef LVS
inout vccd,
inout vssd,
inout vccd1,
inout vssd1,
-`endif
input caravel_clk,
input caravel_clk2,
@@ -48,119 +46,99 @@
wire [73:0] mprj_logic1;
sky130_fd_sc_hd__conb_1 mprj_logic_high [73:0] (
- `ifdef LVS
.VPWR(vccd1),
.VGND(vssd1),
.VPB(vccd1),
.VNB(vssd1),
- `endif
.HI(mprj_logic1),
.LO()
);
sky130_fd_sc_hd__einvp_8 mprj_rstn_buf (
- `ifdef LVS
.VPWR(vccd),
.VGND(vssd),
.VPB(vccd),
.VNB(vssd),
- `endif
.Z(user_resetn),
.A(~caravel_rstn),
.TE(mprj_logic1[0])
);
sky130_fd_sc_hd__einvp_8 mprj_clk_buf (
- `ifdef LVS
.VPWR(vccd),
.VGND(vssd),
.VPB(vccd),
.VNB(vssd),
- `endif
.Z(user_clock),
.A(~caravel_clk),
.TE(mprj_logic1[1])
);
sky130_fd_sc_hd__einvp_8 mprj_clk2_buf (
- `ifdef LVS
.VPWR(vccd),
.VGND(vssd),
.VPB(vccd),
.VNB(vssd),
- `endif
.Z(user_clock2),
.A(~caravel_clk2),
.TE(mprj_logic1[2])
);
sky130_fd_sc_hd__einvp_8 mprj_cyc_buf (
- `ifdef LVS
.VPWR(vccd),
.VGND(vssd),
.VPB(vccd),
.VNB(vssd),
- `endif
.Z(mprj_cyc_o_user),
.A(~mprj_cyc_o_core),
.TE(mprj_logic1[3])
);
sky130_fd_sc_hd__einvp_8 mprj_stb_buf (
- `ifdef LVS
.VPWR(vccd),
.VGND(vssd),
.VPB(vccd),
.VNB(vssd),
- `endif
.Z(mprj_stb_o_user),
.A(~mprj_stb_o_core),
.TE(mprj_logic1[4])
);
sky130_fd_sc_hd__einvp_8 mprj_we_buf (
- `ifdef LVS
.VPWR(vccd),
.VGND(vssd),
.VPB(vccd),
.VNB(vssd),
- `endif
.Z(mprj_we_o_user),
.A(~mprj_we_o_core),
.TE(mprj_logic1[5])
);
sky130_fd_sc_hd__einvp_8 mprj_sel_buf [3:0] (
- `ifdef LVS
.VPWR(vccd),
.VGND(vssd),
.VPB(vccd),
.VNB(vssd),
- `endif
.Z(mprj_sel_o_user),
.A(~mprj_sel_o_core),
.TE(mprj_logic1[9:6])
);
sky130_fd_sc_hd__einvp_8 mprj_adr_buf [31:0] (
- `ifdef LVS
.VPWR(vccd),
.VGND(vssd),
.VPB(vccd),
.VNB(vssd),
- `endif
.Z(mprj_adr_o_user),
.A(~mprj_adr_o_core),
.TE(mprj_logic1[41:10])
);
sky130_fd_sc_hd__einvp_8 mprj_dat_buf [31:0] (
- `ifdef LVS
.VPWR(vccd),
.VGND(vssd),
.VPB(vccd),
.VNB(vssd),
- `endif
.Z(mprj_dat_o_user),
.A(~mprj_dat_o_core),
.TE(mprj_logic1[73:42])
@@ -173,12 +151,10 @@
/* power-down of vccd1. */
sky130_fd_sc_hd__einvp_8 la_buf [127:0] (
- `ifdef LVS
.VPWR(vccd),
.VGND(vssd),
.VPB(vccd),
.VNB(vssd),
- `endif
.Z(la_data_in_mprj),
.A(~la_output_core),
.TE(~la_oen)
diff --git a/verilog/rtl/pads.v b/verilog/rtl/pads.v
index e427b08..9ce690a 100644
--- a/verilog/rtl/pads.v
+++ b/verilog/rtl/pads.v
@@ -38,7 +38,7 @@
.VDDIO(vddio),\
.VCCD(vccd),\
.VSSIO(vssio),\
- .VSSD(vssa),\
+ .VSSD(vssd),\
.VSSIO_Q(vssio_q),
`else
`define USER1_ABUTMENT_PINS
@@ -64,30 +64,30 @@
`ifndef TOP_ROUTING \
.PAD(X), \
`endif \
- .OUT(vssa), \
+ .OUT(vssd), \
.OE_N(vccd), \
- .HLD_H_N(vddio), \
+ .HLD_H_N(vddio), \
.ENABLE_H(porb_h), \
.ENABLE_INP_H(loop_``X), \
.ENABLE_VDDA_H(porb_h), \
.ENABLE_VSWITCH_H(vssa), \
.ENABLE_VDDIO(vccd), \
.INP_DIS(por), \
- .IB_MODE_SEL(vssa), \
- .VTRIP_SEL(vssa), \
- .SLOW(vssa), \
- .HLD_OVR(vssa), \
- .ANALOG_EN(vssa), \
- .ANALOG_SEL(vssa), \
- .ANALOG_POL(vssa), \
- .DM({vssa, vssa, vccd}), \
+ .IB_MODE_SEL(vssd), \
+ .VTRIP_SEL(vssd), \
+ .SLOW(vssd), \
+ .HLD_OVR(vssd), \
+ .ANALOG_EN(vssd), \
+ .ANALOG_SEL(vssd), \
+ .ANALOG_POL(vssd), \
+ .DM({vssd, vssd, vccd}), \
.PAD_A_NOESD_H(), \
.PAD_A_ESD_0_H(), \
.PAD_A_ESD_1_H(), \
.IN(Y), \
.IN_H(), \
.TIE_HI_ESD(), \
- .TIE_LO_ESD(loop_``X) )
+ .TIE_LO_ESD(loop_``X) )
`define OUTPUT_PAD(X,Y,INPUT_DIS,OUT_EN_N) \
wire loop_``X; \
@@ -105,14 +105,14 @@
.ENABLE_VSWITCH_H(vssa), \
.ENABLE_VDDIO(vccd), \
.INP_DIS(INPUT_DIS), \
- .IB_MODE_SEL(vssa), \
- .VTRIP_SEL(vssa), \
- .SLOW(vssa), \
- .HLD_OVR(vssa), \
- .ANALOG_EN(vssa), \
- .ANALOG_SEL(vssa), \
- .ANALOG_POL(vssa), \
- .DM({vccd, vccd, vssa}), \
+ .IB_MODE_SEL(vssd), \
+ .VTRIP_SEL(vssd), \
+ .SLOW(vssd), \
+ .HLD_OVR(vssd), \
+ .ANALOG_EN(vssd), \
+ .ANALOG_SEL(vssd), \
+ .ANALOG_POL(vssd), \
+ .DM({vccd, vccd, vssd}), \
.PAD_A_NOESD_H(), \
.PAD_A_ESD_0_H(), \
.PAD_A_ESD_1_H(), \
@@ -136,13 +136,13 @@
.ENABLE_VSWITCH_H(vssa), \
.ENABLE_VDDIO(vccd), \
.INP_DIS(INPUT_DIS), \
- .IB_MODE_SEL(vssa), \
- .VTRIP_SEL(vssa), \
- .SLOW(vssa), \
- .HLD_OVR(vssa), \
- .ANALOG_EN(vssa), \
- .ANALOG_SEL(vssa), \
- .ANALOG_POL(vssa), \
+ .IB_MODE_SEL(vssd), \
+ .VTRIP_SEL(vssd), \
+ .SLOW(vssd), \
+ .HLD_OVR(vssd), \
+ .ANALOG_EN(vssd), \
+ .ANALOG_SEL(vssd), \
+ .ANALOG_POL(vssd), \
.DM(MODE), \
.PAD_A_NOESD_H(), \
.PAD_A_ESD_0_H(), \
diff --git a/verilog/rtl/simple_por.v b/verilog/rtl/simple_por.v
index 4b92a55..f308fbf 100644
--- a/verilog/rtl/simple_por.v
+++ b/verilog/rtl/simple_por.v
@@ -1,3 +1,5 @@
+`timescale 1 ns / 1 ps
+
module simple_por(
input vdd3v3,
input vss,
@@ -12,7 +14,7 @@
// two schmitt triggers for strong hysteresis/glitch tolerance.
initial begin
- inode <= 1'b0;
+ inode <= 1'b0;
end
// Emulate current source on capacitor as a 500ns delay either up or
@@ -28,23 +30,19 @@
// Instantiate two shmitt trigger buffers in series
sky130_fd_sc_hvl__schmittbuf hystbuf1 (
-`ifdef LVS
.VPWR(vdd3v3),
.VGND(vss),
.VPB(vdd3v3),
.VNB(vss),
-`endif
.A(inode),
.X(mid)
);
sky130_fd_sc_hvl__schmittbuf hystbuf2 (
-`ifdef LVS
.VPWR(vdd3v3),
.VGND(vss),
.VPB(vdd3v3),
.VNB(vss),
-`endif
.A(mid),
.X(porb_h)
);
diff --git a/verilog/rtl/user_id_programming.v b/verilog/rtl/user_id_programming.v
index 30f5eb8..5133605 100644
--- a/verilog/rtl/user_id_programming.v
+++ b/verilog/rtl/user_id_programming.v
@@ -6,6 +6,8 @@
module user_id_programming #(
parameter [ 0:0] USER_PROJECT_ID = 32'h0
) (
+ inout vdd1v8,
+ inout vss,
output [31:0] mask_rev
);
wire [31:0] mask_rev;
@@ -15,12 +17,10 @@
// For the mask revision input, use an array of digital constant logic cells
sky130_fd_sc_hd__conb_1 mask_rev_value [31:0] (
- `ifdef LVS
.VPWR(vdd1v8),
.VPB(vdd1v8),
.VNB(vss),
.VGND(vss),
- `endif
.HI(user_proj_id_high),
.LO(user_proj_id_low)
);
diff --git a/verilog/rtl/user_proj_example.v b/verilog/rtl/user_proj_example.v
index 4c2a6b9..1edc2dc 100644
--- a/verilog/rtl/user_proj_example.v
+++ b/verilog/rtl/user_proj_example.v
@@ -24,7 +24,6 @@
parameter PWR_PADS = 4,
parameter BITS = 32
)(
-`ifdef LVS
inout vdda1, // User area 1 3.3V supply
inout vdda2, // User area 2 3.3V supply
inout vssa1, // User area 1 analog ground
@@ -33,7 +32,6 @@
inout vccd2, // User area 2 1.8v supply
inout vssd1, // User area 1 digital ground
inout vssd2, // User area 2 digital ground
-`endif
// Wishbone Slave ports (WB MI A)
input wb_clk_i,
