| commit | d435614fa36cde3c483c7ab771170a446dedc9ff | [log] [tgz] |
|---|---|---|
| author | Dan Rodrigues <danrr.gh.oss@gmail.com> | Fri Dec 18 12:04:24 2020 +1100 |
| committer | Dan Rodrigues <danrr.gh.oss@gmail.com> | Fri Dec 18 12:04:24 2020 +1100 |
| tree | d0fe7f3c5cca139d378482ec9aa862d340666d20 | |
| parent | 00258e10613f1157c667cddad652843e52acdf77 [diff] |
Default to GL sim
diff --git a/verilog/dv/vdp_lite/core.mk b/verilog/dv/vdp_lite/core.mk index 8b077a1..5dfdda0 100644 --- a/verilog/dv/vdp_lite/core.mk +++ b/verilog/dv/vdp_lite/core.mk
@@ -16,7 +16,7 @@ # Enables the verilog/gl/vdp_lite_user_proj.v instead # This is taken from the *.powered.lvs generated by the openlane flow -GL_SIM ?= 0 +GL_SIM ?= 1 ###