Renamed lvs guard to use_power_pins
- Also, added guard to the cells in the custom memory
- dropped DLVS from the dv Makefiles
diff --git a/verilog/rtl/housekeeping_spi.v b/verilog/rtl/housekeeping_spi.v
index 2942b27..cc8d5d0 100644
--- a/verilog/rtl/housekeeping_spi.v
+++ b/verilog/rtl/housekeeping_spi.v
@@ -48,7 +48,7 @@
//------------------------------------------------------------
module housekeeping_spi(
-`ifdef LVS
+`ifdef USE_POWER_PINS
vdd, vss,
`endif
RSTB, SCK, SDI, CSB, SDO, sdo_enb,
@@ -61,7 +61,7 @@
pass_thru_user_sdi, pass_thru_user_sdo
);
-`ifdef LVS
+`ifdef USE_POWER_PINS
inout vdd; // 3.3V supply
inout vss; // common ground
`endif
