Add forgotten USE_POWER_PINS to user project
Seems to cause LVS issues on the wrapper
diff --git a/verilog/rtl/vdp_lite_user_proj/vdp_lite_user_proj.v b/verilog/rtl/vdp_lite_user_proj/vdp_lite_user_proj.v
index 141793c..cd5b9ab 100644
--- a/verilog/rtl/vdp_lite_user_proj/vdp_lite_user_proj.v
+++ b/verilog/rtl/vdp_lite_user_proj/vdp_lite_user_proj.v
@@ -24,6 +24,7 @@
module vdp_lite_user_proj #(
parameter VRAM_TYPE = "MINIMAL"
) (
+`ifdef USE_POWER_PINS
inout vdda1, // User area 1 3.3V supply
inout vdda2, // User area 2 3.3V supply
inout vssa1, // User area 1 analog ground
@@ -32,6 +33,7 @@
inout vccd2, // User area 2 1.8v supply
inout vssd1, // User area 1 digital ground
inout vssd2, // User area 2 digital ground
+`endif
// Wishbone Slave ports (WB MI A)
input wb_clk_i,
