"Emulate" the substrate in mgmt_protect_hv
- which is shorting grounds together
diff --git a/verilog/rtl/manifest b/verilog/rtl/manifest
index 7c2753a..a79b82a 100644
--- a/verilog/rtl/manifest
+++ b/verilog/rtl/manifest
@@ -1,22 +1,22 @@
-d328f88dd48e015bbaa95e0d7c88954343cc5632 DFFRAM.v
-dab57f3c5464ce3354219840dae589a3fcd27135 DFFRAMBB.v
-c39b4f6a67a044aec105ca83ef1eb6d3f2b06028 caravel.v
b2feeb2a098894d5d731a5b011858a471e855d73 caravel_clocking.v
+c39b4f6a67a044aec105ca83ef1eb6d3f2b06028 caravel.v
38d2c674ea1f696bf2c9deaeee5f9b044f2445fb chip_io.v
d772308bd2a72121d7ed9dcdd40c8e6cbbe4b43c clock_div.v
f937b52e53d45bdbe41bcbd07c65b41104c21756 convert_gpio_sigs.v
a16f89c8efa638eab43641ab7047bb8eeedd6fa6 counter_timer_high.v
d8eab2f4cef158e3c7800778ffc2367ab4abe130 counter_timer_low.v
-fff2d08e49701312c2ebd6714b7425baf83f3d35 digital_pll.v
+dab57f3c5464ce3354219840dae589a3fcd27135 DFFRAMBB.v
+d328f88dd48e015bbaa95e0d7c88954343cc5632 DFFRAM.v
ce49f9af199b5f16d2c39c417d58e5890bc7bab2 digital_pll_controller.v
+fff2d08e49701312c2ebd6714b7425baf83f3d35 digital_pll.v
3588d4fbd0bd941be329ff0697ac2585e9036186 gpio_control_block.v
57554b3586f306944b31718a8c52526fa9a8a574 gpio_wb.v
baf3aba29655ca7021398ddc3f68be81eff0fa0c housekeeping_spi.v
0544035d9f2bfc52ebcb3220a21f29e98a3784b4 la_wb.v
ff3e65a783f3807340e25efac9207787d39fb6cd mem_wb.v
65feb79043201d3609307a3dd5af4e75cc26e81b mgmt_core.v
+3b1ff20593bc386d13f5e2cf1571f08121889957 mgmt_protect_hv.v
4d42909e102c472504739bc37559c6a34fd85ae1 mgmt_protect.v
-f656dadb49cb97a46aada3d37a86a12f565e6e9e mgmt_protect_hv.v
20a482029168de93693a92ce03c00ec16e7b4776 mgmt_soc.v
489b31e48e0ba327b6a70748fee664406c58f7a0 mprj2_logic_high.v
93eb7aa0f8489715145ff0870737fecf8be1fa8c mprj_ctrl.v
@@ -31,7 +31,7 @@
ec5fa62d935e1139de104b9201740020fdea4a17 sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.v
b77b7eb6ae4b253abf157a01f6f349719a81628c spimemio.v
3b4c3de623f8af0f0780f1e5b0f2217ef6406a2f sram_1rw1r_32_256_8_sky130.v
-8dea2030f1f59fc58ce50d943c395b8041ff1fb3 storage.v
7e8d789570ed224df49cf61f69593cc738790a5d storage_bridge_wb.v
+8dea2030f1f59fc58ce50d943c395b8041ff1fb3 storage.v
5e314e94a13d7291117123395ae088e1d17cf487 sysctrl.v
e6246df6bbf0860a331b3547d64f7d235b0eca9a wb_intercon.v
diff --git a/verilog/rtl/mgmt_protect_hv.v b/verilog/rtl/mgmt_protect_hv.v
index c1ecd0b..23d9cf6 100644
--- a/verilog/rtl/mgmt_protect_hv.v
+++ b/verilog/rtl/mgmt_protect_hv.v
@@ -42,6 +42,13 @@
wire mprj_vdd_logic1_h;
wire mprj2_vdd_logic1_h;
+`ifdef USE_POWER_PINS
+ // This is to emulate the substrate shorting grounds together for LVS
+ // purposes
+ assign vssa2 = vssa1;
+ assign vssa1 = vssd;
+`endif
+
// Logic high in the VDDA (3.3V) domains
sky130_fd_sc_hvl__conb_1 mprj_logic_high_hvl (
@@ -91,6 +98,6 @@
.X(mprj2_vdd_logic1),
.A(mprj2_vdd_logic1_h)
);
-
endmodule
+
`default_nettype wire
