commit 21a9aac19537bf1a1e90e356d67a6b0e05bf1091
author Tim Edwards <tim@opencircuitdesign.com> Mon Oct 12 22:05:18 2020 -0400
committer Tim Edwards <tim@opencircuitdesign.com> Mon Oct 12 22:05:18 2020 -0400
tree 96dea37f5673c8e442119bd5fe9ec8416cd5d51c
parent e2ef673adf739e8eec22d45574b754a0269b14e3

Testbench simulations are now all working correctly with the pre-release
version of sky130_fd_io.

verilog/rtl/simple_por.v

diff --git a/verilog/rtl/simple_por.v b/verilog/rtl/simple_por.v
index 4b92a55..f308fbf 100644
--- a/verilog/rtl/simple_por.v
+++ b/verilog/rtl/simple_por.v
@@ -1,3 +1,5 @@
+`timescale 1 ns / 1 ps
+
 module simple_por(
     input vdd3v3,
     input vss,
@@ -12,7 +14,7 @@
     // two schmitt triggers for strong hysteresis/glitch tolerance.
 
     initial begin
-	inode <= 1'b0;
+	inode <= 1'b0; 
     end 
 
     // Emulate current source on capacitor as a 500ns delay either up or
@@ -28,23 +30,19 @@
     // Instantiate two shmitt trigger buffers in series
 
     sky130_fd_sc_hvl__schmittbuf hystbuf1 (
-`ifdef LVS
 	.VPWR(vdd3v3),
 	.VGND(vss),
 	.VPB(vdd3v3),
 	.VNB(vss),
-`endif
 	.A(inode),
 	.X(mid)
     );
 
     sky130_fd_sc_hvl__schmittbuf hystbuf2 (
-`ifdef LVS
 	.VPWR(vdd3v3),
 	.VGND(vss),
 	.VPB(vdd3v3),
 	.VNB(vss),
-`endif
 	.A(mid),
 	.X(porb_h)
     );