add default nettype none
diff --git a/verilog/gl/user_proj_example.v b/verilog/gl/user_proj_example.v
index a80278b..74638c0 100644
--- a/verilog/gl/user_proj_example.v
+++ b/verilog/gl/user_proj_example.v
@@ -1,3 +1,4 @@
+`default_nettype none
 /* Generated by Yosys 0.9+3621 (git sha1 84e9fa7, gcc 8.3.1 -fPIC -Os) */
 
 module user_proj_example(vccd1, vccd2, vdda1, vdda2, vssa1, vssa2, vssd1, vssd2, wb_clk_i, wb_rst_i, wbs_ack_o, wbs_cyc_i, wbs_stb_i, wbs_we_i, VPWR, VGND, io_in, io_oeb, io_out, la_data_in, la_data_out, la_oen, wbs_adr_i, wbs_dat_i, wbs_dat_o, wbs_sel_i);