[DOC] Add more information on tooling for MPW #1
diff --git a/README.md b/README.md
index 198a4b2..2c77d56 100644
--- a/README.md
+++ b/README.md
@@ -6,8 +6,11 @@
<img src="/doc/ciic_harness.png" width="75%" height="75%">
</p>
+
## Getting Started:
+* For information on tooling and versioning, please refer to [this][1].
+
Start by cloning the repo and uncompressing the files.
```bash
git clone https://github.com/efabless/caravel.git
@@ -117,3 +120,4 @@
3. Configure the User Project I/O pads as o/p. Use the Chip LA to control the clock source and reset signals and observe the counter value for five clock cylcles: [LA_Test2](verilog/dv/caravel/user_proj_example/la_test2).
[0]: openlane/README.md
+[1]: mpw-one-a.md
