Vast and substantial changes: Removed the old GPIO control with the new one
that implements a shift register around the perimeter of the chip, to control
most aspects of each GPIO pad locally to avoid excessive wiring. Added modules
for the metal-programmed user ID, two counter-timers, and a general-purpose SPI
master. The SPI master can be internally directly connected to the SPI slave,
so the processor can access the housekeeping SPI in the same way as an external
host. Most signals other than 1 GPIO pin and the SPI flash controller pins were
remapped to pads in the user area, where they are active on startup and until
they are programmed for user use from the management processor. There are
several known syntax issues that need to be fixed; this is a work in progress.
diff --git a/verilog/rtl/caravel_clkrst.v b/verilog/rtl/caravel_clkrst.v
new file mode 100644
index 0000000..af40b8f
--- /dev/null
+++ b/verilog/rtl/caravel_clkrst.v
@@ -0,0 +1,35 @@
+module caravel_clkrst(
+`ifdef LVS
+ input vdd1v8,
+ input vss,
+`endif
+ input ext_clk_sel,
+ input ext_clk,
+ input pll_clk,
+ input resetb,
+ input ext_reset, // NOTE: positive sense reset
+ output core_clk,
+ output resetb_sync
+);
+
+ // Clock assignment (to do: make this glitch-free)
+ assign core_clk = (ext_clk_sel == 1'b1) ? ext_clk : pll_clk;
+
+ // Reset assignment. "reset" comes from POR, while "ext_reset"
+ // comes from standalone SPI (and is normally zero unless
+ // activated from the SPI).
+
+ // Staged-delay reset
+ reg [2:0] reset_delay;
+
+ always @(posedge core_clk or negedge resetb) begin
+ if (resetb == 1'b0) begin
+ reset_delay <= 3'b111;
+ end else begin
+ reset_delay <= {1'b0, reset_delay[2:1]};
+ end
+ end
+
+ assign resetb_sync = ~(reset_delay[0] | ext_reset);
+
+endmodule
