commit fc7e6ae4b87cf45a6f4a19cc980013efee9b2c13
author Mohamed Shalan <mshalan@aucegypt.edu> Wed Jan 20 15:14:01 2021 +0200
committer Mohamed Shalan <mshalan@aucegypt.edu> Wed Jan 20 15:14:01 2021 +0200
tree 0e0d2ad8bf71955df81452320e7366feea43d48e
parent 0565c08c1c1adaad2893fe2ba11aed657f0aff37

Fixed a typo

verilog/rtl/RAM_6Kx32.v

diff --git a/verilog/rtl/RAM_6Kx32.v b/verilog/rtl/RAM_6Kx32.v
index 1b65721..c054ec1 100644
--- a/verilog/rtl/RAM_6Kx32.v
+++ b/verilog/rtl/RAM_6Kx32.v
@@ -48,9 +48,9 @@
     endgenerate 
     
     // The block decoder
-    assign _EN_[0] = A[12:10] == 3'd0;
-    assign _EN_[1] = A[12:10] == 3'd1;
-    assign _EN_[2] = A[12:10] == 3'd2;
+    assign _EN_[0] = A[12:11] == 2'd0;
+    assign _EN_[1] = A[12:11] == 2'd1;
+    assign _EN_[2] = A[12:11] == 2'd2;
     
     // Output Data multiplexor
     assign Do_pre = (A[12:11] == 2'd0) ? _Do_[0] :