commit e2a3da9ae85991c46eb7dbe972aa1302e7f091ad
author Mohamed Shalan <mshalan@aucegypt.edu> Wed Jan 20 15:56:20 2021 +0200
committer Mohamed Shalan <mshalan@aucegypt.edu> Wed Jan 20 15:56:20 2021 +0200
tree af12dbe629af3dc1b41cf7cc975b5643ef7a3709
parent fc7e6ae4b87cf45a6f4a19cc980013efee9b2c13

Changed the number of columns to 4

verilog/rtl/RAM_2x4KB.v

diff --git a/verilog/rtl/RAM_2x4KB.v b/verilog/rtl/RAM_2x4KB.v
index a218d2a..41d5a2e 100644
--- a/verilog/rtl/RAM_2x4KB.v
+++ b/verilog/rtl/RAM_2x4KB.v
@@ -15,7 +15,7 @@
 
     wire    [31:0]  Do_0, Do_1;
 
-    DFFRAM_4KB #(.COLS(2)) RAM0 (
+    DFFRAM_4KB #(.COLS(4)) RAM0 (
                 .CLK(CLK),
                 .WE(WE),
                 .EN(~A[10]),
@@ -24,7 +24,7 @@
                 .A(A[9:0])
             );
     
-    DFFRAM_4KB #(.COLS(2)) RAM1 (
+    DFFRAM_4KB #(.COLS(4)) RAM1 (
                 .CLK(CLK),
                 .WE(WE),
                 .EN(A[10]),