update configs
diff --git a/openlane/RAM_6Kx32/config.tcl b/openlane/RAM_6Kx32/config.tcl
index 18e0f66..72270a5 100644
--- a/openlane/RAM_6Kx32/config.tcl
+++ b/openlane/RAM_6Kx32/config.tcl
@@ -9,7 +9,8 @@
# Change if needed
set ::env(VERILOG_FILES) "\
- $script_dir/../../verilog/rtl/DFFRAM.v \
+ $script_dir/../../verilog/rtl/defines.v \
+ $script_dir/../../verilog/rtl/DFFRAM_4KB.v \
$script_dir/../../verilog/rtl/DFFRAMBB.v \
$script_dir/../../verilog/rtl/RAM_6Kx32.v"
diff --git a/openlane/user_project_wrapper/config.tcl b/openlane/user_project_wrapper/config.tcl
index f74d9f1..e5c389a 100644
--- a/openlane/user_project_wrapper/config.tcl
+++ b/openlane/user_project_wrapper/config.tcl
@@ -52,12 +52,14 @@
set ::env(SYNTH_READ_BLACKBOX_LIB) 1
set ::env(VERILOG_FILES) "\
+ $script_dir/../../verilog/rtl/defines.v
$script_dir/../../verilog/rtl/user_project_wrapper.v
$script_dir/../../verilog/rtl/Caravel_RAM_24KB_wb.v
$script_dir/../../verilog/rtl/Caravel_RAM_24KB.v
$script_dir/../../verilog/rtl/DFFRAMBB.v"
set ::env(VERILOG_FILES_BLACKBOX) "\
+ $script_dir/../../verilog/rtl/defines.v
$script_dir/../../verilog/rtl/DFFRAM.v
$script_dir/../../verilog/rtl/RAM_6Kx32.v"
diff --git a/openlane/user_project_wrapper/interactive.tcl b/openlane/user_project_wrapper/interactive.tcl
index 8e2dd01..15062ee 100644
--- a/openlane/user_project_wrapper/interactive.tcl
+++ b/openlane/user_project_wrapper/interactive.tcl
@@ -82,6 +82,8 @@
save_views -lef_path $::env(magic_result_file_tag).lef \
-def_path $::env(tritonRoute_result_file_tag).def \
-gds_path $::env(magic_result_file_tag).gds \
+ -spice_path $::env(magic_result_file_tag).spice \
+ -verilog_path $::env(CURRENT_NETLIST) \
-mag_path $::env(magic_result_file_tag).mag \
-save_path $save_path \
-tag $::env(RUN_TAG)
