RTL of DFFRAM updated
diff --git a/verilog/rtl/DFFRAM.v b/verilog/rtl/DFFRAM.v
index 7011bb9..73ad0ad 100644
--- a/verilog/rtl/DFFRAM.v
+++ b/verilog/rtl/DFFRAM.v
@@ -10,7 +10,7 @@
`timescale 1ns / 1ps
`default_nettype none
-module DFFRAM_4kb #( parameter COLS=4)
+module DFFRAM #( parameter COLS=4, USE_LATCH=0)
(
CLK,
WE,
@@ -31,10 +31,13 @@
wire [31:0] Do_pre;
wire [COLS-1:0] EN_lines;
+ wire [9:8] A_buf;
+
generate
genvar i;
for (i=0; i<COLS; i=i+1) begin : COLUMN
- DFFRAM_COL4 RAMCOLS ( .CLK(CLK),
+ DFFRAM_COL4 #(.USE_LATCH(USE_LATCH))
+ RAMCOLS ( .CLK(CLK),
.WE(WE),
.EN(EN_lines[i]),
.Di(Di),
@@ -43,64 +46,13 @@
);
end
if(COLS==4) begin
- MUX4x1_32 MUX ( .A0(DOUT[0]), .A1(DOUT[1]), .A2(DOUT[2]), .A3(DOUT[3]), .S(A[9:8]), .X(Do_pre) );
+ sky130_fd_sc_hd__clkbuf_8 ABUF[1:0] (.X(A_buf[9:8]), .A(A[9:8]) );
+ MUX4x1_32 MUX ( .A0(DOUT[0]), .A1(DOUT[1]), .A2(DOUT[2]), .A3(DOUT[3]), .S(A_buf[9:8]), .X(Do_pre) );
DEC2x4 DEC ( .EN(EN), .A(A[9:8]), .SEL(EN_lines) );
end
else if(COLS==2) begin
- MUX2x1_32 MUX ( .A0(DOUT[0]), .A1(DOUT[1]), .S(A[8]), .X(Do_pre) );
- //sky130_fd_sc_hd__inv_4 DEC0 ( .Y(EN_lines[0]), .A(A[8]) );
- //sky130_fd_sc_hd__clkbuf_4 DEC1 (.X(EN_lines[1]), .A(A[8]) );
- DEC1x2 DEC ( .EN(EN), .A(A[8]), .SEL(EN_lines[1:0]) );
-
- end
- else begin
- PASS MUX ( .A(DOUT[0]), .X(Do_pre) );
- sky130_fd_sc_hd__clkbuf_4 ENBUF (.X(EN_lines[0]), .A(EN) );
- end
- endgenerate
-
- sky130_fd_sc_hd__clkbuf_4 DOBUF[31:0] (.X(Do), .A(Do_pre));
-
-endmodule
-
-module DFFRAM_2kb #( parameter COLS=4)
-(
- CLK,
- WE,
- EN,
- Di,
- Do,
- A
-);
-
- input CLK;
- input [3:0] WE;
- input EN;
- input [31:0] Di;
- output [31:0] Do;
- input [7+$clog2(COLS):0] A;
-
- wire [31:0] DOUT [COLS-1:0];
- wire [31:0] Do_pre;
- wire [COLS-1:0] EN_lines;
-
- generate
- genvar i;
- for (i=0; i<COLS; i=i+1) begin : COLUMN
- DFFRAM_COL4 RAMCOLS ( .CLK(CLK),
- .WE(WE),
- .EN(EN_lines[i]),
- .Di(Di),
- .Do(DOUT[i]),
- .A(A[7:0])
- );
- end
- if(COLS==4) begin
- MUX4x1_32 MUX ( .A0(DOUT[0]), .A1(DOUT[1]), .A2(DOUT[2]), .A3(DOUT[3]), .S(A[9:8]), .X(Do_pre) );
- DEC2x4 DEC ( .EN(EN), .A(A[9:8]), .SEL(EN_lines) );
- end
- else if(COLS==2) begin
- MUX2x1_32 MUX ( .A0(DOUT[0]), .A1(DOUT[1]), .S(A[8]), .X(Do_pre) );
+ sky130_fd_sc_hd__clkbuf_8 ABUF[8:8] (.X(A_buf[8]), .A(A[8]) );
+ MUX2x1_32 MUX ( .A0(DOUT[0]), .A1(DOUT[1]), .S(A_buf[8]), .X(Do_pre) );
//sky130_fd_sc_hd__inv_4 DEC0 ( .Y(EN_lines[0]), .A(A[8]) );
//sky130_fd_sc_hd__clkbuf_4 DEC1 (.X(EN_lines[1]), .A(A[8]) );
DEC1x2 DEC ( .EN(EN), .A(A[8]), .SEL(EN_lines[1:0]) );
diff --git a/verilog/rtl/DFFRAMBB.v b/verilog/rtl/DFFRAMBB.v
index ad75f22..efa9725 100644
--- a/verilog/rtl/DFFRAMBB.v
+++ b/verilog/rtl/DFFRAMBB.v
@@ -40,8 +40,35 @@
endmodule
+module BYTE_LATCH (
+ input CLK,
+ input WE,
+ input SEL,
+ input [7:0] Di,
+ output [7:0] Do
+);
-module WORD32 (
+ wire [7:0] q_wire;
+ wire we_wire;
+ wire SEL_B;
+ wire GCLK;
+
+ sky130_fd_sc_hd__inv_1 INV(.Y(SEL_B), .A(SEL));
+ sky130_fd_sc_hd__and2_1 CGAND( .A(SEL), .B(WE), .X(we_wire) );
+ sky130_fd_sc_hd__dlclkp_1 CG( .CLK(CLK), .GCLK(GCLK), .GATE(we_wire) );
+
+ generate
+ genvar i;
+ for(i=0; i<8; i=i+1) begin : BIT
+ //sky130_fd_sc_hd__dfxtp_1 FF ( .D(Di[i]), .Q(q_wire[i]), .CLK(GCLK) );
+ sky130_fd_sc_hd__dlxtp_1 LATCH (.Q(q_wire[i]), .D(Di[i]), .GATE(GCLK) );
+ sky130_fd_sc_hd__ebufn_2 OBUF ( .A(q_wire[i]), .Z(Do[i]), .TE_B(SEL_B) );
+ end
+ endgenerate
+
+endmodule
+
+module WORD32 #(parameter USE_LATCH=1)(
input CLK,
input [3:0] WE,
input SEL,
@@ -49,11 +76,19 @@
output [31:0] Do
);
- BYTE B0 ( .CLK(CLK), .WE(WE[0]), .SEL(SEL), .Di(Di[7:0]), .Do(Do[7:0]) );
- BYTE B1 ( .CLK(CLK), .WE(WE[1]), .SEL(SEL), .Di(Di[15:8]), .Do(Do[15:8]) );
- BYTE B2 ( .CLK(CLK), .WE(WE[2]), .SEL(SEL), .Di(Di[23:16]), .Do(Do[23:16]) );
- BYTE B3 ( .CLK(CLK), .WE(WE[3]), .SEL(SEL), .Di(Di[31:24]), .Do(Do[31:24]) );
-
+ generate
+ if(USE_LATCH == 1) begin
+ BYTE_LATCH B0 ( .CLK(CLK), .WE(WE[0]), .SEL(SEL), .Di(Di[7:0]), .Do(Do[7:0]) );
+ BYTE_LATCH B1 ( .CLK(CLK), .WE(WE[1]), .SEL(SEL), .Di(Di[15:8]), .Do(Do[15:8]) );
+ BYTE_LATCH B2 ( .CLK(CLK), .WE(WE[2]), .SEL(SEL), .Di(Di[23:16]), .Do(Do[23:16]) );
+ BYTE_LATCH B3 ( .CLK(CLK), .WE(WE[3]), .SEL(SEL), .Di(Di[31:24]), .Do(Do[31:24]) );
+ end else begin
+ BYTE B0 ( .CLK(CLK), .WE(WE[0]), .SEL(SEL), .Di(Di[7:0]), .Do(Do[7:0]) );
+ BYTE B1 ( .CLK(CLK), .WE(WE[1]), .SEL(SEL), .Di(Di[15:8]), .Do(Do[15:8]) );
+ BYTE B2 ( .CLK(CLK), .WE(WE[2]), .SEL(SEL), .Di(Di[23:16]), .Do(Do[23:16]) );
+ BYTE B3 ( .CLK(CLK), .WE(WE[3]), .SEL(SEL), .Di(Di[31:24]), .Do(Do[31:24]) );
+ end
+ endgenerate
endmodule
module DEC1x2 (
@@ -134,7 +169,7 @@
assign X = A;
endmodule
-module SRAM64x32(
+module SRAM64x32 #(parameter USE_LATCH=0) (
input CLK,
input [3:0] WE,
input EN,
@@ -158,7 +193,7 @@
generate
genvar i;
for (i=0; i< 64; i=i+1) begin : WORD
- WORD32 W ( .CLK(CLK_buf), .WE(WE_buf), .SEL(SEL[i]), .Di(Di_buf), .Do(Do_pre) );
+ WORD32 #(.USE_LATCH(USE_LATCH)) W ( .CLK(CLK_buf), .WE(WE_buf), .SEL(SEL[i]), .Di(Di_buf), .Do(Do_pre) );
end
endgenerate
@@ -178,7 +213,7 @@
endmodule
-module DFFRAM_COL4
+module DFFRAM_COL4 #( parameter USE_LATCH=0 )
(
CLK,
WE,
@@ -200,7 +235,7 @@
wire [31:0] Do_pre;
wire CLK_buf;
wire [3:0] WE_buf;
- wire [5:3] A_buf;
+ wire [7:0] A_buf;
wire [31:0] Do_B_0_0;
wire [31:0] Do_B_0_1;
@@ -213,16 +248,16 @@
sky130_fd_sc_hd__clkbuf_8 WEBUF[3:0] (.X(WE_buf), .A(WE));
sky130_fd_sc_hd__clkbuf_8 DIBUF[31:0] (.X(Di_buf), .A(Di));
- sky130_fd_sc_hd__clkbuf_16 ABUF[2:0] ( .X(A_buf), .A(A[5:3]) );
-
+ sky130_fd_sc_hd__clkbuf_8 ABUF[7:0] ( .X(A_buf), .A(A[7:0]) );
+
DEC2x4 DEC ( .EN(EN), .A(A[7:6]), .SEL(row_sel) );
- SRAM64x32 B_0_0 ( .CLK(CLK_buf), .WE(WE_buf), .EN(row_sel[0]), .Di(Di_buf), .Do(Do_B_0_0), .A({A_buf,A[2:0]}) );
- SRAM64x32 B_0_1 ( .CLK(CLK_buf), .WE(WE_buf), .EN(row_sel[1]), .Di(Di_buf), .Do(Do_B_0_1), .A({A_buf,A[2:0]}) );
- SRAM64x32 B_0_2 ( .CLK(CLK_buf), .WE(WE_buf), .EN(row_sel[2]), .Di(Di_buf), .Do(Do_B_0_2), .A({A_buf,A[2:0]}) );
- SRAM64x32 B_0_3 ( .CLK(CLK_buf), .WE(WE_buf), .EN(row_sel[3]), .Di(Di_buf), .Do(Do_B_0_3), .A({A_buf,A[2:0]}) );
+ SRAM64x32 #(.USE_LATCH(USE_LATCH)) B_0_0 ( .CLK(CLK_buf), .WE(WE_buf), .EN(row_sel[0]), .Di(Di_buf), .Do(Do_B_0_0), .A(A_buf[5:0]) );
+ SRAM64x32 #(.USE_LATCH(USE_LATCH)) B_0_1 ( .CLK(CLK_buf), .WE(WE_buf), .EN(row_sel[1]), .Di(Di_buf), .Do(Do_B_0_1), .A(A_buf[5:0]) );
+ SRAM64x32 #(.USE_LATCH(USE_LATCH)) B_0_2 ( .CLK(CLK_buf), .WE(WE_buf), .EN(row_sel[2]), .Di(Di_buf), .Do(Do_B_0_2), .A(A_buf[5:0]) );
+ SRAM64x32 #(.USE_LATCH(USE_LATCH)) B_0_3 ( .CLK(CLK_buf), .WE(WE_buf), .EN(row_sel[3]), .Di(Di_buf), .Do(Do_B_0_3), .A(A_buf[5:0]) );
- MUX4x1_32 MUX ( .A0(Do_B_0_0), .A1(Do_B_0_1), .A2(Do_B_0_2), .A3(Do_B_0_3), .S(A[7:6]), .X(Do) );
+ MUX4x1_32 MUX ( .A0(Do_B_0_0), .A1(Do_B_0_1), .A2(Do_B_0_2), .A3(Do_B_0_3), .S(A_buf[7:6]), .X(Do) );
endmodule
diff --git a/verilog/rtl/RAM_6Kx32.v b/verilog/rtl/RAM_6Kx32.v
index 29760a8..0ca62fa 100644
--- a/verilog/rtl/RAM_6Kx32.v
+++ b/verilog/rtl/RAM_6Kx32.v
@@ -18,6 +18,7 @@
wire [BLOCKS-1:0] _EN_ ;
wire [31:0] _Do_ [BLOCKS-1:0];
+ wire [31:0] Do_pre;
generate
genvar gi;
@@ -49,11 +50,14 @@
// Output Data multiplexor
- assign Do = (A[12:10] == 3'd0) ? _Do_[0] :
+ assign Do_pre = (A[12:10] == 3'd0) ? _Do_[0] :
(A[12:10] == 3'd1) ? _Do_[1] :
(A[12:10] == 3'd2) ? _Do_[2] :
(A[12:10] == 3'd3) ? _Do_[3] :
(A[12:10] == 3'd4) ? _Do_[4] :
- (A[12:10] == 3'd5) ? _Do_[5] : 32'd0;
+ (A[12:10] == 3'd5) ? _Do_[5] :
+ 32'd0;
+
+ sky130_fd_sc_hd__clkbuf_4 DOBUF[31:0] (.X(Do), .A(Do_pre));
endmodule
\ No newline at end of file
