commit: 5f4ebd1c064a658bee7a66b112e5ba9c7868bc57
[log]
author: Ahmed Ghazy <ahmed.ghazy@efabless.com>
Wed Jan 13 14:06:06 2021 +0000
committer: Ahmed Ghazy <ahmed.ghazy@efabless.com>
Wed Jan 13 14:06:06 2021 +0000
tree: c5ea398cc3990b3eea6e83dadb9b8ea472dd72c2
parent: 9e6841eaa73e89c080d4f83be2645391f8cd229a [diff]

[DATA] Update RAM_6KX32

def/RAM_6Kx32.def.gz[Added - diff]
gds/RAM_6Kx32.gds.gz.00.split[diff]
gds/RAM_6Kx32.gds.gz.01.split[diff]
gds/RAM_6Kx32.gds.gz.02.split[diff]
lef/RAM_6Kx32.lef[diff]
mag/RAM_6Kx32.mag.gz.00.split[Added - diff]
mag/RAM_6Kx32.mag.gz.01.split[Added - diff]
mag/RAM_6Kx32.mag.gz.02.split[Added - diff]
maglef/RAM_6Kx32.mag[Added - diff]
spi/lvs/RAM_6Kx32.spice[Added - diff]
verilog/gl/RAM_6Kx32.v[Added - diff]

11 files changed

tree: c5ea398cc3990b3eea6e83dadb9b8ea472dd72c2

README.md

Caravel Plus

Caravel management SoC attached to the largest possible SRAM that can fit the user's area.