Added a new 24KB memory model based on 3 x 8KB
diff --git a/.gitignore b/.gitignore
new file mode 100644
index 0000000..1d0b824
--- /dev/null
+++ b/.gitignore
@@ -0,0 +1,14 @@
+*.code-workspace
+*.vvp
+*.hex
+*.elf
+*.exe
+*.vcd
+*.log
+*.lst
+*.bin
+*.out
+/pdk/*
+.DS_Store
+*.exe
+runs/
diff --git a/verilog/rtl/RAM_2x4KB.v b/verilog/rtl/RAM_2x4KB.v
new file mode 100644
index 0000000..a218d2a
--- /dev/null
+++ b/verilog/rtl/RAM_2x4KB.v
@@ -0,0 +1,38 @@
+module RAM_2x4KB (
+ CLK,
+ WE,
+ EN,
+ Di,
+ Do,
+ A
+);
+ input CLK;
+ input [3:0] WE;
+ input EN;
+ input [31:0] Di;
+ output [31:0] Do;
+ input [10:0] A;
+
+ wire [31:0] Do_0, Do_1;
+
+ DFFRAM_4KB #(.COLS(2)) RAM0 (
+ .CLK(CLK),
+ .WE(WE),
+ .EN(~A[10]),
+ .Di(Di),
+ .Do(Do_0),
+ .A(A[9:0])
+ );
+
+ DFFRAM_4KB #(.COLS(2)) RAM1 (
+ .CLK(CLK),
+ .WE(WE),
+ .EN(A[10]),
+ .Di(Di),
+ .Do(Do_1),
+ .A(A[9:0])
+ );
+
+ assign Do = A[10] ? Do_1 : Do_0;
+
+endmodule
\ No newline at end of file
diff --git a/verilog/rtl/RAM_6Kx32-.v b/verilog/rtl/RAM_6Kx32-.v
new file mode 100644
index 0000000..32bcaff
--- /dev/null
+++ b/verilog/rtl/RAM_6Kx32-.v
@@ -0,0 +1,75 @@
+//`define USE_DFFRAM_BEH
+module RAM_6Kx32 (
+`ifdef USE_POWER_PINS
+ VPWR,
+ VGND,
+`endif
+ CLK,
+ WE,
+ EN,
+ Di,
+ Do,
+ A
+);
+`ifdef USE_POWER_PINS
+ input VPWR;
+ input VGND;
+`endif
+ input CLK;
+ input [3:0] WE;
+ input EN;
+ input [31:0] Di;
+ output [31:0] Do;
+ input [12:0] A;
+
+ localparam BLOCKS=6;
+
+ wire [BLOCKS-1:0] _EN_ ;
+ wire [31:0] _Do_ [BLOCKS-1:0];
+ wire [31:0] Do_pre;
+
+ generate
+ genvar gi;
+ for(gi=0; gi<BLOCKS; gi=gi+1)
+
+`ifdef USE_DFFRAM_BEH
+ DFFRAM_beh
+`else
+ DFFRAM_4KB
+`endif
+ #(.COLS(4)) RAM (
+ `ifdef USE_POWER_PINS
+ .VPWR(VPWR),
+ .VGND(VGND),
+ `endif
+ .CLK(CLK),
+ .WE(WE),
+ .EN(_EN_[gi]),
+ .Di(Di),
+ .Do(_Do_[gi]),
+ .A(A[9:0])
+ );
+
+ endgenerate
+
+ // The block decoder
+ assign _EN_[0] = A[12:10] == 3'd0;
+ assign _EN_[1] = A[12:10] == 3'd1;
+ assign _EN_[2] = A[12:10] == 3'd2;
+ assign _EN_[3] = A[12:10] == 3'd3;
+ assign _EN_[4] = A[12:10] == 3'd4;
+ assign _EN_[5] = A[12:10] == 3'd5;
+
+
+ // Output Data multiplexor
+ assign Do_pre = (A[12:10] == 3'd0) ? _Do_[0] :
+ (A[12:10] == 3'd1) ? _Do_[1] :
+ (A[12:10] == 3'd2) ? _Do_[2] :
+ (A[12:10] == 3'd3) ? _Do_[3] :
+ (A[12:10] == 3'd4) ? _Do_[4] :
+ (A[12:10] == 3'd5) ? _Do_[5] :
+ 32'd0;
+
+ sky130_fd_sc_hd__clkbuf_4 DOBUF[31:0] (.X(Do), .A(Do_pre));
+
+endmodule
\ No newline at end of file
diff --git a/verilog/rtl/RAM_6Kx32.v b/verilog/rtl/RAM_6Kx32.v
index 32bcaff..1b65721 100644
--- a/verilog/rtl/RAM_6Kx32.v
+++ b/verilog/rtl/RAM_6Kx32.v
@@ -22,22 +22,17 @@
output [31:0] Do;
input [12:0] A;
- localparam BLOCKS=6;
+ localparam BLOCKS=3;
- wire [BLOCKS-1:0] _EN_ ;
- wire [31:0] _Do_ [BLOCKS-1:0];
- wire [31:0] Do_pre;
+ wire [BLOCKS-1:0] _EN_ ;
+ wire [31:0] _Do_ [BLOCKS-1:0];
+ wire [31:0] Do_pre;
generate
genvar gi;
for(gi=0; gi<BLOCKS; gi=gi+1)
-`ifdef USE_DFFRAM_BEH
- DFFRAM_beh
-`else
- DFFRAM_4KB
-`endif
- #(.COLS(4)) RAM (
+ RAM_2x4KB RAM (
`ifdef USE_POWER_PINS
.VPWR(VPWR),
.VGND(VGND),
@@ -47,7 +42,7 @@
.EN(_EN_[gi]),
.Di(Di),
.Do(_Do_[gi]),
- .A(A[9:0])
+ .A(A[10:0])
);
endgenerate
@@ -56,19 +51,11 @@
assign _EN_[0] = A[12:10] == 3'd0;
assign _EN_[1] = A[12:10] == 3'd1;
assign _EN_[2] = A[12:10] == 3'd2;
- assign _EN_[3] = A[12:10] == 3'd3;
- assign _EN_[4] = A[12:10] == 3'd4;
- assign _EN_[5] = A[12:10] == 3'd5;
-
// Output Data multiplexor
- assign Do_pre = (A[12:10] == 3'd0) ? _Do_[0] :
- (A[12:10] == 3'd1) ? _Do_[1] :
- (A[12:10] == 3'd2) ? _Do_[2] :
- (A[12:10] == 3'd3) ? _Do_[3] :
- (A[12:10] == 3'd4) ? _Do_[4] :
- (A[12:10] == 3'd5) ? _Do_[5] :
- 32'd0;
+ assign Do_pre = (A[12:11] == 2'd0) ? _Do_[0] :
+ (A[12:11] == 2'd1) ? _Do_[1] :
+ (A[12:11] == 2'd2) ? _Do_[2] : 32'd0;
sky130_fd_sc_hd__clkbuf_4 DOBUF[31:0] (.X(Do), .A(Do_pre));
