final gds oasis
diff --git a/mpw_precheck/logs/gds.info b/mpw_precheck/logs/gds.info
new file mode 100644
index 0000000..69c1d7e
--- /dev/null
+++ b/mpw_precheck/logs/gds.info
@@ -0,0 +1 @@
+user_project_wrapper.gds: a5b78e1dee205485a829ba28cdd3753d8636ecf7
\ No newline at end of file
diff --git a/mpw_precheck/logs/git.info b/mpw_precheck/logs/git.info
new file mode 100644
index 0000000..cd4ec94
--- /dev/null
+++ b/mpw_precheck/logs/git.info
@@ -0,0 +1,3 @@
+Repository: https://github.com/egorxe/ophelia_fpga_openmpw.git
+Branch: main
+Commit: 4b407974710e71322cb6270d812c2b44b3e13cbb
diff --git a/mpw_precheck/logs/klayout_beol_check.log b/mpw_precheck/logs/klayout_beol_check.log
new file mode 100644
index 0000000..291e7ad
--- /dev/null
+++ b/mpw_precheck/logs/klayout_beol_check.log
@@ -0,0 +1,421 @@
+2022-12-05 18:58:03 +0000: Memory Usage (543004K) : Starting running GF180MCU Klayout DRC runset on /root/ophelia_efpga/gds/user_project_wrapper.gds
+2022-12-05 18:58:03 +0000: Memory Usage (543004K) : Ruby Version for klayout: 2.0.0
+2022-12-05 18:58:06 +0000: Memory Usage (816820K) : Loading database to memory is complete.
+2022-12-05 18:58:06 +0000: Memory Usage (816820K) : GF180MCU Klayout DRC runset output at: /mnt/uffs/user/u9789_egorxe/design/ophelia_efpga/jobs/mpw_precheck/e91b7603-4cb2-40d3-9c9d-39f7dcd32d80/outputs/reports/klayout_beol_check.xml
+2022-12-05 18:58:06 +0000: Memory Usage (816820K) : Number of threads to use 4
+2022-12-05 18:58:06 +0000: Memory Usage (816820K) : flat mode is enabled.
+2022-12-05 18:58:06 +0000: Memory Usage (816820K) : Read in polygons from layers.
+2022-12-05 18:59:44 +0000: Memory Usage (2188240K) : Starting deriving base layers.
+2022-12-05 19:00:34 +0000: Memory Usage (3094824K) : Evaluate switches.
+2022-12-05 19:00:34 +0000: Memory Usage (3094824K) : FEOL is disabled.
+2022-12-05 19:00:34 +0000: Memory Usage (3094824K) : BEOL is enabled.
+2022-12-05 19:00:35 +0000: Memory Usage (3094824K) : connectivity rules are enabled.
+2022-12-05 19:00:35 +0000: Memory Usage (3094824K) : METAL_TOP Selected is 9K
+2022-12-05 19:00:35 +0000: Memory Usage (3094824K) : METAL_STACK Selected is 5LM
+2022-12-05 19:00:35 +0000: Memory Usage (3094824K) : Wedge enabled true
+2022-12-05 19:00:35 +0000: Memory Usage (3094824K) : Ball enabled true
+2022-12-05 19:00:35 +0000: Memory Usage (3094824K) : Gold enabled true
+2022-12-05 19:00:35 +0000: Memory Usage (3094824K) : MIM Option selected B
+/opt/checks/tech-files/gf180mcuC_mr.drc:543: warning: already initialized constant DRC::DRCEngine::OFFGRID
+/opt/checks/tech-files/gf180mcuC_mr.drc:463: warning: previous definition of OFFGRID was here
+2022-12-05 19:00:35 +0000: Memory Usage (3094824K) : Offgrid enabled true
+2022-12-05 19:00:35 +0000: Memory Usage (3094824K) : Construct connectivity for the design.
+2022-12-05 19:01:20 +0000: Memory Usage (3094824K) : Connectivity rules enabled, Netlist object will be generated.
+2022-12-05 19:03:33 +0000: Memory Usage (4486392K) : Total area of the design is 8997120.228799999 um^2.
+2022-12-05 19:03:33 +0000: Memory Usage (4486392K) : Total no. of polygons in the design is 11391089
+2022-12-05 19:03:33 +0000: Memory Usage (4486392K) : Initialization and base layers definition.
+2022-12-05 19:03:33 +0000: Memory Usage (4486392K) : Starting GF180MCU DRC rules.
+2022-12-05 19:03:33 +0000: Memory Usage (4486392K) : BEOL section
+2022-12-05 19:03:33 +0000: Memory Usage (4486392K) : Executing rule M1.1
+2022-12-05 19:03:37 +0000: Memory Usage (4486392K) : Executing rule M1.2a
+2022-12-05 19:06:03 +0000: Memory Usage (4486392K) : Executing rule M1.2b
+2022-12-05 19:07:16 +0000: Memory Usage (5008128K) : Executing rule M1.3
+2022-12-05 19:07:16 +0000: Memory Usage (5008128K) : Executing rule M2.1
+2022-12-05 19:07:17 +0000: Memory Usage (5008128K) : Executing rule M2.2a
+2022-12-05 19:07:21 +0000: Memory Usage (5008128K) : Executing rule M2.2b
+2022-12-05 19:07:34 +0000: Memory Usage (5008128K) : Executing rule M2.3
+2022-12-05 19:07:34 +0000: Memory Usage (5008128K) : Executing rule M3.1
+2022-12-05 19:07:34 +0000: Memory Usage (5008128K) : Executing rule M3.2a
+2022-12-05 19:07:36 +0000: Memory Usage (5008128K) : Executing rule M3.2b
+2022-12-05 19:07:42 +0000: Memory Usage (5008128K) : Executing rule M3.3
+2022-12-05 19:07:42 +0000: Memory Usage (5008128K) : Executing rule M4.1
+2022-12-05 19:07:42 +0000: Memory Usage (5008128K) : Executing rule M4.2a
+2022-12-05 19:07:43 +0000: Memory Usage (5008128K) : Executing rule M4.2b
+2022-12-05 19:07:45 +0000: Memory Usage (5008128K) : Executing rule M4.3
+2022-12-05 19:07:45 +0000: Memory Usage (5008128K) : Executing rule M5.1
+2022-12-05 19:07:45 +0000: Memory Usage (5008128K) : Executing rule M5.2a
+2022-12-05 19:07:45 +0000: Memory Usage (5008128K) : Executing rule M5.2b
+2022-12-05 19:07:45 +0000: Memory Usage (5008128K) : Executing rule M5.3
+2022-12-05 19:07:45 +0000: Memory Usage (5008128K) : Executing rule V1.1
+2022-12-05 19:07:47 +0000: Memory Usage (5008128K) : Executing rule V1.2a
+2022-12-05 19:07:56 +0000: Memory Usage (5049088K) : Executing rule V1.2b
+2022-12-05 19:07:57 +0000: Memory Usage (5049088K) : Executing rule V1.3a
+2022-12-05 19:09:46 +0000: Memory Usage (6433420K) : Executing rule V1.3c
+2022-12-05 19:10:40 +0000: Memory Usage (6392592K) : Executing rule V1.3d
+2022-12-05 19:11:01 +0000: Memory Usage (6810020K) : Executing rule V1.4a
+2022-12-05 19:11:22 +0000: Memory Usage (6991568K) : Executing rule V1.4b
+2022-12-05 19:11:50 +0000: Memory Usage (7270364K) : Executing rule V1.4c
+2022-12-05 19:11:55 +0000: Memory Usage (7317000K) : Executing rule V2.1
+2022-12-05 19:11:57 +0000: Memory Usage (7426976K) : Executing rule V2.2a
+2022-12-05 19:12:06 +0000: Memory Usage (7451860K) : Executing rule V2.2b
+2022-12-05 19:12:07 +0000: Memory Usage (7451860K) : Executing rule V2.3b
+2022-12-05 19:12:29 +0000: Memory Usage (7651840K) : Executing rule V2.3c
+2022-12-05 19:12:58 +0000: Memory Usage (8043844K) : Executing rule V2.3d
+2022-12-05 19:13:03 +0000: Memory Usage (8077540K) : Executing rule V2.4a
+2022-12-05 19:13:16 +0000: Memory Usage (8178816K) : Executing rule V2.4b
+2022-12-05 19:13:46 +0000: Memory Usage (8604416K) : Executing rule V2.4c
+2022-12-05 19:13:49 +0000: Memory Usage (8692184K) : Executing rule V3.1
+2022-12-05 19:13:50 +0000: Memory Usage (8692184K) : Executing rule V3.2a
+2022-12-05 19:13:55 +0000: Memory Usage (8696136K) : Executing rule V3.2b
+2022-12-05 19:13:55 +0000: Memory Usage (8696136K) : Executing rule V3.3b
+2022-12-05 19:14:05 +0000: Memory Usage (8774064K) : Executing rule V3.3c
+2022-12-05 19:14:19 +0000: Memory Usage (8978380K) : Executing rule V3.3d
+2022-12-05 19:14:22 +0000: Memory Usage (9085300K) : Executing rule V3.4a
+2022-12-05 19:14:38 +0000: Memory Usage (9085300K) : Executing rule V3.4b
+2022-12-05 19:14:57 +0000: Memory Usage (9161284K) : Executing rule V3.4c
+2022-12-05 19:14:58 +0000: Memory Usage (9161284K) : Executing rule V4.1
+2022-12-05 19:14:58 +0000: Memory Usage (9161284K) : Executing rule V4.2a
+2022-12-05 19:14:59 +0000: Memory Usage (9161284K) : Executing rule V4.2b
+2022-12-05 19:14:59 +0000: Memory Usage (9161284K) : Executing rule V4.3b
+2022-12-05 19:15:02 +0000: Memory Usage (9177668K) : Executing rule V4.3c
+2022-12-05 19:15:04 +0000: Memory Usage (9181764K) : Executing rule V4.3d
+2022-12-05 19:15:05 +0000: Memory Usage (9203244K) : Executing rule V4.4a
+2022-12-05 19:15:06 +0000: Memory Usage (9203244K) : Executing rule V4.4b
+2022-12-05 19:15:07 +0000: Memory Usage (9207340K) : Executing rule V4.4c
+2022-12-05 19:15:07 +0000: Memory Usage (9207340K) : Executing rule V5.1
+2022-12-05 19:15:07 +0000: Memory Usage (9207340K) : Executing rule V5.2a
+2022-12-05 19:15:08 +0000: Memory Usage (9207340K) : Executing rule V5.2b
+2022-12-05 19:15:08 +0000: Memory Usage (9207340K) : Executing rule V5.3b
+2022-12-05 19:15:08 +0000: Memory Usage (9207340K) : Executing rule V5.3c
+2022-12-05 19:15:08 +0000: Memory Usage (9207340K) : Executing rule V5.3d
+2022-12-05 19:15:09 +0000: Memory Usage (9207340K) : Executing rule V5.4a
+2022-12-05 19:15:09 +0000: Memory Usage (9207340K) : Executing rule V5.4b
+2022-12-05 19:15:09 +0000: Memory Usage (9207340K) : Executing rule V5.4c
+2022-12-05 19:15:09 +0000: Memory Usage (9207340K) : MetalTop thickness 9k/11k section
+2022-12-05 19:15:10 +0000: Memory Usage (9207340K) : Executing rule MT.1
+2022-12-05 19:15:10 +0000: Memory Usage (9207340K) : Executing rule MT.2a
+2022-12-05 19:15:10 +0000: Memory Usage (9207340K) : Executing rule MT.2b
+2022-12-05 19:15:13 +0000: Memory Usage (9360128K) : Executing rule MT.4
+2022-12-05 19:15:13 +0000: Memory Usage (9360128K) : Executing rule MC.1
+2022-12-05 19:15:13 +0000: Memory Usage (9360128K) : Executing rule MC.2
+2022-12-05 19:15:13 +0000: Memory Usage (9360128K) : Executing rule MC.3
+2022-12-05 19:15:13 +0000: Memory Usage (9360128K) : Executing rule MC.4
+2022-12-05 19:15:19 +0000: Memory Usage (9381020K) : Executing rule PRES.1
+2022-12-05 19:15:20 +0000: Memory Usage (9381020K) : Executing rule PRES.2
+2022-12-05 19:15:20 +0000: Memory Usage (9381020K) : Executing rule PRES.3
+2022-12-05 19:15:20 +0000: Memory Usage (9381020K) : Executing rule PRES.4
+2022-12-05 19:15:20 +0000: Memory Usage (9381020K) : Executing rule PRES.5
+2022-12-05 19:15:20 +0000: Memory Usage (9381020K) : Executing rule PRES.6
+2022-12-05 19:15:20 +0000: Memory Usage (9381020K) : Executing rule PRES.7
+2022-12-05 19:15:27 +0000: Memory Usage (9430172K) : Executing rule PRES.9a
+2022-12-05 19:15:27 +0000: Memory Usage (9430172K) : Executing rule PRES.9b
+2022-12-05 19:15:33 +0000: Memory Usage (9450652K) : Executing rule LRES.1
+2022-12-05 19:15:33 +0000: Memory Usage (9450652K) : Executing rule LRES.2
+2022-12-05 19:15:33 +0000: Memory Usage (9450652K) : Executing rule LRES.3
+2022-12-05 19:15:33 +0000: Memory Usage (9450652K) : Executing rule LRES.4
+2022-12-05 19:15:34 +0000: Memory Usage (9450652K) : Executing rule LRES.5
+2022-12-05 19:15:46 +0000: Memory Usage (9548404K) : Executing rule LRES.6
+2022-12-05 19:15:52 +0000: Memory Usage (9602056K) : Executing rule LRES.7
+2022-12-05 19:15:58 +0000: Memory Usage (9655768K) : Executing rule LRES.9a
+2022-12-05 19:15:58 +0000: Memory Usage (9655768K) : Executing rule LRES.9b
+2022-12-05 19:16:32 +0000: Memory Usage (9948800K) : Executing rule HRES.1
+2022-12-05 19:16:32 +0000: Memory Usage (9948800K) : Executing rule HRES.2
+2022-12-05 19:16:32 +0000: Memory Usage (9948800K) : Executing rule HRES.3
+2022-12-05 19:16:32 +0000: Memory Usage (9948800K) : Executing rule HRES.4
+2022-12-05 19:16:33 +0000: Memory Usage (9948800K) : Executing rule HRES.5
+2022-12-05 19:16:33 +0000: Memory Usage (9948800K) : Executing rule HRES.6
+2022-12-05 19:16:50 +0000: Memory Usage (10084280K) : Executing rule HRES.7
+2022-12-05 19:16:50 +0000: Memory Usage (10084280K) : Executing rule HRES.8
+2022-12-05 19:16:50 +0000: Memory Usage (10084280K) : Executing rule HRES.9
+2022-12-05 19:16:51 +0000: Memory Usage (10084280K) : Executing rule HRES.10
+2022-12-05 19:16:58 +0000: Memory Usage (10084280K) : Executing rule HRES.12a
+2022-12-05 19:16:58 +0000: Memory Usage (10084280K) : Executing rule HRES.12b
+2022-12-05 19:16:58 +0000: Memory Usage (10084280K) : MIM Capacitor Option B section
+2022-12-05 19:16:58 +0000: Memory Usage (10084280K) : Executing rule MIMTM.1
+2022-12-05 19:16:58 +0000: Memory Usage (10084280K) : Executing rule MIMTM.2
+2022-12-05 19:16:58 +0000: Memory Usage (10084280K) : Executing rule MIMTM.3
+2022-12-05 19:16:59 +0000: Memory Usage (10084280K) : Executing rule MIMTM.4
+2022-12-05 19:16:59 +0000: Memory Usage (10084280K) : Executing rule MIMTM.5
+2022-12-05 19:17:00 +0000: Memory Usage (10084280K) : Executing rule MIMTM.6
+2022-12-05 19:17:00 +0000: Memory Usage (10084280K) : Executing rule MIMTM.7
+2022-12-05 19:17:00 +0000: Memory Usage (10084280K) : Executing rule MIMTM.8a
+2022-12-05 19:17:00 +0000: Memory Usage (10084280K) : Executing rule MIMTM.8b
+2022-12-05 19:17:00 +0000: Memory Usage (10084280K) : Executing rule MIMTM.9
+2022-12-05 19:17:01 +0000: Memory Usage (10084280K) : Executing rule MIMTM.10
+2022-12-05 19:17:01 +0000: Memory Usage (10084280K) : Executing rule MIMTM.11
+2022-12-05 19:17:01 +0000: Memory Usage (10084280K) : Executing rule NAT.1
+2022-12-05 19:17:04 +0000: Memory Usage (10238784K) : Executing rule NAT.2
+2022-12-05 19:17:04 +0000: Memory Usage (10238784K) : Executing rule NAT.3
+2022-12-05 19:17:04 +0000: Memory Usage (10238784K) : Executing rule NAT.4
+2022-12-05 19:17:17 +0000: Memory Usage (10336588K) : Executing rule NAT.5
+2022-12-05 19:17:30 +0000: Memory Usage (10500956K) : CONNECTIVITY_RULES section
+2022-12-05 19:17:30 +0000: Memory Usage (10500956K) : Executing rule NAT.6
+2022-12-05 19:17:30 +0000: Memory Usage (10535972K) : Executing rule NAT.7
+2022-12-05 19:17:30 +0000: Memory Usage (10535972K) : Executing rule NAT.8
+2022-12-05 19:17:31 +0000: Memory Usage (10535972K) : Executing rule NAT.9
+2022-12-05 19:17:31 +0000: Memory Usage (10535972K) : Executing rule NAT.10
+2022-12-05 19:17:31 +0000: Memory Usage (10535972K) : Executing rule NAT.11
+2022-12-05 19:17:31 +0000: Memory Usage (10535972K) : Executing rule NAT.12
+2022-12-05 19:17:31 +0000: Memory Usage (10566328K) : Executing rule BJT.1
+2022-12-05 19:17:32 +0000: Memory Usage (10566328K) : Executing rule BJT.2
+2022-12-05 19:17:40 +0000: Memory Usage (10701540K) : Executing rule BJT.3
+2022-12-05 19:17:40 +0000: Memory Usage (10701540K) : Executing rule DE.2
+2022-12-05 19:17:40 +0000: Memory Usage (10701540K) : Executing rule DE.3
+2022-12-05 19:17:41 +0000: Memory Usage (10701540K) : Executing rule DE.4
+2022-12-05 19:17:46 +0000: Memory Usage (10809960K) : Executing rule LVS_BJT.1
+2022-12-05 19:17:46 +0000: Memory Usage (10809960K) : Executing rule O.DF.3a
+2022-12-05 19:17:46 +0000: Memory Usage (10809960K) : Executing rule O.DF.6
+2022-12-05 19:17:46 +0000: Memory Usage (10809960K) : Executing rule O.DF.9
+2022-12-05 19:17:46 +0000: Memory Usage (10809960K) : Executing rule O.PL.2
+2022-12-05 19:18:04 +0000: Memory Usage (11007720K) : Executing rule O.PL.3a
+2022-12-05 19:18:32 +0000: Memory Usage (11293396K) : Executing rule O.PL.4
+2022-12-05 19:18:32 +0000: Memory Usage (11293396K) : Executing rule O.SB.2
+2022-12-05 19:18:33 +0000: Memory Usage (11293396K) : Executing rule O.SB.3
+2022-12-05 19:18:33 +0000: Memory Usage (11293396K) : Executing rule O.SB.4
+2022-12-05 19:18:33 +0000: Memory Usage (11293396K) : Executing rule O.SB.5b_3.3V
+2022-12-05 19:18:33 +0000: Memory Usage (11293396K) : Executing rule O.SB.9
+2022-12-05 19:18:33 +0000: Memory Usage (11293396K) : Executing rule O.SB.11
+2022-12-05 19:18:34 +0000: Memory Usage (11293396K) : Executing rule O.SB.13_3.3V
+2022-12-05 19:18:34 +0000: Memory Usage (11293396K) : Executing rule O.SB.13_5V
+2022-12-05 19:18:34 +0000: Memory Usage (11293396K) : Executing rule O.CO.7
+2022-12-05 19:19:29 +0000: Memory Usage (14451776K) : Executing rule O.PL.ORT
+2022-12-05 19:20:17 +0000: Memory Usage (14451776K) : Executing rule EF.01
+2022-12-05 19:20:25 +0000: Memory Usage (14451776K) : Executing rule EF.02
+2022-12-05 19:20:25 +0000: Memory Usage (14451776K) : Executing rule EF.03
+2022-12-05 19:20:30 +0000: Memory Usage (14451776K) : Executing rule EF.04a
+2022-12-05 19:20:41 +0000: Memory Usage (14451776K) : Executing rule EF.04b
+2022-12-05 19:20:41 +0000: Memory Usage (14451776K) : Executing rule EF.04c
+2022-12-05 19:20:46 +0000: Memory Usage (14451776K) : Executing rule EF.04d
+2022-12-05 19:20:46 +0000: Memory Usage (14451776K) : Executing rule EF.05
+2022-12-05 19:20:57 +0000: Memory Usage (14451776K) : Executing rule EF.06
+2022-12-05 19:20:57 +0000: Memory Usage (14451776K) : Executing rule EF.07
+2022-12-05 19:20:58 +0000: Memory Usage (14451776K) : Executing rule EF.08
+2022-12-05 19:20:58 +0000: Memory Usage (14451776K) : Executing rule EF.09
+2022-12-05 19:20:58 +0000: Memory Usage (14451776K) : Executing rule EF.10
+2022-12-05 19:20:58 +0000: Memory Usage (14451776K) : Executing rule EF.11
+2022-12-05 19:21:16 +0000: Memory Usage (14451776K) : Executing rule EF.12
+2022-12-05 19:21:18 +0000: Memory Usage (14451776K) : Executing rule EF.13
+2022-12-05 19:21:19 +0000: Memory Usage (14451776K) : Executing rule EF.14
+2022-12-05 19:21:20 +0000: Memory Usage (14451776K) : Executing rule EF.15
+2022-12-05 19:21:21 +0000: Memory Usage (14451776K) : Executing rule EF.16a
+2022-12-05 19:21:22 +0000: Memory Usage (14451776K) : Executing rule EF.16b
+2022-12-05 19:21:23 +0000: Memory Usage (14451776K) : Executing rule EF.17
+2022-12-05 19:21:23 +0000: Memory Usage (14451776K) : Executing rule EF.18
+2022-12-05 21:06:13 +0000: Memory Usage (15186992K) : Executing rule EF.19
+2022-12-05 22:35:21 +0000: Memory Usage (15186992K) : Executing rule EF.20
+2022-12-05 22:35:28 +0000: Memory Usage (15186992K) : Executing rule EF.21
+2022-12-05 22:35:28 +0000: Memory Usage (15186992K) : Executing rule EF.22a
+2022-12-05 22:35:29 +0000: Memory Usage (15186992K) : Executing rule EF.22b
+2022-12-05 22:35:29 +0000: Memory Usage (15186992K) : Executing rule MDN.1
+2022-12-05 22:35:30 +0000: Memory Usage (15186992K) : CONNECTIVITY_RULES section
+2022-12-05 22:35:30 +0000: Memory Usage (15186992K) : Executing rule MDN.2a
+2022-12-05 22:35:30 +0000: Memory Usage (15186992K) : Executing rule MDN.2b
+2022-12-05 22:35:43 +0000: Memory Usage (15186992K) : Executing rule MDN.3a
+2022-12-05 22:35:43 +0000: Memory Usage (15186992K) : Executing rule MDN.3b
+2022-12-05 22:35:44 +0000: Memory Usage (15186992K) : Executing rule MDN.4a
+2022-12-05 22:35:44 +0000: Memory Usage (15186992K) : Executing rule MDN.4b
+2022-12-05 22:35:47 +0000: Memory Usage (15186992K) : Executing rule MDN.5ai
+2022-12-05 22:35:47 +0000: Memory Usage (15186992K) : Executing rule MDN.5aii
+2022-12-05 22:35:48 +0000: Memory Usage (15186992K) : Executing rule MDN.5b
+2022-12-05 22:35:48 +0000: Memory Usage (15186992K) : Executing rule MDN.5c
+2022-12-05 22:35:48 +0000: Memory Usage (15186992K) : Executing rule MDN.6
+2022-12-05 22:36:03 +0000: Memory Usage (15186992K) : Executing rule MDN.6a
+2022-12-05 22:36:04 +0000: Memory Usage (15186992K) : Executing rule MDN.7
+2022-12-05 22:36:04 +0000: Memory Usage (15186992K) : Executing rule MDN.7a
+2022-12-05 22:36:04 +0000: Memory Usage (15186992K) : CONNECTIVITY_RULES section
+2022-12-05 22:36:04 +0000: Memory Usage (15186992K) : Executing rule MDN.8a
+2022-12-05 22:36:05 +0000: Memory Usage (15186992K) : Executing rule MDN.8b
+2022-12-05 22:36:05 +0000: Memory Usage (15186992K) : Executing rule MDN.9
+2022-12-05 22:36:31 +0000: Memory Usage (15186992K) : Executing rule MDN.10a
+2022-12-05 22:36:31 +0000: Memory Usage (15186992K) : Executing rule MDN.10b
+2022-12-05 22:36:47 +0000: Memory Usage (15186992K) : Executing rule MDN.10c
+2022-12-05 22:37:21 +0000: Memory Usage (15186992K) : Executing rule MDN.10d
+2022-12-05 22:37:22 +0000: Memory Usage (15186992K) : Executing rule MDN.10ei
+2022-12-05 22:37:32 +0000: Memory Usage (15186992K) : Executing rule MDN.10eii
+2022-12-05 22:37:38 +0000: Memory Usage (15186992K) : Executing rule MDN.10f
+2022-12-05 22:37:49 +0000: Memory Usage (15417540K) : Executing rule MDN.11
+2022-12-05 22:38:09 +0000: Memory Usage (15437356K) : Executing rule MDN.12
+2022-12-05 22:38:09 +0000: Memory Usage (15437356K) : Executing rule MDN.13a
+2022-12-05 22:38:47 +0000: Memory Usage (15643940K) : Executing rule MDN.13b
+2022-12-05 22:38:48 +0000: Memory Usage (15643940K) : Executing rule MDN.13c
+2022-12-05 22:39:17 +0000: Memory Usage (15950320K) : Executing rule MDN.13d
+2022-12-05 22:39:18 +0000: Memory Usage (15950320K) : Executing rule MDN.14
+2022-12-05 22:39:18 +0000: Memory Usage (15950320K) : Executing rule MDN.15a
+2022-12-05 22:39:18 +0000: Memory Usage (15950320K) : Executing rule MDN.15b
+2022-12-05 22:39:39 +0000: Memory Usage (16163268K) : Executing rule MDN.17
+2022-12-05 22:39:58 +0000: Memory Usage (16225232K) : Executing rule MDP.1
+2022-12-05 22:40:10 +0000: Memory Usage (16486372K) : Executing rule MDP.1a
+2022-12-05 23:01:46 +0000: Memory Usage (28421860K) : Executing rule MDP.2
+2022-12-05 23:01:59 +0000: Memory Usage (28530408K) : Executing rule MDP.3
+2022-12-05 23:02:01 +0000: Memory Usage (28530408K) : Executing rule MDP.3ai
+2022-12-05 23:02:02 +0000: Memory Usage (28530408K) : Executing rule MDP.3aii
+2022-12-05 23:02:03 +0000: Memory Usage (28530408K) : Executing rule MDP.3b
+2022-12-05 23:02:03 +0000: Memory Usage (28530408K) : Executing rule MDP.3c
+2022-12-05 23:02:03 +0000: Memory Usage (28530408K) : Executing rule MDP.3d
+2022-12-05 23:02:04 +0000: Memory Usage (28530408K) : Executing rule MDP.4
+2022-12-05 23:03:28 +0000: Memory Usage (28569092K) : Executing rule MDP.4a
+2022-12-05 23:03:28 +0000: Memory Usage (28569092K) : Executing rule MDP.4b
+2022-12-05 23:03:28 +0000: Memory Usage (28569092K) : Executing rule MDP.5
+2022-12-05 23:03:43 +0000: Memory Usage (28727996K) : Executing rule MDP.5a
+2022-12-05 23:03:43 +0000: Memory Usage (28727996K) : Executing rule MDP.6
+2022-12-05 23:03:44 +0000: Memory Usage (28727996K) : Executing rule MDP.6a
+2022-12-05 23:03:44 +0000: Memory Usage (28727996K) : Executing rule MDP.7
+2022-12-05 23:03:44 +0000: Memory Usage (28727996K) : Executing rule MDP.8
+2022-12-05 23:03:45 +0000: Memory Usage (28727996K) : Executing rule MDP.9a
+2022-12-05 23:03:46 +0000: Memory Usage (28787492K) : Executing rule MDP.9b
+2022-12-05 23:03:46 +0000: Memory Usage (28787492K) : Executing rule MDP.9c
+2022-12-05 23:03:58 +0000: Memory Usage (28950832K) : Executing rule MDP.9d
+2022-12-05 23:05:49 +0000: Memory Usage (29214276K) : Executing rule MDP.9ei
+2022-12-05 23:06:29 +0000: Memory Usage (29313948K) : Executing rule MDP.9eii
+2022-12-05 23:06:30 +0000: Memory Usage (29313948K) : Executing rule MDP.9f
+2022-12-05 23:07:08 +0000: Memory Usage (29406108K) : Executing rule MDP.10
+2022-12-05 23:07:09 +0000: Memory Usage (29406108K) : CONNECTIVITY_RULES section
+2022-12-05 23:07:09 +0000: Memory Usage (29406108K) : Executing rule MDP.10a
+2022-12-05 23:07:10 +0000: Memory Usage (29406108K) : Executing rule MDP.10b
+2022-12-05 23:07:10 +0000: Memory Usage (29406108K) : Executing rule MDP.11
+2022-12-05 23:07:11 +0000: Memory Usage (29484368K) : Executing rule MDP.12
+2022-12-05 23:07:32 +0000: Memory Usage (29519552K) : Executing rule MDP.13a
+2022-12-05 23:07:51 +0000: Memory Usage (29603524K) : Executing rule MDP.13b
+2022-12-05 23:07:51 +0000: Memory Usage (29603524K) : Executing rule MDP.13c
+2022-12-05 23:08:01 +0000: Memory Usage (29645264K) : Executing rule MDP.15
+2022-12-05 23:08:02 +0000: Memory Usage (29645264K) : Executing rule MDP.16a
+2022-12-05 23:08:02 +0000: Memory Usage (29645264K) : Executing rule MDP.16b
+2022-12-05 23:08:05 +0000: Memory Usage (29645264K) : Executing rule MDP.17a
+2022-12-05 23:08:06 +0000: Memory Usage (29645264K) : Executing rule MDP.17c
+2022-12-05 23:08:06 +0000: Memory Usage (29645264K) : Executing rule Y.NW.2b_3.3V
+2022-12-05 23:08:07 +0000: Memory Usage (29645264K) : Executing rule Y.NW.2b_5V
+2022-12-05 23:08:07 +0000: Memory Usage (29645264K) : Executing rule Y.DF.6_5V
+2022-12-05 23:08:08 +0000: Memory Usage (29680280K) : Executing rule Y.DF.16_3.3V
+2022-12-05 23:08:12 +0000: Memory Usage (29680280K) : Executing rule Y.DF.16_5V
+2022-12-05 23:08:15 +0000: Memory Usage (29686428K) : Executing rule Y.PL.1_3.3V
+2022-12-05 23:08:22 +0000: Memory Usage (29715184K) : Executing rule Y.PL.1_5V
+2022-12-05 23:08:30 +0000: Memory Usage (29745148K) : Executing rule Y.PL.2_3.3V
+2022-12-05 23:08:47 +0000: Memory Usage (29959292K) : Executing rule Y.PL.2_5V
+2022-12-05 23:09:05 +0000: Memory Usage (30157052K) : Executing rule Y.PL.4_5V
+2022-12-05 23:09:05 +0000: Memory Usage (30157052K) : Executing rule Y.PL.5a_3.3V
+2022-12-05 23:09:06 +0000: Memory Usage (30157052K) : Executing rule Y.PL.5a_5V
+2022-12-05 23:09:06 +0000: Memory Usage (30157052K) : Executing rule Y.PL.5b_3.3V
+2022-12-05 23:09:06 +0000: Memory Usage (30157052K) : Executing rule Y.PL.5b_5V
+2022-12-05 23:09:07 +0000: Memory Usage (30157052K) : Executing rule S.DF.4c_MV
+2022-12-05 23:09:07 +0000: Memory Usage (30175512K) : Executing rule S.DF.6_MV
+2022-12-05 23:09:08 +0000: Memory Usage (30175512K) : Executing rule S.DF.7_MV
+2022-12-05 23:09:08 +0000: Memory Usage (30175512K) : Executing rule S.DF.8_MV
+2022-12-05 23:09:09 +0000: Memory Usage (30175512K) : Executing rule S.DF.16_MV
+2022-12-05 23:09:12 +0000: Memory Usage (30205868K) : Executing rule S.PL.5a_MV
+2022-12-05 23:09:13 +0000: Memory Usage (30205868K) : Executing rule S.PL.5b_MV
+2022-12-05 23:09:13 +0000: Memory Usage (30205868K) : Executing rule S.CO.4_MV
+2022-12-05 23:09:13 +0000: Memory Usage (30205868K) : Executing rule S.DF.4c_LV
+2022-12-05 23:09:14 +0000: Memory Usage (30240716K) : Executing rule S.DF.16_LV
+2022-12-05 23:09:17 +0000: Memory Usage (30271072K) : Executing rule S.CO.3_LV
+2022-12-05 23:09:18 +0000: Memory Usage (30271072K) : Executing rule S.CO.4_LV
+2022-12-05 23:09:18 +0000: Memory Usage (30271072K) : Executing rule S.CO.6_ii_LV
+2022-12-05 23:09:19 +0000: Memory Usage (30271072K) : Executing rule S.M1.1_LV
+2022-12-05 23:09:19 +0000: Memory Usage (30271072K) : OFFGRID-ANGLES section
+2022-12-05 23:09:20 +0000: Memory Usage (30271072K) : Executing rule comp_OFFGRID
+2022-12-05 23:09:20 +0000: Memory Usage (30271072K) : Executing rule dnwell_OFFGRID
+2022-12-05 23:09:21 +0000: Memory Usage (30271072K) : Executing rule nwell_OFFGRID
+2022-12-05 23:09:21 +0000: Memory Usage (30271072K) : Executing rule lvpwell_OFFGRID
+2022-12-05 23:09:22 +0000: Memory Usage (30271072K) : Executing rule dualgate_OFFGRID
+2022-12-05 23:09:22 +0000: Memory Usage (30271072K) : Executing rule poly2_OFFGRID
+2022-12-05 23:09:23 +0000: Memory Usage (30271072K) : Executing rule nplus_OFFGRID
+2022-12-05 23:09:23 +0000: Memory Usage (30271072K) : Executing rule pplus_OFFGRID
+2022-12-05 23:09:24 +0000: Memory Usage (30271072K) : Executing rule sab_OFFGRID
+2022-12-05 23:09:24 +0000: Memory Usage (30271072K) : Executing rule esd_OFFGRID
+2022-12-05 23:09:25 +0000: Memory Usage (30271072K) : Executing rule contact_OFFGRID
+2022-12-05 23:09:27 +0000: Memory Usage (30271072K) : Executing rule metal1_OFFGRID
+2022-12-05 23:09:28 +0000: Memory Usage (30271072K) : Executing rule via1_OFFGRID
+2022-12-05 23:09:29 +0000: Memory Usage (30271072K) : Executing rule metal2_OFFGRID
+2022-12-05 23:09:29 +0000: Memory Usage (30271072K) : Executing rule via2_OFFGRID
+2022-12-05 23:09:30 +0000: Memory Usage (30271072K) : Executing rule metal3_OFFGRID
+2022-12-05 23:09:31 +0000: Memory Usage (30271072K) : Executing rule via3_OFFGRID
+2022-12-05 23:09:31 +0000: Memory Usage (30271072K) : Executing rule metal4_OFFGRID
+2022-12-05 23:09:32 +0000: Memory Usage (30271072K) : Executing rule via4_OFFGRID
+2022-12-05 23:09:32 +0000: Memory Usage (30271072K) : Executing rule metal5_OFFGRID
+2022-12-05 23:09:32 +0000: Memory Usage (30271072K) : Executing rule via5_OFFGRID
+2022-12-05 23:09:33 +0000: Memory Usage (30271072K) : Executing rule metaltop_OFFGRID
+2022-12-05 23:09:33 +0000: Memory Usage (30271072K) : Executing rule pad_OFFGRID
+2022-12-05 23:09:34 +0000: Memory Usage (30271072K) : Executing rule resistor_OFFGRID
+2022-12-05 23:09:34 +0000: Memory Usage (30271072K) : Executing rule fhres_OFFGRID
+2022-12-05 23:09:35 +0000: Memory Usage (30271072K) : Executing rule fusetop_OFFGRID
+2022-12-05 23:09:35 +0000: Memory Usage (30271072K) : Executing rule fusewindow_d_OFFGRID
+2022-12-05 23:09:35 +0000: Memory Usage (30271072K) : Executing rule polyfuse_OFFGRID
+2022-12-05 23:09:36 +0000: Memory Usage (30271072K) : Executing rule mvsd_OFFGRID
+2022-12-05 23:09:36 +0000: Memory Usage (30271072K) : Executing rule mvpsd_OFFGRID
+2022-12-05 23:09:37 +0000: Memory Usage (30271072K) : Executing rule nat_OFFGRID
+2022-12-05 23:09:37 +0000: Memory Usage (30271072K) : Executing rule comp_dummy_OFFGRID
+2022-12-05 23:09:38 +0000: Memory Usage (30271072K) : Executing rule poly2_dummy_OFFGRID
+2022-12-05 23:09:38 +0000: Memory Usage (30271072K) : Executing rule metal1_dummy_OFFGRID
+2022-12-05 23:09:38 +0000: Memory Usage (30271072K) : Executing rule metal2_dummy_OFFGRID
+2022-12-05 23:09:39 +0000: Memory Usage (30271072K) : Executing rule metal3_dummy_OFFGRID
+2022-12-05 23:09:39 +0000: Memory Usage (30271072K) : Executing rule metal4_dummy_OFFGRID
+2022-12-05 23:09:40 +0000: Memory Usage (30271072K) : Executing rule metal5_dummy_OFFGRID
+2022-12-05 23:09:40 +0000: Memory Usage (30271072K) : Executing rule metaltop_dummy_OFFGRID
+2022-12-05 23:09:41 +0000: Memory Usage (30271072K) : Executing rule comp_label_OFFGRID
+2022-12-05 23:09:41 +0000: Memory Usage (30271072K) : Executing rule poly2_label_OFFGRID
+2022-12-05 23:09:41 +0000: Memory Usage (30271072K) : Executing rule metal1_label_OFFGRID
+2022-12-05 23:09:42 +0000: Memory Usage (30271072K) : Executing rule metal2_label_OFFGRID
+2022-12-05 23:09:42 +0000: Memory Usage (30271072K) : Executing rule metal3_label_OFFGRID
+2022-12-05 23:09:43 +0000: Memory Usage (30271072K) : Executing rule metal4_label_OFFGRID
+2022-12-05 23:09:43 +0000: Memory Usage (30271072K) : Executing rule metal5_label_OFFGRID
+2022-12-05 23:09:44 +0000: Memory Usage (30271072K) : Executing rule metaltop_label_OFFGRID
+2022-12-05 23:09:44 +0000: Memory Usage (30271072K) : Executing rule metal1_slot_OFFGRID
+2022-12-05 23:09:44 +0000: Memory Usage (30271072K) : Executing rule metal2_slot_OFFGRID
+2022-12-05 23:09:45 +0000: Memory Usage (30271072K) : Executing rule metal3_slot_OFFGRID
+2022-12-05 23:09:45 +0000: Memory Usage (30271072K) : Executing rule metal4_slot_OFFGRID
+2022-12-05 23:09:46 +0000: Memory Usage (30271072K) : Executing rule metal5_slot_OFFGRID
+2022-12-05 23:09:46 +0000: Memory Usage (30271072K) : Executing rule metaltop_slot_OFFGRID
+2022-12-05 23:09:47 +0000: Memory Usage (30271072K) : Executing rule ubmpperi_OFFGRID
+2022-12-05 23:09:47 +0000: Memory Usage (30271072K) : Executing rule ubmparray_OFFGRID
+2022-12-05 23:09:47 +0000: Memory Usage (30271072K) : Executing rule ubmeplate_OFFGRID
+2022-12-05 23:09:48 +0000: Memory Usage (30271072K) : Executing rule schottky_diode_OFFGRID
+2022-12-05 23:09:48 +0000: Memory Usage (30271072K) : Executing rule zener_OFFGRID
+2022-12-05 23:09:49 +0000: Memory Usage (30271072K) : Executing rule res_mk_OFFGRID
+2022-12-05 23:09:49 +0000: Memory Usage (30271072K) : Executing rule opc_drc_OFFGRID
+2022-12-05 23:09:49 +0000: Memory Usage (30271072K) : Executing rule ndmy_OFFGRID
+2022-12-05 23:09:50 +0000: Memory Usage (30271072K) : Executing rule pmndmy_OFFGRID
+2022-12-05 23:09:50 +0000: Memory Usage (30271072K) : Executing rule v5_xtor_OFFGRID
+2022-12-05 23:09:51 +0000: Memory Usage (30271072K) : Executing rule cap_mk_OFFGRID
+2022-12-05 23:09:51 +0000: Memory Usage (30271072K) : Executing rule mos_cap_mk_OFFGRID
+2022-12-05 23:09:52 +0000: Memory Usage (30271072K) : Executing rule ind_mk_OFFGRID
+2022-12-05 23:09:52 +0000: Memory Usage (30271072K) : Executing rule diode_mk_OFFGRID
+2022-12-05 23:09:53 +0000: Memory Usage (30271072K) : Executing rule drc_bjt_OFFGRID
+2022-12-05 23:09:53 +0000: Memory Usage (30271072K) : Executing rule lvs_bjt_OFFGRID
+2022-12-05 23:09:53 +0000: Memory Usage (30271072K) : Executing rule mim_l_mk_OFFGRID
+2022-12-05 23:09:54 +0000: Memory Usage (30271072K) : Executing rule latchup_mk_OFFGRID
+2022-12-05 23:09:54 +0000: Memory Usage (30271072K) : Executing rule guard_ring_mk_OFFGRID
+2022-12-05 23:09:55 +0000: Memory Usage (30271072K) : Executing rule otp_mk_OFFGRID
+2022-12-05 23:09:55 +0000: Memory Usage (30271072K) : Executing rule mtpmark_OFFGRID
+2022-12-05 23:09:56 +0000: Memory Usage (30271072K) : Executing rule neo_ee_mk_OFFGRID
+2022-12-05 23:09:56 +0000: Memory Usage (30271072K) : Executing rule sramcore_OFFGRID
+2022-12-05 23:09:56 +0000: Memory Usage (30271072K) : Executing rule lvs_rf_OFFGRID
+2022-12-05 23:09:57 +0000: Memory Usage (30271072K) : Executing rule lvs_drain_OFFGRID
+2022-12-05 23:09:57 +0000: Memory Usage (30271072K) : Executing rule hvpolyrs_OFFGRID
+2022-12-05 23:09:58 +0000: Memory Usage (30271072K) : Executing rule lvs_io_OFFGRID
+2022-12-05 23:09:58 +0000: Memory Usage (30271072K) : Executing rule probe_mk_OFFGRID
+2022-12-05 23:09:58 +0000: Memory Usage (30271072K) : Executing rule esd_mk_OFFGRID
+2022-12-05 23:09:59 +0000: Memory Usage (30271072K) : Executing rule lvs_source_OFFGRID
+2022-12-05 23:09:59 +0000: Memory Usage (30271072K) : Executing rule well_diode_mk_OFFGRID
+2022-12-05 23:10:00 +0000: Memory Usage (30271072K) : Executing rule ldmos_xtor_OFFGRID
+2022-12-05 23:10:00 +0000: Memory Usage (30271072K) : Executing rule plfuse_OFFGRID
+2022-12-05 23:10:01 +0000: Memory Usage (30271072K) : Executing rule efuse_mk_OFFGRID
+2022-12-05 23:10:01 +0000: Memory Usage (30271072K) : Executing rule mcell_feol_mk_OFFGRID
+2022-12-05 23:10:01 +0000: Memory Usage (30271072K) : Executing rule ymtp_mk_OFFGRID
+2022-12-05 23:10:02 +0000: Memory Usage (30271072K) : Executing rule dev_wf_mk_OFFGRID
+2022-12-05 23:10:02 +0000: Memory Usage (30271072K) : Executing rule metal1_blk_OFFGRID
+2022-12-05 23:10:03 +0000: Memory Usage (30271072K) : Executing rule metal2_blk_OFFGRID
+2022-12-05 23:10:03 +0000: Memory Usage (30271072K) : Executing rule metal3_blk_OFFGRID
+2022-12-05 23:10:04 +0000: Memory Usage (30271072K) : Executing rule metal4_blk_OFFGRID
+2022-12-05 23:10:04 +0000: Memory Usage (30271072K) : Executing rule metal5_blk_OFFGRID
+2022-12-05 23:10:04 +0000: Memory Usage (30271072K) : Executing rule metalt_blk_OFFGRID
+2022-12-05 23:10:05 +0000: Memory Usage (30271072K) : Executing rule pr_bndry_OFFGRID
+2022-12-05 23:10:05 +0000: Memory Usage (30271072K) : Executing rule mdiode_OFFGRID
+2022-12-05 23:10:06 +0000: Memory Usage (30271072K) : Executing rule metal1_res_OFFGRID
+2022-12-05 23:10:06 +0000: Memory Usage (30271072K) : Executing rule metal2_res_OFFGRID
+2022-12-05 23:10:07 +0000: Memory Usage (30271072K) : Executing rule metal3_res_OFFGRID
+2022-12-05 23:10:07 +0000: Memory Usage (30271072K) : Executing rule metal4_res_OFFGRID
+2022-12-05 23:10:07 +0000: Memory Usage (30271072K) : Executing rule metal5_res_OFFGRID
+2022-12-05 23:10:08 +0000: Memory Usage (30271072K) : Executing rule metal6_res_OFFGRID
+2022-12-05 23:10:08 +0000: Memory Usage (30271072K) : Executing rule border_OFFGRID
+VmPeak: 30519012 kB
+VmHWM: 24532344 kB
+2022-12-05 23:10:09 +0000: Memory Usage (30271072K) : DRC Total Run time 15125.304887 seconds
diff --git a/mpw_precheck/logs/klayout_beol_check.total b/mpw_precheck/logs/klayout_beol_check.total
new file mode 100644
index 0000000..c227083
--- /dev/null
+++ b/mpw_precheck/logs/klayout_beol_check.total
@@ -0,0 +1 @@
+0
\ No newline at end of file
diff --git a/mpw_precheck/logs/klayout_feol_check.log b/mpw_precheck/logs/klayout_feol_check.log
new file mode 100644
index 0000000..fd4493f
--- /dev/null
+++ b/mpw_precheck/logs/klayout_feol_check.log
@@ -0,0 +1,235 @@
+2022-12-05 17:52:11 +0000: Memory Usage (543008K) : Starting running GF180MCU Klayout DRC runset on /root/ophelia_efpga/gds/user_project_wrapper.gds
+2022-12-05 17:52:11 +0000: Memory Usage (543008K) : Ruby Version for klayout: 2.0.0
+2022-12-05 17:52:13 +0000: Memory Usage (816828K) : Loading database to memory is complete.
+2022-12-05 17:52:13 +0000: Memory Usage (816828K) : GF180MCU Klayout DRC runset output at: /mnt/uffs/user/u9789_egorxe/design/ophelia_efpga/jobs/mpw_precheck/e91b7603-4cb2-40d3-9c9d-39f7dcd32d80/outputs/reports/klayout_feol_check.xml
+2022-12-05 17:52:13 +0000: Memory Usage (816828K) : Number of threads to use 4
+2022-12-05 17:52:13 +0000: Memory Usage (816828K) : flat mode is enabled.
+2022-12-05 17:52:13 +0000: Memory Usage (816828K) : Read in polygons from layers.
+2022-12-05 17:53:51 +0000: Memory Usage (2188248K) : Starting deriving base layers.
+2022-12-05 17:54:42 +0000: Memory Usage (3094852K) : Evaluate switches.
+2022-12-05 17:54:42 +0000: Memory Usage (3094852K) : FEOL is enabled.
+2022-12-05 17:54:42 +0000: Memory Usage (3094852K) : BEOL is disabled.
+2022-12-05 17:54:42 +0000: Memory Usage (3094852K) : connectivity rules are enabled.
+2022-12-05 17:54:42 +0000: Memory Usage (3094852K) : METAL_TOP Selected is 9K
+2022-12-05 17:54:42 +0000: Memory Usage (3094852K) : METAL_STACK Selected is 5LM
+2022-12-05 17:54:42 +0000: Memory Usage (3094852K) : Wedge enabled true
+2022-12-05 17:54:42 +0000: Memory Usage (3094852K) : Ball enabled true
+2022-12-05 17:54:42 +0000: Memory Usage (3094852K) : Gold enabled true
+2022-12-05 17:54:42 +0000: Memory Usage (3094852K) : MIM Option selected B
+/opt/checks/tech-files/gf180mcuC_mr.drc:543: warning: already initialized constant DRC::DRCEngine::OFFGRID
+/opt/checks/tech-files/gf180mcuC_mr.drc:463: warning: previous definition of OFFGRID was here
+2022-12-05 17:54:42 +0000: Memory Usage (3094852K) : Offgrid enabled true
+2022-12-05 17:54:42 +0000: Memory Usage (3094852K) : Construct connectivity for the design.
+2022-12-05 17:55:28 +0000: Memory Usage (3094852K) : Connectivity rules enabled, Netlist object will be generated.
+2022-12-05 17:57:43 +0000: Memory Usage (4486396K) : Total area of the design is 8997120.228799999 um^2.
+2022-12-05 17:57:43 +0000: Memory Usage (4486396K) : Total no. of polygons in the design is 11391089
+2022-12-05 17:57:43 +0000: Memory Usage (4486396K) : Initialization and base layers definition.
+2022-12-05 17:57:43 +0000: Memory Usage (4486396K) : Starting GF180MCU DRC rules.
+2022-12-05 17:57:43 +0000: Memory Usage (4486396K) : FEOL section
+2022-12-05 17:57:43 +0000: Memory Usage (4486396K) : Executing rule DN.1
+2022-12-05 17:57:43 +0000: Memory Usage (4486396K) : CONNECTIVITY_RULES section
+2022-12-05 17:57:43 +0000: Memory Usage (4486396K) : Executing rule DN.2a
+2022-12-05 17:57:44 +0000: Memory Usage (4486396K) : Executing rule DN.2b
+2022-12-05 17:57:46 +0000: Memory Usage (4486396K) : Executing rule DN.3
+2022-12-05 17:57:46 +0000: Memory Usage (4486396K) : Executing rule LPW.1_3.3V
+2022-12-05 17:57:46 +0000: Memory Usage (4486396K) : Executing rule LPW.1_5V
+2022-12-05 17:57:46 +0000: Memory Usage (4486396K) : CONNECTIVITY_RULES section
+2022-12-05 17:57:46 +0000: Memory Usage (4486396K) : Executing rule LPW.2a_3.3V
+2022-12-05 17:57:46 +0000: Memory Usage (4486396K) : Executing rule LPW.2a_5V
+2022-12-05 17:57:47 +0000: Memory Usage (4486396K) : Executing rule LPW.2b_3.3V
+2022-12-05 17:57:47 +0000: Memory Usage (4486396K) : Executing rule LPW.2b_5V
+2022-12-05 17:57:47 +0000: Memory Usage (4486396K) : Executing rule LPW.3_3.3V
+2022-12-05 17:57:47 +0000: Memory Usage (4486396K) : Executing rule LPW.3_5V
+2022-12-05 17:57:47 +0000: Memory Usage (4486396K) : Executing rule LPW.5_3.3V
+2022-12-05 17:57:47 +0000: Memory Usage (4486396K) : Executing rule LPW.5_5V
+2022-12-05 17:57:47 +0000: Memory Usage (4486396K) : Executing rule LPW.11
+2022-12-05 17:57:47 +0000: Memory Usage (4486396K) : Executing rule LPW.12
+2022-12-05 17:57:47 +0000: Memory Usage (4486396K) : Executing rule NW.1a_3.3V
+2022-12-05 17:57:48 +0000: Memory Usage (4486396K) : Executing rule NW.1a_5V
+2022-12-05 17:57:48 +0000: Memory Usage (4486396K) : Executing rule NW.1b_3.3V
+2022-12-05 17:57:48 +0000: Memory Usage (4486396K) : Executing rule NW.1b_5V
+2022-12-05 17:57:48 +0000: Memory Usage (4486396K) : CONNECTIVITY_RULES section
+2022-12-05 17:58:11 +0000: Memory Usage (4486396K) : Executing rule NW.2a_3.3V
+2022-12-05 17:58:11 +0000: Memory Usage (4486396K) : Executing rule NW.2a_5V
+2022-12-05 17:58:12 +0000: Memory Usage (4486396K) : Executing rule NW.2b_3.3V
+2022-12-05 17:58:12 +0000: Memory Usage (4486396K) : Executing rule NW.2b_5V
+2022-12-05 17:58:12 +0000: Memory Usage (4486396K) : Executing rule NW.3_3.3V
+2022-12-05 17:58:12 +0000: Memory Usage (4486396K) : Executing rule NW.3_5V
+2022-12-05 17:58:12 +0000: Memory Usage (4486396K) : Executing rule NW.4_3.3V
+2022-12-05 17:58:12 +0000: Memory Usage (4486396K) : Executing rule NW.4_5V
+2022-12-05 17:58:12 +0000: Memory Usage (4486396K) : Executing rule NW.5_3.3V
+2022-12-05 17:58:12 +0000: Memory Usage (4486396K) : Executing rule NW.5_5V
+2022-12-05 17:58:13 +0000: Memory Usage (4486396K) : Executing rule NW.6
+2022-12-05 17:58:13 +0000: Memory Usage (4486396K) : Executing rule DF.1a_3.3V
+2022-12-05 17:58:13 +0000: Memory Usage (4486396K) : Executing rule DF.1a_5V
+2022-12-05 17:58:14 +0000: Memory Usage (4486396K) : Executing rule DF.1c_3.3V
+2022-12-05 17:58:14 +0000: Memory Usage (4486396K) : Executing rule DF.1c_5V
+2022-12-05 17:59:02 +0000: Memory Usage (4486396K) : Executing rule DF.2a_3.3V
+2022-12-05 17:59:03 +0000: Memory Usage (4486396K) : Executing rule DF.2a_5V
+2022-12-05 17:59:15 +0000: Memory Usage (4568320K) : Executing rule DF.2b_3.3V
+2022-12-05 17:59:50 +0000: Memory Usage (5208752K) : Executing rule DF.2b_5V
+2022-12-05 18:00:23 +0000: Memory Usage (5216304K) : Executing rule DF.3a_3.3V
+2022-12-05 18:00:27 +0000: Memory Usage (5216304K) : Executing rule DF.3a_5V
+2022-12-05 18:00:54 +0000: Memory Usage (5216304K) : Executing rule DF.3b_3.3V
+2022-12-05 18:00:54 +0000: Memory Usage (5216304K) : Executing rule DF.3b_5V
+2022-12-05 18:00:54 +0000: Memory Usage (5216304K) : Executing rule DF.3c_3.3V
+2022-12-05 18:00:55 +0000: Memory Usage (5216304K) : Executing rule DF.3c_5V
+2022-12-05 18:01:01 +0000: Memory Usage (5216304K) : Executing rule DF.4a_3.3V
+2022-12-05 18:01:01 +0000: Memory Usage (5216304K) : Executing rule DF.4a_5V
+2022-12-05 18:01:01 +0000: Memory Usage (5216304K) : Executing rule DF.4b_3.3V
+2022-12-05 18:01:13 +0000: Memory Usage (5216304K) : Executing rule DF.4b_5V
+2022-12-05 18:01:24 +0000: Memory Usage (5216304K) : Executing rule DF.4c_3.3V
+2022-12-05 18:01:34 +0000: Memory Usage (5216304K) : Executing rule DF.4c_5V
+2022-12-05 18:01:43 +0000: Memory Usage (5216304K) : Executing rule DF.4d_3.3V
+2022-12-05 18:01:45 +0000: Memory Usage (5216304K) : Executing rule DF.4d_5V
+2022-12-05 18:01:46 +0000: Memory Usage (5216304K) : Executing rule DF.4e_3.3V
+2022-12-05 18:01:46 +0000: Memory Usage (5216304K) : Executing rule DF.4e_5V
+2022-12-05 18:01:47 +0000: Memory Usage (5216304K) : Executing rule DF.5_3.3V
+2022-12-05 18:01:55 +0000: Memory Usage (5280832K) : Executing rule DF.5_5V
+2022-12-05 18:02:03 +0000: Memory Usage (5294560K) : Executing rule DF.6_3.3V
+2022-12-05 18:02:09 +0000: Memory Usage (5563924K) : Executing rule DF.6_5V
+2022-12-05 18:02:16 +0000: Memory Usage (6013912K) : Executing rule DF.7_3.3V
+2022-12-05 18:02:16 +0000: Memory Usage (6013912K) : Executing rule DF.7_5V
+2022-12-05 18:02:16 +0000: Memory Usage (6013912K) : Executing rule DF.8_3.3V
+2022-12-05 18:02:16 +0000: Memory Usage (6013912K) : Executing rule DF.8_5V
+2022-12-05 18:02:17 +0000: Memory Usage (6013912K) : Executing rule DF.9_3.3V
+2022-12-05 18:02:17 +0000: Memory Usage (6013912K) : Executing rule DF.9_5V
+2022-12-05 18:02:17 +0000: Memory Usage (6013912K) : Executing rule DF.10_3.3V
+2022-12-05 18:02:17 +0000: Memory Usage (6013912K) : Executing rule DF.10_5V
+2022-12-05 18:02:18 +0000: Memory Usage (6013912K) : Executing rule DF.11_3.3V
+2022-12-05 18:02:18 +0000: Memory Usage (6013912K) : Executing rule DF.11_5V
+2022-12-05 18:02:18 +0000: Memory Usage (6013912K) : Executing rule DF.12_3.3V
+2022-12-05 18:02:36 +0000: Memory Usage (6244888K) : Executing rule DF.12_5V
+2022-12-05 18:03:07 +0000: Memory Usage (6342544K) : Executing rule DF.13_3.3V
+2022-12-05 18:04:10 +0000: Memory Usage (6339376K) : Executing rule DF.13_5V
+2022-12-05 18:04:48 +0000: Memory Usage (6339376K) : Executing rule DF.14_3.3V
+2022-12-05 18:06:08 +0000: Memory Usage (6410884K) : Executing rule DF.14_5V
+2022-12-05 18:07:04 +0000: Memory Usage (6588032K) : Executing rule DF.16_3.3V
+2022-12-05 18:07:05 +0000: Memory Usage (6588032K) : Executing rule DF.16_5V
+2022-12-05 18:07:10 +0000: Memory Usage (6650788K) : Executing rule DF.17_3.3V
+2022-12-05 18:07:10 +0000: Memory Usage (6650788K) : Executing rule DF.17_5V
+2022-12-05 18:07:10 +0000: Memory Usage (6650788K) : Executing rule DF.18_3.3V
+2022-12-05 18:07:10 +0000: Memory Usage (6650788K) : Executing rule DF.18_5V
+2022-12-05 18:07:10 +0000: Memory Usage (6650788K) : Executing rule DF.19_3.3V
+2022-12-05 18:07:11 +0000: Memory Usage (6650788K) : Executing rule DF.19_5V
+2022-12-05 18:07:11 +0000: Memory Usage (6650788K) : Executing rule DV.1
+2022-12-05 18:07:12 +0000: Memory Usage (6650788K) : Executing rule DV.2
+2022-12-05 18:07:12 +0000: Memory Usage (6650788K) : Executing rule DV.3
+2022-12-05 18:07:29 +0000: Memory Usage (6794400K) : Executing rule DV.5
+2022-12-05 18:07:37 +0000: Memory Usage (6794400K) : Executing rule DV.6
+2022-12-05 18:08:12 +0000: Memory Usage (7081596K) : Executing rule DV.7
+2022-12-05 18:08:28 +0000: Memory Usage (7081596K) : Executing rule DV.8
+2022-12-05 18:09:16 +0000: Memory Usage (7136772K) : Executing rule DV.9
+2022-12-05 18:09:34 +0000: Memory Usage (7136772K) : Executing rule PL.1_3.3V
+2022-12-05 18:09:43 +0000: Memory Usage (7265752K) : Executing rule PL.1_5V
+2022-12-05 18:09:52 +0000: Memory Usage (7346536K) : Executing rule PL.1a_3.3V
+2022-12-05 18:09:53 +0000: Memory Usage (7346536K) : Executing rule PL.1a_5V
+2022-12-05 18:09:53 +0000: Memory Usage (7346536K) : Executing rule PL.2_3.3V
+2022-12-05 18:13:02 +0000: Memory Usage (9153064K) : Executing rule PL.2_5V
+2022-12-05 18:13:02 +0000: Memory Usage (9153064K) : Executing rule PL.3a_3.3V
+2022-12-05 18:13:39 +0000: Memory Usage (9582084K) : Executing rule PL.3a_5V
+2022-12-05 18:14:16 +0000: Memory Usage (10163220K) : Executing rule PL.4_3.3V
+2022-12-05 18:14:22 +0000: Memory Usage (10571260K) : Executing rule PL.4_5V
+2022-12-05 18:14:28 +0000: Memory Usage (10661344K) : Executing rule PL.5a_3.3V
+2022-12-05 18:14:34 +0000: Memory Usage (10661344K) : Executing rule PL.5a_5V
+2022-12-05 18:14:40 +0000: Memory Usage (10743128K) : Executing rule PL.5b_3.3V
+2022-12-05 18:14:45 +0000: Memory Usage (10743128K) : Executing rule PL.5b_5V
+2022-12-05 18:15:43 +0000: Memory Usage (12024136K) : Executing rule PL.6
+2022-12-05 18:16:59 +0000: Memory Usage (14130492K) : Executing rule PL.7_3.3V
+2022-12-05 18:16:59 +0000: Memory Usage (14130492K) : Executing rule PL.7_5V
+2022-12-05 18:17:00 +0000: Memory Usage (14130492K) : Executing rule PL.9
+2022-12-05 18:17:15 +0000: Memory Usage (14242824K) : Executing rule PL.11
+2022-12-05 18:17:15 +0000: Memory Usage (14242824K) : Executing rule PL.12
+2022-12-05 18:17:47 +0000: Memory Usage (14718820K) : Executing rule NP.1
+2022-12-05 18:17:48 +0000: Memory Usage (14718820K) : Executing rule NP.2
+2022-12-05 18:17:48 +0000: Memory Usage (14718820K) : Executing rule NP.3a
+2022-12-05 18:17:59 +0000: Memory Usage (14718820K) : Executing rule NP.3bi
+2022-12-05 18:18:00 +0000: Memory Usage (14718820K) : Executing rule NP.3bii
+2022-12-05 18:18:03 +0000: Memory Usage (14718820K) : Executing rule NP.3ci
+2022-12-05 18:18:09 +0000: Memory Usage (14718820K) : Executing rule NP.3cii
+2022-12-05 18:18:11 +0000: Memory Usage (14718820K) : Executing rule NP.3d
+2022-12-05 18:18:14 +0000: Memory Usage (14735304K) : Executing rule NP.3e
+2022-12-05 18:18:17 +0000: Memory Usage (14735304K) : Executing rule NP.4a
+2022-12-05 18:18:50 +0000: Memory Usage (15252792K) : Executing rule NP.4b
+2022-12-05 18:18:53 +0000: Memory Usage (15220020K) : Executing rule NP.5a
+2022-12-05 18:19:16 +0000: Memory Usage (15474276K) : Executing rule NP.5b
+2022-12-05 18:19:31 +0000: Memory Usage (15539816K) : Executing rule NP.5ci
+2022-12-05 18:19:36 +0000: Memory Usage (15539816K) : Executing rule NP.5cii
+2022-12-05 18:19:39 +0000: Memory Usage (15539816K) : Executing rule NP.5di
+2022-12-05 18:19:46 +0000: Memory Usage (15554152K) : Executing rule NP.5dii
+2022-12-05 18:19:47 +0000: Memory Usage (15554152K) : Executing rule NP.6
+2022-12-05 18:20:31 +0000: Memory Usage (15850500K) : Executing rule NP.7
+2022-12-05 18:20:31 +0000: Memory Usage (15850500K) : Executing rule NP.8a
+2022-12-05 18:20:31 +0000: Memory Usage (15850500K) : Executing rule NP.8b
+2022-12-05 18:20:32 +0000: Memory Usage (15850500K) : Executing rule NP.9
+2022-12-05 18:20:32 +0000: Memory Usage (15850500K) : Executing rule NP.10
+2022-12-05 18:20:37 +0000: Memory Usage (15850500K) : Executing rule NP.11
+2022-12-05 18:20:38 +0000: Memory Usage (15850500K) : Executing rule NP.12
+2022-12-05 18:20:47 +0000: Memory Usage (15850500K) : Executing rule PP.1
+2022-12-05 18:20:48 +0000: Memory Usage (15850500K) : Executing rule PP.2
+2022-12-05 18:20:48 +0000: Memory Usage (15850500K) : Executing rule PP.3a
+2022-12-05 18:21:00 +0000: Memory Usage (16018512K) : Executing rule PP.3bi
+2022-12-05 18:21:01 +0000: Memory Usage (16018512K) : Executing rule PP.3bii
+2022-12-05 18:21:03 +0000: Memory Usage (16065168K) : Executing rule PP.3ci
+2022-12-05 18:21:08 +0000: Memory Usage (16113372K) : Executing rule PP.3cii
+2022-12-05 18:21:09 +0000: Memory Usage (16147716K) : Executing rule PP.3d
+2022-12-05 18:21:10 +0000: Memory Usage (16172292K) : Executing rule PP.3e
+2022-12-05 18:21:11 +0000: Memory Usage (16172292K) : Executing rule PP.4a
+2022-12-05 18:21:45 +0000: Memory Usage (16806044K) : Executing rule PP.4b
+2022-12-05 18:21:47 +0000: Memory Usage (16790056K) : Executing rule PP.5a
+2022-12-05 18:22:04 +0000: Memory Usage (17022304K) : Executing rule PP.5b
+2022-12-05 18:22:15 +0000: Memory Usage (17087844K) : Executing rule PP.5ci
+2022-12-05 18:22:17 +0000: Memory Usage (17087844K) : Executing rule PP.5cii
+2022-12-05 18:22:22 +0000: Memory Usage (17120616K) : Executing rule PP.5di
+2022-12-05 18:22:28 +0000: Memory Usage (17221888K) : Executing rule PP.5dii
+2022-12-05 18:22:33 +0000: Memory Usage (17166568K) : Executing rule PP.6
+2022-12-05 18:22:47 +0000: Memory Usage (17447204K) : Executing rule PP.7
+2022-12-05 18:22:47 +0000: Memory Usage (17447204K) : Executing rule PP.8a
+2022-12-05 18:22:47 +0000: Memory Usage (17447204K) : Executing rule PP.8b
+2022-12-05 18:22:48 +0000: Memory Usage (17447204K) : Executing rule PP.9
+2022-12-05 18:22:48 +0000: Memory Usage (17447204K) : Executing rule PP.10
+2022-12-05 18:22:54 +0000: Memory Usage (17478632K) : Executing rule PP.11
+2022-12-05 18:22:54 +0000: Memory Usage (17478632K) : Executing rule PP.12
+2022-12-05 18:23:04 +0000: Memory Usage (17639748K) : Executing rule SB.1
+2022-12-05 18:23:04 +0000: Memory Usage (17639748K) : Executing rule SB.2
+2022-12-05 18:23:04 +0000: Memory Usage (17639748K) : Executing rule SB.3
+2022-12-05 18:23:05 +0000: Memory Usage (17639748K) : Executing rule SB.4
+2022-12-05 18:23:05 +0000: Memory Usage (17639748K) : Executing rule SB.5a
+2022-12-05 18:23:31 +0000: Memory Usage (18179432K) : Executing rule SB.5b
+2022-12-05 18:23:31 +0000: Memory Usage (18179432K) : Executing rule SB.6
+2022-12-05 18:23:31 +0000: Memory Usage (18179432K) : Executing rule SB.7
+2022-12-05 18:23:32 +0000: Memory Usage (18179432K) : Executing rule SB.8
+2022-12-05 18:23:32 +0000: Memory Usage (18179432K) : Executing rule SB.9
+2022-12-05 18:23:32 +0000: Memory Usage (18179432K) : Executing rule SB.10
+2022-12-05 18:23:33 +0000: Memory Usage (18179432K) : Executing rule SB.11
+2022-12-05 18:23:33 +0000: Memory Usage (18179432K) : Executing rule SB.12
+2022-12-05 18:23:33 +0000: Memory Usage (18209756K) : Executing rule SB.13
+2022-12-05 18:23:34 +0000: Memory Usage (18209756K) : Executing rule SB.14a
+2022-12-05 18:23:46 +0000: Memory Usage (18337044K) : Executing rule SB.14b
+2022-12-05 18:23:52 +0000: Memory Usage (18391096K) : Executing rule SB.15a
+2022-12-05 18:25:09 +0000: Memory Usage (18961492K) : Executing rule SB.15b
+2022-12-05 18:25:09 +0000: Memory Usage (18961492K) : Executing rule SB.16
+2022-12-05 18:25:17 +0000: Memory Usage (19043416K) : Executing rule ESD.1
+2022-12-05 18:25:17 +0000: Memory Usage (19043416K) : Executing rule ESD.2
+2022-12-05 18:25:18 +0000: Memory Usage (19043416K) : Executing rule ESD.3a
+2022-12-05 18:25:18 +0000: Memory Usage (19043416K) : Executing rule ESD.3b
+2022-12-05 18:25:18 +0000: Memory Usage (19043416K) : Executing rule ESD.4a
+2022-12-05 18:25:19 +0000: Memory Usage (19043416K) : Executing rule ESD.4b
+2022-12-05 18:25:19 +0000: Memory Usage (19043416K) : Executing rule ESD.5a
+2022-12-05 18:25:20 +0000: Memory Usage (19043416K) : Executing rule ESD.5b
+2022-12-05 18:25:20 +0000: Memory Usage (19043416K) : Executing rule ESD.6
+2022-12-05 18:25:40 +0000: Memory Usage (19225352K) : Executing rule ESD.7
+2022-12-05 18:25:41 +0000: Memory Usage (19225352K) : Executing rule ESD.8
+2022-12-05 18:25:42 +0000: Memory Usage (19225352K) : Executing rule ESD.pl
+2022-12-05 18:25:43 +0000: Memory Usage (19292540K) : Executing rule ESD.9
+2022-12-05 18:25:43 +0000: Memory Usage (19292540K) : Executing rule ESD.10
+2022-12-05 18:25:43 +0000: Memory Usage (19292540K) : Executing rule CO.1
+2022-12-05 18:26:19 +0000: Memory Usage (20235388K) : Executing rule CO.2a
+2022-12-05 18:28:18 +0000: Memory Usage (21902996K) : Executing rule CO.2b
+2022-12-05 18:28:19 +0000: Memory Usage (21902996K) : Executing rule CO.3
+2022-12-05 18:29:10 +0000: Memory Usage (23931952K) : Executing rule CO.4
+2022-12-05 18:31:10 +0000: Memory Usage (27842620K) : Executing rule CO.5a
+2022-12-05 18:31:18 +0000: Memory Usage (27842620K) : Executing rule CO.5b
+2022-12-05 18:31:19 +0000: Memory Usage (27842620K) : Executing rule CO.6
+2022-12-05 18:42:17 +0000: Memory Usage (27842704K) : Executing rule CO.6a
+2022-12-05 18:57:52 +0000: Memory Usage (33008484K) : Executing rule CO.6b
diff --git a/mpw_precheck/logs/klayout_met_min_ca_density_check.log b/mpw_precheck/logs/klayout_met_min_ca_density_check.log
new file mode 100644
index 0000000..d0a1787
--- /dev/null
+++ b/mpw_precheck/logs/klayout_met_min_ca_density_check.log
@@ -0,0 +1,16 @@
+"input" in: gf180mcu_density.lydrc:15
+ Polygons (raw): 0 (flat) 0 (hierarchical)
+ Elapsed: 0.010s Memory: 792.00M
+"area" in: gf180mcu_density.lydrc:17
+ Elapsed: 0.010s Memory: 792.00M
+"polygons" in: gf180mcu_density.lydrc:19
+ Polygons (raw): 900295 (flat) 646 (hierarchical)
+ Elapsed: 0.120s Memory: 804.00M
+"area" in: gf180mcu_density.lydrc:19
+ Elapsed: 0.840s Memory: 816.00M
+comp_density is Infinity
+"output" in: gf180mcu_density.lydrc:22
+ Polygons (raw): 0 (flat) 0 (hierarchical)
+ Elapsed: 0.040s Memory: 816.00M
+Writing report database: /mnt/uffs/user/u9789_egorxe/design/ophelia_efpga/jobs/mpw_precheck/e91b7603-4cb2-40d3-9c9d-39f7dcd32d80/outputs/reports/klayout_met_min_ca_density_check.xml ..
+Total elapsed: 3.130s Memory: 795.00M
diff --git a/mpw_precheck/logs/klayout_met_min_ca_density_check.total b/mpw_precheck/logs/klayout_met_min_ca_density_check.total
new file mode 100644
index 0000000..c227083
--- /dev/null
+++ b/mpw_precheck/logs/klayout_met_min_ca_density_check.total
@@ -0,0 +1 @@
+0
\ No newline at end of file
diff --git a/mpw_precheck/logs/klayout_offgrid_check.log b/mpw_precheck/logs/klayout_offgrid_check.log
new file mode 100644
index 0000000..f1fafc9
--- /dev/null
+++ b/mpw_precheck/logs/klayout_offgrid_check.log
@@ -0,0 +1,349 @@
+2022-12-05 23:10:12 +0000: Memory Usage (543004K) : Starting running GF180MCU Klayout DRC runset on /root/ophelia_efpga/gds/user_project_wrapper.gds
+2022-12-05 23:10:12 +0000: Memory Usage (543004K) : Ruby Version for klayout: 2.0.0
+2022-12-05 23:10:14 +0000: Memory Usage (816816K) : Loading database to memory is complete.
+2022-12-05 23:10:14 +0000: Memory Usage (816816K) : GF180MCU Klayout DRC runset output at: /mnt/uffs/user/u9789_egorxe/design/ophelia_efpga/jobs/mpw_precheck/e91b7603-4cb2-40d3-9c9d-39f7dcd32d80/outputs/reports/klayout_offgrid_check.xml
+2022-12-05 23:10:14 +0000: Memory Usage (816816K) : Number of threads to use 4
+2022-12-05 23:10:14 +0000: Memory Usage (816816K) : flat mode is enabled.
+2022-12-05 23:10:14 +0000: Memory Usage (816816K) : Read in polygons from layers.
+2022-12-05 23:11:52 +0000: Memory Usage (2188232K) : Starting deriving base layers.
+2022-12-05 23:12:42 +0000: Memory Usage (3094820K) : Evaluate switches.
+2022-12-05 23:12:42 +0000: Memory Usage (3094820K) : FEOL is disabled.
+2022-12-05 23:12:42 +0000: Memory Usage (3094820K) : BEOL is disabled.
+2022-12-05 23:12:42 +0000: Memory Usage (3094820K) : connectivity rules are enabled.
+2022-12-05 23:12:42 +0000: Memory Usage (3094820K) : METAL_TOP Selected is 9K
+2022-12-05 23:12:42 +0000: Memory Usage (3094820K) : METAL_STACK Selected is 5LM
+2022-12-05 23:12:42 +0000: Memory Usage (3094820K) : Wedge enabled true
+2022-12-05 23:12:42 +0000: Memory Usage (3094820K) : Ball enabled true
+2022-12-05 23:12:43 +0000: Memory Usage (3094820K) : Gold enabled true
+2022-12-05 23:12:43 +0000: Memory Usage (3094820K) : MIM Option selected B
+/opt/checks/tech-files/gf180mcuC_mr.drc:543: warning: already initialized constant DRC::DRCEngine::OFFGRID
+/opt/checks/tech-files/gf180mcuC_mr.drc:463: warning: previous definition of OFFGRID was here
+2022-12-05 23:12:43 +0000: Memory Usage (3094820K) : Offgrid enabled true
+2022-12-05 23:12:43 +0000: Memory Usage (3094820K) : Connectivity rules enabled, Netlist object will be generated.
+2022-12-05 23:12:43 +0000: Memory Usage (3094820K) : Total area of the design is 8997120.228799999 um^2.
+2022-12-05 23:12:43 +0000: Memory Usage (3094820K) : Total no. of polygons in the design is 11391089
+2022-12-05 23:12:43 +0000: Memory Usage (3094820K) : Initialization and base layers definition.
+2022-12-05 23:12:43 +0000: Memory Usage (3094820K) : Starting GF180MCU DRC rules.
+2022-12-05 23:12:43 +0000: Memory Usage (3094820K) : Executing rule MC.1
+2022-12-05 23:12:43 +0000: Memory Usage (3094820K) : Executing rule MC.2
+2022-12-05 23:12:43 +0000: Memory Usage (3094820K) : Executing rule MC.3
+2022-12-05 23:12:43 +0000: Memory Usage (3094820K) : Executing rule MC.4
+2022-12-05 23:12:49 +0000: Memory Usage (3094820K) : Executing rule PRES.1
+2022-12-05 23:12:49 +0000: Memory Usage (3094820K) : Executing rule PRES.2
+2022-12-05 23:12:49 +0000: Memory Usage (3094820K) : Executing rule PRES.3
+2022-12-05 23:12:49 +0000: Memory Usage (3094820K) : Executing rule PRES.4
+2022-12-05 23:12:49 +0000: Memory Usage (3094820K) : Executing rule PRES.5
+2022-12-05 23:12:50 +0000: Memory Usage (3094820K) : Executing rule PRES.6
+2022-12-05 23:12:50 +0000: Memory Usage (3094820K) : Executing rule PRES.7
+2022-12-05 23:12:56 +0000: Memory Usage (3094820K) : Executing rule PRES.9a
+2022-12-05 23:12:56 +0000: Memory Usage (3094820K) : Executing rule PRES.9b
+2022-12-05 23:13:02 +0000: Memory Usage (3094820K) : Executing rule LRES.1
+2022-12-05 23:13:02 +0000: Memory Usage (3094820K) : Executing rule LRES.2
+2022-12-05 23:13:02 +0000: Memory Usage (3094820K) : Executing rule LRES.3
+2022-12-05 23:13:02 +0000: Memory Usage (3094820K) : Executing rule LRES.4
+2022-12-05 23:13:02 +0000: Memory Usage (3094820K) : Executing rule LRES.5
+2022-12-05 23:13:14 +0000: Memory Usage (3244532K) : Executing rule LRES.6
+2022-12-05 23:13:20 +0000: Memory Usage (3298236K) : Executing rule LRES.7
+2022-12-05 23:13:26 +0000: Memory Usage (3351956K) : Executing rule LRES.9a
+2022-12-05 23:13:26 +0000: Memory Usage (3351956K) : Executing rule LRES.9b
+2022-12-05 23:14:00 +0000: Memory Usage (3496104K) : Executing rule HRES.1
+2022-12-05 23:14:00 +0000: Memory Usage (3496104K) : Executing rule HRES.2
+2022-12-05 23:14:00 +0000: Memory Usage (3496104K) : Executing rule HRES.3
+2022-12-05 23:14:00 +0000: Memory Usage (3496104K) : Executing rule HRES.4
+2022-12-05 23:14:00 +0000: Memory Usage (3496104K) : Executing rule HRES.5
+2022-12-05 23:14:00 +0000: Memory Usage (3496104K) : Executing rule HRES.6
+2022-12-05 23:14:17 +0000: Memory Usage (3631584K) : Executing rule HRES.7
+2022-12-05 23:14:18 +0000: Memory Usage (3631584K) : Executing rule HRES.8
+2022-12-05 23:14:18 +0000: Memory Usage (3631584K) : Executing rule HRES.9
+2022-12-05 23:14:18 +0000: Memory Usage (3631584K) : Executing rule HRES.10
+2022-12-05 23:14:25 +0000: Memory Usage (3631584K) : Executing rule HRES.12a
+2022-12-05 23:14:25 +0000: Memory Usage (3631584K) : Executing rule HRES.12b
+2022-12-05 23:14:25 +0000: Memory Usage (3631584K) : MIM Capacitor Option B section
+2022-12-05 23:14:25 +0000: Memory Usage (3631584K) : Executing rule MIMTM.1
+2022-12-05 23:14:25 +0000: Memory Usage (3631584K) : Executing rule MIMTM.2
+2022-12-05 23:14:25 +0000: Memory Usage (3631584K) : Executing rule MIMTM.3
+2022-12-05 23:14:25 +0000: Memory Usage (3631584K) : Executing rule MIMTM.4
+2022-12-05 23:14:25 +0000: Memory Usage (3631584K) : Executing rule MIMTM.5
+2022-12-05 23:14:26 +0000: Memory Usage (3631584K) : Executing rule MIMTM.6
+2022-12-05 23:14:26 +0000: Memory Usage (3631584K) : Executing rule MIMTM.7
+2022-12-05 23:14:26 +0000: Memory Usage (3631584K) : Executing rule MIMTM.8a
+2022-12-05 23:14:27 +0000: Memory Usage (3631584K) : Executing rule MIMTM.8b
+2022-12-05 23:14:27 +0000: Memory Usage (3631584K) : Executing rule MIMTM.9
+2022-12-05 23:14:27 +0000: Memory Usage (3631584K) : Executing rule MIMTM.10
+2022-12-05 23:14:27 +0000: Memory Usage (3631584K) : Executing rule MIMTM.11
+2022-12-05 23:14:27 +0000: Memory Usage (3631584K) : Executing rule NAT.1
+2022-12-05 23:14:30 +0000: Memory Usage (3785976K) : Executing rule NAT.2
+2022-12-05 23:14:31 +0000: Memory Usage (3785976K) : Executing rule NAT.3
+2022-12-05 23:14:31 +0000: Memory Usage (3785976K) : Executing rule NAT.4
+2022-12-05 23:14:44 +0000: Memory Usage (3883780K) : Executing rule NAT.5
+2022-12-05 23:14:56 +0000: Memory Usage (4048148K) : CONNECTIVITY_RULES section
+2022-12-05 23:14:56 +0000: Memory Usage (4048148K) : Executing rule NAT.6
+2022-12-05 23:14:56 +0000: Memory Usage (4083164K) : Executing rule NAT.7
+2022-12-05 23:14:56 +0000: Memory Usage (4083164K) : Executing rule NAT.8
+2022-12-05 23:14:56 +0000: Memory Usage (4083164K) : Executing rule NAT.9
+2022-12-05 23:14:56 +0000: Memory Usage (4083164K) : Executing rule NAT.10
+2022-12-05 23:14:57 +0000: Memory Usage (4083164K) : Executing rule NAT.11
+2022-12-05 23:14:57 +0000: Memory Usage (4083164K) : Executing rule NAT.12
+2022-12-05 23:14:57 +0000: Memory Usage (4113488K) : Executing rule BJT.1
+2022-12-05 23:14:57 +0000: Memory Usage (4113488K) : Executing rule BJT.2
+2022-12-05 23:15:06 +0000: Memory Usage (4249072K) : Executing rule BJT.3
+2022-12-05 23:15:06 +0000: Memory Usage (4249072K) : Executing rule DE.2
+2022-12-05 23:15:06 +0000: Memory Usage (4249072K) : Executing rule DE.3
+2022-12-05 23:15:06 +0000: Memory Usage (4249072K) : Executing rule DE.4
+2022-12-05 23:15:11 +0000: Memory Usage (4357668K) : Executing rule LVS_BJT.1
+2022-12-05 23:15:11 +0000: Memory Usage (4357668K) : Executing rule O.DF.3a
+2022-12-05 23:15:12 +0000: Memory Usage (4357668K) : Executing rule O.DF.6
+2022-12-05 23:15:12 +0000: Memory Usage (4357668K) : Executing rule O.DF.9
+2022-12-05 23:15:12 +0000: Memory Usage (4357668K) : Executing rule O.PL.2
+2022-12-05 23:15:29 +0000: Memory Usage (4555428K) : Executing rule O.PL.3a
+2022-12-05 23:15:57 +0000: Memory Usage (4829292K) : Executing rule O.PL.4
+2022-12-05 23:15:57 +0000: Memory Usage (4829292K) : Executing rule O.SB.2
+2022-12-05 23:15:58 +0000: Memory Usage (4829292K) : Executing rule O.SB.3
+2022-12-05 23:15:58 +0000: Memory Usage (4829292K) : Executing rule O.SB.4
+2022-12-05 23:15:58 +0000: Memory Usage (4829292K) : Executing rule O.SB.5b_3.3V
+2022-12-05 23:15:58 +0000: Memory Usage (4829292K) : Executing rule O.SB.9
+2022-12-05 23:15:58 +0000: Memory Usage (4829292K) : Executing rule O.SB.11
+2022-12-05 23:15:58 +0000: Memory Usage (4829292K) : Executing rule O.SB.13_3.3V
+2022-12-05 23:15:58 +0000: Memory Usage (4829292K) : Executing rule O.SB.13_5V
+2022-12-05 23:15:58 +0000: Memory Usage (4829292K) : Executing rule O.CO.7
+2022-12-05 23:17:07 +0000: Memory Usage (8043652K) : Executing rule O.PL.ORT
+2022-12-05 23:17:55 +0000: Memory Usage (8043652K) : Executing rule EF.01
+2022-12-05 23:18:03 +0000: Memory Usage (8043652K) : Executing rule EF.02
+2022-12-05 23:18:03 +0000: Memory Usage (8043652K) : Executing rule EF.03
+2022-12-05 23:18:08 +0000: Memory Usage (8043652K) : Executing rule EF.04a
+2022-12-05 23:18:18 +0000: Memory Usage (8043652K) : Executing rule EF.04b
+2022-12-05 23:18:19 +0000: Memory Usage (8043652K) : Executing rule EF.04c
+2022-12-05 23:18:23 +0000: Memory Usage (8043652K) : Executing rule EF.04d
+2022-12-05 23:18:23 +0000: Memory Usage (8043652K) : Executing rule EF.05
+2022-12-05 23:18:34 +0000: Memory Usage (8043652K) : Executing rule EF.06
+2022-12-05 23:18:34 +0000: Memory Usage (8043652K) : Executing rule EF.07
+2022-12-05 23:18:35 +0000: Memory Usage (8043652K) : Executing rule EF.08
+2022-12-05 23:18:35 +0000: Memory Usage (8043652K) : Executing rule EF.09
+2022-12-05 23:18:35 +0000: Memory Usage (8043652K) : Executing rule EF.10
+2022-12-05 23:18:35 +0000: Memory Usage (8043652K) : Executing rule EF.11
+2022-12-05 23:18:53 +0000: Memory Usage (8043652K) : Executing rule EF.12
+2022-12-05 23:18:55 +0000: Memory Usage (8043652K) : Executing rule EF.13
+2022-12-05 23:18:56 +0000: Memory Usage (8043652K) : Executing rule EF.14
+2022-12-05 23:18:56 +0000: Memory Usage (8043652K) : Executing rule EF.15
+2022-12-05 23:18:57 +0000: Memory Usage (8043652K) : Executing rule EF.16a
+2022-12-05 23:18:58 +0000: Memory Usage (8043652K) : Executing rule EF.16b
+2022-12-05 23:18:59 +0000: Memory Usage (8043652K) : Executing rule EF.17
+2022-12-05 23:18:59 +0000: Memory Usage (8043652K) : Executing rule EF.18
+2022-12-06 01:03:53 +0000: Memory Usage (8739032K) : Executing rule EF.19
+2022-12-06 02:32:54 +0000: Memory Usage (8739032K) : Executing rule EF.20
+2022-12-06 02:33:01 +0000: Memory Usage (8739032K) : Executing rule EF.21
+2022-12-06 02:33:01 +0000: Memory Usage (8739032K) : Executing rule EF.22a
+2022-12-06 02:33:01 +0000: Memory Usage (8739032K) : Executing rule EF.22b
+2022-12-06 02:33:02 +0000: Memory Usage (8739032K) : Executing rule MDN.1
+2022-12-06 02:33:02 +0000: Memory Usage (8739032K) : CONNECTIVITY_RULES section
+2022-12-06 02:33:02 +0000: Memory Usage (8739032K) : Executing rule MDN.2a
+2022-12-06 02:33:02 +0000: Memory Usage (8739032K) : Executing rule MDN.2b
+2022-12-06 02:33:15 +0000: Memory Usage (8739032K) : Executing rule MDN.3a
+2022-12-06 02:33:15 +0000: Memory Usage (8739032K) : Executing rule MDN.3b
+2022-12-06 02:33:15 +0000: Memory Usage (8739032K) : Executing rule MDN.4a
+2022-12-06 02:33:15 +0000: Memory Usage (8739032K) : Executing rule MDN.4b
+2022-12-06 02:33:18 +0000: Memory Usage (8739032K) : Executing rule MDN.5ai
+2022-12-06 02:33:18 +0000: Memory Usage (8739032K) : Executing rule MDN.5aii
+2022-12-06 02:33:19 +0000: Memory Usage (8739032K) : Executing rule MDN.5b
+2022-12-06 02:33:19 +0000: Memory Usage (8739032K) : Executing rule MDN.5c
+2022-12-06 02:33:19 +0000: Memory Usage (8739032K) : Executing rule MDN.6
+2022-12-06 02:33:34 +0000: Memory Usage (8739032K) : Executing rule MDN.6a
+2022-12-06 02:33:34 +0000: Memory Usage (8739032K) : Executing rule MDN.7
+2022-12-06 02:33:34 +0000: Memory Usage (8739032K) : Executing rule MDN.7a
+2022-12-06 02:33:34 +0000: Memory Usage (8739032K) : CONNECTIVITY_RULES section
+2022-12-06 02:33:34 +0000: Memory Usage (8739032K) : Executing rule MDN.8a
+2022-12-06 02:33:35 +0000: Memory Usage (8739032K) : Executing rule MDN.8b
+2022-12-06 02:33:35 +0000: Memory Usage (8739032K) : Executing rule MDN.9
+2022-12-06 02:34:00 +0000: Memory Usage (8739032K) : Executing rule MDN.10a
+2022-12-06 02:34:00 +0000: Memory Usage (8739032K) : Executing rule MDN.10b
+2022-12-06 02:34:15 +0000: Memory Usage (8739032K) : Executing rule MDN.10c
+2022-12-06 02:34:49 +0000: Memory Usage (8739032K) : Executing rule MDN.10d
+2022-12-06 02:34:49 +0000: Memory Usage (8739032K) : Executing rule MDN.10ei
+2022-12-06 02:35:00 +0000: Memory Usage (8739032K) : Executing rule MDN.10eii
+2022-12-06 02:35:06 +0000: Memory Usage (8739032K) : Executing rule MDN.10f
+2022-12-06 02:35:16 +0000: Memory Usage (8969496K) : Executing rule MDN.11
+2022-12-06 02:35:35 +0000: Memory Usage (8989424K) : Executing rule MDN.12
+2022-12-06 02:35:35 +0000: Memory Usage (8989424K) : Executing rule MDN.13a
+2022-12-06 02:36:13 +0000: Memory Usage (9196004K) : Executing rule MDN.13b
+2022-12-06 02:36:13 +0000: Memory Usage (9196004K) : Executing rule MDN.13c
+2022-12-06 02:36:42 +0000: Memory Usage (9502380K) : Executing rule MDN.13d
+2022-12-06 02:36:42 +0000: Memory Usage (9502380K) : Executing rule MDN.14
+2022-12-06 02:36:42 +0000: Memory Usage (9502380K) : Executing rule MDN.15a
+2022-12-06 02:36:43 +0000: Memory Usage (9502380K) : Executing rule MDN.15b
+2022-12-06 02:37:03 +0000: Memory Usage (9715500K) : Executing rule MDN.17
+2022-12-06 02:37:21 +0000: Memory Usage (9777332K) : Executing rule MDP.1
+2022-12-06 02:37:33 +0000: Memory Usage (10038464K) : Executing rule MDP.1a
+2022-12-06 03:01:23 +0000: Memory Usage (21979768K) : Executing rule MDP.2
+2022-12-06 03:01:35 +0000: Memory Usage (22073980K) : Executing rule MDP.3
+2022-12-06 03:01:38 +0000: Memory Usage (22073980K) : Executing rule MDP.3ai
+2022-12-06 03:01:38 +0000: Memory Usage (22073980K) : Executing rule MDP.3aii
+2022-12-06 03:01:39 +0000: Memory Usage (22073980K) : Executing rule MDP.3b
+2022-12-06 03:01:39 +0000: Memory Usage (22073980K) : Executing rule MDP.3c
+2022-12-06 03:01:39 +0000: Memory Usage (22073980K) : Executing rule MDP.3d
+2022-12-06 03:01:40 +0000: Memory Usage (22080324K) : Executing rule MDP.4
+2022-12-06 03:03:04 +0000: Memory Usage (22138256K) : Executing rule MDP.4a
+2022-12-06 03:03:04 +0000: Memory Usage (22138256K) : Executing rule MDP.4b
+2022-12-06 03:03:04 +0000: Memory Usage (22138256K) : Executing rule MDP.5
+2022-12-06 03:03:19 +0000: Memory Usage (22285908K) : Executing rule MDP.5a
+2022-12-06 03:03:19 +0000: Memory Usage (22285908K) : Executing rule MDP.6
+2022-12-06 03:03:19 +0000: Memory Usage (22285908K) : Executing rule MDP.6a
+2022-12-06 03:03:20 +0000: Memory Usage (22285908K) : Executing rule MDP.7
+2022-12-06 03:03:20 +0000: Memory Usage (22285908K) : Executing rule MDP.8
+2022-12-06 03:03:20 +0000: Memory Usage (22285908K) : Executing rule MDP.9a
+2022-12-06 03:03:21 +0000: Memory Usage (22345404K) : Executing rule MDP.9b
+2022-12-06 03:03:22 +0000: Memory Usage (22345404K) : Executing rule MDP.9c
+2022-12-06 03:03:34 +0000: Memory Usage (22508744K) : Executing rule MDP.9d
+2022-12-06 03:05:25 +0000: Memory Usage (22772188K) : Executing rule MDP.9ei
+2022-12-06 03:06:07 +0000: Memory Usage (22871860K) : Executing rule MDP.9eii
+2022-12-06 03:06:07 +0000: Memory Usage (22871860K) : Executing rule MDP.9f
+2022-12-06 03:06:46 +0000: Memory Usage (22970164K) : Executing rule MDP.10
+2022-12-06 03:06:47 +0000: Memory Usage (22970164K) : CONNECTIVITY_RULES section
+2022-12-06 03:06:47 +0000: Memory Usage (22970164K) : Executing rule MDP.10a
+2022-12-06 03:06:47 +0000: Memory Usage (22970164K) : Executing rule MDP.10b
+2022-12-06 03:06:48 +0000: Memory Usage (22970164K) : Executing rule MDP.11
+2022-12-06 03:06:49 +0000: Memory Usage (23057944K) : Executing rule MDP.12
+2022-12-06 03:07:09 +0000: Memory Usage (23093124K) : Executing rule MDP.13a
+2022-12-06 03:07:29 +0000: Memory Usage (23175832K) : Executing rule MDP.13b
+2022-12-06 03:07:29 +0000: Memory Usage (23175832K) : Executing rule MDP.13c
+2022-12-06 03:07:39 +0000: Memory Usage (23204504K) : Executing rule MDP.15
+2022-12-06 03:07:39 +0000: Memory Usage (23204504K) : Executing rule MDP.16a
+2022-12-06 03:07:40 +0000: Memory Usage (23204504K) : Executing rule MDP.16b
+2022-12-06 03:07:43 +0000: Memory Usage (23209808K) : Executing rule MDP.17a
+2022-12-06 03:07:44 +0000: Memory Usage (23209808K) : Executing rule MDP.17c
+2022-12-06 03:07:44 +0000: Memory Usage (23209808K) : Executing rule Y.NW.2b_3.3V
+2022-12-06 03:07:44 +0000: Memory Usage (23209808K) : Executing rule Y.NW.2b_5V
+2022-12-06 03:07:45 +0000: Memory Usage (23209808K) : Executing rule Y.DF.6_5V
+2022-12-06 03:07:45 +0000: Memory Usage (23244824K) : Executing rule Y.DF.16_3.3V
+2022-12-06 03:07:49 +0000: Memory Usage (23244824K) : Executing rule Y.DF.16_5V
+2022-12-06 03:07:53 +0000: Memory Usage (23244824K) : Executing rule Y.PL.1_3.3V
+2022-12-06 03:08:00 +0000: Memory Usage (23289964K) : Executing rule Y.PL.1_5V
+2022-12-06 03:08:07 +0000: Memory Usage (23319928K) : Executing rule Y.PL.2_3.3V
+2022-12-06 03:08:25 +0000: Memory Usage (23517688K) : Executing rule Y.PL.2_5V
+2022-12-06 03:08:42 +0000: Memory Usage (23715448K) : Executing rule Y.PL.4_5V
+2022-12-06 03:08:43 +0000: Memory Usage (23715448K) : Executing rule Y.PL.5a_3.3V
+2022-12-06 03:08:43 +0000: Memory Usage (23715448K) : Executing rule Y.PL.5a_5V
+2022-12-06 03:08:44 +0000: Memory Usage (23715448K) : Executing rule Y.PL.5b_3.3V
+2022-12-06 03:08:44 +0000: Memory Usage (23715448K) : Executing rule Y.PL.5b_5V
+2022-12-06 03:08:44 +0000: Memory Usage (23715448K) : Executing rule S.DF.4c_MV
+2022-12-06 03:08:45 +0000: Memory Usage (23733912K) : Executing rule S.DF.6_MV
+2022-12-06 03:08:45 +0000: Memory Usage (23733912K) : Executing rule S.DF.7_MV
+2022-12-06 03:08:46 +0000: Memory Usage (23733912K) : Executing rule S.DF.8_MV
+2022-12-06 03:08:46 +0000: Memory Usage (23733912K) : Executing rule S.DF.16_MV
+2022-12-06 03:08:49 +0000: Memory Usage (23764268K) : Executing rule S.PL.5a_MV
+2022-12-06 03:08:50 +0000: Memory Usage (23764268K) : Executing rule S.PL.5b_MV
+2022-12-06 03:08:50 +0000: Memory Usage (23764268K) : Executing rule S.CO.4_MV
+2022-12-06 03:08:50 +0000: Memory Usage (23764268K) : Executing rule S.DF.4c_LV
+2022-12-06 03:08:51 +0000: Memory Usage (23799116K) : Executing rule S.DF.16_LV
+2022-12-06 03:08:54 +0000: Memory Usage (23829472K) : Executing rule S.CO.3_LV
+2022-12-06 03:08:55 +0000: Memory Usage (23829472K) : Executing rule S.CO.4_LV
+2022-12-06 03:08:55 +0000: Memory Usage (23829472K) : Executing rule S.CO.6_ii_LV
+2022-12-06 03:08:55 +0000: Memory Usage (23829472K) : Executing rule S.M1.1_LV
+2022-12-06 03:08:56 +0000: Memory Usage (23829472K) : OFFGRID-ANGLES section
+2022-12-06 03:08:56 +0000: Memory Usage (23829472K) : Executing rule comp_OFFGRID
+2022-12-06 03:08:57 +0000: Memory Usage (23829472K) : Executing rule dnwell_OFFGRID
+2022-12-06 03:08:57 +0000: Memory Usage (23829472K) : Executing rule nwell_OFFGRID
+2022-12-06 03:08:57 +0000: Memory Usage (23829472K) : Executing rule lvpwell_OFFGRID
+2022-12-06 03:08:58 +0000: Memory Usage (23829472K) : Executing rule dualgate_OFFGRID
+2022-12-06 03:08:58 +0000: Memory Usage (23829472K) : Executing rule poly2_OFFGRID
+2022-12-06 03:08:59 +0000: Memory Usage (23829472K) : Executing rule nplus_OFFGRID
+2022-12-06 03:08:59 +0000: Memory Usage (23829472K) : Executing rule pplus_OFFGRID
+2022-12-06 03:09:00 +0000: Memory Usage (23829472K) : Executing rule sab_OFFGRID
+2022-12-06 03:09:00 +0000: Memory Usage (23829472K) : Executing rule esd_OFFGRID
+2022-12-06 03:09:00 +0000: Memory Usage (23829472K) : Executing rule contact_OFFGRID
+2022-12-06 03:09:03 +0000: Memory Usage (23829472K) : Executing rule metal1_OFFGRID
+2022-12-06 03:09:04 +0000: Memory Usage (23829472K) : Executing rule via1_OFFGRID
+2022-12-06 03:09:05 +0000: Memory Usage (23829472K) : Executing rule metal2_OFFGRID
+2022-12-06 03:09:06 +0000: Memory Usage (23829472K) : Executing rule via2_OFFGRID
+2022-12-06 03:09:07 +0000: Memory Usage (23829472K) : Executing rule metal3_OFFGRID
+2022-12-06 03:09:08 +0000: Memory Usage (23829472K) : Executing rule via3_OFFGRID
+2022-12-06 03:09:09 +0000: Memory Usage (23829472K) : Executing rule metal4_OFFGRID
+2022-12-06 03:09:09 +0000: Memory Usage (23829472K) : Executing rule via4_OFFGRID
+2022-12-06 03:09:10 +0000: Memory Usage (23829472K) : Executing rule metal5_OFFGRID
+2022-12-06 03:09:10 +0000: Memory Usage (23829472K) : Executing rule via5_OFFGRID
+2022-12-06 03:09:10 +0000: Memory Usage (23829472K) : Executing rule metaltop_OFFGRID
+2022-12-06 03:09:11 +0000: Memory Usage (23829472K) : Executing rule pad_OFFGRID
+2022-12-06 03:09:11 +0000: Memory Usage (23829472K) : Executing rule resistor_OFFGRID
+2022-12-06 03:09:11 +0000: Memory Usage (23829472K) : Executing rule fhres_OFFGRID
+2022-12-06 03:09:12 +0000: Memory Usage (23829472K) : Executing rule fusetop_OFFGRID
+2022-12-06 03:09:12 +0000: Memory Usage (23829472K) : Executing rule fusewindow_d_OFFGRID
+2022-12-06 03:09:12 +0000: Memory Usage (23829472K) : Executing rule polyfuse_OFFGRID
+2022-12-06 03:09:13 +0000: Memory Usage (23829472K) : Executing rule mvsd_OFFGRID
+2022-12-06 03:09:13 +0000: Memory Usage (23829472K) : Executing rule mvpsd_OFFGRID
+2022-12-06 03:09:13 +0000: Memory Usage (23829472K) : Executing rule nat_OFFGRID
+2022-12-06 03:09:14 +0000: Memory Usage (23829472K) : Executing rule comp_dummy_OFFGRID
+2022-12-06 03:09:14 +0000: Memory Usage (23829472K) : Executing rule poly2_dummy_OFFGRID
+2022-12-06 03:09:15 +0000: Memory Usage (23829472K) : Executing rule metal1_dummy_OFFGRID
+2022-12-06 03:09:15 +0000: Memory Usage (23829472K) : Executing rule metal2_dummy_OFFGRID
+2022-12-06 03:09:15 +0000: Memory Usage (23829472K) : Executing rule metal3_dummy_OFFGRID
+2022-12-06 03:09:16 +0000: Memory Usage (23829472K) : Executing rule metal4_dummy_OFFGRID
+2022-12-06 03:09:16 +0000: Memory Usage (23829472K) : Executing rule metal5_dummy_OFFGRID
+2022-12-06 03:09:16 +0000: Memory Usage (23829472K) : Executing rule metaltop_dummy_OFFGRID
+2022-12-06 03:09:17 +0000: Memory Usage (23829472K) : Executing rule comp_label_OFFGRID
+2022-12-06 03:09:17 +0000: Memory Usage (23829472K) : Executing rule poly2_label_OFFGRID
+2022-12-06 03:09:17 +0000: Memory Usage (23829472K) : Executing rule metal1_label_OFFGRID
+2022-12-06 03:09:18 +0000: Memory Usage (23829472K) : Executing rule metal2_label_OFFGRID
+2022-12-06 03:09:18 +0000: Memory Usage (23829472K) : Executing rule metal3_label_OFFGRID
+2022-12-06 03:09:18 +0000: Memory Usage (23829472K) : Executing rule metal4_label_OFFGRID
+2022-12-06 03:09:19 +0000: Memory Usage (23829472K) : Executing rule metal5_label_OFFGRID
+2022-12-06 03:09:19 +0000: Memory Usage (23829472K) : Executing rule metaltop_label_OFFGRID
+2022-12-06 03:09:19 +0000: Memory Usage (23829472K) : Executing rule metal1_slot_OFFGRID
+2022-12-06 03:09:20 +0000: Memory Usage (23829472K) : Executing rule metal2_slot_OFFGRID
+2022-12-06 03:09:20 +0000: Memory Usage (23829472K) : Executing rule metal3_slot_OFFGRID
+2022-12-06 03:09:20 +0000: Memory Usage (23829472K) : Executing rule metal4_slot_OFFGRID
+2022-12-06 03:09:21 +0000: Memory Usage (23829472K) : Executing rule metal5_slot_OFFGRID
+2022-12-06 03:09:21 +0000: Memory Usage (23829472K) : Executing rule metaltop_slot_OFFGRID
+2022-12-06 03:09:22 +0000: Memory Usage (23829472K) : Executing rule ubmpperi_OFFGRID
+2022-12-06 03:09:22 +0000: Memory Usage (23829472K) : Executing rule ubmparray_OFFGRID
+2022-12-06 03:09:22 +0000: Memory Usage (23829472K) : Executing rule ubmeplate_OFFGRID
+2022-12-06 03:09:23 +0000: Memory Usage (23829472K) : Executing rule schottky_diode_OFFGRID
+2022-12-06 03:09:23 +0000: Memory Usage (23829472K) : Executing rule zener_OFFGRID
+2022-12-06 03:09:23 +0000: Memory Usage (23829472K) : Executing rule res_mk_OFFGRID
+2022-12-06 03:09:24 +0000: Memory Usage (23829472K) : Executing rule opc_drc_OFFGRID
+2022-12-06 03:09:24 +0000: Memory Usage (23829472K) : Executing rule ndmy_OFFGRID
+2022-12-06 03:09:24 +0000: Memory Usage (23829472K) : Executing rule pmndmy_OFFGRID
+2022-12-06 03:09:25 +0000: Memory Usage (23829472K) : Executing rule v5_xtor_OFFGRID
+2022-12-06 03:09:25 +0000: Memory Usage (23829472K) : Executing rule cap_mk_OFFGRID
+2022-12-06 03:09:25 +0000: Memory Usage (23829472K) : Executing rule mos_cap_mk_OFFGRID
+2022-12-06 03:09:26 +0000: Memory Usage (23829472K) : Executing rule ind_mk_OFFGRID
+2022-12-06 03:09:26 +0000: Memory Usage (23829472K) : Executing rule diode_mk_OFFGRID
+2022-12-06 03:09:27 +0000: Memory Usage (23829472K) : Executing rule drc_bjt_OFFGRID
+2022-12-06 03:09:27 +0000: Memory Usage (23829472K) : Executing rule lvs_bjt_OFFGRID
+2022-12-06 03:09:27 +0000: Memory Usage (23829472K) : Executing rule mim_l_mk_OFFGRID
+2022-12-06 03:09:28 +0000: Memory Usage (23829472K) : Executing rule latchup_mk_OFFGRID
+2022-12-06 03:09:28 +0000: Memory Usage (23829472K) : Executing rule guard_ring_mk_OFFGRID
+2022-12-06 03:09:28 +0000: Memory Usage (23829472K) : Executing rule otp_mk_OFFGRID
+2022-12-06 03:09:29 +0000: Memory Usage (23829472K) : Executing rule mtpmark_OFFGRID
+2022-12-06 03:09:29 +0000: Memory Usage (23829472K) : Executing rule neo_ee_mk_OFFGRID
+2022-12-06 03:09:29 +0000: Memory Usage (23829472K) : Executing rule sramcore_OFFGRID
+2022-12-06 03:09:30 +0000: Memory Usage (23829472K) : Executing rule lvs_rf_OFFGRID
+2022-12-06 03:09:30 +0000: Memory Usage (23829472K) : Executing rule lvs_drain_OFFGRID
+2022-12-06 03:09:30 +0000: Memory Usage (23829472K) : Executing rule hvpolyrs_OFFGRID
+2022-12-06 03:09:31 +0000: Memory Usage (23829472K) : Executing rule lvs_io_OFFGRID
+2022-12-06 03:09:31 +0000: Memory Usage (23829472K) : Executing rule probe_mk_OFFGRID
+2022-12-06 03:09:31 +0000: Memory Usage (23829472K) : Executing rule esd_mk_OFFGRID
+2022-12-06 03:09:32 +0000: Memory Usage (23829472K) : Executing rule lvs_source_OFFGRID
+2022-12-06 03:09:32 +0000: Memory Usage (23829472K) : Executing rule well_diode_mk_OFFGRID
+2022-12-06 03:09:33 +0000: Memory Usage (23829472K) : Executing rule ldmos_xtor_OFFGRID
+2022-12-06 03:09:33 +0000: Memory Usage (23829472K) : Executing rule plfuse_OFFGRID
+2022-12-06 03:09:33 +0000: Memory Usage (23829472K) : Executing rule efuse_mk_OFFGRID
+2022-12-06 03:09:34 +0000: Memory Usage (23829472K) : Executing rule mcell_feol_mk_OFFGRID
+2022-12-06 03:09:34 +0000: Memory Usage (23829472K) : Executing rule ymtp_mk_OFFGRID
+2022-12-06 03:09:34 +0000: Memory Usage (23829472K) : Executing rule dev_wf_mk_OFFGRID
+2022-12-06 03:09:35 +0000: Memory Usage (23829472K) : Executing rule metal1_blk_OFFGRID
+2022-12-06 03:09:35 +0000: Memory Usage (23829472K) : Executing rule metal2_blk_OFFGRID
+2022-12-06 03:09:35 +0000: Memory Usage (23829472K) : Executing rule metal3_blk_OFFGRID
+2022-12-06 03:09:36 +0000: Memory Usage (23829472K) : Executing rule metal4_blk_OFFGRID
+2022-12-06 03:09:36 +0000: Memory Usage (23829472K) : Executing rule metal5_blk_OFFGRID
+2022-12-06 03:09:36 +0000: Memory Usage (23829472K) : Executing rule metalt_blk_OFFGRID
+2022-12-06 03:09:37 +0000: Memory Usage (23829472K) : Executing rule pr_bndry_OFFGRID
+2022-12-06 03:09:37 +0000: Memory Usage (23829472K) : Executing rule mdiode_OFFGRID
+2022-12-06 03:09:37 +0000: Memory Usage (23829472K) : Executing rule metal1_res_OFFGRID
+2022-12-06 03:09:38 +0000: Memory Usage (23829472K) : Executing rule metal2_res_OFFGRID
+2022-12-06 03:09:38 +0000: Memory Usage (23829472K) : Executing rule metal3_res_OFFGRID
+2022-12-06 03:09:39 +0000: Memory Usage (23829472K) : Executing rule metal4_res_OFFGRID
+2022-12-06 03:09:39 +0000: Memory Usage (23829472K) : Executing rule metal5_res_OFFGRID
+2022-12-06 03:09:39 +0000: Memory Usage (23829472K) : Executing rule metal6_res_OFFGRID
+2022-12-06 03:09:40 +0000: Memory Usage (23829472K) : Executing rule border_OFFGRID
+VmPeak: 24076920 kB
+VmHWM: 19081960 kB
+2022-12-06 03:09:40 +0000: Memory Usage (23829472K) : DRC Total Run time 14368.276410 seconds
diff --git a/mpw_precheck/logs/klayout_offgrid_check.total b/mpw_precheck/logs/klayout_offgrid_check.total
new file mode 100644
index 0000000..c227083
--- /dev/null
+++ b/mpw_precheck/logs/klayout_offgrid_check.total
@@ -0,0 +1 @@
+0
\ No newline at end of file
diff --git a/mpw_precheck/logs/pdks.info b/mpw_precheck/logs/pdks.info
new file mode 100644
index 0000000..375c57b
--- /dev/null
+++ b/mpw_precheck/logs/pdks.info
@@ -0,0 +1,2 @@
+Open PDKs 120b0bd69c745825a0b8b76f364043a1cd08bb6a
+GF180MCUC PDK a897aa30369d3bcec87d9d50ce9b01f320f854ef
\ No newline at end of file
diff --git a/mpw_precheck/logs/precheck.log b/mpw_precheck/logs/precheck.log
new file mode 100644
index 0000000..23908a8
--- /dev/null
+++ b/mpw_precheck/logs/precheck.log
@@ -0,0 +1,45 @@
+2022-12-05 17:51:19 - [INFO] - {{Project Git Info}} Repository: https://github.com/egorxe/ophelia_fpga_openmpw.git | Branch: main | Commit: 4b407974710e71322cb6270d812c2b44b3e13cbb
+2022-12-05 17:51:19 - [INFO] - {{EXTRACTING FILES}} Extracting compressed files in: ophelia_efpga
+2022-12-05 17:51:20 - [INFO] - {{Project Type Info}} digital
+2022-12-05 17:51:20 - [INFO] - {{Project GDS Info}} user_project_wrapper: a5b78e1dee205485a829ba28cdd3753d8636ecf7
+2022-12-05 17:51:21 - [INFO] - {{Tools Info}} KLayout: v0.27.12 | Magic: v8.3.340
+2022-12-05 17:51:21 - [INFO] - {{PDKs Info}} GF180MCUC: a897aa30369d3bcec87d9d50ce9b01f320f854ef | Open PDKs: 120b0bd69c745825a0b8b76f364043a1cd08bb6a
+2022-12-05 17:51:21 - [INFO] - {{START}} Precheck Started, the full log 'precheck.log' will be located in 'ophelia_efpga/jobs/mpw_precheck/e91b7603-4cb2-40d3-9c9d-39f7dcd32d80/logs'
+2022-12-05 17:51:21 - [INFO] - {{PRECHECK SEQUENCE}} Precheck will run the following checks: [License, GPIO-Defines, XOR, Klayout FEOL, Klayout BEOL, Klayout Offgrid, Klayout Metal Minimum Clear Area Density]
+2022-12-05 17:51:21 - [INFO] - {{STEP UPDATE}} Executing Check 1 of 7: License
+2022-12-05 17:51:22 - [INFO] - An approved LICENSE (Apache-2.0) was found in ophelia_efpga.
+2022-12-05 17:51:22 - [INFO] - {{MAIN LICENSE CHECK PASSED}} An approved LICENSE was found in project root.
+2022-12-05 17:51:22 - [INFO] - An approved LICENSE (Apache-2.0) was found in ophelia_efpga.
+2022-12-05 17:51:22 - [INFO] - {{SUBMODULES LICENSE CHECK PASSED}} No prohibited LICENSE file(s) was found in project submodules
+2022-12-05 17:51:23 - [WARNING] - {{SPDX COMPLIANCE CHECK FAILED}} Found 16 non-compliant file(s) with the SPDX Standard.
+2022-12-05 17:51:23 - [INFO] - SPDX COMPLIANCE: NON-COMPLIANT FILE(S) PREVIEW: ['ophelia_efpga/openlane/config.tcl', 'ophelia_efpga/openlane/user_project_wrapper.sdc', 'ophelia_efpga/openlane/efuse_ctrl/config.tcl', 'ophelia_efpga/openlane/fpga_struct_block/config.tcl', 'ophelia_efpga/openlane/fpga_struct_block/fpga_struct_block.sdc', 'ophelia_efpga/sdf/efuse_ctrl.sdf', 'ophelia_efpga/sdf/fpga_struct_block.sdf', 'ophelia_efpga/sdf/user_project_wrapper.sdf', 'ophelia_efpga/verilog/includes/includes.gl+sdf.caravel_user_project', 'ophelia_efpga/verilog/includes/includes.gl.caravel_user_project', 'ophelia_efpga/verilog/includes/includes.rtl.caravel_user_project', 'ophelia_efpga/verilog/rtl/ariel_fpga_top_fromvhdl.v', 'ophelia_efpga/verilog/rtl/fpga_tech.v', 'ophelia_efpga/verilog/rtl/efuse_ctrl/efuse_array_fromvhdl.v', 'ophelia_efpga/verilog/rtl/fpga_struct_block/fpga_struct_block_fromvhdl.v']
+2022-12-05 17:51:23 - [INFO] - For the full SPDX compliance report check: ophelia_efpga/jobs/mpw_precheck/e91b7603-4cb2-40d3-9c9d-39f7dcd32d80/logs/spdx_compliance_report.log
+2022-12-05 17:51:23 - [INFO] - {{STEP UPDATE}} Executing Check 2 of 7: GPIO-Defines
+2022-12-05 17:51:23 - [INFO] - GPIO-DEFINES: Checking verilog/rtl/user_defines.v, parsing files: ['/opt/checks/gpio_defines_check/verilog_assets/gpio_modes_base.v', 'ophelia_efpga/verilog/rtl/user_defines.v', '/opt/checks/gpio_defines_check/verilog_assets/gpio_modes_observe.v']
+2022-12-05 17:51:24 - [INFO] - GPIO-DEFINES report path: ophelia_efpga/jobs/mpw_precheck/e91b7603-4cb2-40d3-9c9d-39f7dcd32d80/outputs/reports/gpio_defines.report
+2022-12-05 17:51:24 - [INFO] - {{GPIO-DEFINES CHECK PASSED}} The user verilog/rtl/user_defines.v is valid.
+2022-12-05 17:51:24 - [INFO] - {{STEP UPDATE}} Executing Check 3 of 7: XOR
+2022-12-05 17:52:11 - [INFO] - {{XOR CHECK UPDATE}} Total XOR differences: 0, for more details view ophelia_efpga/jobs/mpw_precheck/e91b7603-4cb2-40d3-9c9d-39f7dcd32d80/outputs/user_project_wrapper.xor.gds
+2022-12-05 17:52:11 - [INFO] - {{XOR CHECK PASSED}} The GDS file has no XOR violations.
+2022-12-05 17:52:11 - [INFO] - {{STEP UPDATE}} Executing Check 4 of 7: Klayout FEOL
+2022-12-05 17:52:11 - [INFO] - in CUSTOM klayout_gds_drc_check
+2022-12-05 17:52:11 - [INFO] - run: klayout -b -r /opt/checks/tech-files/gf180mcuC_mr.drc -rd input=ophelia_efpga/gds/user_project_wrapper.gds -rd topcell=user_project_wrapper -rd report=ophelia_efpga/jobs/mpw_precheck/e91b7603-4cb2-40d3-9c9d-39f7dcd32d80/outputs/reports/klayout_feol_check.xml -rd feol=true -rd metal_top=9K -rd mim_option=B -rd metal_level=5LM -rd conn_drc=true >& ophelia_efpga/jobs/mpw_precheck/e91b7603-4cb2-40d3-9c9d-39f7dcd32d80/logs/klayout_feol_check.log
+2022-12-05 18:58:03 - [ERROR] - ERROR klayout_feol FAILED, stat=-9, see ophelia_efpga/jobs/mpw_precheck/e91b7603-4cb2-40d3-9c9d-39f7dcd32d80/logs/klayout_feol_check.log
+2022-12-05 18:58:03 - [WARNING] - {{Klayout FEOL CHECK FAILED}} The GDS file, user_project_wrapper.gds, has DRC violations.
+2022-12-05 18:58:03 - [INFO] - {{STEP UPDATE}} Executing Check 5 of 7: Klayout BEOL
+2022-12-05 18:58:03 - [INFO] - in CUSTOM klayout_gds_drc_check
+2022-12-05 18:58:03 - [INFO] - run: klayout -b -r /opt/checks/tech-files/gf180mcuC_mr.drc -rd input=ophelia_efpga/gds/user_project_wrapper.gds -rd topcell=user_project_wrapper -rd report=ophelia_efpga/jobs/mpw_precheck/e91b7603-4cb2-40d3-9c9d-39f7dcd32d80/outputs/reports/klayout_beol_check.xml -rd beol=true -rd metal_top=9K -rd mim_option=B -rd metal_level=5LM -rd conn_drc=true >& ophelia_efpga/jobs/mpw_precheck/e91b7603-4cb2-40d3-9c9d-39f7dcd32d80/logs/klayout_beol_check.log
+2022-12-05 23:10:11 - [INFO] - No DRC Violations found
+2022-12-05 23:10:11 - [INFO] - {{Klayout BEOL CHECK PASSED}} The GDS file, user_project_wrapper.gds, has no DRC violations.
+2022-12-05 23:10:11 - [INFO] - {{STEP UPDATE}} Executing Check 6 of 7: Klayout Offgrid
+2022-12-05 23:10:11 - [INFO] - in CUSTOM klayout_gds_drc_check
+2022-12-05 23:10:11 - [INFO] - run: klayout -b -r /opt/checks/tech-files/gf180mcuC_mr.drc -rd input=ophelia_efpga/gds/user_project_wrapper.gds -rd topcell=user_project_wrapper -rd report=ophelia_efpga/jobs/mpw_precheck/e91b7603-4cb2-40d3-9c9d-39f7dcd32d80/outputs/reports/klayout_offgrid_check.xml -rd offgrid=true -rd metal_top=9K -rd mim_option=B -rd metal_level=5LM -rd conn_drc=true >& ophelia_efpga/jobs/mpw_precheck/e91b7603-4cb2-40d3-9c9d-39f7dcd32d80/logs/klayout_offgrid_check.log
+2022-12-06 03:09:42 - [INFO] - No DRC Violations found
+2022-12-06 03:09:42 - [INFO] - {{Klayout Offgrid CHECK PASSED}} The GDS file, user_project_wrapper.gds, has no DRC violations.
+2022-12-06 03:09:42 - [INFO] - {{STEP UPDATE}} Executing Check 7 of 7: Klayout Metal Minimum Clear Area Density
+2022-12-06 03:09:42 - [INFO] - in CUSTOM klayout_gds_drc_check
+2022-12-06 03:09:42 - [INFO] - run: klayout -b -r /opt/checks/drc_checks/klayout/gf180mcu_density.lydrc -rd input=ophelia_efpga/gds/user_project_wrapper.gds -rd topcell=user_project_wrapper -rd report=ophelia_efpga/jobs/mpw_precheck/e91b7603-4cb2-40d3-9c9d-39f7dcd32d80/outputs/reports/klayout_met_min_ca_density_check.xml >& ophelia_efpga/jobs/mpw_precheck/e91b7603-4cb2-40d3-9c9d-39f7dcd32d80/logs/klayout_met_min_ca_density_check.log
+2022-12-06 03:09:46 - [INFO] - No DRC Violations found
+2022-12-06 03:09:46 - [INFO] - {{Klayout Metal Minimum Clear Area Density CHECK PASSED}} The GDS file, user_project_wrapper.gds, has no DRC violations.
+2022-12-06 03:09:46 - [INFO] - {{FINISH}} Executing Finished, the full log 'precheck.log' can be found in 'ophelia_efpga/jobs/mpw_precheck/e91b7603-4cb2-40d3-9c9d-39f7dcd32d80/logs'
+2022-12-06 03:09:46 - [CRITICAL] - {{FAILURE}} 1 Check(s) Failed: ['Klayout FEOL'] !!!
diff --git a/mpw_precheck/logs/spdx_compliance_report.log b/mpw_precheck/logs/spdx_compliance_report.log
new file mode 100644
index 0000000..0b1d742
--- /dev/null
+++ b/mpw_precheck/logs/spdx_compliance_report.log
@@ -0,0 +1,16 @@
+/root/ophelia_efpga/openlane/config.tcl
+/root/ophelia_efpga/openlane/user_project_wrapper.sdc
+/root/ophelia_efpga/openlane/efuse_ctrl/config.tcl
+/root/ophelia_efpga/openlane/fpga_struct_block/config.tcl
+/root/ophelia_efpga/openlane/fpga_struct_block/fpga_struct_block.sdc
+/root/ophelia_efpga/sdf/efuse_ctrl.sdf
+/root/ophelia_efpga/sdf/fpga_struct_block.sdf
+/root/ophelia_efpga/sdf/user_project_wrapper.sdf
+/root/ophelia_efpga/verilog/includes/includes.gl+sdf.caravel_user_project
+/root/ophelia_efpga/verilog/includes/includes.gl.caravel_user_project
+/root/ophelia_efpga/verilog/includes/includes.rtl.caravel_user_project
+/root/ophelia_efpga/verilog/rtl/ariel_fpga_top_fromvhdl.v
+/root/ophelia_efpga/verilog/rtl/fpga_tech.v
+/root/ophelia_efpga/verilog/rtl/efuse_ctrl/efuse_array_fromvhdl.v
+/root/ophelia_efpga/verilog/rtl/fpga_struct_block/fpga_struct_block_fromvhdl.v
+/root/ophelia_efpga/verilog/rtl/fpga_struct_block/fpga_tech.v
diff --git a/mpw_precheck/logs/tools.info b/mpw_precheck/logs/tools.info
new file mode 100644
index 0000000..4056146
--- /dev/null
+++ b/mpw_precheck/logs/tools.info
@@ -0,0 +1,2 @@
+KLayout: 0.27.12
+Magic: 8.3.340
\ No newline at end of file
diff --git a/mpw_precheck/logs/xor_check.log b/mpw_precheck/logs/xor_check.log
new file mode 100644
index 0000000..f7bb88a
--- /dev/null
+++ b/mpw_precheck/logs/xor_check.log
@@ -0,0 +1,952 @@
+Reading file /root/ophelia_efpga/gds/user_project_wrapper.gds for cell user_project_wrapper
+dbu=0.001
+cell user_project_wrapper dbu-bbox(ll;ur)=(-9580,-8220;2989900,2991340)
+cell user_project_wrapper dbu-bbox(left,bottom,right,top)=(-9580,-8220,2989900,2991340)
+cell user_project_wrapper dbu-size(width,height)=(2999480,2999560)
+cell user_project_wrapper micron-bbox(left,bottom,right,top)=(-9.58,-8.22,2989.9,2991.34)
+cell user_project_wrapper micron-size(width,height)=(2999.48,2999.56)
+Done.
+
+Magic 8.3 revision 340 - Compiled on Thu Nov 17 13:45:26 UTC 2022.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+Processing system .magicrc file
+Sourcing design .magicrc for technology gf180mcuC ...
+10 Magic internal units = 1 Lambda
+Input style import: scaleFactor=10, multiplier=2
+The following types are not handled by extraction and will be treated as non-electrical types:
+ obsactive mvobsactive filldiff fillpoly m1hole obsm1 fillm1 obsv1 m2hole obsm2 fillm2 obsv2 m3hole obsm3 fillm3 m4hole obsm4 fillm4 m5hole obsm5 fillm5 glass fillblock lvstext obscomment
+Scaled tech values by 10 / 1 to match internal grid scaling
+Loading gf180mcuC Device Generator Menu ...
+Loading "/opt/checks/xor_check/erase_box_gf180mcu.tcl" from command line.
+"sky130(vendor)" is not one of the CIF input styles Magic knows.
+The current style is "import".
+The CIF input styles are: import.
+Warning: Calma reading is not undoable! I hope that's OK.
+Library written using GDS-II Release 3.0
+Library name: user_project_wrapper
+Reading "gf180mcu_fd_sc_mcu7t5v0__fill_1".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__fill_1.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__fill_1.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__fill_1.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__fill_1.
+Reading "gf180mcu_fd_sc_mcu7t5v0__endcap".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__endcap.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__endcap.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__endcap.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__endcap.
+Reading "gf180mcu_fd_sc_mcu7t5v0__filltie".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__filltie.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__filltie.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__filltie.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__filltie.
+Reading "gf180mcu_fd_sc_mcu7t5v0__fillcap_64".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__fillcap_64.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__fillcap_64.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__fillcap_64.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__fillcap_64.
+Reading "gf180mcu_fd_sc_mcu7t5v0__fillcap_32".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__fillcap_32.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__fillcap_32.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__fillcap_32.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__fillcap_32.
+Reading "gf180mcu_fd_sc_mcu7t5v0__clkbuf_2".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__clkbuf_2.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__clkbuf_2.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__clkbuf_2.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__clkbuf_2.
+Reading "gf180mcu_fd_sc_mcu7t5v0__fillcap_16".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__fillcap_16.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__fillcap_16.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__fillcap_16.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__fillcap_16.
+Reading "gf180mcu_fd_sc_mcu7t5v0__fillcap_8".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__fillcap_8.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__fillcap_8.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__fillcap_8.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__fillcap_8.
+Reading "gf180mcu_fd_sc_mcu7t5v0__fillcap_4".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__fillcap_4.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__fillcap_4.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__fillcap_4.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__fillcap_4.
+Reading "gf180mcu_fd_sc_mcu7t5v0__antenna".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__antenna.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__antenna.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__antenna.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__antenna.
+Reading "gf180mcu_fd_sc_mcu7t5v0__fill_2".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__fill_2.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__fill_2.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__fill_2.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__fill_2.
+Reading "gf180mcu_fd_sc_mcu7t5v0__clkbuf_3".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__clkbuf_3.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__clkbuf_3.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__clkbuf_3.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__clkbuf_3.
+Reading "gf180mcu_fd_sc_mcu7t5v0__dffq_1".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__dffq_1.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__dffq_1.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__dffq_1.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__dffq_1.
+Reading "gf180mcu_fd_sc_mcu7t5v0__buf_1".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__buf_1.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__buf_1.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__buf_1.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__buf_1.
+Reading "gf180mcu_fd_sc_mcu7t5v0__dlyb_1".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__dlyb_1.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__dlyb_1.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__dlyb_1.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__dlyb_1.
+Reading "gf180mcu_fd_sc_mcu7t5v0__dlyd_4".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__dlyd_4.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__dlyd_4.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__dlyd_4.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__dlyd_4.
+Reading "gf180mcu_fd_sc_mcu7t5v0__clkinv_1".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__clkinv_1.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__clkinv_1.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__clkinv_1.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__clkinv_1.
+Reading "gf180mcu_fd_sc_mcu7t5v0__dlyc_1".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__dlyc_1.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__dlyc_1.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__dlyc_1.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__dlyc_1.
+Reading "gf180mcu_fd_sc_mcu7t5v0__mux4_1".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__mux4_1.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__mux4_1.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__mux4_1.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__mux4_1.
+Reading "gf180mcu_fd_sc_mcu7t5v0__tiel".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__tiel.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__tiel.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__tiel.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__tiel.
+Reading "gf180mcu_fd_sc_mcu7t5v0__clkbuf_1".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__clkbuf_1.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__clkbuf_1.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__clkbuf_1.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__clkbuf_1.
+Reading "gf180mcu_fd_sc_mcu7t5v0__nand3_1".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__nand3_1.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__nand3_1.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__nand3_1.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__nand3_1.
+Reading "gf180mcu_fd_sc_mcu7t5v0__oai211_1".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__oai211_1.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__oai211_1.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__oai211_1.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__oai211_1.
+Reading "gf180mcu_fd_sc_mcu7t5v0__oai21_1".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__oai21_1.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__oai21_1.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__oai21_1.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__oai21_1.
+Reading "gf180mcu_fd_sc_mcu7t5v0__or2_1".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__or2_1.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__or2_1.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__or2_1.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__or2_1.
+Reading "gf180mcu_fd_sc_mcu7t5v0__buf_2".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__buf_2.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__buf_2.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__buf_2.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__buf_2.
+Reading "gf180mcu_fd_sc_mcu7t5v0__buf_8".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__buf_8.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__buf_8.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__buf_8.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__buf_8.
+Reading "gf180mcu_fd_sc_mcu7t5v0__buf_4".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__buf_4.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__buf_4.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__buf_4.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__buf_4.
+Reading "gf180mcu_fd_sc_mcu7t5v0__aoi22_1".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__aoi22_1.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__aoi22_1.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__aoi22_1.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__aoi22_1.
+Reading "gf180mcu_fd_sc_mcu7t5v0__aoi21_1".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__aoi21_1.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__aoi21_1.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__aoi21_1.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__aoi21_1.
+Reading "gf180mcu_fd_sc_mcu7t5v0__and3_1".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__and3_1.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__and3_1.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__and3_1.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__and3_1.
+Reading "gf180mcu_fd_sc_mcu7t5v0__and2_1".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__and2_1.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__and2_1.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__and2_1.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__and2_1.
+Reading "gf180mcu_fd_sc_mcu7t5v0__dffrnq_1".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__dffrnq_1.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__dffrnq_1.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__dffrnq_1.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__dffrnq_1.
+Reading "gf180mcu_fd_sc_mcu7t5v0__clkinv_8".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__clkinv_8.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__clkinv_8.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__clkinv_8.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__clkinv_8.
+Reading "gf180mcu_fd_sc_mcu7t5v0__clkinv_4".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__clkinv_4.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__clkinv_4.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__clkinv_4.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__clkinv_4.
+Reading "gf180mcu_fd_sc_mcu7t5v0__clkinv_3".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__clkinv_3.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__clkinv_3.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__clkinv_3.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__clkinv_3.
+Reading "gf180mcu_fd_sc_mcu7t5v0__clkinv_2".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__clkinv_2.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__clkinv_2.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__clkinv_2.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__clkinv_2.
+Reading "gf180mcu_fd_sc_mcu7t5v0__clkbuf_16".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__clkbuf_16.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__clkbuf_16.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__clkbuf_16.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__clkbuf_16.
+Reading "gf180mcu_fd_sc_mcu7t5v0__nor3_1".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__nor3_1.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__nor3_1.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__nor3_1.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__nor3_1.
+Reading "gf180mcu_fd_sc_mcu7t5v0__nor2_1".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__nor2_1.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__nor2_1.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__nor2_1.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__nor2_1.
+Reading "gf180mcu_fd_sc_mcu7t5v0__nand3_2".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__nand3_2.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__nand3_2.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__nand3_2.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__nand3_2.
+Reading "gf180mcu_fd_sc_mcu7t5v0__nand2_4".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__nand2_4.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__nand2_4.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__nand2_4.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__nand2_4.
+Reading "gf180mcu_fd_sc_mcu7t5v0__nand2_2".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__nand2_2.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__nand2_2.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__nand2_2.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__nand2_2.
+Reading "gf180mcu_fd_sc_mcu7t5v0__nand2_1".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__nand2_1.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__nand2_1.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__nand2_1.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__nand2_1.
+Reading "gf180mcu_fd_sc_mcu7t5v0__inv_1".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__inv_1.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__inv_1.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__inv_1.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__inv_1.
+Reading "fpga_struct_block".
+ 5000 uses
+Reading "gf180mcu_fd_sc_mcu7t5v0__oai21_2".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__oai21_2.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__oai21_2.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__oai21_2.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__oai21_2.
+Reading "gf180mcu_fd_sc_mcu7t5v0__mux4_2".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__mux4_2.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__mux4_2.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__mux4_2.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__mux4_2.
+Reading "gf180mcu_fd_sc_mcu7t5v0__oai22_1".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__oai22_1.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__oai22_1.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__oai22_1.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__oai22_1.
+Reading "gf180mcu_fd_sc_mcu7t5v0__dlyd_1".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__dlyd_1.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__dlyd_1.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__dlyd_1.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__dlyd_1.
+Reading "gf180mcu_fd_sc_mcu7t5v0__buf_3".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__buf_3.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__buf_3.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__buf_3.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__buf_3.
+Reading "gf180mcu_fd_sc_mcu7t5v0__clkbuf_8".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__clkbuf_8.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__clkbuf_8.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__clkbuf_8.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__clkbuf_8.
+Reading "gf180mcu_fd_sc_mcu7t5v0__oai32_1".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__oai32_1.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__oai32_1.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__oai32_1.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__oai32_1.
+Reading "gf180mcu_fd_sc_mcu7t5v0__or4_2".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__or4_2.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__or4_2.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__or4_2.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__or4_2.
+Reading "gf180mcu_fd_sc_mcu7t5v0__nor4_4".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__nor4_4.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__nor4_4.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__nor4_4.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__nor4_4.
+Reading "gf180mcu_fd_sc_mcu7t5v0__nor2_2".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__nor2_2.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__nor2_2.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__nor2_2.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__nor2_2.
+Reading "gf180mcu_fd_sc_mcu7t5v0__aoi211_1".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__aoi211_1.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__aoi211_1.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__aoi211_1.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__aoi211_1.
+Reading "gf180mcu_fd_sc_mcu7t5v0__aoi211_4".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__aoi211_4.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__aoi211_4.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__aoi211_4.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__aoi211_4.
+Reading "gf180mcu_fd_sc_mcu7t5v0__nor3_4".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__nor3_4.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__nor3_4.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__nor3_4.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__nor3_4.
+Reading "gf180mcu_fd_sc_mcu7t5v0__and4_1".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__and4_1.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__and4_1.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__and4_1.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__and4_1.
+Reading "gf180mcu_fd_sc_mcu7t5v0__aoi21_4".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__aoi21_4.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__aoi21_4.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__aoi21_4.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__aoi21_4.
+Reading "gf180mcu_fd_sc_mcu7t5v0__nand4_4".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__nand4_4.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__nand4_4.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__nand4_4.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__nand4_4.
+Reading "gf180mcu_fd_sc_mcu7t5v0__clkbuf_4".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__clkbuf_4.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__clkbuf_4.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__clkbuf_4.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__clkbuf_4.
+Reading "gf180mcu_fd_sc_mcu7t5v0__oai21_4".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__oai21_4.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__oai21_4.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__oai21_4.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__oai21_4.
+Reading "gf180mcu_fd_sc_mcu7t5v0__nor2_4".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__nor2_4.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__nor2_4.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__nor2_4.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__nor2_4.
+Reading "gf180mcu_fd_sc_mcu7t5v0__and3_2".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__and3_2.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__and3_2.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__and3_2.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__and3_2.
+Reading "gf180mcu_fd_sc_mcu7t5v0__aoi21_2".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__aoi21_2.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__aoi21_2.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__aoi21_2.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__aoi21_2.
+Reading "gf180mcu_fd_sc_mcu7t5v0__mux2_2".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__mux2_2.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__mux2_2.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__mux2_2.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__mux2_2.
+Reading "gf180mcu_fd_sc_mcu7t5v0__aoi221_4".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__aoi221_4.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__aoi221_4.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__aoi221_4.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__aoi221_4.
+Reading "gf180mcu_fd_sc_mcu7t5v0__or2_2".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__or2_2.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__or2_2.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__or2_2.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__or2_2.
+Reading "gf180mcu_fd_sc_mcu7t5v0__aoi22_2".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__aoi22_2.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__aoi22_2.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__aoi22_2.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__aoi22_2.
+Reading "gf180mcu_fd_sc_mcu7t5v0__nor3_2".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__nor3_2.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__nor3_2.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__nor3_2.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__nor3_2.
+Reading "gf180mcu_fd_sc_mcu7t5v0__inv_3".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__inv_3.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__inv_3.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__inv_3.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__inv_3.
+Reading "gf180mcu_fd_sc_mcu7t5v0__oai211_2".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__oai211_2.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__oai211_2.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__oai211_2.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__oai211_2.
+Reading "gf180mcu_fd_sc_mcu7t5v0__oai211_4".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__oai211_4.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__oai211_4.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__oai211_4.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__oai211_4.
+Reading "gf180mcu_fd_sc_mcu7t5v0__aoi211_2".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__aoi211_2.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__aoi211_2.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__aoi211_2.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__aoi211_2.
+Reading "gf180mcu_fd_sc_mcu7t5v0__aoi221_1".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__aoi221_1.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__aoi221_1.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__aoi221_1.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__aoi221_1.
+Reading "gf180mcu_fd_sc_mcu7t5v0__tieh".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__tieh.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__tieh.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__tieh.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__tieh.
+Reading "gf180mcu_fd_sc_mcu7t5v0__aoi22_4".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__aoi22_4.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__aoi22_4.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__aoi22_4.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__aoi22_4.
+Reading "gf180mcu_fd_sc_mcu7t5v0__oai221_4".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__oai221_4.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__oai221_4.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__oai221_4.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__oai221_4.
+Reading "gf180mcu_fd_sc_mcu7t5v0__dffsnq_1".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__dffsnq_1.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__dffsnq_1.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__dffsnq_1.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__dffsnq_1.
+Reading "gf180mcu_fd_sc_mcu7t5v0__aoi221_2".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__aoi221_2.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__aoi221_2.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__aoi221_2.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__aoi221_2.
+Reading "gf180mcu_fd_sc_mcu7t5v0__nand3_4".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__nand3_4.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__nand3_4.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__nand3_4.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__nand3_4.
+Reading "gf180mcu_fd_sc_mcu7t5v0__oai221_1".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__oai221_1.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__oai221_1.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__oai221_1.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__oai221_1.
+Reading "gf180mcu_fd_sc_mcu7t5v0__dffrnq_2".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__dffrnq_2.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__dffrnq_2.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__dffrnq_2.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__dffrnq_2.
+Reading "gf180mcu_fd_sc_mcu7t5v0__dffq_2".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__dffq_2.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__dffq_2.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__dffq_2.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__dffq_2.
+Reading "gf180mcu_fd_sc_mcu7t5v0__mux4_4".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__mux4_4.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__mux4_4.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__mux4_4.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__mux4_4.
+Reading "gf180mcu_fd_sc_mcu7t5v0__nand4_2".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__nand4_2.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__nand4_2.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__nand4_2.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__nand4_2.
+Reading "gf180mcu_fd_sc_mcu7t5v0__nand4_1".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__nand4_1.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__nand4_1.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__nand4_1.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__nand4_1.
+Reading "gf180mcu_fd_sc_mcu7t5v0__inv_2".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__inv_2.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__inv_2.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__inv_2.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__inv_2.
+Reading "gf180mcu_fd_sc_mcu7t5v0__oai31_2".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__oai31_2.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__oai31_2.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__oai31_2.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__oai31_2.
+Reading "gf180mcu_fd_sc_mcu7t5v0__oai31_1".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__oai31_1.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__oai31_1.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__oai31_1.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__oai31_1.
+Reading "efuse_array".
+CIF file read warning: CIF style import: units rescaled by factor of 5 / 1
+Error while reading cell "efuse_array" (byte position 7865176): Unknown layer/datatype in boundary, layer=80 type=5
+Error while reading cell "efuse_array" (byte position 7892824): Unknown layer/datatype in boundary, layer=100 type=8
+Error while reading cell "efuse_array" (byte position 7901016): Unknown layer/datatype in boundary, layer=125 type=5
+Error while reading cell "efuse_array" (byte position 7952204): Warning: Cell efuse_array boundary was redefined.
+Error while reading cell "efuse_array" (byte position 7952204): Warning: Cell efuse_array boundary was redefined.
+Error while reading cell "efuse_array" (byte position 7952204): Warning: Cell efuse_array boundary was redefined.
+Error while reading cell "efuse_array" (byte position 7952204): Warning: Cell efuse_array boundary was redefined.
+Error while reading cell "efuse_array" (byte position 7952204): Warning: Cell efuse_array boundary was redefined.
+Error while reading cell "efuse_array" (byte position 7952204): Warning: Cell efuse_array boundary was redefined.
+Error while reading cell "efuse_array" (byte position 7952204): Warning: Cell efuse_array boundary was redefined.
+Reading "efuse_ctrl".
+ 5000 uses
+ 10000 uses
+ 15000 uses
+ 20000 uses
+ 25000 uses
+ 30000 uses
+ 35000 uses
+ 40000 uses
+ 45000 uses
+ 50000 uses
+ 55000 uses
+ 60000 uses
+ 65000 uses
+ 70000 uses
+ 75000 uses
+ 80000 uses
+ 85000 uses
+ 90000 uses
+ 95000 uses
+ 100000 uses
+ 105000 uses
+ 110000 uses
+Reading "user_project_wrapper".
+ 5000 uses
+ 10000 uses
+ 15000 uses
+ 20000 uses
+ 25000 uses
+ 30000 uses
+ 35000 uses
+ 40000 uses
+ 45000 uses
+ 50000 uses
+ 55000 uses
+ 60000 uses
+ 65000 uses
+ 70000 uses
+ 75000 uses
+ 80000 uses
+ 85000 uses
+ 90000 uses
+ 95000 uses
+ 100000 uses
+ 105000 uses
+ 110000 uses
+ 115000 uses
+ 120000 uses
+ 125000 uses
+ 130000 uses
+ 135000 uses
+ 140000 uses
+ 145000 uses
+ 150000 uses
+ 155000 uses
+ 160000 uses
+ 165000 uses
+ 170000 uses
+ 175000 uses
+ 180000 uses
+ 185000 uses
+Root cell box:
+ width x height ( llx, lly ), ( urx, ury ) area (units^2)
+
+microns: 9.580 x 2980.200 (-9.580, 0.000), ( 0.000, 2980.200) 28550.314
+lambda: 191.60 x 59604.00 (-191.60, 0.00 ), ( 0.00, 59604.00) 11420127.00
+internal: 1916 x 596040 ( -1916, 0 ), ( 0, 596040) 1142012640
+Root cell box:
+ width x height ( llx, lly ), ( urx, ury ) area (units^2)
+
+microns: 9.700 x 2980.200 ( 2980.200, 0.000), ( 2989.900, 2980.200) 28907.938
+lambda: 194.00 x 59604.00 ( 59604.00, 0.00 ), ( 59798.00, 59604.00) 11563176.00
+internal: 1940 x 596040 ( 596040, 0 ), ( 597980, 596040) 1156317600
+Root cell box:
+ width x height ( llx, lly ), ( urx, ury ) area (units^2)
+
+microns: 2999.480 x 8.220 (-9.580, -8.220), ( 2989.900, 0.000) 24655.725
+lambda: 59989.60 x 164.40 (-191.60, -164.40), ( 59798.00, 0.00 ) 9862291.00
+internal: 599896 x 1644 ( -1916, -1644 ), ( 597980, 0 ) 986229024
+Root cell box:
+ width x height ( llx, lly ), ( urx, ury ) area (units^2)
+
+microns: 2999.480 x 11.140 (-9.580, 2980.200), ( 2989.900, 2991.340) 33414.207
+lambda: 59989.60 x 222.80 (-191.60, 59604.00), ( 59798.00, 59826.80) 13365683.00
+internal: 599896 x 2228 ( -1916, 596040), ( 597980, 598268) 1336568288
+ Generating output for cell xor_target
+
+Magic 8.3 revision 340 - Compiled on Thu Nov 17 13:45:26 UTC 2022.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+Processing system .magicrc file
+Sourcing design .magicrc for technology gf180mcuC ...
+10 Magic internal units = 1 Lambda
+Input style import: scaleFactor=10, multiplier=2
+The following types are not handled by extraction and will be treated as non-electrical types:
+ obsactive mvobsactive filldiff fillpoly m1hole obsm1 fillm1 obsv1 m2hole obsm2 fillm2 obsv2 m3hole obsm3 fillm3 m4hole obsm4 fillm4 m5hole obsm5 fillm5 glass fillblock lvstext obscomment
+Scaled tech values by 10 / 1 to match internal grid scaling
+Loading gf180mcuC Device Generator Menu ...
+Loading "/opt/checks/xor_check/erase_box_gf180mcu.tcl" from command line.
+"sky130(vendor)" is not one of the CIF input styles Magic knows.
+The current style is "import".
+The CIF input styles are: import.
+Warning: Calma reading is not undoable! I hope that's OK.
+Library written using GDS-II Release 3.0
+Library name: user_project_wrapper
+Reading "gf180mcu_fd_sc_mcu7t5v0__tiel".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__tiel.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__tiel.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__tiel.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__tiel.
+Reading "gf180mcu_fd_sc_mcu7t5v0__filltie".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__filltie.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__filltie.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__filltie.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__filltie.
+Reading "gf180mcu_fd_sc_mcu7t5v0__endcap".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__endcap.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__endcap.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__endcap.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__endcap.
+Reading "gf180mcu_fd_sc_mcu7t5v0__fillcap_4".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__fillcap_4.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__fillcap_4.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__fillcap_4.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__fillcap_4.
+Reading "gf180mcu_fd_sc_mcu7t5v0__fill_2".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__fill_2.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__fill_2.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__fill_2.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__fill_2.
+Reading "gf180mcu_fd_sc_mcu7t5v0__fill_1".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__fill_1.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__fill_1.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__fill_1.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__fill_1.
+Reading "gf180mcu_fd_sc_mcu7t5v0__fillcap_32".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__fillcap_32.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__fillcap_32.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__fillcap_32.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__fillcap_32.
+Reading "gf180mcu_fd_sc_mcu7t5v0__fillcap_16".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__fillcap_16.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__fillcap_16.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__fillcap_16.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__fillcap_16.
+Reading "gf180mcu_fd_sc_mcu7t5v0__fillcap_8".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__fillcap_8.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__fillcap_8.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__fillcap_8.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__fillcap_8.
+Reading "gf180mcu_fd_sc_mcu7t5v0__clkbuf_4".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__clkbuf_4.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__clkbuf_4.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__clkbuf_4.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__clkbuf_4.
+Reading "gf180mcu_fd_sc_mcu7t5v0__clkbuf_1".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__clkbuf_1.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__clkbuf_1.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__clkbuf_1.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__clkbuf_1.
+Reading "gf180mcu_fd_sc_mcu7t5v0__antenna".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__antenna.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__antenna.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__antenna.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__antenna.
+Reading "gf180mcu_fd_sc_mcu7t5v0__fillcap_64".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__fillcap_64.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__fillcap_64.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__fillcap_64.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__fillcap_64.
+Reading "gf180mcu_fd_sc_mcu7t5v0__dffq_1".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__dffq_1.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__dffq_1.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__dffq_1.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__dffq_1.
+Reading "gf180mcu_fd_sc_mcu7t5v0__dffq_2".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__dffq_2.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__dffq_2.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__dffq_2.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__dffq_2.
+Reading "gf180mcu_fd_sc_mcu7t5v0__nor2_1".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__nor2_1.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__nor2_1.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__nor2_1.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__nor2_1.
+Reading "gf180mcu_fd_sc_mcu7t5v0__mux2_2".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__mux2_2.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__mux2_2.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__mux2_2.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__mux2_2.
+Reading "gf180mcu_fd_sc_mcu7t5v0__nand2_1".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__nand2_1.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__nand2_1.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__nand2_1.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__nand2_1.
+Reading "gf180mcu_fd_sc_mcu7t5v0__inv_1".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__inv_1.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__inv_1.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__inv_1.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__inv_1.
+Reading "gf180mcu_fd_sc_mcu7t5v0__nand3_1".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__nand3_1.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__nand3_1.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__nand3_1.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__nand3_1.
+Reading "gf180mcu_fd_sc_mcu7t5v0__nand4_1".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__nand4_1.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__nand4_1.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__nand4_1.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__nand4_1.
+Reading "gf180mcu_fd_sc_mcu7t5v0__clkbuf_16".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__clkbuf_16.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__clkbuf_16.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__clkbuf_16.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__clkbuf_16.
+Reading "gf180mcu_fd_sc_mcu7t5v0__xor2_1".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__xor2_1.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__xor2_1.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__xor2_1.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__xor2_1.
+Reading "gf180mcu_fd_sc_mcu7t5v0__clkinv_1".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__clkinv_1.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__clkinv_1.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__clkinv_1.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__clkinv_1.
+Reading "gf180mcu_fd_sc_mcu7t5v0__aoi21_1".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__aoi21_1.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__aoi21_1.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__aoi21_1.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__aoi21_1.
+Reading "gf180mcu_fd_sc_mcu7t5v0__and3_1".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__and3_1.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__and3_1.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__and3_1.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__and3_1.
+Reading "gf180mcu_fd_sc_mcu7t5v0__buf_1".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__buf_1.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__buf_1.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__buf_1.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__buf_1.
+Reading "gf180mcu_fd_sc_mcu7t5v0__and4_1".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__and4_1.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__and4_1.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__and4_1.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__and4_1.
+Reading "gf180mcu_fd_sc_mcu7t5v0__oai21_1".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__oai21_1.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__oai21_1.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__oai21_1.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__oai21_1.
+Reading "gf180mcu_fd_sc_mcu7t5v0__oai31_1".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__oai31_1.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__oai31_1.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__oai31_1.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__oai31_1.
+Reading "gf180mcu_fd_sc_mcu7t5v0__xnor2_1".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__xnor2_1.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__xnor2_1.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__xnor2_1.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__xnor2_1.
+Reading "gf180mcu_fd_sc_mcu7t5v0__nand4_4".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__nand4_4.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__nand4_4.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__nand4_4.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__nand4_4.
+Reading "gf180mcu_fd_sc_mcu7t5v0__and2_1".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__and2_1.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__and2_1.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__and2_1.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__and2_1.
+Reading "gf180mcu_fd_sc_mcu7t5v0__nor4_4".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__nor4_4.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__nor4_4.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__nor4_4.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__nor4_4.
+Reading "gf180mcu_fd_sc_mcu7t5v0__clkinv_2".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__clkinv_2.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__clkinv_2.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__clkinv_2.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__clkinv_2.
+Reading "gf180mcu_fd_sc_mcu7t5v0__buf_2".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__buf_2.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__buf_2.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__buf_2.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__buf_2.
+Reading "gf180mcu_fd_sc_mcu7t5v0__oai211_1".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__oai211_1.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__oai211_1.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__oai211_1.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__oai211_1.
+Reading "gf180mcu_fd_sc_mcu7t5v0__aoi22_1".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__aoi22_1.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__aoi22_1.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__aoi22_1.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__aoi22_1.
+Reading "gf180mcu_fd_sc_mcu7t5v0__or2_1".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__or2_1.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__or2_1.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__or2_1.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__or2_1.
+Reading "gf180mcu_fd_sc_mcu7t5v0__nor3_1".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__nor3_1.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__nor3_1.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__nor3_1.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__nor3_1.
+Reading "gf180mcu_fd_sc_mcu7t5v0__and4_2".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__and4_2.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__and4_2.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__and4_2.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__and4_2.
+Reading "gf180mcu_fd_sc_mcu7t5v0__or3_1".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__or3_1.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__or3_1.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__or3_1.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__or3_1.
+Reading "gf180mcu_fd_sc_mcu7t5v0__aoi211_1".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__aoi211_1.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__aoi211_1.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__aoi211_1.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__aoi211_1.
+Reading "gf180mcu_fd_sc_mcu7t5v0__aoi221_1".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__aoi221_1.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__aoi221_1.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__aoi221_1.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__aoi221_1.
+Reading "gf180mcu_fd_sc_mcu7t5v0__aoi222_1".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__aoi222_1.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__aoi222_1.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__aoi222_1.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__aoi222_1.
+Reading "gf180mcu_fd_sc_mcu7t5v0__nor4_1".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__nor4_1.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__nor4_1.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__nor4_1.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__nor4_1.
+Reading "gf180mcu_fd_sc_mcu7t5v0__or4_1".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__or4_1.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__or4_1.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__or4_1.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__or4_1.
+Reading "gf180mcu_fd_sc_mcu7t5v0__nor4_2".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__nor4_2.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__nor4_2.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__nor4_2.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__nor4_2.
+Reading "gf180mcu_fd_sc_mcu7t5v0__clkbuf_8".
+Moving label "& Vendor GLOBALFOUNDRIES" from space to nwell in cell gf180mcu_fd_sc_mcu7t5v0__clkbuf_8.
+Moving label "& Product GF018hv5v_mcu_sc7" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__clkbuf_8.
+Moving label "& Version 2015q2v1" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__clkbuf_8.
+Moving label "& Metric 1.00" from space to pwell in cell gf180mcu_fd_sc_mcu7t5v0__clkbuf_8.
+Reading "user_proj_example".
+ 5000 uses
+ 10000 uses
+ 15000 uses
+Reading "user_project_wrapper".
+Root cell box:
+ width x height ( llx, lly ), ( urx, ury ) area (units^2)
+
+microns: 9.580 x 2980.200 (-9.580, 0.000), ( 0.000, 2980.200) 28550.314
+lambda: 191.60 x 59604.00 (-191.60, 0.00 ), ( 0.00, 59604.00) 11420127.00
+internal: 1916 x 596040 ( -1916, 0 ), ( 0, 596040) 1142012640
+Root cell box:
+ width x height ( llx, lly ), ( urx, ury ) area (units^2)
+
+microns: 9.700 x 2980.200 ( 2980.200, 0.000), ( 2989.900, 2980.200) 28907.938
+lambda: 194.00 x 59604.00 ( 59604.00, 0.00 ), ( 59798.00, 59604.00) 11563176.00
+internal: 1940 x 596040 ( 596040, 0 ), ( 597980, 596040) 1156317600
+Root cell box:
+ width x height ( llx, lly ), ( urx, ury ) area (units^2)
+
+microns: 2999.480 x 8.220 (-9.580, -8.220), ( 2989.900, 0.000) 24655.725
+lambda: 59989.60 x 164.40 (-191.60, -164.40), ( 59798.00, 0.00 ) 9862291.00
+internal: 599896 x 1644 ( -1916, -1644 ), ( 597980, 0 ) 986229024
+Root cell box:
+ width x height ( llx, lly ), ( urx, ury ) area (units^2)
+
+microns: 2999.480 x 11.140 (-9.580, 2980.200), ( 2989.900, 2991.340) 33414.207
+lambda: 59989.60 x 222.80 (-191.60, 59604.00), ( 59798.00, 59826.80) 13365683.00
+internal: 599896 x 2228 ( -1916, 596040), ( 597980, 598268) 1336568288
+ Generating output for cell xor_target
+Reading /mnt/uffs/user/u9789_egorxe/design/ophelia_efpga/jobs/mpw_precheck/e91b7603-4cb2-40d3-9c9d-39f7dcd32d80/outputs/user_project_wrapper_erased.gds ..
+Reading /mnt/uffs/user/u9789_egorxe/design/ophelia_efpga/jobs/mpw_precheck/e91b7603-4cb2-40d3-9c9d-39f7dcd32d80/outputs/user_project_wrapper_empty_erased.gds ..
+--- Running XOR for 36/0 ---
+"input" in: xor.rb.drc:39
+ Polygons (raw): 329 (flat) 329 (hierarchical)
+ Elapsed: 0.010s Memory: 524.00M
+"input" in: xor.rb.drc:39
+ Polygons (raw): 329 (flat) 329 (hierarchical)
+ Elapsed: 0.000s Memory: 524.00M
+"^" in: xor.rb.drc:39
+ Polygons (raw): 0 (flat) 0 (hierarchical)
+ Elapsed: 0.020s Memory: 524.00M
+XOR differences: 0
+"output" in: xor.rb.drc:43
+ Polygons (raw): 0 (flat) 0 (hierarchical)
+ Elapsed: 0.000s Memory: 524.00M
+--- Running XOR for 41/0 ---
+"input" in: xor.rb.drc:39
+ Polygons (raw): 128 (flat) 128 (hierarchical)
+ Elapsed: 0.010s Memory: 524.00M
+"input" in: xor.rb.drc:39
+ Polygons (raw): 128 (flat) 128 (hierarchical)
+ Elapsed: 0.000s Memory: 524.00M
+"^" in: xor.rb.drc:39
+ Polygons (raw): 0 (flat) 0 (hierarchical)
+ Elapsed: 0.010s Memory: 524.00M
+XOR differences: 0
+"output" in: xor.rb.drc:43
+ Polygons (raw): 0 (flat) 0 (hierarchical)
+ Elapsed: 0.000s Memory: 524.00M
+--- Running XOR for 42/0 ---
+"input" in: xor.rb.drc:39
+ Polygons (raw): 87 (flat) 87 (hierarchical)
+ Elapsed: 0.010s Memory: 524.00M
+"input" in: xor.rb.drc:39
+ Polygons (raw): 87 (flat) 87 (hierarchical)
+ Elapsed: 0.000s Memory: 524.00M
+"^" in: xor.rb.drc:39
+ Polygons (raw): 0 (flat) 0 (hierarchical)
+ Elapsed: 0.000s Memory: 524.00M
+XOR differences: 0
+"output" in: xor.rb.drc:43
+ Polygons (raw): 0 (flat) 0 (hierarchical)
+ Elapsed: 0.010s Memory: 524.00M
+--- Running XOR for 46/0 ---
+"input" in: xor.rb.drc:39
+ Polygons (raw): 4 (flat) 4 (hierarchical)
+ Elapsed: 0.000s Memory: 524.00M
+"input" in: xor.rb.drc:39
+ Polygons (raw): 4 (flat) 4 (hierarchical)
+ Elapsed: 0.010s Memory: 524.00M
+"^" in: xor.rb.drc:39
+ Polygons (raw): 0 (flat) 0 (hierarchical)
+ Elapsed: 0.000s Memory: 524.00M
+XOR differences: 0
+"output" in: xor.rb.drc:43
+ Polygons (raw): 0 (flat) 0 (hierarchical)
+ Elapsed: 0.010s Memory: 524.00M
+--- Running XOR for 81/0 ---
+"input" in: xor.rb.drc:39
+ Polygons (raw): 4 (flat) 4 (hierarchical)
+ Elapsed: 0.000s Memory: 524.00M
+"input" in: xor.rb.drc:39
+ Polygons (raw): 4 (flat) 4 (hierarchical)
+ Elapsed: 0.000s Memory: 524.00M
+"^" in: xor.rb.drc:39
+ Polygons (raw): 0 (flat) 0 (hierarchical)
+ Elapsed: 0.010s Memory: 524.00M
+XOR differences: 0
+"output" in: xor.rb.drc:43
+ Polygons (raw): 0 (flat) 0 (hierarchical)
+ Elapsed: 0.000s Memory: 524.00M
+Writing layout file: /mnt/uffs/user/u9789_egorxe/design/ophelia_efpga/jobs/mpw_precheck/e91b7603-4cb2-40d3-9c9d-39f7dcd32d80/outputs/user_project_wrapper.xor.gds ..
+Total elapsed: 0.110s Memory: 524.00M
diff --git a/mpw_precheck/logs/xor_check.total b/mpw_precheck/logs/xor_check.total
new file mode 100644
index 0000000..c227083
--- /dev/null
+++ b/mpw_precheck/logs/xor_check.total
@@ -0,0 +1 @@
+0
\ No newline at end of file
diff --git a/mpw_precheck/outputs/reports/gpio_defines.report b/mpw_precheck/outputs/reports/gpio_defines.report
new file mode 100644
index 0000000..0a9cb29
--- /dev/null
+++ b/mpw_precheck/outputs/reports/gpio_defines.report
@@ -0,0 +1,33 @@
+USER_CONFIG_GPIO_5_INIT 10'h008
+USER_CONFIG_GPIO_6_INIT 10'h008
+USER_CONFIG_GPIO_7_INIT 10'h008
+USER_CONFIG_GPIO_8_INIT 10'h008
+USER_CONFIG_GPIO_9_INIT 10'h008
+USER_CONFIG_GPIO_10_INIT 10'h008
+USER_CONFIG_GPIO_11_INIT 10'h008
+USER_CONFIG_GPIO_12_INIT 10'h008
+USER_CONFIG_GPIO_13_INIT 10'h008
+USER_CONFIG_GPIO_14_INIT 10'h008
+USER_CONFIG_GPIO_15_INIT 10'h008
+USER_CONFIG_GPIO_16_INIT 10'h008
+USER_CONFIG_GPIO_17_INIT 10'h008
+USER_CONFIG_GPIO_18_INIT 10'h008
+USER_CONFIG_GPIO_19_INIT 10'h008
+USER_CONFIG_GPIO_20_INIT 10'h008
+USER_CONFIG_GPIO_21_INIT 10'h008
+USER_CONFIG_GPIO_22_INIT 10'h008
+USER_CONFIG_GPIO_23_INIT 10'h008
+USER_CONFIG_GPIO_24_INIT 10'h008
+USER_CONFIG_GPIO_25_INIT 10'h008
+USER_CONFIG_GPIO_26_INIT 10'h008
+USER_CONFIG_GPIO_27_INIT 10'h008
+USER_CONFIG_GPIO_28_INIT 10'h008
+USER_CONFIG_GPIO_29_INIT 10'h008
+USER_CONFIG_GPIO_30_INIT 10'h008
+USER_CONFIG_GPIO_31_INIT 10'h008
+USER_CONFIG_GPIO_32_INIT 10'h008
+USER_CONFIG_GPIO_33_INIT 10'h008
+USER_CONFIG_GPIO_34_INIT 10'h008
+USER_CONFIG_GPIO_35_INIT 10'h008
+USER_CONFIG_GPIO_36_INIT 10'h008
+USER_CONFIG_GPIO_37_INIT 10'h008
diff --git a/mpw_precheck/outputs/reports/klayout_beol_check.xml b/mpw_precheck/outputs/reports/klayout_beol_check.xml
new file mode 100644
index 0000000..0368a13
--- /dev/null
+++ b/mpw_precheck/outputs/reports/klayout_beol_check.xml
@@ -0,0 +1,2949 @@
+<?xml version="1.0" encoding="utf-8"?>
+<report-database>
+ <description>DRC Run Report at</description>
+ <original-file/>
+ <generator>drc: script='/opt/checks/tech-files/gf180mcuC_mr.drc'</generator>
+ <top-cell>user_project_wrapper</top-cell>
+ <tags>
+ </tags>
+ <categories>
+ <category>
+ <name>M1.1</name>
+ <description>M1.1 : min. metal1 width : 0.23µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>M1.2a</name>
+ <description>M1.2a : min. metal1 spacing : 0.23µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>M1.2b</name>
+ <description>M1.2b : Space to wide Metal1 (length & width > 10um) : 0.3µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>M1.3</name>
+ <description>M1.3 : Minimum Metal1 area : 0.1444µm²</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>M2.1</name>
+ <description>M2.1 : min. metal2 width : 0.28µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>M2.2a</name>
+ <description>M2.2a : min. metal2 spacing : 0.28µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>M2.2b</name>
+ <description>M2.2b : Space to wide Metal2 (length & width > 10um) : 0.3µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>M2.3</name>
+ <description>M2.3 : Minimum metal2 area : 0.1444µm²</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>M3.1</name>
+ <description>M3.1 : min. metal3 width : 0.28µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>M3.2a</name>
+ <description>M3.2a : min. metal3 spacing : 0.28µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>M3.2b</name>
+ <description>M3.2b : Space to wide Metal3 (length & width > 10um) : 0.3µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>M3.3</name>
+ <description>M3.3 : Minimum metal3 area : 0.1444µm²</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>M4.1</name>
+ <description>M4.1 : min. metal4 width : 0.28µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>M4.2a</name>
+ <description>M4.2a : min. metal4 spacing : 0.28µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>M4.2b</name>
+ <description>M4.2b : Space to wide Metal4 (length & width > 10um) : 0.3µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>M4.3</name>
+ <description>M4.3 : Minimum metal4 area : 0.1444µm²</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>M5.1</name>
+ <description>M5.1 : min. metal5 width : 0.28µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>M5.2a</name>
+ <description>M5.2a : min. metal5 spacing : 0.28µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>M5.2b</name>
+ <description>M5.2b : Space to wide Metal5 (length & width > 10um) : 0.3µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>M5.3</name>
+ <description>M5.3 : Minimum metal5 area : 0.1444µm²</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>V1.1</name>
+ <description>V1.1 : Min/max Via1 size . : 0.26µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>V1.2a</name>
+ <description>V1.2a : min. via1 spacing : 0.26µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>V1.2b</name>
+ <description>V1.2b : Via1 Space in 4x4 or larger via1 array : 0.36µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>V1.3a</name>
+ <description>V1.3a : metal-1 overlap of via1.</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>V1.3c</name>
+ <description>V1.3c : metal-1 (< 0.34um) end-of-line overlap. : 0.06µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>V1.3d</name>
+ <description>V1.3d : If metal-1 overlap via1 by < 0.04um on one side, adjacent metal-1 edges overlap. : 0.06µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>V1.4a</name>
+ <description>V1.4a : metal-2 overlap of via1.</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>V1.4b</name>
+ <description>V1.4b : metal-2 (< 0.34um) end-of-line overlap. : 0.06µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>V1.4c</name>
+ <description>V1.4c : If metal-2 overlap via1 by < 0.04um on one side, adjacent metal-2 edges overlap. : 0.06µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>V2.1</name>
+ <description>V2.1 : Min/max Via2 size . : 0.26µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>V2.2a</name>
+ <description>V2.2a : min. via2 spacing : 0.26µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>V2.2b</name>
+ <description>V2.2b : Via2 Space in 4x4 or larger via2 array : 0.36µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>V2.3b</name>
+ <description>V2.3b : metal2 overlap of via2.</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>V2.3c</name>
+ <description>V2.3c : metal2 (< 0.34um) end-of-line overlap. : 0.06µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>V2.3d</name>
+ <description>V2.3d : If metal2 overlap via2 by < 0.04um on one side, adjacent metal2 edges overlap. : 0.06µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>V2.4a</name>
+ <description>V2.4a : metal3 overlap of via2.</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>V2.4b</name>
+ <description>V2.4b : metal3 (< 0.34um) end-of-line overlap. : 0.06µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>V2.4c</name>
+ <description>V2.4c : If metal3 overlap via2 by < 0.04um on one side, adjacent metal3 edges overlap. : 0.06µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>V3.1</name>
+ <description>V3.1 : Min/max Via3 size . : 0.26µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>V3.2a</name>
+ <description>V3.2a : min. via3 spacing : 0.26µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>V3.2b</name>
+ <description>V3.2b : Via3 Space in 4x4 or larger via3 array : 0.36µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>V3.3b</name>
+ <description>V3.3b : metal3 overlap of via3.</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>V3.3c</name>
+ <description>V3.3c : metal3 (< 0.34um) end-of-line overlap. : 0.06µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>V3.3d</name>
+ <description>V3.3d : If metal3 overlap via3 by < 0.04um on one side, adjacent metal3 edges overlap. : 0.06µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>V3.4a</name>
+ <description>V3.4a : metal4 overlap of via3.</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>V3.4b</name>
+ <description>V3.4b : metal4 (< 0.34um) end-of-line overlap. : 0.06µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>V3.4c</name>
+ <description>V3.4c : If metal4 overlap via3 by < 0.04um on one side, adjacent metal4 edges overlap. : 0.06µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>V4.1</name>
+ <description>V4.1 : Min/max Via4 size . : 0.26µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>V4.2a</name>
+ <description>V4.2a : min. via4 spacing : 0.26µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>V4.2b</name>
+ <description>V4.2b : Via4 Space in 4x4 or larger Vian array : 0.36µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>V4.3b</name>
+ <description>V4.3b : metal4 overlap of via4.</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>V4.3c</name>
+ <description>V4.3c : metal4 (< 0.34um) end-of-line overlap. : 0.06µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>V4.3d</name>
+ <description>V4.3d : If metal4 overlap Vian by < 0.04um on one side, adjacent metal4 edges overlap. : 0.06µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>V4.4a</name>
+ <description>V4.4a : metal5 overlap of via4.</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>V4.4b</name>
+ <description>V4.4b : metal5 (< 0.34um) end-of-line overlap. : 0.06µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>V4.4c</name>
+ <description>V4.4c : If metal5 overlap via4 by < 0.04um on one side, adjacent metal5 edges overlap. : 0.06µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>V5.1</name>
+ <description>V5.1 : Min/max Via5 size . : 0.26µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>V5.2a</name>
+ <description>V5.2a : min. via5 spacing : 0.26µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>V5.2b</name>
+ <description>V5.2b : Via5 Space in 4x4 or larger via5 array : 0.36µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>V5.3b</name>
+ <description>V5.3b : metal5 overlap of via5.</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>V5.3c</name>
+ <description>V5.3c : metal5 (< 0.34um) end-of-line overlap. : 0.06µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>V5.3d</name>
+ <description>V5.3d : If metal5 overlap via5 by < 0.04um on one side, adjacent metal5 edges overlap. : 0.06µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>V5.4a</name>
+ <description>V5.4a : metaltop overlap of via5.</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>V5.4b</name>
+ <description>V5.4b : metaltop (< 0.34um) end-of-line overlap. : 0.06µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>V5.4c</name>
+ <description>V5.4c : If metaltop overlap via5 by < 0.04um on one side, adjacent metaltop edges overlap. : 0.06µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>MT.1</name>
+ <description>MT.1 : min. metaltop width : 0.44µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>MT.2a</name>
+ <description>MT.2a : min. metaltop spacing : 0.46µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>MT.2b</name>
+ <description>MT.2b : Space to wide Metal2 (length & width > 10um) : 0.6µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>MT.4</name>
+ <description>MT.4 : Minimum MetalTop area : 0.5625µm²</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>MC.1</name>
+ <description>MC.1 : min. mcell width : 0.4µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>MC.2</name>
+ <description>MC.2 : min. mcell spacing : 0.4µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>MC.3</name>
+ <description>MC.3 : Minimum Mcell area : 0.35µm²</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>MC.4</name>
+ <description>MC.4 : Minimum area enclosed by Mcell : 0.35µm²</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>PRES.1</name>
+ <description>PRES.1 : Minimum width of Poly2 resistor. : 0.8µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>PRES.2</name>
+ <description>PRES.2 : Minimum space between Poly2 resistors. : 0.4µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>PRES.3</name>
+ <description>PRES.3 : Minimum space from Poly2 resistor to COMP.</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>PRES.4</name>
+ <description>PRES.4 : Minimum space from Poly2 resistor to unrelated Poly2. : 0.6µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>PRES.5</name>
+ <description>PRES.5 : Minimum Plus implant overlap of Poly2 resistor. : 0.3µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>PRES.6</name>
+ <description>PRES.6 : Minimum salicide block overlap of Poly2 resistor in width direction. : 0.28µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>PRES.7</name>
+ <description>PRES.7 : Space from salicide block to contact on Poly2 resistor.</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>PRES.9a</name>
+ <description>PRES.9a : Pplus Poly2 resistor shall be covered by RES_MK marking. RES_MK length shall be coincide with resistor length (Defined by SAB length) and width covering the width of Poly2.</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>PRES.9b</name>
+ <description>PRES.9b : If the size of single RES_MK mark layer is greater than 15000um2 and both side (X and Y) are greater than 80um. then the minimum spacing to adjacent RES_MK layer. : 20µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>LRES.1</name>
+ <description>LRES.1 : Minimum width of Poly2 resistor. : 0.8µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>LRES.2</name>
+ <description>LRES.2 : Minimum space between Poly2 resistors. : 0.4µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>LRES.3</name>
+ <description>LRES.3 : Minimum space from Poly2 resistor to COMP.</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>LRES.4</name>
+ <description>LRES.4 : Minimum space from Poly2 resistor to unrelated Poly2. : 0.6µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>LRES.5</name>
+ <description>LRES.5 : Minimum Nplus implant overlap of Poly2 resistor. : 0.3µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>LRES.6</name>
+ <description>LRES.6 : Minimum salicide block overlap of Poly2 resistor in width direction. : 0.28µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>LRES.7</name>
+ <description>LRES.7 : Space from salicide block to contact on Poly2 resistor.</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>LRES.9a</name>
+ <description>LRES.9a : Nplus Poly2 resistor shall be covered by RES_MK marking. RES_MK length shall be coincide with resistor length (Defined by SAB length) and width covering the width of Poly2. </description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>LRES.9b</name>
+ <description>LRES.9b : If the size of single RES_MK mark layer is greater than 15000um2 and both side (X and Y) are greater than 80um. then the minimum spacing to adjacent RES_MK layer. : 20µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>HRES.1</name>
+ <description>HRES.1 : Minimum space. Note : Merge if the spacing is less than 0.4 um. : 0.4µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>HRES.2</name>
+ <description>HRES.2 : Minimum width of Poly2 resistor. : 1µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>HRES.3</name>
+ <description>HRES.3 : Minimum space between Poly2 resistors. : 0.4µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>HRES.4</name>
+ <description>HRES.4 : Minimum RESISTOR overlap of Poly2 resistor. : 0.4µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>HRES.5</name>
+ <description>HRES.5 : Minimum RESISTOR space to unrelated Poly2. : 0.3µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>HRES.6</name>
+ <description>HRES.6 : Minimum RESISTOR space to COMP.</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>HRES.7</name>
+ <description>HRES.7 : Minimum Pplus overlap of contact on Poly2 resistor. : 0.2µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>HRES.8</name>
+ <description>HRES.8 : Space from salicide block to contact on Poly2 resistor.</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>HRES.9</name>
+ <description>HRES.9 : Minimum salicide block overlap of Poly2 resistor in width direction.</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>HRES.10</name>
+ <description>HRES.10 : Minimum & maximum Pplus overlap of SAB.</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>HRES.12a</name>
+ <description>HRES.12a : P type Poly2 resistor (high sheet rho) shall be covered by RES_MK marking. RES_MK length shall be coincide with resistor length (Defined by Pplus space) and width covering the width of Poly2. </description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>HRES.12b</name>
+ <description>HRES.12b : If the size of single RES_MK mark layer is greater than 15000 um2 and both side (X and Y) are greater than 80 um. Then the minimum spacing to adjacent RES_MK layer. : 20µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>MIMTM.1</name>
+ <description>MIMTM.1 : Minimum MiM bottom plate spacing to the bottom plate metal (whether adjacent MiM or routing metal). : 1.2µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>MIMTM.2</name>
+ <description>MIMTM.2 : Minimum MiM bottom plate overlap of Vian-1 layer. [This is applicable for Vian-1 within 1.06um oversize of FuseTop layer (referenced to virtual bottom plate)]. : 0.4µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>MIMTM.3</name>
+ <description>MIMTM.3 : Minimum MiM bottom plate overlap of Top plate.</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>MIMTM.4</name>
+ <description>MIMTM.4 : Minimum MiM top plate (FuseTop) overlap of Vian-1. : 0.4µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>MIMTM.5</name>
+ <description>MIMTM.5 : Minimum spacing between top plate and the Vian-1 connecting to the bottom plate. : 0.4µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>MIMTM.6</name>
+ <description>MIMTM.6 : Minimum spacing between unrelated top plates. : 0.6µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>MIMTM.7</name>
+ <description>MIMTM.7 : Min FuseTop enclosure by CAP_MK.</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>MIMTM.8a</name>
+ <description>MIMTM.8a : Minimum MIM cap area (defined by FuseTop area) (um2). : 25µm²</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>MIMTM.8b</name>
+ <description>MIMTM.8b : Maximum single MIM Cap area (Use multiple MIM caps in parallel connection if bigger capacitors are required) (um2). : 10000µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>MIMTM.9</name>
+ <description>MIMTM.9 : Min. Via (Vian-1) spacing for sea of Via on MIM top plate. : 0.5µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>MIMTM.10</name>
+ <description>MIMTM.10 : (a) There cannot be any Vian-2 touching MIM bottom plate Metaln-1. (b) MIM bottom plate Metaln-1 can only be connected through the higher Via (Vian-1).</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>MIMTM.11</name>
+ <description>MIMTM.11 : Bottom plate of multiple MIM caps can be shared (for common nodes) as long as total MIM area with that single common plate does not exceed MIMTM.8b rule. : -µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>NAT.1</name>
+ <description>NAT.1 : Min. NAT Overlap of COMP of Native Vt NMOS. : 2µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>NAT.2</name>
+ <description>NAT.2 : Space to unrelated COMP (outside NAT). : 0.3µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>NAT.3</name>
+ <description>NAT.3 : Space to NWell edge. : 0.5µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>NAT.4</name>
+ <description>NAT.4 : Minimum channel length for 3.3V Native Vt NMOS (For smaller L Ioff will be higher than Spec). : 1.8µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>NAT.5</name>
+ <description>NAT.5 : Minimum channel length for 6.0V Native Vt NMOS (For smaller L Ioff will be higher than Spec). : 1.8µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>NAT.6</name>
+ <description>NAT.6 : Two or more COMPs if connected to different potential are not allowed under same NAT layer.</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>NAT.7</name>
+ <description>NAT.7 : Minimum NAT to NAT spacing. : 0.74µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>NAT.8</name>
+ <description>NAT.8 : Min. Dualgate overlap of NAT (for 5V/6V) native VT NMOS only.</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>NAT.9</name>
+ <description>NAT.9 : Poly interconnect under NAT layer is not allowed, minimum spacing of un-related poly from the NAT layer.</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>NAT.10</name>
+ <description>NAT.10 : Nwell, inside NAT layer are not allowed.</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>NAT.11</name>
+ <description>NAT.11 : NCOMP not intersecting to Poly2, is not allowed inside NAT layer.</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>NAT.12</name>
+ <description>NAT.12 : Poly2 not intersecting with COMP is not allowed inside NAT (Poly2 resistor is not allowed inside NAT).</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>BJT.1</name>
+ <description>BJT.1 : Min. DRC_BJT overlap of DNWELL for NPN BJT.</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>BJT.2</name>
+ <description>BJT.2 : Min. DRC_BJT overlap of PCOM in Psub.</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>BJT.3</name>
+ <description>BJT.3 : Minimum space of DRC_BJT layer to unrelated COMP. : 0.1µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>DE.2</name>
+ <description>DE.2 : Minimum NDMY or PMNDMY size (x or y dimension in um). : 0.8µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>DE.3</name>
+ <description>DE.3 : If size greater than 15000 um2 then two sides should not be greater than (um).</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>DE.4</name>
+ <description>DE.4 : Minimum NDMY to NDMY space (Merge if space is less). : 20µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>LVS_BJT.1</name>
+ <description>LVS_BJT.1 : Minimum LVS_BJT enclosure of NPN or PNP Emitter COMP layers</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>O.DF.3a</name>
+ <description>O.DF.3a : Min. COMP Space. P-substrate tap (PCOMP outside NWELL) can be butted for different voltage devices as the potential is same. : 0.24µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>O.DF.6</name>
+ <description>O.DF.6 : Min. COMP extend beyond poly2 (it also means source/drain overhang). : 0.22µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>O.DF.9</name>
+ <description>O.DF.9 : Min. COMP area (um2). : 0.1444µm²</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>O.PL.2</name>
+ <description>O.PL.2 : Min. poly2 width. : 0.22µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>O.PL.3a</name>
+ <description>O.PL.3a : Min. poly2 Space on COMP. : 0.18µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>O.PL.4</name>
+ <description>O.PL.4 : Min. extension beyond COMP to form Poly2 end cap. : 0.14µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>O.SB.2</name>
+ <description>O.SB.2 : Min. salicide Block Space. : 0.28µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>O.SB.3</name>
+ <description>O.SB.3 : Min. space from salicide block to unrelated COMP. : 0.09µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>O.SB.4</name>
+ <description>O.SB.4 : Min. space from salicide block to contact.</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>O.SB.5b_3.3V</name>
+ <description>O.SB.5b_3.3V : Min. space from salicide block to unrelated Poly2 on COMP. : 0.1µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>O.SB.9</name>
+ <description>O.SB.9 : Min. salicide block extension beyond unsalicided Poly2. : 0.1µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>O.SB.11</name>
+ <description>O.SB.11 : Min. salicide block overlap with COMP. : 0.04µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>O.SB.13_3.3V</name>
+ <description>O.SB.13_3.3V : Min. area of silicide block (um2). : 1.488µm²</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>O.SB.13_5V</name>
+ <description>O.SB.13_5V : Min. area of silicide block (um2). : 2µm²</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>O.CO.7</name>
+ <description>O.CO.7 : Min. space from COMP contact to Poly2 on COMP. : 0.13µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>O.PL.ORT</name>
+ <description>O.PL.ORT : Orientation-restricted gates must have the gate width aligned along the X-axis (poly line running horizontally) in reference to wafer notch down. : 0µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>EF.01</name>
+ <description>EF.01 : Min. (Poly2 butt PLFUSE) within EFUSE_MK and Pplus.</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>EF.02</name>
+ <description>EF.02 : Min. Max. PLFUSE width. : 0.18µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>EF.03</name>
+ <description>EF.03 : Min. Max. PLFUSE length. : 1.26µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>EF.04a</name>
+ <description>EF.04a : Min. Max. PLFUSE overlap Poly2 (coinciding permitted) and touch cathode and anode.</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>EF.04b</name>
+ <description>EF.04b : PLFUSE must be rectangular. : -µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>EF.04c</name>
+ <description>EF.04c : Cathode Poly2 must be rectangular. : -µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>EF.04d</name>
+ <description>EF.04d : Anode Poly2 must be rectangular. : -µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>EF.05</name>
+ <description>EF.05 : Min./Max. LVS_Source overlap Poly2 (at Anode).</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>EF.06</name>
+ <description>EF.06 : Min./Max. Cathode Poly2 width. : 2.26µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>EF.07</name>
+ <description>EF.07 : Min./Max. Cathode Poly2 length. : 1.84µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>EF.08</name>
+ <description>EF.08 : Min./Max. Anode Poly2 width. : 1.06µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>EF.09</name>
+ <description>EF.09 : Min./Max. Anode Poly2 length. : 2.43µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>EF.10</name>
+ <description>EF.10 : Min. Cathode Poly2 to Poly2 space. : 0.26µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>EF.11</name>
+ <description>EF.11 : Min. Anode Poly2 to Poly2 space. : 0.26µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>EF.12</name>
+ <description>EF.12 : Min. Space of Cathode Contact to PLFUSE end.</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>EF.13</name>
+ <description>EF.13 : Min. Space of Anode Contact to PLFUSE end.</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>EF.14</name>
+ <description>EF.14 : Min. EFUSE_MK enclose LVS_Source.</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>EF.15</name>
+ <description>EF.15 : NO Contact is allowed to touch PLFUSE.</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>EF.16a</name>
+ <description>EF.16a : Cathode must contain exact number of Contacts at each ends. : 4µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>EF.16b</name>
+ <description>EF.16b : Anode must contain exact number of Contacts at each ends. : 4µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>EF.17</name>
+ <description>EF.17 : Min. Space of EFUSE_MK to EFUSE_MK. : 0.26µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>EF.18</name>
+ <description>EF.18 : PLFUSE must sit on field oxide (NOT COMP), no cross with any COMP, Nplus, Pplus, ESD, SAB, Resistor, Metal1, Metal2.</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>EF.19</name>
+ <description>EF.19 : Min. PLFUSE space to Metal1, Metal2.</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>EF.20</name>
+ <description>EF.20 : Min. PLFUSE space to COMP, Nplus, Pplus, Resistor, ESD, SAB. : 2.73µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>EF.21</name>
+ <description>EF.21 : Min./Max. eFUSE Poly2 length. : 5.53µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>EF.22a</name>
+ <description>EF.22a : Min./Max. Cathode Poly2 overlap with PLFUSE in width direction. : 1.04µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>EF.22b</name>
+ <description>EF.22b : Min./Max. Anode Poly2 overlap with PLFUSE in width direction. : 0.44µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>MDN.1</name>
+ <description>MDN.1 : Min MVSD width (for litho purpose). : 1µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>MDN.2a</name>
+ <description>MDN.2a : Min MVSD space [Same Potential]. : 1µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>MDN.2b</name>
+ <description>MDN.2b : Min MVSD space [Diff Potential]. : 2µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>MDN.3a</name>
+ <description>MDN.3a : Min transistor channel length. : 0.6µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>MDN.3b</name>
+ <description>MDN.3b : Max transistor channel length: 20 um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>MDN.4a</name>
+ <description>MDN.4a : Min transistor channel width. : 4 µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>MDN.4b</name>
+ <description>MDN.4b : Max transistor channel width. : 50 um </description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>MDN.5ai</name>
+ <description>MDN.5ai : Min PCOMP (Pplus AND COMP) space to LDNMOS Drain MVSD (source and body tap non-butted). PCOMP (Pplus AND COMP) intercept with LDNMOS Drain MVSD is not allowed.</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>MDN.5aii</name>
+ <description>MDN.5aii : Min PCOMP (Pplus AND COMP) space to LDNMOS Drain MVSD (source and body tap butted). PCOMP (Pplus AND COMP) intercept with LDNMOS Drain MVSD is not allowed. : 0.92µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>MDN.5b</name>
+ <description>MDN.5b : Min PCOMP (Pplus AND COMP) space to LDNMOS Source (Nplus AND COMP). Use butted source and p-substrate tab otherwise and that is good for Latch-up immunity as well.</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>MDN.5c</name>
+ <description>MDN.5c : Maximum distance of the nearest edge of the substrate tab from NCOMP edge. : 15µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>MDN.6</name>
+ <description>MDN.6 : ALL LDNMOS shall be covered by Dualgate layer.</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>MDN.6a</name>
+ <description>MDN.6a : Min Dualgate enclose NCOMP.</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>MDN.7</name>
+ <description>MDN.7 : Each LDNMOS shall be covered by LDMOS_XTOR (GDS#226) mark layer.</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>MDN.7a</name>
+ <description>MDN.7a : Min LDMOS_XTOR enclose Dualgate.</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>MDN.8a</name>
+ <description>MDN.8a : Min LDNMOS drain MVSD space to any other equal potential Nwell space.</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>MDN.8b</name>
+ <description>MDN.8b : Min LDNMOS drain MVSD space to any other different potential Nwell space.</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>MDN.9</name>
+ <description>MDN.9 : Min LDNMOS drain MVSD space to NCOMP (Nplus AND COMP) outside LDNMOS drain MVSD. : 4µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>MDN.10a</name>
+ <description>MDN.10a : Min LDNMOS POLY2 width. : 1.2µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>MDN.10b</name>
+ <description>MDN.10b : Min POLY2 extension beyond COMP in the width direction of the transistor (other than the LDNMOS drain direction). : 0.4µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>MDN.10c</name>
+ <description>MDN.10c : Min/Max POLY2 extension beyond COMP on the field towards LDNMOS drain COMP direction.</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>MDN.10d</name>
+ <description>MDN.10d : Min/Max POLY2 on field space to LDNMOS drain COMP.</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>MDN.10ei</name>
+ <description>MDN.10ei : Min POLY2 space to Psub tap (source and body tap non-butted).</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>MDN.10eii</name>
+ <description>MDN.10eii : Min POLY2 space to Psub tap (source and body tap butted). : 0.32µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>MDN.10f</name>
+ <description>MDN.10f : Poly2 interconnect in HV region (LDMOS_XTOR marked region) not allowed. Also, any Poly2 interconnect with poly2 to substrate potential greater than 6V is not allowed.</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>MDN.11</name>
+ <description>MDN.11 : Min/Max MVSD overlap channel COMP ((((LDMOS_XTOR AND MVSD) AND COMP) AND POLY2) AND NPlus).</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>MDN.12</name>
+ <description>MDN.12 : Min MVSD enclose NCOMP in the LDNMOS drain and in the direction along the transistor width.</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>MDN.13a</name>
+ <description>MDN.13a : Max single finger width. : 50µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>MDN.13b</name>
+ <description>MDN.13b : Layout shall have alternative source & drain.</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>MDN.13c</name>
+ <description>MDN.13c : Both sides of the transistor shall be terminated by source.</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>MDN.13d</name>
+ <description>MDN.13d : Every two poly fingers shall be surrounded by a P-sub guard ring. (Exclude the case when each LDNMOS transistor have full width butting to well tap).</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>MDN.14</name>
+ <description>MDN.14 : Min MVSD space to any DNWELL.</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>MDN.15a</name>
+ <description>MDN.15a : Min LDNMOS drain COMP width. : 0.22µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>MDN.15b</name>
+ <description>MDN.15b : Min LDNMOS drain COMP enclose contact. : 0µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>MDN.17</name>
+ <description>MDN.17 : It is recommended to surround the LDNMOS transistor with non-broken Psub guard ring to improve the latch up immunity. Guideline to improve the latch up immunity.</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>MDP.1</name>
+ <description>MDP.1 : Minimum transistor channel length. : 0.6µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>MDP.1a</name>
+ <description>MDP.1a : Max transistor channel length.</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>MDP.2</name>
+ <description>MDP.2 : Minimum transistor channel width. : 4µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>MDP.3</name>
+ <description>MDP.3 : Each LDPMOS shall be surrounded by non-broken Nplus guard ring inside DNWELL</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>MDP.3ai</name>
+ <description>MDP.3ai : Min NCOMP (Nplus AND COMP) space to MVPSD (source and body tap non-butted). NCOMP (Nplus AND COMP) intercept with MVPSD is not allowed.</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>MDP.3aii</name>
+ <description>MDP.3aii : Min NCOMP (Nplus AND COMP) space to MVPSD (source and body tap butted). NCOMP (Nplus AND COMP) intercept with MVPSD is not allowed.</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>MDP.3b</name>
+ <description>MDP.3b : Min NCOMP (Nplus AND COMP) space to PCOMP in DNWELL (Pplus AND COMP AND DNWELL). Use butted source and DNWELL contacts otherwise and that is best for Latch-up immunity as well. : 0.4µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>MDP.3c</name>
+ <description>MDP.3c : Maximum distance of the nearest edge of the DNWELL tab (NCOMP inside DNWELL) from PCOMP edge (PCOMP inside DNWELL). : 15µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>MDP.3d</name>
+ <description>MDP.3d : The metal connection for the Nplus guard ring recommended to be continuous. The maximum gap between this metal if broken. Note: To put maximum number of contact under metal for better manufacturability and reliability. : 10µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>MDP.4</name>
+ <description>MDP.4 : DNWELL covering LDPMOS shall be surrounded by non broken Pplus guard. The metal connection for the Pplus guard ring recommended to be continuous, The maximum gap between this metal if broken. Note: To put maximum number of contact under metal for better manufacturability and reliability.</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>MDP.4a</name>
+ <description>MDP.4a : Min PCOMP (Pplus AND COMP) space to DNWELL. : 2.5µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>MDP.4b</name>
+ <description>MDP.4b : Maximum distance of the nearest edge of the DNWELL from the PCOMP Guard ring outside DNWELL. : 15µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>MDP.5</name>
+ <description>MDP.5 : Each LDPMOS shall be covered by Dualgate layer.</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>MDP.5a</name>
+ <description>MDP.5a : Minimum Dualgate enclose Plus guarding ring PCOMP (Pplus AND COMP). : 0.5µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>MDP.6</name>
+ <description>MDP.6 : Each LDPMOS shall be covered by LDMOS_XTOR (GDS#226) layer.</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>MDP.6a</name>
+ <description>MDP.6a : Minimum LDMOS_XTOR enclose Dualgate.</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>MDP.7</name>
+ <description>MDP.7 : Minimum LDMOS_XTOR layer space to Nwell outside LDMOS_XTOR. : 2µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>MDP.8</name>
+ <description>MDP.8 : Minimum LDMOS_XTOR layer space to NCOMP outside LDMOS_XTOR. : 1.5µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>MDP.9a</name>
+ <description>MDP.9a : Min LDPMOS POLY2 width. : 1.2µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>MDP.9b</name>
+ <description>MDP.9b : Min POLY2 extension beyond COMP in the width direction of the transistor (other than the LDMOS drain direction). : 0.4µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>MDP.9c</name>
+ <description>MDP.9c : Min/Max POLY2 extension beyond COMP on the field towards LDPMOS drain (MVPSD AND COMP AND Pplus NOT POLY2) direction.</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>MDP.9d</name>
+ <description>MDP.9d : Min/Max POLY2 on field to LDPMOS drain COMP (MVPSD AND COMP AND Pplus NOT POLY2) space.</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>MDP.9ei</name>
+ <description>MDP.9ei : Min LDMPOS gate Poly2 space to Nplus guardring (source and body tap non-butted).</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>MDP.9eii</name>
+ <description>MDP.9eii : Min LDMPOS gate Poly2 space to Nplus guardring (source and body tap butted).</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>MDP.9f</name>
+ <description>MDP.9f : Poly2 interconnect is not allowed in LDPMOS region (LDMOS_XTOR marked region). : -µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>MDP.10</name>
+ <description>MDP.10 : Min/Max MVPSD overlap onto the channel (LDMOS_XTOR AND COMP AND POLY2 AND Pplus).</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>MDP.10a</name>
+ <description>MDP.10a : Min MVPSD space within LDMOS_XTOR marking [diff potential]. : 2µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>MDP.10b</name>
+ <description>MDP.10b : Min MVPSD space [same potential]. Merge if space less than 1um. : 1µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>MDP.11</name>
+ <description>MDP.11 : Min MVPSD enclosing PCOMP in the drain (MVPSD AND COMP NOT POLY2) direction and in the direction along the transistor width.</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>MDP.12</name>
+ <description>MDP.12 : Min DNWELL enclose Nplus guard ring (NCOMP). : 0.66µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>MDP.13a</name>
+ <description>MDP.13a : Max single finger width. : 50µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>MDP.13b</name>
+ <description>MDP.13b : Layout shall have alternative source & drain.</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>MDP.13c</name>
+ <description>MDP.13c : Both sides of the transistor shall be terminated by source.</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>MDP.15</name>
+ <description>MDP.15 : Min DNWELL enclosing MVPSD to any DNWELL spacing. : 6µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>MDP.16a</name>
+ <description>MDP.16a : Min LDPMOS drain COMP width. : 0.22µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>MDP.16b</name>
+ <description>MDP.16b : Min LDPMOS drain COMP enclose contact. : 0µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>MDP.17a</name>
+ <description>MDP.17a : For better latch up immunity, it is necessary to put DNWELL guard ring between MVPSD Inside DNWELL covered by LDMOS_XTOR and NCOMP (outside DNWELL and outside Nwell) when spacing between them is less than 40um.</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>MDP.17c</name>
+ <description>MDP.17c : DNWELL guard ring shall have NCOMP tab to be connected to highest potential</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>Y.NW.2b_3.3V</name>
+ <description>Y.NW.2b_3.3V : Min. Nwell Space (Outside DNWELL, Inside YMTP_MK) [Different potential]. : 1µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>Y.NW.2b_5V</name>
+ <description>Y.NW.2b_5V : Min. Nwell Space (Outside DNWELL, Inside YMTP_MK) [Different potential]. : 1µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>Y.DF.6_5V</name>
+ <description>Y.DF.6_5V : Min. COMP extend beyond gate (it also means source/drain overhang) inside YMTP_MK. : 0.15µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>Y.DF.16_3.3V</name>
+ <description>Y.DF.16_3.3V : Min. space from (Nwell outside DNWELL) to (unrelated NCOMP outside Nwell and DNWELL) (inside YMTP_MK). : 0.27µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>Y.DF.16_5V</name>
+ <description>Y.DF.16_5V : Min. space from (Nwell outside DNWELL) to (unrelated NCOMP outside Nwell and DNWELL) (inside YMTP_MK). : 0.23µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>Y.PL.1_3.3V</name>
+ <description>Y.PL.1_3.3V : Interconnect Width (inside YMTP_MK). : 0.13µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>Y.PL.1_5V</name>
+ <description>Y.PL.1_5V : Interconnect Width (inside YMTP_MK). This rule is currently not applicable for 5V.</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>Y.PL.2_3.3V</name>
+ <description>Y.PL.2_3.3V : Gate Width (Channel Length) (inside YMTP_MK). : 0.13µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>Y.PL.2_5V</name>
+ <description>Y.PL.2_5V : Gate Width (Channel Length) (inside YMTP_MK). : 0.47µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>Y.PL.4_5V</name>
+ <description>Y.PL.4_5V : Poly2 extension beyond COMP to form Poly2 end cap (inside YMTP_MK). : 0.16µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>Y.PL.5a_3.3V</name>
+ <description>Y.PL.5a_3.3V : Space from field Poly2 to unrelated COMP (inside YMTP_MK). Space from field Poly2 to Guard-ring (inside YMTP_MK). : 0.04µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>Y.PL.5a_5V</name>
+ <description>Y.PL.5a_5V : Space from field Poly2 to unrelated COMP (inside YMTP_MK). Space from field Poly2 to Guard-ring (inside YMTP_MK). : 0.2µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>Y.PL.5b_3.3V</name>
+ <description>Y.PL.5b_3.3V : Space from field Poly2 to related COMP (inside YMTP_MK). : 0.04µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>Y.PL.5b_5V</name>
+ <description>Y.PL.5b_5V : Space from field Poly2 to related COMP (inside YMTP_MK). : 0.2µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>S.DF.4c_MV</name>
+ <description>S.DF.4c_MV : Min. (Nwell overlap of PCOMP) outside DNWELL. : 0.45µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>S.DF.6_MV</name>
+ <description>S.DF.6_MV : Min. COMP extend beyond gate (it also means source/drain overhang). : 0.32µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>S.DF.7_MV</name>
+ <description>S.DF.7_MV : Min. (LVPWELL Spacer to PCOMP) inside DNWELL. : 0.45µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>S.DF.8_MV</name>
+ <description>S.DF.8_MV : Min. (LVPWELL overlap of NCOMP) Inside DNWELL. : 0.45µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>S.DF.16_MV</name>
+ <description>S.DF.16_MV : Min. space from (Nwell outside DNWELL) to (NCOMP outside Nwell and DNWELL). : 0.45µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>S.PL.5a_MV</name>
+ <description>S.PL.5a_MV : Space from field Poly2 to unrelated COMP Spacer from field Poly2 to Guard-ring. : 0.12µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>S.PL.5b_MV</name>
+ <description>S.PL.5b_MV : Space from field Poly2 to related COMP. : 0.12µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>S.CO.4_MV</name>
+ <description>S.CO.4_MV : COMP overlap of contact. : 0.04µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>S.DF.4c_LV</name>
+ <description>S.DF.4c_LV : Min. (Nwell overlap of PCOMP) outside DNWELL. : 0.4µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>S.DF.16_LV</name>
+ <description>S.DF.16_LV : Min. space from (Nwell outside DNWELL) to (NCOMP outside Nwell and DNWELL). : 0.4µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>S.CO.3_LV</name>
+ <description>S.CO.3_LV : Poly2 overlap of contact. : 0.04µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>S.CO.4_LV</name>
+ <description>S.CO.4_LV : COMP overlap of contact. : 0.03µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>S.CO.6_ii_LV</name>
+ <description>S.CO.6_ii_LV : (ii) If Metal1 overlaps contact by < 0.04um on one side, adjacent metal1 edges overlap</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>S.M1.1_LV</name>
+ <description>S.M1.1_LV : min. metal1 width : 0.22µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>comp_OFFGRID</name>
+ <description>OFFGRID : OFFGRID vertex on comp</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>comp_angle</name>
+ <description>ACUTE : non 45 degree angle comp</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>dnwell_OFFGRID</name>
+ <description>OFFGRID : OFFGRID vertex on dnwell</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>dnwell_angle</name>
+ <description>ACUTE : non 45 degree angle dnwell</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>nwell_OFFGRID</name>
+ <description>OFFGRID : OFFGRID vertex on nwell</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>nwell_angle</name>
+ <description>ACUTE : non 45 degree angle nwell</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>lvpwell_OFFGRID</name>
+ <description>OFFGRID : OFFGRID vertex on lvpwell</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>lvpwell_angle</name>
+ <description>ACUTE : non 45 degree angle lvpwell</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>dualgate_OFFGRID</name>
+ <description>OFFGRID : OFFGRID vertex on dualgate</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>dualgate_angle</name>
+ <description>ACUTE : non 45 degree angle dualgate</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>poly2_OFFGRID</name>
+ <description>OFFGRID : OFFGRID vertex on poly2</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>poly2_angle</name>
+ <description>ACUTE : non 45 degree angle poly2</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>nplus_OFFGRID</name>
+ <description>OFFGRID : OFFGRID vertex on nplus</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>nplus_angle</name>
+ <description>ACUTE : non 45 degree angle nplus</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>pplus_OFFGRID</name>
+ <description>OFFGRID : OFFGRID vertex on pplus</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>pplus_angle</name>
+ <description>ACUTE : non 45 degree angle pplus</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>sab_OFFGRID</name>
+ <description>OFFGRID : OFFGRID vertex on sab</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>sab_angle</name>
+ <description>ACUTE : non 45 degree angle sab</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>esd_OFFGRID</name>
+ <description>OFFGRID : OFFGRID vertex on esd</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>esd_angle</name>
+ <description>ACUTE : non 45 degree angle esd</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>contact_OFFGRID</name>
+ <description>OFFGRID : OFFGRID vertex on contact</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>contact_angle</name>
+ <description>ACUTE : non 45 degree angle contact</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>metal1_OFFGRID</name>
+ <description>OFFGRID : OFFGRID vertex on metal1</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>metal1_angle</name>
+ <description>ACUTE : non 45 degree angle metal1</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via1_OFFGRID</name>
+ <description>OFFGRID : OFFGRID vertex on via1</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via1_angle</name>
+ <description>ACUTE : non 45 degree angle via1</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>metal2_OFFGRID</name>
+ <description>OFFGRID : OFFGRID vertex on metal2</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>metal2_angle</name>
+ <description>ACUTE : non 45 degree angle metal2</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via2_OFFGRID</name>
+ <description>OFFGRID : OFFGRID vertex on via2</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via2_angle</name>
+ <description>ACUTE : non 45 degree angle via2</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>metal3_OFFGRID</name>
+ <description>OFFGRID : OFFGRID vertex on metal3</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>metal3_angle</name>
+ <description>ACUTE : non 45 degree angle metal3</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via3_OFFGRID</name>
+ <description>OFFGRID : OFFGRID vertex on via3</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via3_angle</name>
+ <description>ACUTE : non 45 degree angle via3</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>metal4_OFFGRID</name>
+ <description>OFFGRID : OFFGRID vertex on metal4</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>metal4_angle</name>
+ <description>ACUTE : non 45 degree angle metal4</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via4_OFFGRID</name>
+ <description>OFFGRID : OFFGRID vertex on via4</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via4_angle</name>
+ <description>ACUTE : non 45 degree angle via4</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>metal5_OFFGRID</name>
+ <description>OFFGRID : OFFGRID vertex on metal5</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>metal5_angle</name>
+ <description>ACUTE : non 45 degree angle metal5</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via5_OFFGRID</name>
+ <description>OFFGRID : OFFGRID vertex on via5</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via5_angle</name>
+ <description>ACUTE : non 45 degree angle via5</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>metaltop_OFFGRID</name>
+ <description>OFFGRID : OFFGRID vertex on metaltop</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>metaltop_angle</name>
+ <description>ACUTE : non 45 degree angle metaltop</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>pad_OFFGRID</name>
+ <description>OFFGRID : OFFGRID vertex on pad</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>pad_angle</name>
+ <description>ACUTE : non 45 degree angle pad</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>resistor_OFFGRID</name>
+ <description>OFFGRID : OFFGRID vertex on resistor</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>resistor_angle</name>
+ <description>ACUTE : non 45 degree angle resistor</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>fhres_OFFGRID</name>
+ <description>OFFGRID : OFFGRID vertex on fhres</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>fhres_angle</name>
+ <description>ACUTE : non 45 degree angle fhres</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>fusetop_OFFGRID</name>
+ <description>OFFGRID : OFFGRID vertex on fusetop</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>fusetop_angle</name>
+ <description>ACUTE : non 45 degree angle fusetop</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>fusewindow_d_OFFGRID</name>
+ <description>OFFGRID : OFFGRID vertex on fusewindow_d</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>fusewindow_d_angle</name>
+ <description>ACUTE : non 45 degree angle fusewindow_d</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>polyfuse_OFFGRID</name>
+ <description>OFFGRID : OFFGRID vertex on polyfuse</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>polyfuse_angle</name>
+ <description>ACUTE : non 45 degree angle polyfuse</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>mvsd_OFFGRID</name>
+ <description>OFFGRID : OFFGRID vertex on mvsd</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>mvsd_angle</name>
+ <description>ACUTE : non 45 degree angle mvsd</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>mvpsd_OFFGRID</name>
+ <description>OFFGRID : OFFGRID vertex on mvpsd</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>mvpsd_angle</name>
+ <description>ACUTE : non 45 degree angle mvpsd</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>nat_OFFGRID</name>
+ <description>OFFGRID : OFFGRID vertex on nat</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>nat_angle</name>
+ <description>ACUTE : non 45 degree angle nat</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>comp_dummy_OFFGRID</name>
+ <description>OFFGRID : OFFGRID vertex on comp_dummy</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>comp_dummy_angle</name>
+ <description>ACUTE : non 45 degree angle comp_dummy</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>poly2_dummy_OFFGRID</name>
+ <description>OFFGRID : OFFGRID vertex on poly2_dummy</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>poly2_dummy_angle</name>
+ <description>ACUTE : non 45 degree angle poly2_dummy</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>metal1_dummy_OFFGRID</name>
+ <description>OFFGRID : OFFGRID vertex on metal1_dummy</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>metal1_dummy_angle</name>
+ <description>ACUTE : non 45 degree angle metal1_dummy</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>metal2_dummy_OFFGRID</name>
+ <description>OFFGRID : OFFGRID vertex on metal2_dummy</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>metal2_dummy_angle</name>
+ <description>ACUTE : non 45 degree angle metal2_dummy</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>metal3_dummy_OFFGRID</name>
+ <description>OFFGRID : OFFGRID vertex on metal3_dummy</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>metal3_dummy_angle</name>
+ <description>ACUTE : non 45 degree angle metal3_dummy</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>metal4_dummy_OFFGRID</name>
+ <description>OFFGRID : OFFGRID vertex on metal4_dummy</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>metal4_dummy_angle</name>
+ <description>ACUTE : non 45 degree angle metal4_dummy</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>metal5_dummy_OFFGRID</name>
+ <description>OFFGRID : OFFGRID vertex on metal5_dummy</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>metal5_dummy_angle</name>
+ <description>ACUTE : non 45 degree angle metal5_dummy</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>metaltop_dummy_OFFGRID</name>
+ <description>OFFGRID : OFFGRID vertex on metaltop_dummy</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>metaltop_dummy_angle</name>
+ <description>ACUTE : non 45 degree angle metaltop_dummy</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>comp_label_OFFGRID</name>
+ <description>OFFGRID : OFFGRID vertex on comp_label</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>comp_label_angle</name>
+ <description>ACUTE : non 45 degree angle comp_label</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>poly2_label_OFFGRID</name>
+ <description>OFFGRID : OFFGRID vertex on poly2_label</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>poly2_label_angle</name>
+ <description>ACUTE : non 45 degree angle poly2_label</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>metal1_label_OFFGRID</name>
+ <description>OFFGRID : OFFGRID vertex on metal1_label</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>metal1_label_angle</name>
+ <description>ACUTE : non 45 degree angle metal1_label</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>metal2_label_OFFGRID</name>
+ <description>OFFGRID : OFFGRID vertex on metal2_label</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>metal2_label_angle</name>
+ <description>ACUTE : non 45 degree angle metal2_label</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>metal3_label_OFFGRID</name>
+ <description>OFFGRID : OFFGRID vertex on metal3_label</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>metal3_label_angle</name>
+ <description>ACUTE : non 45 degree angle metal3_label</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>metal4_label_OFFGRID</name>
+ <description>OFFGRID : OFFGRID vertex on metal4_label</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>metal4_label_angle</name>
+ <description>ACUTE : non 45 degree angle metal4_label</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>metal5_label_OFFGRID</name>
+ <description>OFFGRID : OFFGRID vertex on metal5_label</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>metal5_label_angle</name>
+ <description>ACUTE : non 45 degree angle metal5_label</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>metaltop_label_OFFGRID</name>
+ <description>OFFGRID : OFFGRID vertex on metaltop_label</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>metaltop_label_angle</name>
+ <description>ACUTE : non 45 degree angle metaltop_label</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>metal1_slot_OFFGRID</name>
+ <description>OFFGRID : OFFGRID vertex on metal1_slot</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>metal1_slot_angle</name>
+ <description>ACUTE : non 45 degree angle metal1_slot</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>metal2_slot_OFFGRID</name>
+ <description>OFFGRID : OFFGRID vertex on metal2_slot</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>metal2_slot_angle</name>
+ <description>ACUTE : non 45 degree angle metal2_slot</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>metal3_slot_OFFGRID</name>
+ <description>OFFGRID : OFFGRID vertex on metal3_slot</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>metal3_slot_angle</name>
+ <description>ACUTE : non 45 degree angle metal3_slot</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>metal4_slot_OFFGRID</name>
+ <description>OFFGRID : OFFGRID vertex on metal4_slot</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>metal4_slot_angle</name>
+ <description>ACUTE : non 45 degree angle metal4_slot</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>metal5_slot_OFFGRID</name>
+ <description>OFFGRID : OFFGRID vertex on metal5_slot</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>metal5_slot_angle</name>
+ <description>ACUTE : non 45 degree angle metal5_slot</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>metaltop_slot_OFFGRID</name>
+ <description>OFFGRID : OFFGRID vertex on metaltop_slot</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>metaltop_slot_angle</name>
+ <description>ACUTE : non 45 degree angle metaltop_slot</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>ubmpperi_OFFGRID</name>
+ <description>OFFGRID : OFFGRID vertex on ubmpperi</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>ubmpperi_angle</name>
+ <description>ACUTE : non 45 degree angle ubmpperi</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>ubmparray_OFFGRID</name>
+ <description>OFFGRID : OFFGRID vertex on ubmparray</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>ubmparray_angle</name>
+ <description>ACUTE : non 45 degree angle ubmparray</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>ubmeplate_OFFGRID</name>
+ <description>OFFGRID : OFFGRID vertex on ubmeplate</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>ubmeplate_angle</name>
+ <description>ACUTE : non 45 degree angle ubmeplate</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>schottky_diode_OFFGRID</name>
+ <description>OFFGRID : OFFGRID vertex on schottky_diode</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>schottky_diode_angle</name>
+ <description>ACUTE : non 45 degree angle schottky_diode</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>zener_OFFGRID</name>
+ <description>OFFGRID : OFFGRID vertex on zener</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>zener_angle</name>
+ <description>ACUTE : non 45 degree angle zener</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>res_mk_OFFGRID</name>
+ <description>OFFGRID : OFFGRID vertex on res_mk</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>res_mk_angle</name>
+ <description>ACUTE : non 45 degree angle res_mk</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>opc_drc_OFFGRID</name>
+ <description>OFFGRID : OFFGRID vertex on opc_drc</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>opc_drc_angle</name>
+ <description>ACUTE : non 45 degree angle opc_drc</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>ndmy_OFFGRID</name>
+ <description>OFFGRID : OFFGRID vertex on ndmy</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>ndmy_angle</name>
+ <description>ACUTE : non 45 degree angle ndmy</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>pmndmy_OFFGRID</name>
+ <description>OFFGRID : OFFGRID vertex on pmndmy</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>pmndmy_angle</name>
+ <description>ACUTE : non 45 degree angle pmndmy</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>v5_xtor_OFFGRID</name>
+ <description>OFFGRID : OFFGRID vertex on v5_xtor</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>v5_xtor_angle</name>
+ <description>ACUTE : non 45 degree angle v5_xtor</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>cap_mk_OFFGRID</name>
+ <description>OFFGRID : OFFGRID vertex on cap_mk</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>cap_mk_angle</name>
+ <description>ACUTE : non 45 degree angle cap_mk</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>mos_cap_mk_OFFGRID</name>
+ <description>OFFGRID : OFFGRID vertex on mos_cap_mk</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>mos_cap_mk_angle</name>
+ <description>ACUTE : non 45 degree angle mos_cap_mk</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>ind_mk_OFFGRID</name>
+ <description>OFFGRID : OFFGRID vertex on ind_mk</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>ind_mk_angle</name>
+ <description>ACUTE : non 45 degree angle ind_mk</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>diode_mk_OFFGRID</name>
+ <description>OFFGRID : OFFGRID vertex on diode_mk</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>diode_mk_angle</name>
+ <description>ACUTE : non 45 degree angle diode_mk</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>drc_bjt_OFFGRID</name>
+ <description>OFFGRID : OFFGRID vertex on drc_bjt</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>drc_bjt_angle</name>
+ <description>ACUTE : non 45 degree angle drc_bjt</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>lvs_bjt_OFFGRID</name>
+ <description>OFFGRID : OFFGRID vertex on lvs_bjt</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>lvs_bjt_angle</name>
+ <description>ACUTE : non 45 degree angle lvs_bjt</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>mim_l_mk_OFFGRID</name>
+ <description>OFFGRID : OFFGRID vertex on mim_l_mk</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>mim_l_mk_angle</name>
+ <description>ACUTE : non 45 degree angle mim_l_mk</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>latchup_mk_OFFGRID</name>
+ <description>OFFGRID : OFFGRID vertex on latchup_mk</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>latchup_mk_angle</name>
+ <description>ACUTE : non 45 degree angle latchup_mk</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>guard_ring_mk_OFFGRID</name>
+ <description>OFFGRID : OFFGRID vertex on guard_ring_mk</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>guard_ring_mk_angle</name>
+ <description>ACUTE : non 45 degree angle guard_ring_mk</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>otp_mk_OFFGRID</name>
+ <description>OFFGRID : OFFGRID vertex on otp_mk</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>otp_mk_angle</name>
+ <description>ACUTE : non 45 degree angle otp_mk</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>mtpmark_OFFGRID</name>
+ <description>OFFGRID : OFFGRID vertex on mtpmark</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>mtpmark_angle</name>
+ <description>ACUTE : non 45 degree angle mtpmark</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>neo_ee_mk_OFFGRID</name>
+ <description>OFFGRID : OFFGRID vertex on neo_ee_mk</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>neo_ee_mk_angle</name>
+ <description>ACUTE : non 45 degree angle neo_ee_mk</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>sramcore_OFFGRID</name>
+ <description>OFFGRID : OFFGRID vertex on sramcore</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>sramcore_angle</name>
+ <description>ACUTE : non 45 degree angle sramcore</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>lvs_rf_OFFGRID</name>
+ <description>OFFGRID : OFFGRID vertex on lvs_rf</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>lvs_rf_angle</name>
+ <description>ACUTE : non 45 degree angle lvs_rf</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>lvs_drain_OFFGRID</name>
+ <description>OFFGRID : OFFGRID vertex on lvs_drain</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>lvs_drain_angle</name>
+ <description>ACUTE : non 45 degree angle lvs_drain</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvpolyrs_OFFGRID</name>
+ <description>OFFGRID : OFFGRID vertex on hvpolyrs</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvpolyrs_angle</name>
+ <description>ACUTE : non 45 degree angle hvpolyrs</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>lvs_io_OFFGRID</name>
+ <description>OFFGRID : OFFGRID vertex on lvs_io</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>lvs_io_angle</name>
+ <description>ACUTE : non 45 degree angle lvs_io</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>probe_mk_OFFGRID</name>
+ <description>OFFGRID : OFFGRID vertex on probe_mk</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>probe_mk_angle</name>
+ <description>ACUTE : non 45 degree angle probe_mk</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>esd_mk_OFFGRID</name>
+ <description>OFFGRID : OFFGRID vertex on esd_mk</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>esd_mk_angle</name>
+ <description>ACUTE : non 45 degree angle esd_mk</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>lvs_source_OFFGRID</name>
+ <description>OFFGRID : OFFGRID vertex on lvs_source</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>lvs_source_angle</name>
+ <description>ACUTE : non 45 degree angle lvs_source</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>well_diode_mk_OFFGRID</name>
+ <description>OFFGRID : OFFGRID vertex on well_diode_mk</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>well_diode_mk_angle</name>
+ <description>ACUTE : non 45 degree angle well_diode_mk</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>ldmos_xtor_OFFGRID</name>
+ <description>OFFGRID : OFFGRID vertex on ldmos_xtor</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>ldmos_xtor_angle</name>
+ <description>ACUTE : non 45 degree angle ldmos_xtor</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>plfuse_OFFGRID</name>
+ <description>OFFGRID : OFFGRID vertex on plfuse</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>plfuse_angle</name>
+ <description>ACUTE : non 45 degree angle plfuse</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>efuse_mk_OFFGRID</name>
+ <description>OFFGRID : OFFGRID vertex on efuse_mk</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>efuse_mk_angle</name>
+ <description>ACUTE : non 45 degree angle efuse_mk</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>mcell_feol_mk_OFFGRID</name>
+ <description>OFFGRID : OFFGRID vertex on mcell_feol_mk</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>mcell_feol_mk_angle</name>
+ <description>ACUTE : non 45 degree angle mcell_feol_mk</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>ymtp_mk_OFFGRID</name>
+ <description>OFFGRID : OFFGRID vertex on ymtp_mk</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>ymtp_mk_angle</name>
+ <description>ACUTE : non 45 degree angle ymtp_mk</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>dev_wf_mk_OFFGRID</name>
+ <description>OFFGRID : OFFGRID vertex on dev_wf_mk</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>dev_wf_mk_angle</name>
+ <description>ACUTE : non 45 degree angle dev_wf_mk</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>metal1_blk_OFFGRID</name>
+ <description>OFFGRID : OFFGRID vertex on metal1_blk</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>metal1_blk_angle</name>
+ <description>ACUTE : non 45 degree angle metal1_blk</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>metal2_blk_OFFGRID</name>
+ <description>OFFGRID : OFFGRID vertex on metal2_blk</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>metal2_blk_angle</name>
+ <description>ACUTE : non 45 degree angle metal2_blk</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>metal3_blk_OFFGRID</name>
+ <description>OFFGRID : OFFGRID vertex on metal3_blk</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>metal3_blk_angle</name>
+ <description>ACUTE : non 45 degree angle metal3_blk</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>metal4_blk_OFFGRID</name>
+ <description>OFFGRID : OFFGRID vertex on metal4_blk</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>metal4_blk_angle</name>
+ <description>ACUTE : non 45 degree angle metal4_blk</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>metal5_blk_OFFGRID</name>
+ <description>OFFGRID : OFFGRID vertex on metal5_blk</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>metal5_blk_angle</name>
+ <description>ACUTE : non 45 degree angle metal5_blk</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>metalt_blk_OFFGRID</name>
+ <description>OFFGRID : OFFGRID vertex on metalt_blk</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>metalt_blk_angle</name>
+ <description>ACUTE : non 45 degree angle metalt_blk</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>pr_bndry_OFFGRID</name>
+ <description>OFFGRID : OFFGRID vertex on pr_bndry</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>pr_bndry_angle</name>
+ <description>ACUTE : non 45 degree angle pr_bndry</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>mdiode_OFFGRID</name>
+ <description>OFFGRID : OFFGRID vertex on mdiode</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>mdiode_angle</name>
+ <description>ACUTE : non 45 degree angle mdiode</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>metal1_res_OFFGRID</name>
+ <description>OFFGRID : OFFGRID vertex on metal1_res</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>metal1_res_angle</name>
+ <description>ACUTE : non 45 degree angle metal1_res</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>metal2_res_OFFGRID</name>
+ <description>OFFGRID : OFFGRID vertex on metal2_res</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>metal2_res_angle</name>
+ <description>ACUTE : non 45 degree angle metal2_res</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>metal3_res_OFFGRID</name>
+ <description>OFFGRID : OFFGRID vertex on metal3_res</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>metal3_res_angle</name>
+ <description>ACUTE : non 45 degree angle metal3_res</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>metal4_res_OFFGRID</name>
+ <description>OFFGRID : OFFGRID vertex on metal4_res</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>metal4_res_angle</name>
+ <description>ACUTE : non 45 degree angle metal4_res</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>metal5_res_OFFGRID</name>
+ <description>OFFGRID : OFFGRID vertex on metal5_res</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>metal5_res_angle</name>
+ <description>ACUTE : non 45 degree angle metal5_res</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>metal6_res_OFFGRID</name>
+ <description>OFFGRID : OFFGRID vertex on metal6_res</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>metal6_res_angle</name>
+ <description>ACUTE : non 45 degree angle metal6_res</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>border_OFFGRID</name>
+ <description>OFFGRID : OFFGRID vertex on border</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>border_angle</name>
+ <description>ACUTE : non 45 degree angle border</description>
+ <categories>
+ </categories>
+ </category>
+ </categories>
+ <cells>
+ <cell>
+ <name>user_project_wrapper</name>
+ <variant/>
+ <references>
+ </references>
+ </cell>
+ </cells>
+ <items>
+ </items>
+</report-database>
diff --git a/mpw_precheck/outputs/reports/klayout_met_min_ca_density_check.xml b/mpw_precheck/outputs/reports/klayout_met_min_ca_density_check.xml
new file mode 100644
index 0000000..b3fc698
--- /dev/null
+++ b/mpw_precheck/outputs/reports/klayout_met_min_ca_density_check.xml
@@ -0,0 +1,27 @@
+<?xml version="1.0" encoding="utf-8"?>
+<report-database>
+ <description>Density Checks</description>
+ <original-file/>
+ <generator>drc: script='/opt/checks/drc_checks/klayout/gf180mcu_density.lydrc'</generator>
+ <top-cell>user_project_wrapper</top-cell>
+ <tags>
+ </tags>
+ <categories>
+ <category>
+ <name>comp.density</name>
+ <description>0.7 max comp density</description>
+ <categories>
+ </categories>
+ </category>
+ </categories>
+ <cells>
+ <cell>
+ <name>user_project_wrapper</name>
+ <variant/>
+ <references>
+ </references>
+ </cell>
+ </cells>
+ <items>
+ </items>
+</report-database>
diff --git a/mpw_precheck/outputs/reports/klayout_offgrid_check.xml b/mpw_precheck/outputs/reports/klayout_offgrid_check.xml
new file mode 100644
index 0000000..b73ff41
--- /dev/null
+++ b/mpw_precheck/outputs/reports/klayout_offgrid_check.xml
@@ -0,0 +1,2535 @@
+<?xml version="1.0" encoding="utf-8"?>
+<report-database>
+ <description>DRC Run Report at</description>
+ <original-file/>
+ <generator>drc: script='/opt/checks/tech-files/gf180mcuC_mr.drc'</generator>
+ <top-cell>user_project_wrapper</top-cell>
+ <tags>
+ </tags>
+ <categories>
+ <category>
+ <name>MC.1</name>
+ <description>MC.1 : min. mcell width : 0.4µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>MC.2</name>
+ <description>MC.2 : min. mcell spacing : 0.4µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>MC.3</name>
+ <description>MC.3 : Minimum Mcell area : 0.35µm²</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>MC.4</name>
+ <description>MC.4 : Minimum area enclosed by Mcell : 0.35µm²</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>PRES.1</name>
+ <description>PRES.1 : Minimum width of Poly2 resistor. : 0.8µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>PRES.2</name>
+ <description>PRES.2 : Minimum space between Poly2 resistors. : 0.4µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>PRES.3</name>
+ <description>PRES.3 : Minimum space from Poly2 resistor to COMP.</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>PRES.4</name>
+ <description>PRES.4 : Minimum space from Poly2 resistor to unrelated Poly2. : 0.6µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>PRES.5</name>
+ <description>PRES.5 : Minimum Plus implant overlap of Poly2 resistor. : 0.3µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>PRES.6</name>
+ <description>PRES.6 : Minimum salicide block overlap of Poly2 resistor in width direction. : 0.28µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>PRES.7</name>
+ <description>PRES.7 : Space from salicide block to contact on Poly2 resistor.</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>PRES.9a</name>
+ <description>PRES.9a : Pplus Poly2 resistor shall be covered by RES_MK marking. RES_MK length shall be coincide with resistor length (Defined by SAB length) and width covering the width of Poly2.</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>PRES.9b</name>
+ <description>PRES.9b : If the size of single RES_MK mark layer is greater than 15000um2 and both side (X and Y) are greater than 80um. then the minimum spacing to adjacent RES_MK layer. : 20µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>LRES.1</name>
+ <description>LRES.1 : Minimum width of Poly2 resistor. : 0.8µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>LRES.2</name>
+ <description>LRES.2 : Minimum space between Poly2 resistors. : 0.4µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>LRES.3</name>
+ <description>LRES.3 : Minimum space from Poly2 resistor to COMP.</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>LRES.4</name>
+ <description>LRES.4 : Minimum space from Poly2 resistor to unrelated Poly2. : 0.6µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>LRES.5</name>
+ <description>LRES.5 : Minimum Nplus implant overlap of Poly2 resistor. : 0.3µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>LRES.6</name>
+ <description>LRES.6 : Minimum salicide block overlap of Poly2 resistor in width direction. : 0.28µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>LRES.7</name>
+ <description>LRES.7 : Space from salicide block to contact on Poly2 resistor.</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>LRES.9a</name>
+ <description>LRES.9a : Nplus Poly2 resistor shall be covered by RES_MK marking. RES_MK length shall be coincide with resistor length (Defined by SAB length) and width covering the width of Poly2. </description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>LRES.9b</name>
+ <description>LRES.9b : If the size of single RES_MK mark layer is greater than 15000um2 and both side (X and Y) are greater than 80um. then the minimum spacing to adjacent RES_MK layer. : 20µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>HRES.1</name>
+ <description>HRES.1 : Minimum space. Note : Merge if the spacing is less than 0.4 um. : 0.4µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>HRES.2</name>
+ <description>HRES.2 : Minimum width of Poly2 resistor. : 1µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>HRES.3</name>
+ <description>HRES.3 : Minimum space between Poly2 resistors. : 0.4µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>HRES.4</name>
+ <description>HRES.4 : Minimum RESISTOR overlap of Poly2 resistor. : 0.4µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>HRES.5</name>
+ <description>HRES.5 : Minimum RESISTOR space to unrelated Poly2. : 0.3µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>HRES.6</name>
+ <description>HRES.6 : Minimum RESISTOR space to COMP.</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>HRES.7</name>
+ <description>HRES.7 : Minimum Pplus overlap of contact on Poly2 resistor. : 0.2µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>HRES.8</name>
+ <description>HRES.8 : Space from salicide block to contact on Poly2 resistor.</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>HRES.9</name>
+ <description>HRES.9 : Minimum salicide block overlap of Poly2 resistor in width direction.</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>HRES.10</name>
+ <description>HRES.10 : Minimum & maximum Pplus overlap of SAB.</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>HRES.12a</name>
+ <description>HRES.12a : P type Poly2 resistor (high sheet rho) shall be covered by RES_MK marking. RES_MK length shall be coincide with resistor length (Defined by Pplus space) and width covering the width of Poly2. </description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>HRES.12b</name>
+ <description>HRES.12b : If the size of single RES_MK mark layer is greater than 15000 um2 and both side (X and Y) are greater than 80 um. Then the minimum spacing to adjacent RES_MK layer. : 20µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>MIMTM.1</name>
+ <description>MIMTM.1 : Minimum MiM bottom plate spacing to the bottom plate metal (whether adjacent MiM or routing metal). : 1.2µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>MIMTM.2</name>
+ <description>MIMTM.2 : Minimum MiM bottom plate overlap of Vian-1 layer. [This is applicable for Vian-1 within 1.06um oversize of FuseTop layer (referenced to virtual bottom plate)]. : 0.4µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>MIMTM.3</name>
+ <description>MIMTM.3 : Minimum MiM bottom plate overlap of Top plate.</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>MIMTM.4</name>
+ <description>MIMTM.4 : Minimum MiM top plate (FuseTop) overlap of Vian-1. : 0.4µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>MIMTM.5</name>
+ <description>MIMTM.5 : Minimum spacing between top plate and the Vian-1 connecting to the bottom plate. : 0.4µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>MIMTM.6</name>
+ <description>MIMTM.6 : Minimum spacing between unrelated top plates. : 0.6µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>MIMTM.7</name>
+ <description>MIMTM.7 : Min FuseTop enclosure by CAP_MK.</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>MIMTM.8a</name>
+ <description>MIMTM.8a : Minimum MIM cap area (defined by FuseTop area) (um2). : 25µm²</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>MIMTM.8b</name>
+ <description>MIMTM.8b : Maximum single MIM Cap area (Use multiple MIM caps in parallel connection if bigger capacitors are required) (um2). : 10000µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>MIMTM.9</name>
+ <description>MIMTM.9 : Min. Via (Vian-1) spacing for sea of Via on MIM top plate. : 0.5µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>MIMTM.10</name>
+ <description>MIMTM.10 : (a) There cannot be any Vian-2 touching MIM bottom plate Metaln-1. (b) MIM bottom plate Metaln-1 can only be connected through the higher Via (Vian-1).</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>MIMTM.11</name>
+ <description>MIMTM.11 : Bottom plate of multiple MIM caps can be shared (for common nodes) as long as total MIM area with that single common plate does not exceed MIMTM.8b rule. : -µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>NAT.1</name>
+ <description>NAT.1 : Min. NAT Overlap of COMP of Native Vt NMOS. : 2µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>NAT.2</name>
+ <description>NAT.2 : Space to unrelated COMP (outside NAT). : 0.3µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>NAT.3</name>
+ <description>NAT.3 : Space to NWell edge. : 0.5µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>NAT.4</name>
+ <description>NAT.4 : Minimum channel length for 3.3V Native Vt NMOS (For smaller L Ioff will be higher than Spec). : 1.8µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>NAT.5</name>
+ <description>NAT.5 : Minimum channel length for 6.0V Native Vt NMOS (For smaller L Ioff will be higher than Spec). : 1.8µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>NAT.6</name>
+ <description>NAT.6 : Two or more COMPs if connected to different potential are not allowed under same NAT layer.</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>NAT.7</name>
+ <description>NAT.7 : Minimum NAT to NAT spacing. : 0.74µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>NAT.8</name>
+ <description>NAT.8 : Min. Dualgate overlap of NAT (for 5V/6V) native VT NMOS only.</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>NAT.9</name>
+ <description>NAT.9 : Poly interconnect under NAT layer is not allowed, minimum spacing of un-related poly from the NAT layer.</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>NAT.10</name>
+ <description>NAT.10 : Nwell, inside NAT layer are not allowed.</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>NAT.11</name>
+ <description>NAT.11 : NCOMP not intersecting to Poly2, is not allowed inside NAT layer.</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>NAT.12</name>
+ <description>NAT.12 : Poly2 not intersecting with COMP is not allowed inside NAT (Poly2 resistor is not allowed inside NAT).</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>BJT.1</name>
+ <description>BJT.1 : Min. DRC_BJT overlap of DNWELL for NPN BJT.</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>BJT.2</name>
+ <description>BJT.2 : Min. DRC_BJT overlap of PCOM in Psub.</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>BJT.3</name>
+ <description>BJT.3 : Minimum space of DRC_BJT layer to unrelated COMP. : 0.1µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>DE.2</name>
+ <description>DE.2 : Minimum NDMY or PMNDMY size (x or y dimension in um). : 0.8µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>DE.3</name>
+ <description>DE.3 : If size greater than 15000 um2 then two sides should not be greater than (um).</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>DE.4</name>
+ <description>DE.4 : Minimum NDMY to NDMY space (Merge if space is less). : 20µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>LVS_BJT.1</name>
+ <description>LVS_BJT.1 : Minimum LVS_BJT enclosure of NPN or PNP Emitter COMP layers</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>O.DF.3a</name>
+ <description>O.DF.3a : Min. COMP Space. P-substrate tap (PCOMP outside NWELL) can be butted for different voltage devices as the potential is same. : 0.24µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>O.DF.6</name>
+ <description>O.DF.6 : Min. COMP extend beyond poly2 (it also means source/drain overhang). : 0.22µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>O.DF.9</name>
+ <description>O.DF.9 : Min. COMP area (um2). : 0.1444µm²</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>O.PL.2</name>
+ <description>O.PL.2 : Min. poly2 width. : 0.22µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>O.PL.3a</name>
+ <description>O.PL.3a : Min. poly2 Space on COMP. : 0.18µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>O.PL.4</name>
+ <description>O.PL.4 : Min. extension beyond COMP to form Poly2 end cap. : 0.14µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>O.SB.2</name>
+ <description>O.SB.2 : Min. salicide Block Space. : 0.28µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>O.SB.3</name>
+ <description>O.SB.3 : Min. space from salicide block to unrelated COMP. : 0.09µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>O.SB.4</name>
+ <description>O.SB.4 : Min. space from salicide block to contact.</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>O.SB.5b_3.3V</name>
+ <description>O.SB.5b_3.3V : Min. space from salicide block to unrelated Poly2 on COMP. : 0.1µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>O.SB.9</name>
+ <description>O.SB.9 : Min. salicide block extension beyond unsalicided Poly2. : 0.1µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>O.SB.11</name>
+ <description>O.SB.11 : Min. salicide block overlap with COMP. : 0.04µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>O.SB.13_3.3V</name>
+ <description>O.SB.13_3.3V : Min. area of silicide block (um2). : 1.488µm²</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>O.SB.13_5V</name>
+ <description>O.SB.13_5V : Min. area of silicide block (um2). : 2µm²</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>O.CO.7</name>
+ <description>O.CO.7 : Min. space from COMP contact to Poly2 on COMP. : 0.13µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>O.PL.ORT</name>
+ <description>O.PL.ORT : Orientation-restricted gates must have the gate width aligned along the X-axis (poly line running horizontally) in reference to wafer notch down. : 0µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>EF.01</name>
+ <description>EF.01 : Min. (Poly2 butt PLFUSE) within EFUSE_MK and Pplus.</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>EF.02</name>
+ <description>EF.02 : Min. Max. PLFUSE width. : 0.18µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>EF.03</name>
+ <description>EF.03 : Min. Max. PLFUSE length. : 1.26µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>EF.04a</name>
+ <description>EF.04a : Min. Max. PLFUSE overlap Poly2 (coinciding permitted) and touch cathode and anode.</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>EF.04b</name>
+ <description>EF.04b : PLFUSE must be rectangular. : -µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>EF.04c</name>
+ <description>EF.04c : Cathode Poly2 must be rectangular. : -µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>EF.04d</name>
+ <description>EF.04d : Anode Poly2 must be rectangular. : -µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>EF.05</name>
+ <description>EF.05 : Min./Max. LVS_Source overlap Poly2 (at Anode).</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>EF.06</name>
+ <description>EF.06 : Min./Max. Cathode Poly2 width. : 2.26µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>EF.07</name>
+ <description>EF.07 : Min./Max. Cathode Poly2 length. : 1.84µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>EF.08</name>
+ <description>EF.08 : Min./Max. Anode Poly2 width. : 1.06µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>EF.09</name>
+ <description>EF.09 : Min./Max. Anode Poly2 length. : 2.43µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>EF.10</name>
+ <description>EF.10 : Min. Cathode Poly2 to Poly2 space. : 0.26µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>EF.11</name>
+ <description>EF.11 : Min. Anode Poly2 to Poly2 space. : 0.26µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>EF.12</name>
+ <description>EF.12 : Min. Space of Cathode Contact to PLFUSE end.</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>EF.13</name>
+ <description>EF.13 : Min. Space of Anode Contact to PLFUSE end.</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>EF.14</name>
+ <description>EF.14 : Min. EFUSE_MK enclose LVS_Source.</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>EF.15</name>
+ <description>EF.15 : NO Contact is allowed to touch PLFUSE.</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>EF.16a</name>
+ <description>EF.16a : Cathode must contain exact number of Contacts at each ends. : 4µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>EF.16b</name>
+ <description>EF.16b : Anode must contain exact number of Contacts at each ends. : 4µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>EF.17</name>
+ <description>EF.17 : Min. Space of EFUSE_MK to EFUSE_MK. : 0.26µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>EF.18</name>
+ <description>EF.18 : PLFUSE must sit on field oxide (NOT COMP), no cross with any COMP, Nplus, Pplus, ESD, SAB, Resistor, Metal1, Metal2.</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>EF.19</name>
+ <description>EF.19 : Min. PLFUSE space to Metal1, Metal2.</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>EF.20</name>
+ <description>EF.20 : Min. PLFUSE space to COMP, Nplus, Pplus, Resistor, ESD, SAB. : 2.73µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>EF.21</name>
+ <description>EF.21 : Min./Max. eFUSE Poly2 length. : 5.53µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>EF.22a</name>
+ <description>EF.22a : Min./Max. Cathode Poly2 overlap with PLFUSE in width direction. : 1.04µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>EF.22b</name>
+ <description>EF.22b : Min./Max. Anode Poly2 overlap with PLFUSE in width direction. : 0.44µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>MDN.1</name>
+ <description>MDN.1 : Min MVSD width (for litho purpose). : 1µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>MDN.2a</name>
+ <description>MDN.2a : Min MVSD space [Same Potential]. : 1µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>MDN.2b</name>
+ <description>MDN.2b : Min MVSD space [Diff Potential]. : 2µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>MDN.3a</name>
+ <description>MDN.3a : Min transistor channel length. : 0.6µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>MDN.3b</name>
+ <description>MDN.3b : Max transistor channel length: 20 um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>MDN.4a</name>
+ <description>MDN.4a : Min transistor channel width. : 4 µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>MDN.4b</name>
+ <description>MDN.4b : Max transistor channel width. : 50 um </description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>MDN.5ai</name>
+ <description>MDN.5ai : Min PCOMP (Pplus AND COMP) space to LDNMOS Drain MVSD (source and body tap non-butted). PCOMP (Pplus AND COMP) intercept with LDNMOS Drain MVSD is not allowed.</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>MDN.5aii</name>
+ <description>MDN.5aii : Min PCOMP (Pplus AND COMP) space to LDNMOS Drain MVSD (source and body tap butted). PCOMP (Pplus AND COMP) intercept with LDNMOS Drain MVSD is not allowed. : 0.92µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>MDN.5b</name>
+ <description>MDN.5b : Min PCOMP (Pplus AND COMP) space to LDNMOS Source (Nplus AND COMP). Use butted source and p-substrate tab otherwise and that is good for Latch-up immunity as well.</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>MDN.5c</name>
+ <description>MDN.5c : Maximum distance of the nearest edge of the substrate tab from NCOMP edge. : 15µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>MDN.6</name>
+ <description>MDN.6 : ALL LDNMOS shall be covered by Dualgate layer.</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>MDN.6a</name>
+ <description>MDN.6a : Min Dualgate enclose NCOMP.</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>MDN.7</name>
+ <description>MDN.7 : Each LDNMOS shall be covered by LDMOS_XTOR (GDS#226) mark layer.</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>MDN.7a</name>
+ <description>MDN.7a : Min LDMOS_XTOR enclose Dualgate.</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>MDN.8a</name>
+ <description>MDN.8a : Min LDNMOS drain MVSD space to any other equal potential Nwell space.</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>MDN.8b</name>
+ <description>MDN.8b : Min LDNMOS drain MVSD space to any other different potential Nwell space.</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>MDN.9</name>
+ <description>MDN.9 : Min LDNMOS drain MVSD space to NCOMP (Nplus AND COMP) outside LDNMOS drain MVSD. : 4µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>MDN.10a</name>
+ <description>MDN.10a : Min LDNMOS POLY2 width. : 1.2µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>MDN.10b</name>
+ <description>MDN.10b : Min POLY2 extension beyond COMP in the width direction of the transistor (other than the LDNMOS drain direction). : 0.4µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>MDN.10c</name>
+ <description>MDN.10c : Min/Max POLY2 extension beyond COMP on the field towards LDNMOS drain COMP direction.</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>MDN.10d</name>
+ <description>MDN.10d : Min/Max POLY2 on field space to LDNMOS drain COMP.</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>MDN.10ei</name>
+ <description>MDN.10ei : Min POLY2 space to Psub tap (source and body tap non-butted).</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>MDN.10eii</name>
+ <description>MDN.10eii : Min POLY2 space to Psub tap (source and body tap butted). : 0.32µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>MDN.10f</name>
+ <description>MDN.10f : Poly2 interconnect in HV region (LDMOS_XTOR marked region) not allowed. Also, any Poly2 interconnect with poly2 to substrate potential greater than 6V is not allowed.</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>MDN.11</name>
+ <description>MDN.11 : Min/Max MVSD overlap channel COMP ((((LDMOS_XTOR AND MVSD) AND COMP) AND POLY2) AND NPlus).</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>MDN.12</name>
+ <description>MDN.12 : Min MVSD enclose NCOMP in the LDNMOS drain and in the direction along the transistor width.</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>MDN.13a</name>
+ <description>MDN.13a : Max single finger width. : 50µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>MDN.13b</name>
+ <description>MDN.13b : Layout shall have alternative source & drain.</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>MDN.13c</name>
+ <description>MDN.13c : Both sides of the transistor shall be terminated by source.</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>MDN.13d</name>
+ <description>MDN.13d : Every two poly fingers shall be surrounded by a P-sub guard ring. (Exclude the case when each LDNMOS transistor have full width butting to well tap).</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>MDN.14</name>
+ <description>MDN.14 : Min MVSD space to any DNWELL.</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>MDN.15a</name>
+ <description>MDN.15a : Min LDNMOS drain COMP width. : 0.22µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>MDN.15b</name>
+ <description>MDN.15b : Min LDNMOS drain COMP enclose contact. : 0µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>MDN.17</name>
+ <description>MDN.17 : It is recommended to surround the LDNMOS transistor with non-broken Psub guard ring to improve the latch up immunity. Guideline to improve the latch up immunity.</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>MDP.1</name>
+ <description>MDP.1 : Minimum transistor channel length. : 0.6µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>MDP.1a</name>
+ <description>MDP.1a : Max transistor channel length.</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>MDP.2</name>
+ <description>MDP.2 : Minimum transistor channel width. : 4µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>MDP.3</name>
+ <description>MDP.3 : Each LDPMOS shall be surrounded by non-broken Nplus guard ring inside DNWELL</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>MDP.3ai</name>
+ <description>MDP.3ai : Min NCOMP (Nplus AND COMP) space to MVPSD (source and body tap non-butted). NCOMP (Nplus AND COMP) intercept with MVPSD is not allowed.</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>MDP.3aii</name>
+ <description>MDP.3aii : Min NCOMP (Nplus AND COMP) space to MVPSD (source and body tap butted). NCOMP (Nplus AND COMP) intercept with MVPSD is not allowed.</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>MDP.3b</name>
+ <description>MDP.3b : Min NCOMP (Nplus AND COMP) space to PCOMP in DNWELL (Pplus AND COMP AND DNWELL). Use butted source and DNWELL contacts otherwise and that is best for Latch-up immunity as well. : 0.4µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>MDP.3c</name>
+ <description>MDP.3c : Maximum distance of the nearest edge of the DNWELL tab (NCOMP inside DNWELL) from PCOMP edge (PCOMP inside DNWELL). : 15µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>MDP.3d</name>
+ <description>MDP.3d : The metal connection for the Nplus guard ring recommended to be continuous. The maximum gap between this metal if broken. Note: To put maximum number of contact under metal for better manufacturability and reliability. : 10µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>MDP.4</name>
+ <description>MDP.4 : DNWELL covering LDPMOS shall be surrounded by non broken Pplus guard. The metal connection for the Pplus guard ring recommended to be continuous, The maximum gap between this metal if broken. Note: To put maximum number of contact under metal for better manufacturability and reliability.</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>MDP.4a</name>
+ <description>MDP.4a : Min PCOMP (Pplus AND COMP) space to DNWELL. : 2.5µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>MDP.4b</name>
+ <description>MDP.4b : Maximum distance of the nearest edge of the DNWELL from the PCOMP Guard ring outside DNWELL. : 15µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>MDP.5</name>
+ <description>MDP.5 : Each LDPMOS shall be covered by Dualgate layer.</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>MDP.5a</name>
+ <description>MDP.5a : Minimum Dualgate enclose Plus guarding ring PCOMP (Pplus AND COMP). : 0.5µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>MDP.6</name>
+ <description>MDP.6 : Each LDPMOS shall be covered by LDMOS_XTOR (GDS#226) layer.</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>MDP.6a</name>
+ <description>MDP.6a : Minimum LDMOS_XTOR enclose Dualgate.</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>MDP.7</name>
+ <description>MDP.7 : Minimum LDMOS_XTOR layer space to Nwell outside LDMOS_XTOR. : 2µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>MDP.8</name>
+ <description>MDP.8 : Minimum LDMOS_XTOR layer space to NCOMP outside LDMOS_XTOR. : 1.5µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>MDP.9a</name>
+ <description>MDP.9a : Min LDPMOS POLY2 width. : 1.2µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>MDP.9b</name>
+ <description>MDP.9b : Min POLY2 extension beyond COMP in the width direction of the transistor (other than the LDMOS drain direction). : 0.4µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>MDP.9c</name>
+ <description>MDP.9c : Min/Max POLY2 extension beyond COMP on the field towards LDPMOS drain (MVPSD AND COMP AND Pplus NOT POLY2) direction.</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>MDP.9d</name>
+ <description>MDP.9d : Min/Max POLY2 on field to LDPMOS drain COMP (MVPSD AND COMP AND Pplus NOT POLY2) space.</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>MDP.9ei</name>
+ <description>MDP.9ei : Min LDMPOS gate Poly2 space to Nplus guardring (source and body tap non-butted).</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>MDP.9eii</name>
+ <description>MDP.9eii : Min LDMPOS gate Poly2 space to Nplus guardring (source and body tap butted).</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>MDP.9f</name>
+ <description>MDP.9f : Poly2 interconnect is not allowed in LDPMOS region (LDMOS_XTOR marked region). : -µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>MDP.10</name>
+ <description>MDP.10 : Min/Max MVPSD overlap onto the channel (LDMOS_XTOR AND COMP AND POLY2 AND Pplus).</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>MDP.10a</name>
+ <description>MDP.10a : Min MVPSD space within LDMOS_XTOR marking [diff potential]. : 2µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>MDP.10b</name>
+ <description>MDP.10b : Min MVPSD space [same potential]. Merge if space less than 1um. : 1µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>MDP.11</name>
+ <description>MDP.11 : Min MVPSD enclosing PCOMP in the drain (MVPSD AND COMP NOT POLY2) direction and in the direction along the transistor width.</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>MDP.12</name>
+ <description>MDP.12 : Min DNWELL enclose Nplus guard ring (NCOMP). : 0.66µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>MDP.13a</name>
+ <description>MDP.13a : Max single finger width. : 50µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>MDP.13b</name>
+ <description>MDP.13b : Layout shall have alternative source & drain.</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>MDP.13c</name>
+ <description>MDP.13c : Both sides of the transistor shall be terminated by source.</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>MDP.15</name>
+ <description>MDP.15 : Min DNWELL enclosing MVPSD to any DNWELL spacing. : 6µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>MDP.16a</name>
+ <description>MDP.16a : Min LDPMOS drain COMP width. : 0.22µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>MDP.16b</name>
+ <description>MDP.16b : Min LDPMOS drain COMP enclose contact. : 0µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>MDP.17a</name>
+ <description>MDP.17a : For better latch up immunity, it is necessary to put DNWELL guard ring between MVPSD Inside DNWELL covered by LDMOS_XTOR and NCOMP (outside DNWELL and outside Nwell) when spacing between them is less than 40um.</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>MDP.17c</name>
+ <description>MDP.17c : DNWELL guard ring shall have NCOMP tab to be connected to highest potential</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>Y.NW.2b_3.3V</name>
+ <description>Y.NW.2b_3.3V : Min. Nwell Space (Outside DNWELL, Inside YMTP_MK) [Different potential]. : 1µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>Y.NW.2b_5V</name>
+ <description>Y.NW.2b_5V : Min. Nwell Space (Outside DNWELL, Inside YMTP_MK) [Different potential]. : 1µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>Y.DF.6_5V</name>
+ <description>Y.DF.6_5V : Min. COMP extend beyond gate (it also means source/drain overhang) inside YMTP_MK. : 0.15µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>Y.DF.16_3.3V</name>
+ <description>Y.DF.16_3.3V : Min. space from (Nwell outside DNWELL) to (unrelated NCOMP outside Nwell and DNWELL) (inside YMTP_MK). : 0.27µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>Y.DF.16_5V</name>
+ <description>Y.DF.16_5V : Min. space from (Nwell outside DNWELL) to (unrelated NCOMP outside Nwell and DNWELL) (inside YMTP_MK). : 0.23µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>Y.PL.1_3.3V</name>
+ <description>Y.PL.1_3.3V : Interconnect Width (inside YMTP_MK). : 0.13µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>Y.PL.1_5V</name>
+ <description>Y.PL.1_5V : Interconnect Width (inside YMTP_MK). This rule is currently not applicable for 5V.</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>Y.PL.2_3.3V</name>
+ <description>Y.PL.2_3.3V : Gate Width (Channel Length) (inside YMTP_MK). : 0.13µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>Y.PL.2_5V</name>
+ <description>Y.PL.2_5V : Gate Width (Channel Length) (inside YMTP_MK). : 0.47µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>Y.PL.4_5V</name>
+ <description>Y.PL.4_5V : Poly2 extension beyond COMP to form Poly2 end cap (inside YMTP_MK). : 0.16µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>Y.PL.5a_3.3V</name>
+ <description>Y.PL.5a_3.3V : Space from field Poly2 to unrelated COMP (inside YMTP_MK). Space from field Poly2 to Guard-ring (inside YMTP_MK). : 0.04µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>Y.PL.5a_5V</name>
+ <description>Y.PL.5a_5V : Space from field Poly2 to unrelated COMP (inside YMTP_MK). Space from field Poly2 to Guard-ring (inside YMTP_MK). : 0.2µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>Y.PL.5b_3.3V</name>
+ <description>Y.PL.5b_3.3V : Space from field Poly2 to related COMP (inside YMTP_MK). : 0.04µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>Y.PL.5b_5V</name>
+ <description>Y.PL.5b_5V : Space from field Poly2 to related COMP (inside YMTP_MK). : 0.2µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>S.DF.4c_MV</name>
+ <description>S.DF.4c_MV : Min. (Nwell overlap of PCOMP) outside DNWELL. : 0.45µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>S.DF.6_MV</name>
+ <description>S.DF.6_MV : Min. COMP extend beyond gate (it also means source/drain overhang). : 0.32µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>S.DF.7_MV</name>
+ <description>S.DF.7_MV : Min. (LVPWELL Spacer to PCOMP) inside DNWELL. : 0.45µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>S.DF.8_MV</name>
+ <description>S.DF.8_MV : Min. (LVPWELL overlap of NCOMP) Inside DNWELL. : 0.45µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>S.DF.16_MV</name>
+ <description>S.DF.16_MV : Min. space from (Nwell outside DNWELL) to (NCOMP outside Nwell and DNWELL). : 0.45µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>S.PL.5a_MV</name>
+ <description>S.PL.5a_MV : Space from field Poly2 to unrelated COMP Spacer from field Poly2 to Guard-ring. : 0.12µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>S.PL.5b_MV</name>
+ <description>S.PL.5b_MV : Space from field Poly2 to related COMP. : 0.12µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>S.CO.4_MV</name>
+ <description>S.CO.4_MV : COMP overlap of contact. : 0.04µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>S.DF.4c_LV</name>
+ <description>S.DF.4c_LV : Min. (Nwell overlap of PCOMP) outside DNWELL. : 0.4µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>S.DF.16_LV</name>
+ <description>S.DF.16_LV : Min. space from (Nwell outside DNWELL) to (NCOMP outside Nwell and DNWELL). : 0.4µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>S.CO.3_LV</name>
+ <description>S.CO.3_LV : Poly2 overlap of contact. : 0.04µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>S.CO.4_LV</name>
+ <description>S.CO.4_LV : COMP overlap of contact. : 0.03µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>S.CO.6_ii_LV</name>
+ <description>S.CO.6_ii_LV : (ii) If Metal1 overlaps contact by < 0.04um on one side, adjacent metal1 edges overlap</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>S.M1.1_LV</name>
+ <description>S.M1.1_LV : min. metal1 width : 0.22µm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>comp_OFFGRID</name>
+ <description>OFFGRID : OFFGRID vertex on comp</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>comp_angle</name>
+ <description>ACUTE : non 45 degree angle comp</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>dnwell_OFFGRID</name>
+ <description>OFFGRID : OFFGRID vertex on dnwell</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>dnwell_angle</name>
+ <description>ACUTE : non 45 degree angle dnwell</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>nwell_OFFGRID</name>
+ <description>OFFGRID : OFFGRID vertex on nwell</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>nwell_angle</name>
+ <description>ACUTE : non 45 degree angle nwell</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>lvpwell_OFFGRID</name>
+ <description>OFFGRID : OFFGRID vertex on lvpwell</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>lvpwell_angle</name>
+ <description>ACUTE : non 45 degree angle lvpwell</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>dualgate_OFFGRID</name>
+ <description>OFFGRID : OFFGRID vertex on dualgate</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>dualgate_angle</name>
+ <description>ACUTE : non 45 degree angle dualgate</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>poly2_OFFGRID</name>
+ <description>OFFGRID : OFFGRID vertex on poly2</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>poly2_angle</name>
+ <description>ACUTE : non 45 degree angle poly2</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>nplus_OFFGRID</name>
+ <description>OFFGRID : OFFGRID vertex on nplus</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>nplus_angle</name>
+ <description>ACUTE : non 45 degree angle nplus</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>pplus_OFFGRID</name>
+ <description>OFFGRID : OFFGRID vertex on pplus</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>pplus_angle</name>
+ <description>ACUTE : non 45 degree angle pplus</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>sab_OFFGRID</name>
+ <description>OFFGRID : OFFGRID vertex on sab</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>sab_angle</name>
+ <description>ACUTE : non 45 degree angle sab</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>esd_OFFGRID</name>
+ <description>OFFGRID : OFFGRID vertex on esd</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>esd_angle</name>
+ <description>ACUTE : non 45 degree angle esd</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>contact_OFFGRID</name>
+ <description>OFFGRID : OFFGRID vertex on contact</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>contact_angle</name>
+ <description>ACUTE : non 45 degree angle contact</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>metal1_OFFGRID</name>
+ <description>OFFGRID : OFFGRID vertex on metal1</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>metal1_angle</name>
+ <description>ACUTE : non 45 degree angle metal1</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via1_OFFGRID</name>
+ <description>OFFGRID : OFFGRID vertex on via1</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via1_angle</name>
+ <description>ACUTE : non 45 degree angle via1</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>metal2_OFFGRID</name>
+ <description>OFFGRID : OFFGRID vertex on metal2</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>metal2_angle</name>
+ <description>ACUTE : non 45 degree angle metal2</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via2_OFFGRID</name>
+ <description>OFFGRID : OFFGRID vertex on via2</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via2_angle</name>
+ <description>ACUTE : non 45 degree angle via2</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>metal3_OFFGRID</name>
+ <description>OFFGRID : OFFGRID vertex on metal3</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>metal3_angle</name>
+ <description>ACUTE : non 45 degree angle metal3</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via3_OFFGRID</name>
+ <description>OFFGRID : OFFGRID vertex on via3</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via3_angle</name>
+ <description>ACUTE : non 45 degree angle via3</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>metal4_OFFGRID</name>
+ <description>OFFGRID : OFFGRID vertex on metal4</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>metal4_angle</name>
+ <description>ACUTE : non 45 degree angle metal4</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via4_OFFGRID</name>
+ <description>OFFGRID : OFFGRID vertex on via4</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via4_angle</name>
+ <description>ACUTE : non 45 degree angle via4</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>metal5_OFFGRID</name>
+ <description>OFFGRID : OFFGRID vertex on metal5</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>metal5_angle</name>
+ <description>ACUTE : non 45 degree angle metal5</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via5_OFFGRID</name>
+ <description>OFFGRID : OFFGRID vertex on via5</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via5_angle</name>
+ <description>ACUTE : non 45 degree angle via5</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>metaltop_OFFGRID</name>
+ <description>OFFGRID : OFFGRID vertex on metaltop</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>metaltop_angle</name>
+ <description>ACUTE : non 45 degree angle metaltop</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>pad_OFFGRID</name>
+ <description>OFFGRID : OFFGRID vertex on pad</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>pad_angle</name>
+ <description>ACUTE : non 45 degree angle pad</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>resistor_OFFGRID</name>
+ <description>OFFGRID : OFFGRID vertex on resistor</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>resistor_angle</name>
+ <description>ACUTE : non 45 degree angle resistor</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>fhres_OFFGRID</name>
+ <description>OFFGRID : OFFGRID vertex on fhres</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>fhres_angle</name>
+ <description>ACUTE : non 45 degree angle fhres</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>fusetop_OFFGRID</name>
+ <description>OFFGRID : OFFGRID vertex on fusetop</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>fusetop_angle</name>
+ <description>ACUTE : non 45 degree angle fusetop</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>fusewindow_d_OFFGRID</name>
+ <description>OFFGRID : OFFGRID vertex on fusewindow_d</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>fusewindow_d_angle</name>
+ <description>ACUTE : non 45 degree angle fusewindow_d</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>polyfuse_OFFGRID</name>
+ <description>OFFGRID : OFFGRID vertex on polyfuse</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>polyfuse_angle</name>
+ <description>ACUTE : non 45 degree angle polyfuse</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>mvsd_OFFGRID</name>
+ <description>OFFGRID : OFFGRID vertex on mvsd</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>mvsd_angle</name>
+ <description>ACUTE : non 45 degree angle mvsd</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>mvpsd_OFFGRID</name>
+ <description>OFFGRID : OFFGRID vertex on mvpsd</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>mvpsd_angle</name>
+ <description>ACUTE : non 45 degree angle mvpsd</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>nat_OFFGRID</name>
+ <description>OFFGRID : OFFGRID vertex on nat</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>nat_angle</name>
+ <description>ACUTE : non 45 degree angle nat</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>comp_dummy_OFFGRID</name>
+ <description>OFFGRID : OFFGRID vertex on comp_dummy</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>comp_dummy_angle</name>
+ <description>ACUTE : non 45 degree angle comp_dummy</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>poly2_dummy_OFFGRID</name>
+ <description>OFFGRID : OFFGRID vertex on poly2_dummy</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>poly2_dummy_angle</name>
+ <description>ACUTE : non 45 degree angle poly2_dummy</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>metal1_dummy_OFFGRID</name>
+ <description>OFFGRID : OFFGRID vertex on metal1_dummy</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>metal1_dummy_angle</name>
+ <description>ACUTE : non 45 degree angle metal1_dummy</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>metal2_dummy_OFFGRID</name>
+ <description>OFFGRID : OFFGRID vertex on metal2_dummy</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>metal2_dummy_angle</name>
+ <description>ACUTE : non 45 degree angle metal2_dummy</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>metal3_dummy_OFFGRID</name>
+ <description>OFFGRID : OFFGRID vertex on metal3_dummy</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>metal3_dummy_angle</name>
+ <description>ACUTE : non 45 degree angle metal3_dummy</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>metal4_dummy_OFFGRID</name>
+ <description>OFFGRID : OFFGRID vertex on metal4_dummy</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>metal4_dummy_angle</name>
+ <description>ACUTE : non 45 degree angle metal4_dummy</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>metal5_dummy_OFFGRID</name>
+ <description>OFFGRID : OFFGRID vertex on metal5_dummy</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>metal5_dummy_angle</name>
+ <description>ACUTE : non 45 degree angle metal5_dummy</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>metaltop_dummy_OFFGRID</name>
+ <description>OFFGRID : OFFGRID vertex on metaltop_dummy</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>metaltop_dummy_angle</name>
+ <description>ACUTE : non 45 degree angle metaltop_dummy</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>comp_label_OFFGRID</name>
+ <description>OFFGRID : OFFGRID vertex on comp_label</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>comp_label_angle</name>
+ <description>ACUTE : non 45 degree angle comp_label</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>poly2_label_OFFGRID</name>
+ <description>OFFGRID : OFFGRID vertex on poly2_label</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>poly2_label_angle</name>
+ <description>ACUTE : non 45 degree angle poly2_label</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>metal1_label_OFFGRID</name>
+ <description>OFFGRID : OFFGRID vertex on metal1_label</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>metal1_label_angle</name>
+ <description>ACUTE : non 45 degree angle metal1_label</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>metal2_label_OFFGRID</name>
+ <description>OFFGRID : OFFGRID vertex on metal2_label</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>metal2_label_angle</name>
+ <description>ACUTE : non 45 degree angle metal2_label</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>metal3_label_OFFGRID</name>
+ <description>OFFGRID : OFFGRID vertex on metal3_label</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>metal3_label_angle</name>
+ <description>ACUTE : non 45 degree angle metal3_label</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>metal4_label_OFFGRID</name>
+ <description>OFFGRID : OFFGRID vertex on metal4_label</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>metal4_label_angle</name>
+ <description>ACUTE : non 45 degree angle metal4_label</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>metal5_label_OFFGRID</name>
+ <description>OFFGRID : OFFGRID vertex on metal5_label</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>metal5_label_angle</name>
+ <description>ACUTE : non 45 degree angle metal5_label</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>metaltop_label_OFFGRID</name>
+ <description>OFFGRID : OFFGRID vertex on metaltop_label</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>metaltop_label_angle</name>
+ <description>ACUTE : non 45 degree angle metaltop_label</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>metal1_slot_OFFGRID</name>
+ <description>OFFGRID : OFFGRID vertex on metal1_slot</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>metal1_slot_angle</name>
+ <description>ACUTE : non 45 degree angle metal1_slot</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>metal2_slot_OFFGRID</name>
+ <description>OFFGRID : OFFGRID vertex on metal2_slot</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>metal2_slot_angle</name>
+ <description>ACUTE : non 45 degree angle metal2_slot</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>metal3_slot_OFFGRID</name>
+ <description>OFFGRID : OFFGRID vertex on metal3_slot</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>metal3_slot_angle</name>
+ <description>ACUTE : non 45 degree angle metal3_slot</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>metal4_slot_OFFGRID</name>
+ <description>OFFGRID : OFFGRID vertex on metal4_slot</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>metal4_slot_angle</name>
+ <description>ACUTE : non 45 degree angle metal4_slot</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>metal5_slot_OFFGRID</name>
+ <description>OFFGRID : OFFGRID vertex on metal5_slot</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>metal5_slot_angle</name>
+ <description>ACUTE : non 45 degree angle metal5_slot</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>metaltop_slot_OFFGRID</name>
+ <description>OFFGRID : OFFGRID vertex on metaltop_slot</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>metaltop_slot_angle</name>
+ <description>ACUTE : non 45 degree angle metaltop_slot</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>ubmpperi_OFFGRID</name>
+ <description>OFFGRID : OFFGRID vertex on ubmpperi</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>ubmpperi_angle</name>
+ <description>ACUTE : non 45 degree angle ubmpperi</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>ubmparray_OFFGRID</name>
+ <description>OFFGRID : OFFGRID vertex on ubmparray</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>ubmparray_angle</name>
+ <description>ACUTE : non 45 degree angle ubmparray</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>ubmeplate_OFFGRID</name>
+ <description>OFFGRID : OFFGRID vertex on ubmeplate</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>ubmeplate_angle</name>
+ <description>ACUTE : non 45 degree angle ubmeplate</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>schottky_diode_OFFGRID</name>
+ <description>OFFGRID : OFFGRID vertex on schottky_diode</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>schottky_diode_angle</name>
+ <description>ACUTE : non 45 degree angle schottky_diode</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>zener_OFFGRID</name>
+ <description>OFFGRID : OFFGRID vertex on zener</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>zener_angle</name>
+ <description>ACUTE : non 45 degree angle zener</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>res_mk_OFFGRID</name>
+ <description>OFFGRID : OFFGRID vertex on res_mk</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>res_mk_angle</name>
+ <description>ACUTE : non 45 degree angle res_mk</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>opc_drc_OFFGRID</name>
+ <description>OFFGRID : OFFGRID vertex on opc_drc</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>opc_drc_angle</name>
+ <description>ACUTE : non 45 degree angle opc_drc</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>ndmy_OFFGRID</name>
+ <description>OFFGRID : OFFGRID vertex on ndmy</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>ndmy_angle</name>
+ <description>ACUTE : non 45 degree angle ndmy</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>pmndmy_OFFGRID</name>
+ <description>OFFGRID : OFFGRID vertex on pmndmy</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>pmndmy_angle</name>
+ <description>ACUTE : non 45 degree angle pmndmy</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>v5_xtor_OFFGRID</name>
+ <description>OFFGRID : OFFGRID vertex on v5_xtor</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>v5_xtor_angle</name>
+ <description>ACUTE : non 45 degree angle v5_xtor</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>cap_mk_OFFGRID</name>
+ <description>OFFGRID : OFFGRID vertex on cap_mk</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>cap_mk_angle</name>
+ <description>ACUTE : non 45 degree angle cap_mk</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>mos_cap_mk_OFFGRID</name>
+ <description>OFFGRID : OFFGRID vertex on mos_cap_mk</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>mos_cap_mk_angle</name>
+ <description>ACUTE : non 45 degree angle mos_cap_mk</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>ind_mk_OFFGRID</name>
+ <description>OFFGRID : OFFGRID vertex on ind_mk</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>ind_mk_angle</name>
+ <description>ACUTE : non 45 degree angle ind_mk</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>diode_mk_OFFGRID</name>
+ <description>OFFGRID : OFFGRID vertex on diode_mk</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>diode_mk_angle</name>
+ <description>ACUTE : non 45 degree angle diode_mk</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>drc_bjt_OFFGRID</name>
+ <description>OFFGRID : OFFGRID vertex on drc_bjt</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>drc_bjt_angle</name>
+ <description>ACUTE : non 45 degree angle drc_bjt</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>lvs_bjt_OFFGRID</name>
+ <description>OFFGRID : OFFGRID vertex on lvs_bjt</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>lvs_bjt_angle</name>
+ <description>ACUTE : non 45 degree angle lvs_bjt</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>mim_l_mk_OFFGRID</name>
+ <description>OFFGRID : OFFGRID vertex on mim_l_mk</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>mim_l_mk_angle</name>
+ <description>ACUTE : non 45 degree angle mim_l_mk</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>latchup_mk_OFFGRID</name>
+ <description>OFFGRID : OFFGRID vertex on latchup_mk</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>latchup_mk_angle</name>
+ <description>ACUTE : non 45 degree angle latchup_mk</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>guard_ring_mk_OFFGRID</name>
+ <description>OFFGRID : OFFGRID vertex on guard_ring_mk</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>guard_ring_mk_angle</name>
+ <description>ACUTE : non 45 degree angle guard_ring_mk</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>otp_mk_OFFGRID</name>
+ <description>OFFGRID : OFFGRID vertex on otp_mk</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>otp_mk_angle</name>
+ <description>ACUTE : non 45 degree angle otp_mk</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>mtpmark_OFFGRID</name>
+ <description>OFFGRID : OFFGRID vertex on mtpmark</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>mtpmark_angle</name>
+ <description>ACUTE : non 45 degree angle mtpmark</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>neo_ee_mk_OFFGRID</name>
+ <description>OFFGRID : OFFGRID vertex on neo_ee_mk</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>neo_ee_mk_angle</name>
+ <description>ACUTE : non 45 degree angle neo_ee_mk</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>sramcore_OFFGRID</name>
+ <description>OFFGRID : OFFGRID vertex on sramcore</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>sramcore_angle</name>
+ <description>ACUTE : non 45 degree angle sramcore</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>lvs_rf_OFFGRID</name>
+ <description>OFFGRID : OFFGRID vertex on lvs_rf</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>lvs_rf_angle</name>
+ <description>ACUTE : non 45 degree angle lvs_rf</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>lvs_drain_OFFGRID</name>
+ <description>OFFGRID : OFFGRID vertex on lvs_drain</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>lvs_drain_angle</name>
+ <description>ACUTE : non 45 degree angle lvs_drain</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvpolyrs_OFFGRID</name>
+ <description>OFFGRID : OFFGRID vertex on hvpolyrs</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvpolyrs_angle</name>
+ <description>ACUTE : non 45 degree angle hvpolyrs</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>lvs_io_OFFGRID</name>
+ <description>OFFGRID : OFFGRID vertex on lvs_io</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>lvs_io_angle</name>
+ <description>ACUTE : non 45 degree angle lvs_io</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>probe_mk_OFFGRID</name>
+ <description>OFFGRID : OFFGRID vertex on probe_mk</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>probe_mk_angle</name>
+ <description>ACUTE : non 45 degree angle probe_mk</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>esd_mk_OFFGRID</name>
+ <description>OFFGRID : OFFGRID vertex on esd_mk</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>esd_mk_angle</name>
+ <description>ACUTE : non 45 degree angle esd_mk</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>lvs_source_OFFGRID</name>
+ <description>OFFGRID : OFFGRID vertex on lvs_source</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>lvs_source_angle</name>
+ <description>ACUTE : non 45 degree angle lvs_source</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>well_diode_mk_OFFGRID</name>
+ <description>OFFGRID : OFFGRID vertex on well_diode_mk</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>well_diode_mk_angle</name>
+ <description>ACUTE : non 45 degree angle well_diode_mk</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>ldmos_xtor_OFFGRID</name>
+ <description>OFFGRID : OFFGRID vertex on ldmos_xtor</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>ldmos_xtor_angle</name>
+ <description>ACUTE : non 45 degree angle ldmos_xtor</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>plfuse_OFFGRID</name>
+ <description>OFFGRID : OFFGRID vertex on plfuse</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>plfuse_angle</name>
+ <description>ACUTE : non 45 degree angle plfuse</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>efuse_mk_OFFGRID</name>
+ <description>OFFGRID : OFFGRID vertex on efuse_mk</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>efuse_mk_angle</name>
+ <description>ACUTE : non 45 degree angle efuse_mk</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>mcell_feol_mk_OFFGRID</name>
+ <description>OFFGRID : OFFGRID vertex on mcell_feol_mk</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>mcell_feol_mk_angle</name>
+ <description>ACUTE : non 45 degree angle mcell_feol_mk</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>ymtp_mk_OFFGRID</name>
+ <description>OFFGRID : OFFGRID vertex on ymtp_mk</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>ymtp_mk_angle</name>
+ <description>ACUTE : non 45 degree angle ymtp_mk</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>dev_wf_mk_OFFGRID</name>
+ <description>OFFGRID : OFFGRID vertex on dev_wf_mk</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>dev_wf_mk_angle</name>
+ <description>ACUTE : non 45 degree angle dev_wf_mk</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>metal1_blk_OFFGRID</name>
+ <description>OFFGRID : OFFGRID vertex on metal1_blk</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>metal1_blk_angle</name>
+ <description>ACUTE : non 45 degree angle metal1_blk</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>metal2_blk_OFFGRID</name>
+ <description>OFFGRID : OFFGRID vertex on metal2_blk</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>metal2_blk_angle</name>
+ <description>ACUTE : non 45 degree angle metal2_blk</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>metal3_blk_OFFGRID</name>
+ <description>OFFGRID : OFFGRID vertex on metal3_blk</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>metal3_blk_angle</name>
+ <description>ACUTE : non 45 degree angle metal3_blk</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>metal4_blk_OFFGRID</name>
+ <description>OFFGRID : OFFGRID vertex on metal4_blk</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>metal4_blk_angle</name>
+ <description>ACUTE : non 45 degree angle metal4_blk</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>metal5_blk_OFFGRID</name>
+ <description>OFFGRID : OFFGRID vertex on metal5_blk</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>metal5_blk_angle</name>
+ <description>ACUTE : non 45 degree angle metal5_blk</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>metalt_blk_OFFGRID</name>
+ <description>OFFGRID : OFFGRID vertex on metalt_blk</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>metalt_blk_angle</name>
+ <description>ACUTE : non 45 degree angle metalt_blk</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>pr_bndry_OFFGRID</name>
+ <description>OFFGRID : OFFGRID vertex on pr_bndry</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>pr_bndry_angle</name>
+ <description>ACUTE : non 45 degree angle pr_bndry</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>mdiode_OFFGRID</name>
+ <description>OFFGRID : OFFGRID vertex on mdiode</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>mdiode_angle</name>
+ <description>ACUTE : non 45 degree angle mdiode</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>metal1_res_OFFGRID</name>
+ <description>OFFGRID : OFFGRID vertex on metal1_res</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>metal1_res_angle</name>
+ <description>ACUTE : non 45 degree angle metal1_res</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>metal2_res_OFFGRID</name>
+ <description>OFFGRID : OFFGRID vertex on metal2_res</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>metal2_res_angle</name>
+ <description>ACUTE : non 45 degree angle metal2_res</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>metal3_res_OFFGRID</name>
+ <description>OFFGRID : OFFGRID vertex on metal3_res</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>metal3_res_angle</name>
+ <description>ACUTE : non 45 degree angle metal3_res</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>metal4_res_OFFGRID</name>
+ <description>OFFGRID : OFFGRID vertex on metal4_res</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>metal4_res_angle</name>
+ <description>ACUTE : non 45 degree angle metal4_res</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>metal5_res_OFFGRID</name>
+ <description>OFFGRID : OFFGRID vertex on metal5_res</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>metal5_res_angle</name>
+ <description>ACUTE : non 45 degree angle metal5_res</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>metal6_res_OFFGRID</name>
+ <description>OFFGRID : OFFGRID vertex on metal6_res</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>metal6_res_angle</name>
+ <description>ACUTE : non 45 degree angle metal6_res</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>border_OFFGRID</name>
+ <description>OFFGRID : OFFGRID vertex on border</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>border_angle</name>
+ <description>ACUTE : non 45 degree angle border</description>
+ <categories>
+ </categories>
+ </category>
+ </categories>
+ <cells>
+ <cell>
+ <name>user_project_wrapper</name>
+ <variant/>
+ <references>
+ </references>
+ </cell>
+ </cells>
+ <items>
+ </items>
+</report-database>
diff --git a/mpw_precheck/outputs/user_project_wrapper.xor.gds b/mpw_precheck/outputs/user_project_wrapper.xor.gds
new file mode 100644
index 0000000..68fe441
--- /dev/null
+++ b/mpw_precheck/outputs/user_project_wrapper.xor.gds
Binary files differ
diff --git a/mpw_precheck/outputs/user_project_wrapper_empty_erased.gds b/mpw_precheck/outputs/user_project_wrapper_empty_erased.gds
new file mode 100644
index 0000000..156b6a7
--- /dev/null
+++ b/mpw_precheck/outputs/user_project_wrapper_empty_erased.gds
Binary files differ
diff --git a/mpw_precheck/outputs/user_project_wrapper_erased.gds b/mpw_precheck/outputs/user_project_wrapper_erased.gds
new file mode 100644
index 0000000..563f325
--- /dev/null
+++ b/mpw_precheck/outputs/user_project_wrapper_erased.gds
Binary files differ
diff --git a/signoff/.gitignore b/signoff/.gitignore
new file mode 100644
index 0000000..6407046
--- /dev/null
+++ b/signoff/.gitignore
@@ -0,0 +1 @@
+cdrcpost/*
diff --git a/signoff/assigned_slot b/signoff/assigned_slot
new file mode 100644
index 0000000..cadb715
--- /dev/null
+++ b/signoff/assigned_slot
@@ -0,0 +1 @@
+030
diff --git a/tapeout/logs/gds.info b/tapeout/logs/gds.info
new file mode 100644
index 0000000..69c1d7e
--- /dev/null
+++ b/tapeout/logs/gds.info
@@ -0,0 +1 @@
+user_project_wrapper.gds: a5b78e1dee205485a829ba28cdd3753d8636ecf7
\ No newline at end of file
diff --git a/tapeout/logs/gen_gpio_defaults.log b/tapeout/logs/gen_gpio_defaults.log
new file mode 100644
index 0000000..6d24557
--- /dev/null
+++ b/tapeout/logs/gen_gpio_defaults.log
@@ -0,0 +1,79 @@
+Step 1: Create new cells for new GPIO default vectors.
+Creating new layout file /root/project/mag/gpio_defaults_block_009.mag
+Creating new gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_009.v
+Layout file /root/project/mag/gpio_defaults_block_009.mag already exists and does not need to be generated.
+Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_009.v already exists and does not need to be generated.
+Creating new layout file /root/project/mag/gpio_defaults_block_007.mag
+Creating new gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_007.v
+Creating new layout file /root/project/mag/gpio_defaults_block_087.mag
+Creating new gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_087.v
+Layout file /root/project/mag/gpio_defaults_block_007.mag already exists and does not need to be generated.
+Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_007.v already exists and does not need to be generated.
+Creating new layout file /root/project/mag/gpio_defaults_block_008.mag
+Creating new gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_008.v
+Layout file /root/project/mag/gpio_defaults_block_008.mag already exists and does not need to be generated.
+Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_008.v already exists and does not need to be generated.
+Layout file /root/project/mag/gpio_defaults_block_008.mag already exists and does not need to be generated.
+Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_008.v already exists and does not need to be generated.
+Layout file /root/project/mag/gpio_defaults_block_008.mag already exists and does not need to be generated.
+Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_008.v already exists and does not need to be generated.
+Layout file /root/project/mag/gpio_defaults_block_008.mag already exists and does not need to be generated.
+Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_008.v already exists and does not need to be generated.
+Layout file /root/project/mag/gpio_defaults_block_008.mag already exists and does not need to be generated.
+Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_008.v already exists and does not need to be generated.
+Layout file /root/project/mag/gpio_defaults_block_008.mag already exists and does not need to be generated.
+Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_008.v already exists and does not need to be generated.
+Layout file /root/project/mag/gpio_defaults_block_008.mag already exists and does not need to be generated.
+Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_008.v already exists and does not need to be generated.
+Layout file /root/project/mag/gpio_defaults_block_008.mag already exists and does not need to be generated.
+Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_008.v already exists and does not need to be generated.
+Layout file /root/project/mag/gpio_defaults_block_008.mag already exists and does not need to be generated.
+Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_008.v already exists and does not need to be generated.
+Layout file /root/project/mag/gpio_defaults_block_008.mag already exists and does not need to be generated.
+Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_008.v already exists and does not need to be generated.
+Layout file /root/project/mag/gpio_defaults_block_008.mag already exists and does not need to be generated.
+Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_008.v already exists and does not need to be generated.
+Layout file /root/project/mag/gpio_defaults_block_008.mag already exists and does not need to be generated.
+Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_008.v already exists and does not need to be generated.
+Layout file /root/project/mag/gpio_defaults_block_008.mag already exists and does not need to be generated.
+Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_008.v already exists and does not need to be generated.
+Layout file /root/project/mag/gpio_defaults_block_008.mag already exists and does not need to be generated.
+Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_008.v already exists and does not need to be generated.
+Layout file /root/project/mag/gpio_defaults_block_008.mag already exists and does not need to be generated.
+Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_008.v already exists and does not need to be generated.
+Layout file /root/project/mag/gpio_defaults_block_008.mag already exists and does not need to be generated.
+Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_008.v already exists and does not need to be generated.
+Layout file /root/project/mag/gpio_defaults_block_008.mag already exists and does not need to be generated.
+Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_008.v already exists and does not need to be generated.
+Layout file /root/project/mag/gpio_defaults_block_008.mag already exists and does not need to be generated.
+Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_008.v already exists and does not need to be generated.
+Layout file /root/project/mag/gpio_defaults_block_008.mag already exists and does not need to be generated.
+Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_008.v already exists and does not need to be generated.
+Layout file /root/project/mag/gpio_defaults_block_008.mag already exists and does not need to be generated.
+Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_008.v already exists and does not need to be generated.
+Layout file /root/project/mag/gpio_defaults_block_008.mag already exists and does not need to be generated.
+Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_008.v already exists and does not need to be generated.
+Layout file /root/project/mag/gpio_defaults_block_008.mag already exists and does not need to be generated.
+Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_008.v already exists and does not need to be generated.
+Layout file /root/project/mag/gpio_defaults_block_008.mag already exists and does not need to be generated.
+Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_008.v already exists and does not need to be generated.
+Layout file /root/project/mag/gpio_defaults_block_008.mag already exists and does not need to be generated.
+Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_008.v already exists and does not need to be generated.
+Layout file /root/project/mag/gpio_defaults_block_008.mag already exists and does not need to be generated.
+Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_008.v already exists and does not need to be generated.
+Layout file /root/project/mag/gpio_defaults_block_008.mag already exists and does not need to be generated.
+Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_008.v already exists and does not need to be generated.
+Layout file /root/project/mag/gpio_defaults_block_008.mag already exists and does not need to be generated.
+Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_008.v already exists and does not need to be generated.
+Layout file /root/project/mag/gpio_defaults_block_008.mag already exists and does not need to be generated.
+Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_008.v already exists and does not need to be generated.
+Layout file /root/project/mag/gpio_defaults_block_008.mag already exists and does not need to be generated.
+Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_008.v already exists and does not need to be generated.
+Layout file /root/project/mag/gpio_defaults_block_008.mag already exists and does not need to be generated.
+Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_008.v already exists and does not need to be generated.
+Layout file /root/project/mag/gpio_defaults_block_008.mag already exists and does not need to be generated.
+Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_008.v already exists and does not need to be generated.
+Layout file /root/project/mag/gpio_defaults_block_008.mag already exists and does not need to be generated.
+Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_008.v already exists and does not need to be generated.
+Step 2: Modify top-level layouts to use the specified defaults.
+Done.
diff --git a/tapeout/logs/git.info b/tapeout/logs/git.info
new file mode 100644
index 0000000..f72366f
--- /dev/null
+++ b/tapeout/logs/git.info
@@ -0,0 +1,3 @@
+Repository: https://github.com/egorxe/ophelia_fpga_openmpw.git
+Branch: HEAD
+Commit: 4b407974710e71322cb6270d812c2b44b3e13cbb
\ No newline at end of file
diff --git a/tapeout/logs/git_clone.log b/tapeout/logs/git_clone.log
new file mode 100644
index 0000000..482e0ac
--- /dev/null
+++ b/tapeout/logs/git_clone.log
@@ -0,0 +1,20 @@
+https://github.com/egorxe/ophelia_fpga_openmpw.git
+Cloning into '/root/project'...
+Note: switching to '4b407974710e71322cb6270d812c2b44b3e13cbb'.
+
+You are in 'detached HEAD' state. You can look around, make experimental
+changes and commit them, and you can discard any commits you make in this
+state without impacting any branches by switching back to a branch.
+
+If you want to create a new branch to retain commits you create, you may
+do so (now or later) by using -c with the switch command. Example:
+
+ git switch -c <new-branch-name>
+
+Or undo this operation with:
+
+ git switch -
+
+Turn off this advice by setting config variable advice.detachedHead to false
+
+HEAD is now at 4b40797 Fixed errors found during gatelevel simulation. Updated GDS.
diff --git a/tapeout/logs/klayout_gds2oas.log b/tapeout/logs/klayout_gds2oas.log
new file mode 100644
index 0000000..e1c0a11
--- /dev/null
+++ b/tapeout/logs/klayout_gds2oas.log
@@ -0,0 +1 @@
+[INFO] Changing from /mnt/uffs/user/u9789_egorxe/design/ophelia_efpga/jobs/tapeout/fafaa606-1d8b-46f1-9a02-ae2e7c5d65af/outputs/caravel_180045d6.gds to /mnt/uffs/user/u9789_egorxe/design/ophelia_efpga/jobs/tapeout/fafaa606-1d8b-46f1-9a02-ae2e7c5d65af/outputs/caravel_180045d6.oas
diff --git a/tapeout/logs/oasis.info b/tapeout/logs/oasis.info
new file mode 100644
index 0000000..bf31d69
--- /dev/null
+++ b/tapeout/logs/oasis.info
@@ -0,0 +1 @@
+caravel_180045d6.oas: 14fae5065a2b3811334a4421d8409651f25474c7
\ No newline at end of file
diff --git a/tapeout/logs/pdks.info b/tapeout/logs/pdks.info
new file mode 100644
index 0000000..daefa55
--- /dev/null
+++ b/tapeout/logs/pdks.info
@@ -0,0 +1,2 @@
+Open PDKs: b8c6129fb60851c452a3136c2b8c603bb92cb180
+gf180mcuC PDK: a897aa30369d3bcec87d9d50ce9b01f320f854ef
\ No newline at end of file
diff --git a/tapeout/logs/set_user_id.log b/tapeout/logs/set_user_id.log
new file mode 100644
index 0000000..0ddf675
--- /dev/null
+++ b/tapeout/logs/set_user_id.log
@@ -0,0 +1,10 @@
+Project Chip ID is: 402671062
+Setting Project Chip ID to: 180045d6
+Step 1: Modify Layout of the user_id_programming subcell
+Done!
+Step 2: Add user project ID parameter to source verilog.
+Done!
+Step 3: Add user project ID parameter to gate-level verilog.
+Done!
+Step 4: Add user project ID text to top level layout.
+Done!
diff --git a/tapeout/logs/ship_truck.log b/tapeout/logs/ship_truck.log
new file mode 100644
index 0000000..1d37374
--- /dev/null
+++ b/tapeout/logs/ship_truck.log
@@ -0,0 +1,3783 @@
+
+Magic 8.3 revision 348 - Compiled on Mon Dec 12 01:04:33 UTC 2022.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+Processing system .magicrc file
+Sourcing design .magicrc for technology gf180mcuC ...
+10 Magic internal units = 1 Lambda
+Input style import: scaleFactor=10, multiplier=2
+The following types are not handled by extraction and will be treated as non-electrical types:
+ obsactive mvobsactive filldiff fillpoly m1hole obsm1 fillm1 obsv1 m2hole obsm2 fillm2 obsv2 m3hole obsm3 fillm3 m4hole obsm4 fillm4 m5hole obsm5 fillm5 glass fillblock lvstext obscomment
+Scaled tech values by 10 / 1 to match internal grid scaling
+Loading gf180mcuC Device Generator Menu ...
+Loading "/opt/scripts/mag2gds_gf180.tcl" from command line.
+Scaled magic input cell user_project_wrapper geometry by factor of 2
+user_project_wrapper: 10000 rects
+user_project_wrapper: 20000 rects
+user_project_wrapper: 30000 rects
+user_project_wrapper: 40000 rects
+user_project_wrapper: 50000 rects
+user_project_wrapper: 60000 rects
+user_project_wrapper: 70000 rects
+user_project_wrapper: 80000 rects
+user_project_wrapper: 90000 rects
+user_project_wrapper: 100000 rects
+user_project_wrapper: 110000 rects
+user_project_wrapper: 120000 rects
+user_project_wrapper: 130000 rects
+caravel_core: 10000 rects
+caravel_core: 20000 rects
+caravel_core: 30000 rects
+caravel_core: 40000 rects
+caravel_core: 50000 rects
+caravel_core: 60000 rects
+caravel_core: 70000 rects
+caravel_core: 80000 rects
+caravel_core: 90000 rects
+caravel_core: 100000 rects
+caravel_core: 110000 rects
+caravel_core: 120000 rects
+caravel_core: 130000 rects
+caravel_core: 140000 rects
+caravel_core: 150000 rects
+caravel_core: 160000 rects
+caravel_core: 170000 rects
+caravel_core: 180000 rects
+caravel_core: 190000 rects
+caravel_core: 200000 rects
+caravel_core: 210000 rects
+caravel_core: 220000 rects
+caravel_core: 230000 rects
+caravel_core: 240000 rects
+caravel_core: 250000 rects
+caravel_core: 260000 rects
+caravel_core: 270000 rects
+caravel_core: 280000 rects
+caravel_core: 290000 rects
+caravel_core: 300000 rects
+caravel_core: 310000 rects
+caravel_core: 320000 rects
+caravel_core: 330000 rects
+caravel_core: 340000 rects
+caravel_core: 350000 rects
+caravel_core: 360000 rects
+caravel_core: 370000 rects
+caravel_core: 380000 rects
+caravel_core: 390000 rects
+caravel_core: 400000 rects
+caravel_core: 410000 rects
+caravel_core: 420000 rects
+caravel_core: 430000 rects
+caravel_core: 440000 rects
+caravel_core: 450000 rects
+caravel_core: 460000 rects
+caravel_core: 470000 rects
+caravel_core: 480000 rects
+caravel_core: 490000 rects
+caravel_core: 500000 rects
+caravel_core: 510000 rects
+caravel_core: 520000 rects
+caravel_core: 530000 rects
+caravel_core: 540000 rects
+caravel_core: 550000 rects
+caravel_core: 560000 rects
+caravel_core: 570000 rects
+caravel_core: 580000 rects
+caravel_core: 590000 rects
+caravel_core: 600000 rects
+caravel_core: 610000 rects
+caravel_core: 620000 rects
+caravel_core: 630000 rects
+caravel_core: 640000 rects
+caravel_core: 650000 rects
+caravel_core: 660000 rects
+caravel_core: 670000 rects
+caravel_core: 680000 rects
+caravel_core: 690000 rects
+caravel_core: 700000 rects
+caravel_core: 710000 rects
+caravel_core: 720000 rects
+caravel_core: 730000 rects
+caravel_core: 740000 rects
+caravel_core: 750000 rects
+caravel_core: 760000 rects
+caravel_core: 770000 rects
+caravel_core: 780000 rects
+caravel_core: 790000 rects
+caravel_core: 800000 rects
+caravel_core: 810000 rects
+caravel_core: 820000 rects
+caravel_core: 830000 rects
+caravel_core: 840000 rects
+caravel_core: 850000 rects
+caravel_core: 860000 rects
+caravel_core: 870000 rects
+caravel_core: 880000 rects
+caravel_core: 890000 rects
+caravel_core: 900000 rects
+caravel_core: 910000 rects
+caravel_core: 920000 rects
+caravel_core: 930000 rects
+caravel_core: 940000 rects
+caravel_core: 950000 rects
+caravel_core: 960000 rects
+caravel_core: 970000 rects
+caravel_core: 980000 rects
+caravel_core: 990000 rects
+caravel_core: 1000000 rects
+caravel_core: 1010000 rects
+caravel_core: 1020000 rects
+caravel_core: 1030000 rects
+caravel_core: 1040000 rects
+caravel_core: 1050000 rects
+caravel_core: 1060000 rects
+caravel_core: 1070000 rects
+caravel_core: 1080000 rects
+caravel_core: 1090000 rects
+caravel_core: 1100000 rects
+caravel_core: 1110000 rects
+caravel_core: 1120000 rects
+caravel_core: 1130000 rects
+caravel_core: 1140000 rects
+caravel_core: 1150000 rects
+caravel_core: 1160000 rects
+caravel_core: 1170000 rects
+caravel_core: 1180000 rects
+caravel_core: 1190000 rects
+caravel_core: 1200000 rects
+caravel_core: 1210000 rects
+caravel_core: 1220000 rects
+caravel_core: 1230000 rects
+caravel_core: 1240000 rects
+caravel_core: 1250000 rects
+caravel_core: 1260000 rects
+caravel_core: 1270000 rects
+caravel_core: 1280000 rects
+caravel_core: 1290000 rects
+caravel_core: 1300000 rects
+caravel_core: 1310000 rects
+caravel_core: 1320000 rects
+caravel_core: 1330000 rects
+caravel_core: 1340000 rects
+caravel_core: 1350000 rects
+caravel_core: 1360000 rects
+caravel_core: 1370000 rects
+caravel_core: 1380000 rects
+caravel_core: 1390000 rects
+caravel_core: 1400000 rects
+caravel_core: 1410000 rects
+caravel_core: 1420000 rects
+caravel_core: 1430000 rects
+caravel_core: 1440000 rects
+caravel_core: 1450000 rects
+caravel_core: 1460000 rects
+caravel_core: 1470000 rects
+caravel_core: 1480000 rects
+caravel_core: 1490000 rects
+caravel_core: 1500000 rects
+caravel_core: 1510000 rects
+caravel_core: 1520000 rects
+caravel_core: 1530000 rects
+caravel_core: 1540000 rects
+caravel_core: 1550000 rects
+caravel_core: 1560000 rects
+caravel_core: 1570000 rects
+caravel_core: 1580000 rects
+caravel_core: 1590000 rects
+caravel_core: 1600000 rects
+caravel_core: 1610000 rects
+caravel_core: 1620000 rects
+caravel_core: 1630000 rects
+caravel_core: 1640000 rects
+caravel_core: 1650000 rects
+caravel_core: 1660000 rects
+caravel_core: 1670000 rects
+caravel_core: 1680000 rects
+caravel_core: 1690000 rects
+caravel_core: 1700000 rects
+caravel_core: 1710000 rects
+caravel_core: 1720000 rects
+caravel_core: 1730000 rects
+caravel_core: 1740000 rects
+caravel_core: 1750000 rects
+caravel_core: 1760000 rects
+caravel_core: 1770000 rects
+caravel_core: 1780000 rects
+caravel_core: 1790000 rects
+caravel_core: 1800000 rects
+caravel_core: 1810000 rects
+caravel_core: 1820000 rects
+caravel_core: 1830000 rects
+caravel_core: 1840000 rects
+caravel_core: 1850000 rects
+caravel_core: 1860000 rects
+caravel_core: 1870000 rects
+caravel_core: 1880000 rects
+caravel_core: 1890000 rects
+caravel_core: 1900000 rects
+caravel_core: 1910000 rects
+caravel_core: 1920000 rects
+caravel_core: 1930000 rects
+caravel_core: 1940000 rects
+caravel_core: 1950000 rects
+caravel_core: 1960000 rects
+caravel_core: 1970000 rects
+caravel_core: 1980000 rects
+caravel_core: 1990000 rects
+caravel_core: 2000000 rects
+caravel_core: 2010000 rects
+caravel_core: 2020000 rects
+caravel_core: 2030000 rects
+caravel_core: 2040000 rects
+caravel_core: 2050000 rects
+caravel_core: 2060000 rects
+caravel_core: 2070000 rects
+caravel_core: 2080000 rects
+caravel_core: 2090000 rects
+caravel_core: 2100000 rects
+caravel_core: 2110000 rects
+caravel_core: 2120000 rects
+caravel_core: 2130000 rects
+caravel_core: 2140000 rects
+caravel_core: 2150000 rects
+caravel_core: 2160000 rects
+caravel_core: 2170000 rects
+caravel_core: 2180000 rects
+caravel_core: 2190000 rects
+caravel_core: 2200000 rects
+caravel_core: 2210000 rects
+caravel_core: 2220000 rects
+caravel_core: 2230000 rects
+caravel_core: 2240000 rects
+caravel_core: 2250000 rects
+caravel_core: 2260000 rects
+Duplicate cell in caravel_core: Instance of cell user_project_wrapper is from path /root/project/mag but cell was previously read from the current directory.
+New path does not exist and will be ignored.
+Duplicate cell in caravel_core: Instance of cell simple_por is from path /root/project/mag but cell was previously read from /opt/caravel/macros/simple_por/maglef.
+New path does not exist and will be ignored.
+Processing timestamp mismatches: user_id_programmingWarning: Parent cell lists instance of "spare_logic_block" at bad file path /root/project/mag/spare_logic_block.mag.
+The cell exists in the search paths at spare_logic_block.mag.
+The discovered version will be used.
+, spare_logic_blockWarning: Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__tiel" at bad file path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__tiel.mag.
+The cell exists in the search paths at /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__tiel.mag.
+The discovered version will be used.
+, gf180mcu_fd_sc_mcu7t5v0__tielWarning: Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__tieh" at bad file path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__tieh.mag.
+The cell exists in the search paths at /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__tieh.mag.
+The discovered version will be used.
+, gf180mcu_fd_sc_mcu7t5v0__tiehWarning: Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__filltie" at bad file path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__filltie.mag.
+The cell exists in the search paths at /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__filltie.mag.
+The discovered version will be used.
+, gf180mcu_fd_sc_mcu7t5v0__filltieWarning: Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__endcap" at bad file path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__endcap.mag.
+The cell exists in the search paths at /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__endcap.mag.
+The discovered version will be used.
+, gf180mcu_fd_sc_mcu7t5v0__endcapWarning: Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__fillcap_4" at bad file path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__fillcap_4.mag.
+The cell exists in the search paths at /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__fillcap_4.mag.
+The discovered version will be used.
+, gf180mcu_fd_sc_mcu7t5v0__fillcap_4Warning: Parent cell lists instance of "gf180_ram_512x8_wrapper" at bad file path /root/project/mag/gf180_ram_512x8_wrapper.mag.
+The cell exists in the search paths at /opt/caravel/mgmt_core_wrapper/mag/gf180_ram_512x8_wrapper.mag.
+The discovered version will be used.
+gf180_ram_512x8_wrapper: 10000 rects
+, gf180_ram_512x8_wrapper, simple_por, user_project_wrapperWarning: Parent cell lists instance of "housekeeping" at bad file path /root/project/mag/housekeeping.mag.
+The cell exists in the search paths at housekeeping.mag.
+The discovered version will be used.
+housekeeping: 10000 rects
+housekeeping: 20000 rects
+housekeeping: 30000 rects
+housekeeping: 40000 rects
+housekeeping: 50000 rects
+housekeeping: 60000 rects
+housekeeping: 70000 rects
+housekeeping: 80000 rects
+housekeeping: 90000 rects
+housekeeping: 100000 rects
+housekeeping: 110000 rects
+housekeeping: 120000 rects
+housekeeping: 130000 rects
+housekeeping: 140000 rects
+housekeeping: 150000 rects
+housekeeping: 160000 rects
+housekeeping: 170000 rects
+housekeeping: 180000 rects
+housekeeping: 190000 rects
+housekeeping: 200000 rects
+housekeeping: 210000 rects
+housekeeping: 220000 rects
+housekeeping: 230000 rects
+housekeeping: 240000 rects
+housekeeping: 250000 rects
+housekeeping: 260000 rects
+housekeeping: 270000 rects
+housekeeping: 280000 rects
+housekeeping: 290000 rects
+housekeeping: 300000 rects
+housekeeping: 310000 rects
+housekeeping: 320000 rects
+housekeeping: 330000 rects
+housekeeping: 340000 rects
+housekeeping: 350000 rects
+Duplicate cell in housekeeping: Instance of cell gf180mcu_fd_sc_mcu7t5v0__fillcap_4 is from path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag but cell was previously read from /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag.
+New path does not exist and will be ignored.
+Duplicate cell in housekeeping: Instance of cell gf180mcu_fd_sc_mcu7t5v0__endcap is from path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag but cell was previously read from /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag.
+New path does not exist and will be ignored.
+Duplicate cell in housekeeping: Instance of cell gf180mcu_fd_sc_mcu7t5v0__filltie is from path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag but cell was previously read from /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag.
+New path does not exist and will be ignored.
+Duplicate cell in housekeeping: Instance of cell gf180mcu_fd_sc_mcu7t5v0__tieh is from path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag but cell was previously read from /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag.
+New path does not exist and will be ignored.
+, housekeepingWarning: Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__buf_4" at bad file path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__buf_4.mag.
+The cell exists in the search paths at /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__buf_4.mag.
+The discovered version will be used.
+, gf180mcu_fd_sc_mcu7t5v0__buf_4Warning: Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__clkbuf_1" at bad file path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__clkbuf_1.mag.
+The cell exists in the search paths at /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__clkbuf_1.mag.
+The discovered version will be used.
+, gf180mcu_fd_sc_mcu7t5v0__clkbuf_1Warning: Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__clkinv_1" at bad file path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__clkinv_1.mag.
+The cell exists in the search paths at /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__clkinv_1.mag.
+The discovered version will be used.
+, gf180mcu_fd_sc_mcu7t5v0__clkinv_1Warning: Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__clkbuf_4" at bad file path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__clkbuf_4.mag.
+The cell exists in the search paths at /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__clkbuf_4.mag.
+The discovered version will be used.
+, gf180mcu_fd_sc_mcu7t5v0__clkbuf_4Warning: Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__clkbuf_2" at bad file path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__clkbuf_2.mag.
+The cell exists in the search paths at /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__clkbuf_2.mag.
+The discovered version will be used.
+, gf180mcu_fd_sc_mcu7t5v0__clkbuf_2Warning: Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__clkbuf_3" at bad file path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__clkbuf_3.mag.
+The cell exists in the search paths at /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__clkbuf_3.mag.
+The discovered version will be used.
+, gf180mcu_fd_sc_mcu7t5v0__clkbuf_3Warning: Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__dlyb_4" at bad file path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__dlyb_4.mag.
+The cell exists in the search paths at /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__dlyb_4.mag.
+The discovered version will be used.
+, gf180mcu_fd_sc_mcu7t5v0__dlyb_4Warning: Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__clkbuf_8" at bad file path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__clkbuf_8.mag.
+The cell exists in the search paths at /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__clkbuf_8.mag.
+The discovered version will be used.
+, gf180mcu_fd_sc_mcu7t5v0__clkbuf_8Warning: Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__buf_8" at bad file path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__buf_8.mag.
+The cell exists in the search paths at /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__buf_8.mag.
+The discovered version will be used.
+, gf180mcu_fd_sc_mcu7t5v0__buf_8Warning: Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__clkbuf_12" at bad file path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__clkbuf_12.mag.
+The cell exists in the search paths at /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__clkbuf_12.mag.
+The discovered version will be used.
+, gf180mcu_fd_sc_mcu7t5v0__clkbuf_12Warning: Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__dffrnq_4" at bad file path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__dffrnq_4.mag.
+The cell exists in the search paths at /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__dffrnq_4.mag.
+The discovered version will be used.
+, gf180mcu_fd_sc_mcu7t5v0__dffrnq_4Warning: Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__dffrnq_2" at bad file path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__dffrnq_2.mag.
+The cell exists in the search paths at /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__dffrnq_2.mag.
+The discovered version will be used.
+, gf180mcu_fd_sc_mcu7t5v0__dffrnq_2Warning: Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__dffrnq_1" at bad file path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__dffrnq_1.mag.
+The cell exists in the search paths at /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__dffrnq_1.mag.
+The discovered version will be used.
+, gf180mcu_fd_sc_mcu7t5v0__dffrnq_1Warning: Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__dffnsnq_1" at bad file path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__dffnsnq_1.mag.
+The cell exists in the search paths at /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__dffnsnq_1.mag.
+The discovered version will be used.
+, gf180mcu_fd_sc_mcu7t5v0__dffnsnq_1Warning: Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__dffnrnq_1" at bad file path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__dffnrnq_1.mag.
+The cell exists in the search paths at /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__dffnrnq_1.mag.
+The discovered version will be used.
+, gf180mcu_fd_sc_mcu7t5v0__dffnrnq_1Warning: Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__dffq_1" at bad file path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__dffq_1.mag.
+The cell exists in the search paths at /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__dffq_1.mag.
+The discovered version will be used.
+, gf180mcu_fd_sc_mcu7t5v0__dffq_1Warning: Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__dffsnq_1" at bad file path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__dffsnq_1.mag.
+The cell exists in the search paths at /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__dffsnq_1.mag.
+The discovered version will be used.
+, gf180mcu_fd_sc_mcu7t5v0__dffsnq_1Warning: Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__dffsnq_4" at bad file path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__dffsnq_4.mag.
+The cell exists in the search paths at /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__dffsnq_4.mag.
+The discovered version will be used.
+, gf180mcu_fd_sc_mcu7t5v0__dffsnq_4Warning: Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__dffsnq_2" at bad file path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__dffsnq_2.mag.
+The cell exists in the search paths at /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__dffsnq_2.mag.
+The discovered version will be used.
+, gf180mcu_fd_sc_mcu7t5v0__dffsnq_2Warning: Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__and2_4" at bad file path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__and2_4.mag.
+The cell exists in the search paths at /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__and2_4.mag.
+The discovered version will be used.
+, gf180mcu_fd_sc_mcu7t5v0__and2_4Warning: Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__mux2_2" at bad file path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__mux2_2.mag.
+The cell exists in the search paths at /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__mux2_2.mag.
+The discovered version will be used.
+, gf180mcu_fd_sc_mcu7t5v0__mux2_2Warning: Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__nor2_2" at bad file path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__nor2_2.mag.
+The cell exists in the search paths at /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__nor2_2.mag.
+The discovered version will be used.
+, gf180mcu_fd_sc_mcu7t5v0__nor2_2Warning: Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__oai21_4" at bad file path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__oai21_4.mag.
+The cell exists in the search paths at /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__oai21_4.mag.
+The discovered version will be used.
+, gf180mcu_fd_sc_mcu7t5v0__oai21_4Warning: Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__aoi222_4" at bad file path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__aoi222_4.mag.
+The cell exists in the search paths at /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__aoi222_4.mag.
+The discovered version will be used.
+, gf180mcu_fd_sc_mcu7t5v0__aoi222_4Warning: Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__nand2_4" at bad file path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__nand2_4.mag.
+The cell exists in the search paths at /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__nand2_4.mag.
+The discovered version will be used.
+, gf180mcu_fd_sc_mcu7t5v0__nand2_4Warning: Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__aoi221_4" at bad file path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__aoi221_4.mag.
+The cell exists in the search paths at /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__aoi221_4.mag.
+The discovered version will be used.
+, gf180mcu_fd_sc_mcu7t5v0__aoi221_4Warning: Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__aoi22_4" at bad file path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__aoi22_4.mag.
+The cell exists in the search paths at /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__aoi22_4.mag.
+The discovered version will be used.
+, gf180mcu_fd_sc_mcu7t5v0__aoi22_4Warning: Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__aoi21_4" at bad file path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__aoi21_4.mag.
+The cell exists in the search paths at /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__aoi21_4.mag.
+The discovered version will be used.
+, gf180mcu_fd_sc_mcu7t5v0__aoi21_4Warning: Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__and3_4" at bad file path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__and3_4.mag.
+The cell exists in the search paths at /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__and3_4.mag.
+The discovered version will be used.
+, gf180mcu_fd_sc_mcu7t5v0__and3_4Warning: Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__oai32_4" at bad file path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__oai32_4.mag.
+The cell exists in the search paths at /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__oai32_4.mag.
+The discovered version will be used.
+, gf180mcu_fd_sc_mcu7t5v0__oai32_4Warning: Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__nand3_4" at bad file path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__nand3_4.mag.
+The cell exists in the search paths at /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__nand3_4.mag.
+The discovered version will be used.
+, gf180mcu_fd_sc_mcu7t5v0__nand3_4Warning: Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__nor2_4" at bad file path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__nor2_4.mag.
+The cell exists in the search paths at /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__nor2_4.mag.
+The discovered version will be used.
+, gf180mcu_fd_sc_mcu7t5v0__nor2_4Warning: Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__oai211_4" at bad file path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__oai211_4.mag.
+The cell exists in the search paths at /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__oai211_4.mag.
+The discovered version will be used.
+, gf180mcu_fd_sc_mcu7t5v0__oai211_4Warning: Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__oai31_4" at bad file path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__oai31_4.mag.
+The cell exists in the search paths at /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__oai31_4.mag.
+The discovered version will be used.
+, gf180mcu_fd_sc_mcu7t5v0__oai31_4Warning: Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__or2_4" at bad file path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__or2_4.mag.
+The cell exists in the search paths at /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__or2_4.mag.
+The discovered version will be used.
+, gf180mcu_fd_sc_mcu7t5v0__or2_4Warning: Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__oai22_4" at bad file path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__oai22_4.mag.
+The cell exists in the search paths at /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__oai22_4.mag.
+The discovered version will be used.
+, gf180mcu_fd_sc_mcu7t5v0__oai22_4Warning: Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__xor2_1" at bad file path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__xor2_1.mag.
+The cell exists in the search paths at /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__xor2_1.mag.
+The discovered version will be used.
+, gf180mcu_fd_sc_mcu7t5v0__xor2_1Warning: Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__aoi211_4" at bad file path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__aoi211_4.mag.
+The cell exists in the search paths at /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__aoi211_4.mag.
+The discovered version will be used.
+, gf180mcu_fd_sc_mcu7t5v0__aoi211_4Warning: Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__oai221_4" at bad file path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__oai221_4.mag.
+The cell exists in the search paths at /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__oai221_4.mag.
+The discovered version will be used.
+, gf180mcu_fd_sc_mcu7t5v0__oai221_4Warning: Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__clkinv_2" at bad file path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__clkinv_2.mag.
+The cell exists in the search paths at /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__clkinv_2.mag.
+The discovered version will be used.
+, gf180mcu_fd_sc_mcu7t5v0__clkinv_2Warning: Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__inv_1" at bad file path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__inv_1.mag.
+The cell exists in the search paths at /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__inv_1.mag.
+The discovered version will be used.
+, gf180mcu_fd_sc_mcu7t5v0__inv_1Warning: Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__oai222_4" at bad file path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__oai222_4.mag.
+The cell exists in the search paths at /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__oai222_4.mag.
+The discovered version will be used.
+, gf180mcu_fd_sc_mcu7t5v0__oai222_4Warning: Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__mux2_4" at bad file path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__mux2_4.mag.
+The cell exists in the search paths at /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__mux2_4.mag.
+The discovered version will be used.
+, gf180mcu_fd_sc_mcu7t5v0__mux2_4Warning: Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__inv_2" at bad file path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__inv_2.mag.
+The cell exists in the search paths at /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__inv_2.mag.
+The discovered version will be used.
+, gf180mcu_fd_sc_mcu7t5v0__inv_2Warning: Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__xor2_4" at bad file path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__xor2_4.mag.
+The cell exists in the search paths at /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__xor2_4.mag.
+The discovered version will be used.
+, gf180mcu_fd_sc_mcu7t5v0__xor2_4Warning: Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__xor2_2" at bad file path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__xor2_2.mag.
+The cell exists in the search paths at /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__xor2_2.mag.
+The discovered version will be used.
+, gf180mcu_fd_sc_mcu7t5v0__xor2_2Warning: Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__xnor2_2" at bad file path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__xnor2_2.mag.
+The cell exists in the search paths at /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__xnor2_2.mag.
+The discovered version will be used.
+, gf180mcu_fd_sc_mcu7t5v0__xnor2_2Warning: Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__inv_4" at bad file path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__inv_4.mag.
+The cell exists in the search paths at /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__inv_4.mag.
+The discovered version will be used.
+, gf180mcu_fd_sc_mcu7t5v0__inv_4Warning: Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__xnor2_1" at bad file path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__xnor2_1.mag.
+The cell exists in the search paths at /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__xnor2_1.mag.
+The discovered version will be used.
+, gf180mcu_fd_sc_mcu7t5v0__xnor2_1Warning: Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__clkinv_4" at bad file path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__clkinv_4.mag.
+The cell exists in the search paths at /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__clkinv_4.mag.
+The discovered version will be used.
+, gf180mcu_fd_sc_mcu7t5v0__clkinv_4Warning: Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__clkinv_3" at bad file path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__clkinv_3.mag.
+The cell exists in the search paths at /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__clkinv_3.mag.
+The discovered version will be used.
+, gf180mcu_fd_sc_mcu7t5v0__clkinv_3Warning: Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__clkinv_8" at bad file path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__clkinv_8.mag.
+The cell exists in the search paths at /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__clkinv_8.mag.
+The discovered version will be used.
+, gf180mcu_fd_sc_mcu7t5v0__clkinv_8Warning: Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__inv_3" at bad file path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__inv_3.mag.
+The cell exists in the search paths at /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__inv_3.mag.
+The discovered version will be used.
+, gf180mcu_fd_sc_mcu7t5v0__inv_3Warning: Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__fill_2" at bad file path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__fill_2.mag.
+The cell exists in the search paths at /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__fill_2.mag.
+The discovered version will be used.
+Scaled magic input cell gf180mcu_fd_sc_mcu7t5v0__fill_2 geometry by factor of 2
+, gf180mcu_fd_sc_mcu7t5v0__fill_2Warning: Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__fill_1" at bad file path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__fill_1.mag.
+The cell exists in the search paths at /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__fill_1.mag.
+The discovered version will be used.
+Scaled magic input cell gf180mcu_fd_sc_mcu7t5v0__fill_1 geometry by factor of 2
+, gf180mcu_fd_sc_mcu7t5v0__fill_1Warning: Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__fillcap_8" at bad file path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__fillcap_8.mag.
+The cell exists in the search paths at /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__fillcap_8.mag.
+The discovered version will be used.
+, gf180mcu_fd_sc_mcu7t5v0__fillcap_8Warning: Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__fillcap_16" at bad file path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__fillcap_16.mag.
+The cell exists in the search paths at /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__fillcap_16.mag.
+The discovered version will be used.
+, gf180mcu_fd_sc_mcu7t5v0__fillcap_16Warning: Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__fillcap_32" at bad file path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__fillcap_32.mag.
+The cell exists in the search paths at /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__fillcap_32.mag.
+The discovered version will be used.
+, gf180mcu_fd_sc_mcu7t5v0__fillcap_32Warning: Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__fillcap_64" at bad file path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__fillcap_64.mag.
+The cell exists in the search paths at /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__fillcap_64.mag.
+The discovered version will be used.
+, gf180mcu_fd_sc_mcu7t5v0__fillcap_64Warning: Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__antenna" at bad file path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__antenna.mag.
+The cell exists in the search paths at /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag/gf180mcu_fd_sc_mcu7t5v0__antenna.mag.
+The discovered version will be used.
+, gf180mcu_fd_sc_mcu7t5v0__antennaDuplicate cell in gpio_defaults_block_008: Instance of cell gf180mcu_fd_sc_mcu7t5v0__endcap is from path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag but cell was previously read from /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag.
+New path does not exist and will be ignored.
+Duplicate cell in gpio_defaults_block_008: Instance of cell gf180mcu_fd_sc_mcu7t5v0__fillcap_4 is from path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag but cell was previously read from /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag.
+New path does not exist and will be ignored.
+Duplicate cell in gpio_defaults_block_008: Instance of cell gf180mcu_fd_sc_mcu7t5v0__filltie is from path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag but cell was previously read from /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag.
+New path does not exist and will be ignored.
+Duplicate cell in gpio_defaults_block_008: Instance of cell gf180mcu_fd_sc_mcu7t5v0__tieh is from path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag but cell was previously read from /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag.
+New path does not exist and will be ignored.
+Duplicate cell in gpio_defaults_block_008: Instance of cell gf180mcu_fd_sc_mcu7t5v0__tiel is from path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag but cell was previously read from /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag.
+New path does not exist and will be ignored.
+, gpio_defaults_block_008Duplicate cell in gpio_defaults_block_007: Instance of cell gf180mcu_fd_sc_mcu7t5v0__endcap is from path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag but cell was previously read from /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag.
+New path does not exist and will be ignored.
+Duplicate cell in gpio_defaults_block_007: Instance of cell gf180mcu_fd_sc_mcu7t5v0__fillcap_4 is from path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag but cell was previously read from /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag.
+New path does not exist and will be ignored.
+Duplicate cell in gpio_defaults_block_007: Instance of cell gf180mcu_fd_sc_mcu7t5v0__filltie is from path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag but cell was previously read from /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag.
+New path does not exist and will be ignored.
+Duplicate cell in gpio_defaults_block_007: Instance of cell gf180mcu_fd_sc_mcu7t5v0__tieh is from path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag but cell was previously read from /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag.
+New path does not exist and will be ignored.
+Duplicate cell in gpio_defaults_block_007: Instance of cell gf180mcu_fd_sc_mcu7t5v0__tiel is from path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag but cell was previously read from /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag.
+New path does not exist and will be ignored.
+, gpio_defaults_block_007Duplicate cell in gpio_defaults_block_087: Instance of cell gf180mcu_fd_sc_mcu7t5v0__endcap is from path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag but cell was previously read from /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag.
+New path does not exist and will be ignored.
+Duplicate cell in gpio_defaults_block_087: Instance of cell gf180mcu_fd_sc_mcu7t5v0__fillcap_4 is from path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag but cell was previously read from /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag.
+New path does not exist and will be ignored.
+Duplicate cell in gpio_defaults_block_087: Instance of cell gf180mcu_fd_sc_mcu7t5v0__filltie is from path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag but cell was previously read from /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag.
+New path does not exist and will be ignored.
+Duplicate cell in gpio_defaults_block_087: Instance of cell gf180mcu_fd_sc_mcu7t5v0__tieh is from path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag but cell was previously read from /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag.
+New path does not exist and will be ignored.
+Duplicate cell in gpio_defaults_block_087: Instance of cell gf180mcu_fd_sc_mcu7t5v0__tiel is from path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag but cell was previously read from /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag.
+New path does not exist and will be ignored.
+, gpio_defaults_block_087Duplicate cell in gpio_defaults_block_009: Instance of cell gf180mcu_fd_sc_mcu7t5v0__endcap is from path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag but cell was previously read from /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag.
+New path does not exist and will be ignored.
+Duplicate cell in gpio_defaults_block_009: Instance of cell gf180mcu_fd_sc_mcu7t5v0__fillcap_4 is from path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag but cell was previously read from /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag.
+New path does not exist and will be ignored.
+Duplicate cell in gpio_defaults_block_009: Instance of cell gf180mcu_fd_sc_mcu7t5v0__filltie is from path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag but cell was previously read from /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag.
+New path does not exist and will be ignored.
+Duplicate cell in gpio_defaults_block_009: Instance of cell gf180mcu_fd_sc_mcu7t5v0__tieh is from path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag but cell was previously read from /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag.
+New path does not exist and will be ignored.
+Duplicate cell in gpio_defaults_block_009: Instance of cell gf180mcu_fd_sc_mcu7t5v0__tiel is from path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag but cell was previously read from /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag.
+New path does not exist and will be ignored.
+, gpio_defaults_block_009Warning: Parent cell lists instance of "mprj_io_buffer" at bad file path /root/project/mag/mprj_io_buffer.mag.
+The cell exists in the search paths at mprj_io_buffer.mag.
+The discovered version will be used.
+Duplicate cell in mprj_io_buffer: Instance of cell gf180mcu_fd_sc_mcu7t5v0__antenna is from path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag but cell was previously read from /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag.
+New path does not exist and will be ignored.
+Duplicate cell in mprj_io_buffer: Instance of cell gf180mcu_fd_sc_mcu7t5v0__clkbuf_8 is from path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag but cell was previously read from /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag.
+New path does not exist and will be ignored.
+Duplicate cell in mprj_io_buffer: Instance of cell gf180mcu_fd_sc_mcu7t5v0__fill_2 is from path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag but cell was previously read from /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag.
+New path does not exist and will be ignored.
+Duplicate cell in mprj_io_buffer: Instance of cell gf180mcu_fd_sc_mcu7t5v0__fill_1 is from path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag but cell was previously read from /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag.
+New path does not exist and will be ignored.
+Duplicate cell in mprj_io_buffer: Instance of cell gf180mcu_fd_sc_mcu7t5v0__fillcap_8 is from path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag but cell was previously read from /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag.
+New path does not exist and will be ignored.
+Duplicate cell in mprj_io_buffer: Instance of cell gf180mcu_fd_sc_mcu7t5v0__fillcap_4 is from path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag but cell was previously read from /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag.
+New path does not exist and will be ignored.
+Duplicate cell in mprj_io_buffer: Instance of cell gf180mcu_fd_sc_mcu7t5v0__fillcap_16 is from path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag but cell was previously read from /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag.
+New path does not exist and will be ignored.
+Duplicate cell in mprj_io_buffer: Instance of cell gf180mcu_fd_sc_mcu7t5v0__fillcap_32 is from path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag but cell was previously read from /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag.
+New path does not exist and will be ignored.
+Duplicate cell in mprj_io_buffer: Instance of cell gf180mcu_fd_sc_mcu7t5v0__endcap is from path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag but cell was previously read from /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag.
+New path does not exist and will be ignored.
+Duplicate cell in mprj_io_buffer: Instance of cell gf180mcu_fd_sc_mcu7t5v0__filltie is from path /opt/pdks/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag but cell was previously read from /opt/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag.
+New path does not exist and will be ignored.
+, mprj_io_buffer.
+Processing timestamp mismatches: user_id_textblock, chip_io, open_source, copyright_block, caravel_corecaravel_power_routing: 10000 rects
+caravel_power_routing: 20000 rects
+caravel_power_routing: 30000 rects
+caravel_power_routing: 40000 rects
+caravel_power_routing: 50000 rects
+caravel_power_routing: 60000 rects
+caravel_power_routing: 70000 rects
+caravel_power_routing: 80000 rects
+caravel_power_routing: 90000 rects
+caravel_power_routing: 100000 rects
+caravel_power_routing: 110000 rects
+, caravel_power_routingScaled magic input cell caravel_motto geometry by factor of 2
+, caravel_motto, caravel_logo.
+Scaled magic input cell font_73 geometry by factor of 2
+Scaled magic input cell font_69 geometry by factor of 2
+Scaled magic input cell font_68 geometry by factor of 2
+Scaled magic input cell font_67 geometry by factor of 2
+Scaled magic input cell font_65 geometry by factor of 2
+Scaled magic input cell font_61 geometry by factor of 2
+Scaled magic input cell font_54 geometry by factor of 2
+Scaled magic input cell font_53 geometry by factor of 2
+Scaled magic input cell font_49 geometry by factor of 2
+Scaled magic input cell font_43 geometry by factor of 2
+Scaled magic input cell font_22 geometry by factor of 2
+Scaled magic input cell font_6E geometry by factor of 2
+Scaled magic input cell font_6C geometry by factor of 2
+gf180mcu_fd_ip_sram__sram512x8m8wm1: 10000 rects
+gf180mcu_fd_ip_sram__sram512x8m8wm1: 20000 rects
+Scaled magic input cell pmos_5p043105913020110_512x8m81 geometry by factor of 10
+Scaled magic input cell pmos_5p043105913020105_512x8m81 geometry by factor of 10
+Scaled magic input cell pmos_5p043105913020103_512x8m81 geometry by factor of 10
+Scaled magic input cell pmos_5p043105913020104_512x8m81 geometry by factor of 10
+Scaled magic input cell pmos_5p043105913020108_512x8m81 geometry by factor of 10
+Scaled magic input cell nmos_5p043105913020109_512x8m81 geometry by factor of 10
+Scaled magic input cell nmos_5p043105913020107_512x8m81 geometry by factor of 10
+Scaled magic input cell nmos_5p043105913020106_512x8m81 geometry by factor of 10
+Scaled magic input cell nmos_5p04310591302044_512x8m81 geometry by factor of 10
+Scaled magic input cell M3_M2$$204401708_512x8m81 geometry by factor of 10
+Scaled magic input cell M3_M2$$204400684_512x8m81 geometry by factor of 10
+Scaled magic input cell M3_M2$$204399660_512x8m81 geometry by factor of 10
+Scaled magic input cell M3_M2$$204398636_512x8m81 geometry by factor of 10
+Scaled magic input cell M3_M2$$204147756_512x8m81 geometry by factor of 10
+Scaled magic input cell M3_M2$$201252908_512x8m81 geometry by factor of 10
+Scaled magic input cell M3_M2$$201251884_512x8m81 geometry by factor of 10
+Scaled magic input cell M2_M1$02_R270_512x8m81 geometry by factor of 10
+Scaled magic input cell M2_M1$$204408876_512x8m81 geometry by factor of 10
+Scaled magic input cell M2_M1$$204407852_512x8m81 geometry by factor of 10
+Scaled magic input cell M2_M1$$204406828_512x8m81 geometry by factor of 10
+Scaled magic input cell M2_M1$$204405804_512x8m81 geometry by factor of 10
+Scaled magic input cell M2_M1$$204404780_512x8m81 geometry by factor of 10
+Scaled magic input cell M2_M1$$204403756_512x8m81 geometry by factor of 10
+Scaled magic input cell M2_M1$$204402732_512x8m81 geometry by factor of 10
+Scaled magic input cell M2_M1$$202406956_512x8m81 geometry by factor of 10
+Scaled magic input cell M2_M1$$202394668_512x8m81 geometry by factor of 10
+Scaled magic input cell M2_M1$$201262124_512x8m81 geometry by factor of 10
+Scaled magic input cell M2_M1$$46894124_512x8m81 geometry by factor of 10
+Scaled magic input cell M2_M1$$45004844_512x8m81 geometry by factor of 10
+Scaled magic input cell M1_PSUB_05_512x8m81 geometry by factor of 10
+Scaled magic input cell M1_PSUB$$45111340_512x8m81 geometry by factor of 10
+Scaled magic input cell M1_POLY243105913020105_512x8m81 geometry by factor of 10
+Scaled magic input cell M1_POLY24310591302033_512x8m81 geometry by factor of 10
+Scaled magic input cell M1_POLY24310591302031_512x8m81 geometry by factor of 10
+Scaled magic input cell M1_POLY24310591302019_512x8m81 geometry by factor of 10
+Scaled magic input cell M1_PACTIVE43105913020106_51_0 geometry by factor of 10
+Scaled magic input cell M1_PACTIVE03_512x8m81 geometry by factor of 10
+Scaled magic input cell M1_NWELL4310591302032_512x8m81 geometry by factor of 10
+Scaled magic input cell M1_NWELL07_512x8m81 geometry by factor of 10
+Scaled magic input cell M3_M2$01_R270_512x8m81 geometry by factor of 10
+Scaled magic input cell M2_M1$04_R270_512x8m81 geometry by factor of 10
+Scaled magic input cell M1_POLY2_01_R270_512x8m81 geometry by factor of 10
+Scaled magic input cell M1_PACTIVE_R270_512x8m81 geometry by factor of 10
+Scaled magic input cell M1_NACTIVE_01_R270_512x8m81 geometry by factor of 10
+Scaled magic input cell pmos_5p043105913020101_512x8m81 geometry by factor of 10
+Scaled magic input cell pmos_5p043105913020100_512x8m81 geometry by factor of 10
+Scaled magic input cell nmos_5p043105913020111_512x8m81 geometry by factor of 10
+Scaled magic input cell nmos_5p04310591302099_512x8m81 geometry by factor of 10
+Scaled magic input cell nmos_5p043105913020102_512x8m81 geometry by factor of 10
+Scaled magic input cell M3_M2$$204146732_512x8m81 geometry by factor of 10
+Scaled magic input cell M3_M2$$204145708_512x8m81 geometry by factor of 10
+Scaled magic input cell M3_M2$$204144684_512x8m81 geometry by factor of 10
+Scaled magic input cell M3_M2$$204143660_512x8m81 geometry by factor of 10
+Scaled magic input cell M3_M2$$204142636_512x8m81 geometry by factor of 10
+Scaled magic input cell M2_M1$$204222508_512x8m81 geometry by factor of 10
+Scaled magic input cell M2_M1$$204221484_512x8m81 geometry by factor of 10
+Scaled magic input cell M2_M1$$204220460_512x8m81 geometry by factor of 10
+Scaled magic input cell M2_M1$$204141612_512x8m81 geometry by factor of 10
+Scaled magic input cell M2_M1$$204140588_512x8m81 geometry by factor of 10
+Scaled magic input cell M2_M1$$204139564_512x8m81 geometry by factor of 10
+Scaled magic input cell M2_M1$$204138540_512x8m81 geometry by factor of 10
+Scaled magic input cell M1_POLY2$$204150828_512x8m81 geometry by factor of 10
+Scaled magic input cell M1_PACTIVE$11_512x8m81 geometry by factor of 10
+Scaled magic input cell M1_PACTIVE$10_512x8m81 geometry by factor of 10
+Scaled magic input cell M1_NWELL_01_512x8m81 geometry by factor of 10
+Scaled magic input cell M1_NACTIVE_02_512x8m81 geometry by factor of 10
+Scaled magic input cell pmos_5p04310591302043_512x8m81 geometry by factor of 10
+Scaled magic input cell pmos_5p04310591302041_512x8m81 geometry by factor of 10
+Scaled magic input cell pmos_5p04310591302035_512x8m81 geometry by factor of 10
+Scaled magic input cell pmos_5p04310591302020_512x8m81 geometry by factor of 10
+Scaled magic input cell pmos_5p04310591302014_512x8m81 geometry by factor of 10
+Scaled magic input cell nmos_5p04310591302042_512x8m81 geometry by factor of 10
+Scaled magic input cell nmos_5p04310591302040_512x8m81 geometry by factor of 10
+Scaled magic input cell nmos_5p04310591302039_512x8m81 geometry by factor of 10
+Scaled magic input cell nmos_5p04310591302010_512x8m81 geometry by factor of 10
+Scaled magic input cell nmos_5p0431059130208_512x8m81 geometry by factor of 10
+Scaled magic input cell M3_M24310591302036_512x8m81 geometry by factor of 10
+Scaled magic input cell M3_M2$$202397740_512x8m81 geometry by factor of 10
+Scaled magic input cell M2_M14310591302035_512x8m81 geometry by factor of 10
+Scaled magic input cell M2_M1$$202396716_512x8m81 geometry by factor of 10
+Scaled magic input cell M2_M1$$202395692_512x8m81 geometry by factor of 10
+Scaled magic input cell M1_PACTIVE4310591302027_512x8m81 geometry by factor of 10
+Scaled magic input cell M1_NACTIVE_01_512x8m81 geometry by factor of 10
+Scaled magic input cell M1_NACTIVE4310591302037_512x8m81 geometry by factor of 10
+Scaled magic input cell via2_x2_512x8m81 geometry by factor of 10
+Scaled magic input cell via2_512x8m81 geometry by factor of 10
+Scaled magic input cell via1_x2_R90_512x8m81 geometry by factor of 10
+Scaled magic input cell via1_x2_512x8m81 geometry by factor of 10
+Scaled magic input cell via2_x2_R90_512x8m81 geometry by factor of 10
+Scaled magic input cell via1_x2_R270_512x8m81 geometry by factor of 10
+Scaled magic input cell via1_R90_512x8m81 geometry by factor of 10
+Scaled magic input cell po_m1_512x8m81 geometry by factor of 10
+Scaled magic input cell pmos_5p04310591302038_512x8m81 geometry by factor of 10
+Scaled magic input cell pmos_5p04310591302027_512x8m81 geometry by factor of 10
+Scaled magic input cell pmos_5p04310591302031_512x8m81 geometry by factor of 10
+Scaled magic input cell pmos_5p04310591302013_512x8m81 geometry by factor of 10
+Scaled magic input cell pmos_5p04310591302022_512x8m81 geometry by factor of 10
+Scaled magic input cell pmos_5p04310591302024_512x8m81 geometry by factor of 10
+Scaled magic input cell pmos_5p04310591302025_512x8m81 geometry by factor of 10
+Scaled magic input cell pmos_5p04310591302030_512x8m81 geometry by factor of 10
+Scaled magic input cell nmos_5p04310591302034_512x8m81 geometry by factor of 10
+Scaled magic input cell nmos_5p04310591302033_512x8m81 geometry by factor of 10
+Scaled magic input cell nmos_5p04310591302032_512x8m81 geometry by factor of 10
+Scaled magic input cell nmos_5p04310591302028_512x8m81 geometry by factor of 10
+Scaled magic input cell nmos_5p04310591302023_512x8m81 geometry by factor of 10
+Scaled magic input cell nmos_5p04310591302012_512x8m81 geometry by factor of 10
+Scaled magic input cell nmos_5p04310591302037_512x8m81 geometry by factor of 10
+Scaled magic input cell nmos_5p04310591302026_512x8m81 geometry by factor of 10
+Scaled magic input cell nmos_5p04310591302036_512x8m81 geometry by factor of 10
+Scaled magic input cell nmos_5p04310591302029_512x8m81 geometry by factor of 10
+Scaled magic input cell M3_M2$$45008940_512x8m81 geometry by factor of 10
+Scaled magic input cell M3_M2$$45006892_512x8m81 geometry by factor of 10
+Scaled magic input cell M3_M2$$45005868_512x8m81 geometry by factor of 10
+Scaled magic input cell M2_M1c$$203396140_512x8m81 geometry by factor of 10
+Scaled magic input cell M2_M1$$45003820_512x8m81 geometry by factor of 10
+Scaled magic input cell M2_M1$$45002796_512x8m81 geometry by factor of 10
+Scaled magic input cell M2_M1$$43374636_512x8m81 geometry by factor of 10
+Scaled magic input cell M1_PSUB_285_512x8m81 geometry by factor of 10
+Scaled magic input cell M1_PSUB$$44997676_512x8m81 geometry by factor of 10
+Scaled magic input cell M1_POLY2$$45109292_512x8m81 geometry by factor of 10
+Scaled magic input cell M1_POLY2$$44754988_512x8m81 geometry by factor of 10
+Scaled magic input cell M1_POLY2$$44753964_512x8m81 geometry by factor of 10
+Scaled magic input cell M1_PACTIVE4310591302034_512x8m81 geometry by factor of 10
+Scaled magic input cell M1_NWELL04_512x8m81 geometry by factor of 10
+Scaled magic input cell M1_NWELL03_512x8m81 geometry by factor of 10
+Scaled magic input cell M1_NWELL02_512x8m81 geometry by factor of 10
+Scaled magic input cell via1_R270_512x8m81 geometry by factor of 10
+Scaled magic input cell via1_512x8m81 geometry by factor of 10
+Scaled magic input cell via2_x2_R270_512x8m81 geometry by factor of 10
+Scaled magic input cell pmos_5p04310591302019_512x8m81 geometry by factor of 10
+Scaled magic input cell pmos_5p04310591302021_512x8m81 geometry by factor of 10
+Scaled magic input cell pmos_5p04310591302018_512x8m81 geometry by factor of 10
+Scaled magic input cell nmos_5p04310591302015_512x8m81 geometry by factor of 10
+Scaled magic input cell nmos_5p04310591302016_512x8m81 geometry by factor of 10
+Scaled magic input cell nmos_5p04310591302017_512x8m81 geometry by factor of 10
+Scaled magic input cell M3_M2$$43371564_512x8m81 geometry by factor of 10
+Scaled magic input cell M1_PSUB_04_R90_512x8m81 geometry by factor of 10
+Scaled magic input cell M1_PSUB$$46558252_512x8m81 geometry by factor of 10
+Scaled magic input cell M1_PSUB$$46557228_512x8m81 geometry by factor of 10
+Scaled magic input cell M1_PSUB$$46556204_512x8m81 geometry by factor of 10
+Scaled magic input cell M1_PSUB$$46555180_512x8m81 geometry by factor of 10
+Scaled magic input cell M1_NWELL_01_R90_512x8m81 geometry by factor of 10
+Scaled magic input cell M1_NWELL06_512x8m81 geometry by factor of 10
+Scaled magic input cell pmos_5p04310591302051_512x8m81 geometry by factor of 10
+Scaled magic input cell pmos_5p04310591302049_512x8m81 geometry by factor of 10
+Scaled magic input cell pmos_5p04310591302048_512x8m81 geometry by factor of 10
+Scaled magic input cell pmos_5p04310591302047_512x8m81 geometry by factor of 10
+Scaled magic input cell pmos_5p0431059130203_512x8m81 geometry by factor of 10
+Scaled magic input cell nmos_5p04310591302052_512x8m81 geometry by factor of 10
+Scaled magic input cell nmos_5p04310591302050_512x8m81 geometry by factor of 10
+Scaled magic input cell nmos_5p04310591302046_512x8m81 geometry by factor of 10
+Scaled magic input cell nmos_5p04310591302045_512x8m81 geometry by factor of 10
+Scaled magic input cell M3_M2431059130207_512x8m81 geometry by factor of 10
+Scaled magic input cell M2_M1431059130200_512x8m81 geometry by factor of 10
+Scaled magic input cell M2_M1$$168351788_R90_512x8m81 geometry by factor of 10
+Scaled magic input cell M1_PSUB_02_512x8m81 geometry by factor of 10
+Scaled magic input cell M1_PACTIVE4310591302040_512x8m81 geometry by factor of 10
+Scaled magic input cell M1_PACTIVE4310591302039_512x8m81 geometry by factor of 10
+Scaled magic input cell M1_NWELL_01_R270_512x8m81 geometry by factor of 10
+Scaled magic input cell M1_NACTIVE4310591302041_512x8m81 geometry by factor of 10
+Scaled magic input cell M1_NACTIVE4310591302038_512x8m81 geometry by factor of 10
+mux821_512x8m81: 10000 rects
+Scaled magic input cell via2_R90_512x8m81 geometry by factor of 10
+Scaled magic input cell pmos_5p0431059130201_512x8m81 geometry by factor of 10
+Scaled magic input cell nmos_5p0431059130202_512x8m81 geometry by factor of 10
+Scaled magic input cell nmos_5p0431059130200_512x8m81 geometry by factor of 10
+Scaled magic input cell M3_M2431059130201_512x8m81 geometry by factor of 10
+Scaled magic input cell M2_M14310591302020_512x8m81 geometry by factor of 10
+Scaled magic input cell M2_M1431059130208_512x8m81 geometry by factor of 10
+Scaled magic input cell M1_PSUB$$47122476_512x8m81 geometry by factor of 10
+Scaled magic input cell M1_POLY24310591302030_512x8m81 geometry by factor of 10
+Scaled magic input cell M1_NWELL09_512x8m81 geometry by factor of 10
+Scaled magic input cell M1_NWELL05_512x8m81 geometry by factor of 10
+Scaled magic input cell M3_M24310591302029_512x8m81 geometry by factor of 10
+Scaled magic input cell M2_M14310591302018_512x8m81 geometry by factor of 10
+Scaled magic input cell M1_NACTIVE4310591302028_512x8m81 geometry by factor of 10
+Scaled magic input cell po_m1_R270_512x8m81 geometry by factor of 10
+Scaled magic input cell po_m1_R90_512x8m81 geometry by factor of 10
+Scaled magic input cell pmos_5p0431059130209_512x8m81 geometry by factor of 10
+Scaled magic input cell pmos_5p0431059130206_512x8m81 geometry by factor of 10
+Scaled magic input cell pmos_5p0431059130204_512x8m81 geometry by factor of 10
+Scaled magic input cell nmos_5p04310591302011_512x8m81 geometry by factor of 10
+Scaled magic input cell nmos_5p0431059130207_512x8m81 geometry by factor of 10
+Scaled magic input cell nmos_5p0431059130205_512x8m81 geometry by factor of 10
+Scaled magic input cell M3_M2$$46895148_512x8m81 geometry by factor of 10
+Scaled magic input cell M3_M2$$43368492_R90_512x8m81 geometry by factor of 10
+Scaled magic input cell M2_M1$$43375660_R90_512x8m81 geometry by factor of 10
+Scaled magic input cell M1_PSUB$$46893100_512x8m81 geometry by factor of 10
+Scaled magic input cell M1_PSUB$$46892076_512x8m81 geometry by factor of 10
+Scaled magic input cell M1_NWELL08_512x8m81 geometry by factor of 10
+Scaled magic input cell M3_M24310591302026_512x8m81 geometry by factor of 10
+Scaled magic input cell M3_M2$$44741676_512x8m81 geometry by factor of 10
+Scaled magic input cell M3_M2$$43370540_512x8m81 geometry by factor of 10
+Scaled magic input cell M2_M14310591302025_512x8m81 geometry by factor of 10
+Scaled magic input cell M2_M1$$45013036_512x8m81 geometry by factor of 10
+Scaled magic input cell M2_M1$$45012012_512x8m81 geometry by factor of 10
+Scaled magic input cell M1_NACTIVE4310591302024_512x8m81 geometry by factor of 10
+Scaled magic input cell via2_R90_512x8m81_0 geometry by factor of 10
+Scaled magic input cell via1_x2_R90_512x8m81_0 geometry by factor of 10
+Scaled magic input cell via1_R270_512x8m81_0 geometry by factor of 10
+Scaled magic input cell via1_R90_512x8m81_0 geometry by factor of 10
+Scaled magic input cell M3_M2$$43368492_512x8m81_0 geometry by factor of 10
+Scaled magic input cell M2_M1$$46894124_512x8m81_0 geometry by factor of 10
+Scaled magic input cell M1_PSUB$$45111340_512x8m81_0 geometry by factor of 10
+Scaled magic input cell M1_PACTIVE4310591302075_512x8m81 geometry by factor of 10
+Scaled magic input cell M1_NWELL$$47121452_512x8m81 geometry by factor of 10
+Scaled magic input cell M1_NWELL$$46277676_512x8m81 geometry by factor of 10
+Scaled magic input cell via2_x2_R270_512x8m81_0 geometry by factor of 10
+Scaled magic input cell via1_x2_R270_512x8m81_0 geometry by factor of 10
+Scaled magic input cell via2_x2_R90_512x8m81_0 geometry by factor of 10
+Scaled magic input cell pmos_5p04310591302097_512x8m81 geometry by factor of 10
+Scaled magic input cell pmos_5p04310591302095_512x8m81 geometry by factor of 10
+Scaled magic input cell nmos_5p04310591302098_512x8m81 geometry by factor of 10
+Scaled magic input cell nmos_5p04310591302096_512x8m81 geometry by factor of 10
+Scaled magic input cell M2_M1$$47117356_512x8m81 geometry by factor of 10
+Scaled magic input cell M2_M1$$43375660_512x8m81 geometry by factor of 10
+Scaled magic input cell M1_PSUB$$46274604_512x8m81 geometry by factor of 10
+Scaled magic input cell M1_POLY2$$46559276_512x8m81_0 geometry by factor of 10
+Scaled magic input cell M1_NWELL$$44998700_512x8m81 geometry by factor of 10
+Scaled magic input cell M3_M24310591302021_512x8m81 geometry by factor of 10
+Scaled magic input cell 018SRAM_cell1_2x_512x8m81 geometry by factor of 2
+Scaled magic input cell 018SRAM_strap1_2x_512x8m81 geometry by factor of 2
+Scaled magic input cell M3_M24310591302023_512x8m81 geometry by factor of 10
+Scaled magic input cell M3_M24310591302022_512x8m81 geometry by factor of 10
+Scaled magic input cell M3_M2$$201416748_512x8m81 geometry by factor of 10
+Scaled magic input cell M3_M243105913020102_512x8m81 geometry by factor of 10
+Scaled magic input cell M3_M24310591302095_512x8m81 geometry by factor of 10
+Scaled magic input cell M2_M14310591302097_512x8m81 geometry by factor of 10
+Scaled magic input cell M3_M243105913020101_512x8m81 geometry by factor of 10
+Scaled magic input cell M3_M243105913020100_512x8m81 geometry by factor of 10
+Scaled magic input cell M3_M24310591302099_512x8m81 geometry by factor of 10
+Scaled magic input cell M3_M24310591302098_512x8m81 geometry by factor of 10
+Scaled magic input cell M3_M24310591302096_512x8m81 geometry by factor of 10
+Scaled magic input cell M3_M24310591302094_512x8m81 geometry by factor of 10
+Scaled magic input cell M3_M24310591302091_512x8m81 geometry by factor of 10
+Scaled magic input cell M3_M24310591302090_512x8m81 geometry by factor of 10
+Scaled magic input cell M3_M24310591302089_512x8m81 geometry by factor of 10
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+Scaled magic input cell M2_M1_CDNS_40661953145772 geometry by factor of 10
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+GF_NI_IN_S_BASE: 10000 rects
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+Scaled magic input cell nmos_6p0_CDNS_4066195314520 geometry by factor of 10
+Scaled magic input cell nmos_6p0_CDNS_4066195314519 geometry by factor of 10
+Scaled magic input cell nmos_6p0_CDNS_4066195314518 geometry by factor of 10
+Scaled magic input cell nmos_6p0_CDNS_4066195314514 geometry by factor of 10
+Scaled magic input cell M2_M1_CDNS_40661953145181 geometry by factor of 10
+Scaled magic input cell M1_PSUB_CDNS_40661953145238 geometry by factor of 10
+Scaled magic input cell M1_PSUB_CDNS_40661953145235 geometry by factor of 10
+Scaled magic input cell M1_PSUB_CDNS_40661953145234 geometry by factor of 10
+Scaled magic input cell M1_PSUB_CDNS_40661953145233 geometry by factor of 10
+Scaled magic input cell M1_PSUB_CDNS_40661953145232 geometry by factor of 10
+Scaled magic input cell M1_POLY2_CDNS_40661953145229 geometry by factor of 10
+Scaled magic input cell M1_NWELL_CDNS_40661953145236 geometry by factor of 10
+Scaled magic input cell M1_NWELL_CDNS_40661953145231 geometry by factor of 10
+Scaled magic input cell M1_NWELL_CDNS_40661953145230 geometry by factor of 10
+Scaled magic input cell comp018green_out_drv_pleg_4T_Y geometry by factor of 2
+Scaled magic input cell comp018green_out_drv_pleg_4T_X geometry by factor of 2
+Scaled magic input cell M3_M2_CDNS_40661953145353 geometry by factor of 10
+Scaled magic input cell M3_M2_CDNS_40661953145264 geometry by factor of 10
+Scaled magic input cell M3_M2_CDNS_40661953145208 geometry by factor of 10
+Scaled magic input cell M2_M1_CDNS_40661953145366 geometry by factor of 10
+Scaled magic input cell M2_M1_CDNS_40661953145365 geometry by factor of 10
+Scaled magic input cell M3_M2_CDNS_40661953145363 geometry by factor of 10
+Scaled magic input cell M3_M2_CDNS_40661953145358 geometry by factor of 10
+Scaled magic input cell M3_M2_CDNS_40661953145350 geometry by factor of 10
+Scaled magic input cell M3_M2_CDNS_40661953145209 geometry by factor of 10
+Scaled magic input cell M3_M2_CDNS_40661953145180 geometry by factor of 10
+Scaled magic input cell M2_M1_CDNS_40661953145364 geometry by factor of 10
+Scaled magic input cell M2_M1_CDNS_40661953145360 geometry by factor of 10
+Scaled magic input cell M2_M1_CDNS_40661953145359 geometry by factor of 10
+Scaled magic input cell M2_M1_CDNS_40661953145356 geometry by factor of 10
+Scaled magic input cell M2_M1_CDNS_40661953145355 geometry by factor of 10
+Scaled magic input cell M2_M1_CDNS_40661953145354 geometry by factor of 10
+Scaled magic input cell M2_M1_CDNS_40661953145348 geometry by factor of 10
+Scaled magic input cell M2_M1_CDNS_40661953145347 geometry by factor of 10
+Scaled magic input cell M2_M1_CDNS_40661953145346 geometry by factor of 10
+Scaled magic input cell M2_M1_CDNS_40661953145177 geometry by factor of 10
+Scaled magic input cell M1_PSUB_CDNS_40661953145362 geometry by factor of 10
+Scaled magic input cell M1_PSUB_CDNS_40661953145357 geometry by factor of 10
+Scaled magic input cell M1_PSUB_CDNS_40661953145351 geometry by factor of 10
+Scaled magic input cell M1_PSUB_CDNS_40661953145349 geometry by factor of 10
+Scaled magic input cell M1_PSUB_CDNS_40661953145283 geometry by factor of 10
+Scaled magic input cell M1_NWELL_CDNS_40661953145361 geometry by factor of 10
+Scaled magic input cell M1_NWELL_CDNS_40661953145352 geometry by factor of 10
+Scaled magic input cell M1_NWELL_CDNS_40661953145345 geometry by factor of 10
+Scaled magic input cell M1_NWELL_CDNS_40661953145286 geometry by factor of 10
+Scaled magic input cell M3_M2_CDNS_40661953145371 geometry by factor of 10
+Scaled magic input cell M3_M2_CDNS_40661953145370 geometry by factor of 10
+Scaled magic input cell M3_M2_CDNS_40661953145369 geometry by factor of 10
+Scaled magic input cell M2_M1_CDNS_40661953145368 geometry by factor of 10
+Scaled magic input cell M2_M1_CDNS_40661953145367 geometry by factor of 10
+Scaled magic input cell M1_PSUB_CDNS_40661953145376 geometry by factor of 10
+Scaled magic input cell M1_PSUB_CDNS_40661953145375 geometry by factor of 10
+Scaled magic input cell M1_PSUB_CDNS_40661953145372 geometry by factor of 10
+Scaled magic input cell M1_NWELL_CDNS_40661953145374 geometry by factor of 10
+Scaled magic input cell M1_NWELL_CDNS_40661953145373 geometry by factor of 10
+Scaled magic input cell M3_M2_CDNS_40661953145342 geometry by factor of 10
+Scaled magic input cell M3_M2_CDNS_40661953145341 geometry by factor of 10
+Scaled magic input cell M3_M2_CDNS_40661953145340 geometry by factor of 10
+Scaled magic input cell M3_M2_CDNS_40661953145278 geometry by factor of 10
+Scaled magic input cell M3_M2_CDNS_40661953145263 geometry by factor of 10
+Scaled magic input cell M2_M1_CDNS_40661953145344 geometry by factor of 10
+Scaled magic input cell M2_M1_CDNS_40661953145343 geometry by factor of 10
+Scaled magic input cell M2_M1_CDNS_40661953145280 geometry by factor of 10
+Scaled magic input cell M2_M1_CDNS_40661953145279 geometry by factor of 10
+Scaled magic input cell M2_M1_CDNS_40661953145201 geometry by factor of 10
+Scaled magic input cell M1_PSUB_CDNS_40661953145321 geometry by factor of 10
+Scaled magic input cell M1_NWELL_CDNS_40661953145322 geometry by factor of 10
+Scaled magic input cell M1_NWELL_CDNS_40661953145315 geometry by factor of 10
+Scaled magic input cell ppolyf_u_CDNS_4066195314533 geometry by factor of 10
+Scaled magic input cell ppolyf_u_CDNS_4066195314532 geometry by factor of 10
+Scaled magic input cell M1_NWELL_CDNS_40661953145316 geometry by factor of 10
+Scaled magic input cell M1_PSUB_CDNS_40661953145324 geometry by factor of 10
+Scaled magic input cell M1_NWELL_CDNS_40661953145323 geometry by factor of 10
+Scaled magic input cell pmos_6p0_CDNS_4066195314548 geometry by factor of 10
+Scaled magic input cell pmos_6p0_CDNS_4066195314546 geometry by factor of 10
+Scaled magic input cell pmos_6p0_CDNS_4066195314539 geometry by factor of 10
+Scaled magic input cell nmos_6p0_CDNS_4066195314550 geometry by factor of 10
+Scaled magic input cell nmos_6p0_CDNS_4066195314549 geometry by factor of 10
+Scaled magic input cell nmos_6p0_CDNS_4066195314547 geometry by factor of 10
+Scaled magic input cell M2_M1_CDNS_40661953145216 geometry by factor of 10
+Scaled magic input cell M1_PSUB_CDNS_40661953145327 geometry by factor of 10
+Scaled magic input cell M1_PSUB_CDNS_40661953145326 geometry by factor of 10
+Scaled magic input cell M1_NWELL_CDNS_40661953145328 geometry by factor of 10
+Scaled magic input cell M1_NWELL_CDNS_40661953145325 geometry by factor of 10
+Scaled magic input cell pmos_6p0_CDNS_4066195314545 geometry by factor of 10
+Scaled magic input cell pmos_6p0_CDNS_4066195314544 geometry by factor of 10
+Scaled magic input cell pmos_6p0_CDNS_4066195314543 geometry by factor of 10
+Scaled magic input cell pmos_6p0_CDNS_4066195314538 geometry by factor of 10
+Scaled magic input cell pmos_6p0_CDNS_4066195314534 geometry by factor of 10
+Scaled magic input cell nmos_6p0_CDNS_4066195314542 geometry by factor of 10
+Scaled magic input cell nmos_6p0_CDNS_4066195314541 geometry by factor of 10
+Scaled magic input cell nmos_6p0_CDNS_4066195314540 geometry by factor of 10
+Scaled magic input cell nmos_6p0_CDNS_4066195314537 geometry by factor of 10
+Scaled magic input cell nmos_6p0_CDNS_4066195314536 geometry by factor of 10
+Scaled magic input cell nmos_6p0_CDNS_4066195314535 geometry by factor of 10
+Scaled magic input cell M2_M1_CDNS_40661953145115 geometry by factor of 10
+Scaled magic input cell M1_PSUB_CDNS_40661953145319 geometry by factor of 10
+Scaled magic input cell M1_PSUB_CDNS_40661953145317 geometry by factor of 10
+Scaled magic input cell M1_NWELL_CDNS_40661953145320 geometry by factor of 10
+Scaled magic input cell M1_NWELL_CDNS_40661953145318 geometry by factor of 10
+Scaled magic input cell M3_M2_CDNS_40661953145314 geometry by factor of 10
+Scaled magic input cell M3_M2_CDNS_40661953145313 geometry by factor of 10
+Scaled magic input cell M2_M1_CDNS_40661953145312 geometry by factor of 10
+Scaled magic input cell ppolyf_u_CDNS_4066195314525 geometry by factor of 10
+Scaled magic input cell pn_6p0_CDNS_4066195314527 geometry by factor of 10
+Scaled magic input cell np_6p0_CDNS_4066195314526 geometry by factor of 10
+Scaled magic input cell M3_M2_CDNS_40661953145269 geometry by factor of 10
+Scaled magic input cell M3_M2_CDNS_40661953145268 geometry by factor of 10
+Scaled magic input cell M3_M2_CDNS_40661953145265 geometry by factor of 10
+Scaled magic input cell M3_M2_CDNS_40661953145262 geometry by factor of 10
+Scaled magic input cell M3_M2_CDNS_40661953145258 geometry by factor of 10
+Scaled magic input cell M2_M1_CDNS_40661953145270 geometry by factor of 10
+Scaled magic input cell M2_M1_CDNS_40661953145267 geometry by factor of 10
+Scaled magic input cell M2_M1_CDNS_40661953145266 geometry by factor of 10
+Scaled magic input cell M2_M1_CDNS_40661953145261 geometry by factor of 10
+Scaled magic input cell M2_M1_CDNS_40661953145260 geometry by factor of 10
+Scaled magic input cell M2_M1_CDNS_40661953145259 geometry by factor of 10
+Scaled magic input cell M2_M1_CDNS_40661953145257 geometry by factor of 10
+Scaled magic input cell M2_M1_CDNS_40661953145256 geometry by factor of 10
+Scaled magic input cell M2_M1_CDNS_40661953145247 geometry by factor of 10
+Scaled magic input cell M2_M1_CDNS_40661953145239 geometry by factor of 10
+Scaled magic input cell M2_M1_CDNS_40661953145182 geometry by factor of 10
+Scaled magic input cell M1_PACTIVE_CDNS_40661953145253 geometry by factor of 10
+Scaled magic input cell M1_PACTIVE_CDNS_40661953145252 geometry by factor of 10
+Scaled magic input cell M1_PACTIVE_CDNS_40661953145251 geometry by factor of 10
+Scaled magic input cell M1_PACTIVE_CDNS_40661953145250 geometry by factor of 10
+Scaled magic input cell M1_PACTIVE_CDNS_40661953145249 geometry by factor of 10
+Scaled magic input cell M1_PACTIVE_CDNS_40661953145248 geometry by factor of 10
+Scaled magic input cell M1_PACTIVE_CDNS_40661953145240 geometry by factor of 10
+Scaled magic input cell M1_NACTIVE_CDNS_40661953145255 geometry by factor of 10
+Scaled magic input cell M1_NACTIVE_CDNS_40661953145254 geometry by factor of 10
+Scaled magic input cell M1_NACTIVE_CDNS_40661953145246 geometry by factor of 10
+Scaled magic input cell M1_NACTIVE_CDNS_40661953145245 geometry by factor of 10
+Scaled magic input cell M1_NACTIVE_CDNS_40661953145244 geometry by factor of 10
+Scaled magic input cell M1_NACTIVE_CDNS_40661953145243 geometry by factor of 10
+Scaled magic input cell M1_NACTIVE_CDNS_40661953145242 geometry by factor of 10
+Scaled magic input cell M1_NACTIVE_CDNS_40661953145241 geometry by factor of 10
+Scaled magic input cell M3_M2_CDNS_40661953145332 geometry by factor of 10
+Scaled magic input cell M3_M2_CDNS_40661953145330 geometry by factor of 10
+Scaled magic input cell M3_M2_CDNS_40661953145213 geometry by factor of 10
+Scaled magic input cell M3_M2_CDNS_40661953145212 geometry by factor of 10
+Scaled magic input cell M3_M2_CDNS_40661953145210 geometry by factor of 10
+Scaled magic input cell M3_M2_CDNS_40661953145207 geometry by factor of 10
+Scaled magic input cell M3_M2_CDNS_40661953145206 geometry by factor of 10
+Scaled magic input cell M3_M2_CDNS_40661953145204 geometry by factor of 10
+Scaled magic input cell M3_M2_CDNS_40661953145202 geometry by factor of 10
+Scaled magic input cell M3_M2_CDNS_40661953145200 geometry by factor of 10
+Scaled magic input cell M3_M2_CDNS_40661953145199 geometry by factor of 10
+Scaled magic input cell M3_M2_CDNS_40661953145197 geometry by factor of 10
+Scaled magic input cell M3_M2_CDNS_40661953145196 geometry by factor of 10
+Scaled magic input cell M3_M2_CDNS_40661953145194 geometry by factor of 10
+Scaled magic input cell M3_M2_CDNS_40661953145193 geometry by factor of 10
+Scaled magic input cell M3_M2_CDNS_40661953145190 geometry by factor of 10
+Scaled magic input cell M3_M2_CDNS_40661953145188 geometry by factor of 10
+Scaled magic input cell M3_M2_CDNS_40661953145186 geometry by factor of 10
+Scaled magic input cell M3_M2_CDNS_40661953145179 geometry by factor of 10
+Scaled magic input cell M3_M2_CDNS_40661953145174 geometry by factor of 10
+Scaled magic input cell M3_M2_CDNS_40661953145172 geometry by factor of 10
+Scaled magic input cell M3_M2_CDNS_40661953145170 geometry by factor of 10
+Scaled magic input cell M2_M1_CDNS_40661953145378 geometry by factor of 10
+Scaled magic input cell M2_M1_CDNS_40661953145333 geometry by factor of 10
+Scaled magic input cell M2_M1_CDNS_40661953145331 geometry by factor of 10
+Scaled magic input cell M2_M1_CDNS_40661953145329 geometry by factor of 10
+Scaled magic input cell M2_M1_CDNS_40661953145214 geometry by factor of 10
+Scaled magic input cell M2_M1_CDNS_40661953145211 geometry by factor of 10
+Scaled magic input cell M2_M1_CDNS_40661953145205 geometry by factor of 10
+Scaled magic input cell M2_M1_CDNS_40661953145203 geometry by factor of 10
+Scaled magic input cell M2_M1_CDNS_40661953145198 geometry by factor of 10
+Scaled magic input cell M2_M1_CDNS_40661953145195 geometry by factor of 10
+Scaled magic input cell M2_M1_CDNS_40661953145189 geometry by factor of 10
+Scaled magic input cell M2_M1_CDNS_40661953145187 geometry by factor of 10
+Scaled magic input cell M2_M1_CDNS_40661953145185 geometry by factor of 10
+Scaled magic input cell M2_M1_CDNS_40661953145178 geometry by factor of 10
+Scaled magic input cell M2_M1_CDNS_40661953145176 geometry by factor of 10
+Scaled magic input cell M2_M1_CDNS_40661953145173 geometry by factor of 10
+Scaled magic input cell M2_M1_CDNS_40661953145171 geometry by factor of 10
+Scaled magic input cell M2_M1_CDNS_40661953145169 geometry by factor of 10
+Scaled magic input cell M2_M1_CDNS_40661953145163 geometry by factor of 10
+Scaled magic input cell M2_M1_CDNS_40661953145120 geometry by factor of 10
+Scaled magic input cell M2_M1_CDNS_40661953145116 geometry by factor of 10
+Scaled magic input cell M2_M1_CDNS_40661953145114 geometry by factor of 10
+Scaled magic input cell M1_PSUB_CDNS_40661953145339 geometry by factor of 10
+Scaled magic input cell M1_PSUB_CDNS_40661953145338 geometry by factor of 10
+Scaled magic input cell M1_PSUB_CDNS_40661953145215 geometry by factor of 10
+Scaled magic input cell M1_PACTIVE_CDNS_40661953145168 geometry by factor of 10
+Scaled magic input cell M1_PACTIVE_CDNS_40661953145167 geometry by factor of 10
+Scaled magic input cell M1_PACTIVE_CDNS_40661953145166 geometry by factor of 10
+Scaled magic input cell M1_PACTIVE_CDNS_40661953145165 geometry by factor of 10
+Scaled magic input cell M1_NWELL_CDNS_40661953145377 geometry by factor of 10
+GF_NI_IN_C_BASE: 10000 rects
+GF_NI_IN_C_BASE: 20000 rects
+GF_NI_BI_T_BASE: 10000 rects
+GF_NI_BI_T_BASE: 20000 rects
+Scaled magic input cell M3_M2_CDNS_40661953145335 geometry by factor of 10
+Scaled magic input cell M2_M1_CDNS_40661953145334 geometry by factor of 10
+Scaled magic input cell M1_PACTIVE_CDNS_40661953145337 geometry by factor of 10
+Scaled magic input cell M1_PACTIVE_CDNS_40661953145336 geometry by factor of 10
+GF_NI_DVDD_BASE: 10000 rects
+GF_NI_DVDD_BASE: 20000 rects
+GF_NI_DVDD_BASE: 30000 rects
+GF_NI_DVDD_BASE: 40000 rects
+GF_NI_DVDD_BASE: 50000 rects
+GF_NI_DVDD_BASE: 60000 rects
+GF_NI_DVDD_BASE: 70000 rects
+GF_NI_DVDD_BASE: 80000 rects
+nmos_clamp_20_50_4_DVDD: 10000 rects
+nmos_clamp_20_50_4_DVDD: 20000 rects
+nmos_clamp_20_50_4_DVDD: 30000 rects
+Scaled magic input cell M2_M1_CDNS_40661953145139 geometry by factor of 10
+Scaled magic input cell M2_M1_CDNS_40661953145137 geometry by factor of 10
+Scaled magic input cell M2_M1_CDNS_40661953145121 geometry by factor of 10
+Scaled magic input cell M2_M1_CDNS_40661953145119 geometry by factor of 10
+Scaled magic input cell M2_M1_CDNS_40661953145104 geometry by factor of 10
+Scaled magic input cell M3_M2_CDNS_4066195314595 geometry by factor of 10
+Scaled magic input cell M2_M1_CDNS_4066195314591 geometry by factor of 10
+Scaled magic input cell M2_M1_CDNS_4066195314583 geometry by factor of 10
+Scaled magic input cell M2_M1_CDNS_4066195314582 geometry by factor of 10
+Scaled magic input cell M2_M1_CDNS_4066195314581 geometry by factor of 10
+Scaled magic input cell M2_M1_CDNS_4066195314580 geometry by factor of 10
+Scaled magic input cell M2_M1_CDNS_4066195314579 geometry by factor of 10
+Scaled magic input cell M2_M1_CDNS_4066195314578 geometry by factor of 10
+Scaled magic input cell M2_M1_CDNS_4066195314577 geometry by factor of 10
+Scaled magic input cell M2_M1_CDNS_4066195314576 geometry by factor of 10
+Scaled magic input cell M2_M1_CDNS_4066195314575 geometry by factor of 10
+gf180mcu_fd_io__fill5: 10000 rects
+Scaled magic input cell M5_M4_CDNS_4066195314513 geometry by factor of 10
+Scaled magic input cell M5_M4_CDNS_4066195314511 geometry by factor of 10
+Scaled magic input cell M4_M3_CDNS_4066195314514 geometry by factor of 10
+Scaled magic input cell M4_M3_CDNS_4066195314512 geometry by factor of 10
+Scaled magic input cell M2_M1_CDNS_4066195314518 geometry by factor of 10
+Scaled magic input cell M3_M2_CDNS_4066195314517 geometry by factor of 10
+Scaled magic input cell M2_M1_CDNS_4066195314515 geometry by factor of 10
+Scaled magic input cell M1_PSUB_CDNS_4066195314516 geometry by factor of 10
+Scaled magic input cell alpha_1 geometry by factor of 12
+Scaled magic input cell alpha_8 geometry by factor of 12
+Scaled magic input cell alpha_0 geometry by factor of 12
+Scaled magic input cell alpha_4 geometry by factor of 12
+Scaled magic input cell alpha_5 geometry by factor of 12
+Scaled magic input cell alpha_D geometry by factor of 12
+Scaled magic input cell alpha_6 geometry by factor of 12
+Processing timestamp mismatches: gf180mcu_fd_ip_sram__sram512x8m8wm1, gf180mcu_fd_sc_mcu7t5v0__nor3_4, gf180mcu_fd_sc_mcu7t5v0__nand4_4, gf180mcu_fd_sc_mcu7t5v0__or3_4, gf180mcu_fd_sc_mcu7t5v0__and4_4, gf180mcu_fd_sc_mcu7t5v0__nor4_4, gf180mcu_fd_sc_mcu7t5v0__or4_4, gf180mcu_fd_sc_mcu7t5v0__clkbuf_16.
+ Generating output for cell caravel_logo
+ Generating output for cell font_73
+ Generating output for cell font_69
+ Generating output for cell font_68
+ Generating output for cell font_67
+ Generating output for cell font_65
+ Generating output for cell font_61
+ Generating output for cell font_54
+ Generating output for cell font_53
+ Generating output for cell font_49
+ Generating output for cell font_43
+ Generating output for cell font_22
+ Generating output for cell font_6E
+ Generating output for cell font_6C
+ Generating output for cell caravel_motto
+ Generating output for cell caravel_power_routing
+ Generating output for cell gf180mcu_fd_sc_mcu7t5v0__filltie
+ Generating output for cell gf180mcu_fd_sc_mcu7t5v0__endcap
+ Generating output for cell gf180mcu_fd_sc_mcu7t5v0__fill_1
+ Generating output for cell gf180mcu_fd_sc_mcu7t5v0__fill_2
+ Generating output for cell gf180mcu_fd_sc_mcu7t5v0__fillcap_4
+ Generating output for cell gf180mcu_fd_sc_mcu7t5v0__fillcap_8
+ Generating output for cell gf180mcu_fd_sc_mcu7t5v0__fillcap_16
+ Generating output for cell gf180mcu_fd_sc_mcu7t5v0__fillcap_32
+ Generating output for cell gf180mcu_fd_sc_mcu7t5v0__clkbuf_8
+ Generating output for cell gf180mcu_fd_sc_mcu7t5v0__antenna
+ Generating output for cell mprj_io_buffer
+ Generating output for cell gf180mcu_fd_sc_mcu7t5v0__tiel
+ Generating output for cell gf180mcu_fd_sc_mcu7t5v0__tieh
+ Generating output for cell gpio_defaults_block_009
+ Generating output for cell gpio_defaults_block_087
+ Generating output for cell gpio_defaults_block_007
+ Generating output for cell gpio_defaults_block_008
+ Generating output for cell gf180mcu_fd_sc_mcu7t5v0__fillcap_64
+ Generating output for cell gf180mcu_fd_sc_mcu7t5v0__inv_3
+ Generating output for cell gf180mcu_fd_sc_mcu7t5v0__clkinv_8
+ Generating output for cell gf180mcu_fd_sc_mcu7t5v0__clkinv_3
+ Generating output for cell gf180mcu_fd_sc_mcu7t5v0__clkinv_4
+ Generating output for cell gf180mcu_fd_sc_mcu7t5v0__xnor2_1
+ Generating output for cell gf180mcu_fd_sc_mcu7t5v0__inv_4
+ Generating output for cell gf180mcu_fd_sc_mcu7t5v0__xnor2_2
+ Generating output for cell gf180mcu_fd_sc_mcu7t5v0__xor2_2
+ Generating output for cell gf180mcu_fd_sc_mcu7t5v0__xor2_4
+ Generating output for cell gf180mcu_fd_sc_mcu7t5v0__inv_2
+ Generating output for cell gf180mcu_fd_sc_mcu7t5v0__mux2_4
+ Generating output for cell gf180mcu_fd_sc_mcu7t5v0__oai222_4
+ Generating output for cell gf180mcu_fd_sc_mcu7t5v0__inv_1
+ Generating output for cell gf180mcu_fd_sc_mcu7t5v0__clkinv_2
+ Generating output for cell gf180mcu_fd_sc_mcu7t5v0__oai221_4
+ Generating output for cell gf180mcu_fd_sc_mcu7t5v0__aoi211_4
+ Generating output for cell gf180mcu_fd_sc_mcu7t5v0__xor2_1
+ Generating output for cell gf180mcu_fd_sc_mcu7t5v0__oai22_4
+ Generating output for cell gf180mcu_fd_sc_mcu7t5v0__or2_4
+ Generating output for cell gf180mcu_fd_sc_mcu7t5v0__oai31_4
+ Generating output for cell gf180mcu_fd_sc_mcu7t5v0__oai211_4
+ Generating output for cell gf180mcu_fd_sc_mcu7t5v0__nor2_4
+ Generating output for cell gf180mcu_fd_sc_mcu7t5v0__nand3_4
+ Generating output for cell gf180mcu_fd_sc_mcu7t5v0__oai32_4
+ Generating output for cell gf180mcu_fd_sc_mcu7t5v0__and3_4
+ Generating output for cell gf180mcu_fd_sc_mcu7t5v0__aoi21_4
+ Generating output for cell gf180mcu_fd_sc_mcu7t5v0__aoi22_4
+ Generating output for cell gf180mcu_fd_sc_mcu7t5v0__aoi221_4
+ Generating output for cell gf180mcu_fd_sc_mcu7t5v0__nand2_4
+ Generating output for cell gf180mcu_fd_sc_mcu7t5v0__aoi222_4
+ Generating output for cell gf180mcu_fd_sc_mcu7t5v0__oai21_4
+ Generating output for cell gf180mcu_fd_sc_mcu7t5v0__nor2_2
+ Generating output for cell gf180mcu_fd_sc_mcu7t5v0__and2_4
+ Generating output for cell gf180mcu_fd_sc_mcu7t5v0__dffsnq_2
+ Generating output for cell gf180mcu_fd_sc_mcu7t5v0__dffsnq_4
+ Generating output for cell gf180mcu_fd_sc_mcu7t5v0__dffsnq_1
+ Generating output for cell gf180mcu_fd_sc_mcu7t5v0__dffq_1
+ Generating output for cell gf180mcu_fd_sc_mcu7t5v0__dffnrnq_1
+ Generating output for cell gf180mcu_fd_sc_mcu7t5v0__dffnsnq_1
+ Generating output for cell gf180mcu_fd_sc_mcu7t5v0__dffrnq_1
+ Generating output for cell gf180mcu_fd_sc_mcu7t5v0__dffrnq_2
+ Generating output for cell gf180mcu_fd_sc_mcu7t5v0__dffrnq_4
+ Generating output for cell gf180mcu_fd_sc_mcu7t5v0__clkbuf_12
+ Generating output for cell gf180mcu_fd_sc_mcu7t5v0__buf_8
+ Generating output for cell gf180mcu_fd_sc_mcu7t5v0__dlyb_4
+ Generating output for cell gf180mcu_fd_sc_mcu7t5v0__clkbuf_3
+ Generating output for cell gf180mcu_fd_sc_mcu7t5v0__clkbuf_2
+ Generating output for cell gf180mcu_fd_sc_mcu7t5v0__clkbuf_4
+ Generating output for cell gf180mcu_fd_sc_mcu7t5v0__clkinv_1
+ Generating output for cell gf180mcu_fd_sc_mcu7t5v0__clkbuf_1
+ Generating output for cell gf180mcu_fd_sc_mcu7t5v0__buf_4
+ Generating output for cell gf180mcu_fd_sc_mcu7t5v0__clkbuf_16
+ Generating output for cell gf180mcu_fd_sc_mcu7t5v0__or4_4
+ Generating output for cell gf180mcu_fd_sc_mcu7t5v0__nor4_4
+ Generating output for cell gf180mcu_fd_sc_mcu7t5v0__and4_4
+ Generating output for cell gf180mcu_fd_sc_mcu7t5v0__or3_4
+ Generating output for cell gf180mcu_fd_sc_mcu7t5v0__nand4_4
+ Generating output for cell gf180mcu_fd_sc_mcu7t5v0__nor3_4
+ Generating output for cell gf180mcu_fd_sc_mcu7t5v0__mux2_2
+ Generating output for cell housekeeping
+ Generating output for cell user_project_wrapper
+Reading "gf180mcu_fd_sc_mcu7t5v0__fill_1".
+Reading "gf180mcu_fd_sc_mcu7t5v0__endcap".
+Reading "gf180mcu_fd_sc_mcu7t5v0__filltie".
+Reading "gf180mcu_fd_sc_mcu7t5v0__fillcap_64".
+Reading "gf180mcu_fd_sc_mcu7t5v0__fillcap_32".
+Reading "gf180mcu_fd_sc_mcu7t5v0__clkbuf_2".
+Reading "gf180mcu_fd_sc_mcu7t5v0__fillcap_16".
+Reading "gf180mcu_fd_sc_mcu7t5v0__fillcap_8".
+Reading "gf180mcu_fd_sc_mcu7t5v0__fillcap_4".
+Reading "gf180mcu_fd_sc_mcu7t5v0__antenna".
+Reading "gf180mcu_fd_sc_mcu7t5v0__fill_2".
+Reading "gf180mcu_fd_sc_mcu7t5v0__clkbuf_3".
+Reading "gf180mcu_fd_sc_mcu7t5v0__dffq_1".
+Reading "gf180mcu_fd_sc_mcu7t5v0__buf_1".
+Reading "gf180mcu_fd_sc_mcu7t5v0__dlyb_1".
+Reading "gf180mcu_fd_sc_mcu7t5v0__dlyd_4".
+Reading "gf180mcu_fd_sc_mcu7t5v0__clkinv_1".
+Reading "gf180mcu_fd_sc_mcu7t5v0__dlyc_1".
+Reading "gf180mcu_fd_sc_mcu7t5v0__mux4_1".
+Reading "gf180mcu_fd_sc_mcu7t5v0__tiel".
+Reading "gf180mcu_fd_sc_mcu7t5v0__clkbuf_1".
+Reading "gf180mcu_fd_sc_mcu7t5v0__nand3_1".
+Reading "gf180mcu_fd_sc_mcu7t5v0__oai211_1".
+Reading "gf180mcu_fd_sc_mcu7t5v0__oai21_1".
+Reading "gf180mcu_fd_sc_mcu7t5v0__or2_1".
+Reading "gf180mcu_fd_sc_mcu7t5v0__buf_2".
+Reading "gf180mcu_fd_sc_mcu7t5v0__buf_8".
+Reading "gf180mcu_fd_sc_mcu7t5v0__buf_4".
+Reading "gf180mcu_fd_sc_mcu7t5v0__aoi22_1".
+Reading "gf180mcu_fd_sc_mcu7t5v0__aoi21_1".
+Reading "gf180mcu_fd_sc_mcu7t5v0__and3_1".
+Reading "gf180mcu_fd_sc_mcu7t5v0__and2_1".
+Reading "gf180mcu_fd_sc_mcu7t5v0__dffrnq_1".
+Reading "gf180mcu_fd_sc_mcu7t5v0__clkinv_8".
+Reading "gf180mcu_fd_sc_mcu7t5v0__clkinv_4".
+Reading "gf180mcu_fd_sc_mcu7t5v0__clkinv_3".
+Reading "gf180mcu_fd_sc_mcu7t5v0__clkinv_2".
+Reading "gf180mcu_fd_sc_mcu7t5v0__clkbuf_16".
+Reading "gf180mcu_fd_sc_mcu7t5v0__nor3_1".
+Reading "gf180mcu_fd_sc_mcu7t5v0__nor2_1".
+Reading "gf180mcu_fd_sc_mcu7t5v0__nand3_2".
+Reading "gf180mcu_fd_sc_mcu7t5v0__nand2_4".
+Reading "gf180mcu_fd_sc_mcu7t5v0__nand2_2".
+Reading "gf180mcu_fd_sc_mcu7t5v0__nand2_1".
+Reading "gf180mcu_fd_sc_mcu7t5v0__inv_1".
+Reading "fpga_struct_block".
+Reading "gf180mcu_fd_sc_mcu7t5v0__oai21_2".
+Reading "gf180mcu_fd_sc_mcu7t5v0__mux4_2".
+Reading "gf180mcu_fd_sc_mcu7t5v0__oai22_1".
+Reading "gf180mcu_fd_sc_mcu7t5v0__dlyd_1".
+Reading "gf180mcu_fd_sc_mcu7t5v0__buf_3".
+Reading "gf180mcu_fd_sc_mcu7t5v0__clkbuf_8".
+Reading "gf180mcu_fd_sc_mcu7t5v0__oai32_1".
+Reading "gf180mcu_fd_sc_mcu7t5v0__or4_2".
+Reading "gf180mcu_fd_sc_mcu7t5v0__nor4_4".
+Reading "gf180mcu_fd_sc_mcu7t5v0__nor2_2".
+Reading "gf180mcu_fd_sc_mcu7t5v0__aoi211_1".
+Reading "gf180mcu_fd_sc_mcu7t5v0__aoi211_4".
+Reading "gf180mcu_fd_sc_mcu7t5v0__nor3_4".
+Reading "gf180mcu_fd_sc_mcu7t5v0__and4_1".
+Reading "gf180mcu_fd_sc_mcu7t5v0__aoi21_4".
+Reading "gf180mcu_fd_sc_mcu7t5v0__nand4_4".
+Reading "gf180mcu_fd_sc_mcu7t5v0__clkbuf_4".
+Reading "gf180mcu_fd_sc_mcu7t5v0__oai21_4".
+Reading "gf180mcu_fd_sc_mcu7t5v0__nor2_4".
+Reading "gf180mcu_fd_sc_mcu7t5v0__and3_2".
+Reading "gf180mcu_fd_sc_mcu7t5v0__aoi21_2".
+Reading "gf180mcu_fd_sc_mcu7t5v0__mux2_2".
+Reading "gf180mcu_fd_sc_mcu7t5v0__aoi221_4".
+Reading "gf180mcu_fd_sc_mcu7t5v0__or2_2".
+Reading "gf180mcu_fd_sc_mcu7t5v0__aoi22_2".
+Reading "gf180mcu_fd_sc_mcu7t5v0__nor3_2".
+Reading "gf180mcu_fd_sc_mcu7t5v0__inv_3".
+Reading "gf180mcu_fd_sc_mcu7t5v0__oai211_2".
+Reading "gf180mcu_fd_sc_mcu7t5v0__oai211_4".
+Reading "gf180mcu_fd_sc_mcu7t5v0__aoi211_2".
+Reading "gf180mcu_fd_sc_mcu7t5v0__aoi221_1".
+Reading "gf180mcu_fd_sc_mcu7t5v0__tieh".
+Reading "gf180mcu_fd_sc_mcu7t5v0__aoi22_4".
+Reading "gf180mcu_fd_sc_mcu7t5v0__oai221_4".
+Reading "gf180mcu_fd_sc_mcu7t5v0__dffsnq_1".
+Reading "gf180mcu_fd_sc_mcu7t5v0__aoi221_2".
+Reading "gf180mcu_fd_sc_mcu7t5v0__nand3_4".
+Reading "gf180mcu_fd_sc_mcu7t5v0__oai221_1".
+Reading "gf180mcu_fd_sc_mcu7t5v0__dffrnq_2".
+Reading "gf180mcu_fd_sc_mcu7t5v0__dffq_2".
+Reading "gf180mcu_fd_sc_mcu7t5v0__mux4_4".
+Reading "gf180mcu_fd_sc_mcu7t5v0__nand4_2".
+Reading "gf180mcu_fd_sc_mcu7t5v0__nand4_1".
+Reading "gf180mcu_fd_sc_mcu7t5v0__inv_2".
+Reading "gf180mcu_fd_sc_mcu7t5v0__oai31_2".
+Reading "gf180mcu_fd_sc_mcu7t5v0__oai31_1".
+Reading "efuse_array".
+Reading "efuse_ctrl".
+Reading "user_project_wrapper".
+ Generating output for cell simple_por
+Reading "nmos_6p0_BUMBUS".
+Reading "pmos_6p0_GUW2N9".
+Reading "nmos_6p0_BUMBJU".
+Reading "pmos_6p0_MUW2NR".
+Reading "std_inverter".
+Reading "std_buffer".
+Reading "pmos_6p0_UXEQNM".
+Reading "nmos_6p0_BJPB5U".
+Reading "pmos_6p0_9859UL".
+Reading "pmos_6p0_9YEQN4".
+Reading "nmos_6p0_L3YBEV".
+Reading "schmitt_inverter".
+Reading "mim_2p0fF_8KW78G".
+Reading "large_mimcap".
+Reading "nmos_6p0_BJXXPT".
+Reading "nmos_6p0_B4TB5U".
+Reading "via_cont_0p6um".
+Reading "via_cont_2um".
+Reading "pmos_6p0_CYEQN4".
+Reading "pmos_6p0_HUEQQM".
+Reading "pmos_6p0_EYEQQM".
+Reading "ppolyf_u_1k_6p0_TRTT7C".
+Reading "reduction_mirror".
+Reading "simple_por".
+ Generating output for cell pmos_5p043105913020110_512x8m81
+ Generating output for cell pmos_5p043105913020105_512x8m81
+ Generating output for cell pmos_5p043105913020103_512x8m81
+ Generating output for cell pmos_1p2_03_R270_512x8m81
+ Generating output for cell pmos_5p043105913020104_512x8m81
+ Generating output for cell pmos_1p2_02_R270_512x8m81
+ Generating output for cell pmos_5p043105913020108_512x8m81
+ Generating output for cell pmos_1p2_01_R270_512x8m81
+ Generating output for cell nmos_5p043105913020109_512x8m81
+ Generating output for cell nmos_5p043105913020107_512x8m81
+ Generating output for cell nmos_5p043105913020106_512x8m81
+ Generating output for cell nmos_5p04310591302044_512x8m81
+ Generating output for cell nmos_1p2_02_R270_512x8m81
+ Generating output for cell M3_M2$$204401708_512x8m81
+ Generating output for cell M3_M2$$204400684_512x8m81
+ Generating output for cell M3_M2$$204399660_512x8m81
+ Generating output for cell M3_M2$$204398636_512x8m81
+ Generating output for cell M3_M2$$204147756_512x8m81
+ Generating output for cell M3_M2$$201252908_512x8m81
+ Generating output for cell M3_M2$$201251884_512x8m81
+ Generating output for cell M2_M1$02_R270_512x8m81
+ Generating output for cell M2_M1$$204408876_512x8m81
+ Generating output for cell M2_M1$$204407852_512x8m81
+ Generating output for cell M2_M1$$204406828_512x8m81
+ Generating output for cell M2_M1$$204405804_512x8m81
+ Generating output for cell M2_M1$$204404780_512x8m81
+ Generating output for cell M2_M1$$204403756_512x8m81
+ Generating output for cell M2_M1$$204402732_512x8m81
+ Generating output for cell M2_M1$$202406956_512x8m81
+ Generating output for cell M2_M1$$202394668_512x8m81
+ Generating output for cell M2_M1$$201262124_512x8m81
+ Generating output for cell M2_M1$$46894124_512x8m81
+ Generating output for cell M2_M1$$45004844_512x8m81
+ Generating output for cell M1_PSUB_05_512x8m81
+ Generating output for cell M1_PSUB$$45111340_512x8m81
+ Generating output for cell M1_POLY243105913020105_512x8m81
+ Generating output for cell M1_POLY24310591302033_512x8m81
+ Generating output for cell M1_POLY24310591302031_512x8m81
+ Generating output for cell M1_POLY24310591302019_512x8m81
+ Generating output for cell M1_PACTIVE43105913020106_51_0
+ Generating output for cell M1_PACTIVE03_512x8m81
+ Generating output for cell M1_NWELL4310591302032_512x8m81
+ Generating output for cell M1_NWELL07_512x8m81
+ Generating output for cell xdec_512x8m81
+ Generating output for cell xdec8_512x8m81
+ Generating output for cell xdec32_512x8m81
+ Generating output for cell xdec32_468_512x8m81
+ Generating output for cell pmoscap_R270_512x8m81
+ Generating output for cell M3_M2$01_R270_512x8m81
+ Generating output for cell M2_M1$04_R270_512x8m81
+ Generating output for cell M1_POLY2_01_R270_512x8m81
+ Generating output for cell M1_PACTIVE_R270_512x8m81
+ Generating output for cell M1_NACTIVE_01_R270_512x8m81
+ Generating output for cell pmoscap_L1_W2_R270_512x8m81
+ Generating output for cell pmos_5p043105913020101_512x8m81
+ Generating output for cell pmos_5p043105913020100_512x8m81
+ Generating output for cell pmos_1p2_02_R90_512x8m81
+ Generating output for cell pmos_1p2_01_R90_512x8m81
+ Generating output for cell nmos_5p043105913020111_512x8m81
+ Generating output for cell nmos_5p04310591302099_512x8m81
+ Generating output for cell nmos_1p2_02_R90_512x8m81
+ Generating output for cell nmos_5p043105913020102_512x8m81
+ Generating output for cell nmos_1p2_01_R270_512x8m81
+ Generating output for cell M3_M2$$204146732_512x8m81
+ Generating output for cell M3_M2$$204145708_512x8m81
+ Generating output for cell M3_M2$$204144684_512x8m81
+ Generating output for cell M3_M2$$204143660_512x8m81
+ Generating output for cell M3_M2$$204142636_512x8m81
+ Generating output for cell M2_M1$$204222508_512x8m81
+ Generating output for cell M2_M1$$204221484_512x8m81
+ Generating output for cell M2_M1$$204220460_512x8m81
+ Generating output for cell M2_M1$$204141612_512x8m81
+ Generating output for cell M2_M1$$204140588_512x8m81
+ Generating output for cell M2_M1$$204139564_512x8m81
+ Generating output for cell M2_M1$$204138540_512x8m81
+ Generating output for cell M1_POLY2$$204150828_512x8m81
+ Generating output for cell M1_PACTIVE$11_512x8m81
+ Generating output for cell M1_PACTIVE$10_512x8m81
+ Generating output for cell M1_NWELL_01_512x8m81
+ Generating output for cell M1_NACTIVE_02_512x8m81
+ Generating output for cell xdec64_512x8m81
+ Generating output for cell pmos_5p04310591302043_512x8m81
+ Generating output for cell pmos_5p04310591302041_512x8m81
+ Generating output for cell pmos_5p04310591302035_512x8m81
+ Generating output for cell pmos_5p04310591302020_512x8m81
+ Generating output for cell pmos_5p04310591302014_512x8m81
+ Generating output for cell pmos_1p2$$202587180_512x8m81
+ Generating output for cell pmos_1p2$$202586156_512x8m81
+ Generating output for cell pmos_1p2$$202585132_512x8m81
+ Generating output for cell pmos_1p2$$202584108_512x8m81
+ Generating output for cell pmos_1p2$$202583084_512x8m81
+ Generating output for cell nmos_5p04310591302042_512x8m81
+ Generating output for cell nmos_5p04310591302040_512x8m81
+ Generating output for cell nmos_5p04310591302039_512x8m81
+ Generating output for cell nmos_5p04310591302010_512x8m81
+ Generating output for cell nmos_5p0431059130208_512x8m81
+ Generating output for cell nmos_1p2$$202598444_512x8m81
+ Generating output for cell nmos_1p2$$202596396_512x8m81
+ Generating output for cell nmos_1p2$$202595372_512x8m81
+ Generating output for cell nmos_1p2$$202594348_512x8m81
+ Generating output for cell M3_M24310591302036_512x8m81
+ Generating output for cell M3_M2$$202397740_512x8m81
+ Generating output for cell M2_M14310591302035_512x8m81
+ Generating output for cell M2_M1$$202396716_512x8m81
+ Generating output for cell M2_M1$$202395692_512x8m81
+ Generating output for cell M1_PACTIVE4310591302027_512x8m81
+ Generating output for cell M1_NACTIVE_01_512x8m81
+ Generating output for cell M1_NACTIVE4310591302037_512x8m81
+ Generating output for cell wen_wm1_512x8m81
+ Generating output for cell via2_x2_512x8m81
+ Generating output for cell via2_512x8m81
+ Generating output for cell via1_x2_R90_512x8m81
+ Generating output for cell via1_x2_512x8m81
+ Generating output for cell via2_x2_R90_512x8m81
+ Generating output for cell via1_2_x2_512x8m81
+ Generating output for cell via1_x2_R270_512x8m81
+ Generating output for cell via1_R90_512x8m81
+ Generating output for cell po_m1_512x8m81
+ Generating output for cell pmos_5p04310591302038_512x8m81
+ Generating output for cell pmos_5p04310591302027_512x8m81
+ Generating output for cell pmos_5p04310591302031_512x8m81
+ Generating output for cell pmos_1p2$$46287916_512x8m81
+ Generating output for cell pmos_5p04310591302013_512x8m81
+ Generating output for cell pmos_1p2$$46286892_512x8m81
+ Generating output for cell pmos_1p2$$46285868_512x8m81
+ Generating output for cell pmos_1p2$$46284844_512x8m81
+ Generating output for cell pmos_5p04310591302022_512x8m81
+ Generating output for cell pmos_1p2$$46283820_512x8m81
+ Generating output for cell pmos_5p04310591302024_512x8m81
+ Generating output for cell pmos_1p2$$46282796_512x8m81
+ Generating output for cell pmos_5p04310591302025_512x8m81
+ Generating output for cell pmos_1p2$$46281772_512x8m81
+ Generating output for cell pmos_5p04310591302030_512x8m81
+ Generating output for cell pmos_1p2$$45095980_512x8m81
+ Generating output for cell nmos_5p04310591302034_512x8m81
+ Generating output for cell nmos_5p04310591302033_512x8m81
+ Generating output for cell nmos_5p04310591302032_512x8m81
+ Generating output for cell nmos_5p04310591302028_512x8m81
+ Generating output for cell nmos_5p04310591302023_512x8m81
+ Generating output for cell nmos_5p04310591302012_512x8m81
+ Generating output for cell nmos_5p04310591302037_512x8m81
+ Generating output for cell nmos_1p2$$45103148_512x8m81
+ Generating output for cell nmos_5p04310591302026_512x8m81
+ Generating output for cell nmos_1p2$$45102124_512x8m81
+ Generating output for cell nmos_5p04310591302036_512x8m81
+ Generating output for cell nmos_1p2$$45101100_512x8m81
+ Generating output for cell nmos_5p04310591302029_512x8m81
+ Generating output for cell nmos_1p2$$45100076_512x8m81
+ Generating output for cell M3_M2$$45008940_512x8m81
+ Generating output for cell M3_M2$$45006892_512x8m81
+ Generating output for cell M3_M2$$45005868_512x8m81
+ Generating output for cell M2_M1c$$203396140_512x8m81
+ Generating output for cell M2_M1$$45003820_512x8m81
+ Generating output for cell M2_M1$$45002796_512x8m81
+ Generating output for cell M2_M1$$43374636_512x8m81
+ Generating output for cell M1_PSUB_285_512x8m81
+ Generating output for cell M1_PSUB$$44997676_512x8m81
+ Generating output for cell M1_POLY2$$45109292_512x8m81
+ Generating output for cell M1_POLY2$$44754988_512x8m81
+ Generating output for cell M1_POLY2$$44753964_512x8m81
+ Generating output for cell M1_PACTIVE4310591302034_512x8m81
+ Generating output for cell M1_NWELL04_512x8m81
+ Generating output for cell M1_NWELL03_512x8m81
+ Generating output for cell M1_NWELL02_512x8m81
+ Generating output for cell sacntl_2_512x8m81
+ Generating output for cell via1_R270_512x8m81
+ Generating output for cell via1_512x8m81
+ Generating output for cell via2_x2_R270_512x8m81
+ Generating output for cell via1_2_x2_R270_512x8m81
+ Generating output for cell via1_2_x2_R90_512x8m81
+ Generating output for cell pmos_5p04310591302019_512x8m81
+ Generating output for cell pmos_1p2$$46898220_512x8m81
+ Generating output for cell pmos_1p2$$46897196_512x8m81
+ Generating output for cell pmos_5p04310591302021_512x8m81
+ Generating output for cell pmos_1p2$$46896172_512x8m81
+ Generating output for cell pmos_5p04310591302018_512x8m81
+ Generating output for cell pmos_1p2$$46549036_512x8m81
+ Generating output for cell nmos_5p04310591302015_512x8m81
+ Generating output for cell nmos_1p2$$46553132_512x8m81
+ Generating output for cell nmos_5p04310591302016_512x8m81
+ Generating output for cell nmos_1p2$$46552108_512x8m81
+ Generating output for cell nmos_1p2$$46551084_512x8m81
+ Generating output for cell nmos_5p04310591302017_512x8m81
+ Generating output for cell nmos_1p2$$46550060_512x8m81
+ Generating output for cell nmos_1p2$$45107244_512x8m81
+ Generating output for cell M3_M2$$43371564_512x8m81
+ Generating output for cell M1_PSUB_04_R90_512x8m81
+ Generating output for cell M1_PSUB$$46558252_512x8m81
+ Generating output for cell M1_PSUB$$46557228_512x8m81
+ Generating output for cell M1_PSUB$$46556204_512x8m81
+ Generating output for cell M1_PSUB$$46555180_512x8m81
+ Generating output for cell M1_NWELL_01_R90_512x8m81
+ Generating output for cell M1_NWELL06_512x8m81
+ Generating output for cell sa_512x8m81
+ Generating output for cell pmos_5p04310591302051_512x8m81
+ Generating output for cell pmos_5p04310591302049_512x8m81
+ Generating output for cell pmos_5p04310591302048_512x8m81
+ Generating output for cell pmos_5p04310591302047_512x8m81
+ Generating output for cell pmos_5p0431059130203_512x8m81
+ Generating output for cell pmos_1p2$$171625516_512x8m81
+ Generating output for cell nmos_5p04310591302052_512x8m81
+ Generating output for cell nmos_5p04310591302050_512x8m81
+ Generating output for cell nmos_5p04310591302046_512x8m81
+ Generating output for cell nmos_5p04310591302045_512x8m81
+ Generating output for cell M3_M2431059130207_512x8m81
+ Generating output for cell M2_M1431059130200_512x8m81
+ Generating output for cell M2_M1$$168351788_R90_512x8m81
+ Generating output for cell M1_PSUB_02_512x8m81
+ Generating output for cell M1_PACTIVE4310591302040_512x8m81
+ Generating output for cell M1_PACTIVE4310591302039_512x8m81
+ Generating output for cell M1_NWELL_01_R270_512x8m81
+ Generating output for cell M1_NACTIVE4310591302041_512x8m81
+ Generating output for cell M1_NACTIVE4310591302038_512x8m81
+ Generating output for cell outbuf_oe_512x8m81
+ Generating output for cell via2_R90_512x8m81
+ Generating output for cell via1_2_512x8m81
+ Generating output for cell pmos_5p0431059130201_512x8m81
+ Generating output for cell pmos_1p2$$46889004_512x8m81
+ Generating output for cell nmos_5p0431059130202_512x8m81
+ Generating output for cell nmos_5p0431059130200_512x8m81
+ Generating output for cell nmos_1p2$$47119404_512x8m81
+ Generating output for cell M3_M2431059130201_512x8m81
+ Generating output for cell M2_M14310591302020_512x8m81
+ Generating output for cell M2_M1431059130208_512x8m81
+ Generating output for cell M1_PSUB$$47122476_512x8m81
+ Generating output for cell M1_POLY24310591302030_512x8m81
+ Generating output for cell M1_NWELL09_512x8m81
+ Generating output for cell M1_NWELL05_512x8m81
+ Generating output for cell ypass_gate_a_512x8m81
+ Generating output for cell ypass_gate_512x8m81
+ Generating output for cell M3_M24310591302029_512x8m81
+ Generating output for cell M2_M14310591302018_512x8m81
+ Generating output for cell M1_NACTIVE4310591302028_512x8m81
+ Generating output for cell mux821_512x8m81
+ Generating output for cell m2_saout01_512x8m81
+ Generating output for cell po_m1_R270_512x8m81
+ Generating output for cell po_m1_R90_512x8m81
+ Generating output for cell pmos_5p0431059130209_512x8m81
+ Generating output for cell pmos_5p0431059130206_512x8m81
+ Generating output for cell pmos_5p0431059130204_512x8m81
+ Generating output for cell pmos_1p2$$46887980_512x8m81
+ Generating output for cell pmos_1p2$$46885932_512x8m81
+ Generating output for cell pmos_1p2$$46273580_512x8m81
+ Generating output for cell nmos_5p04310591302011_512x8m81
+ Generating output for cell nmos_5p0431059130207_512x8m81
+ Generating output for cell nmos_1p2$$46884908_512x8m81
+ Generating output for cell nmos_5p0431059130205_512x8m81
+ Generating output for cell nmos_1p2$$46883884_512x8m81
+ Generating output for cell nmos_1p2$$46563372_512x8m81
+ Generating output for cell M3_M2$$46895148_512x8m81
+ Generating output for cell M3_M2$$43368492_R90_512x8m81
+ Generating output for cell M2_M1$$43375660_R90_512x8m81
+ Generating output for cell M1_PSUB$$46893100_512x8m81
+ Generating output for cell M1_PSUB$$46892076_512x8m81
+ Generating output for cell M1_NWELL08_512x8m81
+ Generating output for cell din_512x8m81
+ Generating output for cell M3_M24310591302026_512x8m81
+ Generating output for cell M3_M2$$44741676_512x8m81
+ Generating output for cell M3_M2$$43370540_512x8m81
+ Generating output for cell M2_M14310591302025_512x8m81
+ Generating output for cell M2_M1$$45013036_512x8m81
+ Generating output for cell M2_M1$$45012012_512x8m81
+ Generating output for cell M1_NACTIVE4310591302024_512x8m81
+ Generating output for cell saout_m2_512x8m81
+ Generating output for cell saout_R_m2_512x8m81
+ Generating output for cell via2_R90_512x8m81_0
+ Generating output for cell via1_x2_R90_512x8m81_0
+ Generating output for cell via1_R270_512x8m81_0
+ Generating output for cell via1_R90_512x8m81_0
+ Generating output for cell via1_2_512x8m81_0
+ Generating output for cell M3_M2$$43368492_512x8m81_0
+ Generating output for cell M2_M1$$46894124_512x8m81_0
+ Generating output for cell M1_PSUB$$45111340_512x8m81_0
+ Generating output for cell M1_PACTIVE4310591302075_512x8m81
+ Generating output for cell M1_NWELL$$47121452_512x8m81
+ Generating output for cell M1_NWELL$$46277676_512x8m81
+ Generating output for cell ypass_gate_512x8m81_0
+ Generating output for cell via2_x2_R270_512x8m81_0
+ Generating output for cell via1_x2_R270_512x8m81_0
+ Generating output for cell via1_2_x2_R270_512x8m81_0
+ Generating output for cell via2_x2_R90_512x8m81_0
+ Generating output for cell via1_2_x2_R90_512x8m81_0
+ Generating output for cell via1_2_x2_512x8m81_0
+ Generating output for cell pmos_5p04310591302097_512x8m81
+ Generating output for cell pmos_5p04310591302095_512x8m81
+ Generating output for cell nmos_5p04310591302098_512x8m81
+ Generating output for cell nmos_5p04310591302096_512x8m81
+ Generating output for cell M2_M1$$47117356_512x8m81
+ Generating output for cell M2_M1$$43375660_512x8m81
+ Generating output for cell M1_PSUB$$46274604_512x8m81
+ Generating output for cell M1_POLY2$$46559276_512x8m81_0
+ Generating output for cell M1_NWELL$$44998700_512x8m81
+ Generating output for cell 018SRAM_strap1_bndry_512x8m81
+ Generating output for cell M3_M24310591302021_512x8m81
+ Generating output for cell 018SRAM_strap1_512x8m81
+ Generating output for cell 018SRAM_cell1_dummy_R_512x8m81
+ Generating output for cell 018SRAM_cell1_dummy_512x8m81
+ Generating output for cell 018SRAM_cell1_512x8m81
+ Generating output for cell 018SRAM_cell1_2x_512x8m81
+ Generating output for cell rdummy_512x4_512x8m81
+ Generating output for cell 018SRAM_strap1_2x_512x8m81
+ Generating output for cell rarray4_512_512x8m81
+ Generating output for cell dcap_103_novia_512x8m81
+ Generating output for cell M3_M24310591302023_512x8m81
+ Generating output for cell M3_M24310591302022_512x8m81
+ Generating output for cell M3_M2$$201416748_512x8m81
+ Generating output for cell rcol4_512_512x8m81
+ Generating output for cell M3_M243105913020102_512x8m81
+ Generating output for cell M3_M24310591302095_512x8m81
+ Generating output for cell M2_M14310591302097_512x8m81
+ Generating output for cell power_route_07_512x8m81
+ Generating output for cell M3_M243105913020101_512x8m81
+ Generating output for cell M3_M243105913020100_512x8m81
+ Generating output for cell M3_M24310591302099_512x8m81
+ Generating output for cell M3_M24310591302098_512x8m81
+ Generating output for cell power_route_06_512x8m81
+ Generating output for cell M3_M24310591302096_512x8m81
+ Generating output for cell power_route_05_512x8m81
+ Generating output for cell M3_M24310591302094_512x8m81
+ Generating output for cell M3_M24310591302091_512x8m81
+ Generating output for cell M3_M24310591302090_512x8m81
+ Generating output for cell M3_M24310591302089_512x8m81
+ Generating output for cell M3_M24310591302088_512x8m81
+ Generating output for cell M3_M24310591302086_512x8m81
+ Generating output for cell M3_M24310591302085_512x8m81
+ Generating output for cell M3_M24310591302084_512x8m81
+ Generating output for cell M3_M24310591302083_512x8m81
+ Generating output for cell M3_M24310591302082_512x8m81
+ Generating output for cell M3_M24310591302042_512x8m81
+ Generating output for cell M2_M14310591302093_512x8m81
+ Generating output for cell M2_M14310591302092_512x8m81
+ Generating output for cell M2_M14310591302087_512x8m81
+ Generating output for cell M2_M14310591302081_512x8m81
+ Generating output for cell M2_M14310591302080_512x8m81
+ Generating output for cell power_route_04_512x8m81
+ Generating output for cell power_route_02_b_512x8m81
+ Generating output for cell power_route_02_a_512x8m81
+ Generating output for cell M3_M24310591302016_512x8m81
+ Generating output for cell M2_M14310591302017_512x8m81
+ Generating output for cell power_route_01_512x8m81
+ Generating output for cell M3_M2431059130206_512x8m81
+ Generating output for cell M2_M14310591302012_512x8m81
+ Generating output for cell power_route_512x8m81
+ Generating output for cell power_route_01_c_512x8m81
+ Generating output for cell power_route_01_b_512x8m81
+ Generating output for cell power_route_01_a_512x8m81
+ Generating output for cell M3_M243105913020104_512x8m81
+ Generating output for cell M2_M143105913020103_512x8m81
+ Generating output for cell power_a_512x8m81
+ Generating output for cell M3_M2431059130205_512x8m81
+ Generating output for cell m2m3_512x8m81
+ Generating output for cell new_dummyrowunit01_512x8m81
+ Generating output for cell new_dummyrow_unit_512x8m81
+ Generating output for cell 018SRAM_cell1_cutPC_512x8m81
+ Generating output for cell array16_512_dummy_01_512x8m81
+ Generating output for cell ldummy_512x4_512x8m81
+ Generating output for cell 018SRAM_strap1_2x_bndry_512x8m81
+ Generating output for cell Cell_array8x8_512x8m81
+ Generating output for cell col_512a_512x8m81
+ Generating output for cell lcol4_512_512x8m81
+ Generating output for cell pmos_5p04310591302055_512x8m81
+ Generating output for cell nmos_5p04310591302054_512x8m81
+ Generating output for cell M3_M24310591302053_512x8m81
+ Generating output for cell M2_M14310591302056_512x8m81
+ Generating output for cell M2_M14310591302055_512x8m81
+ Generating output for cell M2_M14310591302054_512x8m81
+ Generating output for cell M2_M14310591302052_512x8m81
+ Generating output for cell ypredec1_ys_512x8m81
+ Generating output for cell pmos_5p04310591302060_512x8m81
+ Generating output for cell pmos_1p2$$47821868_512x8m81
+ Generating output for cell pmos_5p04310591302061_512x8m81
+ Generating output for cell pmos_1p2$$47820844_512x8m81
+ Generating output for cell M3_M2$$47819820_512x8m81
+ Generating output for cell M3_M2$$47333420_512x8m81
+ Generating output for cell M3_M2$$47332396_512x8m81
+ Generating output for cell M3_M2$$47108140_512x8m81
+ Generating output for cell M2_M1$$47515692_512x8m81
+ Generating output for cell M2_M1$$43380780_512x8m81
+ Generating output for cell M2_M1$$43379756_512x8m81
+ Generating output for cell M2_M1$$43378732_512x8m81
+ Generating output for cell ypredec1_xa_512x8m81
+ Generating output for cell M3_M24310591302058_512x8m81
+ Generating output for cell M2_M14310591302057_512x8m81
+ Generating output for cell ypredec1_xax8_512x8m81
+ Generating output for cell nmos_5p04310591302057_512x8m81
+ Generating output for cell nmos_1p2$$47514668_512x8m81
+ Generating output for cell pmos_1p2_161_512x8m81
+ Generating output for cell pmos_1p2_160_512x8m81
+ Generating output for cell pmos_5p04310591302058_512x8m81
+ Generating output for cell pmos_1p2$$47331372_512x8m81
+ Generating output for cell nmos_1p2_157_512x8m81
+ Generating output for cell nmos_5p04310591302059_512x8m81
+ Generating output for cell nmos_1p2$$47329324_512x8m81
+ Generating output for cell M3_M2$$47333420_150_512x8m81
+ Generating output for cell M3_M2$$47108140_149_512x8m81
+ Generating output for cell M3_M2$$43368492_151_512x8m81
+ Generating output for cell M2_M1_154_512x8m81
+ Generating output for cell M2_M1$$43380780_152_512x8m81
+ Generating output for cell M2_M1$$43379756_153_512x8m81
+ Generating output for cell M1_PSUB$$45110316_512x8m81
+ Generating output for cell M1_POLY2_155_512x8m81
+ Generating output for cell alatch_512x8m81
+ Generating output for cell M3_M2$$47334444_512x8m81
+ Generating output for cell M3_M2$$43368492_512x8m81
+ Generating output for cell M2_M1$$43377708_512x8m81
+ Generating output for cell M2_M1$$34864172_512x8m81
+ Generating output for cell M1_PSUB$$47818796_512x8m81
+ Generating output for cell M1_POLY2$$46559276_512x8m81
+ Generating output for cell M1_NWELL14_512x8m81
+ Generating output for cell ypredec1_bot_512x8m81
+ Generating output for cell pmos_5p04310591302062_512x8m81
+ Generating output for cell pmos_1p2$$47109164_512x8m81
+ Generating output for cell nmos_5p04310591302056_512x8m81
+ Generating output for cell nmos_5p04310591302053_512x8m81
+ Generating output for cell nmos_1p2$$47342636_512x8m81
+ Generating output for cell M3_M2$$47633452_512x8m81
+ Generating output for cell M3_M2$$47632428_512x8m81
+ Generating output for cell M3_M2$$43368492_R270_512x8m81
+ Generating output for cell M2_M14310591302051_512x8m81
+ Generating output for cell M2_M1$$47631404_512x8m81
+ Generating output for cell M2_M1$$47630380_512x8m81
+ Generating output for cell M1_PSUB$$47114284_512x8m81
+ Generating output for cell M1_NWELL13_512x8m81
+ Generating output for cell M1_NWELL12_512x8m81
+ Generating output for cell ypredec1_512x8m81
+ Generating output for cell pmos_5p04310591302068_512x8m81
+ Generating output for cell pmos_1p2$$47513644_512x8m81
+ Generating output for cell pmos_5p04310591302072_512x8m81
+ Generating output for cell pmos_1p2$$47512620_512x8m81
+ Generating output for cell M2_M1$$47327276_512x8m81
+ Generating output for cell M2_M1$$43376684_512x8m81
+ Generating output for cell M1_POLY24310591302060_512x8m81
+ Generating output for cell xpredec1_xa_512x8m81
+ Generating output for cell pmos_5p04310591302070_512x8m81
+ Generating output for cell pmos_1p2$$47337516_512x8m81
+ Generating output for cell nmos_5p04310591302071_512x8m81
+ Generating output for cell nmos_1p2$$47336492_512x8m81
+ Generating output for cell M1_PSUB$$47335468_512x8m81
+ Generating output for cell M1_NWELL10_512x8m81
+ Generating output for cell xpredec1_bot_512x8m81
+ Generating output for cell M1_POLY2_R270_512x8m81
+ Generating output for cell xpredec1_512x8m81
+ Generating output for cell pmos_5p04310591302067_512x8m81
+ Generating output for cell pmos_1p2$$47643692_512x8m81
+ Generating output for cell pmos_1p2$$47642668_512x8m81
+ Generating output for cell nmos_1p2$$47641644_512x8m81
+ Generating output for cell M3_M2$$47644716_512x8m81
+ Generating output for cell M2_M1$$47640620_512x8m81
+ Generating output for cell M2_M1$$47500332_512x8m81
+ Generating output for cell M1_POLY24310591302059_512x8m81
+ Generating output for cell xpredec0_xa_512x8m81
+ Generating output for cell pmos_5p04310591302063_512x8m81
+ Generating output for cell pmos_1p2$$47504428_512x8m81
+ Generating output for cell pmos_5p04310591302064_512x8m81
+ Generating output for cell pmos_1p2$$47503404_512x8m81
+ Generating output for cell nmos_5p04310591302066_512x8m81
+ Generating output for cell nmos_5p04310591302065_512x8m81
+ Generating output for cell nmos_1p2$$47502380_512x8m81
+ Generating output for cell M3_M2$$47645740_512x8m81
+ Generating output for cell M1_NWELL11_512x8m81
+ Generating output for cell xpredec0_bot_512x8m81
+ Generating output for cell pmos_5p04310591302069_512x8m81
+ Generating output for cell M1_PACTIVE_02_512x8m81
+ Generating output for cell xpredec0_512x8m81
+ Generating output for cell M3_M2$$201412652_512x8m81
+ Generating output for cell M3_M2$$47115308_512x8m81
+ Generating output for cell prexdec_top_512x8m81
+ Generating output for cell pmos_5p04310591302082_512x8m81
+ Generating output for cell pmos_5p04310591302080_512x8m81
+ Generating output for cell pmos_5p04310591302079_512x8m81
+ Generating output for cell pmos_5p04310591302077_512x8m81
+ Generating output for cell nmos_5p04310591302081_512x8m81
+ Generating output for cell nmos_5p04310591302078_512x8m81
+ Generating output for cell nmos_5p04310591302076_512x8m81
+ Generating output for cell nmos_5p04310591302075_512x8m81
+ Generating output for cell M3_M24310591302072_512x8m81
+ Generating output for cell M3_M24310591302050_512x8m81
+ Generating output for cell M3_M2$$201255980_512x8m81
+ Generating output for cell M2_M14310591302074_512x8m81
+ Generating output for cell M2_M14310591302073_512x8m81
+ Generating output for cell M1_PACTIVE4310591302071_512x8m81
+ Generating output for cell M1_PACTIVE4310591302069_512x8m81
+ Generating output for cell M1_NACTIVE4310591302070_512x8m81
+ Generating output for cell wen_v2_512x8m81
+ Generating output for cell pmos_5p04310591302094_512x8m81
+ Generating output for cell pmos_5p04310591302092_512x8m81
+ Generating output for cell pmos_5p04310591302089_512x8m81
+ Generating output for cell pmos_5p04310591302088_512x8m81
+ Generating output for cell pmos_5p04310591302074_512x8m81
+ Generating output for cell pmos_5p04310591302091_512x8m81
+ Generating output for cell pmos_1p2$$48624684_512x8m81
+ Generating output for cell pmos_5p04310591302073_512x8m81
+ Generating output for cell pmos_1p2$$48623660_512x8m81
+ Generating output for cell pmos_5p04310591302087_512x8m81
+ Generating output for cell pmos_1p2$$47815724_512x8m81
+ Generating output for cell pmos_1p2$$47330348_512x8m81
+ Generating output for cell nmos_5p04310591302093_512x8m81
+ Generating output for cell nmos_5p04310591302090_512x8m81
+ Generating output for cell nmos_5p04310591302083_512x8m81
+ Generating output for cell nmos_1p2$$48629804_512x8m81
+ Generating output for cell nmos_5p04310591302084_512x8m81
+ Generating output for cell nmos_1p2$$48308268_512x8m81
+ Generating output for cell nmos_5p04310591302085_512x8m81
+ Generating output for cell nmos_1p2$$48306220_512x8m81
+ Generating output for cell nmos_5p04310591302086_512x8m81
+ Generating output for cell nmos_1p2$$48302124_512x8m81
+ Generating output for cell M3_M24310591302064_512x8m81
+ Generating output for cell M3_M2$$169756716_512x8m81
+ Generating output for cell M3_M2$$169755692_512x8m81
+ Generating output for cell M3_M2$$169753644_512x8m81
+ Generating output for cell M3_M2$$48231468_512x8m81
+ Generating output for cell M3_M2$$48229420_512x8m81
+ Generating output for cell M3_M2$$48228396_512x8m81
+ Generating output for cell M3_M2$$48227372_512x8m81
+ Generating output for cell M3_M2$$48066604_512x8m81
+ Generating output for cell M2_M14310591302065_512x8m81
+ Generating output for cell M2_M1_01_R270_512x8m81
+ Generating output for cell M2_M1$$199746604_512x8m81
+ Generating output for cell M2_M1$$170064940_512x8m81
+ Generating output for cell M2_M1$$170063916_512x8m81
+ Generating output for cell M2_M1$$170061868_512x8m81
+ Generating output for cell M2_M1$$168351788_512x8m81
+ Generating output for cell M2_M1$$48316460_512x8m81
+ Generating output for cell M2_M1$$48224300_512x8m81
+ Generating output for cell M2_M1$$48222252_512x8m81
+ Generating output for cell M2_M1$$48221228_512x8m81
+ Generating output for cell M2_M1$$48220204_512x8m81
+ Generating output for cell M2_M1$$48219180_512x8m81
+ Generating output for cell M2_M1$$48218156_512x8m81
+ Generating output for cell M2_M1$$48217132_512x8m81
+ Generating output for cell M2_M1$$34864172_R90_512x8m81
+ Generating output for cell M1_PSUB_03_R90_512x8m81
+ Generating output for cell M1_PSUB_03_512x8m81
+ Generating output for cell M1_PSUB_02_R90_512x8m81
+ Generating output for cell M1_PSUB$$48312364_512x8m81
+ Generating output for cell M1_POLY24310591302067_512x8m81
+ Generating output for cell M1_POLY24310591302066_512x8m81
+ Generating output for cell M1_POLY24310591302062_512x8m81
+ Generating output for cell M1_POLY24310591302061_512x8m81
+ Generating output for cell M1_PACTIVE_03_R90_512x8m81
+ Generating output for cell M1_PACTIVE_02_R90_512x8m81
+ Generating output for cell M1_PACTIVE_01_R90_512x8m81
+ Generating output for cell M1_PACTIVE4310591302068_512x8m81
+ Generating output for cell M1_PACTIVE06_512x8m81
+ Generating output for cell M1_PACTIVE02_512x8m81
+ Generating output for cell M1_PACTIVE01_512x8m81
+ Generating output for cell M1_NWELL_03_R90_512x8m81
+ Generating output for cell M1_NWELL_02_R90_512x8m81
+ Generating output for cell M1_NWELL17_512x8m81
+ Generating output for cell M1_NWELL16_512x8m81
+ Generating output for cell M1_NWELL01_512x8m81
+ Generating output for cell M1_NACTIVE4310591302063_512x8m81
+ Generating output for cell CON_512x8m81
+ Generating output for cell gen_512x8_512x8m81
+ Generating output for cell M3_M2$$201401388_512x8m81
+ Generating output for cell M2_M1$$202405932_512x8m81
+ Generating output for cell M1_PACTIVE4310591302049_512x8m81
+ Generating output for cell M1_PACTIVE4310591302048_512x8m81
+ Generating output for cell M1_NACTIVE4310591302047_512x8m81
+ Generating output for cell control_512x8_512x8m81
+ Generating output for cell M3_M24310591302015_512x8m81
+ Generating output for cell M3_M24310591302013_512x8m81
+ Generating output for cell M3_M24310591302011_512x8m81
+ Generating output for cell M3_M2431059130209_512x8m81
+ Generating output for cell M3_M2431059130202_512x8m81
+ Generating output for cell M3_M2$$201415724_512x8m81
+ Generating output for cell M3_M2$$201414700_512x8m81
+ Generating output for cell M3_M2$$201413676_512x8m81
+ Generating output for cell M3_M2$$201258028_512x8m81
+ Generating output for cell M3_M2$$201254956_512x8m81
+ Generating output for cell M3_M2$$201253932_512x8m81
+ Generating output for cell M3_M2$$201250860_512x8m81
+ Generating output for cell M3_M2$$201249836_512x8m81
+ Generating output for cell M3_M2$$201248812_512x8m81
+ Generating output for cell M2_M1431059130204_512x8m81
+ Generating output for cell M2_M1431059130203_512x8m81
+ Generating output for cell M2_M1$$201261100_512x8m81
+ Generating output for cell M2_M1$$201260076_512x8m81
+ Generating output for cell M2_M1$$199747628_512x8m81
+ Generating output for cell M1_PSUB4310591302014_512x8m81
+ Generating output for cell M1_PSUB4310591302010_512x8m81
+ Generating output for cell M1_PSUB4310591302046_512x8m81
+ Generating output for cell M1_PSUB4310591302045_512x8m81
+ Generating output for cell M1_PSUB4310591302044_512x8m81
+ Generating output for cell M1_PSUB4310591302043_512x8m81
+ Generating output for cell G_ring_512x8m81
+ Generating output for cell GF018_512x8M8WM1_lef_512x8m81
+ Generating output for cell M3_M24310591302079_512x8m81
+ Generating output for cell M3_M24310591302078_512x8m81
+ Generating output for cell M3_M24310591302077_512x8m81
+ Generating output for cell M2_M14310591302076_512x8m81
+ Generating output for cell 512x8M8W_PWR_512x8m81
+ Generating output for cell gf180mcu_fd_ip_sram__sram512x8m8wm1
+ Generating output for cell gf180_ram_512x8_wrapper
+ Generating output for cell gf180mcu_fd_sc_mcu7t5v0__nand2_2
+ Generating output for cell gf180mcu_fd_sc_mcu7t5v0__dffrsnq_2
+ Generating output for cell gf180mcu_fd_sc_mcu7t5v0__inv_12
+ Generating output for cell spare_logic_block
+ Generating output for cell user_id_programming
+ Generating output for cell gf180mcu_fd_sc_mcu7t5v0__buf_12
+ Generating output for cell gf180mcu_fd_sc_mcu7t5v0__clkbuf_20
+ Generating output for cell gf180mcu_fd_sc_mcu7t5v0__buf_16
+ Generating output for cell gf180mcu_fd_sc_mcu7t5v0__buf_20
+ Generating output for cell gf180mcu_fd_sc_mcu7t5v0__invz_1
+ Generating output for cell gf180mcu_fd_sc_mcu7t5v0__invz_4
+ Generating output for cell gf180mcu_fd_sc_mcu7t5v0__invz_8
+ Generating output for cell gf180mcu_fd_sc_mcu7t5v0__invz_2
+ Generating output for cell gf180mcu_fd_sc_mcu7t5v0__dffrsnq_1
+ Generating output for cell gf180mcu_fd_sc_mcu7t5v0__dffnrnq_2
+ Generating output for cell gf180mcu_fd_sc_mcu7t5v0__dffrsnq_4
+ Generating output for cell gf180mcu_fd_sc_mcu7t5v0__dffq_2
+ Generating output for cell gf180mcu_fd_sc_mcu7t5v0__dffq_4
+ Generating output for cell gf180mcu_fd_sc_mcu7t5v0__dffnsnq_4
+ Generating output for cell gf180mcu_fd_sc_mcu7t5v0__dffnrnq_4
+ Generating output for cell gf180mcu_fd_sc_mcu7t5v0__dffnsnq_2
+ Generating output for cell gf180mcu_fd_sc_mcu7t5v0__xor3_1
+ Generating output for cell gf180mcu_fd_sc_mcu7t5v0__xnor3_1
+ Generating output for cell gf180mcu_fd_sc_mcu7t5v0__oai33_4
+ Generating output for cell gf180mcu_fd_sc_mcu7t5v0__xor3_2
+ Generating output for cell gf180mcu_fd_sc_mcu7t5v0__xnor2_4
+ Generating output for cell gf180mcu_fd_sc_mcu7t5v0__clkinv_12
+ Generating output for cell gf180mcu_fd_sc_mcu7t5v0__clkinv_16
+ Generating output for cell gf180mcu_fd_sc_mcu7t5v0__xnor3_2
+ Generating output for cell gf180mcu_fd_sc_mcu7t5v0__inv_8
+ Generating output for cell gf180mcu_fd_sc_mcu7t5v0__inv_16
+ Generating output for cell caravel_core
+ Generating output for cell font_76
+ Generating output for cell font_75
+ Generating output for cell font_72
+ Generating output for cell font_70
+ Generating output for cell font_66
+ Generating output for cell font_64
+ Generating output for cell font_63
+ Generating output for cell font_62
+ Generating output for cell font_50
+ Generating output for cell font_47
+ Generating output for cell font_46
+ Generating output for cell font_45
+ Generating output for cell font_44
+ Generating output for cell font_32
+ Generating output for cell font_30
+ Generating output for cell font_29
+ Generating output for cell font_28
+ Generating output for cell font_6F
+ Generating output for cell font_4B
+ Generating output for cell font_2D
+ Generating output for cell copyright_block
+ Generating output for cell open_source
+ Generating output for cell M5_M4_CDNS_406619531451
+ Generating output for cell M5_M4_CDNS_406619531450
+ Generating output for cell M4_M3_CDNS_406619531453
+ Generating output for cell M4_M3_CDNS_406619531452
+ Generating output for cell POLY_SUB_FILL_1
+ Generating output for cell M3_M2_CDNS_4066195314510
+ Generating output for cell M3_M2_CDNS_406619531459
+ Generating output for cell M3_M2_CDNS_406619531457
+ Generating output for cell M3_M2_CDNS_406619531456
+ Generating output for cell M2_M1_CDNS_406619531454
+ Generating output for cell M1_PSUB_CDNS_406619531458
+ Generating output for cell M1_PSUB_CDNS_406619531455
+ Generating output for cell GF_NI_FILL10_1
+ Generating output for cell GF_NI_FILL10_0
+ Generating output for cell gf180mcu_fd_io__fill10
+ Generating output for cell M5_M4_CDNS_40661953145532
+ Generating output for cell M5_M4_CDNS_40661953145531
+ Generating output for cell M5_M4_CDNS_40661953145530
+ Generating output for cell M5_M4_CDNS_40661953145505
+ Generating output for cell M5_M4_CDNS_40661953145504
+ Generating output for cell M5_M4_CDNS_40661953145503
+ Generating output for cell M5_M4_CDNS_40661953145493
+ Generating output for cell M5_M4_CDNS_40661953145506
+ Generating output for cell M5_M4_CDNS_40661953145507
+ Generating output for cell M5_M4_CDNS_40661953145508
+ Generating output for cell M5_M4_CDNS_40661953145509
+ Generating output for cell M5_M4_CDNS_40661953145510
+ Generating output for cell M5_M4_CDNS_40661953145511
+ Generating output for cell M5_M4_CDNS_40661953145512
+ Generating output for cell M5_M4_CDNS_40661953145513
+ Generating output for cell M5_M4_CDNS_40661953145514
+ Generating output for cell M5_M4_CDNS_40661953145515
+ Generating output for cell M5_M4_CDNS_40661953145516
+ Generating output for cell M5_M4_CDNS_40661953145501
+ Generating output for cell M5_M4_CDNS_40661953145517
+ Generating output for cell M5_M4_CDNS_40661953145518
+ Generating output for cell M5_M4_CDNS_40661953145519
+ Generating output for cell M5_M4_CDNS_40661953145495
+ Generating output for cell M5_M4_CDNS_40661953145496
+ Generating output for cell M5_M4_CDNS_40661953145441
+ Generating output for cell M5_M4_CDNS_40661953145462
+ Generating output for cell M5_M4_CDNS_40661953145468
+ Generating output for cell M5_M4_CDNS_40661953145469
+ Generating output for cell M5_M4_CDNS_40661953145470
+ Generating output for cell M5_M4_CDNS_40661953145484
+ Generating output for cell M5_M4_CDNS_40661953145485
+ Generating output for cell M5_M4_CDNS_40661953145460
+ Generating output for cell M5_M4_CDNS_40661953145443
+ Generating output for cell M5_M4_CDNS_40661953145487
+ Generating output for cell M5_M4_CDNS_40661953145459
+ Generating output for cell M5_M4_CDNS_40661953145456
+ Generating output for cell M5_M4_CDNS_40661953145454
+ Generating output for cell M5_M4_CDNS_40661953145497
+ Generating output for cell M5_M4_CDNS_40661953145498
+ Generating output for cell M5_M4_CDNS_40661953145499
+ Generating output for cell M5_M4_CDNS_40661953145500
+ Generating output for cell M5_M4_CDNS_40661953145533
+ Generating output for cell M5_M4_CDNS_40661953145534
+ Generating output for cell M5_M4_CDNS_40661953145535
+ Generating output for cell M5_M4_CDNS_40661953145536
+ Generating output for cell M5_M4_CDNS_40661953145537
+ Generating output for cell M5_M4_CDNS_40661953145538
+ Generating output for cell M5_M4_CDNS_40661953145539
+ Generating output for cell M5_M4_CDNS_40661953145540
+ Generating output for cell M5_M4_CDNS_40661953145541
+ Generating output for cell M5_M4_CDNS_40661953145458
+ Generating output for cell M5_M4_CDNS_40661953145440
+ Generating output for cell M5_M4_CDNS_40661953145463
+ Generating output for cell M5_M4_CDNS_40661953145415
+ Generating output for cell M5_M4_CDNS_40661953145461
+ Generating output for cell M5_M4_CDNS_40661953145444
+ Generating output for cell M5_M4_CDNS_40661953145457
+ Generating output for cell M5_M4_CDNS_40661953145488
+ Generating output for cell M5_M4_CDNS_40661953145486
+ Generating output for cell M5_M4_CDNS_40661953145448
+ Generating output for cell M5_M4_CDNS_40661953145452
+ Generating output for cell M5_M4_CDNS_40661953145525
+ Generating output for cell M5_M4_CDNS_40661953145524
+ Generating output for cell M5_M4_CDNS_40661953145523
+ Generating output for cell M5_M4_CDNS_40661953145522
+ Generating output for cell M5_M4_CDNS_40661953145521
+ Generating output for cell M5_M4_CDNS_40661953145520
+ Generating output for cell M5_M4_CDNS_40661953145502
+ Generating output for cell M5_M4_CDNS_40661953145483
+ Generating output for cell M5_M4_CDNS_40661953145482
+ Generating output for cell M5_M4_CDNS_40661953145480
+ Generating output for cell M5_M4_CDNS_40661953145479
+ Generating output for cell M5_M4_CDNS_40661953145467
+ Generating output for cell M5_M4_CDNS_40661953145450
+ Generating output for cell M5_M4_CDNS_40661953145478
+ Generating output for cell M5_M4_CDNS_40661953145477
+ Generating output for cell M5_M4_CDNS_40661953145476
+ Generating output for cell M5_M4_CDNS_40661953145475
+ Generating output for cell M5_M4_CDNS_40661953145474
+ Generating output for cell M5_M4_CDNS_40661953145473
+ Generating output for cell M5_M4_CDNS_40661953145494
+ Generating output for cell M5_M4_CDNS_40661953145472
+ Generating output for cell M5_M4_CDNS_40661953145471
+ Generating output for cell M5_M4_CDNS_40661953145436
+ Generating output for cell M5_M4_CDNS_40661953145529
+ Generating output for cell M5_M4_CDNS_40661953145528
+ Generating output for cell M5_M4_CDNS_40661953145527
+ Generating output for cell M5_M4_CDNS_40661953145526
+ Generating output for cell M5_M4_CDNS_40661953145481
+ Generating output for cell M5_M4_CDNS_40661953145446
+ Generating output for cell M5_M4_CDNS_40661953145445
+ Generating output for cell M5_M4_CDNS_40661953145442
+ Generating output for cell M5_M4_CDNS_40661953145425
+ Generating output for cell M5_M4_CDNS_40661953145435
+ Generating output for cell M5_M4_CDNS_40661953145433
+ Generating output for cell M5_M4_CDNS_40661953145434
+ Generating output for cell M5_M4_CDNS_40661953145455
+ Generating output for cell M5_M4_CDNS_40661953145432
+ Generating output for cell M5_M4_CDNS_40661953145430
+ Generating output for cell M5_M4_CDNS_40661953145431
+ Generating output for cell M5_M4_CDNS_40661953145451
+ Generating output for cell M5_M4_CDNS_40661953145429
+ Generating output for cell M5_M4_CDNS_40661953145453
+ Generating output for cell M5_M4_CDNS_40661953145439
+ Generating output for cell M5_M4_CDNS_40661953145427
+ Generating output for cell M5_M4_CDNS_40661953145492
+ Generating output for cell M5_M4_CDNS_40661953145449
+ Generating output for cell M5_M4_CDNS_40661953145447
+ Generating output for cell M5_M4_CDNS_40661953145417
+ Generating output for cell M5_M4_CDNS_40661953145423
+ Generating output for cell M5_M4_CDNS_40661953145419
+ Generating output for cell M5_M4_CDNS_40661953145428
+ Generating output for cell M5_M4_CDNS_40661953145438
+ Generating output for cell M5_M4_CDNS_40661953145416
+ Generating output for cell polygon00035
+ Generating output for cell polygon00036
+ Generating output for cell M5_M4_CDNS_40661953145422
+ Generating output for cell M5_M4_CDNS_40661953145421
+ Generating output for cell M5_M4_CDNS_40661953145420
+ Generating output for cell M5_M4_CDNS_40661953145437
+ Generating output for cell polygon00032
+ Generating output for cell polygon00033
+ Generating output for cell polygon00034
+ Generating output for cell M5_M4_CDNS_40661953145491
+ Generating output for cell M5_M4_CDNS_40661953145490
+ Generating output for cell M5_M4_CDNS_40661953145489
+ Generating output for cell M5_M4_CDNS_40661953145466
+ Generating output for cell M5_M4_CDNS_40661953145465
+ Generating output for cell M5_M4_CDNS_40661953145464
+ Generating output for cell M5_M4_CDNS_40661953145426
+ Generating output for cell M5_M4_CDNS_40661953145424
+ Generating output for cell M5_M4_CDNS_40661953145418
+ Generating output for cell M4_M3_CDNS_40661953145615
+ Generating output for cell M4_M3_CDNS_40661953145614
+ Generating output for cell M4_M3_CDNS_40661953145554
+ Generating output for cell M4_M3_CDNS_40661953145551
+ Generating output for cell M4_M3_CDNS_40661953145550
+ Generating output for cell M4_M3_CDNS_40661953145549
+ Generating output for cell M4_M3_CDNS_40661953145548
+ Generating output for cell M4_M3_CDNS_40661953145610
+ Generating output for cell M4_M3_CDNS_40661953145611
+ Generating output for cell M4_M3_CDNS_40661953145612
+ Generating output for cell M4_M3_CDNS_40661953145613
+ Generating output for cell M4_M3_CDNS_40661953145606
+ Generating output for cell M4_M3_CDNS_40661953145607
+ Generating output for cell M4_M3_CDNS_40661953145608
+ Generating output for cell M4_M3_CDNS_40661953145609
+ Generating output for cell M4_M3_CDNS_40661953145603
+ Generating output for cell M4_M3_CDNS_40661953145604
+ Generating output for cell M4_M3_CDNS_40661953145605
+ Generating output for cell M4_M3_CDNS_40661953145599
+ Generating output for cell M4_M3_CDNS_40661953145600
+ Generating output for cell M4_M3_CDNS_40661953145601
+ Generating output for cell M4_M3_CDNS_40661953145602
+ Generating output for cell M4_M3_CDNS_40661953145552
+ Generating output for cell M4_M3_CDNS_40661953145598
+ Generating output for cell M4_M3_CDNS_40661953145571
+ Generating output for cell M4_M3_CDNS_40661953145573
+ Generating output for cell M4_M3_CDNS_40661953145580
+ Generating output for cell M4_M3_CDNS_40661953145581
+ Generating output for cell M4_M3_CDNS_40661953145584
+ Generating output for cell M4_M3_CDNS_40661953145585
+ Generating output for cell M4_M3_CDNS_40661953145579
+ Generating output for cell M4_M3_CDNS_40661953145586
+ Generating output for cell M4_M3_CDNS_40661953145578
+ Generating output for cell M4_M3_CDNS_40661953145588
+ Generating output for cell M4_M3_CDNS_40661953145590
+ Generating output for cell M4_M3_CDNS_40661953145592
+ Generating output for cell M4_M3_CDNS_40661953145546
+ Generating output for cell M4_M3_CDNS_40661953145544
+ Generating output for cell M4_M3_CDNS_40661953145555
+ Generating output for cell M4_M3_CDNS_40661953145561
+ Generating output for cell M4_M3_CDNS_40661953145593
+ Generating output for cell M4_M3_CDNS_40661953145594
+ Generating output for cell M4_M3_CDNS_40661953145595
+ Generating output for cell M4_M3_CDNS_40661953145596
+ Generating output for cell M4_M3_CDNS_40661953145597
+ Generating output for cell M4_M3_CDNS_40661953145616
+ Generating output for cell M4_M3_CDNS_40661953145646
+ Generating output for cell M4_M3_CDNS_40661953145647
+ Generating output for cell M4_M3_CDNS_40661953145648
+ Generating output for cell M4_M3_CDNS_40661953145649
+ Generating output for cell M4_M3_CDNS_40661953145583
+ Generating output for cell M4_M3_CDNS_40661953145582
+ Generating output for cell M4_M3_CDNS_40661953145572
+ Generating output for cell M4_M3_CDNS_40661953145574
+ Generating output for cell M4_M3_CDNS_40661953145587
+ Generating output for cell M4_M3_CDNS_40661953145589
+ Generating output for cell M4_M3_CDNS_40661953145591
+ Generating output for cell M4_M3_CDNS_40661953145556
+ Generating output for cell M4_M3_CDNS_40661953145543
+ Generating output for cell M4_M3_CDNS_40661953145558
+ Generating output for cell M4_M3_CDNS_40661953145542
+ Generating output for cell M4_M3_CDNS_40661953145650
+ Generating output for cell M4_M3_CDNS_40661953145570
+ Generating output for cell M4_M3_CDNS_40661953145569
+ Generating output for cell M4_M3_CDNS_40661953145568
+ Generating output for cell M4_M3_CDNS_40661953145567
+ Generating output for cell M4_M3_CDNS_40661953145566
+ Generating output for cell M4_M3_CDNS_40661953145656
+ Generating output for cell M4_M3_CDNS_40661953145655
+ Generating output for cell M4_M3_CDNS_40661953145654
+ Generating output for cell M4_M3_CDNS_40661953145653
+ Generating output for cell M4_M3_CDNS_40661953145652
+ Generating output for cell M4_M3_CDNS_40661953145651
+ Generating output for cell M4_M3_CDNS_40661953145617
+ Generating output for cell M4_M3_CDNS_40661953145662
+ Generating output for cell M4_M3_CDNS_40661953145661
+ Generating output for cell M4_M3_CDNS_40661953145660
+ Generating output for cell M4_M3_CDNS_40661953145659
+ Generating output for cell M4_M3_CDNS_40661953145658
+ Generating output for cell M4_M3_CDNS_40661953145657
+ Generating output for cell M4_M3_CDNS_40661953145666
+ Generating output for cell M4_M3_CDNS_40661953145665
+ Generating output for cell M4_M3_CDNS_40661953145664
+ Generating output for cell M4_M3_CDNS_40661953145663
+ Generating output for cell M4_M3_CDNS_40661953145577
+ Generating output for cell M4_M3_CDNS_40661953145565
+ Generating output for cell M4_M3_CDNS_40661953145564
+ Generating output for cell M4_M3_CDNS_40661953145563
+ Generating output for cell M4_M3_CDNS_40661953145562
+ Generating output for cell M4_M3_CDNS_40661953145619
+ Generating output for cell M4_M3_CDNS_40661953145621
+ Generating output for cell M4_M3_CDNS_40661953145623
+ Generating output for cell M4_M3_CDNS_40661953145625
+ Generating output for cell M4_M3_CDNS_40661953145629
+ Generating output for cell M4_M3_CDNS_40661953145627
+ Generating output for cell M4_M3_CDNS_40661953145631
+ Generating output for cell M4_M3_CDNS_40661953145545
+ Generating output for cell M4_M3_CDNS_40661953145635
+ Generating output for cell M4_M3_CDNS_40661953145633
+ Generating output for cell M4_M3_CDNS_40661953145547
+ Generating output for cell M4_M3_CDNS_40661953145557
+ Generating output for cell M4_M3_CDNS_40661953145553
+ Generating output for cell M4_M3_CDNS_40661953145559
+ Generating output for cell M4_M3_CDNS_40661953145560
+ Generating output for cell M4_M3_CDNS_40661953145618
+ Generating output for cell M4_M3_CDNS_40661953145637
+ Generating output for cell M4_M3_CDNS_40661953145620
+ Generating output for cell M4_M3_CDNS_40661953145624
+ Generating output for cell M4_M3_CDNS_40661953145622
+ Generating output for cell M4_M3_CDNS_40661953145628
+ Generating output for cell M4_M3_CDNS_40661953145626
+ Generating output for cell M4_M3_CDNS_40661953145630
+ Generating output for cell M4_M3_CDNS_40661953145634
+ Generating output for cell M4_M3_CDNS_40661953145632
+ Generating output for cell polygon00024
+ Generating output for cell polygon00025
+ Generating output for cell M4_M3_CDNS_40661953145636
+ Generating output for cell M4_M3_CDNS_40661953145640
+ Generating output for cell M4_M3_CDNS_40661953145638
+ Generating output for cell M4_M3_CDNS_40661953145642
+ Generating output for cell polygon00021
+ Generating output for cell polygon00022
+ Generating output for cell polygon00023
+ Generating output for cell M4_M3_CDNS_40661953145668
+ Generating output for cell M4_M3_CDNS_40661953145667
+ Generating output for cell M4_M3_CDNS_40661953145645
+ Generating output for cell M4_M3_CDNS_40661953145644
+ Generating output for cell M4_M3_CDNS_40661953145643
+ Generating output for cell M4_M3_CDNS_40661953145641
+ Generating output for cell M4_M3_CDNS_40661953145639
+ Generating output for cell M4_M3_CDNS_40661953145576
+ Generating output for cell M4_M3_CDNS_40661953145575
+ Generating output for cell polygon00013
+ Generating output for cell polygon00014
+ Generating output for cell M1_PSUB_CDNS_40661953145674
+ Generating output for cell polygon00012
+ Generating output for cell M1_PSUB_CDNS_40661953145669
+ Generating output for cell M3_M2_CDNS_40661953145676
+ Generating output for cell M3_M2_CDNS_40661953145675
+ Generating output for cell M1_PSUB_CDNS_40661953145673
+ Generating output for cell polygon00011
+ Generating output for cell polygon00010
+ Generating output for cell polygon00009
+ Generating output for cell polygon00008
+ Generating output for cell polygon00007
+ Generating output for cell M1_PSUB_CDNS_40661953145672
+ Generating output for cell M1_PSUB_CDNS_40661953145670
+ Generating output for cell M1_PSUB_CDNS_40661953145671
+ Generating output for cell polygon00001
+ Generating output for cell polygon00002
+ Generating output for cell polygon00003
+ Generating output for cell polygon00004
+ Generating output for cell polygon00005
+ Generating output for cell polygon00006
+ Generating output for cell POWER_RAIL_COR_1
+ Generating output for cell polygon00015
+ Generating output for cell polygon00016
+ Generating output for cell polygon00017
+ Generating output for cell polygon00018
+ Generating output for cell polygon00019
+ Generating output for cell polygon00020
+ Generating output for cell POWER_RAIL_COR_0
+ Generating output for cell polygon00026
+ Generating output for cell polygon00027
+ Generating output for cell polygon00028
+ Generating output for cell polygon00029
+ Generating output for cell polygon00030
+ Generating output for cell polygon00031
+ Generating output for cell POWER_RAIL_COR
+ Generating output for cell M3_M2_CDNS_40661953145776
+ Generating output for cell M3_M2_CDNS_40661953145773
+ Generating output for cell M3_M2_CDNS_40661953145771
+ Generating output for cell M3_M2_CDNS_40661953145770
+ Generating output for cell M3_M2_CDNS_40661953145768
+ Generating output for cell M3_M2_CDNS_40661953145766
+ Generating output for cell M3_M2_CDNS_40661953145764
+ Generating output for cell M3_M2_CDNS_40661953145762
+ Generating output for cell M3_M2_CDNS_40661953145760
+ Generating output for cell M3_M2_CDNS_40661953145758
+ Generating output for cell M3_M2_CDNS_40661953145756
+ Generating output for cell M3_M2_CDNS_40661953145754
+ Generating output for cell M3_M2_CDNS_40661953145753
+ Generating output for cell M3_M2_CDNS_40661953145750
+ Generating output for cell M3_M2_CDNS_40661953145747
+ Generating output for cell M3_M2_CDNS_40661953145746
+ Generating output for cell M3_M2_CDNS_40661953145744
+ Generating output for cell M3_M2_CDNS_40661953145742
+ Generating output for cell M3_M2_CDNS_40661953145741
+ Generating output for cell M3_M2_CDNS_40661953145739
+ Generating output for cell M3_M2_CDNS_40661953145738
+ Generating output for cell M3_M2_CDNS_40661953145737
+ Generating output for cell M3_M2_CDNS_40661953145730
+ Generating output for cell M3_M2_CDNS_40661953145727
+ Generating output for cell M3_M2_CDNS_40661953145726
+ Generating output for cell M3_M2_CDNS_40661953145719
+ Generating output for cell M3_M2_CDNS_40661953145696
+ Generating output for cell M3_M2_CDNS_40661953145693
+ Generating output for cell M3_M2_CDNS_40661953145691
+ Generating output for cell M3_M2_CDNS_40661953145690
+ Generating output for cell M3_M2_CDNS_40661953145689
+ Generating output for cell M3_M2_CDNS_40661953145175
+ Generating output for cell M2_M1_CDNS_40661953145775
+ Generating output for cell M2_M1_CDNS_40661953145774
+ Generating output for cell M2_M1_CDNS_40661953145772
+ Generating output for cell M2_M1_CDNS_40661953145769
+ Generating output for cell M2_M1_CDNS_40661953145767
+ Generating output for cell M2_M1_CDNS_40661953145765
+ Generating output for cell M2_M1_CDNS_40661953145763
+ Generating output for cell M2_M1_CDNS_40661953145761
+ Generating output for cell M2_M1_CDNS_40661953145759
+ Generating output for cell M2_M1_CDNS_40661953145757
+ Generating output for cell M2_M1_CDNS_40661953145755
+ Generating output for cell M2_M1_CDNS_40661953145752
+ Generating output for cell M2_M1_CDNS_40661953145751
+ Generating output for cell M2_M1_CDNS_40661953145749
+ Generating output for cell M2_M1_CDNS_40661953145748
+ Generating output for cell M2_M1_CDNS_40661953145745
+ Generating output for cell M2_M1_CDNS_40661953145743
+ Generating output for cell M2_M1_CDNS_40661953145740
+ Generating output for cell M2_M1_CDNS_40661953145736
+ Generating output for cell M2_M1_CDNS_40661953145735
+ Generating output for cell M2_M1_CDNS_40661953145734
+ Generating output for cell M2_M1_CDNS_40661953145733
+ Generating output for cell M2_M1_CDNS_40661953145732
+ Generating output for cell M2_M1_CDNS_40661953145731
+ Generating output for cell M2_M1_CDNS_40661953145729
+ Generating output for cell M2_M1_CDNS_40661953145728
+ Generating output for cell M2_M1_CDNS_40661953145725
+ Generating output for cell M2_M1_CDNS_40661953145724
+ Generating output for cell M2_M1_CDNS_40661953145722
+ Generating output for cell M2_M1_CDNS_40661953145694
+ Generating output for cell M2_M1_CDNS_40661953145692
+ Generating output for cell M2_M1_CDNS_40661953145688
+ Generating output for cell M2_M1_CDNS_40661953145687
+ Generating output for cell M2_M1_CDNS_40661953145686
+ Generating output for cell M2_M1_CDNS_40661953145183
+ Generating output for cell M1_PSUB_CDNS_40661953145723
+ Generating output for cell M1_PSUB_CDNS_40661953145721
+ Generating output for cell M1_PSUB_CDNS_40661953145720
+ Generating output for cell M1_PSUB_CDNS_40661953145718
+ Generating output for cell M1_PSUB_CDNS_40661953145717
+ Generating output for cell M1_PSUB_CDNS_40661953145716
+ Generating output for cell M1_PSUB_CDNS_40661953145715
+ Generating output for cell M1_PSUB_CDNS_40661953145714
+ Generating output for cell M1_PSUB_CDNS_40661953145713
+ Generating output for cell M1_PSUB_CDNS_40661953145712
+ Generating output for cell M1_PSUB_CDNS_40661953145711
+ Generating output for cell M1_PSUB_CDNS_40661953145710
+ Generating output for cell M1_PSUB_CDNS_40661953145709
+ Generating output for cell M1_PSUB_CDNS_40661953145708
+ Generating output for cell M1_PSUB_CDNS_40661953145707
+ Generating output for cell M1_PSUB_CDNS_40661953145706
+ Generating output for cell M1_PSUB_CDNS_40661953145705
+ Generating output for cell M1_PSUB_CDNS_40661953145704
+ Generating output for cell M1_PSUB_CDNS_40661953145703
+ Generating output for cell M1_PSUB_CDNS_40661953145702
+ Generating output for cell M1_PSUB_CDNS_40661953145701
+ Generating output for cell M1_PSUB_CDNS_40661953145700
+ Generating output for cell M1_PSUB_CDNS_40661953145699
+ Generating output for cell M1_PSUB_CDNS_40661953145698
+ Generating output for cell M1_PSUB_CDNS_40661953145697
+ Generating output for cell M1_PSUB_CDNS_40661953145695
+ Generating output for cell M1_PSUB_CDNS_40661953145685
+ Generating output for cell moscap_routing
+ Generating output for cell nmoscap_6p0_CDNS_406619531454
+ Generating output for cell M1_PSUB_CDNS_40661953145129
+ Generating output for cell M1_PSUB_CDNS_40661953145126
+ Generating output for cell moscap_corner
+ Generating output for cell M1_PSUB_CDNS_40661953145684
+ Generating output for cell M1_PSUB_CDNS_40661953145683
+ Generating output for cell M1_PSUB_CDNS_40661953145682
+ Generating output for cell M1_PSUB_CDNS_40661953145681
+ Generating output for cell moscap_corner_3
+ Generating output for cell M1_PSUB_CDNS_40661953145680
+ Generating output for cell M1_PSUB_CDNS_40661953145679
+ Generating output for cell moscap_corner_2
+ Generating output for cell M1_PSUB_CDNS_40661953145678
+ Generating output for cell moscap_corner_1
+ Generating output for cell M1_PSUB_CDNS_40661953145677
+ Generating output for cell top_routing_cor
+ Generating output for cell M3_M2_CDNS_40661953145804
+ Generating output for cell M3_M2_CDNS_40661953145803
+ Generating output for cell M3_M2_CDNS_40661953145802
+ Generating output for cell M3_M2_CDNS_40661953145801
+ Generating output for cell M3_M2_CDNS_40661953145800
+ Generating output for cell M3_M2_CDNS_40661953145799
+ Generating output for cell M3_M2_CDNS_40661953145798
+ Generating output for cell M3_M2_CDNS_40661953145797
+ Generating output for cell M3_M2_CDNS_40661953145796
+ Generating output for cell M3_M2_CDNS_40661953145795
+ Generating output for cell M3_M2_CDNS_40661953145786
+ Generating output for cell M3_M2_CDNS_40661953145785
+ Generating output for cell M3_M2_CDNS_40661953145784
+ Generating output for cell M3_M2_CDNS_40661953145783
+ Generating output for cell M3_M2_CDNS_40661953145782
+ Generating output for cell M3_M2_CDNS_40661953145781
+ Generating output for cell M3_M2_CDNS_4066195314590
+ Generating output for cell M3_M2_CDNS_4066195314587
+ Generating output for cell M3_M2_CDNS_4066195314584
+ Generating output for cell M2_M1_CDNS_4066195314588
+ Generating output for cell power_via_cor_5
+ Generating output for cell M3_M2_CDNS_40661953145780
+ Generating output for cell M3_M2_CDNS_40661953145779
+ Generating output for cell M3_M2_CDNS_40661953145778
+ Generating output for cell M3_M2_CDNS_40661953145777
+ Generating output for cell power_via_cor_3
+ Generating output for cell M2_M1_CDNS_40661953145805
+ Generating output for cell M2_M1_CDNS_40661953145794
+ Generating output for cell M2_M1_CDNS_40661953145793
+ Generating output for cell M2_M1_CDNS_40661953145791
+ Generating output for cell M2_M1_CDNS_40661953145788
+ Generating output for cell M2_M1_CDNS_40661953145292
+ Generating output for cell M2_M1_CDNS_40661953145147
+ Generating output for cell top_route_1
+ Generating output for cell pmos_6p0_CDNS_406619531456
+ Generating output for cell pmos_6p0_CDNS_406619531455
+ Generating output for cell pmos_6p0_CDNS_406619531452
+ Generating output for cell nmos_6p0_CDNS_406619531457
+ Generating output for cell M2_M1_CDNS_40661953145792
+ Generating output for cell M2_M1_CDNS_40661953145790
+ Generating output for cell M2_M1_CDNS_40661953145789
+ Generating output for cell M2_M1_CDNS_40661953145787
+ Generating output for cell M2_M1_CDNS_40661953145158
+ Generating output for cell M2_M1_CDNS_40661953145149
+ Generating output for cell M2_M1_CDNS_40661953145136
+ Generating output for cell M1_PSUB_CDNS_40661953145134
+ Generating output for cell M1_PSUB_CDNS_40661953145133
+ Generating output for cell M1_PSUB_CDNS_40661953145130
+ Generating output for cell M1_POLY2_CDNS_40661953145132
+ Generating output for cell M1_NWELL_CDNS_40661953145135
+ Generating output for cell M1_NWELL_CDNS_40661953145131
+ Generating output for cell nmos_clamp_20_50_4
+ Generating output for cell nmos_6p0_CDNS_406619531459
+ Generating output for cell nmos_6p0_CDNS_406619531458
+ Generating output for cell ppolyf_u_CDNS_406619531453
+ Generating output for cell M1_NWELL_CDNS_40661953145128
+ Generating output for cell M1_NWELL_CDNS_40661953145127
+ Generating output for cell comp018green_esd_rc_v5p0
+ Generating output for cell M2_M1_CDNS_40661953145103
+ Generating output for cell M1_PSUB_CDNS_40661953145102
+ Generating output for cell M1_POLY2_CDNS_40661953145110
+ Generating output for cell M1_POLY2_CDNS_40661953145109
+ Generating output for cell M1_POLY2_CDNS_40661953145108
+ Generating output for cell M1_POLY2_CDNS_40661953145106
+ Generating output for cell M1_POLY2_CDNS_40661953145105
+ Generating output for cell M1_NWELL_CDNS_40661953145111
+ Generating output for cell M1_NWELL_CDNS_40661953145107
+ Generating output for cell comp018green_esd_clamp_v5p0_2
+ Generating output for cell top_route
+ Generating output for cell comp018green_esd_rc_v5p0_1
+ Generating output for cell comp018green_esd_clamp_v5p0_1
+ Generating output for cell ESD_CLAMP_COR
+ Generating output for cell GF_NI_COR_BASE
+ Generating output for cell gf180mcu_fd_io__cor
+ Generating output for cell np_6p0_CDNS_406619531451
+ Generating output for cell nmoscap_6p0_CDNS_406619531450
+ Generating output for cell M2_M1_CDNS_40661953145162
+ Generating output for cell M2_M1_CDNS_40661953145146
+ Generating output for cell M2_M1_CDNS_40661953145140
+ Generating output for cell M2_M1_CDNS_40661953145138
+ Generating output for cell M2_M1_CDNS_4066195314586
+ Generating output for cell M2_M1_CDNS_4066195314585
+ Generating output for cell M2_M1_CDNS_4066195314574
+ Generating output for cell M2_M1_CDNS_4066195314573
+ Generating output for cell nmos_clamp_20_50_4_DVSS
+ Generating output for cell M2_M1_CDNS_40661953145161
+ Generating output for cell M2_M1_CDNS_40661953145160
+ Generating output for cell M2_M1_CDNS_40661953145159
+ Generating output for cell M2_M1_CDNS_40661953145125
+ Generating output for cell M2_M1_CDNS_40661953145122
+ Generating output for cell M2_M1_CDNS_40661953145118
+ Generating output for cell M2_M1_CDNS_40661953145117
+ Generating output for cell M2_M1_CDNS_40661953145113
+ Generating output for cell M2_M1_CDNS_40661953145112
+ Generating output for cell M1_PSUB_CDNS_40661953145124
+ Generating output for cell M1_PSUB_CDNS_40661953145123
+ Generating output for cell comp018green_esd_clamp_v5p0_DVSS
+ Generating output for cell M3_M2_CDNS_40661953145155
+ Generating output for cell M3_M2_CDNS_40661953145153
+ Generating output for cell M3_M2_CDNS_40661953145152
+ Generating output for cell M3_M2_CDNS_40661953145150
+ Generating output for cell M3_M2_CDNS_4066195314598
+ Generating output for cell M3_M2_CDNS_4066195314597
+ Generating output for cell M3_M2_CDNS_4066195314596
+ Generating output for cell M3_M2_CDNS_4066195314594
+ Generating output for cell M3_M2_CDNS_4066195314593
+ Generating output for cell M3_M2_CDNS_4066195314592
+ Generating output for cell M3_M2_CDNS_4066195314589
+ Generating output for cell M2_M1_CDNS_40661953145157
+ Generating output for cell M2_M1_CDNS_40661953145156
+ Generating output for cell M2_M1_CDNS_40661953145154
+ Generating output for cell M2_M1_CDNS_40661953145151
+ Generating output for cell M2_M1_CDNS_40661953145148
+ Generating output for cell M2_M1_CDNS_40661953145145
+ Generating output for cell M2_M1_CDNS_40661953145144
+ Generating output for cell M2_M1_CDNS_40661953145143
+ Generating output for cell M2_M1_CDNS_40661953145142
+ Generating output for cell M2_M1_CDNS_40661953145141
+ Generating output for cell M1_PSUB_CDNS_40661953145101
+ Generating output for cell M1_PSUB_CDNS_40661953145100
+ Generating output for cell M1_PSUB_CDNS_4066195314599
+ Generating output for cell M1_PSUB_CDNS_4066195314570
+ Generating output for cell M1_PSUB_CDNS_4066195314569
+ Generating output for cell M1_PSUB_CDNS_4066195314568
+ Generating output for cell M1_PSUB_CDNS_4066195314567
+ Generating output for cell M1_PSUB_CDNS_4066195314566
+ Generating output for cell M1_PSUB_CDNS_4066195314565
+ Generating output for cell M1_PSUB_CDNS_4066195314564
+ Generating output for cell M1_NWELL_CDNS_4066195314572
+ Generating output for cell M1_NWELL_CDNS_4066195314571
+ Generating output for cell GF_NI_DVSS_BASE
+ Generating output for cell M5_M4_CDNS_4066195314556
+ Generating output for cell M5_M4_CDNS_4066195314555
+ Generating output for cell M5_M4_CDNS_4066195314554
+ Generating output for cell M5_M4_CDNS_4066195314553
+ Generating output for cell M4_M3_CDNS_4066195314551
+ Generating output for cell M4_M3_CDNS_4066195314549
+ Generating output for cell M4_M3_CDNS_4066195314547
+ Generating output for cell M4_M3_CDNS_4066195314546
+ Generating output for cell M3_M2_CDNS_4066195314552
+ Generating output for cell M3_M2_CDNS_4066195314550
+ Generating output for cell M3_M2_CDNS_4066195314548
+ Generating output for cell M3_M2_CDNS_4066195314545
+ Generating output for cell Bondpad_5LM
+ Generating output for cell M5_M4_CDNS_4066195314561
+ Generating output for cell M5_M4_CDNS_4066195314560
+ Generating output for cell M5_M4_CDNS_4066195314559
+ Generating output for cell M4_M3_CDNS_4066195314558
+ Generating output for cell M4_M3_CDNS_4066195314557
+ Generating output for cell M4_M3_CDNS_4066195314562
+ Generating output for cell M1_PSUB_CDNS_4066195314563
+ Generating output for cell 3LM_METAL_RAIL
+ Generating output for cell 4LM_METAL_RAIL
+ Generating output for cell 5LM_METAL_RAIL
+ Generating output for cell 5LM_METAL_RAIL_PAD_60
+ Generating output for cell gf180mcu_fd_io__dvss
+ Generating output for cell ppolyf_u_CDNS_4066195314551
+ Generating output for cell pn_6p0_CDNS_4066195314528
+ Generating output for cell nmoscap_6p0_CDNS_4066195314523
+ Generating output for cell nmoscap_6p0_CDNS_4066195314522
+ Generating output for cell pmos_6p0_CDNS_4066195314529
+ Generating output for cell pmos_6p0_CDNS_4066195314512
+ Generating output for cell nmos_6p0_CDNS_4066195314531
+ Generating output for cell nmos_6p0_CDNS_4066195314530
+ Generating output for cell M1_PSUB_CDNS_40661953145275
+ Generating output for cell M1_PSUB_CDNS_40661953145237
+ Generating output for cell M1_PSUB_CDNS_40661953145228
+ Generating output for cell M1_PSUB_CDNS_40661953145226
+ Generating output for cell M1_POLY2_CDNS_40661953145222
+ Generating output for cell M1_NWELL_CDNS_40661953145274
+ Generating output for cell M1_NWELL_CDNS_40661953145273
+ Generating output for cell M1_NWELL_CDNS_40661953145223
+ Generating output for cell comp018green_sigbuf_1
+ Generating output for cell pn_6p0_CDNS_4066195314510
+ Generating output for cell pmos_6p0_CDNS_4066195314513
+ Generating output for cell nmos_6p0_CDNS_4066195314511
+ Generating output for cell M2_M1_CDNS_40661953145227
+ Generating output for cell M2_M1_CDNS_40661953145164
+ Generating output for cell M1_PSUB_CDNS_40661953145224
+ Generating output for cell M1_PSUB_CDNS_40661953145221
+ Generating output for cell M1_NWELL_CDNS_40661953145225
+ Generating output for cell M1_NWELL_CDNS_40661953145218
+ Generating output for cell comp018green_out_sigbuf_oe
+ Generating output for cell M1_PSUB_CDNS_40661953145271
+ Generating output for cell M1_NWELL_CDNS_40661953145272
+ Generating output for cell comp018green_out_sigbuf_a
+ Generating output for cell pmos_6p0_CDNS_4066195314521
+ Generating output for cell pmos_6p0_CDNS_4066195314517
+ Generating output for cell pmos_6p0_CDNS_4066195314516
+ Generating output for cell pmos_6p0_CDNS_4066195314515
+ Generating output for cell nmos_6p0_CDNS_4066195314520
+ Generating output for cell nmos_6p0_CDNS_4066195314519
+ Generating output for cell nmos_6p0_CDNS_4066195314518
+ Generating output for cell nmos_6p0_CDNS_4066195314514
+ Generating output for cell M2_M1_CDNS_40661953145181
+ Generating output for cell M1_PSUB_CDNS_40661953145238
+ Generating output for cell M1_PSUB_CDNS_40661953145235
+ Generating output for cell M1_PSUB_CDNS_40661953145234
+ Generating output for cell M1_PSUB_CDNS_40661953145233
+ Generating output for cell M1_PSUB_CDNS_40661953145232
+ Generating output for cell M1_POLY2_CDNS_40661953145229
+ Generating output for cell M1_NWELL_CDNS_40661953145236
+ Generating output for cell M1_NWELL_CDNS_40661953145231
+ Generating output for cell M1_NWELL_CDNS_40661953145230
+ Generating output for cell comp018green_out_predrv
+ Generating output for cell pmos_6p0_esd_40
+ Generating output for cell comp018green_out_drv_pleg_4T_Y
+ Generating output for cell comp018green_out_drv_pleg_4T_X
+ Generating output for cell M3_M2_CDNS_40661953145353
+ Generating output for cell M3_M2_CDNS_40661953145264
+ Generating output for cell M3_M2_CDNS_40661953145208
+ Generating output for cell M2_M1_CDNS_40661953145366
+ Generating output for cell M2_M1_CDNS_40661953145365
+ Generating output for cell PMOS_4T_metal_stack
+ Generating output for cell M3_M2_CDNS_40661953145363
+ Generating output for cell M3_M2_CDNS_40661953145358
+ Generating output for cell M3_M2_CDNS_40661953145350
+ Generating output for cell M3_M2_CDNS_40661953145209
+ Generating output for cell M3_M2_CDNS_40661953145180
+ Generating output for cell M2_M1_CDNS_40661953145364
+ Generating output for cell M2_M1_CDNS_40661953145360
+ Generating output for cell M2_M1_CDNS_40661953145359
+ Generating output for cell M2_M1_CDNS_40661953145356
+ Generating output for cell M2_M1_CDNS_40661953145355
+ Generating output for cell M2_M1_CDNS_40661953145354
+ Generating output for cell M2_M1_CDNS_40661953145348
+ Generating output for cell M2_M1_CDNS_40661953145347
+ Generating output for cell M2_M1_CDNS_40661953145346
+ Generating output for cell M2_M1_CDNS_40661953145177
+ Generating output for cell M1_PSUB_CDNS_40661953145362
+ Generating output for cell M1_PSUB_CDNS_40661953145357
+ Generating output for cell M1_PSUB_CDNS_40661953145351
+ Generating output for cell M1_PSUB_CDNS_40661953145349
+ Generating output for cell M1_PSUB_CDNS_40661953145283
+ Generating output for cell M1_NWELL_CDNS_40661953145361
+ Generating output for cell M1_NWELL_CDNS_40661953145352
+ Generating output for cell M1_NWELL_CDNS_40661953145345
+ Generating output for cell M1_NWELL_CDNS_40661953145286
+ Generating output for cell comp018green_out_paddrv_4T_PMOS_GROUP
+ Generating output for cell M3_M2_CDNS_40661953145371
+ Generating output for cell M3_M2_CDNS_40661953145370
+ Generating output for cell M3_M2_CDNS_40661953145369
+ Generating output for cell M2_M1_CDNS_40661953145368
+ Generating output for cell M2_M1_CDNS_40661953145367
+ Generating output for cell nmos_4T_metal_stack
+ Generating output for cell comp018green_out_drv_nleg_4T
+ Generating output for cell M1_PSUB_CDNS_40661953145376
+ Generating output for cell M1_PSUB_CDNS_40661953145375
+ Generating output for cell M1_PSUB_CDNS_40661953145372
+ Generating output for cell M1_NWELL_CDNS_40661953145374
+ Generating output for cell M1_NWELL_CDNS_40661953145373
+ Generating output for cell GR_NMOS_4T
+ Generating output for cell comp018green_out_paddrv_4T_NMOS_GROUP
+ Generating output for cell M3_M2_CDNS_40661953145342
+ Generating output for cell M3_M2_CDNS_40661953145341
+ Generating output for cell M3_M2_CDNS_40661953145340
+ Generating output for cell M3_M2_CDNS_40661953145278
+ Generating output for cell M3_M2_CDNS_40661953145263
+ Generating output for cell M2_M1_CDNS_40661953145344
+ Generating output for cell M2_M1_CDNS_40661953145343
+ Generating output for cell M2_M1_CDNS_40661953145280
+ Generating output for cell M2_M1_CDNS_40661953145279
+ Generating output for cell M2_M1_CDNS_40661953145201
+ Generating output for cell comp018green_out_paddrv_16T
+ Generating output for cell M1_PSUB_CDNS_40661953145321
+ Generating output for cell M1_NWELL_CDNS_40661953145322
+ Generating output for cell M1_NWELL_CDNS_40661953145315
+ Generating output for cell comp018green_sigbuf
+ Generating output for cell ppolyf_u_CDNS_4066195314533
+ Generating output for cell ppolyf_u_CDNS_4066195314532
+ Generating output for cell M1_NWELL_CDNS_40661953145316
+ Generating output for cell comp018green_in_pupd
+ Generating output for cell M1_PSUB_CDNS_40661953145324
+ Generating output for cell M1_NWELL_CDNS_40661953145323
+ Generating output for cell comp018green_std_xor2
+ Generating output for cell comp018green_std_nand2
+ Generating output for cell comp018green_in_logic_pupd
+ Generating output for cell pmos_6p0_CDNS_4066195314548
+ Generating output for cell pmos_6p0_CDNS_4066195314546
+ Generating output for cell pmos_6p0_CDNS_4066195314539
+ Generating output for cell nmos_6p0_CDNS_4066195314550
+ Generating output for cell nmos_6p0_CDNS_4066195314549
+ Generating output for cell nmos_6p0_CDNS_4066195314547
+ Generating output for cell M2_M1_CDNS_40661953145216
+ Generating output for cell M1_PSUB_CDNS_40661953145327
+ Generating output for cell M1_PSUB_CDNS_40661953145326
+ Generating output for cell M1_NWELL_CDNS_40661953145328
+ Generating output for cell M1_NWELL_CDNS_40661953145325
+ Generating output for cell comp018green_in_drv
+ Generating output for cell pmos_6p0_CDNS_4066195314545
+ Generating output for cell pmos_6p0_CDNS_4066195314544
+ Generating output for cell pmos_6p0_CDNS_4066195314543
+ Generating output for cell pmos_6p0_CDNS_4066195314538
+ Generating output for cell pmos_6p0_CDNS_4066195314534
+ Generating output for cell nmos_6p0_CDNS_4066195314542
+ Generating output for cell nmos_6p0_CDNS_4066195314541
+ Generating output for cell nmos_6p0_CDNS_4066195314540
+ Generating output for cell nmos_6p0_CDNS_4066195314537
+ Generating output for cell nmos_6p0_CDNS_4066195314536
+ Generating output for cell nmos_6p0_CDNS_4066195314535
+ Generating output for cell M2_M1_CDNS_40661953145115
+ Generating output for cell M1_PSUB_CDNS_40661953145319
+ Generating output for cell M1_PSUB_CDNS_40661953145317
+ Generating output for cell M1_NWELL_CDNS_40661953145320
+ Generating output for cell M1_NWELL_CDNS_40661953145318
+ Generating output for cell comp018green_in_cms_smt
+ Generating output for cell M3_M2_CDNS_40661953145314
+ Generating output for cell M3_M2_CDNS_40661953145313
+ Generating output for cell M2_M1_CDNS_40661953145312
+ Generating output for cell comp018green_inpath_cms_smt
+ Generating output for cell ppolyf_u_CDNS_4066195314525
+ Generating output for cell pn_6p0_CDNS_4066195314527
+ Generating output for cell np_6p0_CDNS_4066195314526
+ Generating output for cell M3_M2_CDNS_40661953145269
+ Generating output for cell M3_M2_CDNS_40661953145268
+ Generating output for cell M3_M2_CDNS_40661953145265
+ Generating output for cell M3_M2_CDNS_40661953145262
+ Generating output for cell M3_M2_CDNS_40661953145258
+ Generating output for cell M2_M1_CDNS_40661953145270
+ Generating output for cell M2_M1_CDNS_40661953145267
+ Generating output for cell M2_M1_CDNS_40661953145266
+ Generating output for cell M2_M1_CDNS_40661953145261
+ Generating output for cell M2_M1_CDNS_40661953145260
+ Generating output for cell M2_M1_CDNS_40661953145259
+ Generating output for cell M2_M1_CDNS_40661953145257
+ Generating output for cell M2_M1_CDNS_40661953145256
+ Generating output for cell M2_M1_CDNS_40661953145247
+ Generating output for cell M2_M1_CDNS_40661953145239
+ Generating output for cell M2_M1_CDNS_40661953145182
+ Generating output for cell M1_PACTIVE_CDNS_40661953145253
+ Generating output for cell M1_PACTIVE_CDNS_40661953145252
+ Generating output for cell M1_PACTIVE_CDNS_40661953145251
+ Generating output for cell M1_PACTIVE_CDNS_40661953145250
+ Generating output for cell M1_PACTIVE_CDNS_40661953145249
+ Generating output for cell M1_PACTIVE_CDNS_40661953145248
+ Generating output for cell M1_PACTIVE_CDNS_40661953145240
+ Generating output for cell M1_NACTIVE_CDNS_40661953145255
+ Generating output for cell M1_NACTIVE_CDNS_40661953145254
+ Generating output for cell M1_NACTIVE_CDNS_40661953145246
+ Generating output for cell M1_NACTIVE_CDNS_40661953145245
+ Generating output for cell M1_NACTIVE_CDNS_40661953145244
+ Generating output for cell M1_NACTIVE_CDNS_40661953145243
+ Generating output for cell M1_NACTIVE_CDNS_40661953145242
+ Generating output for cell M1_NACTIVE_CDNS_40661953145241
+ Generating output for cell comp018green_esd_cdm
+ Generating output for cell M3_M2_CDNS_40661953145332
+ Generating output for cell M3_M2_CDNS_40661953145330
+ Generating output for cell M3_M2_CDNS_40661953145213
+ Generating output for cell M3_M2_CDNS_40661953145212
+ Generating output for cell M3_M2_CDNS_40661953145210
+ Generating output for cell M3_M2_CDNS_40661953145207
+ Generating output for cell M3_M2_CDNS_40661953145206
+ Generating output for cell M3_M2_CDNS_40661953145204
+ Generating output for cell M3_M2_CDNS_40661953145202
+ Generating output for cell M3_M2_CDNS_40661953145200
+ Generating output for cell M3_M2_CDNS_40661953145199
+ Generating output for cell M3_M2_CDNS_40661953145197
+ Generating output for cell M3_M2_CDNS_40661953145196
+ Generating output for cell M3_M2_CDNS_40661953145194
+ Generating output for cell M3_M2_CDNS_40661953145193
+ Generating output for cell M3_M2_CDNS_40661953145190
+ Generating output for cell M3_M2_CDNS_40661953145188
+ Generating output for cell M3_M2_CDNS_40661953145186
+ Generating output for cell M3_M2_CDNS_40661953145179
+ Generating output for cell M3_M2_CDNS_40661953145174
+ Generating output for cell M3_M2_CDNS_40661953145172
+ Generating output for cell M3_M2_CDNS_40661953145170
+ Generating output for cell M2_M1_CDNS_40661953145378
+ Generating output for cell M2_M1_CDNS_40661953145333
+ Generating output for cell M2_M1_CDNS_40661953145331
+ Generating output for cell M2_M1_CDNS_40661953145329
+ Generating output for cell M2_M1_CDNS_40661953145214
+ Generating output for cell M2_M1_CDNS_40661953145211
+ Generating output for cell M2_M1_CDNS_40661953145205
+ Generating output for cell M2_M1_CDNS_40661953145203
+ Generating output for cell M2_M1_CDNS_40661953145198
+ Generating output for cell M2_M1_CDNS_40661953145195
+ Generating output for cell M2_M1_CDNS_40661953145189
+ Generating output for cell M2_M1_CDNS_40661953145187
+ Generating output for cell M2_M1_CDNS_40661953145185
+ Generating output for cell M2_M1_CDNS_40661953145178
+ Generating output for cell M2_M1_CDNS_40661953145176
+ Generating output for cell M2_M1_CDNS_40661953145173
+ Generating output for cell M2_M1_CDNS_40661953145171
+ Generating output for cell M2_M1_CDNS_40661953145169
+ Generating output for cell M2_M1_CDNS_40661953145163
+ Generating output for cell M2_M1_CDNS_40661953145120
+ Generating output for cell M2_M1_CDNS_40661953145116
+ Generating output for cell M2_M1_CDNS_40661953145114
+ Generating output for cell M1_PSUB_CDNS_40661953145339
+ Generating output for cell M1_PSUB_CDNS_40661953145338
+ Generating output for cell M1_PSUB_CDNS_40661953145215
+ Generating output for cell M1_PACTIVE_CDNS_40661953145168
+ Generating output for cell M1_PACTIVE_CDNS_40661953145167
+ Generating output for cell M1_PACTIVE_CDNS_40661953145166
+ Generating output for cell M1_PACTIVE_CDNS_40661953145165
+ Generating output for cell M1_NWELL_CDNS_40661953145377
+ Generating output for cell GF_NI_IN_S_BASE
+ Generating output for cell gf180mcu_fd_io__in_s
+ Generating output for cell GF_NI_IN_C_BASE
+ Generating output for cell gf180mcu_fd_io__in_c
+ Generating output for cell M3_M2_CDNS_40661953145335
+ Generating output for cell M2_M1_CDNS_40661953145334
+ Generating output for cell M1_PACTIVE_CDNS_40661953145337
+ Generating output for cell M1_PACTIVE_CDNS_40661953145336
+ Generating output for cell GF_NI_BI_T_BASE
+ Generating output for cell gf180mcu_fd_io__bi_t
+ Generating output for cell M2_M1_CDNS_40661953145139
+ Generating output for cell M2_M1_CDNS_40661953145137
+ Generating output for cell nmos_clamp_20_50_4_DVDD
+ Generating output for cell M2_M1_CDNS_40661953145121
+ Generating output for cell M2_M1_CDNS_40661953145119
+ Generating output for cell M2_M1_CDNS_40661953145104
+ Generating output for cell comp018green_esd_clamp_v5p0_DVDD
+ Generating output for cell M3_M2_CDNS_4066195314595
+ Generating output for cell M2_M1_CDNS_4066195314591
+ Generating output for cell M2_M1_CDNS_4066195314583
+ Generating output for cell M2_M1_CDNS_4066195314582
+ Generating output for cell M2_M1_CDNS_4066195314581
+ Generating output for cell M2_M1_CDNS_4066195314580
+ Generating output for cell M2_M1_CDNS_4066195314579
+ Generating output for cell M2_M1_CDNS_4066195314578
+ Generating output for cell M2_M1_CDNS_4066195314577
+ Generating output for cell M2_M1_CDNS_4066195314576
+ Generating output for cell M2_M1_CDNS_4066195314575
+ Generating output for cell GF_NI_DVDD_BASE
+ Generating output for cell gf180mcu_fd_io__dvdd
+ Generating output for cell M5_M4_CDNS_4066195314513
+ Generating output for cell M5_M4_CDNS_4066195314511
+ Generating output for cell M4_M3_CDNS_4066195314514
+ Generating output for cell M4_M3_CDNS_4066195314512
+ Generating output for cell M2_M1_CDNS_4066195314518
+ Generating output for cell POLY_SUB_FILL
+ Generating output for cell M3_M2_CDNS_4066195314517
+ Generating output for cell M2_M1_CDNS_4066195314515
+ Generating output for cell M1_PSUB_CDNS_4066195314516
+ Generating output for cell GF_NI_FILL5_1
+ Generating output for cell GF_NI_FILL5_0
+ Generating output for cell gf180mcu_fd_io__fill5
+ Generating output for cell chip_io
+ Generating output for cell alpha_1
+ Generating output for cell alpha_8
+ Generating output for cell alpha_0
+ Generating output for cell alpha_4
+ Generating output for cell alpha_5
+ Generating output for cell alpha_D
+ Generating output for cell alpha_6
+ Generating output for cell user_id_textblock
+ Generating output for cell caravel_180045d6
diff --git a/tapeout/logs/tools.info b/tapeout/logs/tools.info
new file mode 100644
index 0000000..98b8cee
--- /dev/null
+++ b/tapeout/logs/tools.info
@@ -0,0 +1,2 @@
+KLayout: 0.28
+Magic: 8.3.348
\ No newline at end of file
diff --git a/tapeout/logs/uncompress.log b/tapeout/logs/uncompress.log
new file mode 100644
index 0000000..5ca3179
--- /dev/null
+++ b/tapeout/logs/uncompress.log
@@ -0,0 +1,24 @@
+/bin/sh: line 0: cd: /root/project/verilog/dv/caravel/mgmt_soc/: No such file or directory
+/bin/sh: line 0: cd: /root/project/verilog/dv/caravel/mgmt_soc/: No such file or directory
+/bin/sh: line 0: cd: /root/project/verilog/dv/caravel/mgmt_soc/: No such file or directory
+/bin/sh: line 0: cd: /root/project/verilog/dv/caravel/mgmt_soc/: No such file or directory
+/bin/sh: line 0: cd: /root/project/verilog/dv/caravel/mgmt_soc/: No such file or directory
+/bin/sh: line 0: cd: /root/project/verilog/dv/caravel/mgmt_soc/: No such file or directory
+/bin/sh: line 0: cd: /root/project/verilog/dv/caravel/mgmt_soc/: No such file or directory
+/bin/sh: line 0: cd: /root/project/verilog/dv/caravel/mgmt_soc/: No such file or directory
+/bin/sh: line 0: cd: /root/project/verilog/dv/caravel/mgmt_soc/: No such file or directory
+/bin/sh: line 0: cd: /root/project/verilog/dv/caravel/mgmt_soc/: No such file or directory
+make: Nothing to be done for `check-env'.
+def/efuse_ctrl.def.gz -> def/efuse_ctrl.def
+def/fpga_struct_block.def.gz -> def/fpga_struct_block.def
+def/user_project_wrapper.def.gz -> def/user_project_wrapper.def
+gds/efuse_ctrl.gds.gz -> gds/efuse_ctrl.gds
+gds/fpga_struct_block.gds.gz -> gds/fpga_struct_block.gds
+gds/user_project_wrapper.gds.gz -> gds/user_project_wrapper.gds
+sdf/efuse_ctrl.sdf.gz -> sdf/efuse_ctrl.sdf
+sdf/fpga_struct_block.sdf.gz -> sdf/fpga_struct_block.sdf
+sdf/user_project_wrapper.sdf.gz -> sdf/user_project_wrapper.sdf
+verilog/gl/efuse_ctrl.v.gz -> verilog/gl/efuse_ctrl.v
+verilog/gl/fpga_struct_block.v.gz -> verilog/gl/fpga_struct_block.v
+verilog/gl/user_project_wrapper.v.gz -> verilog/gl/user_project_wrapper.v
+All files are uncompressed!
diff --git a/tapeout/outputs/gds/caravel_180045d6.gds.gz b/tapeout/outputs/gds/caravel_180045d6.gds.gz
new file mode 100644
index 0000000..1eb35c0
--- /dev/null
+++ b/tapeout/outputs/gds/caravel_180045d6.gds.gz
Binary files differ
diff --git a/tapeout/outputs/gf180mcuC.magicrc b/tapeout/outputs/gf180mcuC.magicrc
new file mode 100644
index 0000000..d1fc484
--- /dev/null
+++ b/tapeout/outputs/gf180mcuC.magicrc
@@ -0,0 +1,65 @@
+puts stdout "Sourcing design .magicrc for technology gf180mcuC ..."
+
+# Put internal grid on 0.005 pitch. This is important to match vendor file
+# input (as opposed to SCMOS-style layout. The default lambda grid is 0.05um).
+
+set scalefac [tech lambda]
+if {[lindex $scalefac 1] < 10} {
+ scalegrid 1 10
+}
+
+# drc off
+drc euclidean on
+# Change this to a fixed number for repeatable behavior with GDS writes
+# e.g., "random seed 12345"
+catch {random seed}
+
+# Allow override of PDK path from environment variable PDK_ROOT
+# "file nativename" guards against a local PDK_ROOT with "~" in the name
+if {[catch {set PDK_ROOT [file nativename $env(PDK_ROOT)]}]} {
+ set PDK_ROOT /usr/local/pdk/volare/gf180mcu/build/b8c6129fb60851c452a3136c2b8c603bb92cb180
+}
+
+# loading technology
+tech load $PDK_ROOT/gf180mcuC/libs.tech/magic/gf180mcuC.tech
+
+# load device generator
+source $PDK_ROOT/gf180mcuC/libs.tech/magic/gf180mcuC.tcl
+
+# load bind keys
+# source $PDK_ROOT/gf180mcuC/libs.tech/magic/gf180mcuC-BindKeys
+
+# set units to lambda grid
+snap lambda
+
+# set gf180mcu standard power, ground, and substrate names
+set VDD VDD
+set GND VSS
+set SUB VSUBS
+
+# Allow override of type of magic library views used, "mag" or "maglef",
+# from environment variable MAGTYPE
+
+if {[catch {set MAGTYPE $env(MAGTYPE)}]} {
+ set MAGTYPE mag
+}
+
+# add path to reference cells
+if {[file isdir ${PDK_ROOT}/gf180mcuC/libs.ref/${MAGTYPE}]} {
+ addpath ${PDK_ROOT}/gf180mcuC/libs.ref/${MAGTYPE}/gf180mcu_fd_pr
+ addpath ${PDK_ROOT}/gf180mcuC/libs.ref/${MAGTYPE}/gf180mcu_mcu7t5v0
+ addpath ${PDK_ROOT}/gf180mcuC/libs.ref/${MAGTYPE}/gf180mcu_mcu9t5v0
+ addpath ${PDK_ROOT}/gf180mcuC/libs.ref/${MAGTYPE}/gf180mcu_fd_io
+ addpath ${PDK_ROOT}/gf180mcuC/libs.ref/${MAGTYPE}/gf180mcu_fd_ip_sram
+} else {
+ addpath ${PDK_ROOT}/gf180mcuC/libs.ref/gf180mcu_fd_pr/${MAGTYPE}
+ addpath ${PDK_ROOT}/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/${MAGTYPE}
+ addpath ${PDK_ROOT}/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu9t5v0/${MAGTYPE}
+ addpath ${PDK_ROOT}/gf180mcuC/libs.ref/gf180mcu_fd_io/${MAGTYPE}
+ addpath ${PDK_ROOT}/gf180mcuC/libs.ref/gf180mcu_fd_ip_sram/${MAGTYPE}
+}
+
+# add path to IP from catalog. This procedure defined in the PDK script.
+catch {magic::query_mylib_ip}
+# add path to local IP from user design space. Defined in the PDK script.
+catch {magic::query_my_projects}
diff --git a/tapeout/outputs/mag/caravel_core.mag b/tapeout/outputs/mag/caravel_core.mag
new file mode 100644
index 0000000..9ad9c7f
--- /dev/null
+++ b/tapeout/outputs/mag/caravel_core.mag
Binary files differ
diff --git a/tapeout/outputs/mag/gpio_defaults_block_007.mag b/tapeout/outputs/mag/gpio_defaults_block_007.mag
new file mode 100644
index 0000000..0c4bcec
--- /dev/null
+++ b/tapeout/outputs/mag/gpio_defaults_block_007.mag
@@ -0,0 +1,320 @@
+magic
+tech gf180mcuC
+magscale 1 10
+timestamp 1669928025
+<< metal1 >>
+rect 598 2766 673 3020
+rect 916 2806 991 3030
+rect 468 2694 673 2766
+rect 468 2675 540 2694
+rect 468 2010 540 2029
+rect 1812 2010 1884 2029
+rect 2932 2010 3004 2029
+rect 468 1938 673 2010
+rect 1812 1938 2017 2010
+rect 2932 1938 3137 2010
+rect 598 1684 673 1938
+rect 916 1674 991 1898
+rect 1942 1684 2017 1938
+rect 2260 1674 2335 1898
+rect 3062 1684 3137 1938
+rect 3380 1674 3455 1898
+rect 598 1198 673 1452
+rect 916 1238 991 1462
+rect 1942 1198 2017 1452
+rect 2260 1238 2335 1462
+rect 3062 1198 3137 1452
+rect 3380 1238 3455 1462
+rect 468 1126 673 1198
+rect 1812 1126 2017 1198
+rect 2932 1126 3137 1198
+rect 468 1107 540 1126
+rect 1812 1107 1884 1126
+rect 2932 1107 3004 1126
+rect 468 442 540 461
+rect 1812 442 1884 461
+rect 2932 442 3004 461
+rect 468 370 673 442
+rect 1812 370 2017 442
+rect 2932 370 3137 442
+rect 598 116 673 370
+rect 916 106 991 330
+rect 1942 116 2017 370
+rect 2260 106 2335 330
+rect 3062 116 3137 370
+rect 3380 106 3455 330
+<< via1 >>
+rect 83 3110 652 3170
+rect 1793 2330 2362 2390
+rect 83 1540 652 1600
+rect 1793 750 2362 810
+rect 92 -29 621 31
+rect 923 2827 983 2887
+rect 605 1817 665 1877
+rect 2267 1817 2327 1877
+rect 3387 1817 3447 1877
+rect 605 1259 665 1319
+rect 2267 1259 2327 1319
+rect 3387 1259 3447 1319
+rect 605 249 665 309
+rect 2267 249 2327 309
+rect 3387 249 3447 309
+<< metal2 >>
+rect 70 3170 666 3181
+rect 70 3110 83 3170
+rect 652 3110 666 3170
+rect 70 3098 666 3110
+rect 576 2825 1699 2889
+rect 585 1815 1428 1879
+rect 70 1600 666 1611
+rect 70 1540 83 1600
+rect 652 1540 666 1600
+rect 70 1528 666 1540
+rect 585 1257 1132 1321
+rect 572 247 1004 311
+rect 80 31 633 43
+rect 80 -29 92 31
+rect 621 -29 633 31
+rect 80 -40 633 -29
+rect 700 -84 756 247
+rect 1076 157 1132 1257
+rect 1036 97 1132 157
+rect 1036 -84 1092 97
+rect 1372 -84 1428 1815
+rect 1643 496 1699 2825
+rect 1780 2390 2376 2401
+rect 1780 2330 1793 2390
+rect 2362 2330 2376 2390
+rect 1780 2318 2376 2330
+rect 1929 1815 2772 1879
+rect 1929 1257 2496 1321
+rect 1780 810 2376 821
+rect 1780 750 1793 810
+rect 2362 750 2376 810
+rect 1780 738 2376 750
+rect 1643 440 1764 496
+rect 1708 -84 1764 440
+rect 1915 247 2348 311
+rect 2044 -84 2100 247
+rect 2440 174 2496 1257
+rect 2380 118 2496 174
+rect 2380 -84 2436 118
+rect 2716 -84 2772 1815
+rect 2921 1815 3468 1879
+rect 2921 177 2977 1815
+rect 3041 1257 3780 1321
+rect 3043 247 3462 311
+rect 2921 121 3108 177
+rect 3052 -84 3108 121
+rect 3388 -84 3444 247
+rect 3724 -84 3780 1257
+<< via2 >>
+rect 83 3110 652 3170
+rect 83 1540 652 1600
+rect 92 -29 621 31
+rect 1793 2330 2362 2390
+rect 1793 750 2362 810
+<< metal3 >>
+rect 66 3170 672 3192
+rect 66 3110 83 3170
+rect 652 3110 672 3170
+rect 66 1600 672 3110
+rect 66 1540 83 1600
+rect 652 1540 672 1600
+rect 66 31 672 1540
+rect 66 -29 92 31
+rect 621 -29 672 31
+rect 66 -53 672 -29
+rect 1773 2390 2379 3192
+rect 1773 2330 1793 2390
+rect 2362 2330 2379 2390
+rect 1773 810 2379 2330
+rect 1773 750 1793 810
+rect 2362 750 2379 810
+rect 1773 -53 2379 750
+use gf180mcu_fd_sc_mcu7t5v0__endcap ENDCAP_0 $PDK_ROOT/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag
+timestamp 1669862171
+transform 1 0 0 0 1 0
+box -86 -86 310 870
+use gf180mcu_fd_sc_mcu7t5v0__endcap ENDCAP_1
+timestamp 1669862171
+transform 1 0 2464 0 -1 3136
+box -86 -86 310 870
+use gf180mcu_fd_sc_mcu7t5v0__endcap ENDCAP_2
+timestamp 1669862171
+transform 1 0 3584 0 -1 3136
+box -86 -86 310 870
+use gf180mcu_fd_sc_mcu7t5v0__endcap ENDCAP_3
+timestamp 1669862171
+transform 1 0 0 0 -1 3136
+box -86 -86 310 870
+use gf180mcu_fd_sc_mcu7t5v0__endcap ENDCAP_4
+timestamp 1669862171
+transform 1 0 0 0 1 1568
+box -86 -86 310 870
+use gf180mcu_fd_sc_mcu7t5v0__endcap ENDCAP_5
+timestamp 1669862171
+transform 1 0 2464 0 1 1568
+box -86 -86 310 870
+use gf180mcu_fd_sc_mcu7t5v0__endcap ENDCAP_6
+timestamp 1669862171
+transform 1 0 3584 0 1 1568
+box -86 -86 310 870
+use gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLCAP_4_0 $PDK_ROOT/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag
+timestamp 1669862171
+transform 1 0 1120 0 1 0
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLCAP_4_1
+timestamp 1669862171
+transform 1 0 1120 0 -1 3136
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLCAP_4_2
+timestamp 1669862171
+transform 1 0 2016 0 -1 3136
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLCAP_4_3
+timestamp 1669862171
+transform 1 0 1120 0 -1 1568
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLCAP_4_4
+timestamp 1669862171
+transform 1 0 3136 0 -1 3136
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLCAP_4_5
+timestamp 1669862171
+transform 1 0 1568 0 -1 3136
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLCAP_4_6
+timestamp 1669862171
+transform 1 0 1120 0 1 1568
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLCAP_4_7
+timestamp 1669862171
+transform 1 0 2688 0 -1 3136
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__filltie FILLTIE_0 $PDK_ROOT/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag
+timestamp 1669862171
+transform 1 0 2464 0 1 0
+box -86 -86 310 870
+use gf180mcu_fd_sc_mcu7t5v0__filltie FILLTIE_1
+timestamp 1669862171
+transform 1 0 3584 0 1 0
+box -86 -86 310 870
+use gf180mcu_fd_sc_mcu7t5v0__filltie FILLTIE_2
+timestamp 1669862171
+transform 1 0 3584 0 -1 1568
+box -86 -86 310 870
+use gf180mcu_fd_sc_mcu7t5v0__filltie FILLTIE_4
+timestamp 1669862171
+transform 1 0 0 0 -1 1568
+box -86 -86 310 870
+use gf180mcu_fd_sc_mcu7t5v0__filltie FILLTIE_5
+timestamp 1669862171
+transform 1 0 2464 0 -1 1568
+box -86 -86 310 870
+use gf180mcu_fd_sc_mcu7t5v0__tieh gpio_default_value_one[0] $PDK_ROOT/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag
+timestamp 1669862171
+transform 1 0 224 0 1 0
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__tieh gpio_default_value_one[1]
+timestamp 1669862171
+transform 1 0 224 0 -1 1568
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__tieh gpio_default_value_one[2]
+timestamp 1669862171
+transform 1 0 224 0 1 1568
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__tieh gpio_default_value_one[3]
+timestamp 1669862171
+transform 1 0 224 0 -1 3136
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__tieh gpio_default_value_one[4]
+timestamp 1669862171
+transform 1 0 1568 0 1 0
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__tieh gpio_default_value_one[5]
+timestamp 1669862171
+transform 1 0 1568 0 -1 1568
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__tieh gpio_default_value_one[6]
+timestamp 1669862171
+transform 1 0 1568 0 1 1568
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__tieh gpio_default_value_one[8]
+timestamp 1669862171
+transform 1 0 2688 0 1 0
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__tieh gpio_default_value_one[9]
+timestamp 1669862171
+transform 1 0 2688 0 -1 1568
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__tieh gpio_default_value_one[7]
+timestamp 1669862171
+transform 1 0 2688 0 1 1568
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__tiel gpio_default_value_zero[0] $PDK_ROOT/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag
+timestamp 1669862171
+transform 1 0 672 0 1 0
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__tiel gpio_default_value_zero[1]
+timestamp 1669862171
+transform 1 0 672 0 -1 1568
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__tiel gpio_default_value_zero[2]
+timestamp 1669862171
+transform 1 0 672 0 1 1568
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__tiel gpio_default_value_zero[3]
+timestamp 1669862171
+transform 1 0 672 0 -1 3136
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__tiel gpio_default_value_zero[4]
+timestamp 1669862171
+transform 1 0 2016 0 1 0
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__tiel gpio_default_value_zero[5]
+timestamp 1669862171
+transform 1 0 2016 0 -1 1568
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__tiel gpio_default_value_zero[6]
+timestamp 1669862171
+transform 1 0 2016 0 1 1568
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__tiel gpio_default_value_zero[8]
+timestamp 1669862171
+transform 1 0 3136 0 1 0
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__tiel gpio_default_value_zero[9]
+timestamp 1669862171
+transform 1 0 3136 0 -1 1568
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__tiel gpio_default_value_zero[7]
+timestamp 1669862171
+transform 1 0 3136 0 1 1568
+box -86 -86 534 870
+<< labels >>
+flabel metal3 1773 -53 2379 750 0 FreeSans 1600 0 0 0 VDD
+port 11 nsew
+flabel metal3 66 55 672 858 0 FreeSans 1600 0 0 0 VSS
+port 12 nsew
+flabel metal2 700 -84 756 150 0 FreeSans 400 90 0 0 gpio_defaults[0]
+port 1 nsew
+flabel metal2 1036 -84 1092 150 0 FreeSans 400 90 0 0 gpio_defaults[1]
+port 5 nsew
+flabel metal2 1372 -84 1428 150 0 FreeSans 400 90 0 0 gpio_defaults[2]
+port 9 nsew
+flabel metal2 1708 -84 1764 150 0 FreeSans 400 90 0 0 gpio_defaults[3]
+port 8 nsew
+flabel metal2 2044 -84 2100 150 0 FreeSans 400 90 0 0 gpio_defaults[4]
+port 2 nsew
+flabel metal2 2380 -84 2436 150 0 FreeSans 400 90 0 0 gpio_defaults[5]
+port 6 nsew
+flabel metal2 2716 -84 2772 150 0 FreeSans 400 90 0 0 gpio_defaults[6]
+port 10 nsew
+flabel metal2 3052 -84 3108 150 0 FreeSans 400 90 0 0 gpio_defaults[7]
+port 4 nsew
+flabel metal2 3388 -84 3444 150 0 FreeSans 400 90 0 0 gpio_defaults[8]
+port 3 nsew
+flabel metal2 3724 -84 3780 150 0 FreeSans 400 90 0 0 gpio_defaults[9]
+port 7 nsew
+<< end >>
diff --git a/tapeout/outputs/mag/gpio_defaults_block_008.mag b/tapeout/outputs/mag/gpio_defaults_block_008.mag
new file mode 100644
index 0000000..e8c5dac
--- /dev/null
+++ b/tapeout/outputs/mag/gpio_defaults_block_008.mag
@@ -0,0 +1,320 @@
+magic
+tech gf180mcuC
+magscale 1 10
+timestamp 1669928025
+<< metal1 >>
+rect 598 2766 673 3020
+rect 916 2806 991 3030
+rect 468 2694 673 2766
+rect 468 2675 540 2694
+rect 468 2010 540 2029
+rect 1812 2010 1884 2029
+rect 2932 2010 3004 2029
+rect 468 1938 673 2010
+rect 1812 1938 2017 2010
+rect 2932 1938 3137 2010
+rect 598 1684 673 1938
+rect 916 1674 991 1898
+rect 1942 1684 2017 1938
+rect 2260 1674 2335 1898
+rect 3062 1684 3137 1938
+rect 3380 1674 3455 1898
+rect 598 1198 673 1452
+rect 916 1238 991 1462
+rect 1942 1198 2017 1452
+rect 2260 1238 2335 1462
+rect 3062 1198 3137 1452
+rect 3380 1238 3455 1462
+rect 468 1126 673 1198
+rect 1812 1126 2017 1198
+rect 2932 1126 3137 1198
+rect 468 1107 540 1126
+rect 1812 1107 1884 1126
+rect 2932 1107 3004 1126
+rect 468 442 540 461
+rect 1812 442 1884 461
+rect 2932 442 3004 461
+rect 468 370 673 442
+rect 1812 370 2017 442
+rect 2932 370 3137 442
+rect 598 116 673 370
+rect 916 106 991 330
+rect 1942 116 2017 370
+rect 2260 106 2335 330
+rect 3062 116 3137 370
+rect 3380 106 3455 330
+<< via1 >>
+rect 83 3110 652 3170
+rect 1793 2330 2362 2390
+rect 83 1540 652 1600
+rect 1793 750 2362 810
+rect 92 -29 621 31
+rect 605 2827 665 2887
+rect 923 1817 983 1877
+rect 2267 1817 2327 1877
+rect 3387 1817 3447 1877
+rect 923 1259 983 1319
+rect 2267 1259 2327 1319
+rect 3387 1259 3447 1319
+rect 923 249 983 309
+rect 2267 249 2327 309
+rect 3387 249 3447 309
+<< metal2 >>
+rect 70 3170 666 3181
+rect 70 3110 83 3170
+rect 652 3110 666 3170
+rect 70 3098 666 3110
+rect 576 2825 1699 2889
+rect 585 1815 1428 1879
+rect 70 1600 666 1611
+rect 70 1540 83 1600
+rect 652 1540 666 1600
+rect 70 1528 666 1540
+rect 585 1257 1132 1321
+rect 572 247 1004 311
+rect 80 31 633 43
+rect 80 -29 92 31
+rect 621 -29 633 31
+rect 80 -40 633 -29
+rect 700 -84 756 247
+rect 1076 157 1132 1257
+rect 1036 97 1132 157
+rect 1036 -84 1092 97
+rect 1372 -84 1428 1815
+rect 1643 496 1699 2825
+rect 1780 2390 2376 2401
+rect 1780 2330 1793 2390
+rect 2362 2330 2376 2390
+rect 1780 2318 2376 2330
+rect 1929 1815 2772 1879
+rect 1929 1257 2496 1321
+rect 1780 810 2376 821
+rect 1780 750 1793 810
+rect 2362 750 2376 810
+rect 1780 738 2376 750
+rect 1643 440 1764 496
+rect 1708 -84 1764 440
+rect 1915 247 2348 311
+rect 2044 -84 2100 247
+rect 2440 174 2496 1257
+rect 2380 118 2496 174
+rect 2380 -84 2436 118
+rect 2716 -84 2772 1815
+rect 2921 1815 3468 1879
+rect 2921 177 2977 1815
+rect 3041 1257 3780 1321
+rect 3043 247 3462 311
+rect 2921 121 3108 177
+rect 3052 -84 3108 121
+rect 3388 -84 3444 247
+rect 3724 -84 3780 1257
+<< via2 >>
+rect 83 3110 652 3170
+rect 83 1540 652 1600
+rect 92 -29 621 31
+rect 1793 2330 2362 2390
+rect 1793 750 2362 810
+<< metal3 >>
+rect 66 3170 672 3192
+rect 66 3110 83 3170
+rect 652 3110 672 3170
+rect 66 1600 672 3110
+rect 66 1540 83 1600
+rect 652 1540 672 1600
+rect 66 31 672 1540
+rect 66 -29 92 31
+rect 621 -29 672 31
+rect 66 -53 672 -29
+rect 1773 2390 2379 3192
+rect 1773 2330 1793 2390
+rect 2362 2330 2379 2390
+rect 1773 810 2379 2330
+rect 1773 750 1793 810
+rect 2362 750 2379 810
+rect 1773 -53 2379 750
+use gf180mcu_fd_sc_mcu7t5v0__endcap ENDCAP_0 $PDK_ROOT/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag
+timestamp 1669862171
+transform 1 0 0 0 1 0
+box -86 -86 310 870
+use gf180mcu_fd_sc_mcu7t5v0__endcap ENDCAP_1
+timestamp 1669862171
+transform 1 0 2464 0 -1 3136
+box -86 -86 310 870
+use gf180mcu_fd_sc_mcu7t5v0__endcap ENDCAP_2
+timestamp 1669862171
+transform 1 0 3584 0 -1 3136
+box -86 -86 310 870
+use gf180mcu_fd_sc_mcu7t5v0__endcap ENDCAP_3
+timestamp 1669862171
+transform 1 0 0 0 -1 3136
+box -86 -86 310 870
+use gf180mcu_fd_sc_mcu7t5v0__endcap ENDCAP_4
+timestamp 1669862171
+transform 1 0 0 0 1 1568
+box -86 -86 310 870
+use gf180mcu_fd_sc_mcu7t5v0__endcap ENDCAP_5
+timestamp 1669862171
+transform 1 0 2464 0 1 1568
+box -86 -86 310 870
+use gf180mcu_fd_sc_mcu7t5v0__endcap ENDCAP_6
+timestamp 1669862171
+transform 1 0 3584 0 1 1568
+box -86 -86 310 870
+use gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLCAP_4_0 $PDK_ROOT/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag
+timestamp 1669862171
+transform 1 0 1120 0 1 0
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLCAP_4_1
+timestamp 1669862171
+transform 1 0 1120 0 -1 3136
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLCAP_4_2
+timestamp 1669862171
+transform 1 0 2016 0 -1 3136
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLCAP_4_3
+timestamp 1669862171
+transform 1 0 1120 0 -1 1568
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLCAP_4_4
+timestamp 1669862171
+transform 1 0 3136 0 -1 3136
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLCAP_4_5
+timestamp 1669862171
+transform 1 0 1568 0 -1 3136
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLCAP_4_6
+timestamp 1669862171
+transform 1 0 1120 0 1 1568
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLCAP_4_7
+timestamp 1669862171
+transform 1 0 2688 0 -1 3136
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__filltie FILLTIE_0 $PDK_ROOT/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag
+timestamp 1669862171
+transform 1 0 2464 0 1 0
+box -86 -86 310 870
+use gf180mcu_fd_sc_mcu7t5v0__filltie FILLTIE_1
+timestamp 1669862171
+transform 1 0 3584 0 1 0
+box -86 -86 310 870
+use gf180mcu_fd_sc_mcu7t5v0__filltie FILLTIE_2
+timestamp 1669862171
+transform 1 0 3584 0 -1 1568
+box -86 -86 310 870
+use gf180mcu_fd_sc_mcu7t5v0__filltie FILLTIE_4
+timestamp 1669862171
+transform 1 0 0 0 -1 1568
+box -86 -86 310 870
+use gf180mcu_fd_sc_mcu7t5v0__filltie FILLTIE_5
+timestamp 1669862171
+transform 1 0 2464 0 -1 1568
+box -86 -86 310 870
+use gf180mcu_fd_sc_mcu7t5v0__tieh gpio_default_value_one[0] $PDK_ROOT/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag
+timestamp 1669862171
+transform 1 0 224 0 1 0
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__tieh gpio_default_value_one[1]
+timestamp 1669862171
+transform 1 0 224 0 -1 1568
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__tieh gpio_default_value_one[2]
+timestamp 1669862171
+transform 1 0 224 0 1 1568
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__tieh gpio_default_value_one[3]
+timestamp 1669862171
+transform 1 0 224 0 -1 3136
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__tieh gpio_default_value_one[4]
+timestamp 1669862171
+transform 1 0 1568 0 1 0
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__tieh gpio_default_value_one[5]
+timestamp 1669862171
+transform 1 0 1568 0 -1 1568
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__tieh gpio_default_value_one[6]
+timestamp 1669862171
+transform 1 0 1568 0 1 1568
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__tieh gpio_default_value_one[8]
+timestamp 1669862171
+transform 1 0 2688 0 1 0
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__tieh gpio_default_value_one[9]
+timestamp 1669862171
+transform 1 0 2688 0 -1 1568
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__tieh gpio_default_value_one[7]
+timestamp 1669862171
+transform 1 0 2688 0 1 1568
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__tiel gpio_default_value_zero[0] $PDK_ROOT/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag
+timestamp 1669862171
+transform 1 0 672 0 1 0
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__tiel gpio_default_value_zero[1]
+timestamp 1669862171
+transform 1 0 672 0 -1 1568
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__tiel gpio_default_value_zero[2]
+timestamp 1669862171
+transform 1 0 672 0 1 1568
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__tiel gpio_default_value_zero[3]
+timestamp 1669862171
+transform 1 0 672 0 -1 3136
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__tiel gpio_default_value_zero[4]
+timestamp 1669862171
+transform 1 0 2016 0 1 0
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__tiel gpio_default_value_zero[5]
+timestamp 1669862171
+transform 1 0 2016 0 -1 1568
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__tiel gpio_default_value_zero[6]
+timestamp 1669862171
+transform 1 0 2016 0 1 1568
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__tiel gpio_default_value_zero[8]
+timestamp 1669862171
+transform 1 0 3136 0 1 0
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__tiel gpio_default_value_zero[9]
+timestamp 1669862171
+transform 1 0 3136 0 -1 1568
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__tiel gpio_default_value_zero[7]
+timestamp 1669862171
+transform 1 0 3136 0 1 1568
+box -86 -86 534 870
+<< labels >>
+flabel metal3 1773 -53 2379 750 0 FreeSans 1600 0 0 0 VDD
+port 11 nsew
+flabel metal3 66 55 672 858 0 FreeSans 1600 0 0 0 VSS
+port 12 nsew
+flabel metal2 700 -84 756 150 0 FreeSans 400 90 0 0 gpio_defaults[0]
+port 1 nsew
+flabel metal2 1036 -84 1092 150 0 FreeSans 400 90 0 0 gpio_defaults[1]
+port 5 nsew
+flabel metal2 1372 -84 1428 150 0 FreeSans 400 90 0 0 gpio_defaults[2]
+port 9 nsew
+flabel metal2 1708 -84 1764 150 0 FreeSans 400 90 0 0 gpio_defaults[3]
+port 8 nsew
+flabel metal2 2044 -84 2100 150 0 FreeSans 400 90 0 0 gpio_defaults[4]
+port 2 nsew
+flabel metal2 2380 -84 2436 150 0 FreeSans 400 90 0 0 gpio_defaults[5]
+port 6 nsew
+flabel metal2 2716 -84 2772 150 0 FreeSans 400 90 0 0 gpio_defaults[6]
+port 10 nsew
+flabel metal2 3052 -84 3108 150 0 FreeSans 400 90 0 0 gpio_defaults[7]
+port 4 nsew
+flabel metal2 3388 -84 3444 150 0 FreeSans 400 90 0 0 gpio_defaults[8]
+port 3 nsew
+flabel metal2 3724 -84 3780 150 0 FreeSans 400 90 0 0 gpio_defaults[9]
+port 7 nsew
+<< end >>
diff --git a/tapeout/outputs/mag/gpio_defaults_block_009.mag b/tapeout/outputs/mag/gpio_defaults_block_009.mag
new file mode 100644
index 0000000..aefbd62
--- /dev/null
+++ b/tapeout/outputs/mag/gpio_defaults_block_009.mag
@@ -0,0 +1,320 @@
+magic
+tech gf180mcuC
+magscale 1 10
+timestamp 1669928025
+<< metal1 >>
+rect 598 2766 673 3020
+rect 916 2806 991 3030
+rect 468 2694 673 2766
+rect 468 2675 540 2694
+rect 468 2010 540 2029
+rect 1812 2010 1884 2029
+rect 2932 2010 3004 2029
+rect 468 1938 673 2010
+rect 1812 1938 2017 2010
+rect 2932 1938 3137 2010
+rect 598 1684 673 1938
+rect 916 1674 991 1898
+rect 1942 1684 2017 1938
+rect 2260 1674 2335 1898
+rect 3062 1684 3137 1938
+rect 3380 1674 3455 1898
+rect 598 1198 673 1452
+rect 916 1238 991 1462
+rect 1942 1198 2017 1452
+rect 2260 1238 2335 1462
+rect 3062 1198 3137 1452
+rect 3380 1238 3455 1462
+rect 468 1126 673 1198
+rect 1812 1126 2017 1198
+rect 2932 1126 3137 1198
+rect 468 1107 540 1126
+rect 1812 1107 1884 1126
+rect 2932 1107 3004 1126
+rect 468 442 540 461
+rect 1812 442 1884 461
+rect 2932 442 3004 461
+rect 468 370 673 442
+rect 1812 370 2017 442
+rect 2932 370 3137 442
+rect 598 116 673 370
+rect 916 106 991 330
+rect 1942 116 2017 370
+rect 2260 106 2335 330
+rect 3062 116 3137 370
+rect 3380 106 3455 330
+<< via1 >>
+rect 83 3110 652 3170
+rect 1793 2330 2362 2390
+rect 83 1540 652 1600
+rect 1793 750 2362 810
+rect 92 -29 621 31
+rect 605 2827 665 2887
+rect 923 1817 983 1877
+rect 2267 1817 2327 1877
+rect 3387 1817 3447 1877
+rect 923 1259 983 1319
+rect 2267 1259 2327 1319
+rect 3387 1259 3447 1319
+rect 605 249 665 309
+rect 2267 249 2327 309
+rect 3387 249 3447 309
+<< metal2 >>
+rect 70 3170 666 3181
+rect 70 3110 83 3170
+rect 652 3110 666 3170
+rect 70 3098 666 3110
+rect 576 2825 1699 2889
+rect 585 1815 1428 1879
+rect 70 1600 666 1611
+rect 70 1540 83 1600
+rect 652 1540 666 1600
+rect 70 1528 666 1540
+rect 585 1257 1132 1321
+rect 572 247 1004 311
+rect 80 31 633 43
+rect 80 -29 92 31
+rect 621 -29 633 31
+rect 80 -40 633 -29
+rect 700 -84 756 247
+rect 1076 157 1132 1257
+rect 1036 97 1132 157
+rect 1036 -84 1092 97
+rect 1372 -84 1428 1815
+rect 1643 496 1699 2825
+rect 1780 2390 2376 2401
+rect 1780 2330 1793 2390
+rect 2362 2330 2376 2390
+rect 1780 2318 2376 2330
+rect 1929 1815 2772 1879
+rect 1929 1257 2496 1321
+rect 1780 810 2376 821
+rect 1780 750 1793 810
+rect 2362 750 2376 810
+rect 1780 738 2376 750
+rect 1643 440 1764 496
+rect 1708 -84 1764 440
+rect 1915 247 2348 311
+rect 2044 -84 2100 247
+rect 2440 174 2496 1257
+rect 2380 118 2496 174
+rect 2380 -84 2436 118
+rect 2716 -84 2772 1815
+rect 2921 1815 3468 1879
+rect 2921 177 2977 1815
+rect 3041 1257 3780 1321
+rect 3043 247 3462 311
+rect 2921 121 3108 177
+rect 3052 -84 3108 121
+rect 3388 -84 3444 247
+rect 3724 -84 3780 1257
+<< via2 >>
+rect 83 3110 652 3170
+rect 83 1540 652 1600
+rect 92 -29 621 31
+rect 1793 2330 2362 2390
+rect 1793 750 2362 810
+<< metal3 >>
+rect 66 3170 672 3192
+rect 66 3110 83 3170
+rect 652 3110 672 3170
+rect 66 1600 672 3110
+rect 66 1540 83 1600
+rect 652 1540 672 1600
+rect 66 31 672 1540
+rect 66 -29 92 31
+rect 621 -29 672 31
+rect 66 -53 672 -29
+rect 1773 2390 2379 3192
+rect 1773 2330 1793 2390
+rect 2362 2330 2379 2390
+rect 1773 810 2379 2330
+rect 1773 750 1793 810
+rect 2362 750 2379 810
+rect 1773 -53 2379 750
+use gf180mcu_fd_sc_mcu7t5v0__endcap ENDCAP_0 $PDK_ROOT/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag
+timestamp 1669862171
+transform 1 0 0 0 1 0
+box -86 -86 310 870
+use gf180mcu_fd_sc_mcu7t5v0__endcap ENDCAP_1
+timestamp 1669862171
+transform 1 0 2464 0 -1 3136
+box -86 -86 310 870
+use gf180mcu_fd_sc_mcu7t5v0__endcap ENDCAP_2
+timestamp 1669862171
+transform 1 0 3584 0 -1 3136
+box -86 -86 310 870
+use gf180mcu_fd_sc_mcu7t5v0__endcap ENDCAP_3
+timestamp 1669862171
+transform 1 0 0 0 -1 3136
+box -86 -86 310 870
+use gf180mcu_fd_sc_mcu7t5v0__endcap ENDCAP_4
+timestamp 1669862171
+transform 1 0 0 0 1 1568
+box -86 -86 310 870
+use gf180mcu_fd_sc_mcu7t5v0__endcap ENDCAP_5
+timestamp 1669862171
+transform 1 0 2464 0 1 1568
+box -86 -86 310 870
+use gf180mcu_fd_sc_mcu7t5v0__endcap ENDCAP_6
+timestamp 1669862171
+transform 1 0 3584 0 1 1568
+box -86 -86 310 870
+use gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLCAP_4_0 $PDK_ROOT/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag
+timestamp 1669862171
+transform 1 0 1120 0 1 0
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLCAP_4_1
+timestamp 1669862171
+transform 1 0 1120 0 -1 3136
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLCAP_4_2
+timestamp 1669862171
+transform 1 0 2016 0 -1 3136
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLCAP_4_3
+timestamp 1669862171
+transform 1 0 1120 0 -1 1568
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLCAP_4_4
+timestamp 1669862171
+transform 1 0 3136 0 -1 3136
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLCAP_4_5
+timestamp 1669862171
+transform 1 0 1568 0 -1 3136
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLCAP_4_6
+timestamp 1669862171
+transform 1 0 1120 0 1 1568
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLCAP_4_7
+timestamp 1669862171
+transform 1 0 2688 0 -1 3136
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__filltie FILLTIE_0 $PDK_ROOT/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag
+timestamp 1669862171
+transform 1 0 2464 0 1 0
+box -86 -86 310 870
+use gf180mcu_fd_sc_mcu7t5v0__filltie FILLTIE_1
+timestamp 1669862171
+transform 1 0 3584 0 1 0
+box -86 -86 310 870
+use gf180mcu_fd_sc_mcu7t5v0__filltie FILLTIE_2
+timestamp 1669862171
+transform 1 0 3584 0 -1 1568
+box -86 -86 310 870
+use gf180mcu_fd_sc_mcu7t5v0__filltie FILLTIE_4
+timestamp 1669862171
+transform 1 0 0 0 -1 1568
+box -86 -86 310 870
+use gf180mcu_fd_sc_mcu7t5v0__filltie FILLTIE_5
+timestamp 1669862171
+transform 1 0 2464 0 -1 1568
+box -86 -86 310 870
+use gf180mcu_fd_sc_mcu7t5v0__tieh gpio_default_value_one[0] $PDK_ROOT/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag
+timestamp 1669862171
+transform 1 0 224 0 1 0
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__tieh gpio_default_value_one[1]
+timestamp 1669862171
+transform 1 0 224 0 -1 1568
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__tieh gpio_default_value_one[2]
+timestamp 1669862171
+transform 1 0 224 0 1 1568
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__tieh gpio_default_value_one[3]
+timestamp 1669862171
+transform 1 0 224 0 -1 3136
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__tieh gpio_default_value_one[4]
+timestamp 1669862171
+transform 1 0 1568 0 1 0
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__tieh gpio_default_value_one[5]
+timestamp 1669862171
+transform 1 0 1568 0 -1 1568
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__tieh gpio_default_value_one[6]
+timestamp 1669862171
+transform 1 0 1568 0 1 1568
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__tieh gpio_default_value_one[8]
+timestamp 1669862171
+transform 1 0 2688 0 1 0
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__tieh gpio_default_value_one[9]
+timestamp 1669862171
+transform 1 0 2688 0 -1 1568
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__tieh gpio_default_value_one[7]
+timestamp 1669862171
+transform 1 0 2688 0 1 1568
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__tiel gpio_default_value_zero[0] $PDK_ROOT/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag
+timestamp 1669862171
+transform 1 0 672 0 1 0
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__tiel gpio_default_value_zero[1]
+timestamp 1669862171
+transform 1 0 672 0 -1 1568
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__tiel gpio_default_value_zero[2]
+timestamp 1669862171
+transform 1 0 672 0 1 1568
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__tiel gpio_default_value_zero[3]
+timestamp 1669862171
+transform 1 0 672 0 -1 3136
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__tiel gpio_default_value_zero[4]
+timestamp 1669862171
+transform 1 0 2016 0 1 0
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__tiel gpio_default_value_zero[5]
+timestamp 1669862171
+transform 1 0 2016 0 -1 1568
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__tiel gpio_default_value_zero[6]
+timestamp 1669862171
+transform 1 0 2016 0 1 1568
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__tiel gpio_default_value_zero[8]
+timestamp 1669862171
+transform 1 0 3136 0 1 0
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__tiel gpio_default_value_zero[9]
+timestamp 1669862171
+transform 1 0 3136 0 -1 1568
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__tiel gpio_default_value_zero[7]
+timestamp 1669862171
+transform 1 0 3136 0 1 1568
+box -86 -86 534 870
+<< labels >>
+flabel metal3 1773 -53 2379 750 0 FreeSans 1600 0 0 0 VDD
+port 11 nsew
+flabel metal3 66 55 672 858 0 FreeSans 1600 0 0 0 VSS
+port 12 nsew
+flabel metal2 700 -84 756 150 0 FreeSans 400 90 0 0 gpio_defaults[0]
+port 1 nsew
+flabel metal2 1036 -84 1092 150 0 FreeSans 400 90 0 0 gpio_defaults[1]
+port 5 nsew
+flabel metal2 1372 -84 1428 150 0 FreeSans 400 90 0 0 gpio_defaults[2]
+port 9 nsew
+flabel metal2 1708 -84 1764 150 0 FreeSans 400 90 0 0 gpio_defaults[3]
+port 8 nsew
+flabel metal2 2044 -84 2100 150 0 FreeSans 400 90 0 0 gpio_defaults[4]
+port 2 nsew
+flabel metal2 2380 -84 2436 150 0 FreeSans 400 90 0 0 gpio_defaults[5]
+port 6 nsew
+flabel metal2 2716 -84 2772 150 0 FreeSans 400 90 0 0 gpio_defaults[6]
+port 10 nsew
+flabel metal2 3052 -84 3108 150 0 FreeSans 400 90 0 0 gpio_defaults[7]
+port 4 nsew
+flabel metal2 3388 -84 3444 150 0 FreeSans 400 90 0 0 gpio_defaults[8]
+port 3 nsew
+flabel metal2 3724 -84 3780 150 0 FreeSans 400 90 0 0 gpio_defaults[9]
+port 7 nsew
+<< end >>
diff --git a/tapeout/outputs/mag/gpio_defaults_block_087.mag b/tapeout/outputs/mag/gpio_defaults_block_087.mag
new file mode 100644
index 0000000..1771fff
--- /dev/null
+++ b/tapeout/outputs/mag/gpio_defaults_block_087.mag
@@ -0,0 +1,320 @@
+magic
+tech gf180mcuC
+magscale 1 10
+timestamp 1669928025
+<< metal1 >>
+rect 598 2766 673 3020
+rect 916 2806 991 3030
+rect 468 2694 673 2766
+rect 468 2675 540 2694
+rect 468 2010 540 2029
+rect 1812 2010 1884 2029
+rect 2932 2010 3004 2029
+rect 468 1938 673 2010
+rect 1812 1938 2017 2010
+rect 2932 1938 3137 2010
+rect 598 1684 673 1938
+rect 916 1674 991 1898
+rect 1942 1684 2017 1938
+rect 2260 1674 2335 1898
+rect 3062 1684 3137 1938
+rect 3380 1674 3455 1898
+rect 598 1198 673 1452
+rect 916 1238 991 1462
+rect 1942 1198 2017 1452
+rect 2260 1238 2335 1462
+rect 3062 1198 3137 1452
+rect 3380 1238 3455 1462
+rect 468 1126 673 1198
+rect 1812 1126 2017 1198
+rect 2932 1126 3137 1198
+rect 468 1107 540 1126
+rect 1812 1107 1884 1126
+rect 2932 1107 3004 1126
+rect 468 442 540 461
+rect 1812 442 1884 461
+rect 2932 442 3004 461
+rect 468 370 673 442
+rect 1812 370 2017 442
+rect 2932 370 3137 442
+rect 598 116 673 370
+rect 916 106 991 330
+rect 1942 116 2017 370
+rect 2260 106 2335 330
+rect 3062 116 3137 370
+rect 3380 106 3455 330
+<< via1 >>
+rect 83 3110 652 3170
+rect 1793 2330 2362 2390
+rect 83 1540 652 1600
+rect 1793 750 2362 810
+rect 92 -29 621 31
+rect 923 2827 983 2887
+rect 605 1817 665 1877
+rect 2267 1817 2327 1877
+rect 3069 1817 3129 1877
+rect 605 1259 665 1319
+rect 2267 1259 2327 1319
+rect 3387 1259 3447 1319
+rect 605 249 665 309
+rect 2267 249 2327 309
+rect 3387 249 3447 309
+<< metal2 >>
+rect 70 3170 666 3181
+rect 70 3110 83 3170
+rect 652 3110 666 3170
+rect 70 3098 666 3110
+rect 576 2825 1699 2889
+rect 585 1815 1428 1879
+rect 70 1600 666 1611
+rect 70 1540 83 1600
+rect 652 1540 666 1600
+rect 70 1528 666 1540
+rect 585 1257 1132 1321
+rect 572 247 1004 311
+rect 80 31 633 43
+rect 80 -29 92 31
+rect 621 -29 633 31
+rect 80 -40 633 -29
+rect 700 -84 756 247
+rect 1076 157 1132 1257
+rect 1036 97 1132 157
+rect 1036 -84 1092 97
+rect 1372 -84 1428 1815
+rect 1643 496 1699 2825
+rect 1780 2390 2376 2401
+rect 1780 2330 1793 2390
+rect 2362 2330 2376 2390
+rect 1780 2318 2376 2330
+rect 1929 1815 2772 1879
+rect 1929 1257 2496 1321
+rect 1780 810 2376 821
+rect 1780 750 1793 810
+rect 2362 750 2376 810
+rect 1780 738 2376 750
+rect 1643 440 1764 496
+rect 1708 -84 1764 440
+rect 1915 247 2348 311
+rect 2044 -84 2100 247
+rect 2440 174 2496 1257
+rect 2380 118 2496 174
+rect 2380 -84 2436 118
+rect 2716 -84 2772 1815
+rect 2921 1815 3468 1879
+rect 2921 177 2977 1815
+rect 3041 1257 3780 1321
+rect 3043 247 3462 311
+rect 2921 121 3108 177
+rect 3052 -84 3108 121
+rect 3388 -84 3444 247
+rect 3724 -84 3780 1257
+<< via2 >>
+rect 83 3110 652 3170
+rect 83 1540 652 1600
+rect 92 -29 621 31
+rect 1793 2330 2362 2390
+rect 1793 750 2362 810
+<< metal3 >>
+rect 66 3170 672 3192
+rect 66 3110 83 3170
+rect 652 3110 672 3170
+rect 66 1600 672 3110
+rect 66 1540 83 1600
+rect 652 1540 672 1600
+rect 66 31 672 1540
+rect 66 -29 92 31
+rect 621 -29 672 31
+rect 66 -53 672 -29
+rect 1773 2390 2379 3192
+rect 1773 2330 1793 2390
+rect 2362 2330 2379 2390
+rect 1773 810 2379 2330
+rect 1773 750 1793 810
+rect 2362 750 2379 810
+rect 1773 -53 2379 750
+use gf180mcu_fd_sc_mcu7t5v0__endcap ENDCAP_0 $PDK_ROOT/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag
+timestamp 1669862171
+transform 1 0 0 0 1 0
+box -86 -86 310 870
+use gf180mcu_fd_sc_mcu7t5v0__endcap ENDCAP_1
+timestamp 1669862171
+transform 1 0 2464 0 -1 3136
+box -86 -86 310 870
+use gf180mcu_fd_sc_mcu7t5v0__endcap ENDCAP_2
+timestamp 1669862171
+transform 1 0 3584 0 -1 3136
+box -86 -86 310 870
+use gf180mcu_fd_sc_mcu7t5v0__endcap ENDCAP_3
+timestamp 1669862171
+transform 1 0 0 0 -1 3136
+box -86 -86 310 870
+use gf180mcu_fd_sc_mcu7t5v0__endcap ENDCAP_4
+timestamp 1669862171
+transform 1 0 0 0 1 1568
+box -86 -86 310 870
+use gf180mcu_fd_sc_mcu7t5v0__endcap ENDCAP_5
+timestamp 1669862171
+transform 1 0 2464 0 1 1568
+box -86 -86 310 870
+use gf180mcu_fd_sc_mcu7t5v0__endcap ENDCAP_6
+timestamp 1669862171
+transform 1 0 3584 0 1 1568
+box -86 -86 310 870
+use gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLCAP_4_0 $PDK_ROOT/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag
+timestamp 1669862171
+transform 1 0 1120 0 1 0
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLCAP_4_1
+timestamp 1669862171
+transform 1 0 1120 0 -1 3136
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLCAP_4_2
+timestamp 1669862171
+transform 1 0 2016 0 -1 3136
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLCAP_4_3
+timestamp 1669862171
+transform 1 0 1120 0 -1 1568
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLCAP_4_4
+timestamp 1669862171
+transform 1 0 3136 0 -1 3136
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLCAP_4_5
+timestamp 1669862171
+transform 1 0 1568 0 -1 3136
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLCAP_4_6
+timestamp 1669862171
+transform 1 0 1120 0 1 1568
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLCAP_4_7
+timestamp 1669862171
+transform 1 0 2688 0 -1 3136
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__filltie FILLTIE_0 $PDK_ROOT/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag
+timestamp 1669862171
+transform 1 0 2464 0 1 0
+box -86 -86 310 870
+use gf180mcu_fd_sc_mcu7t5v0__filltie FILLTIE_1
+timestamp 1669862171
+transform 1 0 3584 0 1 0
+box -86 -86 310 870
+use gf180mcu_fd_sc_mcu7t5v0__filltie FILLTIE_2
+timestamp 1669862171
+transform 1 0 3584 0 -1 1568
+box -86 -86 310 870
+use gf180mcu_fd_sc_mcu7t5v0__filltie FILLTIE_4
+timestamp 1669862171
+transform 1 0 0 0 -1 1568
+box -86 -86 310 870
+use gf180mcu_fd_sc_mcu7t5v0__filltie FILLTIE_5
+timestamp 1669862171
+transform 1 0 2464 0 -1 1568
+box -86 -86 310 870
+use gf180mcu_fd_sc_mcu7t5v0__tieh gpio_default_value_one[0] $PDK_ROOT/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag
+timestamp 1669862171
+transform 1 0 224 0 1 0
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__tieh gpio_default_value_one[1]
+timestamp 1669862171
+transform 1 0 224 0 -1 1568
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__tieh gpio_default_value_one[2]
+timestamp 1669862171
+transform 1 0 224 0 1 1568
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__tieh gpio_default_value_one[3]
+timestamp 1669862171
+transform 1 0 224 0 -1 3136
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__tieh gpio_default_value_one[4]
+timestamp 1669862171
+transform 1 0 1568 0 1 0
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__tieh gpio_default_value_one[5]
+timestamp 1669862171
+transform 1 0 1568 0 -1 1568
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__tieh gpio_default_value_one[6]
+timestamp 1669862171
+transform 1 0 1568 0 1 1568
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__tieh gpio_default_value_one[8]
+timestamp 1669862171
+transform 1 0 2688 0 1 0
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__tieh gpio_default_value_one[9]
+timestamp 1669862171
+transform 1 0 2688 0 -1 1568
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__tieh gpio_default_value_one[7]
+timestamp 1669862171
+transform 1 0 2688 0 1 1568
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__tiel gpio_default_value_zero[0] $PDK_ROOT/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag
+timestamp 1669862171
+transform 1 0 672 0 1 0
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__tiel gpio_default_value_zero[1]
+timestamp 1669862171
+transform 1 0 672 0 -1 1568
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__tiel gpio_default_value_zero[2]
+timestamp 1669862171
+transform 1 0 672 0 1 1568
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__tiel gpio_default_value_zero[3]
+timestamp 1669862171
+transform 1 0 672 0 -1 3136
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__tiel gpio_default_value_zero[4]
+timestamp 1669862171
+transform 1 0 2016 0 1 0
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__tiel gpio_default_value_zero[5]
+timestamp 1669862171
+transform 1 0 2016 0 -1 1568
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__tiel gpio_default_value_zero[6]
+timestamp 1669862171
+transform 1 0 2016 0 1 1568
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__tiel gpio_default_value_zero[8]
+timestamp 1669862171
+transform 1 0 3136 0 1 0
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__tiel gpio_default_value_zero[9]
+timestamp 1669862171
+transform 1 0 3136 0 -1 1568
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__tiel gpio_default_value_zero[7]
+timestamp 1669862171
+transform 1 0 3136 0 1 1568
+box -86 -86 534 870
+<< labels >>
+flabel metal3 1773 -53 2379 750 0 FreeSans 1600 0 0 0 VDD
+port 11 nsew
+flabel metal3 66 55 672 858 0 FreeSans 1600 0 0 0 VSS
+port 12 nsew
+flabel metal2 700 -84 756 150 0 FreeSans 400 90 0 0 gpio_defaults[0]
+port 1 nsew
+flabel metal2 1036 -84 1092 150 0 FreeSans 400 90 0 0 gpio_defaults[1]
+port 5 nsew
+flabel metal2 1372 -84 1428 150 0 FreeSans 400 90 0 0 gpio_defaults[2]
+port 9 nsew
+flabel metal2 1708 -84 1764 150 0 FreeSans 400 90 0 0 gpio_defaults[3]
+port 8 nsew
+flabel metal2 2044 -84 2100 150 0 FreeSans 400 90 0 0 gpio_defaults[4]
+port 2 nsew
+flabel metal2 2380 -84 2436 150 0 FreeSans 400 90 0 0 gpio_defaults[5]
+port 6 nsew
+flabel metal2 2716 -84 2772 150 0 FreeSans 400 90 0 0 gpio_defaults[6]
+port 10 nsew
+flabel metal2 3052 -84 3108 150 0 FreeSans 400 90 0 0 gpio_defaults[7]
+port 4 nsew
+flabel metal2 3388 -84 3444 150 0 FreeSans 400 90 0 0 gpio_defaults[8]
+port 3 nsew
+flabel metal2 3724 -84 3780 150 0 FreeSans 400 90 0 0 gpio_defaults[9]
+port 7 nsew
+<< end >>
diff --git a/tapeout/outputs/mag/user_id_prog_zero.mag b/tapeout/outputs/mag/user_id_prog_zero.mag
new file mode 100644
index 0000000..31a4c08
--- /dev/null
+++ b/tapeout/outputs/mag/user_id_prog_zero.mag
@@ -0,0 +1,928 @@
+magic
+tech gf180mcuC
+magscale 1 10
+timestamp 1669928529
+<< metal1 >>
+rect 1494 1198 1569 1452
+rect 1812 1238 1887 1462
+rect 2838 1198 2913 1452
+rect 3156 1238 3231 1462
+rect 3958 1198 4033 1452
+rect 4276 1238 4351 1462
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+rect 2838 116 2913 370
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+rect 8084 106 8159 330
+rect 8886 116 8961 370
+rect 9204 106 9279 330
+rect 10230 116 10305 370
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+rect 11350 116 11425 370
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+rect 12694 116 12769 370
+rect 13012 106 13087 330
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+rect 14132 106 14207 330
+rect 15158 116 15233 370
+rect 15476 106 15551 330
+rect 16278 116 16353 370
+rect 16596 106 16671 330
+rect 16722 201 16775 377
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+rect 18075 372 18135 384
+rect 18612 442 18684 461
+rect 19190 449 19250 461
+rect 16718 189 16778 201
+rect 16718 117 16778 129
+rect 17622 116 17697 370
+rect 17940 106 18015 330
+rect 18079 196 18132 372
+rect 18612 370 18817 442
+rect 19190 377 19250 389
+rect 19956 442 20028 461
+rect 20531 444 20591 456
+rect 18075 184 18135 196
+rect 18075 112 18135 124
+rect 18742 116 18817 370
+rect 19060 106 19135 330
+rect 19194 201 19247 377
+rect 19956 370 20161 442
+rect 20531 372 20591 384
+rect 19190 189 19250 201
+rect 19190 117 19250 129
+rect 20086 116 20161 370
+rect 20404 106 20479 330
+rect 20536 196 20589 372
+rect 20531 184 20591 196
+rect 20531 112 20591 124
+rect 1716 57 2009 60
+rect 2004 -57 2009 57
+rect 1716 -60 2009 -57
+<< via1 >>
+rect 1714 1510 2007 1624
+rect 10714 1510 11007 1624
+rect 19714 1510 20007 1624
+rect 1818 1258 1878 1318
+rect 3162 1258 3222 1318
+rect 4282 1258 4342 1318
+rect 5626 1258 5686 1318
+rect 6746 1258 6806 1318
+rect 8090 1258 8150 1318
+rect 9210 1258 9270 1318
+rect 10554 1258 10614 1318
+rect 11674 1258 11734 1318
+rect 13018 1258 13078 1318
+rect 14138 1258 14198 1318
+rect 15482 1258 15542 1318
+rect 16602 1258 16662 1318
+rect 17946 1258 18006 1318
+rect 19066 1258 19126 1318
+rect 20410 1258 20470 1318
+rect 6216 724 6506 844
+rect 15216 724 15506 844
+rect 16718 389 16778 449
+rect 1818 250 1878 310
+rect 3162 250 3222 310
+rect 4282 250 4342 310
+rect 5626 250 5686 310
+rect 6746 250 6806 310
+rect 8090 250 8150 310
+rect 9210 250 9270 310
+rect 10554 250 10614 310
+rect 11674 250 11734 310
+rect 13018 250 13078 310
+rect 14138 250 14198 310
+rect 15482 250 15542 310
+rect 16602 250 16662 310
+rect 18075 384 18135 444
+rect 16718 129 16778 189
+rect 17946 250 18006 310
+rect 19190 389 19250 449
+rect 18075 124 18135 184
+rect 19066 250 19126 310
+rect 20531 384 20591 444
+rect 19190 129 19250 189
+rect 20410 250 20470 310
+rect 20531 124 20591 184
+rect 1716 -57 2004 57
+rect 10716 -57 11004 57
+rect 19716 -57 20004 57
+<< metal2 >>
+rect 1701 1714 2021 1725
+rect 1701 1507 1714 1714
+rect 1703 1414 1714 1507
+rect 2007 1414 2021 1714
+rect 10703 1714 11021 1725
+rect 10703 1628 10714 1714
+rect 10701 1507 10714 1628
+rect 1703 1405 2021 1414
+rect 10703 1414 10714 1507
+rect 11007 1414 11021 1714
+rect 19703 1714 20021 1725
+rect 19703 1628 19714 1714
+rect 19701 1507 19714 1628
+rect 10703 1405 11021 1414
+rect 19703 1414 19714 1507
+rect 20007 1414 20021 1714
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+rect 1058 1256 1900 1320
+rect 2345 1256 3244 1320
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+rect 4747 1256 5708 1320
+rect 6074 1256 6828 1320
+rect 6972 1256 8172 1320
+rect 8428 1256 9294 1320
+rect 9772 1256 10634 1320
+rect 11228 1256 11754 1320
+rect 12572 1256 13098 1320
+rect 13632 1256 14218 1320
+rect 14985 1256 15560 1320
+rect 16264 1256 16778 1320
+rect 17609 1256 18133 1320
+rect 18730 1256 19248 1320
+rect 20073 1256 20589 1320
+rect 1058 488 1114 1256
+rect 28 432 1114 488
+rect 28 -420 84 432
+rect 700 248 1900 312
+rect 700 -420 756 248
+rect 2345 178 2401 1256
+rect 1484 122 2401 178
+rect 2549 248 3244 312
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+rect 1703 57 2020 60
+rect 1703 -57 1716 57
+rect 2004 -57 2020 57
+rect 2549 38 2605 248
+rect 3320 48 3376 1256
+rect 3478 248 4364 312
+rect 1703 -144 1726 -57
+rect 2000 -144 2020 -57
+rect 1703 -163 2020 -144
+rect 2156 -18 2605 38
+rect 2828 -8 3376 48
+rect 2156 -420 2212 -18
+rect 2828 -420 2884 -8
+rect 3500 -420 3556 248
+rect 4747 134 4803 1256
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+rect 4172 78 4803 134
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+rect 14985 121 15041 1256
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+rect 16722 451 16778 1256
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+rect 15145 248 16100 312
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+rect 20073 248 21700 312
+rect 14985 65 15428 121
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+rect 16044 -420 16100 248
+rect 16695 189 16797 191
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+rect 16778 129 16797 189
+rect 16716 127 16797 129
+rect 16716 -420 16772 127
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+rect 18063 184 18228 186
+rect 18063 124 18075 184
+rect 18135 124 18228 184
+rect 18063 122 18228 124
+rect 17495 -103 17556 -8
+rect 17500 -420 17556 -103
+rect 18172 -420 18228 122
+rect 18351 143 18407 248
+rect 19178 189 19572 191
+rect 18351 87 18900 143
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+rect 19250 135 19572 189
+rect 19250 129 19262 135
+rect 19178 126 19262 129
+rect 18844 -420 18900 87
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+rect 19743 179 19799 248
+rect 20519 184 20603 186
+rect 19743 123 20356 179
+rect 19703 57 20020 60
+rect 19703 -57 19716 57
+rect 20004 -57 20020 57
+rect 19703 -144 19726 -57
+rect 20000 -144 20020 -57
+rect 19703 -163 20020 -144
+rect 20300 -420 20356 123
+rect 20519 124 20531 184
+rect 20591 181 20603 184
+rect 20591 125 21028 181
+rect 20591 124 20603 125
+rect 20519 122 20603 124
+rect 20972 -420 21028 125
+rect 21644 -420 21700 248
+<< via2 >>
+rect 1714 1624 2007 1714
+rect 1714 1510 2007 1624
+rect 1714 1414 2007 1510
+rect 10714 1624 11007 1714
+rect 10714 1510 11007 1624
+rect 10714 1414 11007 1510
+rect 19714 1624 20007 1714
+rect 19714 1510 20007 1624
+rect 19714 1414 20007 1510
+rect 1726 -57 2000 51
+rect 1726 -144 2000 -57
+rect 6216 844 6506 942
+rect 6216 724 6506 844
+rect 6216 652 6506 724
+rect 10726 -57 11000 51
+rect 10726 -144 11000 -57
+rect 15216 844 15506 942
+rect 15216 724 15506 844
+rect 15216 652 15506 724
+rect 19726 -57 20000 51
+rect 19726 -144 20000 -57
+<< metal3 >>
+rect 1697 1714 2027 1732
+rect 1697 1414 1714 1714
+rect 2007 1414 2027 1714
+rect 1697 51 2027 1414
+rect 1697 -144 1726 51
+rect 2000 -144 2027 51
+rect 1697 -168 2027 -144
+rect 6197 942 6527 1732
+rect 6197 652 6216 942
+rect 6506 652 6527 942
+rect 6197 -168 6527 652
+rect 10697 1714 11027 1732
+rect 10697 1414 10714 1714
+rect 11007 1414 11027 1714
+rect 10697 51 11027 1414
+rect 10697 -144 10726 51
+rect 11000 -144 11027 51
+rect 10697 -168 11027 -144
+rect 15197 942 15527 1732
+rect 15197 652 15216 942
+rect 15506 652 15527 942
+rect 15197 -168 15527 652
+rect 19697 1714 20027 1732
+rect 19697 1414 19714 1714
+rect 20007 1414 20027 1714
+rect 19697 51 20027 1414
+rect 19697 -144 19726 51
+rect 20000 -144 20027 51
+rect 19697 -168 20027 -144
+use gf180mcu_fd_sc_mcu7t5v0__endcap ENDCAP_0 $PDK_ROOT/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag
+timestamp 1669862171
+transform 1 0 896 0 -1 1568
+box -86 -86 310 870
+use gf180mcu_fd_sc_mcu7t5v0__endcap ENDCAP_1
+timestamp 1669862171
+transform 1 0 20608 0 -1 1568
+box -86 -86 310 870
+use gf180mcu_fd_sc_mcu7t5v0__endcap ENDCAP_2
+timestamp 1669862171
+transform 1 0 20608 0 1 0
+box -86 -86 310 870
+use gf180mcu_fd_sc_mcu7t5v0__endcap ENDCAP_3
+timestamp 1669862171
+transform 1 0 896 0 1 0
+box -86 -86 310 870
+use gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLCAP_4_0 $PDK_ROOT/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag
+timestamp 1669862171
+transform 1 0 14336 0 1 0
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLCAP_4_1
+timestamp 1669862171
+transform 1 0 11872 0 1 0
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLCAP_4_2
+timestamp 1669862171
+transform 1 0 16800 0 1 0
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLCAP_4_3
+timestamp 1669862171
+transform 1 0 9408 0 1 0
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLCAP_4_4
+timestamp 1669862171
+transform 1 0 19264 0 1 0
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLCAP_4_5
+timestamp 1669862171
+transform 1 0 6944 0 1 0
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLCAP_4_6
+timestamp 1669862171
+transform 1 0 2016 0 -1 1568
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLCAP_4_7
+timestamp 1669862171
+transform 1 0 4480 0 1 0
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLCAP_4_8
+timestamp 1669862171
+transform 1 0 448 0 -1 1568
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLCAP_4_9
+timestamp 1669862171
+transform 1 0 448 0 1 0
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLCAP_4_10
+timestamp 1669862171
+transform 1 0 4480 0 -1 1568
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLCAP_4_11
+timestamp 1669862171
+transform 1 0 6944 0 -1 1568
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLCAP_4_12
+timestamp 1669862171
+transform 1 0 9408 0 -1 1568
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLCAP_4_13
+timestamp 1669862171
+transform 1 0 11872 0 -1 1568
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLCAP_4_14
+timestamp 1669862171
+transform 1 0 14336 0 -1 1568
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLCAP_4_15
+timestamp 1669862171
+transform 1 0 16800 0 -1 1568
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLCAP_4_16
+timestamp 1669862171
+transform 1 0 19264 0 -1 1568
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLCAP_4_17
+timestamp 1669862171
+transform 1 0 2016 0 1 0
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLCAP_4_18
+timestamp 1669862171
+transform 1 0 0 0 -1 1568
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLCAP_4_19
+timestamp 1669862171
+transform 1 0 0 0 1 0
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLCAP_4_20
+timestamp 1669862171
+transform 1 0 21280 0 -1 1568
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLCAP_4_21
+timestamp 1669862171
+transform 1 0 21280 0 1 0
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLCAP_4_22
+timestamp 1669862171
+transform 1 0 20832 0 -1 1568
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLCAP_4_23
+timestamp 1669862171
+transform 1 0 20832 0 1 0
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__filltie FILLTIE_0 $PDK_ROOT/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag
+timestamp 1669862171
+transform 1 0 13216 0 1 0
+box -86 -86 310 870
+use gf180mcu_fd_sc_mcu7t5v0__filltie FILLTIE_1
+timestamp 1669862171
+transform 1 0 15680 0 1 0
+box -86 -86 310 870
+use gf180mcu_fd_sc_mcu7t5v0__filltie FILLTIE_2
+timestamp 1669862171
+transform 1 0 18144 0 1 0
+box -86 -86 310 870
+use gf180mcu_fd_sc_mcu7t5v0__filltie FILLTIE_4
+timestamp 1669862171
+transform 1 0 10752 0 1 0
+box -86 -86 310 870
+use gf180mcu_fd_sc_mcu7t5v0__filltie FILLTIE_5
+timestamp 1669862171
+transform 1 0 8288 0 1 0
+box -86 -86 310 870
+use gf180mcu_fd_sc_mcu7t5v0__filltie FILLTIE_6
+timestamp 1669862171
+transform 1 0 5824 0 1 0
+box -86 -86 310 870
+use gf180mcu_fd_sc_mcu7t5v0__filltie FILLTIE_7
+timestamp 1669862171
+transform 1 0 3360 0 1 0
+box -86 -86 310 870
+use gf180mcu_fd_sc_mcu7t5v0__filltie FILLTIE_8
+timestamp 1669862171
+transform 1 0 3360 0 -1 1568
+box -86 -86 310 870
+use gf180mcu_fd_sc_mcu7t5v0__filltie FILLTIE_9
+timestamp 1669862171
+transform 1 0 5824 0 -1 1568
+box -86 -86 310 870
+use gf180mcu_fd_sc_mcu7t5v0__filltie FILLTIE_10
+timestamp 1669862171
+transform 1 0 8288 0 -1 1568
+box -86 -86 310 870
+use gf180mcu_fd_sc_mcu7t5v0__filltie FILLTIE_11
+timestamp 1669862171
+transform 1 0 10752 0 -1 1568
+box -86 -86 310 870
+use gf180mcu_fd_sc_mcu7t5v0__filltie FILLTIE_12
+timestamp 1669862171
+transform 1 0 13216 0 -1 1568
+box -86 -86 310 870
+use gf180mcu_fd_sc_mcu7t5v0__filltie FILLTIE_13
+timestamp 1669862171
+transform 1 0 15680 0 -1 1568
+box -86 -86 310 870
+use gf180mcu_fd_sc_mcu7t5v0__filltie FILLTIE_14
+timestamp 1669862171
+transform 1 0 18144 0 -1 1568
+box -86 -86 310 870
+use gf180mcu_fd_sc_mcu7t5v0__tieh mask_rev_value_one[0] $PDK_ROOT/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag
+timestamp 1669862171
+transform 1 0 1120 0 -1 1568
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__tieh mask_rev_value_one[1]
+timestamp 1669862171
+transform 1 0 1120 0 1 0
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__tieh mask_rev_value_one[2]
+timestamp 1669862171
+transform 1 0 2464 0 -1 1568
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__tieh mask_rev_value_one[3]
+timestamp 1669862171
+transform 1 0 2464 0 1 0
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__tieh mask_rev_value_one[4]
+timestamp 1669862171
+transform 1 0 3584 0 -1 1568
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__tieh mask_rev_value_one[5]
+timestamp 1669862171
+transform 1 0 3584 0 1 0
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__tieh mask_rev_value_one[6]
+timestamp 1669862171
+transform 1 0 4928 0 -1 1568
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__tieh mask_rev_value_one[7]
+timestamp 1669862171
+transform 1 0 4928 0 1 0
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__tieh mask_rev_value_one[8]
+timestamp 1669862171
+transform 1 0 6048 0 -1 1568
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__tieh mask_rev_value_one[9]
+timestamp 1669862171
+transform 1 0 6048 0 1 0
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__tieh mask_rev_value_one[10]
+timestamp 1669862171
+transform 1 0 7392 0 -1 1568
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__tieh mask_rev_value_one[11]
+timestamp 1669862171
+transform 1 0 7392 0 1 0
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__tieh mask_rev_value_one[12]
+timestamp 1669862171
+transform 1 0 8512 0 -1 1568
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__tieh mask_rev_value_one[13]
+timestamp 1669862171
+transform 1 0 8512 0 1 0
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__tieh mask_rev_value_one[14]
+timestamp 1669862171
+transform 1 0 9856 0 -1 1568
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__tieh mask_rev_value_one[15]
+timestamp 1669862171
+transform 1 0 9856 0 1 0
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__tieh mask_rev_value_one[16]
+timestamp 1669862171
+transform 1 0 10976 0 -1 1568
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__tieh mask_rev_value_one[17]
+timestamp 1669862171
+transform 1 0 10976 0 1 0
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__tieh mask_rev_value_one[18]
+timestamp 1669862171
+transform 1 0 12320 0 -1 1568
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__tieh mask_rev_value_one[19]
+timestamp 1669862171
+transform 1 0 12320 0 1 0
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__tieh mask_rev_value_one[20]
+timestamp 1669862171
+transform 1 0 13440 0 -1 1568
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__tieh mask_rev_value_one[21]
+timestamp 1669862171
+transform 1 0 13440 0 1 0
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__tieh mask_rev_value_one[22]
+timestamp 1669862171
+transform 1 0 14784 0 -1 1568
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__tieh mask_rev_value_one[23]
+timestamp 1669862171
+transform 1 0 14784 0 1 0
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__tieh mask_rev_value_one[24]
+timestamp 1669862171
+transform 1 0 15904 0 -1 1568
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__tieh mask_rev_value_one[25]
+timestamp 1669862171
+transform 1 0 15904 0 1 0
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__tieh mask_rev_value_one[26]
+timestamp 1669862171
+transform 1 0 17248 0 -1 1568
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__tieh mask_rev_value_one[27]
+timestamp 1669862171
+transform 1 0 17248 0 1 0
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__tieh mask_rev_value_one[28]
+timestamp 1669862171
+transform 1 0 18368 0 -1 1568
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__tieh mask_rev_value_one[29]
+timestamp 1669862171
+transform 1 0 18368 0 1 0
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__tieh mask_rev_value_one[30]
+timestamp 1669862171
+transform 1 0 19712 0 -1 1568
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__tieh mask_rev_value_one[31]
+timestamp 1669862171
+transform 1 0 19712 0 1 0
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__tiel mask_rev_value_zero[0] $PDK_ROOT/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag
+timestamp 1669862171
+transform 1 0 1568 0 -1 1568
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__tiel mask_rev_value_zero[1]
+timestamp 1669862171
+transform 1 0 1568 0 1 0
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__tiel mask_rev_value_zero[2]
+timestamp 1669862171
+transform 1 0 2912 0 -1 1568
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__tiel mask_rev_value_zero[3]
+timestamp 1669862171
+transform 1 0 2912 0 1 0
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__tiel mask_rev_value_zero[4]
+timestamp 1669862171
+transform 1 0 4032 0 -1 1568
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__tiel mask_rev_value_zero[5]
+timestamp 1669862171
+transform 1 0 4032 0 1 0
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__tiel mask_rev_value_zero[6]
+timestamp 1669862171
+transform 1 0 5376 0 -1 1568
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__tiel mask_rev_value_zero[7]
+timestamp 1669862171
+transform 1 0 5376 0 1 0
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__tiel mask_rev_value_zero[8]
+timestamp 1669862171
+transform 1 0 6496 0 -1 1568
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__tiel mask_rev_value_zero[9]
+timestamp 1669862171
+transform 1 0 6496 0 1 0
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__tiel mask_rev_value_zero[10]
+timestamp 1669862171
+transform 1 0 7840 0 -1 1568
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__tiel mask_rev_value_zero[11]
+timestamp 1669862171
+transform 1 0 7840 0 1 0
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__tiel mask_rev_value_zero[12]
+timestamp 1669862171
+transform 1 0 8960 0 -1 1568
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__tiel mask_rev_value_zero[13]
+timestamp 1669862171
+transform 1 0 8960 0 1 0
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__tiel mask_rev_value_zero[14]
+timestamp 1669862171
+transform 1 0 10304 0 -1 1568
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__tiel mask_rev_value_zero[15]
+timestamp 1669862171
+transform 1 0 10304 0 1 0
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__tiel mask_rev_value_zero[16]
+timestamp 1669862171
+transform 1 0 11424 0 -1 1568
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__tiel mask_rev_value_zero[17]
+timestamp 1669862171
+transform 1 0 11424 0 1 0
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__tiel mask_rev_value_zero[18]
+timestamp 1669862171
+transform 1 0 12768 0 -1 1568
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__tiel mask_rev_value_zero[19]
+timestamp 1669862171
+transform 1 0 12768 0 1 0
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__tiel mask_rev_value_zero[20]
+timestamp 1669862171
+transform 1 0 13888 0 -1 1568
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__tiel mask_rev_value_zero[21]
+timestamp 1669862171
+transform 1 0 13888 0 1 0
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__tiel mask_rev_value_zero[22]
+timestamp 1669862171
+transform 1 0 15232 0 -1 1568
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__tiel mask_rev_value_zero[23]
+timestamp 1669862171
+transform 1 0 15232 0 1 0
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__tiel mask_rev_value_zero[24]
+timestamp 1669862171
+transform 1 0 16352 0 -1 1568
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__tiel mask_rev_value_zero[25]
+timestamp 1669862171
+transform 1 0 16352 0 1 0
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__tiel mask_rev_value_zero[26]
+timestamp 1669862171
+transform 1 0 17696 0 -1 1568
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__tiel mask_rev_value_zero[27]
+timestamp 1669862171
+transform 1 0 17696 0 1 0
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__tiel mask_rev_value_zero[28]
+timestamp 1669862171
+transform 1 0 18816 0 -1 1568
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__tiel mask_rev_value_zero[29]
+timestamp 1669862171
+transform 1 0 18816 0 1 0
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__tiel mask_rev_value_zero[30]
+timestamp 1669862171
+transform 1 0 20160 0 -1 1568
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__tiel mask_rev_value_zero[31]
+timestamp 1669862171
+transform 1 0 20160 0 1 0
+box -86 -86 534 870
+<< labels >>
+flabel metal3 6197 -168 6527 162 0 FreeSans 1600 0 0 0 VDD
+port 32 nsew
+flabel metal3 10697 51 11027 1414 0 FreeSans 1600 0 0 0 VSS
+port 33 nsew
+flabel metal2 28 -420 84 -10 0 FreeSans 400 90 0 0 mask_rev[0]
+port 0 nsew
+flabel metal2 700 -420 756 -10 0 FreeSans 400 90 0 0 mask_rev[1]
+port 11 nsew
+flabel metal2 1484 -420 1540 -10 0 FreeSans 400 90 0 0 mask_rev[2]
+port 22 nsew
+flabel metal2 2156 -420 2212 -10 0 FreeSans 400 90 0 0 mask_rev[3]
+port 25 nsew
+flabel metal2 2828 -420 2884 -10 0 FreeSans 400 90 0 0 mask_rev[4]
+port 26 nsew
+flabel metal2 3500 -420 3556 -10 0 FreeSans 400 90 0 0 mask_rev[5]
+port 27 nsew
+flabel metal2 4172 -420 4228 -10 0 FreeSans 400 90 0 0 mask_rev[6]
+port 28 nsew
+flabel metal2 4956 -420 5012 -10 0 FreeSans 400 90 0 0 mask_rev[7]
+port 29 nsew
+flabel metal2 5628 -420 5684 -10 0 FreeSans 400 90 0 0 mask_rev[8]
+port 30 nsew
+flabel metal2 6300 -420 6356 -10 0 FreeSans 400 90 0 0 mask_rev[9]
+port 31 nsew
+flabel metal2 6972 -420 7028 -10 0 FreeSans 400 90 0 0 mask_rev[10]
+port 1 nsew
+flabel metal2 7756 -420 7812 -10 0 FreeSans 400 90 0 0 mask_rev[11]
+port 2 nsew
+flabel metal2 8428 -420 8484 -10 0 FreeSans 400 90 0 0 mask_rev[12]
+port 3 nsew
+flabel metal2 9100 -420 9156 -10 0 FreeSans 400 90 0 0 mask_rev[13]
+port 4 nsew
+flabel metal2 9772 -420 9828 -10 0 FreeSans 400 90 0 0 mask_rev[14]
+port 5 nsew
+flabel metal2 10444 -420 10500 -10 0 FreeSans 400 90 0 0 mask_rev[15]
+port 6 nsew
+flabel metal2 11228 -420 11284 -10 0 FreeSans 400 90 0 0 mask_rev[16]
+port 7 nsew
+flabel metal2 11900 -420 11956 -10 0 FreeSans 400 90 0 0 mask_rev[17]
+port 8 nsew
+flabel metal2 12572 -420 12628 -10 0 FreeSans 400 90 0 0 mask_rev[18]
+port 9 nsew
+flabel metal2 13244 -420 13300 -10 0 FreeSans 400 90 0 0 mask_rev[19]
+port 10 nsew
+flabel metal2 14028 -420 14084 -10 0 FreeSans 400 90 0 0 mask_rev[20]
+port 12 nsew
+flabel metal2 14700 -420 14756 -10 0 FreeSans 400 90 0 0 mask_rev[21]
+port 13 nsew
+flabel metal2 15372 -420 15428 -10 0 FreeSans 400 90 0 0 mask_rev[22]
+port 14 nsew
+flabel metal2 16044 -420 16100 -10 0 FreeSans 400 90 0 0 mask_rev[23]
+port 15 nsew
+flabel metal2 16716 -420 16772 -10 0 FreeSans 400 90 0 0 mask_rev[24]
+port 16 nsew
+flabel metal2 17500 -420 17556 -10 0 FreeSans 400 90 0 0 mask_rev[25]
+port 17 nsew
+flabel metal2 18172 -420 18228 -10 0 FreeSans 400 90 0 0 mask_rev[26]
+port 18 nsew
+flabel metal2 18844 -420 18900 -10 0 FreeSans 400 90 0 0 mask_rev[27]
+port 19 nsew
+flabel metal2 19516 -420 19572 -10 0 FreeSans 400 90 0 0 mask_rev[28]
+port 20 nsew
+flabel metal2 20300 -420 20356 -10 0 FreeSans 400 90 0 0 mask_rev[29]
+port 21 nsew
+flabel metal2 20972 -420 21028 -10 0 FreeSans 400 90 0 0 mask_rev[30]
+port 23 nsew
+flabel metal2 21644 -420 21700 -10 0 FreeSans 400 90 0 0 mask_rev[31]
+port 24 nsew
+<< end >>
diff --git a/tapeout/outputs/mag/user_id_programming.mag b/tapeout/outputs/mag/user_id_programming.mag
new file mode 100644
index 0000000..ea19298
--- /dev/null
+++ b/tapeout/outputs/mag/user_id_programming.mag
@@ -0,0 +1,928 @@
+magic
+tech gf180mcuC
+magscale 1 10
+timestamp 1669928529
+<< metal1 >>
+rect 1494 1198 1569 1452
+rect 1812 1238 1887 1462
+rect 2838 1198 2913 1452
+rect 3156 1238 3231 1462
+rect 3958 1198 4033 1452
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+<< metal3 >>
+rect 1697 1714 2027 1732
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+rect 19697 -168 20027 -144
+use gf180mcu_fd_sc_mcu7t5v0__endcap ENDCAP_0 $PDK_ROOT/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag
+timestamp 1669862171
+transform 1 0 896 0 -1 1568
+box -86 -86 310 870
+use gf180mcu_fd_sc_mcu7t5v0__endcap ENDCAP_1
+timestamp 1669862171
+transform 1 0 20608 0 -1 1568
+box -86 -86 310 870
+use gf180mcu_fd_sc_mcu7t5v0__endcap ENDCAP_2
+timestamp 1669862171
+transform 1 0 20608 0 1 0
+box -86 -86 310 870
+use gf180mcu_fd_sc_mcu7t5v0__endcap ENDCAP_3
+timestamp 1669862171
+transform 1 0 896 0 1 0
+box -86 -86 310 870
+use gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLCAP_4_0 $PDK_ROOT/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag
+timestamp 1669862171
+transform 1 0 14336 0 1 0
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLCAP_4_1
+timestamp 1669862171
+transform 1 0 11872 0 1 0
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLCAP_4_2
+timestamp 1669862171
+transform 1 0 16800 0 1 0
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLCAP_4_3
+timestamp 1669862171
+transform 1 0 9408 0 1 0
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLCAP_4_4
+timestamp 1669862171
+transform 1 0 19264 0 1 0
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLCAP_4_5
+timestamp 1669862171
+transform 1 0 6944 0 1 0
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLCAP_4_6
+timestamp 1669862171
+transform 1 0 2016 0 -1 1568
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLCAP_4_7
+timestamp 1669862171
+transform 1 0 4480 0 1 0
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLCAP_4_8
+timestamp 1669862171
+transform 1 0 448 0 -1 1568
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLCAP_4_9
+timestamp 1669862171
+transform 1 0 448 0 1 0
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLCAP_4_10
+timestamp 1669862171
+transform 1 0 4480 0 -1 1568
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLCAP_4_11
+timestamp 1669862171
+transform 1 0 6944 0 -1 1568
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLCAP_4_12
+timestamp 1669862171
+transform 1 0 9408 0 -1 1568
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLCAP_4_13
+timestamp 1669862171
+transform 1 0 11872 0 -1 1568
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLCAP_4_14
+timestamp 1669862171
+transform 1 0 14336 0 -1 1568
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLCAP_4_15
+timestamp 1669862171
+transform 1 0 16800 0 -1 1568
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLCAP_4_16
+timestamp 1669862171
+transform 1 0 19264 0 -1 1568
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLCAP_4_17
+timestamp 1669862171
+transform 1 0 2016 0 1 0
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLCAP_4_18
+timestamp 1669862171
+transform 1 0 0 0 -1 1568
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLCAP_4_19
+timestamp 1669862171
+transform 1 0 0 0 1 0
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLCAP_4_20
+timestamp 1669862171
+transform 1 0 21280 0 -1 1568
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLCAP_4_21
+timestamp 1669862171
+transform 1 0 21280 0 1 0
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLCAP_4_22
+timestamp 1669862171
+transform 1 0 20832 0 -1 1568
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLCAP_4_23
+timestamp 1669862171
+transform 1 0 20832 0 1 0
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__filltie FILLTIE_0 $PDK_ROOT/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag
+timestamp 1669862171
+transform 1 0 13216 0 1 0
+box -86 -86 310 870
+use gf180mcu_fd_sc_mcu7t5v0__filltie FILLTIE_1
+timestamp 1669862171
+transform 1 0 15680 0 1 0
+box -86 -86 310 870
+use gf180mcu_fd_sc_mcu7t5v0__filltie FILLTIE_2
+timestamp 1669862171
+transform 1 0 18144 0 1 0
+box -86 -86 310 870
+use gf180mcu_fd_sc_mcu7t5v0__filltie FILLTIE_4
+timestamp 1669862171
+transform 1 0 10752 0 1 0
+box -86 -86 310 870
+use gf180mcu_fd_sc_mcu7t5v0__filltie FILLTIE_5
+timestamp 1669862171
+transform 1 0 8288 0 1 0
+box -86 -86 310 870
+use gf180mcu_fd_sc_mcu7t5v0__filltie FILLTIE_6
+timestamp 1669862171
+transform 1 0 5824 0 1 0
+box -86 -86 310 870
+use gf180mcu_fd_sc_mcu7t5v0__filltie FILLTIE_7
+timestamp 1669862171
+transform 1 0 3360 0 1 0
+box -86 -86 310 870
+use gf180mcu_fd_sc_mcu7t5v0__filltie FILLTIE_8
+timestamp 1669862171
+transform 1 0 3360 0 -1 1568
+box -86 -86 310 870
+use gf180mcu_fd_sc_mcu7t5v0__filltie FILLTIE_9
+timestamp 1669862171
+transform 1 0 5824 0 -1 1568
+box -86 -86 310 870
+use gf180mcu_fd_sc_mcu7t5v0__filltie FILLTIE_10
+timestamp 1669862171
+transform 1 0 8288 0 -1 1568
+box -86 -86 310 870
+use gf180mcu_fd_sc_mcu7t5v0__filltie FILLTIE_11
+timestamp 1669862171
+transform 1 0 10752 0 -1 1568
+box -86 -86 310 870
+use gf180mcu_fd_sc_mcu7t5v0__filltie FILLTIE_12
+timestamp 1669862171
+transform 1 0 13216 0 -1 1568
+box -86 -86 310 870
+use gf180mcu_fd_sc_mcu7t5v0__filltie FILLTIE_13
+timestamp 1669862171
+transform 1 0 15680 0 -1 1568
+box -86 -86 310 870
+use gf180mcu_fd_sc_mcu7t5v0__filltie FILLTIE_14
+timestamp 1669862171
+transform 1 0 18144 0 -1 1568
+box -86 -86 310 870
+use gf180mcu_fd_sc_mcu7t5v0__tieh mask_rev_value_one[0] $PDK_ROOT/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag
+timestamp 1669862171
+transform 1 0 1120 0 -1 1568
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__tieh mask_rev_value_one[1]
+timestamp 1669862171
+transform 1 0 1120 0 1 0
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__tieh mask_rev_value_one[2]
+timestamp 1669862171
+transform 1 0 2464 0 -1 1568
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__tieh mask_rev_value_one[3]
+timestamp 1669862171
+transform 1 0 2464 0 1 0
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__tieh mask_rev_value_one[4]
+timestamp 1669862171
+transform 1 0 3584 0 -1 1568
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__tieh mask_rev_value_one[5]
+timestamp 1669862171
+transform 1 0 3584 0 1 0
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__tieh mask_rev_value_one[6]
+timestamp 1669862171
+transform 1 0 4928 0 -1 1568
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__tieh mask_rev_value_one[7]
+timestamp 1669862171
+transform 1 0 4928 0 1 0
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__tieh mask_rev_value_one[8]
+timestamp 1669862171
+transform 1 0 6048 0 -1 1568
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__tieh mask_rev_value_one[9]
+timestamp 1669862171
+transform 1 0 6048 0 1 0
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__tieh mask_rev_value_one[10]
+timestamp 1669862171
+transform 1 0 7392 0 -1 1568
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__tieh mask_rev_value_one[11]
+timestamp 1669862171
+transform 1 0 7392 0 1 0
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__tieh mask_rev_value_one[12]
+timestamp 1669862171
+transform 1 0 8512 0 -1 1568
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__tieh mask_rev_value_one[13]
+timestamp 1669862171
+transform 1 0 8512 0 1 0
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__tieh mask_rev_value_one[14]
+timestamp 1669862171
+transform 1 0 9856 0 -1 1568
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__tieh mask_rev_value_one[15]
+timestamp 1669862171
+transform 1 0 9856 0 1 0
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__tieh mask_rev_value_one[16]
+timestamp 1669862171
+transform 1 0 10976 0 -1 1568
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__tieh mask_rev_value_one[17]
+timestamp 1669862171
+transform 1 0 10976 0 1 0
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__tieh mask_rev_value_one[18]
+timestamp 1669862171
+transform 1 0 12320 0 -1 1568
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__tieh mask_rev_value_one[19]
+timestamp 1669862171
+transform 1 0 12320 0 1 0
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__tieh mask_rev_value_one[20]
+timestamp 1669862171
+transform 1 0 13440 0 -1 1568
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__tieh mask_rev_value_one[21]
+timestamp 1669862171
+transform 1 0 13440 0 1 0
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__tieh mask_rev_value_one[22]
+timestamp 1669862171
+transform 1 0 14784 0 -1 1568
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__tieh mask_rev_value_one[23]
+timestamp 1669862171
+transform 1 0 14784 0 1 0
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__tieh mask_rev_value_one[24]
+timestamp 1669862171
+transform 1 0 15904 0 -1 1568
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__tieh mask_rev_value_one[25]
+timestamp 1669862171
+transform 1 0 15904 0 1 0
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__tieh mask_rev_value_one[26]
+timestamp 1669862171
+transform 1 0 17248 0 -1 1568
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__tieh mask_rev_value_one[27]
+timestamp 1669862171
+transform 1 0 17248 0 1 0
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__tieh mask_rev_value_one[28]
+timestamp 1669862171
+transform 1 0 18368 0 -1 1568
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__tieh mask_rev_value_one[29]
+timestamp 1669862171
+transform 1 0 18368 0 1 0
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__tieh mask_rev_value_one[30]
+timestamp 1669862171
+transform 1 0 19712 0 -1 1568
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__tieh mask_rev_value_one[31]
+timestamp 1669862171
+transform 1 0 19712 0 1 0
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__tiel mask_rev_value_zero[0] $PDK_ROOT/$PDK/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag
+timestamp 1669862171
+transform 1 0 1568 0 -1 1568
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__tiel mask_rev_value_zero[1]
+timestamp 1669862171
+transform 1 0 1568 0 1 0
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__tiel mask_rev_value_zero[2]
+timestamp 1669862171
+transform 1 0 2912 0 -1 1568
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__tiel mask_rev_value_zero[3]
+timestamp 1669862171
+transform 1 0 2912 0 1 0
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__tiel mask_rev_value_zero[4]
+timestamp 1669862171
+transform 1 0 4032 0 -1 1568
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__tiel mask_rev_value_zero[5]
+timestamp 1669862171
+transform 1 0 4032 0 1 0
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__tiel mask_rev_value_zero[6]
+timestamp 1669862171
+transform 1 0 5376 0 -1 1568
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__tiel mask_rev_value_zero[7]
+timestamp 1669862171
+transform 1 0 5376 0 1 0
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__tiel mask_rev_value_zero[8]
+timestamp 1669862171
+transform 1 0 6496 0 -1 1568
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__tiel mask_rev_value_zero[9]
+timestamp 1669862171
+transform 1 0 6496 0 1 0
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__tiel mask_rev_value_zero[10]
+timestamp 1669862171
+transform 1 0 7840 0 -1 1568
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__tiel mask_rev_value_zero[11]
+timestamp 1669862171
+transform 1 0 7840 0 1 0
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__tiel mask_rev_value_zero[12]
+timestamp 1669862171
+transform 1 0 8960 0 -1 1568
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__tiel mask_rev_value_zero[13]
+timestamp 1669862171
+transform 1 0 8960 0 1 0
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__tiel mask_rev_value_zero[14]
+timestamp 1669862171
+transform 1 0 10304 0 -1 1568
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__tiel mask_rev_value_zero[15]
+timestamp 1669862171
+transform 1 0 10304 0 1 0
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__tiel mask_rev_value_zero[16]
+timestamp 1669862171
+transform 1 0 11424 0 -1 1568
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__tiel mask_rev_value_zero[17]
+timestamp 1669862171
+transform 1 0 11424 0 1 0
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__tiel mask_rev_value_zero[18]
+timestamp 1669862171
+transform 1 0 12768 0 -1 1568
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__tiel mask_rev_value_zero[19]
+timestamp 1669862171
+transform 1 0 12768 0 1 0
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__tiel mask_rev_value_zero[20]
+timestamp 1669862171
+transform 1 0 13888 0 -1 1568
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__tiel mask_rev_value_zero[21]
+timestamp 1669862171
+transform 1 0 13888 0 1 0
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__tiel mask_rev_value_zero[22]
+timestamp 1669862171
+transform 1 0 15232 0 -1 1568
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__tiel mask_rev_value_zero[23]
+timestamp 1669862171
+transform 1 0 15232 0 1 0
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__tiel mask_rev_value_zero[24]
+timestamp 1669862171
+transform 1 0 16352 0 -1 1568
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__tiel mask_rev_value_zero[25]
+timestamp 1669862171
+transform 1 0 16352 0 1 0
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__tiel mask_rev_value_zero[26]
+timestamp 1669862171
+transform 1 0 17696 0 -1 1568
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__tiel mask_rev_value_zero[27]
+timestamp 1669862171
+transform 1 0 17696 0 1 0
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__tiel mask_rev_value_zero[28]
+timestamp 1669862171
+transform 1 0 18816 0 -1 1568
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__tiel mask_rev_value_zero[29]
+timestamp 1669862171
+transform 1 0 18816 0 1 0
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__tiel mask_rev_value_zero[30]
+timestamp 1669862171
+transform 1 0 20160 0 -1 1568
+box -86 -86 534 870
+use gf180mcu_fd_sc_mcu7t5v0__tiel mask_rev_value_zero[31]
+timestamp 1669862171
+transform 1 0 20160 0 1 0
+box -86 -86 534 870
+<< labels >>
+flabel metal3 6197 -168 6527 162 0 FreeSans 1600 0 0 0 VDD
+port 32 nsew
+flabel metal3 10697 51 11027 1414 0 FreeSans 1600 0 0 0 VSS
+port 33 nsew
+flabel metal2 28 -420 84 -10 0 FreeSans 400 90 0 0 mask_rev[0]
+port 0 nsew
+flabel metal2 700 -420 756 -10 0 FreeSans 400 90 0 0 mask_rev[1]
+port 11 nsew
+flabel metal2 1484 -420 1540 -10 0 FreeSans 400 90 0 0 mask_rev[2]
+port 22 nsew
+flabel metal2 2156 -420 2212 -10 0 FreeSans 400 90 0 0 mask_rev[3]
+port 25 nsew
+flabel metal2 2828 -420 2884 -10 0 FreeSans 400 90 0 0 mask_rev[4]
+port 26 nsew
+flabel metal2 3500 -420 3556 -10 0 FreeSans 400 90 0 0 mask_rev[5]
+port 27 nsew
+flabel metal2 4172 -420 4228 -10 0 FreeSans 400 90 0 0 mask_rev[6]
+port 28 nsew
+flabel metal2 4956 -420 5012 -10 0 FreeSans 400 90 0 0 mask_rev[7]
+port 29 nsew
+flabel metal2 5628 -420 5684 -10 0 FreeSans 400 90 0 0 mask_rev[8]
+port 30 nsew
+flabel metal2 6300 -420 6356 -10 0 FreeSans 400 90 0 0 mask_rev[9]
+port 31 nsew
+flabel metal2 6972 -420 7028 -10 0 FreeSans 400 90 0 0 mask_rev[10]
+port 1 nsew
+flabel metal2 7756 -420 7812 -10 0 FreeSans 400 90 0 0 mask_rev[11]
+port 2 nsew
+flabel metal2 8428 -420 8484 -10 0 FreeSans 400 90 0 0 mask_rev[12]
+port 3 nsew
+flabel metal2 9100 -420 9156 -10 0 FreeSans 400 90 0 0 mask_rev[13]
+port 4 nsew
+flabel metal2 9772 -420 9828 -10 0 FreeSans 400 90 0 0 mask_rev[14]
+port 5 nsew
+flabel metal2 10444 -420 10500 -10 0 FreeSans 400 90 0 0 mask_rev[15]
+port 6 nsew
+flabel metal2 11228 -420 11284 -10 0 FreeSans 400 90 0 0 mask_rev[16]
+port 7 nsew
+flabel metal2 11900 -420 11956 -10 0 FreeSans 400 90 0 0 mask_rev[17]
+port 8 nsew
+flabel metal2 12572 -420 12628 -10 0 FreeSans 400 90 0 0 mask_rev[18]
+port 9 nsew
+flabel metal2 13244 -420 13300 -10 0 FreeSans 400 90 0 0 mask_rev[19]
+port 10 nsew
+flabel metal2 14028 -420 14084 -10 0 FreeSans 400 90 0 0 mask_rev[20]
+port 12 nsew
+flabel metal2 14700 -420 14756 -10 0 FreeSans 400 90 0 0 mask_rev[21]
+port 13 nsew
+flabel metal2 15372 -420 15428 -10 0 FreeSans 400 90 0 0 mask_rev[22]
+port 14 nsew
+flabel metal2 16044 -420 16100 -10 0 FreeSans 400 90 0 0 mask_rev[23]
+port 15 nsew
+flabel metal2 16716 -420 16772 -10 0 FreeSans 400 90 0 0 mask_rev[24]
+port 16 nsew
+flabel metal2 17500 -420 17556 -10 0 FreeSans 400 90 0 0 mask_rev[25]
+port 17 nsew
+flabel metal2 18172 -420 18228 -10 0 FreeSans 400 90 0 0 mask_rev[26]
+port 18 nsew
+flabel metal2 18844 -420 18900 -10 0 FreeSans 400 90 0 0 mask_rev[27]
+port 19 nsew
+flabel metal2 19516 -420 19572 -10 0 FreeSans 400 90 0 0 mask_rev[28]
+port 20 nsew
+flabel metal2 20300 -420 20356 -10 0 FreeSans 400 90 0 0 mask_rev[29]
+port 21 nsew
+flabel metal2 20972 -420 21028 -10 0 FreeSans 400 90 0 0 mask_rev[30]
+port 23 nsew
+flabel metal2 21644 -420 21700 -10 0 FreeSans 400 90 0 0 mask_rev[31]
+port 24 nsew
+<< end >>
diff --git a/tapeout/outputs/mag/user_id_textblock.mag b/tapeout/outputs/mag/user_id_textblock.mag
new file mode 100644
index 0000000..3e02ada
--- /dev/null
+++ b/tapeout/outputs/mag/user_id_textblock.mag
@@ -0,0 +1,39 @@
+magic
+tech gf180mcuC
+magscale 1 10
+timestamp 1670447911
+<< fillblock >>
+rect 0 0 41440 10810
+use alpha_6 alphaX_0 hexdigits
+timestamp 1654634570
+transform 1 0 36895 0 1 890
+box 0 0 3888 9072
+use alpha_D alphaX_1 hexdigits
+timestamp 1654634570
+transform 1 0 31710 0 1 890
+box 0 0 3888 9072
+use alpha_5 alphaX_2 hexdigits
+timestamp 1654634570
+transform 1 0 26585 0 1 890
+box 0 0 3888 9072
+use alpha_4 alphaX_3 hexdigits
+timestamp 1654634570
+transform 1 0 21460 0 1 890
+box 0 0 3888 9072
+use alpha_0 alphaX_4 hexdigits
+timestamp 1654634570
+transform 1 0 16335 0 1 890
+box 0 0 3888 9072
+use alpha_0 alphaX_5
+timestamp 1654634570
+transform 1 0 11210 0 1 890
+box 0 0 3888 9072
+use alpha_8 alphaX_6 hexdigits
+timestamp 1654634570
+transform 1 0 6085 0 1 890
+box 0 0 3888 9072
+use alpha_1 alphaX_7 hexdigits
+timestamp 1654634570
+transform 1 0 960 0 1 890
+box 0 0 3888 9072
+<< end >>
diff --git a/tapeout/outputs/oas/caravel_180045d6.oas b/tapeout/outputs/oas/caravel_180045d6.oas
new file mode 100644
index 0000000..5f99c04
--- /dev/null
+++ b/tapeout/outputs/oas/caravel_180045d6.oas
Binary files differ
diff --git a/tapeout/outputs/verilog/gl/caravel_core.v b/tapeout/outputs/verilog/gl/caravel_core.v
new file mode 100644
index 0000000..f8bedd0
--- /dev/null
+++ b/tapeout/outputs/verilog/gl/caravel_core.v
@@ -0,0 +1,616087 @@
+module caravel_core (clock_core,
+ flash_clk_frame,
+ flash_clk_oe,
+ flash_csb_frame,
+ flash_csb_oe,
+ flash_io0_di,
+ flash_io0_do,
+ flash_io0_ie,
+ flash_io0_oe,
+ flash_io1_di,
+ flash_io1_do,
+ flash_io1_ie,
+ flash_io1_oe,
+ gpio_in_core,
+ gpio_inenb_core,
+ gpio_out_core,
+ gpio_outenb_core,
+ rstb,
+ VSS,
+ VDD,
+ const_one,
+ const_zero,
+ gpio_drive_select_core,
+ mprj_io_drive_sel,
+ mprj_io_ie,
+ mprj_io_in,
+ mprj_io_oe,
+ mprj_io_out,
+ mprj_io_pulldown_sel,
+ mprj_io_pullup_sel,
+ mprj_io_schmitt_sel,
+ mprj_io_slew_sel);
+ input clock_core;
+ output flash_clk_frame;
+ output flash_clk_oe;
+ output flash_csb_frame;
+ output flash_csb_oe;
+ input flash_io0_di;
+ output flash_io0_do;
+ output flash_io0_ie;
+ output flash_io0_oe;
+ input flash_io1_di;
+ output flash_io1_do;
+ output flash_io1_ie;
+ output flash_io1_oe;
+ input gpio_in_core;
+ output gpio_inenb_core;
+ output gpio_out_core;
+ output gpio_outenb_core;
+ input rstb;
+ input VSS;
+ input VDD;
+ output [1:0] const_one;
+ output [9:0] const_zero;
+ output [1:0] gpio_drive_select_core;
+ output [75:0] mprj_io_drive_sel;
+ output [37:0] mprj_io_ie;
+ input [37:0] mprj_io_in;
+ output [37:0] mprj_io_oe;
+ output [37:0] mprj_io_out;
+ output [37:0] mprj_io_pulldown_sel;
+ output [37:0] mprj_io_pullup_sel;
+ output [37:0] mprj_io_schmitt_sel;
+ output [37:0] mprj_io_slew_sel;
+
+ wire _00000_;
+ wire _00001_;
+ wire _00002_;
+ wire _00003_;
+ wire _00004_;
+ wire _00005_;
+ wire _00006_;
+ wire _00007_;
+ wire _00008_;
+ wire _00009_;
+ wire _00010_;
+ wire _00011_;
+ wire _00012_;
+ wire _00013_;
+ wire _00014_;
+ wire _00015_;
+ wire _00016_;
+ wire _00017_;
+ wire _00018_;
+ wire _00019_;
+ wire _00020_;
+ wire _00021_;
+ wire _00022_;
+ wire _00023_;
+ wire _00024_;
+ wire _00025_;
+ wire _00026_;
+ wire _00027_;
+ wire _00028_;
+ wire _00029_;
+ wire _00030_;
+ wire _00031_;
+ wire _00032_;
+ wire _00033_;
+ wire _00034_;
+ wire _00035_;
+ wire _00036_;
+ wire _00037_;
+ wire _00038_;
+ wire _00039_;
+ wire _00040_;
+ wire _00041_;
+ wire _00042_;
+ wire _00043_;
+ wire _00044_;
+ wire _00045_;
+ wire _00046_;
+ wire _00047_;
+ wire _00048_;
+ wire _00049_;
+ wire _00050_;
+ wire _00051_;
+ wire _00052_;
+ wire _00053_;
+ wire _00054_;
+ wire _00055_;
+ wire _00056_;
+ wire _00057_;
+ wire _00058_;
+ wire _00059_;
+ wire _00060_;
+ wire _00061_;
+ wire _00062_;
+ wire _00063_;
+ wire _00064_;
+ wire _00065_;
+ wire _00066_;
+ wire _00067_;
+ wire _00068_;
+ wire _00069_;
+ wire _00070_;
+ wire _00071_;
+ wire _00072_;
+ wire _00073_;
+ wire _00074_;
+ wire _00075_;
+ wire _00076_;
+ wire _00077_;
+ wire _00078_;
+ wire _00079_;
+ wire _00080_;
+ wire _00081_;
+ wire _00082_;
+ wire _00083_;
+ wire _00084_;
+ wire _00085_;
+ wire _00086_;
+ wire _00087_;
+ wire _00088_;
+ wire _00089_;
+ wire _00090_;
+ wire _00091_;
+ wire _00092_;
+ wire _00093_;
+ wire _00094_;
+ wire _00095_;
+ wire _00096_;
+ wire _00097_;
+ wire _00098_;
+ wire _00099_;
+ wire _00100_;
+ wire _00101_;
+ wire _00102_;
+ wire _00103_;
+ wire _00104_;
+ wire _00105_;
+ wire _00106_;
+ wire _00107_;
+ wire _00108_;
+ wire _00109_;
+ wire _00110_;
+ wire _00111_;
+ wire _00112_;
+ wire _00113_;
+ wire _00114_;
+ wire _00115_;
+ wire _00116_;
+ wire _00117_;
+ wire _00118_;
+ wire _00119_;
+ wire _00120_;
+ wire _00121_;
+ wire _00122_;
+ wire _00123_;
+ wire _00124_;
+ wire _00125_;
+ wire _00126_;
+ wire _00127_;
+ wire _00128_;
+ wire _00129_;
+ wire _00130_;
+ wire _00131_;
+ wire _00132_;
+ wire _00133_;
+ wire _00134_;
+ wire _00135_;
+ wire _00136_;
+ wire _00137_;
+ wire _00138_;
+ wire _00139_;
+ wire _00140_;
+ wire _00141_;
+ wire _00142_;
+ wire _00143_;
+ wire _00144_;
+ wire _00145_;
+ wire _00146_;
+ wire _00147_;
+ wire _00148_;
+ wire _00149_;
+ wire _00150_;
+ wire _00151_;
+ wire _00152_;
+ wire _00153_;
+ wire _00154_;
+ wire _00155_;
+ wire _00156_;
+ wire _00157_;
+ wire _00158_;
+ wire _00159_;
+ wire _00160_;
+ wire _00161_;
+ wire _00162_;
+ wire _00163_;
+ wire _00164_;
+ wire _00165_;
+ wire _00166_;
+ wire _00167_;
+ wire _00168_;
+ wire _00169_;
+ wire _00170_;
+ wire _00171_;
+ wire _00172_;
+ wire _00173_;
+ wire _00174_;
+ wire _00175_;
+ wire _00176_;
+ wire _00177_;
+ wire _00178_;
+ wire _00179_;
+ wire _00180_;
+ wire _00181_;
+ wire _00182_;
+ wire _00183_;
+ wire _00184_;
+ wire _00185_;
+ wire _00186_;
+ wire _00187_;
+ wire _00188_;
+ wire _00189_;
+ wire _00190_;
+ wire _00191_;
+ wire _00192_;
+ wire _00193_;
+ wire _00194_;
+ wire _00195_;
+ wire _00196_;
+ wire _00197_;
+ wire _00198_;
+ wire _00199_;
+ wire _00200_;
+ wire _00201_;
+ wire _00202_;
+ wire _00203_;
+ wire _00204_;
+ wire _00205_;
+ wire _00206_;
+ wire _00207_;
+ wire _00208_;
+ wire _00209_;
+ wire _00210_;
+ wire _00211_;
+ wire _00212_;
+ wire _00213_;
+ wire _00214_;
+ wire _00215_;
+ wire _00216_;
+ wire _00217_;
+ wire _00218_;
+ wire _00219_;
+ wire _00220_;
+ wire _00221_;
+ wire _00222_;
+ wire _00223_;
+ wire _00224_;
+ wire _00225_;
+ wire _00226_;
+ wire _00227_;
+ wire _00228_;
+ wire _00229_;
+ wire _00230_;
+ wire _00231_;
+ wire _00232_;
+ wire _00233_;
+ wire _00234_;
+ wire _00235_;
+ wire _00236_;
+ wire _00237_;
+ wire _00238_;
+ wire _00239_;
+ wire _00240_;
+ wire _00241_;
+ wire _00242_;
+ wire _00243_;
+ wire _00244_;
+ wire _00245_;
+ wire _00246_;
+ wire _00247_;
+ wire _00248_;
+ wire _00249_;
+ wire _00250_;
+ wire _00251_;
+ wire _00252_;
+ wire _00253_;
+ wire _00254_;
+ wire _00255_;
+ wire _00256_;
+ wire _00257_;
+ wire _00258_;
+ wire _00259_;
+ wire _00260_;
+ wire _00261_;
+ wire _00262_;
+ wire _00263_;
+ wire _00264_;
+ wire _00265_;
+ wire _00266_;
+ wire _00267_;
+ wire _00268_;
+ wire _00269_;
+ wire _00270_;
+ wire _00271_;
+ wire _00272_;
+ wire _00273_;
+ wire _00274_;
+ wire _00275_;
+ wire _00276_;
+ wire _00277_;
+ wire _00278_;
+ wire _00279_;
+ wire _00280_;
+ wire _00281_;
+ wire _00282_;
+ wire _00283_;
+ wire _00284_;
+ wire _00285_;
+ wire _00286_;
+ wire _00287_;
+ wire _00288_;
+ wire _00289_;
+ wire _00290_;
+ wire _00291_;
+ wire _00292_;
+ wire _00293_;
+ wire _00294_;
+ wire _00295_;
+ wire _00296_;
+ wire _00297_;
+ wire _00298_;
+ wire _00299_;
+ wire _00300_;
+ wire _00301_;
+ wire _00302_;
+ wire _00303_;
+ wire _00304_;
+ wire _00305_;
+ wire _00306_;
+ wire _00307_;
+ wire _00308_;
+ wire _00309_;
+ wire _00310_;
+ wire _00311_;
+ wire _00312_;
+ wire _00313_;
+ wire _00314_;
+ wire _00315_;
+ wire _00316_;
+ wire _00317_;
+ wire _00318_;
+ wire _00319_;
+ wire _00320_;
+ wire _00321_;
+ wire _00322_;
+ wire _00323_;
+ wire _00324_;
+ wire _00325_;
+ wire _00326_;
+ wire _00327_;
+ wire _00328_;
+ wire _00329_;
+ wire _00330_;
+ wire _00331_;
+ wire _00332_;
+ wire _00333_;
+ wire _00334_;
+ wire _00335_;
+ wire _00336_;
+ wire _00337_;
+ wire _00338_;
+ wire _00339_;
+ wire _00340_;
+ wire _00341_;
+ wire _00342_;
+ wire _00343_;
+ wire _00344_;
+ wire _00345_;
+ wire _00346_;
+ wire _00347_;
+ wire _00348_;
+ wire _00349_;
+ wire _00350_;
+ wire _00351_;
+ wire _00352_;
+ wire _00353_;
+ wire _00354_;
+ wire _00355_;
+ wire _00356_;
+ wire _00357_;
+ wire _00358_;
+ wire _00359_;
+ wire _00360_;
+ wire _00361_;
+ wire _00362_;
+ wire _00363_;
+ wire _00364_;
+ wire _00365_;
+ wire _00366_;
+ wire _00367_;
+ wire _00368_;
+ wire _00369_;
+ wire _00370_;
+ wire _00371_;
+ wire _00372_;
+ wire _00373_;
+ wire _00374_;
+ wire _00375_;
+ wire _00376_;
+ wire _00377_;
+ wire _00378_;
+ wire _00379_;
+ wire _00380_;
+ wire _00381_;
+ wire _00382_;
+ wire _00383_;
+ wire _00384_;
+ wire _00385_;
+ wire _00386_;
+ wire _00387_;
+ wire _00388_;
+ wire _00389_;
+ wire _00390_;
+ wire _00391_;
+ wire _00392_;
+ wire _00393_;
+ wire _00394_;
+ wire _00395_;
+ wire _00396_;
+ wire _00397_;
+ wire _00398_;
+ wire _00399_;
+ wire _00400_;
+ wire _00401_;
+ wire _00402_;
+ wire _00403_;
+ wire _00404_;
+ wire _00405_;
+ wire _00406_;
+ wire _00407_;
+ wire _00408_;
+ wire _00409_;
+ wire _00410_;
+ wire _00411_;
+ wire _00412_;
+ wire _00413_;
+ wire _00414_;
+ wire _00415_;
+ wire _00416_;
+ wire _00417_;
+ wire _00418_;
+ wire _00419_;
+ wire _00420_;
+ wire _00421_;
+ wire _00422_;
+ wire _00423_;
+ wire _00424_;
+ wire _00425_;
+ wire _00426_;
+ wire _00427_;
+ wire _00428_;
+ wire _00429_;
+ wire _00430_;
+ wire _00431_;
+ wire _00432_;
+ wire _00433_;
+ wire _00434_;
+ wire _00435_;
+ wire _00436_;
+ wire _00437_;
+ wire _00438_;
+ wire _00439_;
+ wire _00440_;
+ wire _00441_;
+ wire _00442_;
+ wire _00443_;
+ wire _00444_;
+ wire _00445_;
+ wire _00446_;
+ wire _00447_;
+ wire _00448_;
+ wire _00449_;
+ wire _00450_;
+ wire _00451_;
+ wire _00452_;
+ wire _00453_;
+ wire _00454_;
+ wire _00455_;
+ wire _00456_;
+ wire _00457_;
+ wire _00458_;
+ wire _00459_;
+ wire _00460_;
+ wire _00461_;
+ wire _00462_;
+ wire _00463_;
+ wire _00464_;
+ wire _00465_;
+ wire _00466_;
+ wire _00467_;
+ wire _00468_;
+ wire _00469_;
+ wire _00470_;
+ wire _00471_;
+ wire _00472_;
+ wire _00473_;
+ wire _00474_;
+ wire _00475_;
+ wire _00476_;
+ wire _00477_;
+ wire _00478_;
+ wire _00479_;
+ wire _00480_;
+ wire _00481_;
+ wire _00482_;
+ wire _00483_;
+ wire _00484_;
+ wire _00485_;
+ wire _00486_;
+ wire _00487_;
+ wire _00488_;
+ wire _00489_;
+ wire _00490_;
+ wire _00491_;
+ wire _00492_;
+ wire _00493_;
+ wire _00494_;
+ wire _00495_;
+ wire _00496_;
+ wire _00497_;
+ wire _00498_;
+ wire _00499_;
+ wire _00500_;
+ wire _00501_;
+ wire _00502_;
+ wire _00503_;
+ wire _00504_;
+ wire _00505_;
+ wire _00506_;
+ wire _00507_;
+ wire _00508_;
+ wire _00509_;
+ wire _00510_;
+ wire _00511_;
+ wire _00512_;
+ wire _00513_;
+ wire _00514_;
+ wire _00515_;
+ wire _00516_;
+ wire _00517_;
+ wire _00518_;
+ wire _00519_;
+ wire _00520_;
+ wire _00521_;
+ wire _00522_;
+ wire _00523_;
+ wire _00524_;
+ wire _00525_;
+ wire _00526_;
+ wire _00527_;
+ wire _00528_;
+ wire _00529_;
+ wire _00530_;
+ wire _00531_;
+ wire _00532_;
+ wire _00533_;
+ wire _00534_;
+ wire _00535_;
+ wire _00536_;
+ wire _00537_;
+ wire _00538_;
+ wire _00539_;
+ wire _00540_;
+ wire _00541_;
+ wire _00542_;
+ wire _00543_;
+ wire _00544_;
+ wire _00545_;
+ wire _00546_;
+ wire _00547_;
+ wire _00548_;
+ wire _00549_;
+ wire _00550_;
+ wire _00551_;
+ wire _00552_;
+ wire _00553_;
+ wire _00554_;
+ wire _00555_;
+ wire _00556_;
+ wire _00557_;
+ wire _00558_;
+ wire _00559_;
+ wire _00560_;
+ wire _00561_;
+ wire _00562_;
+ wire _00563_;
+ wire _00564_;
+ wire _00565_;
+ wire _00566_;
+ wire _00567_;
+ wire _00568_;
+ wire _00569_;
+ wire _00570_;
+ wire _00571_;
+ wire _00572_;
+ wire _00573_;
+ wire _00574_;
+ wire _00575_;
+ wire _00576_;
+ wire _00577_;
+ wire _00578_;
+ wire _00579_;
+ wire _00580_;
+ wire _00581_;
+ wire _00582_;
+ wire _00583_;
+ wire _00584_;
+ wire _00585_;
+ wire _00586_;
+ wire _00587_;
+ wire _00588_;
+ wire _00589_;
+ wire _00590_;
+ wire _00591_;
+ wire _00592_;
+ wire _00593_;
+ wire _00594_;
+ wire _00595_;
+ wire _00596_;
+ wire _00597_;
+ wire _00598_;
+ wire _00599_;
+ wire _00600_;
+ wire _00601_;
+ wire _00602_;
+ wire _00603_;
+ wire _00604_;
+ wire _00605_;
+ wire _00606_;
+ wire _00607_;
+ wire _00608_;
+ wire _00609_;
+ wire _00610_;
+ wire _00611_;
+ wire _00612_;
+ wire _00613_;
+ wire _00614_;
+ wire _00615_;
+ wire _00616_;
+ wire _00617_;
+ wire _00618_;
+ wire _00619_;
+ wire _00620_;
+ wire _00621_;
+ wire _00622_;
+ wire _00623_;
+ wire _00624_;
+ wire _00625_;
+ wire _00626_;
+ wire _00627_;
+ wire _00628_;
+ wire _00629_;
+ wire _00630_;
+ wire _00631_;
+ wire _00632_;
+ wire _00633_;
+ wire _00634_;
+ wire _00635_;
+ wire _00636_;
+ wire _00637_;
+ wire _00638_;
+ wire _00639_;
+ wire _00640_;
+ wire _00641_;
+ wire _00642_;
+ wire _00643_;
+ wire _00644_;
+ wire _00645_;
+ wire _00646_;
+ wire _00647_;
+ wire _00648_;
+ wire _00649_;
+ wire _00650_;
+ wire _00651_;
+ wire _00652_;
+ wire _00653_;
+ wire _00654_;
+ wire _00655_;
+ wire _00656_;
+ wire _00657_;
+ wire _00658_;
+ wire _00659_;
+ wire _00660_;
+ wire _00661_;
+ wire _00662_;
+ wire _00663_;
+ wire _00664_;
+ wire _00665_;
+ wire _00666_;
+ wire _00667_;
+ wire _00668_;
+ wire _00669_;
+ wire _00670_;
+ wire _00671_;
+ wire _00672_;
+ wire _00673_;
+ wire _00674_;
+ wire _00675_;
+ wire _00676_;
+ wire _00677_;
+ wire _00678_;
+ wire _00679_;
+ wire _00680_;
+ wire _00681_;
+ wire _00682_;
+ wire _00683_;
+ wire _00684_;
+ wire _00685_;
+ wire _00686_;
+ wire _00687_;
+ wire _00688_;
+ wire _00689_;
+ wire _00690_;
+ wire _00691_;
+ wire _00692_;
+ wire _00693_;
+ wire _00694_;
+ wire _00695_;
+ wire _00696_;
+ wire _00697_;
+ wire _00698_;
+ wire _00699_;
+ wire _00700_;
+ wire _00701_;
+ wire _00702_;
+ wire _00703_;
+ wire _00704_;
+ wire _00705_;
+ wire _00706_;
+ wire _00707_;
+ wire _00708_;
+ wire _00709_;
+ wire _00710_;
+ wire _00711_;
+ wire _00712_;
+ wire _00713_;
+ wire _00714_;
+ wire _00715_;
+ wire _00716_;
+ wire _00717_;
+ wire _00718_;
+ wire _00719_;
+ wire _00720_;
+ wire _00721_;
+ wire _00722_;
+ wire _00723_;
+ wire _00724_;
+ wire _00725_;
+ wire _00726_;
+ wire _00727_;
+ wire _00728_;
+ wire _00729_;
+ wire _00730_;
+ wire _00731_;
+ wire _00732_;
+ wire _00733_;
+ wire _00734_;
+ wire _00735_;
+ wire _00736_;
+ wire _00737_;
+ wire _00738_;
+ wire _00739_;
+ wire _00740_;
+ wire _00741_;
+ wire _00742_;
+ wire _00743_;
+ wire _00744_;
+ wire _00745_;
+ wire _00746_;
+ wire _00747_;
+ wire _00748_;
+ wire _00749_;
+ wire _00750_;
+ wire _00751_;
+ wire _00752_;
+ wire _00753_;
+ wire _00754_;
+ wire _00755_;
+ wire _00756_;
+ wire _00757_;
+ wire _00758_;
+ wire _00759_;
+ wire _00760_;
+ wire _00761_;
+ wire _00762_;
+ wire _00763_;
+ wire _00764_;
+ wire _00765_;
+ wire _00766_;
+ wire _00767_;
+ wire _00768_;
+ wire _00769_;
+ wire _00770_;
+ wire _00771_;
+ wire _00772_;
+ wire _00773_;
+ wire _00774_;
+ wire _00775_;
+ wire _00776_;
+ wire _00777_;
+ wire _00778_;
+ wire _00779_;
+ wire _00780_;
+ wire _00781_;
+ wire _00782_;
+ wire _00783_;
+ wire _00784_;
+ wire _00785_;
+ wire _00786_;
+ wire _00787_;
+ wire _00788_;
+ wire _00789_;
+ wire _00790_;
+ wire _00791_;
+ wire _00792_;
+ wire _00793_;
+ wire _00794_;
+ wire _00795_;
+ wire _00796_;
+ wire _00797_;
+ wire _00798_;
+ wire _00799_;
+ wire _00800_;
+ wire _00801_;
+ wire _00802_;
+ wire _00803_;
+ wire _00804_;
+ wire _00805_;
+ wire _00806_;
+ wire _00807_;
+ wire _00808_;
+ wire _00809_;
+ wire _00810_;
+ wire _00811_;
+ wire _00812_;
+ wire _00813_;
+ wire _00814_;
+ wire _00815_;
+ wire _00816_;
+ wire _00817_;
+ wire _00818_;
+ wire _00819_;
+ wire _00820_;
+ wire _00821_;
+ wire _00822_;
+ wire _00823_;
+ wire _00824_;
+ wire _00825_;
+ wire _00826_;
+ wire _00827_;
+ wire _00828_;
+ wire _00829_;
+ wire _00830_;
+ wire _00831_;
+ wire _00832_;
+ wire _00833_;
+ wire _00834_;
+ wire _00835_;
+ wire _00836_;
+ wire _00837_;
+ wire _00838_;
+ wire _00839_;
+ wire _00840_;
+ wire _00841_;
+ wire _00842_;
+ wire _00843_;
+ wire _00844_;
+ wire _00845_;
+ wire _00846_;
+ wire _00847_;
+ wire _00848_;
+ wire _00849_;
+ wire _00850_;
+ wire _00851_;
+ wire _00852_;
+ wire _00853_;
+ wire _00854_;
+ wire _00855_;
+ wire _00856_;
+ wire _00857_;
+ wire _00858_;
+ wire _00859_;
+ wire _00860_;
+ wire _00861_;
+ wire _00862_;
+ wire _00863_;
+ wire _00864_;
+ wire _00865_;
+ wire _00866_;
+ wire _00867_;
+ wire _00868_;
+ wire _00869_;
+ wire _00870_;
+ wire _00871_;
+ wire _00872_;
+ wire _00873_;
+ wire _00874_;
+ wire _00875_;
+ wire _00876_;
+ wire _00877_;
+ wire _00878_;
+ wire _00879_;
+ wire _00880_;
+ wire _00881_;
+ wire _00882_;
+ wire _00883_;
+ wire _00884_;
+ wire _00885_;
+ wire _00886_;
+ wire _00887_;
+ wire _00888_;
+ wire _00889_;
+ wire _00890_;
+ wire _00891_;
+ wire _00892_;
+ wire _00893_;
+ wire _00894_;
+ wire _00895_;
+ wire _00896_;
+ wire _00897_;
+ wire _00898_;
+ wire _00899_;
+ wire _00900_;
+ wire _00901_;
+ wire _00902_;
+ wire _00903_;
+ wire _00904_;
+ wire _00905_;
+ wire _00906_;
+ wire _00907_;
+ wire _00908_;
+ wire _00909_;
+ wire _00910_;
+ wire _00911_;
+ wire _00912_;
+ wire _00913_;
+ wire _00914_;
+ wire _00915_;
+ wire _00916_;
+ wire _00917_;
+ wire _00918_;
+ wire _00919_;
+ wire _00920_;
+ wire _00921_;
+ wire _00922_;
+ wire _00923_;
+ wire _00924_;
+ wire _00925_;
+ wire _00926_;
+ wire _00927_;
+ wire _00928_;
+ wire _00929_;
+ wire _00930_;
+ wire _00931_;
+ wire _00932_;
+ wire _00933_;
+ wire _00934_;
+ wire _00935_;
+ wire _00936_;
+ wire _00937_;
+ wire _00938_;
+ wire _00939_;
+ wire _00940_;
+ wire _00941_;
+ wire _00942_;
+ wire _00943_;
+ wire _00944_;
+ wire _00945_;
+ wire _00946_;
+ wire _00947_;
+ wire _00948_;
+ wire _00949_;
+ wire _00950_;
+ wire _00951_;
+ wire _00952_;
+ wire _00953_;
+ wire _00954_;
+ wire _00955_;
+ wire _00956_;
+ wire _00957_;
+ wire _00958_;
+ wire _00959_;
+ wire _00960_;
+ wire _00961_;
+ wire _00962_;
+ wire _00963_;
+ wire _00964_;
+ wire _00965_;
+ wire _00966_;
+ wire _00967_;
+ wire _00968_;
+ wire _00969_;
+ wire _00970_;
+ wire _00971_;
+ wire _00972_;
+ wire _00973_;
+ wire _00974_;
+ wire _00975_;
+ wire _00976_;
+ wire _00977_;
+ wire _00978_;
+ wire _00979_;
+ wire _00980_;
+ wire _00981_;
+ wire _00982_;
+ wire _00983_;
+ wire _00984_;
+ wire _00985_;
+ wire _00986_;
+ wire _00987_;
+ wire _00988_;
+ wire _00989_;
+ wire _00990_;
+ wire _00991_;
+ wire _00992_;
+ wire _00993_;
+ wire _00994_;
+ wire _00995_;
+ wire _00996_;
+ wire _00997_;
+ wire _00998_;
+ wire _00999_;
+ wire _01000_;
+ wire _01001_;
+ wire _01002_;
+ wire _01003_;
+ wire _01004_;
+ wire _01005_;
+ wire _01006_;
+ wire _01007_;
+ wire _01008_;
+ wire _01009_;
+ wire _01010_;
+ wire _01011_;
+ wire _01012_;
+ wire _01013_;
+ wire _01014_;
+ wire _01015_;
+ wire _01016_;
+ wire _01017_;
+ wire _01018_;
+ wire _01019_;
+ wire _01020_;
+ wire _01021_;
+ wire _01022_;
+ wire _01023_;
+ wire _01024_;
+ wire _01025_;
+ wire _01026_;
+ wire _01027_;
+ wire _01028_;
+ wire _01029_;
+ wire _01030_;
+ wire _01031_;
+ wire _01032_;
+ wire _01033_;
+ wire _01034_;
+ wire _01035_;
+ wire _01036_;
+ wire _01037_;
+ wire _01038_;
+ wire _01039_;
+ wire _01040_;
+ wire _01041_;
+ wire _01042_;
+ wire _01043_;
+ wire _01044_;
+ wire _01045_;
+ wire _01046_;
+ wire _01047_;
+ wire _01048_;
+ wire _01049_;
+ wire _01050_;
+ wire _01051_;
+ wire _01052_;
+ wire _01053_;
+ wire _01054_;
+ wire _01055_;
+ wire _01056_;
+ wire _01057_;
+ wire _01058_;
+ wire _01059_;
+ wire _01060_;
+ wire _01061_;
+ wire _01062_;
+ wire _01063_;
+ wire _01064_;
+ wire _01065_;
+ wire _01066_;
+ wire _01067_;
+ wire _01068_;
+ wire _01069_;
+ wire _01070_;
+ wire _01071_;
+ wire _01072_;
+ wire _01073_;
+ wire _01074_;
+ wire _01075_;
+ wire _01076_;
+ wire _01077_;
+ wire _01078_;
+ wire _01079_;
+ wire _01080_;
+ wire _01081_;
+ wire _01082_;
+ wire _01083_;
+ wire _01084_;
+ wire _01085_;
+ wire _01086_;
+ wire _01087_;
+ wire _01088_;
+ wire _01089_;
+ wire _01090_;
+ wire _01091_;
+ wire _01092_;
+ wire _01093_;
+ wire _01094_;
+ wire _01095_;
+ wire _01096_;
+ wire _01097_;
+ wire _01098_;
+ wire _01099_;
+ wire _01100_;
+ wire _01101_;
+ wire _01102_;
+ wire _01103_;
+ wire _01104_;
+ wire _01105_;
+ wire _01106_;
+ wire _01107_;
+ wire _01108_;
+ wire _01109_;
+ wire _01110_;
+ wire _01111_;
+ wire _01112_;
+ wire _01113_;
+ wire _01114_;
+ wire _01115_;
+ wire _01116_;
+ wire _01117_;
+ wire _01118_;
+ wire _01119_;
+ wire _01120_;
+ wire _01121_;
+ wire _01122_;
+ wire _01123_;
+ wire _01124_;
+ wire _01125_;
+ wire _01126_;
+ wire _01127_;
+ wire _01128_;
+ wire _01129_;
+ wire _01130_;
+ wire _01131_;
+ wire _01132_;
+ wire _01133_;
+ wire _01134_;
+ wire _01135_;
+ wire _01136_;
+ wire _01137_;
+ wire _01138_;
+ wire _01139_;
+ wire _01140_;
+ wire _01141_;
+ wire _01142_;
+ wire _01143_;
+ wire _01144_;
+ wire _01145_;
+ wire _01146_;
+ wire _01147_;
+ wire _01148_;
+ wire _01149_;
+ wire _01150_;
+ wire _01151_;
+ wire _01152_;
+ wire _01153_;
+ wire _01154_;
+ wire _01155_;
+ wire _01156_;
+ wire _01157_;
+ wire _01158_;
+ wire _01159_;
+ wire _01160_;
+ wire _01161_;
+ wire _01162_;
+ wire _01163_;
+ wire _01164_;
+ wire _01165_;
+ wire _01166_;
+ wire _01167_;
+ wire _01168_;
+ wire _01169_;
+ wire _01170_;
+ wire _01171_;
+ wire _01172_;
+ wire _01173_;
+ wire _01174_;
+ wire _01175_;
+ wire _01176_;
+ wire _01177_;
+ wire _01178_;
+ wire _01179_;
+ wire _01180_;
+ wire _01181_;
+ wire _01182_;
+ wire _01183_;
+ wire _01184_;
+ wire _01185_;
+ wire _01186_;
+ wire _01187_;
+ wire _01188_;
+ wire _01189_;
+ wire _01190_;
+ wire _01191_;
+ wire _01192_;
+ wire _01193_;
+ wire _01194_;
+ wire _01195_;
+ wire _01196_;
+ wire _01197_;
+ wire _01198_;
+ wire _01199_;
+ wire _01200_;
+ wire _01201_;
+ wire _01202_;
+ wire _01203_;
+ wire _01204_;
+ wire _01205_;
+ wire _01206_;
+ wire _01207_;
+ wire _01208_;
+ wire _01209_;
+ wire _01210_;
+ wire _01211_;
+ wire _01212_;
+ wire _01213_;
+ wire _01214_;
+ wire _01215_;
+ wire _01216_;
+ wire _01217_;
+ wire _01218_;
+ wire _01219_;
+ wire _01220_;
+ wire _01221_;
+ wire _01222_;
+ wire _01223_;
+ wire _01224_;
+ wire _01225_;
+ wire _01226_;
+ wire _01227_;
+ wire _01228_;
+ wire _01229_;
+ wire _01230_;
+ wire _01231_;
+ wire _01232_;
+ wire _01233_;
+ wire _01234_;
+ wire _01235_;
+ wire _01236_;
+ wire _01237_;
+ wire _01238_;
+ wire _01239_;
+ wire _01240_;
+ wire _01241_;
+ wire _01242_;
+ wire _01243_;
+ wire _01244_;
+ wire _01245_;
+ wire _01246_;
+ wire _01247_;
+ wire _01248_;
+ wire _01249_;
+ wire _01250_;
+ wire _01251_;
+ wire _01252_;
+ wire _01253_;
+ wire _01254_;
+ wire _01255_;
+ wire _01256_;
+ wire _01257_;
+ wire _01258_;
+ wire _01259_;
+ wire _01260_;
+ wire _01261_;
+ wire _01262_;
+ wire _01263_;
+ wire _01264_;
+ wire _01265_;
+ wire _01266_;
+ wire _01267_;
+ wire _01268_;
+ wire _01269_;
+ wire _01270_;
+ wire _01271_;
+ wire _01272_;
+ wire _01273_;
+ wire _01274_;
+ wire _01275_;
+ wire _01276_;
+ wire _01277_;
+ wire _01278_;
+ wire _01279_;
+ wire _01280_;
+ wire _01281_;
+ wire _01282_;
+ wire _01283_;
+ wire _01284_;
+ wire _01285_;
+ wire _01286_;
+ wire _01287_;
+ wire _01288_;
+ wire _01289_;
+ wire _01290_;
+ wire _01291_;
+ wire _01292_;
+ wire _01293_;
+ wire _01294_;
+ wire _01295_;
+ wire _01296_;
+ wire _01297_;
+ wire _01298_;
+ wire _01299_;
+ wire _01300_;
+ wire _01301_;
+ wire _01302_;
+ wire _01303_;
+ wire _01304_;
+ wire _01305_;
+ wire _01306_;
+ wire _01307_;
+ wire _01308_;
+ wire _01309_;
+ wire _01310_;
+ wire _01311_;
+ wire _01312_;
+ wire _01313_;
+ wire _01314_;
+ wire _01315_;
+ wire _01316_;
+ wire _01317_;
+ wire _01318_;
+ wire _01319_;
+ wire _01320_;
+ wire _01321_;
+ wire _01322_;
+ wire _01323_;
+ wire _01324_;
+ wire _01325_;
+ wire _01326_;
+ wire _01327_;
+ wire _01328_;
+ wire _01329_;
+ wire _01330_;
+ wire _01331_;
+ wire _01332_;
+ wire _01333_;
+ wire _01334_;
+ wire _01335_;
+ wire _01336_;
+ wire _01337_;
+ wire _01338_;
+ wire _01339_;
+ wire _01340_;
+ wire _01341_;
+ wire _01342_;
+ wire _01343_;
+ wire _01344_;
+ wire _01345_;
+ wire _01346_;
+ wire _01347_;
+ wire _01348_;
+ wire _01349_;
+ wire _01350_;
+ wire _01351_;
+ wire _01352_;
+ wire _01353_;
+ wire _01354_;
+ wire _01355_;
+ wire _01356_;
+ wire _01357_;
+ wire _01358_;
+ wire _01359_;
+ wire _01360_;
+ wire _01361_;
+ wire _01362_;
+ wire _01363_;
+ wire _01364_;
+ wire _01365_;
+ wire _01366_;
+ wire _01367_;
+ wire _01368_;
+ wire _01369_;
+ wire _01370_;
+ wire _01371_;
+ wire _01372_;
+ wire _01373_;
+ wire _01374_;
+ wire _01375_;
+ wire _01376_;
+ wire _01377_;
+ wire _01378_;
+ wire _01379_;
+ wire _01380_;
+ wire _01381_;
+ wire _01382_;
+ wire _01383_;
+ wire _01384_;
+ wire _01385_;
+ wire _01386_;
+ wire _01387_;
+ wire _01388_;
+ wire _01389_;
+ wire _01390_;
+ wire _01391_;
+ wire _01392_;
+ wire _01393_;
+ wire _01394_;
+ wire _01395_;
+ wire _01396_;
+ wire _01397_;
+ wire _01398_;
+ wire _01399_;
+ wire _01400_;
+ wire _01401_;
+ wire _01402_;
+ wire _01403_;
+ wire _01404_;
+ wire _01405_;
+ wire _01406_;
+ wire _01407_;
+ wire _01408_;
+ wire _01409_;
+ wire _01410_;
+ wire _01411_;
+ wire _01412_;
+ wire _01413_;
+ wire _01414_;
+ wire _01415_;
+ wire _01416_;
+ wire _01417_;
+ wire _01418_;
+ wire _01419_;
+ wire _01420_;
+ wire _01421_;
+ wire _01422_;
+ wire _01423_;
+ wire _01424_;
+ wire _01425_;
+ wire _01426_;
+ wire _01427_;
+ wire _01428_;
+ wire _01429_;
+ wire _01430_;
+ wire _01431_;
+ wire _01432_;
+ wire _01433_;
+ wire _01434_;
+ wire _01435_;
+ wire _01436_;
+ wire _01437_;
+ wire _01438_;
+ wire _01439_;
+ wire _01440_;
+ wire _01441_;
+ wire _01442_;
+ wire _01443_;
+ wire _01444_;
+ wire _01445_;
+ wire _01446_;
+ wire _01447_;
+ wire _01448_;
+ wire _01449_;
+ wire _01450_;
+ wire _01451_;
+ wire _01452_;
+ wire _01453_;
+ wire _01454_;
+ wire _01455_;
+ wire _01456_;
+ wire _01457_;
+ wire _01458_;
+ wire _01459_;
+ wire _01460_;
+ wire _01461_;
+ wire _01462_;
+ wire _01463_;
+ wire _01464_;
+ wire _01465_;
+ wire _01466_;
+ wire _01467_;
+ wire _01468_;
+ wire _01469_;
+ wire _01470_;
+ wire _01471_;
+ wire _01472_;
+ wire _01473_;
+ wire _01474_;
+ wire _01475_;
+ wire _01476_;
+ wire _01477_;
+ wire _01478_;
+ wire _01479_;
+ wire _01480_;
+ wire _01481_;
+ wire _01482_;
+ wire _01483_;
+ wire _01484_;
+ wire _01485_;
+ wire _01486_;
+ wire _01487_;
+ wire _01488_;
+ wire _01489_;
+ wire _01490_;
+ wire _01491_;
+ wire _01492_;
+ wire _01493_;
+ wire _01494_;
+ wire _01495_;
+ wire _01496_;
+ wire _01497_;
+ wire _01498_;
+ wire _01499_;
+ wire _01500_;
+ wire _01501_;
+ wire _01502_;
+ wire _01503_;
+ wire _01504_;
+ wire _01505_;
+ wire _01506_;
+ wire _01507_;
+ wire _01508_;
+ wire _01509_;
+ wire _01510_;
+ wire _01511_;
+ wire _01512_;
+ wire _01513_;
+ wire _01514_;
+ wire _01515_;
+ wire _01516_;
+ wire _01517_;
+ wire _01518_;
+ wire _01519_;
+ wire _01520_;
+ wire _01521_;
+ wire _01522_;
+ wire _01523_;
+ wire _01524_;
+ wire _01525_;
+ wire _01526_;
+ wire _01527_;
+ wire _01528_;
+ wire _01529_;
+ wire _01530_;
+ wire _01531_;
+ wire _01532_;
+ wire _01533_;
+ wire _01534_;
+ wire _01535_;
+ wire _01536_;
+ wire _01537_;
+ wire _01538_;
+ wire _01539_;
+ wire _01540_;
+ wire _01541_;
+ wire _01542_;
+ wire _01543_;
+ wire _01544_;
+ wire _01545_;
+ wire _01546_;
+ wire _01547_;
+ wire _01548_;
+ wire _01549_;
+ wire _01550_;
+ wire _01551_;
+ wire _01552_;
+ wire _01553_;
+ wire _01554_;
+ wire _01555_;
+ wire _01556_;
+ wire _01557_;
+ wire _01558_;
+ wire _01559_;
+ wire _01560_;
+ wire _01561_;
+ wire _01562_;
+ wire _01563_;
+ wire _01564_;
+ wire _01565_;
+ wire _01566_;
+ wire _01567_;
+ wire _01568_;
+ wire _01569_;
+ wire _01570_;
+ wire _01571_;
+ wire _01572_;
+ wire _01573_;
+ wire _01574_;
+ wire _01575_;
+ wire _01576_;
+ wire _01577_;
+ wire _01578_;
+ wire _01579_;
+ wire _01580_;
+ wire _01581_;
+ wire _01582_;
+ wire _01583_;
+ wire _01584_;
+ wire _01585_;
+ wire _01586_;
+ wire _01587_;
+ wire _01588_;
+ wire _01589_;
+ wire _01590_;
+ wire _01591_;
+ wire _01592_;
+ wire _01593_;
+ wire _01594_;
+ wire _01595_;
+ wire _01596_;
+ wire _01597_;
+ wire _01598_;
+ wire _01599_;
+ wire _01600_;
+ wire _01601_;
+ wire _01602_;
+ wire _01603_;
+ wire _01604_;
+ wire _01605_;
+ wire _01606_;
+ wire _01607_;
+ wire _01608_;
+ wire _01609_;
+ wire _01610_;
+ wire _01611_;
+ wire _01612_;
+ wire _01613_;
+ wire _01614_;
+ wire _01615_;
+ wire _01616_;
+ wire _01617_;
+ wire _01618_;
+ wire _01619_;
+ wire _01620_;
+ wire _01621_;
+ wire _01622_;
+ wire _01623_;
+ wire _01624_;
+ wire _01625_;
+ wire _01626_;
+ wire _01627_;
+ wire _01628_;
+ wire _01629_;
+ wire _01630_;
+ wire _01631_;
+ wire _01632_;
+ wire _01633_;
+ wire _01634_;
+ wire _01635_;
+ wire _01636_;
+ wire _01637_;
+ wire _01638_;
+ wire _01639_;
+ wire _01640_;
+ wire _01641_;
+ wire _01642_;
+ wire _01643_;
+ wire _01644_;
+ wire _01645_;
+ wire _01646_;
+ wire _01647_;
+ wire _01648_;
+ wire _01649_;
+ wire _01650_;
+ wire _01651_;
+ wire _01652_;
+ wire _01653_;
+ wire _01654_;
+ wire _01655_;
+ wire _01656_;
+ wire _01657_;
+ wire _01658_;
+ wire _01659_;
+ wire _01660_;
+ wire _01661_;
+ wire _01662_;
+ wire _01663_;
+ wire _01664_;
+ wire _01665_;
+ wire _01666_;
+ wire _01667_;
+ wire _01668_;
+ wire _01669_;
+ wire _01670_;
+ wire _01671_;
+ wire _01672_;
+ wire _01673_;
+ wire _01674_;
+ wire _01675_;
+ wire _01676_;
+ wire _01677_;
+ wire _01678_;
+ wire _01679_;
+ wire _01680_;
+ wire _01681_;
+ wire _01682_;
+ wire _01683_;
+ wire _01684_;
+ wire _01685_;
+ wire _01686_;
+ wire _01687_;
+ wire _01688_;
+ wire _01689_;
+ wire _01690_;
+ wire _01691_;
+ wire _01692_;
+ wire _01693_;
+ wire _01694_;
+ wire _01695_;
+ wire _01696_;
+ wire _01697_;
+ wire _01698_;
+ wire _01699_;
+ wire _01700_;
+ wire _01701_;
+ wire _01702_;
+ wire _01703_;
+ wire _01704_;
+ wire _01705_;
+ wire _01706_;
+ wire _01707_;
+ wire _01708_;
+ wire _01709_;
+ wire _01710_;
+ wire _01711_;
+ wire _01712_;
+ wire _01713_;
+ wire _01714_;
+ wire _01715_;
+ wire _01716_;
+ wire _01717_;
+ wire _01718_;
+ wire _01719_;
+ wire _01720_;
+ wire _01721_;
+ wire _01722_;
+ wire _01723_;
+ wire _01724_;
+ wire _01725_;
+ wire _01726_;
+ wire _01727_;
+ wire _01728_;
+ wire _01729_;
+ wire _01730_;
+ wire _01731_;
+ wire _01732_;
+ wire _01733_;
+ wire _01734_;
+ wire _01735_;
+ wire _01736_;
+ wire _01737_;
+ wire _01738_;
+ wire _01739_;
+ wire _01740_;
+ wire _01741_;
+ wire _01742_;
+ wire _01743_;
+ wire _01744_;
+ wire _01745_;
+ wire _01746_;
+ wire _01747_;
+ wire _01748_;
+ wire _01749_;
+ wire _01750_;
+ wire _01751_;
+ wire _01752_;
+ wire _01753_;
+ wire _01754_;
+ wire _01755_;
+ wire _01756_;
+ wire _01757_;
+ wire _01758_;
+ wire _01759_;
+ wire _01760_;
+ wire _01761_;
+ wire _01762_;
+ wire _01763_;
+ wire _01764_;
+ wire _01765_;
+ wire _01766_;
+ wire _01767_;
+ wire _01768_;
+ wire _01769_;
+ wire _01770_;
+ wire _01771_;
+ wire _01772_;
+ wire _01773_;
+ wire _01774_;
+ wire _01775_;
+ wire _01776_;
+ wire _01777_;
+ wire _01778_;
+ wire _01779_;
+ wire _01780_;
+ wire _01781_;
+ wire _01782_;
+ wire _01783_;
+ wire _01784_;
+ wire _01785_;
+ wire _01786_;
+ wire _01787_;
+ wire _01788_;
+ wire _01789_;
+ wire _01790_;
+ wire _01791_;
+ wire _01792_;
+ wire _01793_;
+ wire _01794_;
+ wire _01795_;
+ wire _01796_;
+ wire _01797_;
+ wire _01798_;
+ wire _01799_;
+ wire _01800_;
+ wire _01801_;
+ wire _01802_;
+ wire _01803_;
+ wire _01804_;
+ wire _01805_;
+ wire _01806_;
+ wire _01807_;
+ wire _01808_;
+ wire _01809_;
+ wire _01810_;
+ wire _01811_;
+ wire _01812_;
+ wire _01813_;
+ wire _01814_;
+ wire _01815_;
+ wire _01816_;
+ wire _01817_;
+ wire _01818_;
+ wire _01819_;
+ wire _01820_;
+ wire _01821_;
+ wire _01822_;
+ wire _01823_;
+ wire _01824_;
+ wire _01825_;
+ wire _01826_;
+ wire _01827_;
+ wire _01828_;
+ wire _01829_;
+ wire _01830_;
+ wire _01831_;
+ wire _01832_;
+ wire _01833_;
+ wire _01834_;
+ wire _01835_;
+ wire _01836_;
+ wire _01837_;
+ wire _01838_;
+ wire _01839_;
+ wire _01840_;
+ wire _01841_;
+ wire _01842_;
+ wire _01843_;
+ wire _01844_;
+ wire _01845_;
+ wire _01846_;
+ wire _01847_;
+ wire _01848_;
+ wire _01849_;
+ wire _01850_;
+ wire _01851_;
+ wire _01852_;
+ wire _01853_;
+ wire _01854_;
+ wire _01855_;
+ wire _01856_;
+ wire _01857_;
+ wire _01858_;
+ wire _01859_;
+ wire _01860_;
+ wire _01861_;
+ wire _01862_;
+ wire _01863_;
+ wire _01864_;
+ wire _01865_;
+ wire _01866_;
+ wire _01867_;
+ wire _01868_;
+ wire _01869_;
+ wire _01870_;
+ wire _01871_;
+ wire _01872_;
+ wire _01873_;
+ wire _01874_;
+ wire _01875_;
+ wire _01876_;
+ wire _01877_;
+ wire _01878_;
+ wire _01879_;
+ wire _01880_;
+ wire _01881_;
+ wire _01882_;
+ wire _01883_;
+ wire _01884_;
+ wire _01885_;
+ wire _01886_;
+ wire _01887_;
+ wire _01888_;
+ wire _01889_;
+ wire _01890_;
+ wire _01891_;
+ wire _01892_;
+ wire _01893_;
+ wire _01894_;
+ wire _01895_;
+ wire _01896_;
+ wire _01897_;
+ wire _01898_;
+ wire _01899_;
+ wire _01900_;
+ wire _01901_;
+ wire _01902_;
+ wire _01903_;
+ wire _01904_;
+ wire _01905_;
+ wire _01906_;
+ wire _01907_;
+ wire _01908_;
+ wire _01909_;
+ wire _01910_;
+ wire _01911_;
+ wire _01912_;
+ wire _01913_;
+ wire _01914_;
+ wire _01915_;
+ wire _01916_;
+ wire _01917_;
+ wire _01918_;
+ wire _01919_;
+ wire _01920_;
+ wire _01921_;
+ wire _01922_;
+ wire _01923_;
+ wire _01924_;
+ wire _01925_;
+ wire _01926_;
+ wire _01927_;
+ wire _01928_;
+ wire _01929_;
+ wire _01930_;
+ wire _01931_;
+ wire _01932_;
+ wire _01933_;
+ wire _01934_;
+ wire _01935_;
+ wire _01936_;
+ wire _01937_;
+ wire _01938_;
+ wire _01939_;
+ wire _01940_;
+ wire _01941_;
+ wire _01942_;
+ wire _01943_;
+ wire _01944_;
+ wire _01945_;
+ wire _01946_;
+ wire _01947_;
+ wire _01948_;
+ wire _01949_;
+ wire _01950_;
+ wire _01951_;
+ wire _01952_;
+ wire _01953_;
+ wire _01954_;
+ wire _01955_;
+ wire _01956_;
+ wire _01957_;
+ wire _01958_;
+ wire _01959_;
+ wire _01960_;
+ wire _01961_;
+ wire _01962_;
+ wire _01963_;
+ wire _01964_;
+ wire _01965_;
+ wire _01966_;
+ wire _01967_;
+ wire _01968_;
+ wire _01969_;
+ wire _01970_;
+ wire _01971_;
+ wire _01972_;
+ wire _01973_;
+ wire _01974_;
+ wire _01975_;
+ wire _01976_;
+ wire _01977_;
+ wire _01978_;
+ wire _01979_;
+ wire _01980_;
+ wire _01981_;
+ wire _01982_;
+ wire _01983_;
+ wire _01984_;
+ wire _01985_;
+ wire _01986_;
+ wire _01987_;
+ wire _01988_;
+ wire _01989_;
+ wire _01990_;
+ wire _01991_;
+ wire _01992_;
+ wire _01993_;
+ wire _01994_;
+ wire _01995_;
+ wire _01996_;
+ wire _01997_;
+ wire _01998_;
+ wire _01999_;
+ wire _02000_;
+ wire _02001_;
+ wire _02002_;
+ wire _02003_;
+ wire _02004_;
+ wire _02005_;
+ wire _02006_;
+ wire _02007_;
+ wire _02008_;
+ wire _02009_;
+ wire _02010_;
+ wire _02011_;
+ wire _02012_;
+ wire _02013_;
+ wire _02014_;
+ wire _02015_;
+ wire _02016_;
+ wire _02017_;
+ wire _02018_;
+ wire _02019_;
+ wire _02020_;
+ wire _02021_;
+ wire _02022_;
+ wire _02023_;
+ wire _02024_;
+ wire _02025_;
+ wire _02026_;
+ wire _02027_;
+ wire _02028_;
+ wire _02029_;
+ wire _02030_;
+ wire _02031_;
+ wire _02032_;
+ wire _02033_;
+ wire _02034_;
+ wire _02035_;
+ wire _02036_;
+ wire _02037_;
+ wire _02038_;
+ wire _02039_;
+ wire _02040_;
+ wire _02041_;
+ wire _02042_;
+ wire _02043_;
+ wire _02044_;
+ wire _02045_;
+ wire _02046_;
+ wire _02047_;
+ wire _02048_;
+ wire _02049_;
+ wire _02050_;
+ wire _02051_;
+ wire _02052_;
+ wire _02053_;
+ wire _02054_;
+ wire _02055_;
+ wire _02056_;
+ wire _02057_;
+ wire _02058_;
+ wire _02059_;
+ wire _02060_;
+ wire _02061_;
+ wire _02062_;
+ wire _02063_;
+ wire _02064_;
+ wire _02065_;
+ wire _02066_;
+ wire _02067_;
+ wire _02068_;
+ wire _02069_;
+ wire _02070_;
+ wire _02071_;
+ wire _02072_;
+ wire _02073_;
+ wire _02074_;
+ wire _02075_;
+ wire _02076_;
+ wire _02077_;
+ wire _02078_;
+ wire _02079_;
+ wire _02080_;
+ wire _02081_;
+ wire _02082_;
+ wire _02083_;
+ wire _02084_;
+ wire _02085_;
+ wire _02086_;
+ wire _02087_;
+ wire _02088_;
+ wire _02089_;
+ wire _02090_;
+ wire _02091_;
+ wire _02092_;
+ wire _02093_;
+ wire _02094_;
+ wire _02095_;
+ wire _02096_;
+ wire _02097_;
+ wire _02098_;
+ wire _02099_;
+ wire _02100_;
+ wire _02101_;
+ wire _02102_;
+ wire _02103_;
+ wire _02104_;
+ wire _02105_;
+ wire _02106_;
+ wire _02107_;
+ wire _02108_;
+ wire _02109_;
+ wire _02110_;
+ wire _02111_;
+ wire _02112_;
+ wire _02113_;
+ wire _02114_;
+ wire _02115_;
+ wire _02116_;
+ wire _02117_;
+ wire _02118_;
+ wire _02119_;
+ wire _02120_;
+ wire _02121_;
+ wire _02122_;
+ wire _02123_;
+ wire _02124_;
+ wire _02125_;
+ wire _02126_;
+ wire _02127_;
+ wire _02128_;
+ wire _02129_;
+ wire _02130_;
+ wire _02131_;
+ wire _02132_;
+ wire _02133_;
+ wire _02134_;
+ wire _02135_;
+ wire _02136_;
+ wire _02137_;
+ wire _02138_;
+ wire _02139_;
+ wire _02140_;
+ wire _02141_;
+ wire _02142_;
+ wire _02143_;
+ wire _02144_;
+ wire _02145_;
+ wire _02146_;
+ wire _02147_;
+ wire _02148_;
+ wire _02149_;
+ wire _02150_;
+ wire _02151_;
+ wire _02152_;
+ wire _02153_;
+ wire _02154_;
+ wire _02155_;
+ wire _02156_;
+ wire _02157_;
+ wire _02158_;
+ wire _02159_;
+ wire _02160_;
+ wire _02161_;
+ wire _02162_;
+ wire _02163_;
+ wire _02164_;
+ wire _02165_;
+ wire _02166_;
+ wire _02167_;
+ wire _02168_;
+ wire _02169_;
+ wire _02170_;
+ wire _02171_;
+ wire _02172_;
+ wire _02173_;
+ wire _02174_;
+ wire _02175_;
+ wire _02176_;
+ wire _02177_;
+ wire _02178_;
+ wire _02179_;
+ wire _02180_;
+ wire _02181_;
+ wire _02182_;
+ wire _02183_;
+ wire _02184_;
+ wire _02185_;
+ wire _02186_;
+ wire _02187_;
+ wire _02188_;
+ wire _02189_;
+ wire _02190_;
+ wire _02191_;
+ wire _02192_;
+ wire _02193_;
+ wire _02194_;
+ wire _02195_;
+ wire _02196_;
+ wire _02197_;
+ wire _02198_;
+ wire _02199_;
+ wire _02200_;
+ wire _02201_;
+ wire _02202_;
+ wire _02203_;
+ wire _02204_;
+ wire _02205_;
+ wire _02206_;
+ wire _02207_;
+ wire _02208_;
+ wire _02209_;
+ wire _02210_;
+ wire _02211_;
+ wire _02212_;
+ wire _02213_;
+ wire _02214_;
+ wire _02215_;
+ wire _02216_;
+ wire _02217_;
+ wire _02218_;
+ wire _02219_;
+ wire _02220_;
+ wire _02221_;
+ wire _02222_;
+ wire _02223_;
+ wire _02224_;
+ wire _02225_;
+ wire _02226_;
+ wire _02227_;
+ wire _02228_;
+ wire _02229_;
+ wire _02230_;
+ wire _02231_;
+ wire _02232_;
+ wire _02233_;
+ wire _02234_;
+ wire _02235_;
+ wire _02236_;
+ wire _02237_;
+ wire _02238_;
+ wire _02239_;
+ wire _02240_;
+ wire _02241_;
+ wire _02242_;
+ wire _02243_;
+ wire _02244_;
+ wire _02245_;
+ wire _02246_;
+ wire _02247_;
+ wire _02248_;
+ wire _02249_;
+ wire _02250_;
+ wire _02251_;
+ wire _02252_;
+ wire _02253_;
+ wire _02254_;
+ wire _02255_;
+ wire _02256_;
+ wire _02257_;
+ wire _02258_;
+ wire _02259_;
+ wire _02260_;
+ wire _02261_;
+ wire _02262_;
+ wire _02263_;
+ wire _02264_;
+ wire _02265_;
+ wire _02266_;
+ wire _02267_;
+ wire _02268_;
+ wire _02269_;
+ wire _02270_;
+ wire _02271_;
+ wire _02272_;
+ wire _02273_;
+ wire _02274_;
+ wire _02275_;
+ wire _02276_;
+ wire _02277_;
+ wire _02278_;
+ wire _02279_;
+ wire _02280_;
+ wire _02281_;
+ wire _02282_;
+ wire _02283_;
+ wire _02284_;
+ wire _02285_;
+ wire _02286_;
+ wire _02287_;
+ wire _02288_;
+ wire _02289_;
+ wire _02290_;
+ wire _02291_;
+ wire _02292_;
+ wire _02293_;
+ wire _02294_;
+ wire _02295_;
+ wire _02296_;
+ wire _02297_;
+ wire _02298_;
+ wire _02299_;
+ wire _02300_;
+ wire _02301_;
+ wire _02302_;
+ wire _02303_;
+ wire _02304_;
+ wire _02305_;
+ wire _02306_;
+ wire _02307_;
+ wire _02308_;
+ wire _02309_;
+ wire _02310_;
+ wire _02311_;
+ wire _02312_;
+ wire _02313_;
+ wire _02314_;
+ wire _02315_;
+ wire _02316_;
+ wire _02317_;
+ wire _02318_;
+ wire _02319_;
+ wire _02320_;
+ wire _02321_;
+ wire _02322_;
+ wire _02323_;
+ wire _02324_;
+ wire _02325_;
+ wire _02326_;
+ wire _02327_;
+ wire _02328_;
+ wire _02329_;
+ wire _02330_;
+ wire _02331_;
+ wire _02332_;
+ wire _02333_;
+ wire _02334_;
+ wire _02335_;
+ wire _02336_;
+ wire _02337_;
+ wire _02338_;
+ wire _02339_;
+ wire _02340_;
+ wire _02341_;
+ wire _02342_;
+ wire _02343_;
+ wire _02344_;
+ wire _02345_;
+ wire _02346_;
+ wire _02347_;
+ wire _02348_;
+ wire _02349_;
+ wire _02350_;
+ wire _02351_;
+ wire _02352_;
+ wire _02353_;
+ wire _02354_;
+ wire _02355_;
+ wire _02356_;
+ wire _02357_;
+ wire _02358_;
+ wire _02359_;
+ wire _02360_;
+ wire _02361_;
+ wire _02362_;
+ wire _02363_;
+ wire _02364_;
+ wire _02365_;
+ wire _02366_;
+ wire _02367_;
+ wire _02368_;
+ wire _02369_;
+ wire _02370_;
+ wire _02371_;
+ wire _02372_;
+ wire _02373_;
+ wire _02374_;
+ wire _02375_;
+ wire _02376_;
+ wire _02377_;
+ wire _02378_;
+ wire _02379_;
+ wire _02380_;
+ wire _02381_;
+ wire _02382_;
+ wire _02383_;
+ wire _02384_;
+ wire _02385_;
+ wire _02386_;
+ wire _02387_;
+ wire _02388_;
+ wire _02389_;
+ wire _02390_;
+ wire _02391_;
+ wire _02392_;
+ wire _02393_;
+ wire _02394_;
+ wire _02395_;
+ wire _02396_;
+ wire _02397_;
+ wire _02398_;
+ wire _02399_;
+ wire _02400_;
+ wire _02401_;
+ wire _02402_;
+ wire _02403_;
+ wire _02404_;
+ wire _02405_;
+ wire _02406_;
+ wire _02407_;
+ wire _02408_;
+ wire _02409_;
+ wire _02410_;
+ wire _02411_;
+ wire _02412_;
+ wire _02413_;
+ wire _02414_;
+ wire _02415_;
+ wire _02416_;
+ wire _02417_;
+ wire _02418_;
+ wire _02419_;
+ wire _02420_;
+ wire _02421_;
+ wire _02422_;
+ wire _02423_;
+ wire _02424_;
+ wire _02425_;
+ wire _02426_;
+ wire _02427_;
+ wire _02428_;
+ wire _02429_;
+ wire _02430_;
+ wire _02431_;
+ wire _02432_;
+ wire _02433_;
+ wire _02434_;
+ wire _02435_;
+ wire _02436_;
+ wire _02437_;
+ wire _02438_;
+ wire _02439_;
+ wire _02440_;
+ wire _02441_;
+ wire _02442_;
+ wire _02443_;
+ wire _02444_;
+ wire _02445_;
+ wire _02446_;
+ wire _02447_;
+ wire _02448_;
+ wire _02449_;
+ wire _02450_;
+ wire _02451_;
+ wire _02452_;
+ wire _02453_;
+ wire _02454_;
+ wire _02455_;
+ wire _02456_;
+ wire _02457_;
+ wire _02458_;
+ wire _02459_;
+ wire _02460_;
+ wire _02461_;
+ wire _02462_;
+ wire _02463_;
+ wire _02464_;
+ wire _02465_;
+ wire _02466_;
+ wire _02467_;
+ wire _02468_;
+ wire _02469_;
+ wire _02470_;
+ wire _02471_;
+ wire _02472_;
+ wire _02473_;
+ wire _02474_;
+ wire _02475_;
+ wire _02476_;
+ wire _02477_;
+ wire _02478_;
+ wire _02479_;
+ wire _02480_;
+ wire _02481_;
+ wire _02482_;
+ wire _02483_;
+ wire _02484_;
+ wire _02485_;
+ wire _02486_;
+ wire _02487_;
+ wire _02488_;
+ wire _02489_;
+ wire _02490_;
+ wire _02491_;
+ wire _02492_;
+ wire _02493_;
+ wire _02494_;
+ wire _02495_;
+ wire _02496_;
+ wire _02497_;
+ wire _02498_;
+ wire _02499_;
+ wire _02500_;
+ wire _02501_;
+ wire _02502_;
+ wire _02503_;
+ wire _02504_;
+ wire _02505_;
+ wire _02506_;
+ wire _02507_;
+ wire _02508_;
+ wire _02509_;
+ wire _02510_;
+ wire _02511_;
+ wire _02512_;
+ wire _02513_;
+ wire _02514_;
+ wire _02515_;
+ wire _02516_;
+ wire _02517_;
+ wire _02518_;
+ wire _02519_;
+ wire _02520_;
+ wire _02521_;
+ wire _02522_;
+ wire _02523_;
+ wire _02524_;
+ wire _02525_;
+ wire _02526_;
+ wire _02527_;
+ wire _02528_;
+ wire _02529_;
+ wire _02530_;
+ wire _02531_;
+ wire _02532_;
+ wire _02533_;
+ wire _02534_;
+ wire _02535_;
+ wire _02536_;
+ wire _02537_;
+ wire _02538_;
+ wire _02539_;
+ wire _02540_;
+ wire _02541_;
+ wire _02542_;
+ wire _02543_;
+ wire _02544_;
+ wire _02545_;
+ wire _02546_;
+ wire _02547_;
+ wire _02548_;
+ wire _02549_;
+ wire _02550_;
+ wire _02551_;
+ wire _02552_;
+ wire _02553_;
+ wire _02554_;
+ wire _02555_;
+ wire _02556_;
+ wire _02557_;
+ wire _02558_;
+ wire _02559_;
+ wire _02560_;
+ wire _02561_;
+ wire _02562_;
+ wire _02563_;
+ wire _02564_;
+ wire _02565_;
+ wire _02566_;
+ wire _02567_;
+ wire _02568_;
+ wire _02569_;
+ wire _02570_;
+ wire _02571_;
+ wire _02572_;
+ wire _02573_;
+ wire _02574_;
+ wire _02575_;
+ wire _02576_;
+ wire _02577_;
+ wire _02578_;
+ wire _02579_;
+ wire _02580_;
+ wire _02581_;
+ wire _02582_;
+ wire _02583_;
+ wire _02584_;
+ wire _02585_;
+ wire _02586_;
+ wire _02587_;
+ wire _02588_;
+ wire _02589_;
+ wire _02590_;
+ wire _02591_;
+ wire _02592_;
+ wire _02593_;
+ wire _02594_;
+ wire _02595_;
+ wire _02596_;
+ wire _02597_;
+ wire _02598_;
+ wire _02599_;
+ wire _02600_;
+ wire _02601_;
+ wire _02602_;
+ wire _02603_;
+ wire _02604_;
+ wire _02605_;
+ wire _02606_;
+ wire _02607_;
+ wire _02608_;
+ wire _02609_;
+ wire _02610_;
+ wire _02611_;
+ wire _02612_;
+ wire _02613_;
+ wire _02614_;
+ wire _02615_;
+ wire _02616_;
+ wire _02617_;
+ wire _02618_;
+ wire _02619_;
+ wire _02620_;
+ wire _02621_;
+ wire _02622_;
+ wire _02623_;
+ wire _02624_;
+ wire _02625_;
+ wire _02626_;
+ wire _02627_;
+ wire _02628_;
+ wire _02629_;
+ wire _02630_;
+ wire _02631_;
+ wire _02632_;
+ wire _02633_;
+ wire _02634_;
+ wire _02635_;
+ wire _02636_;
+ wire _02637_;
+ wire _02638_;
+ wire _02639_;
+ wire _02640_;
+ wire _02641_;
+ wire _02642_;
+ wire _02643_;
+ wire _02644_;
+ wire _02645_;
+ wire _02646_;
+ wire _02647_;
+ wire _02648_;
+ wire _02649_;
+ wire _02650_;
+ wire _02651_;
+ wire _02652_;
+ wire _02653_;
+ wire _02654_;
+ wire _02655_;
+ wire _02656_;
+ wire _02657_;
+ wire _02658_;
+ wire _02659_;
+ wire _02660_;
+ wire _02661_;
+ wire _02662_;
+ wire _02663_;
+ wire _02664_;
+ wire _02665_;
+ wire _02666_;
+ wire _02667_;
+ wire _02668_;
+ wire _02669_;
+ wire _02670_;
+ wire _02671_;
+ wire _02672_;
+ wire _02673_;
+ wire _02674_;
+ wire _02675_;
+ wire _02676_;
+ wire _02677_;
+ wire _02678_;
+ wire _02679_;
+ wire _02680_;
+ wire _02681_;
+ wire _02682_;
+ wire _02683_;
+ wire _02684_;
+ wire _02685_;
+ wire _02686_;
+ wire _02687_;
+ wire _02688_;
+ wire _02689_;
+ wire _02690_;
+ wire _02691_;
+ wire _02692_;
+ wire _02693_;
+ wire _02694_;
+ wire _02695_;
+ wire _02696_;
+ wire _02697_;
+ wire _02698_;
+ wire _02699_;
+ wire _02700_;
+ wire _02701_;
+ wire _02702_;
+ wire _02703_;
+ wire _02704_;
+ wire _02705_;
+ wire _02706_;
+ wire _02707_;
+ wire _02708_;
+ wire _02709_;
+ wire _02710_;
+ wire _02711_;
+ wire _02712_;
+ wire _02713_;
+ wire _02714_;
+ wire _02715_;
+ wire _02716_;
+ wire _02717_;
+ wire _02718_;
+ wire _02719_;
+ wire _02720_;
+ wire _02721_;
+ wire _02722_;
+ wire _02723_;
+ wire _02724_;
+ wire _02725_;
+ wire _02726_;
+ wire _02727_;
+ wire _02728_;
+ wire _02729_;
+ wire _02730_;
+ wire _02731_;
+ wire _02732_;
+ wire _02733_;
+ wire _02734_;
+ wire _02735_;
+ wire _02736_;
+ wire _02737_;
+ wire _02738_;
+ wire _02739_;
+ wire _02740_;
+ wire _02741_;
+ wire _02742_;
+ wire _02743_;
+ wire _02744_;
+ wire _02745_;
+ wire _02746_;
+ wire _02747_;
+ wire _02748_;
+ wire _02749_;
+ wire _02750_;
+ wire _02751_;
+ wire _02752_;
+ wire _02753_;
+ wire _02754_;
+ wire _02755_;
+ wire _02756_;
+ wire _02757_;
+ wire _02758_;
+ wire _02759_;
+ wire _02760_;
+ wire _02761_;
+ wire _02762_;
+ wire _02763_;
+ wire _02764_;
+ wire _02765_;
+ wire _02766_;
+ wire _02767_;
+ wire _02768_;
+ wire _02769_;
+ wire _02770_;
+ wire _02771_;
+ wire _02772_;
+ wire _02773_;
+ wire _02774_;
+ wire _02775_;
+ wire _02776_;
+ wire _02777_;
+ wire _02778_;
+ wire _02779_;
+ wire _02780_;
+ wire _02781_;
+ wire _02782_;
+ wire _02783_;
+ wire _02784_;
+ wire _02785_;
+ wire _02786_;
+ wire _02787_;
+ wire _02788_;
+ wire _02789_;
+ wire _02790_;
+ wire _02791_;
+ wire _02792_;
+ wire _02793_;
+ wire _02794_;
+ wire _02795_;
+ wire _02796_;
+ wire _02797_;
+ wire _02798_;
+ wire _02799_;
+ wire _02800_;
+ wire _02801_;
+ wire _02802_;
+ wire _02803_;
+ wire _02804_;
+ wire _02805_;
+ wire _02806_;
+ wire _02807_;
+ wire _02808_;
+ wire _02809_;
+ wire _02810_;
+ wire _02811_;
+ wire _02812_;
+ wire _02813_;
+ wire _02814_;
+ wire _02815_;
+ wire _02816_;
+ wire _02817_;
+ wire _02818_;
+ wire _02819_;
+ wire _02820_;
+ wire _02821_;
+ wire _02822_;
+ wire _02823_;
+ wire _02824_;
+ wire _02825_;
+ wire _02826_;
+ wire _02827_;
+ wire _02828_;
+ wire _02829_;
+ wire _02830_;
+ wire _02831_;
+ wire _02832_;
+ wire _02833_;
+ wire _02834_;
+ wire _02835_;
+ wire _02836_;
+ wire _02837_;
+ wire _02838_;
+ wire _02839_;
+ wire _02840_;
+ wire _02841_;
+ wire _02842_;
+ wire _02843_;
+ wire _02844_;
+ wire _02845_;
+ wire _02846_;
+ wire _02847_;
+ wire _02848_;
+ wire _02849_;
+ wire _02850_;
+ wire _02851_;
+ wire _02852_;
+ wire _02853_;
+ wire _02854_;
+ wire _02855_;
+ wire _02856_;
+ wire _02857_;
+ wire _02858_;
+ wire _02859_;
+ wire _02860_;
+ wire _02861_;
+ wire _02862_;
+ wire _02863_;
+ wire _02864_;
+ wire _02865_;
+ wire _02866_;
+ wire _02867_;
+ wire _02868_;
+ wire _02869_;
+ wire _02870_;
+ wire _02871_;
+ wire _02872_;
+ wire _02873_;
+ wire _02874_;
+ wire _02875_;
+ wire _02876_;
+ wire _02877_;
+ wire _02878_;
+ wire _02879_;
+ wire _02880_;
+ wire _02881_;
+ wire _02882_;
+ wire _02883_;
+ wire _02884_;
+ wire _02885_;
+ wire _02886_;
+ wire _02887_;
+ wire _02888_;
+ wire _02889_;
+ wire _02890_;
+ wire _02891_;
+ wire _02892_;
+ wire _02893_;
+ wire _02894_;
+ wire _02895_;
+ wire _02896_;
+ wire _02897_;
+ wire _02898_;
+ wire _02899_;
+ wire _02900_;
+ wire _02901_;
+ wire _02902_;
+ wire _02903_;
+ wire _02904_;
+ wire _02905_;
+ wire _02906_;
+ wire _02907_;
+ wire _02908_;
+ wire _02909_;
+ wire _02910_;
+ wire _02911_;
+ wire _02912_;
+ wire _02913_;
+ wire _02914_;
+ wire _02915_;
+ wire _02916_;
+ wire _02917_;
+ wire _02918_;
+ wire _02919_;
+ wire _02920_;
+ wire _02921_;
+ wire _02922_;
+ wire _02923_;
+ wire _02924_;
+ wire _02925_;
+ wire _02926_;
+ wire _02927_;
+ wire _02928_;
+ wire _02929_;
+ wire _02930_;
+ wire _02931_;
+ wire _02932_;
+ wire _02933_;
+ wire _02934_;
+ wire _02935_;
+ wire _02936_;
+ wire _02937_;
+ wire _02938_;
+ wire _02939_;
+ wire _02940_;
+ wire _02941_;
+ wire _02942_;
+ wire _02943_;
+ wire _02944_;
+ wire _02945_;
+ wire _02946_;
+ wire _02947_;
+ wire _02948_;
+ wire _02949_;
+ wire _02950_;
+ wire _02951_;
+ wire _02952_;
+ wire _02953_;
+ wire _02954_;
+ wire _02955_;
+ wire _02956_;
+ wire _02957_;
+ wire _02958_;
+ wire _02959_;
+ wire _02960_;
+ wire _02961_;
+ wire _02962_;
+ wire _02963_;
+ wire _02964_;
+ wire _02965_;
+ wire _02966_;
+ wire _02967_;
+ wire _02968_;
+ wire _02969_;
+ wire _02970_;
+ wire _02971_;
+ wire _02972_;
+ wire _02973_;
+ wire _02974_;
+ wire _02975_;
+ wire _02976_;
+ wire _02977_;
+ wire _02978_;
+ wire _02979_;
+ wire _02980_;
+ wire _02981_;
+ wire _02982_;
+ wire _02983_;
+ wire _02984_;
+ wire _02985_;
+ wire _02986_;
+ wire _02987_;
+ wire _02988_;
+ wire _02989_;
+ wire _02990_;
+ wire _02991_;
+ wire _02992_;
+ wire _02993_;
+ wire _02994_;
+ wire _02995_;
+ wire _02996_;
+ wire _02997_;
+ wire _02998_;
+ wire _02999_;
+ wire _03000_;
+ wire _03001_;
+ wire _03002_;
+ wire _03003_;
+ wire _03004_;
+ wire _03005_;
+ wire _03006_;
+ wire _03007_;
+ wire _03008_;
+ wire _03009_;
+ wire _03010_;
+ wire _03011_;
+ wire _03012_;
+ wire _03013_;
+ wire _03014_;
+ wire _03015_;
+ wire _03016_;
+ wire _03017_;
+ wire _03018_;
+ wire _03019_;
+ wire _03020_;
+ wire _03021_;
+ wire _03022_;
+ wire _03023_;
+ wire _03024_;
+ wire _03025_;
+ wire _03026_;
+ wire _03027_;
+ wire _03028_;
+ wire _03029_;
+ wire _03030_;
+ wire _03031_;
+ wire _03032_;
+ wire _03033_;
+ wire _03034_;
+ wire _03035_;
+ wire _03036_;
+ wire _03037_;
+ wire _03038_;
+ wire _03039_;
+ wire _03040_;
+ wire _03041_;
+ wire _03042_;
+ wire _03043_;
+ wire _03044_;
+ wire _03045_;
+ wire _03046_;
+ wire _03047_;
+ wire _03048_;
+ wire _03049_;
+ wire _03050_;
+ wire _03051_;
+ wire _03052_;
+ wire _03053_;
+ wire _03054_;
+ wire _03055_;
+ wire _03056_;
+ wire _03057_;
+ wire _03058_;
+ wire _03059_;
+ wire _03060_;
+ wire _03061_;
+ wire _03062_;
+ wire _03063_;
+ wire _03064_;
+ wire _03065_;
+ wire _03066_;
+ wire _03067_;
+ wire _03068_;
+ wire _03069_;
+ wire _03070_;
+ wire _03071_;
+ wire _03072_;
+ wire _03073_;
+ wire _03074_;
+ wire _03075_;
+ wire _03076_;
+ wire _03077_;
+ wire _03078_;
+ wire _03079_;
+ wire _03080_;
+ wire _03081_;
+ wire _03082_;
+ wire _03083_;
+ wire _03084_;
+ wire _03085_;
+ wire _03086_;
+ wire _03087_;
+ wire _03088_;
+ wire _03089_;
+ wire _03090_;
+ wire _03091_;
+ wire _03092_;
+ wire _03093_;
+ wire _03094_;
+ wire _03095_;
+ wire _03096_;
+ wire _03097_;
+ wire _03098_;
+ wire _03099_;
+ wire _03100_;
+ wire _03101_;
+ wire _03102_;
+ wire _03103_;
+ wire _03104_;
+ wire _03105_;
+ wire _03106_;
+ wire _03107_;
+ wire _03108_;
+ wire _03109_;
+ wire _03110_;
+ wire _03111_;
+ wire _03112_;
+ wire _03113_;
+ wire _03114_;
+ wire _03115_;
+ wire _03116_;
+ wire _03117_;
+ wire _03118_;
+ wire _03119_;
+ wire _03120_;
+ wire _03121_;
+ wire _03122_;
+ wire _03123_;
+ wire _03124_;
+ wire _03125_;
+ wire _03126_;
+ wire _03127_;
+ wire _03128_;
+ wire _03129_;
+ wire _03130_;
+ wire _03131_;
+ wire _03132_;
+ wire _03133_;
+ wire _03134_;
+ wire _03135_;
+ wire _03136_;
+ wire _03137_;
+ wire _03138_;
+ wire _03139_;
+ wire _03140_;
+ wire _03141_;
+ wire _03142_;
+ wire _03143_;
+ wire _03144_;
+ wire _03145_;
+ wire _03146_;
+ wire _03147_;
+ wire _03148_;
+ wire _03149_;
+ wire _03150_;
+ wire _03151_;
+ wire _03152_;
+ wire _03153_;
+ wire _03154_;
+ wire _03155_;
+ wire _03156_;
+ wire _03157_;
+ wire _03158_;
+ wire _03159_;
+ wire _03160_;
+ wire _03161_;
+ wire _03162_;
+ wire _03163_;
+ wire _03164_;
+ wire _03165_;
+ wire _03166_;
+ wire _03167_;
+ wire _03168_;
+ wire _03169_;
+ wire _03170_;
+ wire _03171_;
+ wire _03172_;
+ wire _03173_;
+ wire _03174_;
+ wire _03175_;
+ wire _03176_;
+ wire _03177_;
+ wire _03178_;
+ wire _03179_;
+ wire _03180_;
+ wire _03181_;
+ wire _03182_;
+ wire _03183_;
+ wire _03184_;
+ wire _03185_;
+ wire _03186_;
+ wire _03187_;
+ wire _03188_;
+ wire _03189_;
+ wire _03190_;
+ wire _03191_;
+ wire _03192_;
+ wire _03193_;
+ wire _03194_;
+ wire _03195_;
+ wire _03196_;
+ wire _03197_;
+ wire _03198_;
+ wire _03199_;
+ wire _03200_;
+ wire _03201_;
+ wire _03202_;
+ wire _03203_;
+ wire _03204_;
+ wire _03205_;
+ wire _03206_;
+ wire _03207_;
+ wire _03208_;
+ wire _03209_;
+ wire _03210_;
+ wire _03211_;
+ wire _03212_;
+ wire _03213_;
+ wire _03214_;
+ wire _03215_;
+ wire _03216_;
+ wire _03217_;
+ wire _03218_;
+ wire _03219_;
+ wire _03220_;
+ wire _03221_;
+ wire _03222_;
+ wire _03223_;
+ wire _03224_;
+ wire _03225_;
+ wire _03226_;
+ wire _03227_;
+ wire _03228_;
+ wire _03229_;
+ wire _03230_;
+ wire _03231_;
+ wire _03232_;
+ wire _03233_;
+ wire _03234_;
+ wire _03235_;
+ wire _03236_;
+ wire _03237_;
+ wire _03238_;
+ wire _03239_;
+ wire _03240_;
+ wire _03241_;
+ wire _03242_;
+ wire _03243_;
+ wire _03244_;
+ wire _03245_;
+ wire _03246_;
+ wire _03247_;
+ wire _03248_;
+ wire _03249_;
+ wire _03250_;
+ wire _03251_;
+ wire _03252_;
+ wire _03253_;
+ wire _03254_;
+ wire _03255_;
+ wire _03256_;
+ wire _03257_;
+ wire _03258_;
+ wire _03259_;
+ wire _03260_;
+ wire _03261_;
+ wire _03262_;
+ wire _03263_;
+ wire _03264_;
+ wire _03265_;
+ wire _03266_;
+ wire _03267_;
+ wire _03268_;
+ wire _03269_;
+ wire _03270_;
+ wire _03271_;
+ wire _03272_;
+ wire _03273_;
+ wire _03274_;
+ wire _03275_;
+ wire _03276_;
+ wire _03277_;
+ wire _03278_;
+ wire _03279_;
+ wire _03280_;
+ wire _03281_;
+ wire _03282_;
+ wire _03283_;
+ wire _03284_;
+ wire _03285_;
+ wire _03286_;
+ wire _03287_;
+ wire _03288_;
+ wire _03289_;
+ wire _03290_;
+ wire _03291_;
+ wire _03292_;
+ wire _03293_;
+ wire _03294_;
+ wire _03295_;
+ wire _03296_;
+ wire _03297_;
+ wire _03298_;
+ wire _03299_;
+ wire _03300_;
+ wire _03301_;
+ wire _03302_;
+ wire _03303_;
+ wire _03304_;
+ wire _03305_;
+ wire _03306_;
+ wire _03307_;
+ wire _03308_;
+ wire _03309_;
+ wire _03310_;
+ wire _03311_;
+ wire _03312_;
+ wire _03313_;
+ wire _03314_;
+ wire _03315_;
+ wire _03316_;
+ wire _03317_;
+ wire _03318_;
+ wire _03319_;
+ wire _03320_;
+ wire _03321_;
+ wire _03322_;
+ wire _03323_;
+ wire _03324_;
+ wire _03325_;
+ wire _03326_;
+ wire _03327_;
+ wire _03328_;
+ wire _03329_;
+ wire _03330_;
+ wire _03331_;
+ wire _03332_;
+ wire _03333_;
+ wire _03334_;
+ wire _03335_;
+ wire _03336_;
+ wire _03337_;
+ wire _03338_;
+ wire _03339_;
+ wire _03340_;
+ wire _03341_;
+ wire _03342_;
+ wire _03343_;
+ wire _03344_;
+ wire _03345_;
+ wire _03346_;
+ wire _03347_;
+ wire _03348_;
+ wire _03349_;
+ wire _03350_;
+ wire _03351_;
+ wire _03352_;
+ wire _03353_;
+ wire _03354_;
+ wire _03355_;
+ wire _03356_;
+ wire _03357_;
+ wire _03358_;
+ wire _03359_;
+ wire _03360_;
+ wire _03361_;
+ wire _03362_;
+ wire _03363_;
+ wire _03364_;
+ wire _03365_;
+ wire _03366_;
+ wire _03367_;
+ wire _03368_;
+ wire _03369_;
+ wire _03370_;
+ wire _03371_;
+ wire _03372_;
+ wire _03373_;
+ wire _03374_;
+ wire _03375_;
+ wire _03376_;
+ wire _03377_;
+ wire _03378_;
+ wire _03379_;
+ wire _03380_;
+ wire _03381_;
+ wire _03382_;
+ wire _03383_;
+ wire _03384_;
+ wire _03385_;
+ wire _03386_;
+ wire _03387_;
+ wire _03388_;
+ wire _03389_;
+ wire _03390_;
+ wire _03391_;
+ wire _03392_;
+ wire _03393_;
+ wire _03394_;
+ wire _03395_;
+ wire _03396_;
+ wire _03397_;
+ wire _03398_;
+ wire _03399_;
+ wire _03400_;
+ wire _03401_;
+ wire _03402_;
+ wire _03403_;
+ wire _03404_;
+ wire _03405_;
+ wire _03406_;
+ wire _03407_;
+ wire _03408_;
+ wire _03409_;
+ wire _03410_;
+ wire _03411_;
+ wire _03412_;
+ wire _03413_;
+ wire _03414_;
+ wire _03415_;
+ wire _03416_;
+ wire _03417_;
+ wire _03418_;
+ wire _03419_;
+ wire _03420_;
+ wire _03421_;
+ wire _03422_;
+ wire _03423_;
+ wire _03424_;
+ wire _03425_;
+ wire _03426_;
+ wire _03427_;
+ wire _03428_;
+ wire _03429_;
+ wire _03430_;
+ wire _03431_;
+ wire _03432_;
+ wire _03433_;
+ wire _03434_;
+ wire _03435_;
+ wire _03436_;
+ wire _03437_;
+ wire _03438_;
+ wire _03439_;
+ wire _03440_;
+ wire _03441_;
+ wire _03442_;
+ wire _03443_;
+ wire _03444_;
+ wire _03445_;
+ wire _03446_;
+ wire _03447_;
+ wire _03448_;
+ wire _03449_;
+ wire _03450_;
+ wire _03451_;
+ wire _03452_;
+ wire _03453_;
+ wire _03454_;
+ wire _03455_;
+ wire _03456_;
+ wire _03457_;
+ wire _03458_;
+ wire _03459_;
+ wire _03460_;
+ wire _03461_;
+ wire _03462_;
+ wire _03463_;
+ wire _03464_;
+ wire _03465_;
+ wire _03466_;
+ wire _03467_;
+ wire _03468_;
+ wire _03469_;
+ wire _03470_;
+ wire _03471_;
+ wire _03472_;
+ wire _03473_;
+ wire _03474_;
+ wire _03475_;
+ wire _03476_;
+ wire _03477_;
+ wire _03478_;
+ wire _03479_;
+ wire _03480_;
+ wire _03481_;
+ wire _03482_;
+ wire _03483_;
+ wire _03484_;
+ wire _03485_;
+ wire _03486_;
+ wire _03487_;
+ wire _03488_;
+ wire _03489_;
+ wire _03490_;
+ wire _03491_;
+ wire _03492_;
+ wire _03493_;
+ wire _03494_;
+ wire _03495_;
+ wire _03496_;
+ wire _03497_;
+ wire _03498_;
+ wire _03499_;
+ wire _03500_;
+ wire _03501_;
+ wire _03502_;
+ wire _03503_;
+ wire _03504_;
+ wire _03505_;
+ wire _03506_;
+ wire _03507_;
+ wire _03508_;
+ wire _03509_;
+ wire _03510_;
+ wire _03511_;
+ wire _03512_;
+ wire _03513_;
+ wire _03514_;
+ wire _03515_;
+ wire _03516_;
+ wire _03517_;
+ wire _03518_;
+ wire _03519_;
+ wire _03520_;
+ wire _03521_;
+ wire _03522_;
+ wire _03523_;
+ wire _03524_;
+ wire _03525_;
+ wire _03526_;
+ wire _03527_;
+ wire _03528_;
+ wire _03529_;
+ wire _03530_;
+ wire _03531_;
+ wire _03532_;
+ wire _03533_;
+ wire _03534_;
+ wire _03535_;
+ wire _03536_;
+ wire _03537_;
+ wire _03538_;
+ wire _03539_;
+ wire _03540_;
+ wire _03541_;
+ wire _03542_;
+ wire _03543_;
+ wire _03544_;
+ wire _03545_;
+ wire _03546_;
+ wire _03547_;
+ wire _03548_;
+ wire _03549_;
+ wire _03550_;
+ wire _03551_;
+ wire _03552_;
+ wire _03553_;
+ wire _03554_;
+ wire _03555_;
+ wire _03556_;
+ wire _03557_;
+ wire _03558_;
+ wire _03559_;
+ wire _03560_;
+ wire _03561_;
+ wire _03562_;
+ wire _03563_;
+ wire _03564_;
+ wire _03565_;
+ wire _03566_;
+ wire _03567_;
+ wire _03568_;
+ wire _03569_;
+ wire _03570_;
+ wire _03571_;
+ wire _03572_;
+ wire _03573_;
+ wire _03574_;
+ wire _03575_;
+ wire _03576_;
+ wire _03577_;
+ wire _03578_;
+ wire _03579_;
+ wire _03580_;
+ wire _03581_;
+ wire _03582_;
+ wire _03583_;
+ wire _03584_;
+ wire _03585_;
+ wire _03586_;
+ wire _03587_;
+ wire _03588_;
+ wire _03589_;
+ wire _03590_;
+ wire _03591_;
+ wire _03592_;
+ wire _03593_;
+ wire _03594_;
+ wire _03595_;
+ wire _03596_;
+ wire _03597_;
+ wire _03598_;
+ wire _03599_;
+ wire _03600_;
+ wire _03601_;
+ wire _03602_;
+ wire _03603_;
+ wire _03604_;
+ wire _03605_;
+ wire _03606_;
+ wire _03607_;
+ wire _03608_;
+ wire _03609_;
+ wire _03610_;
+ wire _03611_;
+ wire _03612_;
+ wire _03613_;
+ wire _03614_;
+ wire _03615_;
+ wire _03616_;
+ wire _03617_;
+ wire _03618_;
+ wire _03619_;
+ wire _03620_;
+ wire _03621_;
+ wire _03622_;
+ wire _03623_;
+ wire _03624_;
+ wire _03625_;
+ wire _03626_;
+ wire _03627_;
+ wire _03628_;
+ wire _03629_;
+ wire _03630_;
+ wire _03631_;
+ wire _03632_;
+ wire _03633_;
+ wire _03634_;
+ wire _03635_;
+ wire _03636_;
+ wire _03637_;
+ wire _03638_;
+ wire _03639_;
+ wire _03640_;
+ wire _03641_;
+ wire _03642_;
+ wire _03643_;
+ wire _03644_;
+ wire _03645_;
+ wire _03646_;
+ wire _03647_;
+ wire _03648_;
+ wire _03649_;
+ wire _03650_;
+ wire _03651_;
+ wire _03652_;
+ wire _03653_;
+ wire _03654_;
+ wire _03655_;
+ wire _03656_;
+ wire _03657_;
+ wire _03658_;
+ wire _03659_;
+ wire _03660_;
+ wire _03661_;
+ wire _03662_;
+ wire _03663_;
+ wire _03664_;
+ wire _03665_;
+ wire _03666_;
+ wire _03667_;
+ wire _03668_;
+ wire _03669_;
+ wire _03670_;
+ wire _03671_;
+ wire _03672_;
+ wire _03673_;
+ wire _03674_;
+ wire _03675_;
+ wire _03676_;
+ wire _03677_;
+ wire _03678_;
+ wire _03679_;
+ wire _03680_;
+ wire _03681_;
+ wire _03682_;
+ wire _03683_;
+ wire _03684_;
+ wire _03685_;
+ wire _03686_;
+ wire _03687_;
+ wire _03688_;
+ wire _03689_;
+ wire _03690_;
+ wire _03691_;
+ wire _03692_;
+ wire _03693_;
+ wire _03694_;
+ wire _03695_;
+ wire _03696_;
+ wire _03697_;
+ wire _03698_;
+ wire _03699_;
+ wire _03700_;
+ wire _03701_;
+ wire _03702_;
+ wire _03703_;
+ wire _03704_;
+ wire _03705_;
+ wire _03706_;
+ wire _03707_;
+ wire _03708_;
+ wire _03709_;
+ wire _03710_;
+ wire _03711_;
+ wire _03712_;
+ wire _03713_;
+ wire _03714_;
+ wire _03715_;
+ wire _03716_;
+ wire _03717_;
+ wire _03718_;
+ wire _03719_;
+ wire _03720_;
+ wire _03721_;
+ wire _03722_;
+ wire _03723_;
+ wire _03724_;
+ wire _03725_;
+ wire _03726_;
+ wire _03727_;
+ wire _03728_;
+ wire _03729_;
+ wire _03730_;
+ wire _03731_;
+ wire _03732_;
+ wire _03733_;
+ wire _03734_;
+ wire _03735_;
+ wire _03736_;
+ wire _03737_;
+ wire _03738_;
+ wire _03739_;
+ wire _03740_;
+ wire _03741_;
+ wire _03742_;
+ wire _03743_;
+ wire _03744_;
+ wire _03745_;
+ wire _03746_;
+ wire _03747_;
+ wire _03748_;
+ wire _03749_;
+ wire _03750_;
+ wire _03751_;
+ wire _03752_;
+ wire _03753_;
+ wire _03754_;
+ wire _03755_;
+ wire _03756_;
+ wire _03757_;
+ wire _03758_;
+ wire _03759_;
+ wire _03760_;
+ wire _03761_;
+ wire _03762_;
+ wire _03763_;
+ wire _03764_;
+ wire _03765_;
+ wire _03766_;
+ wire _03767_;
+ wire _03768_;
+ wire _03769_;
+ wire _03770_;
+ wire _03771_;
+ wire _03772_;
+ wire _03773_;
+ wire _03774_;
+ wire _03775_;
+ wire _03776_;
+ wire _03777_;
+ wire _03778_;
+ wire _03779_;
+ wire _03780_;
+ wire _03781_;
+ wire _03782_;
+ wire _03783_;
+ wire _03784_;
+ wire _03785_;
+ wire _03786_;
+ wire _03787_;
+ wire _03788_;
+ wire _03789_;
+ wire _03790_;
+ wire _03791_;
+ wire _03792_;
+ wire _03793_;
+ wire _03794_;
+ wire _03795_;
+ wire _03796_;
+ wire _03797_;
+ wire _03798_;
+ wire _03799_;
+ wire _03800_;
+ wire _03801_;
+ wire _03802_;
+ wire _03803_;
+ wire _03804_;
+ wire _03805_;
+ wire _03806_;
+ wire _03807_;
+ wire _03808_;
+ wire _03809_;
+ wire _03810_;
+ wire _03811_;
+ wire _03812_;
+ wire _03813_;
+ wire _03814_;
+ wire _03815_;
+ wire _03816_;
+ wire _03817_;
+ wire _03818_;
+ wire _03819_;
+ wire _03820_;
+ wire _03821_;
+ wire _03822_;
+ wire _03823_;
+ wire _03824_;
+ wire _03825_;
+ wire _03826_;
+ wire _03827_;
+ wire _03828_;
+ wire _03829_;
+ wire _03830_;
+ wire _03831_;
+ wire _03832_;
+ wire _03833_;
+ wire _03834_;
+ wire _03835_;
+ wire _03836_;
+ wire _03837_;
+ wire _03838_;
+ wire _03839_;
+ wire _03840_;
+ wire _03841_;
+ wire _03842_;
+ wire _03843_;
+ wire _03844_;
+ wire _03845_;
+ wire _03846_;
+ wire _03847_;
+ wire _03848_;
+ wire _03849_;
+ wire _03850_;
+ wire _03851_;
+ wire _03852_;
+ wire _03853_;
+ wire _03854_;
+ wire _03855_;
+ wire _03856_;
+ wire _03857_;
+ wire _03858_;
+ wire _03859_;
+ wire _03860_;
+ wire _03861_;
+ wire _03862_;
+ wire _03863_;
+ wire _03864_;
+ wire _03865_;
+ wire _03866_;
+ wire _03867_;
+ wire _03868_;
+ wire _03869_;
+ wire _03870_;
+ wire _03871_;
+ wire _03872_;
+ wire _03873_;
+ wire _03874_;
+ wire _03875_;
+ wire _03876_;
+ wire _03877_;
+ wire _03878_;
+ wire _03879_;
+ wire _03880_;
+ wire _03881_;
+ wire _03882_;
+ wire _03883_;
+ wire _03884_;
+ wire _03885_;
+ wire _03886_;
+ wire _03887_;
+ wire _03888_;
+ wire _03889_;
+ wire _03890_;
+ wire _03891_;
+ wire _03892_;
+ wire _03893_;
+ wire _03894_;
+ wire _03895_;
+ wire _03896_;
+ wire _03897_;
+ wire _03898_;
+ wire _03899_;
+ wire _03900_;
+ wire _03901_;
+ wire _03902_;
+ wire _03903_;
+ wire _03904_;
+ wire _03905_;
+ wire _03906_;
+ wire _03907_;
+ wire _03908_;
+ wire _03909_;
+ wire _03910_;
+ wire _03911_;
+ wire _03912_;
+ wire _03913_;
+ wire _03914_;
+ wire _03915_;
+ wire _03916_;
+ wire _03917_;
+ wire _03918_;
+ wire _03919_;
+ wire _03920_;
+ wire _03921_;
+ wire _03922_;
+ wire _03923_;
+ wire _03924_;
+ wire _03925_;
+ wire _03926_;
+ wire _03927_;
+ wire _03928_;
+ wire _03929_;
+ wire _03930_;
+ wire _03931_;
+ wire _03932_;
+ wire _03933_;
+ wire _03934_;
+ wire _03935_;
+ wire _03936_;
+ wire _03937_;
+ wire _03938_;
+ wire _03939_;
+ wire _03940_;
+ wire _03941_;
+ wire _03942_;
+ wire _03943_;
+ wire _03944_;
+ wire _03945_;
+ wire _03946_;
+ wire _03947_;
+ wire _03948_;
+ wire _03949_;
+ wire _03950_;
+ wire _03951_;
+ wire _03952_;
+ wire _03953_;
+ wire _03954_;
+ wire _03955_;
+ wire _03956_;
+ wire _03957_;
+ wire _03958_;
+ wire _03959_;
+ wire _03960_;
+ wire _03961_;
+ wire _03962_;
+ wire _03963_;
+ wire _03964_;
+ wire _03965_;
+ wire _03966_;
+ wire _03967_;
+ wire _03968_;
+ wire _03969_;
+ wire _03970_;
+ wire _03971_;
+ wire _03972_;
+ wire _03973_;
+ wire _03974_;
+ wire _03975_;
+ wire _03976_;
+ wire _03977_;
+ wire _03978_;
+ wire _03979_;
+ wire _03980_;
+ wire _03981_;
+ wire _03982_;
+ wire _03983_;
+ wire _03984_;
+ wire _03985_;
+ wire _03986_;
+ wire _03987_;
+ wire _03988_;
+ wire _03989_;
+ wire _03990_;
+ wire _03991_;
+ wire _03992_;
+ wire _03993_;
+ wire _03994_;
+ wire _03995_;
+ wire _03996_;
+ wire _03997_;
+ wire _03998_;
+ wire _03999_;
+ wire _04000_;
+ wire _04001_;
+ wire _04002_;
+ wire _04003_;
+ wire _04004_;
+ wire _04005_;
+ wire _04006_;
+ wire _04007_;
+ wire _04008_;
+ wire _04009_;
+ wire _04010_;
+ wire _04011_;
+ wire _04012_;
+ wire _04013_;
+ wire _04014_;
+ wire _04015_;
+ wire _04016_;
+ wire _04017_;
+ wire _04018_;
+ wire _04019_;
+ wire _04020_;
+ wire _04021_;
+ wire _04022_;
+ wire _04023_;
+ wire _04024_;
+ wire _04025_;
+ wire _04026_;
+ wire _04027_;
+ wire _04028_;
+ wire _04029_;
+ wire _04030_;
+ wire _04031_;
+ wire _04032_;
+ wire _04033_;
+ wire _04034_;
+ wire _04035_;
+ wire _04036_;
+ wire _04037_;
+ wire _04038_;
+ wire _04039_;
+ wire _04040_;
+ wire _04041_;
+ wire _04042_;
+ wire _04043_;
+ wire _04044_;
+ wire _04045_;
+ wire _04046_;
+ wire _04047_;
+ wire _04048_;
+ wire _04049_;
+ wire _04050_;
+ wire _04051_;
+ wire _04052_;
+ wire _04053_;
+ wire _04054_;
+ wire _04055_;
+ wire _04056_;
+ wire _04057_;
+ wire _04058_;
+ wire _04059_;
+ wire _04060_;
+ wire _04061_;
+ wire _04062_;
+ wire _04063_;
+ wire _04064_;
+ wire _04065_;
+ wire _04066_;
+ wire _04067_;
+ wire _04068_;
+ wire _04069_;
+ wire _04070_;
+ wire _04071_;
+ wire _04072_;
+ wire _04073_;
+ wire _04074_;
+ wire _04075_;
+ wire _04076_;
+ wire _04077_;
+ wire _04078_;
+ wire _04079_;
+ wire _04080_;
+ wire _04081_;
+ wire _04082_;
+ wire _04083_;
+ wire _04084_;
+ wire _04085_;
+ wire _04086_;
+ wire _04087_;
+ wire _04088_;
+ wire _04089_;
+ wire _04090_;
+ wire _04091_;
+ wire _04092_;
+ wire _04093_;
+ wire _04094_;
+ wire _04095_;
+ wire _04096_;
+ wire _04097_;
+ wire _04098_;
+ wire _04099_;
+ wire _04100_;
+ wire _04101_;
+ wire _04102_;
+ wire _04103_;
+ wire _04104_;
+ wire _04105_;
+ wire _04106_;
+ wire _04107_;
+ wire _04108_;
+ wire _04109_;
+ wire _04110_;
+ wire _04111_;
+ wire _04112_;
+ wire _04113_;
+ wire _04114_;
+ wire _04115_;
+ wire _04116_;
+ wire _04117_;
+ wire _04118_;
+ wire _04119_;
+ wire _04120_;
+ wire _04121_;
+ wire _04122_;
+ wire _04123_;
+ wire _04124_;
+ wire _04125_;
+ wire _04126_;
+ wire _04127_;
+ wire _04128_;
+ wire _04129_;
+ wire _04130_;
+ wire _04131_;
+ wire _04132_;
+ wire _04133_;
+ wire _04134_;
+ wire _04135_;
+ wire _04136_;
+ wire _04137_;
+ wire _04138_;
+ wire _04139_;
+ wire _04140_;
+ wire _04141_;
+ wire _04142_;
+ wire _04143_;
+ wire _04144_;
+ wire _04145_;
+ wire _04146_;
+ wire _04147_;
+ wire _04148_;
+ wire _04149_;
+ wire _04150_;
+ wire _04151_;
+ wire _04152_;
+ wire _04153_;
+ wire _04154_;
+ wire _04155_;
+ wire _04156_;
+ wire _04157_;
+ wire _04158_;
+ wire _04159_;
+ wire _04160_;
+ wire _04161_;
+ wire _04162_;
+ wire _04163_;
+ wire _04164_;
+ wire _04165_;
+ wire _04166_;
+ wire _04167_;
+ wire _04168_;
+ wire _04169_;
+ wire _04170_;
+ wire _04171_;
+ wire _04172_;
+ wire _04173_;
+ wire _04174_;
+ wire _04175_;
+ wire _04176_;
+ wire _04177_;
+ wire _04178_;
+ wire _04179_;
+ wire _04180_;
+ wire _04181_;
+ wire _04182_;
+ wire _04183_;
+ wire _04184_;
+ wire _04185_;
+ wire _04186_;
+ wire _04187_;
+ wire _04188_;
+ wire _04189_;
+ wire _04190_;
+ wire _04191_;
+ wire _04192_;
+ wire _04193_;
+ wire _04194_;
+ wire _04195_;
+ wire _04196_;
+ wire _04197_;
+ wire _04198_;
+ wire _04199_;
+ wire _04200_;
+ wire _04201_;
+ wire _04202_;
+ wire _04203_;
+ wire _04204_;
+ wire _04205_;
+ wire _04206_;
+ wire _04207_;
+ wire _04208_;
+ wire _04209_;
+ wire _04210_;
+ wire _04211_;
+ wire _04212_;
+ wire _04213_;
+ wire _04214_;
+ wire _04215_;
+ wire _04216_;
+ wire _04217_;
+ wire _04218_;
+ wire _04219_;
+ wire _04220_;
+ wire _04221_;
+ wire _04222_;
+ wire _04223_;
+ wire _04224_;
+ wire _04225_;
+ wire _04226_;
+ wire _04227_;
+ wire _04228_;
+ wire _04229_;
+ wire _04230_;
+ wire _04231_;
+ wire _04232_;
+ wire _04233_;
+ wire _04234_;
+ wire _04235_;
+ wire _04236_;
+ wire _04237_;
+ wire _04238_;
+ wire _04239_;
+ wire _04240_;
+ wire _04241_;
+ wire _04242_;
+ wire _04243_;
+ wire _04244_;
+ wire _04245_;
+ wire _04246_;
+ wire _04247_;
+ wire _04248_;
+ wire _04249_;
+ wire _04250_;
+ wire _04251_;
+ wire _04252_;
+ wire _04253_;
+ wire _04254_;
+ wire _04255_;
+ wire _04256_;
+ wire _04257_;
+ wire _04258_;
+ wire _04259_;
+ wire _04260_;
+ wire _04261_;
+ wire _04262_;
+ wire _04263_;
+ wire _04264_;
+ wire _04265_;
+ wire _04266_;
+ wire _04267_;
+ wire _04268_;
+ wire _04269_;
+ wire _04270_;
+ wire _04271_;
+ wire _04272_;
+ wire _04273_;
+ wire _04274_;
+ wire _04275_;
+ wire _04276_;
+ wire _04277_;
+ wire _04278_;
+ wire _04279_;
+ wire _04280_;
+ wire _04281_;
+ wire _04282_;
+ wire _04283_;
+ wire _04284_;
+ wire _04285_;
+ wire _04286_;
+ wire _04287_;
+ wire _04288_;
+ wire _04289_;
+ wire _04290_;
+ wire _04291_;
+ wire _04292_;
+ wire _04293_;
+ wire _04294_;
+ wire _04295_;
+ wire _04296_;
+ wire _04297_;
+ wire _04298_;
+ wire _04299_;
+ wire _04300_;
+ wire _04301_;
+ wire _04302_;
+ wire _04303_;
+ wire _04304_;
+ wire _04305_;
+ wire _04306_;
+ wire _04307_;
+ wire _04308_;
+ wire _04309_;
+ wire _04310_;
+ wire _04311_;
+ wire _04312_;
+ wire _04313_;
+ wire _04314_;
+ wire _04315_;
+ wire _04316_;
+ wire _04317_;
+ wire _04318_;
+ wire _04319_;
+ wire _04320_;
+ wire _04321_;
+ wire _04322_;
+ wire _04323_;
+ wire _04324_;
+ wire _04325_;
+ wire _04326_;
+ wire _04327_;
+ wire _04328_;
+ wire _04329_;
+ wire _04330_;
+ wire _04331_;
+ wire _04332_;
+ wire _04333_;
+ wire _04334_;
+ wire _04335_;
+ wire _04336_;
+ wire _04337_;
+ wire _04338_;
+ wire _04339_;
+ wire _04340_;
+ wire _04341_;
+ wire _04342_;
+ wire _04343_;
+ wire _04344_;
+ wire _04345_;
+ wire _04346_;
+ wire _04347_;
+ wire _04348_;
+ wire _04349_;
+ wire _04350_;
+ wire _04351_;
+ wire _04352_;
+ wire _04353_;
+ wire _04354_;
+ wire _04355_;
+ wire _04356_;
+ wire _04357_;
+ wire _04358_;
+ wire _04359_;
+ wire _04360_;
+ wire _04361_;
+ wire _04362_;
+ wire _04363_;
+ wire _04364_;
+ wire _04365_;
+ wire _04366_;
+ wire _04367_;
+ wire _04368_;
+ wire _04369_;
+ wire _04370_;
+ wire _04371_;
+ wire _04372_;
+ wire _04373_;
+ wire _04374_;
+ wire _04375_;
+ wire _04376_;
+ wire _04377_;
+ wire _04378_;
+ wire _04379_;
+ wire _04380_;
+ wire _04381_;
+ wire _04382_;
+ wire _04383_;
+ wire _04384_;
+ wire _04385_;
+ wire _04386_;
+ wire _04387_;
+ wire _04388_;
+ wire _04389_;
+ wire _04390_;
+ wire _04391_;
+ wire _04392_;
+ wire _04393_;
+ wire _04394_;
+ wire _04395_;
+ wire _04396_;
+ wire _04397_;
+ wire _04398_;
+ wire _04399_;
+ wire _04400_;
+ wire _04401_;
+ wire _04402_;
+ wire _04403_;
+ wire _04404_;
+ wire _04405_;
+ wire _04406_;
+ wire _04407_;
+ wire _04408_;
+ wire _04409_;
+ wire _04410_;
+ wire _04411_;
+ wire _04412_;
+ wire _04413_;
+ wire _04414_;
+ wire _04415_;
+ wire _04416_;
+ wire _04417_;
+ wire _04418_;
+ wire _04419_;
+ wire _04420_;
+ wire _04421_;
+ wire _04422_;
+ wire _04423_;
+ wire _04424_;
+ wire _04425_;
+ wire _04426_;
+ wire _04427_;
+ wire _04428_;
+ wire _04429_;
+ wire _04430_;
+ wire _04431_;
+ wire _04432_;
+ wire _04433_;
+ wire _04434_;
+ wire _04435_;
+ wire _04436_;
+ wire _04437_;
+ wire _04438_;
+ wire _04439_;
+ wire _04440_;
+ wire _04441_;
+ wire _04442_;
+ wire _04443_;
+ wire _04444_;
+ wire _04445_;
+ wire _04446_;
+ wire _04447_;
+ wire _04448_;
+ wire _04449_;
+ wire _04450_;
+ wire _04451_;
+ wire _04452_;
+ wire _04453_;
+ wire _04454_;
+ wire _04455_;
+ wire _04456_;
+ wire _04457_;
+ wire _04458_;
+ wire _04459_;
+ wire _04460_;
+ wire _04461_;
+ wire _04462_;
+ wire _04463_;
+ wire _04464_;
+ wire _04465_;
+ wire _04466_;
+ wire _04467_;
+ wire _04468_;
+ wire _04469_;
+ wire _04470_;
+ wire _04471_;
+ wire _04472_;
+ wire _04473_;
+ wire _04474_;
+ wire _04475_;
+ wire _04476_;
+ wire _04477_;
+ wire _04478_;
+ wire _04479_;
+ wire _04480_;
+ wire _04481_;
+ wire _04482_;
+ wire _04483_;
+ wire _04484_;
+ wire _04485_;
+ wire _04486_;
+ wire _04487_;
+ wire _04488_;
+ wire _04489_;
+ wire _04490_;
+ wire _04491_;
+ wire _04492_;
+ wire _04493_;
+ wire _04494_;
+ wire _04495_;
+ wire _04496_;
+ wire _04497_;
+ wire _04498_;
+ wire _04499_;
+ wire _04500_;
+ wire _04501_;
+ wire _04502_;
+ wire _04503_;
+ wire _04504_;
+ wire _04505_;
+ wire _04506_;
+ wire _04507_;
+ wire _04508_;
+ wire _04509_;
+ wire _04510_;
+ wire _04511_;
+ wire _04512_;
+ wire _04513_;
+ wire _04514_;
+ wire _04515_;
+ wire _04516_;
+ wire _04517_;
+ wire _04518_;
+ wire _04519_;
+ wire _04520_;
+ wire _04521_;
+ wire _04522_;
+ wire _04523_;
+ wire _04524_;
+ wire _04525_;
+ wire _04526_;
+ wire _04527_;
+ wire _04528_;
+ wire _04529_;
+ wire _04530_;
+ wire _04531_;
+ wire _04532_;
+ wire _04533_;
+ wire _04534_;
+ wire _04535_;
+ wire _04536_;
+ wire _04537_;
+ wire _04538_;
+ wire _04539_;
+ wire _04540_;
+ wire _04541_;
+ wire _04542_;
+ wire _04543_;
+ wire _04544_;
+ wire _04545_;
+ wire _04546_;
+ wire _04547_;
+ wire _04548_;
+ wire _04549_;
+ wire _04550_;
+ wire _04551_;
+ wire _04552_;
+ wire _04553_;
+ wire _04554_;
+ wire _04555_;
+ wire _04556_;
+ wire _04557_;
+ wire _04558_;
+ wire _04559_;
+ wire _04560_;
+ wire _04561_;
+ wire _04562_;
+ wire _04563_;
+ wire _04564_;
+ wire _04565_;
+ wire _04566_;
+ wire _04567_;
+ wire _04568_;
+ wire _04569_;
+ wire _04570_;
+ wire _04571_;
+ wire _04572_;
+ wire _04573_;
+ wire _04574_;
+ wire _04575_;
+ wire _04576_;
+ wire _04577_;
+ wire _04578_;
+ wire _04579_;
+ wire _04580_;
+ wire _04581_;
+ wire _04582_;
+ wire _04583_;
+ wire _04584_;
+ wire _04585_;
+ wire _04586_;
+ wire _04587_;
+ wire _04588_;
+ wire _04589_;
+ wire _04590_;
+ wire _04591_;
+ wire _04592_;
+ wire _04593_;
+ wire _04594_;
+ wire _04595_;
+ wire _04596_;
+ wire _04597_;
+ wire _04598_;
+ wire _04599_;
+ wire _04600_;
+ wire _04601_;
+ wire _04602_;
+ wire _04603_;
+ wire _04604_;
+ wire _04605_;
+ wire _04606_;
+ wire _04607_;
+ wire _04608_;
+ wire _04609_;
+ wire _04610_;
+ wire _04611_;
+ wire _04612_;
+ wire _04613_;
+ wire _04614_;
+ wire _04615_;
+ wire _04616_;
+ wire _04617_;
+ wire _04618_;
+ wire _04619_;
+ wire _04620_;
+ wire _04621_;
+ wire _04622_;
+ wire _04623_;
+ wire _04624_;
+ wire _04625_;
+ wire _04626_;
+ wire _04627_;
+ wire _04628_;
+ wire _04629_;
+ wire _04630_;
+ wire _04631_;
+ wire _04632_;
+ wire _04633_;
+ wire _04634_;
+ wire _04635_;
+ wire _04636_;
+ wire _04637_;
+ wire _04638_;
+ wire _04639_;
+ wire _04640_;
+ wire _04641_;
+ wire _04642_;
+ wire _04643_;
+ wire _04644_;
+ wire _04645_;
+ wire _04646_;
+ wire _04647_;
+ wire _04648_;
+ wire _04649_;
+ wire _04650_;
+ wire _04651_;
+ wire _04652_;
+ wire _04653_;
+ wire _04654_;
+ wire _04655_;
+ wire _04656_;
+ wire _04657_;
+ wire _04658_;
+ wire _04659_;
+ wire _04660_;
+ wire _04661_;
+ wire _04662_;
+ wire _04663_;
+ wire _04664_;
+ wire _04665_;
+ wire _04666_;
+ wire _04667_;
+ wire _04668_;
+ wire _04669_;
+ wire _04670_;
+ wire _04671_;
+ wire _04672_;
+ wire _04673_;
+ wire _04674_;
+ wire _04675_;
+ wire _04676_;
+ wire _04677_;
+ wire _04678_;
+ wire _04679_;
+ wire _04680_;
+ wire _04681_;
+ wire _04682_;
+ wire _04683_;
+ wire _04684_;
+ wire _04685_;
+ wire _04686_;
+ wire _04687_;
+ wire _04688_;
+ wire _04689_;
+ wire _04690_;
+ wire _04691_;
+ wire _04692_;
+ wire _04693_;
+ wire _04694_;
+ wire _04695_;
+ wire _04696_;
+ wire _04697_;
+ wire _04698_;
+ wire _04699_;
+ wire _04700_;
+ wire _04701_;
+ wire _04702_;
+ wire _04703_;
+ wire _04704_;
+ wire _04705_;
+ wire _04706_;
+ wire _04707_;
+ wire _04708_;
+ wire _04709_;
+ wire _04710_;
+ wire _04711_;
+ wire _04712_;
+ wire _04713_;
+ wire _04714_;
+ wire _04715_;
+ wire _04716_;
+ wire _04717_;
+ wire _04718_;
+ wire _04719_;
+ wire _04720_;
+ wire _04721_;
+ wire _04722_;
+ wire _04723_;
+ wire _04724_;
+ wire _04725_;
+ wire _04726_;
+ wire _04727_;
+ wire _04728_;
+ wire _04729_;
+ wire _04730_;
+ wire _04731_;
+ wire _04732_;
+ wire _04733_;
+ wire _04734_;
+ wire _04735_;
+ wire _04736_;
+ wire _04737_;
+ wire _04738_;
+ wire _04739_;
+ wire _04740_;
+ wire _04741_;
+ wire _04742_;
+ wire _04743_;
+ wire _04744_;
+ wire _04745_;
+ wire _04746_;
+ wire _04747_;
+ wire _04748_;
+ wire _04749_;
+ wire _04750_;
+ wire _04751_;
+ wire _04752_;
+ wire _04753_;
+ wire _04754_;
+ wire _04755_;
+ wire _04756_;
+ wire _04757_;
+ wire _04758_;
+ wire _04759_;
+ wire _04760_;
+ wire _04761_;
+ wire _04762_;
+ wire _04763_;
+ wire _04764_;
+ wire _04765_;
+ wire _04766_;
+ wire _04767_;
+ wire _04768_;
+ wire _04769_;
+ wire _04770_;
+ wire _04771_;
+ wire _04772_;
+ wire _04773_;
+ wire _04774_;
+ wire _04775_;
+ wire _04776_;
+ wire _04777_;
+ wire _04778_;
+ wire _04779_;
+ wire _04780_;
+ wire _04781_;
+ wire _04782_;
+ wire _04783_;
+ wire _04784_;
+ wire _04785_;
+ wire _04786_;
+ wire _04787_;
+ wire _04788_;
+ wire _04789_;
+ wire _04790_;
+ wire _04791_;
+ wire _04792_;
+ wire _04793_;
+ wire _04794_;
+ wire _04795_;
+ wire _04796_;
+ wire _04797_;
+ wire _04798_;
+ wire _04799_;
+ wire _04800_;
+ wire _04801_;
+ wire _04802_;
+ wire _04803_;
+ wire _04804_;
+ wire _04805_;
+ wire _04806_;
+ wire _04807_;
+ wire _04808_;
+ wire _04809_;
+ wire _04810_;
+ wire _04811_;
+ wire _04812_;
+ wire _04813_;
+ wire _04814_;
+ wire _04815_;
+ wire _04816_;
+ wire _04817_;
+ wire _04818_;
+ wire _04819_;
+ wire _04820_;
+ wire _04821_;
+ wire _04822_;
+ wire _04823_;
+ wire _04824_;
+ wire _04825_;
+ wire _04826_;
+ wire _04827_;
+ wire _04828_;
+ wire _04829_;
+ wire _04830_;
+ wire _04831_;
+ wire _04832_;
+ wire _04833_;
+ wire _04834_;
+ wire _04835_;
+ wire _04836_;
+ wire _04837_;
+ wire _04838_;
+ wire _04839_;
+ wire _04840_;
+ wire _04841_;
+ wire _04842_;
+ wire _04843_;
+ wire _04844_;
+ wire _04845_;
+ wire _04846_;
+ wire _04847_;
+ wire _04848_;
+ wire _04849_;
+ wire _04850_;
+ wire _04851_;
+ wire _04852_;
+ wire _04853_;
+ wire _04854_;
+ wire _04855_;
+ wire _04856_;
+ wire _04857_;
+ wire _04858_;
+ wire _04859_;
+ wire _04860_;
+ wire _04861_;
+ wire _04862_;
+ wire _04863_;
+ wire _04864_;
+ wire _04865_;
+ wire _04866_;
+ wire _04867_;
+ wire _04868_;
+ wire _04869_;
+ wire _04870_;
+ wire _04871_;
+ wire _04872_;
+ wire _04873_;
+ wire _04874_;
+ wire _04875_;
+ wire _04876_;
+ wire _04877_;
+ wire _04878_;
+ wire _04879_;
+ wire _04880_;
+ wire _04881_;
+ wire _04882_;
+ wire _04883_;
+ wire _04884_;
+ wire _04885_;
+ wire _04886_;
+ wire _04887_;
+ wire _04888_;
+ wire _04889_;
+ wire _04890_;
+ wire _04891_;
+ wire _04892_;
+ wire _04893_;
+ wire _04894_;
+ wire _04895_;
+ wire _04896_;
+ wire _04897_;
+ wire _04898_;
+ wire _04899_;
+ wire _04900_;
+ wire _04901_;
+ wire _04902_;
+ wire _04903_;
+ wire _04904_;
+ wire _04905_;
+ wire _04906_;
+ wire _04907_;
+ wire _04908_;
+ wire _04909_;
+ wire _04910_;
+ wire _04911_;
+ wire _04912_;
+ wire _04913_;
+ wire _04914_;
+ wire _04915_;
+ wire _04916_;
+ wire _04917_;
+ wire _04918_;
+ wire _04919_;
+ wire _04920_;
+ wire _04921_;
+ wire _04922_;
+ wire _04923_;
+ wire _04924_;
+ wire _04925_;
+ wire _04926_;
+ wire _04927_;
+ wire _04928_;
+ wire _04929_;
+ wire _04930_;
+ wire _04931_;
+ wire _04932_;
+ wire _04933_;
+ wire _04934_;
+ wire _04935_;
+ wire _04936_;
+ wire _04937_;
+ wire _04938_;
+ wire _04939_;
+ wire _04940_;
+ wire _04941_;
+ wire _04942_;
+ wire _04943_;
+ wire _04944_;
+ wire _04945_;
+ wire _04946_;
+ wire _04947_;
+ wire _04948_;
+ wire _04949_;
+ wire _04950_;
+ wire _04951_;
+ wire _04952_;
+ wire _04953_;
+ wire _04954_;
+ wire _04955_;
+ wire _04956_;
+ wire _04957_;
+ wire _04958_;
+ wire _04959_;
+ wire _04960_;
+ wire _04961_;
+ wire _04962_;
+ wire _04963_;
+ wire _04964_;
+ wire _04965_;
+ wire _04966_;
+ wire _04967_;
+ wire _04968_;
+ wire _04969_;
+ wire _04970_;
+ wire _04971_;
+ wire _04972_;
+ wire _04973_;
+ wire _04974_;
+ wire _04975_;
+ wire _04976_;
+ wire _04977_;
+ wire _04978_;
+ wire _04979_;
+ wire _04980_;
+ wire _04981_;
+ wire _04982_;
+ wire _04983_;
+ wire _04984_;
+ wire _04985_;
+ wire _04986_;
+ wire _04987_;
+ wire _04988_;
+ wire _04989_;
+ wire _04990_;
+ wire _04991_;
+ wire _04992_;
+ wire _04993_;
+ wire _04994_;
+ wire _04995_;
+ wire _04996_;
+ wire _04997_;
+ wire _04998_;
+ wire _04999_;
+ wire _05000_;
+ wire _05001_;
+ wire _05002_;
+ wire _05003_;
+ wire _05004_;
+ wire _05005_;
+ wire _05006_;
+ wire _05007_;
+ wire _05008_;
+ wire _05009_;
+ wire _05010_;
+ wire _05011_;
+ wire _05012_;
+ wire _05013_;
+ wire _05014_;
+ wire _05015_;
+ wire _05016_;
+ wire _05017_;
+ wire _05018_;
+ wire _05019_;
+ wire _05020_;
+ wire _05021_;
+ wire _05022_;
+ wire _05023_;
+ wire _05024_;
+ wire _05025_;
+ wire _05026_;
+ wire _05027_;
+ wire _05028_;
+ wire _05029_;
+ wire _05030_;
+ wire _05031_;
+ wire _05032_;
+ wire _05033_;
+ wire _05034_;
+ wire _05035_;
+ wire _05036_;
+ wire _05037_;
+ wire _05038_;
+ wire _05039_;
+ wire _05040_;
+ wire _05041_;
+ wire _05042_;
+ wire _05043_;
+ wire _05044_;
+ wire _05045_;
+ wire _05046_;
+ wire _05047_;
+ wire _05048_;
+ wire _05049_;
+ wire _05050_;
+ wire _05051_;
+ wire _05052_;
+ wire _05053_;
+ wire _05054_;
+ wire _05055_;
+ wire _05056_;
+ wire _05057_;
+ wire _05058_;
+ wire _05059_;
+ wire _05060_;
+ wire _05061_;
+ wire _05062_;
+ wire _05063_;
+ wire _05064_;
+ wire _05065_;
+ wire _05066_;
+ wire _05067_;
+ wire _05068_;
+ wire _05069_;
+ wire _05070_;
+ wire _05071_;
+ wire _05072_;
+ wire _05073_;
+ wire _05074_;
+ wire _05075_;
+ wire _05076_;
+ wire _05077_;
+ wire _05078_;
+ wire _05079_;
+ wire _05080_;
+ wire _05081_;
+ wire _05082_;
+ wire _05083_;
+ wire _05084_;
+ wire _05085_;
+ wire _05086_;
+ wire _05087_;
+ wire _05088_;
+ wire _05089_;
+ wire _05090_;
+ wire _05091_;
+ wire _05092_;
+ wire _05093_;
+ wire _05094_;
+ wire _05095_;
+ wire _05096_;
+ wire _05097_;
+ wire _05098_;
+ wire _05099_;
+ wire _05100_;
+ wire _05101_;
+ wire _05102_;
+ wire _05103_;
+ wire _05104_;
+ wire _05105_;
+ wire _05106_;
+ wire _05107_;
+ wire _05108_;
+ wire _05109_;
+ wire _05110_;
+ wire _05111_;
+ wire _05112_;
+ wire _05113_;
+ wire _05114_;
+ wire _05115_;
+ wire _05116_;
+ wire _05117_;
+ wire _05118_;
+ wire _05119_;
+ wire _05120_;
+ wire _05121_;
+ wire _05122_;
+ wire _05123_;
+ wire _05124_;
+ wire _05125_;
+ wire _05126_;
+ wire _05127_;
+ wire _05128_;
+ wire _05129_;
+ wire _05130_;
+ wire _05131_;
+ wire _05132_;
+ wire _05133_;
+ wire _05134_;
+ wire _05135_;
+ wire _05136_;
+ wire _05137_;
+ wire _05138_;
+ wire _05139_;
+ wire _05140_;
+ wire _05141_;
+ wire _05142_;
+ wire _05143_;
+ wire _05144_;
+ wire _05145_;
+ wire _05146_;
+ wire _05147_;
+ wire _05148_;
+ wire _05149_;
+ wire _05150_;
+ wire _05151_;
+ wire _05152_;
+ wire _05153_;
+ wire _05154_;
+ wire _05155_;
+ wire _05156_;
+ wire _05157_;
+ wire _05158_;
+ wire _05159_;
+ wire _05160_;
+ wire _05161_;
+ wire _05162_;
+ wire _05163_;
+ wire _05164_;
+ wire _05165_;
+ wire _05166_;
+ wire _05167_;
+ wire _05168_;
+ wire _05169_;
+ wire _05170_;
+ wire _05171_;
+ wire _05172_;
+ wire _05173_;
+ wire _05174_;
+ wire _05175_;
+ wire _05176_;
+ wire _05177_;
+ wire _05178_;
+ wire _05179_;
+ wire _05180_;
+ wire _05181_;
+ wire _05182_;
+ wire _05183_;
+ wire _05184_;
+ wire _05185_;
+ wire _05186_;
+ wire _05187_;
+ wire _05188_;
+ wire _05189_;
+ wire _05190_;
+ wire _05191_;
+ wire _05192_;
+ wire _05193_;
+ wire _05194_;
+ wire _05195_;
+ wire _05196_;
+ wire _05197_;
+ wire _05198_;
+ wire _05199_;
+ wire _05200_;
+ wire _05201_;
+ wire _05202_;
+ wire _05203_;
+ wire _05204_;
+ wire _05205_;
+ wire _05206_;
+ wire _05207_;
+ wire _05208_;
+ wire _05209_;
+ wire _05210_;
+ wire _05211_;
+ wire _05212_;
+ wire _05213_;
+ wire _05214_;
+ wire _05215_;
+ wire _05216_;
+ wire _05217_;
+ wire _05218_;
+ wire _05219_;
+ wire _05220_;
+ wire _05221_;
+ wire _05222_;
+ wire _05223_;
+ wire _05224_;
+ wire _05225_;
+ wire _05226_;
+ wire _05227_;
+ wire _05228_;
+ wire _05229_;
+ wire _05230_;
+ wire _05231_;
+ wire _05232_;
+ wire _05233_;
+ wire _05234_;
+ wire _05235_;
+ wire _05236_;
+ wire _05237_;
+ wire _05238_;
+ wire _05239_;
+ wire _05240_;
+ wire _05241_;
+ wire _05242_;
+ wire _05243_;
+ wire _05244_;
+ wire _05245_;
+ wire _05246_;
+ wire _05247_;
+ wire _05248_;
+ wire _05249_;
+ wire _05250_;
+ wire _05251_;
+ wire _05252_;
+ wire _05253_;
+ wire _05254_;
+ wire _05255_;
+ wire _05256_;
+ wire _05257_;
+ wire _05258_;
+ wire _05259_;
+ wire _05260_;
+ wire _05261_;
+ wire _05262_;
+ wire _05263_;
+ wire _05264_;
+ wire _05265_;
+ wire _05266_;
+ wire _05267_;
+ wire _05268_;
+ wire _05269_;
+ wire _05270_;
+ wire _05271_;
+ wire _05272_;
+ wire _05273_;
+ wire _05274_;
+ wire _05275_;
+ wire _05276_;
+ wire _05277_;
+ wire _05278_;
+ wire _05279_;
+ wire _05280_;
+ wire _05281_;
+ wire _05282_;
+ wire _05283_;
+ wire _05284_;
+ wire _05285_;
+ wire _05286_;
+ wire _05287_;
+ wire _05288_;
+ wire _05289_;
+ wire _05290_;
+ wire _05291_;
+ wire _05292_;
+ wire _05293_;
+ wire _05294_;
+ wire _05295_;
+ wire _05296_;
+ wire _05297_;
+ wire _05298_;
+ wire _05299_;
+ wire _05300_;
+ wire _05301_;
+ wire _05302_;
+ wire _05303_;
+ wire _05304_;
+ wire _05305_;
+ wire _05306_;
+ wire _05307_;
+ wire _05308_;
+ wire _05309_;
+ wire _05310_;
+ wire _05311_;
+ wire _05312_;
+ wire _05313_;
+ wire _05314_;
+ wire _05315_;
+ wire _05316_;
+ wire _05317_;
+ wire _05318_;
+ wire _05319_;
+ wire _05320_;
+ wire _05321_;
+ wire _05322_;
+ wire _05323_;
+ wire _05324_;
+ wire _05325_;
+ wire _05326_;
+ wire _05327_;
+ wire _05328_;
+ wire _05329_;
+ wire _05330_;
+ wire _05331_;
+ wire _05332_;
+ wire _05333_;
+ wire _05334_;
+ wire _05335_;
+ wire _05336_;
+ wire _05337_;
+ wire _05338_;
+ wire _05339_;
+ wire _05340_;
+ wire _05341_;
+ wire _05342_;
+ wire _05343_;
+ wire _05344_;
+ wire _05345_;
+ wire _05346_;
+ wire _05347_;
+ wire _05348_;
+ wire _05349_;
+ wire _05350_;
+ wire _05351_;
+ wire _05352_;
+ wire _05353_;
+ wire _05354_;
+ wire _05355_;
+ wire _05356_;
+ wire _05357_;
+ wire _05358_;
+ wire _05359_;
+ wire _05360_;
+ wire _05361_;
+ wire _05362_;
+ wire _05363_;
+ wire _05364_;
+ wire _05365_;
+ wire _05366_;
+ wire _05367_;
+ wire _05368_;
+ wire _05369_;
+ wire _05370_;
+ wire _05371_;
+ wire _05372_;
+ wire _05373_;
+ wire _05374_;
+ wire _05375_;
+ wire _05376_;
+ wire _05377_;
+ wire _05378_;
+ wire _05379_;
+ wire _05380_;
+ wire _05381_;
+ wire _05382_;
+ wire _05383_;
+ wire _05384_;
+ wire _05385_;
+ wire _05386_;
+ wire _05387_;
+ wire _05388_;
+ wire _05389_;
+ wire _05390_;
+ wire _05391_;
+ wire _05392_;
+ wire _05393_;
+ wire _05394_;
+ wire _05395_;
+ wire _05396_;
+ wire _05397_;
+ wire _05398_;
+ wire _05399_;
+ wire _05400_;
+ wire _05401_;
+ wire _05402_;
+ wire _05403_;
+ wire _05404_;
+ wire _05405_;
+ wire _05406_;
+ wire _05407_;
+ wire _05408_;
+ wire _05409_;
+ wire _05410_;
+ wire _05411_;
+ wire _05412_;
+ wire _05413_;
+ wire _05414_;
+ wire _05415_;
+ wire _05416_;
+ wire _05417_;
+ wire _05418_;
+ wire _05419_;
+ wire _05420_;
+ wire _05421_;
+ wire _05422_;
+ wire _05423_;
+ wire _05424_;
+ wire _05425_;
+ wire _05426_;
+ wire _05427_;
+ wire _05428_;
+ wire _05429_;
+ wire _05430_;
+ wire _05431_;
+ wire _05432_;
+ wire _05433_;
+ wire _05434_;
+ wire _05435_;
+ wire _05436_;
+ wire _05437_;
+ wire _05438_;
+ wire _05439_;
+ wire _05440_;
+ wire _05441_;
+ wire _05442_;
+ wire _05443_;
+ wire _05444_;
+ wire _05445_;
+ wire _05446_;
+ wire _05447_;
+ wire _05448_;
+ wire _05449_;
+ wire _05450_;
+ wire _05451_;
+ wire _05452_;
+ wire _05453_;
+ wire _05454_;
+ wire _05455_;
+ wire _05456_;
+ wire _05457_;
+ wire _05458_;
+ wire _05459_;
+ wire _05460_;
+ wire _05461_;
+ wire _05462_;
+ wire _05463_;
+ wire _05464_;
+ wire _05465_;
+ wire _05466_;
+ wire _05467_;
+ wire _05468_;
+ wire _05469_;
+ wire _05470_;
+ wire _05471_;
+ wire _05472_;
+ wire _05473_;
+ wire _05474_;
+ wire _05475_;
+ wire _05476_;
+ wire _05477_;
+ wire _05478_;
+ wire _05479_;
+ wire _05480_;
+ wire _05481_;
+ wire _05482_;
+ wire _05483_;
+ wire _05484_;
+ wire _05485_;
+ wire _05486_;
+ wire _05487_;
+ wire _05488_;
+ wire _05489_;
+ wire _05490_;
+ wire _05491_;
+ wire _05492_;
+ wire _05493_;
+ wire _05494_;
+ wire _05495_;
+ wire _05496_;
+ wire _05497_;
+ wire _05498_;
+ wire _05499_;
+ wire _05500_;
+ wire _05501_;
+ wire _05502_;
+ wire _05503_;
+ wire _05504_;
+ wire _05505_;
+ wire _05506_;
+ wire _05507_;
+ wire _05508_;
+ wire _05509_;
+ wire _05510_;
+ wire _05511_;
+ wire _05512_;
+ wire _05513_;
+ wire _05514_;
+ wire _05515_;
+ wire _05516_;
+ wire _05517_;
+ wire _05518_;
+ wire _05519_;
+ wire _05520_;
+ wire _05521_;
+ wire _05522_;
+ wire _05523_;
+ wire _05524_;
+ wire _05525_;
+ wire _05526_;
+ wire _05527_;
+ wire _05528_;
+ wire _05529_;
+ wire _05530_;
+ wire _05531_;
+ wire _05532_;
+ wire _05533_;
+ wire _05534_;
+ wire _05535_;
+ wire _05536_;
+ wire _05537_;
+ wire _05538_;
+ wire _05539_;
+ wire _05540_;
+ wire _05541_;
+ wire _05542_;
+ wire _05543_;
+ wire _05544_;
+ wire _05545_;
+ wire _05546_;
+ wire _05547_;
+ wire _05548_;
+ wire _05549_;
+ wire _05550_;
+ wire _05551_;
+ wire _05552_;
+ wire _05553_;
+ wire _05554_;
+ wire _05555_;
+ wire _05556_;
+ wire _05557_;
+ wire _05558_;
+ wire _05559_;
+ wire _05560_;
+ wire _05561_;
+ wire _05562_;
+ wire _05563_;
+ wire _05564_;
+ wire _05565_;
+ wire _05566_;
+ wire _05567_;
+ wire _05568_;
+ wire _05569_;
+ wire _05570_;
+ wire _05571_;
+ wire _05572_;
+ wire _05573_;
+ wire _05574_;
+ wire _05575_;
+ wire _05576_;
+ wire _05577_;
+ wire _05578_;
+ wire _05579_;
+ wire _05580_;
+ wire _05581_;
+ wire _05582_;
+ wire _05583_;
+ wire _05584_;
+ wire _05585_;
+ wire _05586_;
+ wire _05587_;
+ wire _05588_;
+ wire _05589_;
+ wire _05590_;
+ wire _05591_;
+ wire _05592_;
+ wire _05593_;
+ wire _05594_;
+ wire _05595_;
+ wire _05596_;
+ wire _05597_;
+ wire _05598_;
+ wire _05599_;
+ wire _05600_;
+ wire _05601_;
+ wire _05602_;
+ wire _05603_;
+ wire _05604_;
+ wire _05605_;
+ wire _05606_;
+ wire _05607_;
+ wire _05608_;
+ wire _05609_;
+ wire _05610_;
+ wire _05611_;
+ wire _05612_;
+ wire _05613_;
+ wire _05614_;
+ wire _05615_;
+ wire _05616_;
+ wire _05617_;
+ wire _05618_;
+ wire _05619_;
+ wire _05620_;
+ wire _05621_;
+ wire _05622_;
+ wire _05623_;
+ wire _05624_;
+ wire _05625_;
+ wire _05626_;
+ wire _05627_;
+ wire _05628_;
+ wire _05629_;
+ wire _05630_;
+ wire _05631_;
+ wire _05632_;
+ wire _05633_;
+ wire _05634_;
+ wire _05635_;
+ wire _05636_;
+ wire _05637_;
+ wire _05638_;
+ wire _05639_;
+ wire _05640_;
+ wire _05641_;
+ wire _05642_;
+ wire _05643_;
+ wire _05644_;
+ wire _05645_;
+ wire _05646_;
+ wire _05647_;
+ wire _05648_;
+ wire _05649_;
+ wire _05650_;
+ wire _05651_;
+ wire _05652_;
+ wire _05653_;
+ wire _05654_;
+ wire _05655_;
+ wire _05656_;
+ wire _05657_;
+ wire _05658_;
+ wire _05659_;
+ wire _05660_;
+ wire _05661_;
+ wire _05662_;
+ wire _05663_;
+ wire _05664_;
+ wire _05665_;
+ wire _05666_;
+ wire _05667_;
+ wire _05668_;
+ wire _05669_;
+ wire _05670_;
+ wire _05671_;
+ wire _05672_;
+ wire _05673_;
+ wire _05674_;
+ wire _05675_;
+ wire _05676_;
+ wire _05677_;
+ wire _05678_;
+ wire _05679_;
+ wire _05680_;
+ wire _05681_;
+ wire _05682_;
+ wire _05683_;
+ wire _05684_;
+ wire _05685_;
+ wire _05686_;
+ wire _05687_;
+ wire _05688_;
+ wire _05689_;
+ wire _05690_;
+ wire _05691_;
+ wire _05692_;
+ wire _05693_;
+ wire _05694_;
+ wire _05695_;
+ wire _05696_;
+ wire _05697_;
+ wire _05698_;
+ wire _05699_;
+ wire _05700_;
+ wire _05701_;
+ wire _05702_;
+ wire _05703_;
+ wire _05704_;
+ wire _05705_;
+ wire _05706_;
+ wire _05707_;
+ wire _05708_;
+ wire _05709_;
+ wire _05710_;
+ wire _05711_;
+ wire _05712_;
+ wire _05713_;
+ wire _05714_;
+ wire _05715_;
+ wire _05716_;
+ wire _05717_;
+ wire _05718_;
+ wire _05719_;
+ wire _05720_;
+ wire _05721_;
+ wire _05722_;
+ wire _05723_;
+ wire _05724_;
+ wire _05725_;
+ wire _05726_;
+ wire _05727_;
+ wire _05728_;
+ wire _05729_;
+ wire _05730_;
+ wire _05731_;
+ wire _05732_;
+ wire _05733_;
+ wire _05734_;
+ wire _05735_;
+ wire _05736_;
+ wire _05737_;
+ wire _05738_;
+ wire _05739_;
+ wire _05740_;
+ wire _05741_;
+ wire _05742_;
+ wire _05743_;
+ wire _05744_;
+ wire _05745_;
+ wire _05746_;
+ wire _05747_;
+ wire _05748_;
+ wire _05749_;
+ wire _05750_;
+ wire _05751_;
+ wire _05752_;
+ wire _05753_;
+ wire _05754_;
+ wire _05755_;
+ wire _05756_;
+ wire _05757_;
+ wire _05758_;
+ wire _05759_;
+ wire _05760_;
+ wire _05761_;
+ wire _05762_;
+ wire _05763_;
+ wire _05764_;
+ wire _05765_;
+ wire _05766_;
+ wire _05767_;
+ wire _05768_;
+ wire _05769_;
+ wire _05770_;
+ wire _05771_;
+ wire _05772_;
+ wire _05773_;
+ wire _05774_;
+ wire _05775_;
+ wire _05776_;
+ wire _05777_;
+ wire _05778_;
+ wire _05779_;
+ wire _05780_;
+ wire _05781_;
+ wire _05782_;
+ wire _05783_;
+ wire _05784_;
+ wire _05785_;
+ wire _05786_;
+ wire _05787_;
+ wire _05788_;
+ wire _05789_;
+ wire _05790_;
+ wire _05791_;
+ wire _05792_;
+ wire _05793_;
+ wire _05794_;
+ wire _05795_;
+ wire _05796_;
+ wire _05797_;
+ wire _05798_;
+ wire _05799_;
+ wire _05800_;
+ wire _05801_;
+ wire _05802_;
+ wire _05803_;
+ wire _05804_;
+ wire _05805_;
+ wire _05806_;
+ wire _05807_;
+ wire _05808_;
+ wire _05809_;
+ wire _05810_;
+ wire _05811_;
+ wire _05812_;
+ wire _05813_;
+ wire _05814_;
+ wire _05815_;
+ wire _05816_;
+ wire _05817_;
+ wire _05818_;
+ wire _05819_;
+ wire _05820_;
+ wire _05821_;
+ wire _05822_;
+ wire _05823_;
+ wire _05824_;
+ wire _05825_;
+ wire _05826_;
+ wire _05827_;
+ wire _05828_;
+ wire _05829_;
+ wire _05830_;
+ wire _05831_;
+ wire _05832_;
+ wire _05833_;
+ wire _05834_;
+ wire _05835_;
+ wire _05836_;
+ wire _05837_;
+ wire _05838_;
+ wire _05839_;
+ wire _05840_;
+ wire _05841_;
+ wire _05842_;
+ wire _05843_;
+ wire _05844_;
+ wire _05845_;
+ wire _05846_;
+ wire _05847_;
+ wire _05848_;
+ wire _05849_;
+ wire _05850_;
+ wire _05851_;
+ wire _05852_;
+ wire _05853_;
+ wire _05854_;
+ wire _05855_;
+ wire _05856_;
+ wire _05857_;
+ wire _05858_;
+ wire _05859_;
+ wire _05860_;
+ wire _05861_;
+ wire _05862_;
+ wire _05863_;
+ wire _05864_;
+ wire _05865_;
+ wire _05866_;
+ wire _05867_;
+ wire _05868_;
+ wire _05869_;
+ wire _05870_;
+ wire _05871_;
+ wire _05872_;
+ wire _05873_;
+ wire _05874_;
+ wire _05875_;
+ wire _05876_;
+ wire _05877_;
+ wire _05878_;
+ wire _05879_;
+ wire _05880_;
+ wire _05881_;
+ wire _05882_;
+ wire _05883_;
+ wire _05884_;
+ wire _05885_;
+ wire _05886_;
+ wire _05887_;
+ wire _05888_;
+ wire _05889_;
+ wire _05890_;
+ wire _05891_;
+ wire _05892_;
+ wire _05893_;
+ wire _05894_;
+ wire _05895_;
+ wire _05896_;
+ wire _05897_;
+ wire _05898_;
+ wire _05899_;
+ wire _05900_;
+ wire _05901_;
+ wire _05902_;
+ wire _05903_;
+ wire _05904_;
+ wire _05905_;
+ wire _05906_;
+ wire _05907_;
+ wire _05908_;
+ wire _05909_;
+ wire _05910_;
+ wire _05911_;
+ wire _05912_;
+ wire _05913_;
+ wire _05914_;
+ wire _05915_;
+ wire _05916_;
+ wire _05917_;
+ wire _05918_;
+ wire _05919_;
+ wire _05920_;
+ wire _05921_;
+ wire _05922_;
+ wire _05923_;
+ wire _05924_;
+ wire _05925_;
+ wire _05926_;
+ wire _05927_;
+ wire _05928_;
+ wire _05929_;
+ wire _05930_;
+ wire _05931_;
+ wire _05932_;
+ wire _05933_;
+ wire _05934_;
+ wire _05935_;
+ wire _05936_;
+ wire _05937_;
+ wire _05938_;
+ wire _05939_;
+ wire _05940_;
+ wire _05941_;
+ wire _05942_;
+ wire _05943_;
+ wire _05944_;
+ wire _05945_;
+ wire _05946_;
+ wire _05947_;
+ wire _05948_;
+ wire _05949_;
+ wire _05950_;
+ wire _05951_;
+ wire _05952_;
+ wire _05953_;
+ wire _05954_;
+ wire _05955_;
+ wire _05956_;
+ wire _05957_;
+ wire _05958_;
+ wire _05959_;
+ wire _05960_;
+ wire _05961_;
+ wire _05962_;
+ wire _05963_;
+ wire _05964_;
+ wire _05965_;
+ wire _05966_;
+ wire _05967_;
+ wire _05968_;
+ wire _05969_;
+ wire _05970_;
+ wire _05971_;
+ wire _05972_;
+ wire _05973_;
+ wire _05974_;
+ wire _05975_;
+ wire _05976_;
+ wire _05977_;
+ wire _05978_;
+ wire _05979_;
+ wire _05980_;
+ wire _05981_;
+ wire _05982_;
+ wire _05983_;
+ wire _05984_;
+ wire _05985_;
+ wire _05986_;
+ wire _05987_;
+ wire _05988_;
+ wire _05989_;
+ wire _05990_;
+ wire _05991_;
+ wire _05992_;
+ wire _05993_;
+ wire _05994_;
+ wire _05995_;
+ wire _05996_;
+ wire _05997_;
+ wire _05998_;
+ wire _05999_;
+ wire _06000_;
+ wire _06001_;
+ wire _06002_;
+ wire _06003_;
+ wire _06004_;
+ wire _06005_;
+ wire _06006_;
+ wire _06007_;
+ wire _06008_;
+ wire _06009_;
+ wire _06010_;
+ wire _06011_;
+ wire _06012_;
+ wire _06013_;
+ wire _06014_;
+ wire _06015_;
+ wire _06016_;
+ wire _06017_;
+ wire _06018_;
+ wire _06019_;
+ wire _06020_;
+ wire _06021_;
+ wire _06022_;
+ wire _06023_;
+ wire _06024_;
+ wire _06025_;
+ wire _06026_;
+ wire _06027_;
+ wire _06028_;
+ wire _06029_;
+ wire _06030_;
+ wire _06031_;
+ wire _06032_;
+ wire _06033_;
+ wire _06034_;
+ wire _06035_;
+ wire _06036_;
+ wire _06037_;
+ wire _06038_;
+ wire _06039_;
+ wire _06040_;
+ wire _06041_;
+ wire _06042_;
+ wire _06043_;
+ wire _06044_;
+ wire _06045_;
+ wire _06046_;
+ wire _06047_;
+ wire _06048_;
+ wire _06049_;
+ wire _06050_;
+ wire _06051_;
+ wire _06052_;
+ wire _06053_;
+ wire _06054_;
+ wire _06055_;
+ wire _06056_;
+ wire _06057_;
+ wire _06058_;
+ wire _06059_;
+ wire _06060_;
+ wire _06061_;
+ wire _06062_;
+ wire _06063_;
+ wire _06064_;
+ wire _06065_;
+ wire _06066_;
+ wire _06067_;
+ wire _06068_;
+ wire _06069_;
+ wire _06070_;
+ wire _06071_;
+ wire _06072_;
+ wire _06073_;
+ wire _06074_;
+ wire _06075_;
+ wire _06076_;
+ wire _06077_;
+ wire _06078_;
+ wire _06079_;
+ wire _06080_;
+ wire _06081_;
+ wire _06082_;
+ wire _06083_;
+ wire _06084_;
+ wire _06085_;
+ wire _06086_;
+ wire _06087_;
+ wire _06088_;
+ wire _06089_;
+ wire _06090_;
+ wire _06091_;
+ wire _06092_;
+ wire _06093_;
+ wire _06094_;
+ wire _06095_;
+ wire _06096_;
+ wire _06097_;
+ wire _06098_;
+ wire _06099_;
+ wire _06100_;
+ wire _06101_;
+ wire _06102_;
+ wire _06103_;
+ wire _06104_;
+ wire _06105_;
+ wire _06106_;
+ wire _06107_;
+ wire _06108_;
+ wire _06109_;
+ wire _06110_;
+ wire _06111_;
+ wire _06112_;
+ wire _06113_;
+ wire _06114_;
+ wire _06115_;
+ wire _06116_;
+ wire _06117_;
+ wire _06118_;
+ wire _06119_;
+ wire _06120_;
+ wire _06121_;
+ wire _06122_;
+ wire _06123_;
+ wire _06124_;
+ wire _06125_;
+ wire _06126_;
+ wire _06127_;
+ wire _06128_;
+ wire _06129_;
+ wire _06130_;
+ wire _06131_;
+ wire _06132_;
+ wire _06133_;
+ wire _06134_;
+ wire _06135_;
+ wire _06136_;
+ wire _06137_;
+ wire _06138_;
+ wire _06139_;
+ wire _06140_;
+ wire _06141_;
+ wire _06142_;
+ wire _06143_;
+ wire _06144_;
+ wire _06145_;
+ wire _06146_;
+ wire _06147_;
+ wire _06148_;
+ wire _06149_;
+ wire _06150_;
+ wire _06151_;
+ wire _06152_;
+ wire _06153_;
+ wire _06154_;
+ wire _06155_;
+ wire _06156_;
+ wire _06157_;
+ wire _06158_;
+ wire _06159_;
+ wire _06160_;
+ wire _06161_;
+ wire _06162_;
+ wire _06163_;
+ wire _06164_;
+ wire _06165_;
+ wire _06166_;
+ wire _06167_;
+ wire _06168_;
+ wire _06169_;
+ wire _06170_;
+ wire _06171_;
+ wire _06172_;
+ wire _06173_;
+ wire _06174_;
+ wire _06175_;
+ wire _06176_;
+ wire _06177_;
+ wire _06178_;
+ wire _06179_;
+ wire _06180_;
+ wire _06181_;
+ wire _06182_;
+ wire _06183_;
+ wire _06184_;
+ wire _06185_;
+ wire _06186_;
+ wire _06187_;
+ wire _06188_;
+ wire _06189_;
+ wire _06190_;
+ wire _06191_;
+ wire _06192_;
+ wire _06193_;
+ wire _06194_;
+ wire _06195_;
+ wire _06196_;
+ wire _06197_;
+ wire _06198_;
+ wire _06199_;
+ wire _06200_;
+ wire _06201_;
+ wire _06202_;
+ wire _06203_;
+ wire _06204_;
+ wire _06205_;
+ wire _06206_;
+ wire _06207_;
+ wire _06208_;
+ wire _06209_;
+ wire _06210_;
+ wire _06211_;
+ wire _06212_;
+ wire _06213_;
+ wire _06214_;
+ wire _06215_;
+ wire _06216_;
+ wire _06217_;
+ wire _06218_;
+ wire _06219_;
+ wire _06220_;
+ wire _06221_;
+ wire _06222_;
+ wire _06223_;
+ wire _06224_;
+ wire _06225_;
+ wire _06226_;
+ wire _06227_;
+ wire _06228_;
+ wire _06229_;
+ wire _06230_;
+ wire _06231_;
+ wire _06232_;
+ wire _06233_;
+ wire _06234_;
+ wire _06235_;
+ wire _06236_;
+ wire _06237_;
+ wire _06238_;
+ wire _06239_;
+ wire _06240_;
+ wire _06241_;
+ wire _06242_;
+ wire _06243_;
+ wire _06244_;
+ wire _06245_;
+ wire _06246_;
+ wire _06247_;
+ wire _06248_;
+ wire _06249_;
+ wire _06250_;
+ wire _06251_;
+ wire _06252_;
+ wire _06253_;
+ wire _06254_;
+ wire _06255_;
+ wire _06256_;
+ wire _06257_;
+ wire _06258_;
+ wire _06259_;
+ wire _06260_;
+ wire _06261_;
+ wire _06262_;
+ wire _06263_;
+ wire _06264_;
+ wire _06265_;
+ wire _06266_;
+ wire _06267_;
+ wire _06268_;
+ wire _06269_;
+ wire _06270_;
+ wire _06271_;
+ wire _06272_;
+ wire _06273_;
+ wire _06274_;
+ wire _06275_;
+ wire _06276_;
+ wire _06277_;
+ wire _06278_;
+ wire _06279_;
+ wire _06280_;
+ wire _06281_;
+ wire _06282_;
+ wire _06283_;
+ wire _06284_;
+ wire _06285_;
+ wire _06286_;
+ wire _06287_;
+ wire _06288_;
+ wire _06289_;
+ wire _06290_;
+ wire _06291_;
+ wire _06292_;
+ wire _06293_;
+ wire _06294_;
+ wire _06295_;
+ wire _06296_;
+ wire _06297_;
+ wire _06298_;
+ wire _06299_;
+ wire _06300_;
+ wire _06301_;
+ wire _06302_;
+ wire _06303_;
+ wire _06304_;
+ wire _06305_;
+ wire _06306_;
+ wire _06307_;
+ wire _06308_;
+ wire _06309_;
+ wire _06310_;
+ wire _06311_;
+ wire _06312_;
+ wire _06313_;
+ wire _06314_;
+ wire _06315_;
+ wire _06316_;
+ wire _06317_;
+ wire _06318_;
+ wire _06319_;
+ wire _06320_;
+ wire _06321_;
+ wire _06322_;
+ wire _06323_;
+ wire _06324_;
+ wire _06325_;
+ wire _06326_;
+ wire _06327_;
+ wire _06328_;
+ wire _06329_;
+ wire _06330_;
+ wire _06331_;
+ wire _06332_;
+ wire _06333_;
+ wire _06334_;
+ wire _06335_;
+ wire _06336_;
+ wire _06337_;
+ wire _06338_;
+ wire _06339_;
+ wire _06340_;
+ wire _06341_;
+ wire _06342_;
+ wire _06343_;
+ wire _06344_;
+ wire _06345_;
+ wire _06346_;
+ wire _06347_;
+ wire _06348_;
+ wire _06349_;
+ wire _06350_;
+ wire _06351_;
+ wire _06352_;
+ wire _06353_;
+ wire _06354_;
+ wire _06355_;
+ wire _06356_;
+ wire _06357_;
+ wire _06358_;
+ wire _06359_;
+ wire _06360_;
+ wire _06361_;
+ wire _06362_;
+ wire _06363_;
+ wire _06364_;
+ wire _06365_;
+ wire _06366_;
+ wire _06367_;
+ wire _06368_;
+ wire _06369_;
+ wire _06370_;
+ wire _06371_;
+ wire _06372_;
+ wire _06373_;
+ wire _06374_;
+ wire _06375_;
+ wire _06376_;
+ wire _06377_;
+ wire _06378_;
+ wire _06379_;
+ wire _06380_;
+ wire _06381_;
+ wire _06382_;
+ wire _06383_;
+ wire _06384_;
+ wire _06385_;
+ wire _06386_;
+ wire _06387_;
+ wire _06388_;
+ wire _06389_;
+ wire _06390_;
+ wire _06391_;
+ wire _06392_;
+ wire _06393_;
+ wire _06394_;
+ wire _06395_;
+ wire _06396_;
+ wire _06397_;
+ wire _06398_;
+ wire _06399_;
+ wire _06400_;
+ wire _06401_;
+ wire _06402_;
+ wire _06403_;
+ wire _06404_;
+ wire _06405_;
+ wire _06406_;
+ wire _06407_;
+ wire _06408_;
+ wire _06409_;
+ wire _06410_;
+ wire _06411_;
+ wire _06412_;
+ wire _06413_;
+ wire _06414_;
+ wire _06415_;
+ wire _06416_;
+ wire _06417_;
+ wire _06418_;
+ wire _06419_;
+ wire _06420_;
+ wire _06421_;
+ wire _06422_;
+ wire _06423_;
+ wire _06424_;
+ wire _06425_;
+ wire _06426_;
+ wire _06427_;
+ wire _06428_;
+ wire _06429_;
+ wire _06430_;
+ wire _06431_;
+ wire _06432_;
+ wire _06433_;
+ wire _06434_;
+ wire _06435_;
+ wire _06436_;
+ wire _06437_;
+ wire _06438_;
+ wire _06439_;
+ wire _06440_;
+ wire _06441_;
+ wire _06442_;
+ wire _06443_;
+ wire _06444_;
+ wire _06445_;
+ wire _06446_;
+ wire _06447_;
+ wire _06448_;
+ wire _06449_;
+ wire _06450_;
+ wire _06451_;
+ wire _06452_;
+ wire _06453_;
+ wire _06454_;
+ wire _06455_;
+ wire _06456_;
+ wire _06457_;
+ wire _06458_;
+ wire _06459_;
+ wire _06460_;
+ wire _06461_;
+ wire _06462_;
+ wire _06463_;
+ wire _06464_;
+ wire _06465_;
+ wire _06466_;
+ wire _06467_;
+ wire _06468_;
+ wire _06469_;
+ wire _06470_;
+ wire _06471_;
+ wire _06472_;
+ wire _06473_;
+ wire _06474_;
+ wire _06475_;
+ wire _06476_;
+ wire _06477_;
+ wire _06478_;
+ wire _06479_;
+ wire _06480_;
+ wire _06481_;
+ wire _06482_;
+ wire _06483_;
+ wire _06484_;
+ wire _06485_;
+ wire _06486_;
+ wire _06487_;
+ wire _06488_;
+ wire _06489_;
+ wire _06490_;
+ wire _06491_;
+ wire _06492_;
+ wire _06493_;
+ wire _06494_;
+ wire _06495_;
+ wire _06496_;
+ wire _06497_;
+ wire _06498_;
+ wire _06499_;
+ wire _06500_;
+ wire _06501_;
+ wire _06502_;
+ wire _06503_;
+ wire _06504_;
+ wire _06505_;
+ wire _06506_;
+ wire _06507_;
+ wire _06508_;
+ wire _06509_;
+ wire _06510_;
+ wire _06511_;
+ wire _06512_;
+ wire _06513_;
+ wire _06514_;
+ wire _06515_;
+ wire _06516_;
+ wire _06517_;
+ wire _06518_;
+ wire _06519_;
+ wire _06520_;
+ wire _06521_;
+ wire _06522_;
+ wire _06523_;
+ wire _06524_;
+ wire _06525_;
+ wire _06526_;
+ wire _06527_;
+ wire _06528_;
+ wire _06529_;
+ wire _06530_;
+ wire _06531_;
+ wire _06532_;
+ wire _06533_;
+ wire _06534_;
+ wire _06535_;
+ wire _06536_;
+ wire _06537_;
+ wire _06538_;
+ wire _06539_;
+ wire _06540_;
+ wire _06541_;
+ wire _06542_;
+ wire _06543_;
+ wire _06544_;
+ wire _06545_;
+ wire _06546_;
+ wire _06547_;
+ wire _06548_;
+ wire _06549_;
+ wire _06550_;
+ wire _06551_;
+ wire _06552_;
+ wire _06553_;
+ wire _06554_;
+ wire _06555_;
+ wire _06556_;
+ wire _06557_;
+ wire _06558_;
+ wire _06559_;
+ wire _06560_;
+ wire _06561_;
+ wire _06562_;
+ wire _06563_;
+ wire _06564_;
+ wire _06565_;
+ wire _06566_;
+ wire _06567_;
+ wire _06568_;
+ wire _06569_;
+ wire _06570_;
+ wire _06571_;
+ wire _06572_;
+ wire _06573_;
+ wire _06574_;
+ wire _06575_;
+ wire _06576_;
+ wire _06577_;
+ wire _06578_;
+ wire _06579_;
+ wire _06580_;
+ wire _06581_;
+ wire _06582_;
+ wire _06583_;
+ wire _06584_;
+ wire _06585_;
+ wire _06586_;
+ wire _06587_;
+ wire _06588_;
+ wire _06589_;
+ wire _06590_;
+ wire _06591_;
+ wire _06592_;
+ wire _06593_;
+ wire _06594_;
+ wire _06595_;
+ wire _06596_;
+ wire _06597_;
+ wire _06598_;
+ wire _06599_;
+ wire _06600_;
+ wire _06601_;
+ wire _06602_;
+ wire _06603_;
+ wire _06604_;
+ wire _06605_;
+ wire _06606_;
+ wire _06607_;
+ wire _06608_;
+ wire _06609_;
+ wire _06610_;
+ wire _06611_;
+ wire _06612_;
+ wire _06613_;
+ wire _06614_;
+ wire _06615_;
+ wire _06616_;
+ wire _06617_;
+ wire _06618_;
+ wire _06619_;
+ wire _06620_;
+ wire _06621_;
+ wire _06622_;
+ wire _06623_;
+ wire _06624_;
+ wire _06625_;
+ wire _06626_;
+ wire _06627_;
+ wire _06628_;
+ wire _06629_;
+ wire _06630_;
+ wire _06631_;
+ wire _06632_;
+ wire _06633_;
+ wire _06634_;
+ wire _06635_;
+ wire _06636_;
+ wire _06637_;
+ wire _06638_;
+ wire _06639_;
+ wire _06640_;
+ wire _06641_;
+ wire _06642_;
+ wire _06643_;
+ wire _06644_;
+ wire _06645_;
+ wire _06646_;
+ wire _06647_;
+ wire _06648_;
+ wire _06649_;
+ wire _06650_;
+ wire _06651_;
+ wire _06652_;
+ wire _06653_;
+ wire _06654_;
+ wire _06655_;
+ wire _06656_;
+ wire _06657_;
+ wire _06658_;
+ wire _06659_;
+ wire _06660_;
+ wire _06661_;
+ wire _06662_;
+ wire _06663_;
+ wire _06664_;
+ wire _06665_;
+ wire _06666_;
+ wire _06667_;
+ wire _06668_;
+ wire _06669_;
+ wire _06670_;
+ wire _06671_;
+ wire _06672_;
+ wire _06673_;
+ wire _06674_;
+ wire _06675_;
+ wire _06676_;
+ wire _06677_;
+ wire _06678_;
+ wire _06679_;
+ wire _06680_;
+ wire _06681_;
+ wire _06682_;
+ wire _06683_;
+ wire _06684_;
+ wire _06685_;
+ wire _06686_;
+ wire _06687_;
+ wire _06688_;
+ wire _06689_;
+ wire _06690_;
+ wire _06691_;
+ wire _06692_;
+ wire _06693_;
+ wire _06694_;
+ wire _06695_;
+ wire _06696_;
+ wire _06697_;
+ wire _06698_;
+ wire _06699_;
+ wire _06700_;
+ wire _06701_;
+ wire _06702_;
+ wire _06703_;
+ wire _06704_;
+ wire _06705_;
+ wire _06706_;
+ wire _06707_;
+ wire _06708_;
+ wire _06709_;
+ wire _06710_;
+ wire _06711_;
+ wire _06712_;
+ wire _06713_;
+ wire _06714_;
+ wire _06715_;
+ wire _06716_;
+ wire _06717_;
+ wire _06718_;
+ wire _06719_;
+ wire _06720_;
+ wire _06721_;
+ wire _06722_;
+ wire _06723_;
+ wire _06724_;
+ wire _06725_;
+ wire _06726_;
+ wire _06727_;
+ wire _06728_;
+ wire _06729_;
+ wire _06730_;
+ wire _06731_;
+ wire _06732_;
+ wire _06733_;
+ wire _06734_;
+ wire _06735_;
+ wire _06736_;
+ wire _06737_;
+ wire _06738_;
+ wire _06739_;
+ wire _06740_;
+ wire _06741_;
+ wire _06742_;
+ wire _06743_;
+ wire _06744_;
+ wire _06745_;
+ wire _06746_;
+ wire _06747_;
+ wire _06748_;
+ wire _06749_;
+ wire _06750_;
+ wire _06751_;
+ wire _06752_;
+ wire _06753_;
+ wire _06754_;
+ wire _06755_;
+ wire _06756_;
+ wire _06757_;
+ wire _06758_;
+ wire _06759_;
+ wire _06760_;
+ wire _06761_;
+ wire _06762_;
+ wire _06763_;
+ wire _06764_;
+ wire _06765_;
+ wire _06766_;
+ wire _06767_;
+ wire _06768_;
+ wire _06769_;
+ wire _06770_;
+ wire _06771_;
+ wire _06772_;
+ wire _06773_;
+ wire _06774_;
+ wire _06775_;
+ wire _06776_;
+ wire _06777_;
+ wire _06778_;
+ wire _06779_;
+ wire _06780_;
+ wire _06781_;
+ wire _06782_;
+ wire _06783_;
+ wire _06784_;
+ wire _06785_;
+ wire _06786_;
+ wire _06787_;
+ wire _06788_;
+ wire _06789_;
+ wire _06790_;
+ wire _06791_;
+ wire _06792_;
+ wire _06793_;
+ wire _06794_;
+ wire _06795_;
+ wire _06796_;
+ wire _06797_;
+ wire _06798_;
+ wire _06799_;
+ wire _06800_;
+ wire _06801_;
+ wire _06802_;
+ wire _06803_;
+ wire _06804_;
+ wire _06805_;
+ wire _06806_;
+ wire _06807_;
+ wire _06808_;
+ wire _06809_;
+ wire _06810_;
+ wire _06811_;
+ wire _06812_;
+ wire _06813_;
+ wire _06814_;
+ wire _06815_;
+ wire _06816_;
+ wire _06817_;
+ wire _06818_;
+ wire _06819_;
+ wire _06820_;
+ wire _06821_;
+ wire _06822_;
+ wire _06823_;
+ wire _06824_;
+ wire _06825_;
+ wire _06826_;
+ wire _06827_;
+ wire _06828_;
+ wire _06829_;
+ wire _06830_;
+ wire _06831_;
+ wire _06832_;
+ wire _06833_;
+ wire _06834_;
+ wire _06835_;
+ wire _06836_;
+ wire _06837_;
+ wire _06838_;
+ wire _06839_;
+ wire _06840_;
+ wire _06841_;
+ wire _06842_;
+ wire _06843_;
+ wire _06844_;
+ wire _06845_;
+ wire _06846_;
+ wire _06847_;
+ wire _06848_;
+ wire _06849_;
+ wire _06850_;
+ wire _06851_;
+ wire _06852_;
+ wire _06853_;
+ wire _06854_;
+ wire _06855_;
+ wire _06856_;
+ wire _06857_;
+ wire _06858_;
+ wire _06859_;
+ wire _06860_;
+ wire _06861_;
+ wire _06862_;
+ wire _06863_;
+ wire _06864_;
+ wire _06865_;
+ wire _06866_;
+ wire _06867_;
+ wire _06868_;
+ wire _06869_;
+ wire _06870_;
+ wire _06871_;
+ wire _06872_;
+ wire _06873_;
+ wire _06874_;
+ wire _06875_;
+ wire _06876_;
+ wire _06877_;
+ wire _06878_;
+ wire _06879_;
+ wire _06880_;
+ wire _06881_;
+ wire _06882_;
+ wire _06883_;
+ wire _06884_;
+ wire _06885_;
+ wire _06886_;
+ wire _06887_;
+ wire _06888_;
+ wire _06889_;
+ wire _06890_;
+ wire _06891_;
+ wire _06892_;
+ wire _06893_;
+ wire _06894_;
+ wire _06895_;
+ wire _06896_;
+ wire _06897_;
+ wire _06898_;
+ wire _06899_;
+ wire _06900_;
+ wire _06901_;
+ wire _06902_;
+ wire _06903_;
+ wire _06904_;
+ wire _06905_;
+ wire _06906_;
+ wire _06907_;
+ wire _06908_;
+ wire _06909_;
+ wire _06910_;
+ wire _06911_;
+ wire _06912_;
+ wire _06913_;
+ wire _06914_;
+ wire _06915_;
+ wire _06916_;
+ wire _06917_;
+ wire _06918_;
+ wire _06919_;
+ wire _06920_;
+ wire _06921_;
+ wire _06922_;
+ wire _06923_;
+ wire _06924_;
+ wire _06925_;
+ wire _06926_;
+ wire _06927_;
+ wire _06928_;
+ wire _06929_;
+ wire _06930_;
+ wire _06931_;
+ wire _06932_;
+ wire _06933_;
+ wire _06934_;
+ wire _06935_;
+ wire _06936_;
+ wire _06937_;
+ wire _06938_;
+ wire _06939_;
+ wire _06940_;
+ wire _06941_;
+ wire _06942_;
+ wire _06943_;
+ wire _06944_;
+ wire _06945_;
+ wire _06946_;
+ wire _06947_;
+ wire _06948_;
+ wire _06949_;
+ wire _06950_;
+ wire _06951_;
+ wire _06952_;
+ wire _06953_;
+ wire _06954_;
+ wire _06955_;
+ wire _06956_;
+ wire _06957_;
+ wire _06958_;
+ wire _06959_;
+ wire _06960_;
+ wire _06961_;
+ wire _06962_;
+ wire _06963_;
+ wire _06964_;
+ wire _06965_;
+ wire _06966_;
+ wire _06967_;
+ wire _06968_;
+ wire _06969_;
+ wire _06970_;
+ wire _06971_;
+ wire _06972_;
+ wire _06973_;
+ wire _06974_;
+ wire _06975_;
+ wire _06976_;
+ wire _06977_;
+ wire _06978_;
+ wire _06979_;
+ wire _06980_;
+ wire _06981_;
+ wire _06982_;
+ wire _06983_;
+ wire _06984_;
+ wire _06985_;
+ wire _06986_;
+ wire _06987_;
+ wire _06988_;
+ wire _06989_;
+ wire _06990_;
+ wire _06991_;
+ wire _06992_;
+ wire _06993_;
+ wire _06994_;
+ wire _06995_;
+ wire _06996_;
+ wire _06997_;
+ wire _06998_;
+ wire _06999_;
+ wire _07000_;
+ wire _07001_;
+ wire _07002_;
+ wire _07003_;
+ wire _07004_;
+ wire _07005_;
+ wire _07006_;
+ wire _07007_;
+ wire _07008_;
+ wire _07009_;
+ wire _07010_;
+ wire _07011_;
+ wire _07012_;
+ wire _07013_;
+ wire _07014_;
+ wire _07015_;
+ wire _07016_;
+ wire _07017_;
+ wire _07018_;
+ wire _07019_;
+ wire _07020_;
+ wire _07021_;
+ wire _07022_;
+ wire _07023_;
+ wire _07024_;
+ wire _07025_;
+ wire _07026_;
+ wire _07027_;
+ wire _07028_;
+ wire _07029_;
+ wire _07030_;
+ wire _07031_;
+ wire _07032_;
+ wire _07033_;
+ wire _07034_;
+ wire _07035_;
+ wire _07036_;
+ wire _07037_;
+ wire _07038_;
+ wire _07039_;
+ wire _07040_;
+ wire _07041_;
+ wire _07042_;
+ wire _07043_;
+ wire _07044_;
+ wire _07045_;
+ wire _07046_;
+ wire _07047_;
+ wire _07048_;
+ wire _07049_;
+ wire _07050_;
+ wire _07051_;
+ wire _07052_;
+ wire _07053_;
+ wire _07054_;
+ wire _07055_;
+ wire _07056_;
+ wire _07057_;
+ wire _07058_;
+ wire _07059_;
+ wire _07060_;
+ wire _07061_;
+ wire _07062_;
+ wire _07063_;
+ wire _07064_;
+ wire _07065_;
+ wire _07066_;
+ wire _07067_;
+ wire _07068_;
+ wire _07069_;
+ wire _07070_;
+ wire _07071_;
+ wire _07072_;
+ wire _07073_;
+ wire _07074_;
+ wire _07075_;
+ wire _07076_;
+ wire _07077_;
+ wire _07078_;
+ wire _07079_;
+ wire _07080_;
+ wire _07081_;
+ wire _07082_;
+ wire _07083_;
+ wire _07084_;
+ wire _07085_;
+ wire _07086_;
+ wire _07087_;
+ wire _07088_;
+ wire _07089_;
+ wire _07090_;
+ wire _07091_;
+ wire _07092_;
+ wire _07093_;
+ wire _07094_;
+ wire _07095_;
+ wire _07096_;
+ wire _07097_;
+ wire _07098_;
+ wire _07099_;
+ wire _07100_;
+ wire _07101_;
+ wire _07102_;
+ wire _07103_;
+ wire _07104_;
+ wire _07105_;
+ wire _07106_;
+ wire _07107_;
+ wire _07108_;
+ wire _07109_;
+ wire _07110_;
+ wire _07111_;
+ wire _07112_;
+ wire _07113_;
+ wire _07114_;
+ wire _07115_;
+ wire _07116_;
+ wire _07117_;
+ wire _07118_;
+ wire _07119_;
+ wire _07120_;
+ wire _07121_;
+ wire _07122_;
+ wire _07123_;
+ wire _07124_;
+ wire _07125_;
+ wire _07126_;
+ wire _07127_;
+ wire _07128_;
+ wire _07129_;
+ wire _07130_;
+ wire _07131_;
+ wire _07132_;
+ wire _07133_;
+ wire _07134_;
+ wire _07135_;
+ wire _07136_;
+ wire _07137_;
+ wire _07138_;
+ wire _07139_;
+ wire _07140_;
+ wire _07141_;
+ wire _07142_;
+ wire _07143_;
+ wire _07144_;
+ wire _07145_;
+ wire _07146_;
+ wire _07147_;
+ wire _07148_;
+ wire _07149_;
+ wire _07150_;
+ wire _07151_;
+ wire _07152_;
+ wire _07153_;
+ wire _07154_;
+ wire _07155_;
+ wire _07156_;
+ wire _07157_;
+ wire _07158_;
+ wire _07159_;
+ wire _07160_;
+ wire _07161_;
+ wire _07162_;
+ wire _07163_;
+ wire _07164_;
+ wire _07165_;
+ wire _07166_;
+ wire _07167_;
+ wire _07168_;
+ wire _07169_;
+ wire _07170_;
+ wire _07171_;
+ wire _07172_;
+ wire _07173_;
+ wire _07174_;
+ wire _07175_;
+ wire _07176_;
+ wire _07177_;
+ wire _07178_;
+ wire _07179_;
+ wire _07180_;
+ wire _07181_;
+ wire _07182_;
+ wire _07183_;
+ wire _07184_;
+ wire _07185_;
+ wire _07186_;
+ wire _07187_;
+ wire _07188_;
+ wire _07189_;
+ wire _07190_;
+ wire _07191_;
+ wire _07192_;
+ wire _07193_;
+ wire _07194_;
+ wire _07195_;
+ wire _07196_;
+ wire _07197_;
+ wire _07198_;
+ wire _07199_;
+ wire _07200_;
+ wire _07201_;
+ wire _07202_;
+ wire _07203_;
+ wire _07204_;
+ wire _07205_;
+ wire _07206_;
+ wire _07207_;
+ wire _07208_;
+ wire _07209_;
+ wire _07210_;
+ wire _07211_;
+ wire _07212_;
+ wire _07213_;
+ wire _07214_;
+ wire _07215_;
+ wire _07216_;
+ wire _07217_;
+ wire _07218_;
+ wire _07219_;
+ wire _07220_;
+ wire _07221_;
+ wire _07222_;
+ wire _07223_;
+ wire _07224_;
+ wire _07225_;
+ wire _07226_;
+ wire _07227_;
+ wire _07228_;
+ wire _07229_;
+ wire _07230_;
+ wire _07231_;
+ wire _07232_;
+ wire _07233_;
+ wire _07234_;
+ wire _07235_;
+ wire _07236_;
+ wire _07237_;
+ wire _07238_;
+ wire _07239_;
+ wire _07240_;
+ wire _07241_;
+ wire _07242_;
+ wire _07243_;
+ wire _07244_;
+ wire _07245_;
+ wire _07246_;
+ wire _07247_;
+ wire _07248_;
+ wire _07249_;
+ wire _07250_;
+ wire _07251_;
+ wire _07252_;
+ wire _07253_;
+ wire _07254_;
+ wire _07255_;
+ wire _07256_;
+ wire _07257_;
+ wire _07258_;
+ wire _07259_;
+ wire _07260_;
+ wire _07261_;
+ wire _07262_;
+ wire _07263_;
+ wire _07264_;
+ wire _07265_;
+ wire _07266_;
+ wire _07267_;
+ wire _07268_;
+ wire _07269_;
+ wire _07270_;
+ wire _07271_;
+ wire _07272_;
+ wire _07273_;
+ wire _07274_;
+ wire _07275_;
+ wire _07276_;
+ wire _07277_;
+ wire _07278_;
+ wire _07279_;
+ wire _07280_;
+ wire _07281_;
+ wire _07282_;
+ wire _07283_;
+ wire _07284_;
+ wire _07285_;
+ wire _07286_;
+ wire _07287_;
+ wire _07288_;
+ wire _07289_;
+ wire _07290_;
+ wire _07291_;
+ wire _07292_;
+ wire _07293_;
+ wire _07294_;
+ wire _07295_;
+ wire _07296_;
+ wire _07297_;
+ wire _07298_;
+ wire _07299_;
+ wire _07300_;
+ wire _07301_;
+ wire _07302_;
+ wire _07303_;
+ wire _07304_;
+ wire _07305_;
+ wire _07306_;
+ wire _07307_;
+ wire _07308_;
+ wire _07309_;
+ wire _07310_;
+ wire _07311_;
+ wire _07312_;
+ wire _07313_;
+ wire _07314_;
+ wire _07315_;
+ wire _07316_;
+ wire _07317_;
+ wire _07318_;
+ wire _07319_;
+ wire _07320_;
+ wire _07321_;
+ wire _07322_;
+ wire _07323_;
+ wire _07324_;
+ wire _07325_;
+ wire _07326_;
+ wire _07327_;
+ wire _07328_;
+ wire _07329_;
+ wire _07330_;
+ wire _07331_;
+ wire _07332_;
+ wire _07333_;
+ wire _07334_;
+ wire _07335_;
+ wire _07336_;
+ wire _07337_;
+ wire _07338_;
+ wire _07339_;
+ wire _07340_;
+ wire _07341_;
+ wire _07342_;
+ wire _07343_;
+ wire _07344_;
+ wire _07345_;
+ wire _07346_;
+ wire _07347_;
+ wire _07348_;
+ wire _07349_;
+ wire _07350_;
+ wire _07351_;
+ wire _07352_;
+ wire _07353_;
+ wire _07354_;
+ wire _07355_;
+ wire _07356_;
+ wire _07357_;
+ wire _07358_;
+ wire _07359_;
+ wire _07360_;
+ wire _07361_;
+ wire _07362_;
+ wire _07363_;
+ wire _07364_;
+ wire _07365_;
+ wire _07366_;
+ wire _07367_;
+ wire _07368_;
+ wire _07369_;
+ wire _07370_;
+ wire _07371_;
+ wire _07372_;
+ wire _07373_;
+ wire _07374_;
+ wire _07375_;
+ wire _07376_;
+ wire _07377_;
+ wire _07378_;
+ wire _07379_;
+ wire _07380_;
+ wire _07381_;
+ wire _07382_;
+ wire _07383_;
+ wire _07384_;
+ wire _07385_;
+ wire _07386_;
+ wire _07387_;
+ wire _07388_;
+ wire _07389_;
+ wire _07390_;
+ wire _07391_;
+ wire _07392_;
+ wire _07393_;
+ wire _07394_;
+ wire _07395_;
+ wire _07396_;
+ wire _07397_;
+ wire _07398_;
+ wire _07399_;
+ wire _07400_;
+ wire _07401_;
+ wire _07402_;
+ wire _07403_;
+ wire _07404_;
+ wire _07405_;
+ wire _07406_;
+ wire _07407_;
+ wire _07408_;
+ wire _07409_;
+ wire _07410_;
+ wire _07411_;
+ wire _07412_;
+ wire _07413_;
+ wire _07414_;
+ wire _07415_;
+ wire _07416_;
+ wire _07417_;
+ wire _07418_;
+ wire _07419_;
+ wire _07420_;
+ wire _07421_;
+ wire _07422_;
+ wire _07423_;
+ wire _07424_;
+ wire _07425_;
+ wire _07426_;
+ wire _07427_;
+ wire _07428_;
+ wire _07429_;
+ wire _07430_;
+ wire _07431_;
+ wire _07432_;
+ wire _07433_;
+ wire _07434_;
+ wire _07435_;
+ wire _07436_;
+ wire _07437_;
+ wire _07438_;
+ wire _07439_;
+ wire _07440_;
+ wire _07441_;
+ wire _07442_;
+ wire _07443_;
+ wire _07444_;
+ wire _07445_;
+ wire _07446_;
+ wire _07447_;
+ wire _07448_;
+ wire _07449_;
+ wire _07450_;
+ wire _07451_;
+ wire _07452_;
+ wire _07453_;
+ wire _07454_;
+ wire _07455_;
+ wire _07456_;
+ wire _07457_;
+ wire _07458_;
+ wire _07459_;
+ wire _07460_;
+ wire _07461_;
+ wire _07462_;
+ wire _07463_;
+ wire _07464_;
+ wire _07465_;
+ wire _07466_;
+ wire _07467_;
+ wire _07468_;
+ wire _07469_;
+ wire _07470_;
+ wire _07471_;
+ wire _07472_;
+ wire _07473_;
+ wire _07474_;
+ wire _07475_;
+ wire _07476_;
+ wire _07477_;
+ wire _07478_;
+ wire _07479_;
+ wire _07480_;
+ wire _07481_;
+ wire _07482_;
+ wire _07483_;
+ wire _07484_;
+ wire _07485_;
+ wire _07486_;
+ wire _07487_;
+ wire _07488_;
+ wire _07489_;
+ wire _07490_;
+ wire _07491_;
+ wire _07492_;
+ wire _07493_;
+ wire _07494_;
+ wire _07495_;
+ wire _07496_;
+ wire _07497_;
+ wire _07498_;
+ wire _07499_;
+ wire _07500_;
+ wire _07501_;
+ wire _07502_;
+ wire _07503_;
+ wire _07504_;
+ wire _07505_;
+ wire _07506_;
+ wire _07507_;
+ wire _07508_;
+ wire _07509_;
+ wire _07510_;
+ wire _07511_;
+ wire _07512_;
+ wire _07513_;
+ wire _07514_;
+ wire _07515_;
+ wire _07516_;
+ wire _07517_;
+ wire _07518_;
+ wire _07519_;
+ wire _07520_;
+ wire _07521_;
+ wire _07522_;
+ wire _07523_;
+ wire _07524_;
+ wire _07525_;
+ wire _07526_;
+ wire _07527_;
+ wire _07528_;
+ wire _07529_;
+ wire _07530_;
+ wire _07531_;
+ wire _07532_;
+ wire _07533_;
+ wire _07534_;
+ wire _07535_;
+ wire _07536_;
+ wire _07537_;
+ wire _07538_;
+ wire _07539_;
+ wire _07540_;
+ wire _07541_;
+ wire _07542_;
+ wire _07543_;
+ wire _07544_;
+ wire _07545_;
+ wire _07546_;
+ wire _07547_;
+ wire _07548_;
+ wire _07549_;
+ wire _07550_;
+ wire _07551_;
+ wire _07552_;
+ wire _07553_;
+ wire _07554_;
+ wire _07555_;
+ wire _07556_;
+ wire _07557_;
+ wire _07558_;
+ wire _07559_;
+ wire _07560_;
+ wire _07561_;
+ wire _07562_;
+ wire _07563_;
+ wire _07564_;
+ wire _07565_;
+ wire _07566_;
+ wire _07567_;
+ wire _07568_;
+ wire _07569_;
+ wire _07570_;
+ wire _07571_;
+ wire _07572_;
+ wire _07573_;
+ wire _07574_;
+ wire _07575_;
+ wire _07576_;
+ wire _07577_;
+ wire _07578_;
+ wire _07579_;
+ wire _07580_;
+ wire _07581_;
+ wire _07582_;
+ wire _07583_;
+ wire _07584_;
+ wire _07585_;
+ wire _07586_;
+ wire _07587_;
+ wire _07588_;
+ wire _07589_;
+ wire _07590_;
+ wire _07591_;
+ wire _07592_;
+ wire _07593_;
+ wire _07594_;
+ wire _07595_;
+ wire _07596_;
+ wire _07597_;
+ wire _07598_;
+ wire _07599_;
+ wire _07600_;
+ wire _07601_;
+ wire _07602_;
+ wire _07603_;
+ wire _07604_;
+ wire _07605_;
+ wire _07606_;
+ wire _07607_;
+ wire _07608_;
+ wire _07609_;
+ wire _07610_;
+ wire _07611_;
+ wire _07612_;
+ wire _07613_;
+ wire _07614_;
+ wire _07615_;
+ wire _07616_;
+ wire _07617_;
+ wire _07618_;
+ wire _07619_;
+ wire _07620_;
+ wire _07621_;
+ wire _07622_;
+ wire _07623_;
+ wire _07624_;
+ wire _07625_;
+ wire _07626_;
+ wire _07627_;
+ wire _07628_;
+ wire _07629_;
+ wire _07630_;
+ wire _07631_;
+ wire _07632_;
+ wire _07633_;
+ wire _07634_;
+ wire _07635_;
+ wire _07636_;
+ wire _07637_;
+ wire _07638_;
+ wire _07639_;
+ wire _07640_;
+ wire _07641_;
+ wire _07642_;
+ wire _07643_;
+ wire _07644_;
+ wire _07645_;
+ wire _07646_;
+ wire _07647_;
+ wire _07648_;
+ wire _07649_;
+ wire _07650_;
+ wire _07651_;
+ wire _07652_;
+ wire _07653_;
+ wire _07654_;
+ wire _07655_;
+ wire _07656_;
+ wire _07657_;
+ wire _07658_;
+ wire _07659_;
+ wire _07660_;
+ wire _07661_;
+ wire _07662_;
+ wire _07663_;
+ wire _07664_;
+ wire _07665_;
+ wire _07666_;
+ wire _07667_;
+ wire _07668_;
+ wire _07669_;
+ wire _07670_;
+ wire _07671_;
+ wire _07672_;
+ wire _07673_;
+ wire _07674_;
+ wire _07675_;
+ wire _07676_;
+ wire _07677_;
+ wire _07678_;
+ wire _07679_;
+ wire _07680_;
+ wire _07681_;
+ wire _07682_;
+ wire _07683_;
+ wire _07684_;
+ wire _07685_;
+ wire _07686_;
+ wire _07687_;
+ wire _07688_;
+ wire _07689_;
+ wire _07690_;
+ wire _07691_;
+ wire _07692_;
+ wire _07693_;
+ wire _07694_;
+ wire _07695_;
+ wire _07696_;
+ wire _07697_;
+ wire _07698_;
+ wire _07699_;
+ wire _07700_;
+ wire _07701_;
+ wire _07702_;
+ wire _07703_;
+ wire _07704_;
+ wire _07705_;
+ wire _07706_;
+ wire _07707_;
+ wire _07708_;
+ wire _07709_;
+ wire _07710_;
+ wire _07711_;
+ wire _07712_;
+ wire _07713_;
+ wire _07714_;
+ wire _07715_;
+ wire _07716_;
+ wire _07717_;
+ wire _07718_;
+ wire _07719_;
+ wire _07720_;
+ wire _07721_;
+ wire _07722_;
+ wire _07723_;
+ wire _07724_;
+ wire _07725_;
+ wire _07726_;
+ wire _07727_;
+ wire _07728_;
+ wire _07729_;
+ wire _07730_;
+ wire _07731_;
+ wire _07732_;
+ wire _07733_;
+ wire _07734_;
+ wire _07735_;
+ wire _07736_;
+ wire _07737_;
+ wire _07738_;
+ wire _07739_;
+ wire _07740_;
+ wire _07741_;
+ wire _07742_;
+ wire _07743_;
+ wire _07744_;
+ wire _07745_;
+ wire _07746_;
+ wire _07747_;
+ wire _07748_;
+ wire _07749_;
+ wire _07750_;
+ wire _07751_;
+ wire _07752_;
+ wire _07753_;
+ wire _07754_;
+ wire _07755_;
+ wire _07756_;
+ wire _07757_;
+ wire _07758_;
+ wire _07759_;
+ wire _07760_;
+ wire _07761_;
+ wire _07762_;
+ wire _07763_;
+ wire _07764_;
+ wire _07765_;
+ wire _07766_;
+ wire _07767_;
+ wire _07768_;
+ wire _07769_;
+ wire _07770_;
+ wire _07771_;
+ wire _07772_;
+ wire _07773_;
+ wire _07774_;
+ wire _07775_;
+ wire _07776_;
+ wire _07777_;
+ wire _07778_;
+ wire _07779_;
+ wire _07780_;
+ wire _07781_;
+ wire _07782_;
+ wire _07783_;
+ wire _07784_;
+ wire _07785_;
+ wire _07786_;
+ wire _07787_;
+ wire _07788_;
+ wire _07789_;
+ wire _07790_;
+ wire _07791_;
+ wire _07792_;
+ wire _07793_;
+ wire _07794_;
+ wire _07795_;
+ wire _07796_;
+ wire _07797_;
+ wire _07798_;
+ wire _07799_;
+ wire _07800_;
+ wire _07801_;
+ wire _07802_;
+ wire _07803_;
+ wire _07804_;
+ wire _07805_;
+ wire _07806_;
+ wire _07807_;
+ wire _07808_;
+ wire _07809_;
+ wire _07810_;
+ wire _07811_;
+ wire _07812_;
+ wire _07813_;
+ wire _07814_;
+ wire _07815_;
+ wire _07816_;
+ wire _07817_;
+ wire _07818_;
+ wire _07819_;
+ wire _07820_;
+ wire _07821_;
+ wire _07822_;
+ wire _07823_;
+ wire _07824_;
+ wire _07825_;
+ wire _07826_;
+ wire _07827_;
+ wire _07828_;
+ wire _07829_;
+ wire _07830_;
+ wire _07831_;
+ wire _07832_;
+ wire _07833_;
+ wire _07834_;
+ wire _07835_;
+ wire _07836_;
+ wire _07837_;
+ wire _07838_;
+ wire _07839_;
+ wire _07840_;
+ wire _07841_;
+ wire _07842_;
+ wire _07843_;
+ wire _07844_;
+ wire _07845_;
+ wire _07846_;
+ wire _07847_;
+ wire _07848_;
+ wire _07849_;
+ wire _07850_;
+ wire _07851_;
+ wire _07852_;
+ wire _07853_;
+ wire _07854_;
+ wire _07855_;
+ wire _07856_;
+ wire _07857_;
+ wire _07858_;
+ wire _07859_;
+ wire _07860_;
+ wire _07861_;
+ wire _07862_;
+ wire _07863_;
+ wire _07864_;
+ wire _07865_;
+ wire _07866_;
+ wire _07867_;
+ wire _07868_;
+ wire _07869_;
+ wire _07870_;
+ wire _07871_;
+ wire _07872_;
+ wire _07873_;
+ wire _07874_;
+ wire _07875_;
+ wire _07876_;
+ wire _07877_;
+ wire _07878_;
+ wire _07879_;
+ wire _07880_;
+ wire _07881_;
+ wire _07882_;
+ wire _07883_;
+ wire _07884_;
+ wire _07885_;
+ wire _07886_;
+ wire _07887_;
+ wire _07888_;
+ wire _07889_;
+ wire _07890_;
+ wire _07891_;
+ wire _07892_;
+ wire _07893_;
+ wire _07894_;
+ wire _07895_;
+ wire _07896_;
+ wire _07897_;
+ wire _07898_;
+ wire _07899_;
+ wire _07900_;
+ wire _07901_;
+ wire _07902_;
+ wire _07903_;
+ wire _07904_;
+ wire _07905_;
+ wire _07906_;
+ wire _07907_;
+ wire _07908_;
+ wire _07909_;
+ wire _07910_;
+ wire _07911_;
+ wire _07912_;
+ wire _07913_;
+ wire _07914_;
+ wire _07915_;
+ wire _07916_;
+ wire _07917_;
+ wire _07918_;
+ wire _07919_;
+ wire _07920_;
+ wire _07921_;
+ wire _07922_;
+ wire _07923_;
+ wire _07924_;
+ wire _07925_;
+ wire _07926_;
+ wire _07927_;
+ wire _07928_;
+ wire _07929_;
+ wire _07930_;
+ wire _07931_;
+ wire _07932_;
+ wire _07933_;
+ wire _07934_;
+ wire _07935_;
+ wire _07936_;
+ wire _07937_;
+ wire _07938_;
+ wire _07939_;
+ wire _07940_;
+ wire _07941_;
+ wire _07942_;
+ wire _07943_;
+ wire _07944_;
+ wire _07945_;
+ wire _07946_;
+ wire _07947_;
+ wire _07948_;
+ wire _07949_;
+ wire _07950_;
+ wire _07951_;
+ wire _07952_;
+ wire _07953_;
+ wire _07954_;
+ wire _07955_;
+ wire _07956_;
+ wire _07957_;
+ wire _07958_;
+ wire _07959_;
+ wire _07960_;
+ wire _07961_;
+ wire _07962_;
+ wire _07963_;
+ wire _07964_;
+ wire _07965_;
+ wire _07966_;
+ wire _07967_;
+ wire _07968_;
+ wire _07969_;
+ wire _07970_;
+ wire _07971_;
+ wire _07972_;
+ wire _07973_;
+ wire _07974_;
+ wire _07975_;
+ wire _07976_;
+ wire _07977_;
+ wire _07978_;
+ wire _07979_;
+ wire _07980_;
+ wire _07981_;
+ wire _07982_;
+ wire _07983_;
+ wire _07984_;
+ wire _07985_;
+ wire _07986_;
+ wire _07987_;
+ wire _07988_;
+ wire _07989_;
+ wire _07990_;
+ wire _07991_;
+ wire _07992_;
+ wire _07993_;
+ wire _07994_;
+ wire _07995_;
+ wire _07996_;
+ wire _07997_;
+ wire _07998_;
+ wire _07999_;
+ wire _08000_;
+ wire _08001_;
+ wire _08002_;
+ wire _08003_;
+ wire _08004_;
+ wire _08005_;
+ wire _08006_;
+ wire _08007_;
+ wire _08008_;
+ wire _08009_;
+ wire _08010_;
+ wire _08011_;
+ wire _08012_;
+ wire _08013_;
+ wire _08014_;
+ wire _08015_;
+ wire _08016_;
+ wire _08017_;
+ wire _08018_;
+ wire _08019_;
+ wire _08020_;
+ wire _08021_;
+ wire _08022_;
+ wire _08023_;
+ wire _08024_;
+ wire _08025_;
+ wire _08026_;
+ wire _08027_;
+ wire _08028_;
+ wire _08029_;
+ wire _08030_;
+ wire _08031_;
+ wire _08032_;
+ wire _08033_;
+ wire _08034_;
+ wire _08035_;
+ wire _08036_;
+ wire _08037_;
+ wire _08038_;
+ wire _08039_;
+ wire _08040_;
+ wire _08041_;
+ wire _08042_;
+ wire _08043_;
+ wire _08044_;
+ wire _08045_;
+ wire _08046_;
+ wire _08047_;
+ wire _08048_;
+ wire _08049_;
+ wire _08050_;
+ wire _08051_;
+ wire _08052_;
+ wire _08053_;
+ wire _08054_;
+ wire _08055_;
+ wire _08056_;
+ wire _08057_;
+ wire _08058_;
+ wire _08059_;
+ wire _08060_;
+ wire _08061_;
+ wire _08062_;
+ wire _08063_;
+ wire _08064_;
+ wire _08065_;
+ wire _08066_;
+ wire _08067_;
+ wire _08068_;
+ wire _08069_;
+ wire _08070_;
+ wire _08071_;
+ wire _08072_;
+ wire _08073_;
+ wire _08074_;
+ wire _08075_;
+ wire _08076_;
+ wire _08077_;
+ wire _08078_;
+ wire _08079_;
+ wire _08080_;
+ wire _08081_;
+ wire _08082_;
+ wire _08083_;
+ wire _08084_;
+ wire _08085_;
+ wire _08086_;
+ wire _08087_;
+ wire _08088_;
+ wire _08089_;
+ wire _08090_;
+ wire _08091_;
+ wire _08092_;
+ wire _08093_;
+ wire _08094_;
+ wire _08095_;
+ wire _08096_;
+ wire _08097_;
+ wire _08098_;
+ wire _08099_;
+ wire _08100_;
+ wire _08101_;
+ wire _08102_;
+ wire _08103_;
+ wire _08104_;
+ wire _08105_;
+ wire _08106_;
+ wire _08107_;
+ wire _08108_;
+ wire _08109_;
+ wire _08110_;
+ wire _08111_;
+ wire _08112_;
+ wire _08113_;
+ wire _08114_;
+ wire _08115_;
+ wire _08116_;
+ wire _08117_;
+ wire _08118_;
+ wire _08119_;
+ wire _08120_;
+ wire _08121_;
+ wire _08122_;
+ wire _08123_;
+ wire _08124_;
+ wire _08125_;
+ wire _08126_;
+ wire _08127_;
+ wire _08128_;
+ wire _08129_;
+ wire _08130_;
+ wire _08131_;
+ wire _08132_;
+ wire _08133_;
+ wire _08134_;
+ wire _08135_;
+ wire _08136_;
+ wire _08137_;
+ wire _08138_;
+ wire _08139_;
+ wire _08140_;
+ wire _08141_;
+ wire _08142_;
+ wire _08143_;
+ wire _08144_;
+ wire _08145_;
+ wire _08146_;
+ wire _08147_;
+ wire _08148_;
+ wire _08149_;
+ wire _08150_;
+ wire _08151_;
+ wire _08152_;
+ wire _08153_;
+ wire _08154_;
+ wire _08155_;
+ wire _08156_;
+ wire _08157_;
+ wire _08158_;
+ wire _08159_;
+ wire _08160_;
+ wire _08161_;
+ wire _08162_;
+ wire _08163_;
+ wire _08164_;
+ wire _08165_;
+ wire _08166_;
+ wire _08167_;
+ wire _08168_;
+ wire _08169_;
+ wire _08170_;
+ wire _08171_;
+ wire _08172_;
+ wire _08173_;
+ wire _08174_;
+ wire _08175_;
+ wire _08176_;
+ wire _08177_;
+ wire _08178_;
+ wire _08179_;
+ wire _08180_;
+ wire _08181_;
+ wire _08182_;
+ wire _08183_;
+ wire _08184_;
+ wire _08185_;
+ wire _08186_;
+ wire _08187_;
+ wire _08188_;
+ wire _08189_;
+ wire _08190_;
+ wire _08191_;
+ wire _08192_;
+ wire _08193_;
+ wire _08194_;
+ wire _08195_;
+ wire _08196_;
+ wire _08197_;
+ wire _08198_;
+ wire _08199_;
+ wire _08200_;
+ wire _08201_;
+ wire _08202_;
+ wire _08203_;
+ wire _08204_;
+ wire _08205_;
+ wire _08206_;
+ wire _08207_;
+ wire _08208_;
+ wire _08209_;
+ wire _08210_;
+ wire _08211_;
+ wire _08212_;
+ wire _08213_;
+ wire _08214_;
+ wire _08215_;
+ wire _08216_;
+ wire _08217_;
+ wire _08218_;
+ wire _08219_;
+ wire _08220_;
+ wire _08221_;
+ wire _08222_;
+ wire _08223_;
+ wire _08224_;
+ wire _08225_;
+ wire _08226_;
+ wire _08227_;
+ wire _08228_;
+ wire _08229_;
+ wire _08230_;
+ wire _08231_;
+ wire _08232_;
+ wire _08233_;
+ wire _08234_;
+ wire _08235_;
+ wire _08236_;
+ wire _08237_;
+ wire _08238_;
+ wire _08239_;
+ wire _08240_;
+ wire _08241_;
+ wire _08242_;
+ wire _08243_;
+ wire _08244_;
+ wire _08245_;
+ wire _08246_;
+ wire _08247_;
+ wire _08248_;
+ wire _08249_;
+ wire _08250_;
+ wire _08251_;
+ wire _08252_;
+ wire _08253_;
+ wire _08254_;
+ wire _08255_;
+ wire _08256_;
+ wire _08257_;
+ wire _08258_;
+ wire _08259_;
+ wire _08260_;
+ wire _08261_;
+ wire _08262_;
+ wire _08263_;
+ wire _08264_;
+ wire _08265_;
+ wire _08266_;
+ wire _08267_;
+ wire _08268_;
+ wire _08269_;
+ wire _08270_;
+ wire _08271_;
+ wire _08272_;
+ wire _08273_;
+ wire _08274_;
+ wire _08275_;
+ wire _08276_;
+ wire _08277_;
+ wire _08278_;
+ wire _08279_;
+ wire _08280_;
+ wire _08281_;
+ wire _08282_;
+ wire _08283_;
+ wire _08284_;
+ wire _08285_;
+ wire _08286_;
+ wire _08287_;
+ wire _08288_;
+ wire _08289_;
+ wire _08290_;
+ wire _08291_;
+ wire _08292_;
+ wire _08293_;
+ wire _08294_;
+ wire _08295_;
+ wire _08296_;
+ wire _08297_;
+ wire _08298_;
+ wire _08299_;
+ wire _08300_;
+ wire _08301_;
+ wire _08302_;
+ wire _08303_;
+ wire _08304_;
+ wire _08305_;
+ wire _08306_;
+ wire _08307_;
+ wire _08308_;
+ wire _08309_;
+ wire _08310_;
+ wire _08311_;
+ wire _08312_;
+ wire _08313_;
+ wire _08314_;
+ wire _08315_;
+ wire _08316_;
+ wire _08317_;
+ wire _08318_;
+ wire _08319_;
+ wire _08320_;
+ wire _08321_;
+ wire _08322_;
+ wire _08323_;
+ wire _08324_;
+ wire _08325_;
+ wire _08326_;
+ wire _08327_;
+ wire _08328_;
+ wire _08329_;
+ wire _08330_;
+ wire _08331_;
+ wire _08332_;
+ wire _08333_;
+ wire _08334_;
+ wire _08335_;
+ wire _08336_;
+ wire _08337_;
+ wire _08338_;
+ wire _08339_;
+ wire _08340_;
+ wire _08341_;
+ wire _08342_;
+ wire _08343_;
+ wire _08344_;
+ wire _08345_;
+ wire _08346_;
+ wire _08347_;
+ wire _08348_;
+ wire _08349_;
+ wire _08350_;
+ wire _08351_;
+ wire _08352_;
+ wire _08353_;
+ wire _08354_;
+ wire _08355_;
+ wire _08356_;
+ wire _08357_;
+ wire _08358_;
+ wire _08359_;
+ wire _08360_;
+ wire _08361_;
+ wire _08362_;
+ wire _08363_;
+ wire _08364_;
+ wire _08365_;
+ wire _08366_;
+ wire _08367_;
+ wire _08368_;
+ wire _08369_;
+ wire _08370_;
+ wire _08371_;
+ wire _08372_;
+ wire _08373_;
+ wire _08374_;
+ wire _08375_;
+ wire _08376_;
+ wire _08377_;
+ wire _08378_;
+ wire _08379_;
+ wire _08380_;
+ wire _08381_;
+ wire _08382_;
+ wire _08383_;
+ wire _08384_;
+ wire _08385_;
+ wire _08386_;
+ wire _08387_;
+ wire _08388_;
+ wire _08389_;
+ wire _08390_;
+ wire _08391_;
+ wire _08392_;
+ wire _08393_;
+ wire _08394_;
+ wire _08395_;
+ wire _08396_;
+ wire _08397_;
+ wire _08398_;
+ wire _08399_;
+ wire _08400_;
+ wire _08401_;
+ wire _08402_;
+ wire _08403_;
+ wire _08404_;
+ wire _08405_;
+ wire _08406_;
+ wire _08407_;
+ wire _08408_;
+ wire _08409_;
+ wire _08410_;
+ wire _08411_;
+ wire _08412_;
+ wire _08413_;
+ wire _08414_;
+ wire _08415_;
+ wire _08416_;
+ wire _08417_;
+ wire _08418_;
+ wire _08419_;
+ wire _08420_;
+ wire _08421_;
+ wire _08422_;
+ wire _08423_;
+ wire _08424_;
+ wire _08425_;
+ wire _08426_;
+ wire _08427_;
+ wire _08428_;
+ wire _08429_;
+ wire _08430_;
+ wire _08431_;
+ wire _08432_;
+ wire _08433_;
+ wire _08434_;
+ wire _08435_;
+ wire _08436_;
+ wire _08437_;
+ wire _08438_;
+ wire _08439_;
+ wire _08440_;
+ wire _08441_;
+ wire _08442_;
+ wire _08443_;
+ wire _08444_;
+ wire _08445_;
+ wire _08446_;
+ wire _08447_;
+ wire _08448_;
+ wire _08449_;
+ wire _08450_;
+ wire _08451_;
+ wire _08452_;
+ wire _08453_;
+ wire _08454_;
+ wire _08455_;
+ wire _08456_;
+ wire _08457_;
+ wire _08458_;
+ wire _08459_;
+ wire _08460_;
+ wire _08461_;
+ wire _08462_;
+ wire _08463_;
+ wire _08464_;
+ wire _08465_;
+ wire _08466_;
+ wire _08467_;
+ wire _08468_;
+ wire _08469_;
+ wire _08470_;
+ wire _08471_;
+ wire _08472_;
+ wire _08473_;
+ wire _08474_;
+ wire _08475_;
+ wire _08476_;
+ wire _08477_;
+ wire _08478_;
+ wire _08479_;
+ wire _08480_;
+ wire _08481_;
+ wire _08482_;
+ wire _08483_;
+ wire _08484_;
+ wire _08485_;
+ wire _08486_;
+ wire _08487_;
+ wire _08488_;
+ wire _08489_;
+ wire _08490_;
+ wire _08491_;
+ wire _08492_;
+ wire _08493_;
+ wire _08494_;
+ wire _08495_;
+ wire _08496_;
+ wire _08497_;
+ wire _08498_;
+ wire _08499_;
+ wire _08500_;
+ wire _08501_;
+ wire _08502_;
+ wire _08503_;
+ wire _08504_;
+ wire _08505_;
+ wire _08506_;
+ wire _08507_;
+ wire _08508_;
+ wire _08509_;
+ wire _08510_;
+ wire _08511_;
+ wire _08512_;
+ wire _08513_;
+ wire _08514_;
+ wire _08515_;
+ wire _08516_;
+ wire _08517_;
+ wire _08518_;
+ wire _08519_;
+ wire _08520_;
+ wire _08521_;
+ wire _08522_;
+ wire _08523_;
+ wire _08524_;
+ wire _08525_;
+ wire _08526_;
+ wire _08527_;
+ wire _08528_;
+ wire _08529_;
+ wire _08530_;
+ wire _08531_;
+ wire _08532_;
+ wire _08533_;
+ wire _08534_;
+ wire _08535_;
+ wire _08536_;
+ wire _08537_;
+ wire _08538_;
+ wire _08539_;
+ wire _08540_;
+ wire _08541_;
+ wire _08542_;
+ wire _08543_;
+ wire _08544_;
+ wire _08545_;
+ wire _08546_;
+ wire _08547_;
+ wire _08548_;
+ wire _08549_;
+ wire _08550_;
+ wire _08551_;
+ wire _08552_;
+ wire _08553_;
+ wire _08554_;
+ wire _08555_;
+ wire _08556_;
+ wire _08557_;
+ wire _08558_;
+ wire _08559_;
+ wire _08560_;
+ wire _08561_;
+ wire _08562_;
+ wire _08563_;
+ wire _08564_;
+ wire _08565_;
+ wire _08566_;
+ wire _08567_;
+ wire _08568_;
+ wire _08569_;
+ wire _08570_;
+ wire _08571_;
+ wire _08572_;
+ wire _08573_;
+ wire _08574_;
+ wire _08575_;
+ wire _08576_;
+ wire _08577_;
+ wire _08578_;
+ wire _08579_;
+ wire _08580_;
+ wire _08581_;
+ wire _08582_;
+ wire _08583_;
+ wire _08584_;
+ wire _08585_;
+ wire _08586_;
+ wire _08587_;
+ wire _08588_;
+ wire _08589_;
+ wire _08590_;
+ wire _08591_;
+ wire _08592_;
+ wire _08593_;
+ wire _08594_;
+ wire _08595_;
+ wire _08596_;
+ wire _08597_;
+ wire _08598_;
+ wire _08599_;
+ wire _08600_;
+ wire _08601_;
+ wire _08602_;
+ wire _08603_;
+ wire _08604_;
+ wire _08605_;
+ wire _08606_;
+ wire _08607_;
+ wire _08608_;
+ wire _08609_;
+ wire _08610_;
+ wire _08611_;
+ wire _08612_;
+ wire _08613_;
+ wire _08614_;
+ wire _08615_;
+ wire _08616_;
+ wire _08617_;
+ wire _08618_;
+ wire _08619_;
+ wire _08620_;
+ wire _08621_;
+ wire _08622_;
+ wire _08623_;
+ wire _08624_;
+ wire _08625_;
+ wire _08626_;
+ wire _08627_;
+ wire _08628_;
+ wire _08629_;
+ wire _08630_;
+ wire _08631_;
+ wire _08632_;
+ wire _08633_;
+ wire _08634_;
+ wire _08635_;
+ wire _08636_;
+ wire _08637_;
+ wire _08638_;
+ wire _08639_;
+ wire _08640_;
+ wire _08641_;
+ wire _08642_;
+ wire _08643_;
+ wire _08644_;
+ wire _08645_;
+ wire _08646_;
+ wire _08647_;
+ wire _08648_;
+ wire _08649_;
+ wire _08650_;
+ wire _08651_;
+ wire _08652_;
+ wire _08653_;
+ wire _08654_;
+ wire _08655_;
+ wire _08656_;
+ wire _08657_;
+ wire _08658_;
+ wire _08659_;
+ wire _08660_;
+ wire _08661_;
+ wire _08662_;
+ wire _08663_;
+ wire _08664_;
+ wire _08665_;
+ wire _08666_;
+ wire _08667_;
+ wire _08668_;
+ wire _08669_;
+ wire _08670_;
+ wire _08671_;
+ wire _08672_;
+ wire _08673_;
+ wire _08674_;
+ wire _08675_;
+ wire _08676_;
+ wire _08677_;
+ wire _08678_;
+ wire _08679_;
+ wire _08680_;
+ wire _08681_;
+ wire _08682_;
+ wire _08683_;
+ wire _08684_;
+ wire _08685_;
+ wire _08686_;
+ wire _08687_;
+ wire _08688_;
+ wire _08689_;
+ wire _08690_;
+ wire _08691_;
+ wire _08692_;
+ wire _08693_;
+ wire _08694_;
+ wire _08695_;
+ wire _08696_;
+ wire _08697_;
+ wire _08698_;
+ wire _08699_;
+ wire _08700_;
+ wire _08701_;
+ wire _08702_;
+ wire _08703_;
+ wire _08704_;
+ wire _08705_;
+ wire _08706_;
+ wire _08707_;
+ wire _08708_;
+ wire _08709_;
+ wire _08710_;
+ wire _08711_;
+ wire _08712_;
+ wire _08713_;
+ wire _08714_;
+ wire _08715_;
+ wire _08716_;
+ wire _08717_;
+ wire _08718_;
+ wire _08719_;
+ wire _08720_;
+ wire _08721_;
+ wire _08722_;
+ wire _08723_;
+ wire _08724_;
+ wire _08725_;
+ wire _08726_;
+ wire _08727_;
+ wire _08728_;
+ wire _08729_;
+ wire _08730_;
+ wire _08731_;
+ wire _08732_;
+ wire _08733_;
+ wire _08734_;
+ wire _08735_;
+ wire _08736_;
+ wire _08737_;
+ wire _08738_;
+ wire _08739_;
+ wire _08740_;
+ wire _08741_;
+ wire _08742_;
+ wire _08743_;
+ wire _08744_;
+ wire _08745_;
+ wire _08746_;
+ wire _08747_;
+ wire _08748_;
+ wire _08749_;
+ wire _08750_;
+ wire _08751_;
+ wire _08752_;
+ wire _08753_;
+ wire _08754_;
+ wire _08755_;
+ wire _08756_;
+ wire _08757_;
+ wire _08758_;
+ wire _08759_;
+ wire _08760_;
+ wire _08761_;
+ wire _08762_;
+ wire _08763_;
+ wire _08764_;
+ wire _08765_;
+ wire _08766_;
+ wire _08767_;
+ wire _08768_;
+ wire _08769_;
+ wire _08770_;
+ wire _08771_;
+ wire _08772_;
+ wire _08773_;
+ wire _08774_;
+ wire _08775_;
+ wire _08776_;
+ wire _08777_;
+ wire _08778_;
+ wire _08779_;
+ wire _08780_;
+ wire _08781_;
+ wire _08782_;
+ wire _08783_;
+ wire _08784_;
+ wire _08785_;
+ wire _08786_;
+ wire _08787_;
+ wire _08788_;
+ wire _08789_;
+ wire _08790_;
+ wire _08791_;
+ wire _08792_;
+ wire _08793_;
+ wire _08794_;
+ wire _08795_;
+ wire _08796_;
+ wire _08797_;
+ wire _08798_;
+ wire _08799_;
+ wire _08800_;
+ wire _08801_;
+ wire _08802_;
+ wire _08803_;
+ wire _08804_;
+ wire _08805_;
+ wire _08806_;
+ wire _08807_;
+ wire _08808_;
+ wire _08809_;
+ wire _08810_;
+ wire _08811_;
+ wire _08812_;
+ wire _08813_;
+ wire _08814_;
+ wire _08815_;
+ wire _08816_;
+ wire _08817_;
+ wire _08818_;
+ wire _08819_;
+ wire _08820_;
+ wire _08821_;
+ wire _08822_;
+ wire _08823_;
+ wire _08824_;
+ wire _08825_;
+ wire _08826_;
+ wire _08827_;
+ wire _08828_;
+ wire _08829_;
+ wire _08830_;
+ wire _08831_;
+ wire _08832_;
+ wire _08833_;
+ wire _08834_;
+ wire _08835_;
+ wire _08836_;
+ wire _08837_;
+ wire _08838_;
+ wire _08839_;
+ wire _08840_;
+ wire _08841_;
+ wire _08842_;
+ wire _08843_;
+ wire _08844_;
+ wire _08845_;
+ wire _08846_;
+ wire _08847_;
+ wire _08848_;
+ wire _08849_;
+ wire _08850_;
+ wire _08851_;
+ wire _08852_;
+ wire _08853_;
+ wire _08854_;
+ wire _08855_;
+ wire _08856_;
+ wire _08857_;
+ wire _08858_;
+ wire _08859_;
+ wire _08860_;
+ wire _08861_;
+ wire _08862_;
+ wire _08863_;
+ wire _08864_;
+ wire _08865_;
+ wire _08866_;
+ wire _08867_;
+ wire _08868_;
+ wire _08869_;
+ wire _08870_;
+ wire _08871_;
+ wire _08872_;
+ wire _08873_;
+ wire _08874_;
+ wire _08875_;
+ wire _08876_;
+ wire _08877_;
+ wire _08878_;
+ wire _08879_;
+ wire _08880_;
+ wire _08881_;
+ wire _08882_;
+ wire _08883_;
+ wire _08884_;
+ wire _08885_;
+ wire _08886_;
+ wire _08887_;
+ wire _08888_;
+ wire _08889_;
+ wire _08890_;
+ wire _08891_;
+ wire _08892_;
+ wire _08893_;
+ wire _08894_;
+ wire _08895_;
+ wire _08896_;
+ wire _08897_;
+ wire _08898_;
+ wire _08899_;
+ wire _08900_;
+ wire _08901_;
+ wire _08902_;
+ wire _08903_;
+ wire _08904_;
+ wire _08905_;
+ wire _08906_;
+ wire _08907_;
+ wire _08908_;
+ wire _08909_;
+ wire _08910_;
+ wire _08911_;
+ wire _08912_;
+ wire _08913_;
+ wire _08914_;
+ wire _08915_;
+ wire _08916_;
+ wire _08917_;
+ wire _08918_;
+ wire _08919_;
+ wire _08920_;
+ wire _08921_;
+ wire _08922_;
+ wire _08923_;
+ wire _08924_;
+ wire _08925_;
+ wire _08926_;
+ wire _08927_;
+ wire _08928_;
+ wire _08929_;
+ wire _08930_;
+ wire _08931_;
+ wire _08932_;
+ wire _08933_;
+ wire _08934_;
+ wire _08935_;
+ wire _08936_;
+ wire _08937_;
+ wire _08938_;
+ wire _08939_;
+ wire _08940_;
+ wire _08941_;
+ wire _08942_;
+ wire _08943_;
+ wire _08944_;
+ wire _08945_;
+ wire _08946_;
+ wire _08947_;
+ wire _08948_;
+ wire _08949_;
+ wire _08950_;
+ wire _08951_;
+ wire _08952_;
+ wire _08953_;
+ wire _08954_;
+ wire _08955_;
+ wire _08956_;
+ wire _08957_;
+ wire _08958_;
+ wire _08959_;
+ wire _08960_;
+ wire _08961_;
+ wire _08962_;
+ wire _08963_;
+ wire _08964_;
+ wire _08965_;
+ wire _08966_;
+ wire _08967_;
+ wire _08968_;
+ wire _08969_;
+ wire _08970_;
+ wire _08971_;
+ wire _08972_;
+ wire _08973_;
+ wire _08974_;
+ wire _08975_;
+ wire _08976_;
+ wire _08977_;
+ wire _08978_;
+ wire _08979_;
+ wire _08980_;
+ wire _08981_;
+ wire _08982_;
+ wire _08983_;
+ wire _08984_;
+ wire _08985_;
+ wire _08986_;
+ wire _08987_;
+ wire _08988_;
+ wire _08989_;
+ wire _08990_;
+ wire _08991_;
+ wire _08992_;
+ wire _08993_;
+ wire _08994_;
+ wire _08995_;
+ wire _08996_;
+ wire _08997_;
+ wire _08998_;
+ wire _08999_;
+ wire _09000_;
+ wire _09001_;
+ wire _09002_;
+ wire _09003_;
+ wire _09004_;
+ wire _09005_;
+ wire _09006_;
+ wire _09007_;
+ wire _09008_;
+ wire _09009_;
+ wire _09010_;
+ wire _09011_;
+ wire _09012_;
+ wire _09013_;
+ wire _09014_;
+ wire _09015_;
+ wire _09016_;
+ wire _09017_;
+ wire _09018_;
+ wire _09019_;
+ wire _09020_;
+ wire _09021_;
+ wire _09022_;
+ wire _09023_;
+ wire _09024_;
+ wire _09025_;
+ wire _09026_;
+ wire _09027_;
+ wire _09028_;
+ wire _09029_;
+ wire _09030_;
+ wire _09031_;
+ wire _09032_;
+ wire _09033_;
+ wire _09034_;
+ wire _09035_;
+ wire _09036_;
+ wire _09037_;
+ wire _09038_;
+ wire _09039_;
+ wire _09040_;
+ wire _09041_;
+ wire _09042_;
+ wire _09043_;
+ wire _09044_;
+ wire _09045_;
+ wire _09046_;
+ wire _09047_;
+ wire _09048_;
+ wire _09049_;
+ wire _09050_;
+ wire _09051_;
+ wire _09052_;
+ wire _09053_;
+ wire _09054_;
+ wire _09055_;
+ wire _09056_;
+ wire _09057_;
+ wire _09058_;
+ wire _09059_;
+ wire _09060_;
+ wire _09061_;
+ wire _09062_;
+ wire _09063_;
+ wire _09064_;
+ wire _09065_;
+ wire _09066_;
+ wire _09067_;
+ wire _09068_;
+ wire _09069_;
+ wire _09070_;
+ wire _09071_;
+ wire _09072_;
+ wire _09073_;
+ wire _09074_;
+ wire _09075_;
+ wire _09076_;
+ wire _09077_;
+ wire _09078_;
+ wire _09079_;
+ wire _09080_;
+ wire _09081_;
+ wire _09082_;
+ wire _09083_;
+ wire _09084_;
+ wire _09085_;
+ wire _09086_;
+ wire _09087_;
+ wire _09088_;
+ wire _09089_;
+ wire _09090_;
+ wire _09091_;
+ wire _09092_;
+ wire _09093_;
+ wire _09094_;
+ wire _09095_;
+ wire _09096_;
+ wire _09097_;
+ wire _09098_;
+ wire _09099_;
+ wire _09100_;
+ wire _09101_;
+ wire _09102_;
+ wire _09103_;
+ wire _09104_;
+ wire _09105_;
+ wire _09106_;
+ wire _09107_;
+ wire _09108_;
+ wire _09109_;
+ wire _09110_;
+ wire _09111_;
+ wire _09112_;
+ wire _09113_;
+ wire _09114_;
+ wire _09115_;
+ wire _09116_;
+ wire _09117_;
+ wire _09118_;
+ wire _09119_;
+ wire _09120_;
+ wire _09121_;
+ wire _09122_;
+ wire _09123_;
+ wire _09124_;
+ wire _09125_;
+ wire _09126_;
+ wire _09127_;
+ wire _09128_;
+ wire _09129_;
+ wire _09130_;
+ wire _09131_;
+ wire _09132_;
+ wire _09133_;
+ wire _09134_;
+ wire _09135_;
+ wire _09136_;
+ wire _09137_;
+ wire _09138_;
+ wire _09139_;
+ wire _09140_;
+ wire _09141_;
+ wire _09142_;
+ wire _09143_;
+ wire _09144_;
+ wire _09145_;
+ wire _09146_;
+ wire _09147_;
+ wire _09148_;
+ wire _09149_;
+ wire _09150_;
+ wire _09151_;
+ wire _09152_;
+ wire _09153_;
+ wire _09154_;
+ wire _09155_;
+ wire _09156_;
+ wire _09157_;
+ wire _09158_;
+ wire _09159_;
+ wire _09160_;
+ wire _09161_;
+ wire _09162_;
+ wire _09163_;
+ wire _09164_;
+ wire _09165_;
+ wire _09166_;
+ wire _09167_;
+ wire _09168_;
+ wire _09169_;
+ wire _09170_;
+ wire _09171_;
+ wire _09172_;
+ wire _09173_;
+ wire _09174_;
+ wire _09175_;
+ wire _09176_;
+ wire _09177_;
+ wire _09178_;
+ wire _09179_;
+ wire _09180_;
+ wire _09181_;
+ wire _09182_;
+ wire _09183_;
+ wire _09184_;
+ wire _09185_;
+ wire _09186_;
+ wire _09187_;
+ wire _09188_;
+ wire _09189_;
+ wire _09190_;
+ wire _09191_;
+ wire _09192_;
+ wire _09193_;
+ wire _09194_;
+ wire _09195_;
+ wire _09196_;
+ wire _09197_;
+ wire _09198_;
+ wire _09199_;
+ wire _09200_;
+ wire _09201_;
+ wire _09202_;
+ wire _09203_;
+ wire _09204_;
+ wire _09205_;
+ wire _09206_;
+ wire _09207_;
+ wire _09208_;
+ wire _09209_;
+ wire _09210_;
+ wire _09211_;
+ wire _09212_;
+ wire _09213_;
+ wire _09214_;
+ wire _09215_;
+ wire _09216_;
+ wire _09217_;
+ wire _09218_;
+ wire _09219_;
+ wire _09220_;
+ wire _09221_;
+ wire _09222_;
+ wire _09223_;
+ wire _09224_;
+ wire _09225_;
+ wire _09226_;
+ wire _09227_;
+ wire _09228_;
+ wire _09229_;
+ wire _09230_;
+ wire _09231_;
+ wire _09232_;
+ wire _09233_;
+ wire _09234_;
+ wire _09235_;
+ wire _09236_;
+ wire _09237_;
+ wire _09238_;
+ wire _09239_;
+ wire _09240_;
+ wire _09241_;
+ wire _09242_;
+ wire _09243_;
+ wire _09244_;
+ wire _09245_;
+ wire _09246_;
+ wire _09247_;
+ wire _09248_;
+ wire _09249_;
+ wire _09250_;
+ wire _09251_;
+ wire _09252_;
+ wire _09253_;
+ wire _09254_;
+ wire _09255_;
+ wire _09256_;
+ wire _09257_;
+ wire _09258_;
+ wire _09259_;
+ wire _09260_;
+ wire _09261_;
+ wire _09262_;
+ wire _09263_;
+ wire _09264_;
+ wire _09265_;
+ wire _09266_;
+ wire _09267_;
+ wire _09268_;
+ wire _09269_;
+ wire _09270_;
+ wire _09271_;
+ wire _09272_;
+ wire _09273_;
+ wire _09274_;
+ wire _09275_;
+ wire _09276_;
+ wire _09277_;
+ wire _09278_;
+ wire _09279_;
+ wire _09280_;
+ wire _09281_;
+ wire _09282_;
+ wire _09283_;
+ wire _09284_;
+ wire _09285_;
+ wire _09286_;
+ wire _09287_;
+ wire _09288_;
+ wire _09289_;
+ wire _09290_;
+ wire _09291_;
+ wire _09292_;
+ wire _09293_;
+ wire _09294_;
+ wire _09295_;
+ wire _09296_;
+ wire _09297_;
+ wire _09298_;
+ wire _09299_;
+ wire _09300_;
+ wire _09301_;
+ wire _09302_;
+ wire _09303_;
+ wire _09304_;
+ wire _09305_;
+ wire _09306_;
+ wire _09307_;
+ wire _09308_;
+ wire _09309_;
+ wire _09310_;
+ wire _09311_;
+ wire _09312_;
+ wire _09313_;
+ wire _09314_;
+ wire _09315_;
+ wire _09316_;
+ wire _09317_;
+ wire _09318_;
+ wire _09319_;
+ wire _09320_;
+ wire _09321_;
+ wire _09322_;
+ wire _09323_;
+ wire _09324_;
+ wire _09325_;
+ wire _09326_;
+ wire _09327_;
+ wire _09328_;
+ wire _09329_;
+ wire _09330_;
+ wire _09331_;
+ wire _09332_;
+ wire _09333_;
+ wire _09334_;
+ wire _09335_;
+ wire _09336_;
+ wire _09337_;
+ wire _09338_;
+ wire _09339_;
+ wire _09340_;
+ wire _09341_;
+ wire _09342_;
+ wire _09343_;
+ wire _09344_;
+ wire _09345_;
+ wire _09346_;
+ wire _09347_;
+ wire _09348_;
+ wire _09349_;
+ wire _09350_;
+ wire _09351_;
+ wire _09352_;
+ wire _09353_;
+ wire _09354_;
+ wire _09355_;
+ wire _09356_;
+ wire _09357_;
+ wire _09358_;
+ wire _09359_;
+ wire _09360_;
+ wire _09361_;
+ wire _09362_;
+ wire _09363_;
+ wire _09364_;
+ wire _09365_;
+ wire _09366_;
+ wire _09367_;
+ wire _09368_;
+ wire _09369_;
+ wire _09370_;
+ wire _09371_;
+ wire _09372_;
+ wire _09373_;
+ wire _09374_;
+ wire _09375_;
+ wire _09376_;
+ wire _09377_;
+ wire _09378_;
+ wire _09379_;
+ wire _09380_;
+ wire _09381_;
+ wire _09382_;
+ wire _09383_;
+ wire _09384_;
+ wire _09385_;
+ wire _09386_;
+ wire _09387_;
+ wire _09388_;
+ wire _09389_;
+ wire _09390_;
+ wire _09391_;
+ wire _09392_;
+ wire _09393_;
+ wire _09394_;
+ wire _09395_;
+ wire _09396_;
+ wire _09397_;
+ wire _09398_;
+ wire _09399_;
+ wire _09400_;
+ wire _09401_;
+ wire _09402_;
+ wire _09403_;
+ wire _09404_;
+ wire _09405_;
+ wire _09406_;
+ wire _09407_;
+ wire _09408_;
+ wire _09409_;
+ wire _09410_;
+ wire _09411_;
+ wire _09412_;
+ wire _09413_;
+ wire _09414_;
+ wire _09415_;
+ wire _09416_;
+ wire _09417_;
+ wire _09418_;
+ wire _09419_;
+ wire _09420_;
+ wire _09421_;
+ wire _09422_;
+ wire _09423_;
+ wire _09424_;
+ wire _09425_;
+ wire _09426_;
+ wire _09427_;
+ wire _09428_;
+ wire _09429_;
+ wire _09430_;
+ wire _09431_;
+ wire _09432_;
+ wire _09433_;
+ wire _09434_;
+ wire _09435_;
+ wire _09436_;
+ wire _09437_;
+ wire _09438_;
+ wire _09439_;
+ wire _09440_;
+ wire _09441_;
+ wire _09442_;
+ wire _09443_;
+ wire _09444_;
+ wire _09445_;
+ wire _09446_;
+ wire _09447_;
+ wire _09448_;
+ wire _09449_;
+ wire _09450_;
+ wire _09451_;
+ wire _09452_;
+ wire _09453_;
+ wire _09454_;
+ wire _09455_;
+ wire _09456_;
+ wire _09457_;
+ wire _09458_;
+ wire _09459_;
+ wire _09460_;
+ wire _09461_;
+ wire _09462_;
+ wire _09463_;
+ wire _09464_;
+ wire _09465_;
+ wire _09466_;
+ wire _09467_;
+ wire _09468_;
+ wire _09469_;
+ wire _09470_;
+ wire _09471_;
+ wire _09472_;
+ wire _09473_;
+ wire _09474_;
+ wire _09475_;
+ wire _09476_;
+ wire _09477_;
+ wire _09478_;
+ wire _09479_;
+ wire _09480_;
+ wire _09481_;
+ wire _09482_;
+ wire _09483_;
+ wire _09484_;
+ wire _09485_;
+ wire _09486_;
+ wire _09487_;
+ wire _09488_;
+ wire _09489_;
+ wire _09490_;
+ wire _09491_;
+ wire _09492_;
+ wire _09493_;
+ wire _09494_;
+ wire _09495_;
+ wire _09496_;
+ wire _09497_;
+ wire _09498_;
+ wire _09499_;
+ wire _09500_;
+ wire _09501_;
+ wire _09502_;
+ wire _09503_;
+ wire _09504_;
+ wire _09505_;
+ wire _09506_;
+ wire _09507_;
+ wire _09508_;
+ wire _09509_;
+ wire _09510_;
+ wire _09511_;
+ wire _09512_;
+ wire _09513_;
+ wire _09514_;
+ wire _09515_;
+ wire _09516_;
+ wire _09517_;
+ wire _09518_;
+ wire _09519_;
+ wire _09520_;
+ wire _09521_;
+ wire _09522_;
+ wire _09523_;
+ wire _09524_;
+ wire _09525_;
+ wire _09526_;
+ wire _09527_;
+ wire _09528_;
+ wire _09529_;
+ wire _09530_;
+ wire _09531_;
+ wire _09532_;
+ wire _09533_;
+ wire _09534_;
+ wire _09535_;
+ wire _09536_;
+ wire _09537_;
+ wire _09538_;
+ wire _09539_;
+ wire _09540_;
+ wire _09541_;
+ wire _09542_;
+ wire _09543_;
+ wire _09544_;
+ wire _09545_;
+ wire _09546_;
+ wire _09547_;
+ wire _09548_;
+ wire _09549_;
+ wire _09550_;
+ wire _09551_;
+ wire _09552_;
+ wire _09553_;
+ wire _09554_;
+ wire _09555_;
+ wire _09556_;
+ wire _09557_;
+ wire _09558_;
+ wire _09559_;
+ wire _09560_;
+ wire _09561_;
+ wire _09562_;
+ wire _09563_;
+ wire _09564_;
+ wire _09565_;
+ wire _09566_;
+ wire _09567_;
+ wire _09568_;
+ wire _09569_;
+ wire _09570_;
+ wire _09571_;
+ wire _09572_;
+ wire _09573_;
+ wire _09574_;
+ wire _09575_;
+ wire _09576_;
+ wire _09577_;
+ wire _09578_;
+ wire _09579_;
+ wire _09580_;
+ wire _09581_;
+ wire _09582_;
+ wire _09583_;
+ wire _09584_;
+ wire _09585_;
+ wire _09586_;
+ wire _09587_;
+ wire _09588_;
+ wire _09589_;
+ wire _09590_;
+ wire _09591_;
+ wire _09592_;
+ wire _09593_;
+ wire _09594_;
+ wire _09595_;
+ wire _09596_;
+ wire _09597_;
+ wire _09598_;
+ wire _09599_;
+ wire _09600_;
+ wire _09601_;
+ wire _09602_;
+ wire _09603_;
+ wire _09604_;
+ wire _09605_;
+ wire _09606_;
+ wire _09607_;
+ wire _09608_;
+ wire _09609_;
+ wire _09610_;
+ wire _09611_;
+ wire _09612_;
+ wire _09613_;
+ wire _09614_;
+ wire _09615_;
+ wire _09616_;
+ wire _09617_;
+ wire _09618_;
+ wire _09619_;
+ wire _09620_;
+ wire _09621_;
+ wire _09622_;
+ wire _09623_;
+ wire _09624_;
+ wire _09625_;
+ wire _09626_;
+ wire _09627_;
+ wire _09628_;
+ wire _09629_;
+ wire _09630_;
+ wire _09631_;
+ wire _09632_;
+ wire _09633_;
+ wire _09634_;
+ wire _09635_;
+ wire _09636_;
+ wire _09637_;
+ wire _09638_;
+ wire _09639_;
+ wire _09640_;
+ wire _09641_;
+ wire _09642_;
+ wire _09643_;
+ wire _09644_;
+ wire _09645_;
+ wire _09646_;
+ wire _09647_;
+ wire _09648_;
+ wire _09649_;
+ wire _09650_;
+ wire _09651_;
+ wire _09652_;
+ wire _09653_;
+ wire _09654_;
+ wire _09655_;
+ wire _09656_;
+ wire _09657_;
+ wire _09658_;
+ wire _09659_;
+ wire _09660_;
+ wire _09661_;
+ wire _09662_;
+ wire _09663_;
+ wire _09664_;
+ wire _09665_;
+ wire _09666_;
+ wire _09667_;
+ wire _09668_;
+ wire _09669_;
+ wire _09670_;
+ wire _09671_;
+ wire _09672_;
+ wire _09673_;
+ wire _09674_;
+ wire _09675_;
+ wire _09676_;
+ wire _09677_;
+ wire _09678_;
+ wire _09679_;
+ wire _09680_;
+ wire _09681_;
+ wire _09682_;
+ wire _09683_;
+ wire _09684_;
+ wire _09685_;
+ wire _09686_;
+ wire _09687_;
+ wire _09688_;
+ wire _09689_;
+ wire _09690_;
+ wire _09691_;
+ wire _09692_;
+ wire _09693_;
+ wire _09694_;
+ wire _09695_;
+ wire _09696_;
+ wire _09697_;
+ wire _09698_;
+ wire _09699_;
+ wire _09700_;
+ wire _09701_;
+ wire _09702_;
+ wire _09703_;
+ wire _09704_;
+ wire _09705_;
+ wire _09706_;
+ wire _09707_;
+ wire _09708_;
+ wire _09709_;
+ wire _09710_;
+ wire _09711_;
+ wire _09712_;
+ wire _09713_;
+ wire _09714_;
+ wire _09715_;
+ wire _09716_;
+ wire _09717_;
+ wire _09718_;
+ wire _09719_;
+ wire _09720_;
+ wire _09721_;
+ wire _09722_;
+ wire _09723_;
+ wire _09724_;
+ wire _09725_;
+ wire _09726_;
+ wire _09727_;
+ wire _09728_;
+ wire _09729_;
+ wire _09730_;
+ wire _09731_;
+ wire _09732_;
+ wire _09733_;
+ wire _09734_;
+ wire _09735_;
+ wire _09736_;
+ wire _09737_;
+ wire _09738_;
+ wire _09739_;
+ wire _09740_;
+ wire _09741_;
+ wire _09742_;
+ wire _09743_;
+ wire _09744_;
+ wire _09745_;
+ wire _09746_;
+ wire _09747_;
+ wire _09748_;
+ wire _09749_;
+ wire _09750_;
+ wire _09751_;
+ wire _09752_;
+ wire _09753_;
+ wire _09754_;
+ wire _09755_;
+ wire _09756_;
+ wire _09757_;
+ wire _09758_;
+ wire _09759_;
+ wire _09760_;
+ wire _09761_;
+ wire _09762_;
+ wire _09763_;
+ wire _09764_;
+ wire _09765_;
+ wire _09766_;
+ wire _09767_;
+ wire _09768_;
+ wire _09769_;
+ wire _09770_;
+ wire _09771_;
+ wire _09772_;
+ wire _09773_;
+ wire _09774_;
+ wire _09775_;
+ wire _09776_;
+ wire _09777_;
+ wire _09778_;
+ wire _09779_;
+ wire _09780_;
+ wire _09781_;
+ wire _09782_;
+ wire _09783_;
+ wire _09784_;
+ wire _09785_;
+ wire _09786_;
+ wire _09787_;
+ wire _09788_;
+ wire _09789_;
+ wire _09790_;
+ wire _09791_;
+ wire _09792_;
+ wire _09793_;
+ wire _09794_;
+ wire _09795_;
+ wire _09796_;
+ wire _09797_;
+ wire _09798_;
+ wire _09799_;
+ wire _09800_;
+ wire _09801_;
+ wire _09802_;
+ wire _09803_;
+ wire _09804_;
+ wire _09805_;
+ wire _09806_;
+ wire _09807_;
+ wire _09808_;
+ wire _09809_;
+ wire _09810_;
+ wire _09811_;
+ wire _09812_;
+ wire _09813_;
+ wire _09814_;
+ wire _09815_;
+ wire _09816_;
+ wire _09817_;
+ wire _09818_;
+ wire _09819_;
+ wire _09820_;
+ wire _09821_;
+ wire _09822_;
+ wire _09823_;
+ wire _09824_;
+ wire _09825_;
+ wire _09826_;
+ wire _09827_;
+ wire _09828_;
+ wire _09829_;
+ wire _09830_;
+ wire _09831_;
+ wire _09832_;
+ wire _09833_;
+ wire _09834_;
+ wire _09835_;
+ wire _09836_;
+ wire _09837_;
+ wire _09838_;
+ wire _09839_;
+ wire _09840_;
+ wire _09841_;
+ wire _09842_;
+ wire _09843_;
+ wire _09844_;
+ wire _09845_;
+ wire _09846_;
+ wire _09847_;
+ wire _09848_;
+ wire _09849_;
+ wire _09850_;
+ wire _09851_;
+ wire _09852_;
+ wire _09853_;
+ wire _09854_;
+ wire _09855_;
+ wire _09856_;
+ wire _09857_;
+ wire _09858_;
+ wire _09859_;
+ wire _09860_;
+ wire _09861_;
+ wire _09862_;
+ wire _09863_;
+ wire _09864_;
+ wire _09865_;
+ wire _09866_;
+ wire _09867_;
+ wire _09868_;
+ wire _09869_;
+ wire _09870_;
+ wire _09871_;
+ wire _09872_;
+ wire _09873_;
+ wire _09874_;
+ wire _09875_;
+ wire _09876_;
+ wire _09877_;
+ wire _09878_;
+ wire _09879_;
+ wire _09880_;
+ wire _09881_;
+ wire _09882_;
+ wire _09883_;
+ wire _09884_;
+ wire _09885_;
+ wire _09886_;
+ wire _09887_;
+ wire _09888_;
+ wire _09889_;
+ wire _09890_;
+ wire _09891_;
+ wire _09892_;
+ wire _09893_;
+ wire _09894_;
+ wire _09895_;
+ wire _09896_;
+ wire _09897_;
+ wire _09898_;
+ wire _09899_;
+ wire _09900_;
+ wire _09901_;
+ wire _09902_;
+ wire _09903_;
+ wire _09904_;
+ wire _09905_;
+ wire _09906_;
+ wire _09907_;
+ wire _09908_;
+ wire _09909_;
+ wire _09910_;
+ wire _09911_;
+ wire _09912_;
+ wire _09913_;
+ wire _09914_;
+ wire _09915_;
+ wire _09916_;
+ wire _09917_;
+ wire _09918_;
+ wire _09919_;
+ wire _09920_;
+ wire _09921_;
+ wire _09922_;
+ wire _09923_;
+ wire _09924_;
+ wire _09925_;
+ wire _09926_;
+ wire _09927_;
+ wire _09928_;
+ wire _09929_;
+ wire _09930_;
+ wire _09931_;
+ wire _09932_;
+ wire _09933_;
+ wire _09934_;
+ wire _09935_;
+ wire _09936_;
+ wire _09937_;
+ wire _09938_;
+ wire _09939_;
+ wire _09940_;
+ wire _09941_;
+ wire _09942_;
+ wire _09943_;
+ wire _09944_;
+ wire _09945_;
+ wire _09946_;
+ wire _09947_;
+ wire _09948_;
+ wire _09949_;
+ wire _09950_;
+ wire _09951_;
+ wire _09952_;
+ wire _09953_;
+ wire _09954_;
+ wire _09955_;
+ wire _09956_;
+ wire _09957_;
+ wire _09958_;
+ wire _09959_;
+ wire _09960_;
+ wire _09961_;
+ wire _09962_;
+ wire _09963_;
+ wire _09964_;
+ wire _09965_;
+ wire _09966_;
+ wire _09967_;
+ wire _09968_;
+ wire _09969_;
+ wire _09970_;
+ wire _09971_;
+ wire _09972_;
+ wire _09973_;
+ wire _09974_;
+ wire _09975_;
+ wire _09976_;
+ wire _09977_;
+ wire _09978_;
+ wire _09979_;
+ wire _09980_;
+ wire _09981_;
+ wire _09982_;
+ wire _09983_;
+ wire _09984_;
+ wire _09985_;
+ wire _09986_;
+ wire _09987_;
+ wire _09988_;
+ wire _09989_;
+ wire _09990_;
+ wire _09991_;
+ wire _09992_;
+ wire _09993_;
+ wire _09994_;
+ wire _09995_;
+ wire _09996_;
+ wire _09997_;
+ wire _09998_;
+ wire _09999_;
+ wire _10000_;
+ wire _10001_;
+ wire _10002_;
+ wire _10003_;
+ wire _10004_;
+ wire _10005_;
+ wire _10006_;
+ wire _10007_;
+ wire _10008_;
+ wire _10009_;
+ wire _10010_;
+ wire _10011_;
+ wire _10012_;
+ wire _10013_;
+ wire _10014_;
+ wire _10015_;
+ wire _10016_;
+ wire _10017_;
+ wire _10018_;
+ wire _10019_;
+ wire _10020_;
+ wire _10021_;
+ wire _10022_;
+ wire _10023_;
+ wire _10024_;
+ wire _10025_;
+ wire _10026_;
+ wire _10027_;
+ wire _10028_;
+ wire _10029_;
+ wire _10030_;
+ wire _10031_;
+ wire _10032_;
+ wire _10033_;
+ wire _10034_;
+ wire _10035_;
+ wire _10036_;
+ wire _10037_;
+ wire _10038_;
+ wire _10039_;
+ wire _10040_;
+ wire _10041_;
+ wire _10042_;
+ wire _10043_;
+ wire _10044_;
+ wire _10045_;
+ wire _10046_;
+ wire _10047_;
+ wire _10048_;
+ wire _10049_;
+ wire _10050_;
+ wire _10051_;
+ wire _10052_;
+ wire _10053_;
+ wire _10054_;
+ wire _10055_;
+ wire _10056_;
+ wire _10057_;
+ wire _10058_;
+ wire _10059_;
+ wire _10060_;
+ wire _10061_;
+ wire _10062_;
+ wire _10063_;
+ wire _10064_;
+ wire _10065_;
+ wire _10066_;
+ wire _10067_;
+ wire _10068_;
+ wire _10069_;
+ wire _10070_;
+ wire _10071_;
+ wire _10072_;
+ wire _10073_;
+ wire _10074_;
+ wire _10075_;
+ wire _10076_;
+ wire _10077_;
+ wire _10078_;
+ wire _10079_;
+ wire _10080_;
+ wire _10081_;
+ wire _10082_;
+ wire _10083_;
+ wire _10084_;
+ wire _10085_;
+ wire _10086_;
+ wire _10087_;
+ wire _10088_;
+ wire _10089_;
+ wire _10090_;
+ wire _10091_;
+ wire _10092_;
+ wire _10093_;
+ wire _10094_;
+ wire _10095_;
+ wire _10096_;
+ wire _10097_;
+ wire _10098_;
+ wire _10099_;
+ wire _10100_;
+ wire _10101_;
+ wire _10102_;
+ wire _10103_;
+ wire _10104_;
+ wire _10105_;
+ wire _10106_;
+ wire _10107_;
+ wire _10108_;
+ wire _10109_;
+ wire _10110_;
+ wire _10111_;
+ wire _10112_;
+ wire _10113_;
+ wire _10114_;
+ wire _10115_;
+ wire _10116_;
+ wire _10117_;
+ wire _10118_;
+ wire _10119_;
+ wire _10120_;
+ wire _10121_;
+ wire _10122_;
+ wire _10123_;
+ wire _10124_;
+ wire _10125_;
+ wire _10126_;
+ wire _10127_;
+ wire _10128_;
+ wire _10129_;
+ wire _10130_;
+ wire _10131_;
+ wire _10132_;
+ wire _10133_;
+ wire _10134_;
+ wire _10135_;
+ wire _10136_;
+ wire _10137_;
+ wire _10138_;
+ wire _10139_;
+ wire _10140_;
+ wire _10141_;
+ wire _10142_;
+ wire _10143_;
+ wire _10144_;
+ wire _10145_;
+ wire _10146_;
+ wire _10147_;
+ wire _10148_;
+ wire _10149_;
+ wire _10150_;
+ wire _10151_;
+ wire _10152_;
+ wire _10153_;
+ wire _10154_;
+ wire _10155_;
+ wire _10156_;
+ wire _10157_;
+ wire _10158_;
+ wire _10159_;
+ wire _10160_;
+ wire _10161_;
+ wire _10162_;
+ wire _10163_;
+ wire _10164_;
+ wire _10165_;
+ wire _10166_;
+ wire _10167_;
+ wire _10168_;
+ wire _10169_;
+ wire _10170_;
+ wire _10171_;
+ wire _10172_;
+ wire _10173_;
+ wire _10174_;
+ wire _10175_;
+ wire _10176_;
+ wire _10177_;
+ wire _10178_;
+ wire _10179_;
+ wire _10180_;
+ wire _10181_;
+ wire _10182_;
+ wire _10183_;
+ wire _10184_;
+ wire _10185_;
+ wire _10186_;
+ wire _10187_;
+ wire _10188_;
+ wire _10189_;
+ wire _10190_;
+ wire _10191_;
+ wire _10192_;
+ wire _10193_;
+ wire _10194_;
+ wire _10195_;
+ wire _10196_;
+ wire _10197_;
+ wire _10198_;
+ wire _10199_;
+ wire _10200_;
+ wire _10201_;
+ wire _10202_;
+ wire _10203_;
+ wire _10204_;
+ wire _10205_;
+ wire _10206_;
+ wire _10207_;
+ wire _10208_;
+ wire _10209_;
+ wire _10210_;
+ wire _10211_;
+ wire _10212_;
+ wire _10213_;
+ wire _10214_;
+ wire _10215_;
+ wire _10216_;
+ wire _10217_;
+ wire _10218_;
+ wire _10219_;
+ wire _10220_;
+ wire _10221_;
+ wire _10222_;
+ wire _10223_;
+ wire _10224_;
+ wire _10225_;
+ wire _10226_;
+ wire _10227_;
+ wire _10228_;
+ wire _10229_;
+ wire _10230_;
+ wire _10231_;
+ wire _10232_;
+ wire _10233_;
+ wire _10234_;
+ wire _10235_;
+ wire _10236_;
+ wire _10237_;
+ wire _10238_;
+ wire _10239_;
+ wire _10240_;
+ wire _10241_;
+ wire _10242_;
+ wire _10243_;
+ wire _10244_;
+ wire _10245_;
+ wire _10246_;
+ wire _10247_;
+ wire _10248_;
+ wire _10249_;
+ wire _10250_;
+ wire _10251_;
+ wire _10252_;
+ wire _10253_;
+ wire _10254_;
+ wire _10255_;
+ wire _10256_;
+ wire _10257_;
+ wire _10258_;
+ wire _10259_;
+ wire _10260_;
+ wire _10261_;
+ wire _10262_;
+ wire _10263_;
+ wire _10264_;
+ wire _10265_;
+ wire _10266_;
+ wire _10267_;
+ wire _10268_;
+ wire _10269_;
+ wire _10270_;
+ wire _10271_;
+ wire _10272_;
+ wire _10273_;
+ wire _10274_;
+ wire _10275_;
+ wire _10276_;
+ wire _10277_;
+ wire _10278_;
+ wire _10279_;
+ wire _10280_;
+ wire _10281_;
+ wire _10282_;
+ wire _10283_;
+ wire _10284_;
+ wire _10285_;
+ wire _10286_;
+ wire _10287_;
+ wire _10288_;
+ wire _10289_;
+ wire _10290_;
+ wire _10291_;
+ wire _10292_;
+ wire _10293_;
+ wire _10294_;
+ wire _10295_;
+ wire _10296_;
+ wire _10297_;
+ wire _10298_;
+ wire _10299_;
+ wire _10300_;
+ wire _10301_;
+ wire _10302_;
+ wire _10303_;
+ wire _10304_;
+ wire _10305_;
+ wire _10306_;
+ wire _10307_;
+ wire _10308_;
+ wire _10309_;
+ wire _10310_;
+ wire _10311_;
+ wire _10312_;
+ wire _10313_;
+ wire _10314_;
+ wire _10315_;
+ wire _10316_;
+ wire _10317_;
+ wire _10318_;
+ wire _10319_;
+ wire _10320_;
+ wire _10321_;
+ wire _10322_;
+ wire _10323_;
+ wire _10324_;
+ wire _10325_;
+ wire _10326_;
+ wire _10327_;
+ wire _10328_;
+ wire _10329_;
+ wire _10330_;
+ wire _10331_;
+ wire _10332_;
+ wire _10333_;
+ wire _10334_;
+ wire _10335_;
+ wire _10336_;
+ wire _10337_;
+ wire _10338_;
+ wire _10339_;
+ wire _10340_;
+ wire _10341_;
+ wire _10342_;
+ wire _10343_;
+ wire _10344_;
+ wire _10345_;
+ wire _10346_;
+ wire _10347_;
+ wire _10348_;
+ wire _10349_;
+ wire _10350_;
+ wire _10351_;
+ wire _10352_;
+ wire _10353_;
+ wire _10354_;
+ wire _10355_;
+ wire _10356_;
+ wire _10357_;
+ wire _10358_;
+ wire _10359_;
+ wire _10360_;
+ wire _10361_;
+ wire _10362_;
+ wire _10363_;
+ wire _10364_;
+ wire _10365_;
+ wire _10366_;
+ wire _10367_;
+ wire _10368_;
+ wire _10369_;
+ wire _10370_;
+ wire _10371_;
+ wire _10372_;
+ wire _10373_;
+ wire _10374_;
+ wire _10375_;
+ wire _10376_;
+ wire _10377_;
+ wire _10378_;
+ wire _10379_;
+ wire _10380_;
+ wire _10381_;
+ wire _10382_;
+ wire _10383_;
+ wire _10384_;
+ wire _10385_;
+ wire _10386_;
+ wire _10387_;
+ wire _10388_;
+ wire _10389_;
+ wire _10390_;
+ wire _10391_;
+ wire _10392_;
+ wire _10393_;
+ wire _10394_;
+ wire _10395_;
+ wire _10396_;
+ wire _10397_;
+ wire _10398_;
+ wire _10399_;
+ wire _10400_;
+ wire _10401_;
+ wire _10402_;
+ wire _10403_;
+ wire _10404_;
+ wire _10405_;
+ wire _10406_;
+ wire _10407_;
+ wire _10408_;
+ wire _10409_;
+ wire _10410_;
+ wire _10411_;
+ wire _10412_;
+ wire _10413_;
+ wire _10414_;
+ wire _10415_;
+ wire _10416_;
+ wire _10417_;
+ wire _10418_;
+ wire _10419_;
+ wire _10420_;
+ wire _10421_;
+ wire _10422_;
+ wire _10423_;
+ wire _10424_;
+ wire _10425_;
+ wire _10426_;
+ wire _10427_;
+ wire _10428_;
+ wire _10429_;
+ wire _10430_;
+ wire _10431_;
+ wire _10432_;
+ wire _10433_;
+ wire _10434_;
+ wire _10435_;
+ wire _10436_;
+ wire _10437_;
+ wire _10438_;
+ wire _10439_;
+ wire _10440_;
+ wire _10441_;
+ wire _10442_;
+ wire _10443_;
+ wire _10444_;
+ wire _10445_;
+ wire _10446_;
+ wire _10447_;
+ wire _10448_;
+ wire _10449_;
+ wire _10450_;
+ wire _10451_;
+ wire _10452_;
+ wire _10453_;
+ wire _10454_;
+ wire _10455_;
+ wire _10456_;
+ wire _10457_;
+ wire _10458_;
+ wire _10459_;
+ wire _10460_;
+ wire _10461_;
+ wire _10462_;
+ wire _10463_;
+ wire _10464_;
+ wire _10465_;
+ wire _10466_;
+ wire _10467_;
+ wire _10468_;
+ wire _10469_;
+ wire _10470_;
+ wire _10471_;
+ wire _10472_;
+ wire _10473_;
+ wire _10474_;
+ wire _10475_;
+ wire _10476_;
+ wire _10477_;
+ wire _10478_;
+ wire _10479_;
+ wire _10480_;
+ wire _10481_;
+ wire _10482_;
+ wire _10483_;
+ wire _10484_;
+ wire _10485_;
+ wire _10486_;
+ wire _10487_;
+ wire _10488_;
+ wire _10489_;
+ wire _10490_;
+ wire _10491_;
+ wire _10492_;
+ wire _10493_;
+ wire _10494_;
+ wire _10495_;
+ wire _10496_;
+ wire _10497_;
+ wire _10498_;
+ wire _10499_;
+ wire _10500_;
+ wire _10501_;
+ wire _10502_;
+ wire _10503_;
+ wire _10504_;
+ wire _10505_;
+ wire _10506_;
+ wire _10507_;
+ wire _10508_;
+ wire _10509_;
+ wire _10510_;
+ wire _10511_;
+ wire _10512_;
+ wire _10513_;
+ wire _10514_;
+ wire _10515_;
+ wire _10516_;
+ wire _10517_;
+ wire _10518_;
+ wire _10519_;
+ wire _10520_;
+ wire _10521_;
+ wire _10522_;
+ wire _10523_;
+ wire _10524_;
+ wire _10525_;
+ wire _10526_;
+ wire _10527_;
+ wire _10528_;
+ wire _10529_;
+ wire _10530_;
+ wire _10531_;
+ wire _10532_;
+ wire _10533_;
+ wire _10534_;
+ wire _10535_;
+ wire _10536_;
+ wire _10537_;
+ wire _10538_;
+ wire _10539_;
+ wire _10540_;
+ wire _10541_;
+ wire _10542_;
+ wire _10543_;
+ wire _10544_;
+ wire _10545_;
+ wire _10546_;
+ wire _10547_;
+ wire _10548_;
+ wire _10549_;
+ wire _10550_;
+ wire _10551_;
+ wire _10552_;
+ wire _10553_;
+ wire _10554_;
+ wire _10555_;
+ wire _10556_;
+ wire _10557_;
+ wire _10558_;
+ wire _10559_;
+ wire _10560_;
+ wire _10561_;
+ wire _10562_;
+ wire _10563_;
+ wire _10564_;
+ wire _10565_;
+ wire _10566_;
+ wire _10567_;
+ wire _10568_;
+ wire _10569_;
+ wire _10570_;
+ wire _10571_;
+ wire _10572_;
+ wire _10573_;
+ wire _10574_;
+ wire _10575_;
+ wire _10576_;
+ wire _10577_;
+ wire _10578_;
+ wire _10579_;
+ wire _10580_;
+ wire _10581_;
+ wire _10582_;
+ wire _10583_;
+ wire _10584_;
+ wire _10585_;
+ wire _10586_;
+ wire _10587_;
+ wire _10588_;
+ wire _10589_;
+ wire _10590_;
+ wire _10591_;
+ wire _10592_;
+ wire _10593_;
+ wire _10594_;
+ wire _10595_;
+ wire _10596_;
+ wire _10597_;
+ wire _10598_;
+ wire _10599_;
+ wire _10600_;
+ wire _10601_;
+ wire _10602_;
+ wire _10603_;
+ wire _10604_;
+ wire _10605_;
+ wire _10606_;
+ wire _10607_;
+ wire _10608_;
+ wire _10609_;
+ wire _10610_;
+ wire _10611_;
+ wire _10612_;
+ wire _10613_;
+ wire _10614_;
+ wire _10615_;
+ wire _10616_;
+ wire _10617_;
+ wire _10618_;
+ wire _10619_;
+ wire _10620_;
+ wire _10621_;
+ wire _10622_;
+ wire _10623_;
+ wire _10624_;
+ wire _10625_;
+ wire _10626_;
+ wire _10627_;
+ wire _10628_;
+ wire _10629_;
+ wire _10630_;
+ wire _10631_;
+ wire _10632_;
+ wire _10633_;
+ wire _10634_;
+ wire _10635_;
+ wire _10636_;
+ wire _10637_;
+ wire _10638_;
+ wire _10639_;
+ wire _10640_;
+ wire _10641_;
+ wire _10642_;
+ wire _10643_;
+ wire _10644_;
+ wire _10645_;
+ wire _10646_;
+ wire _10647_;
+ wire _10648_;
+ wire _10649_;
+ wire _10650_;
+ wire _10651_;
+ wire _10652_;
+ wire _10653_;
+ wire _10654_;
+ wire _10655_;
+ wire _10656_;
+ wire _10657_;
+ wire _10658_;
+ wire _10659_;
+ wire _10660_;
+ wire _10661_;
+ wire _10662_;
+ wire _10663_;
+ wire _10664_;
+ wire _10665_;
+ wire _10666_;
+ wire _10667_;
+ wire _10668_;
+ wire _10669_;
+ wire _10670_;
+ wire _10671_;
+ wire _10672_;
+ wire _10673_;
+ wire _10674_;
+ wire _10675_;
+ wire _10676_;
+ wire _10677_;
+ wire _10678_;
+ wire _10679_;
+ wire _10680_;
+ wire _10681_;
+ wire _10682_;
+ wire _10683_;
+ wire _10684_;
+ wire _10685_;
+ wire _10686_;
+ wire _10687_;
+ wire _10688_;
+ wire _10689_;
+ wire _10690_;
+ wire _10691_;
+ wire _10692_;
+ wire _10693_;
+ wire _10694_;
+ wire _10695_;
+ wire _10696_;
+ wire _10697_;
+ wire _10698_;
+ wire _10699_;
+ wire _10700_;
+ wire _10701_;
+ wire _10702_;
+ wire _10703_;
+ wire _10704_;
+ wire _10705_;
+ wire _10706_;
+ wire _10707_;
+ wire _10708_;
+ wire _10709_;
+ wire _10710_;
+ wire _10711_;
+ wire _10712_;
+ wire _10713_;
+ wire _10714_;
+ wire _10715_;
+ wire _10716_;
+ wire _10717_;
+ wire _10718_;
+ wire _10719_;
+ wire _10720_;
+ wire _10721_;
+ wire _10722_;
+ wire _10723_;
+ wire _10724_;
+ wire _10725_;
+ wire _10726_;
+ wire _10727_;
+ wire _10728_;
+ wire _10729_;
+ wire _10730_;
+ wire _10731_;
+ wire _10732_;
+ wire _10733_;
+ wire _10734_;
+ wire _10735_;
+ wire _10736_;
+ wire _10737_;
+ wire _10738_;
+ wire _10739_;
+ wire _10740_;
+ wire _10741_;
+ wire _10742_;
+ wire _10743_;
+ wire _10744_;
+ wire _10745_;
+ wire _10746_;
+ wire _10747_;
+ wire _10748_;
+ wire _10749_;
+ wire _10750_;
+ wire _10751_;
+ wire _10752_;
+ wire _10753_;
+ wire _10754_;
+ wire _10755_;
+ wire _10756_;
+ wire _10757_;
+ wire _10758_;
+ wire _10759_;
+ wire _10760_;
+ wire _10761_;
+ wire _10762_;
+ wire _10763_;
+ wire _10764_;
+ wire _10765_;
+ wire _10766_;
+ wire _10767_;
+ wire _10768_;
+ wire _10769_;
+ wire _10770_;
+ wire _10771_;
+ wire _10772_;
+ wire _10773_;
+ wire _10774_;
+ wire _10775_;
+ wire _10776_;
+ wire _10777_;
+ wire _10778_;
+ wire _10779_;
+ wire _10780_;
+ wire _10781_;
+ wire _10782_;
+ wire _10783_;
+ wire _10784_;
+ wire _10785_;
+ wire _10786_;
+ wire _10787_;
+ wire _10788_;
+ wire _10789_;
+ wire _10790_;
+ wire _10791_;
+ wire _10792_;
+ wire _10793_;
+ wire _10794_;
+ wire _10795_;
+ wire _10796_;
+ wire _10797_;
+ wire _10798_;
+ wire _10799_;
+ wire _10800_;
+ wire _10801_;
+ wire _10802_;
+ wire _10803_;
+ wire _10804_;
+ wire _10805_;
+ wire _10806_;
+ wire _10807_;
+ wire _10808_;
+ wire _10809_;
+ wire _10810_;
+ wire _10811_;
+ wire _10812_;
+ wire _10813_;
+ wire _10814_;
+ wire _10815_;
+ wire _10816_;
+ wire _10817_;
+ wire _10818_;
+ wire _10819_;
+ wire _10820_;
+ wire _10821_;
+ wire _10822_;
+ wire _10823_;
+ wire _10824_;
+ wire _10825_;
+ wire _10826_;
+ wire _10827_;
+ wire _10828_;
+ wire _10829_;
+ wire _10830_;
+ wire _10831_;
+ wire _10832_;
+ wire _10833_;
+ wire _10834_;
+ wire _10835_;
+ wire _10836_;
+ wire _10837_;
+ wire _10838_;
+ wire _10839_;
+ wire _10840_;
+ wire _10841_;
+ wire _10842_;
+ wire _10843_;
+ wire _10844_;
+ wire _10845_;
+ wire _10846_;
+ wire _10847_;
+ wire _10848_;
+ wire _10849_;
+ wire _10850_;
+ wire _10851_;
+ wire _10852_;
+ wire _10853_;
+ wire _10854_;
+ wire _10855_;
+ wire _10856_;
+ wire _10857_;
+ wire _10858_;
+ wire _10859_;
+ wire _10860_;
+ wire _10861_;
+ wire _10862_;
+ wire _10863_;
+ wire _10864_;
+ wire _10865_;
+ wire _10866_;
+ wire _10867_;
+ wire _10868_;
+ wire _10869_;
+ wire _10870_;
+ wire _10871_;
+ wire _10872_;
+ wire _10873_;
+ wire _10874_;
+ wire _10875_;
+ wire _10876_;
+ wire _10877_;
+ wire _10878_;
+ wire _10879_;
+ wire _10880_;
+ wire _10881_;
+ wire _10882_;
+ wire _10883_;
+ wire _10884_;
+ wire _10885_;
+ wire _10886_;
+ wire _10887_;
+ wire _10888_;
+ wire _10889_;
+ wire _10890_;
+ wire _10891_;
+ wire _10892_;
+ wire _10893_;
+ wire _10894_;
+ wire _10895_;
+ wire _10896_;
+ wire _10897_;
+ wire _10898_;
+ wire _10899_;
+ wire _10900_;
+ wire _10901_;
+ wire _10902_;
+ wire _10903_;
+ wire _10904_;
+ wire _10905_;
+ wire _10906_;
+ wire _10907_;
+ wire _10908_;
+ wire _10909_;
+ wire _10910_;
+ wire _10911_;
+ wire _10912_;
+ wire _10913_;
+ wire _10914_;
+ wire _10915_;
+ wire _10916_;
+ wire _10917_;
+ wire _10918_;
+ wire _10919_;
+ wire _10920_;
+ wire _10921_;
+ wire _10922_;
+ wire _10923_;
+ wire _10924_;
+ wire _10925_;
+ wire _10926_;
+ wire _10927_;
+ wire _10928_;
+ wire _10929_;
+ wire _10930_;
+ wire _10931_;
+ wire _10932_;
+ wire _10933_;
+ wire _10934_;
+ wire _10935_;
+ wire _10936_;
+ wire _10937_;
+ wire _10938_;
+ wire _10939_;
+ wire _10940_;
+ wire _10941_;
+ wire _10942_;
+ wire _10943_;
+ wire _10944_;
+ wire _10945_;
+ wire _10946_;
+ wire _10947_;
+ wire _10948_;
+ wire _10949_;
+ wire _10950_;
+ wire _10951_;
+ wire _10952_;
+ wire _10953_;
+ wire _10954_;
+ wire _10955_;
+ wire _10956_;
+ wire _10957_;
+ wire _10958_;
+ wire _10959_;
+ wire _10960_;
+ wire _10961_;
+ wire _10962_;
+ wire _10963_;
+ wire _10964_;
+ wire _10965_;
+ wire _10966_;
+ wire _10967_;
+ wire _10968_;
+ wire _10969_;
+ wire _10970_;
+ wire _10971_;
+ wire _10972_;
+ wire _10973_;
+ wire _10974_;
+ wire _10975_;
+ wire _10976_;
+ wire _10977_;
+ wire _10978_;
+ wire _10979_;
+ wire _10980_;
+ wire _10981_;
+ wire _10982_;
+ wire _10983_;
+ wire _10984_;
+ wire _10985_;
+ wire _10986_;
+ wire _10987_;
+ wire _10988_;
+ wire _10989_;
+ wire _10990_;
+ wire _10991_;
+ wire _10992_;
+ wire _10993_;
+ wire _10994_;
+ wire _10995_;
+ wire _10996_;
+ wire _10997_;
+ wire _10998_;
+ wire _10999_;
+ wire _11000_;
+ wire _11001_;
+ wire _11002_;
+ wire _11003_;
+ wire _11004_;
+ wire _11005_;
+ wire _11006_;
+ wire _11007_;
+ wire _11008_;
+ wire _11009_;
+ wire _11010_;
+ wire _11011_;
+ wire _11012_;
+ wire _11013_;
+ wire _11014_;
+ wire _11015_;
+ wire _11016_;
+ wire _11017_;
+ wire _11018_;
+ wire _11019_;
+ wire _11020_;
+ wire _11021_;
+ wire _11022_;
+ wire _11023_;
+ wire _11024_;
+ wire _11025_;
+ wire _11026_;
+ wire _11027_;
+ wire _11028_;
+ wire _11029_;
+ wire _11030_;
+ wire _11031_;
+ wire _11032_;
+ wire _11033_;
+ wire _11034_;
+ wire _11035_;
+ wire _11036_;
+ wire _11037_;
+ wire _11038_;
+ wire _11039_;
+ wire _11040_;
+ wire _11041_;
+ wire _11042_;
+ wire _11043_;
+ wire _11044_;
+ wire _11045_;
+ wire _11046_;
+ wire _11047_;
+ wire _11048_;
+ wire _11049_;
+ wire _11050_;
+ wire _11051_;
+ wire _11052_;
+ wire _11053_;
+ wire _11054_;
+ wire _11055_;
+ wire _11056_;
+ wire _11057_;
+ wire _11058_;
+ wire _11059_;
+ wire _11060_;
+ wire _11061_;
+ wire _11062_;
+ wire _11063_;
+ wire _11064_;
+ wire _11065_;
+ wire _11066_;
+ wire _11067_;
+ wire _11068_;
+ wire _11069_;
+ wire _11070_;
+ wire _11071_;
+ wire _11072_;
+ wire _11073_;
+ wire _11074_;
+ wire _11075_;
+ wire _11076_;
+ wire _11077_;
+ wire _11078_;
+ wire _11079_;
+ wire _11080_;
+ wire _11081_;
+ wire _11082_;
+ wire _11083_;
+ wire _11084_;
+ wire _11085_;
+ wire _11086_;
+ wire _11087_;
+ wire _11088_;
+ wire _11089_;
+ wire _11090_;
+ wire _11091_;
+ wire _11092_;
+ wire _11093_;
+ wire _11094_;
+ wire _11095_;
+ wire _11096_;
+ wire _11097_;
+ wire _11098_;
+ wire _11099_;
+ wire _11100_;
+ wire _11101_;
+ wire _11102_;
+ wire _11103_;
+ wire _11104_;
+ wire _11105_;
+ wire _11106_;
+ wire _11107_;
+ wire _11108_;
+ wire _11109_;
+ wire _11110_;
+ wire _11111_;
+ wire _11112_;
+ wire _11113_;
+ wire _11114_;
+ wire _11115_;
+ wire _11116_;
+ wire _11117_;
+ wire _11118_;
+ wire _11119_;
+ wire _11120_;
+ wire _11121_;
+ wire _11122_;
+ wire _11123_;
+ wire _11124_;
+ wire _11125_;
+ wire _11126_;
+ wire _11127_;
+ wire _11128_;
+ wire _11129_;
+ wire _11130_;
+ wire _11131_;
+ wire _11132_;
+ wire _11133_;
+ wire _11134_;
+ wire _11135_;
+ wire _11136_;
+ wire _11137_;
+ wire _11138_;
+ wire _11139_;
+ wire _11140_;
+ wire _11141_;
+ wire _11142_;
+ wire _11143_;
+ wire _11144_;
+ wire _11145_;
+ wire _11146_;
+ wire _11147_;
+ wire _11148_;
+ wire _11149_;
+ wire _11150_;
+ wire _11151_;
+ wire _11152_;
+ wire _11153_;
+ wire _11154_;
+ wire _11155_;
+ wire _11156_;
+ wire _11157_;
+ wire _11158_;
+ wire _11159_;
+ wire _11160_;
+ wire _11161_;
+ wire _11162_;
+ wire _11163_;
+ wire _11164_;
+ wire _11165_;
+ wire _11166_;
+ wire _11167_;
+ wire _11168_;
+ wire _11169_;
+ wire _11170_;
+ wire _11171_;
+ wire _11172_;
+ wire _11173_;
+ wire _11174_;
+ wire _11175_;
+ wire _11176_;
+ wire _11177_;
+ wire _11178_;
+ wire _11179_;
+ wire _11180_;
+ wire _11181_;
+ wire _11182_;
+ wire _11183_;
+ wire _11184_;
+ wire _11185_;
+ wire _11186_;
+ wire _11187_;
+ wire _11188_;
+ wire _11189_;
+ wire _11190_;
+ wire _11191_;
+ wire _11192_;
+ wire _11193_;
+ wire _11194_;
+ wire _11195_;
+ wire _11196_;
+ wire _11197_;
+ wire _11198_;
+ wire _11199_;
+ wire _11200_;
+ wire _11201_;
+ wire _11202_;
+ wire _11203_;
+ wire _11204_;
+ wire _11205_;
+ wire _11206_;
+ wire _11207_;
+ wire _11208_;
+ wire _11209_;
+ wire _11210_;
+ wire _11211_;
+ wire _11212_;
+ wire _11213_;
+ wire _11214_;
+ wire _11215_;
+ wire _11216_;
+ wire _11217_;
+ wire _11218_;
+ wire _11219_;
+ wire _11220_;
+ wire _11221_;
+ wire _11222_;
+ wire _11223_;
+ wire _11224_;
+ wire _11225_;
+ wire _11226_;
+ wire _11227_;
+ wire _11228_;
+ wire _11229_;
+ wire _11230_;
+ wire _11231_;
+ wire _11232_;
+ wire _11233_;
+ wire _11234_;
+ wire _11235_;
+ wire _11236_;
+ wire _11237_;
+ wire _11238_;
+ wire _11239_;
+ wire _11240_;
+ wire _11241_;
+ wire _11242_;
+ wire _11243_;
+ wire _11244_;
+ wire _11245_;
+ wire _11246_;
+ wire _11247_;
+ wire _11248_;
+ wire _11249_;
+ wire _11250_;
+ wire _11251_;
+ wire _11252_;
+ wire _11253_;
+ wire _11254_;
+ wire _11255_;
+ wire _11256_;
+ wire _11257_;
+ wire _11258_;
+ wire _11259_;
+ wire _11260_;
+ wire _11261_;
+ wire _11262_;
+ wire _11263_;
+ wire _11264_;
+ wire _11265_;
+ wire _11266_;
+ wire _11267_;
+ wire _11268_;
+ wire _11269_;
+ wire _11270_;
+ wire _11271_;
+ wire _11272_;
+ wire _11273_;
+ wire _11274_;
+ wire _11275_;
+ wire _11276_;
+ wire _11277_;
+ wire _11278_;
+ wire _11279_;
+ wire _11280_;
+ wire _11281_;
+ wire _11282_;
+ wire _11283_;
+ wire _11284_;
+ wire _11285_;
+ wire _11286_;
+ wire _11287_;
+ wire _11288_;
+ wire _11289_;
+ wire _11290_;
+ wire _11291_;
+ wire _11292_;
+ wire _11293_;
+ wire _11294_;
+ wire _11295_;
+ wire _11296_;
+ wire _11297_;
+ wire _11298_;
+ wire _11299_;
+ wire _11300_;
+ wire _11301_;
+ wire _11302_;
+ wire _11303_;
+ wire _11304_;
+ wire _11305_;
+ wire _11306_;
+ wire _11307_;
+ wire _11308_;
+ wire _11309_;
+ wire _11310_;
+ wire _11311_;
+ wire _11312_;
+ wire _11313_;
+ wire _11314_;
+ wire _11315_;
+ wire _11316_;
+ wire _11317_;
+ wire _11318_;
+ wire _11319_;
+ wire _11320_;
+ wire _11321_;
+ wire _11322_;
+ wire _11323_;
+ wire _11324_;
+ wire _11325_;
+ wire _11326_;
+ wire _11327_;
+ wire _11328_;
+ wire _11329_;
+ wire _11330_;
+ wire _11331_;
+ wire _11332_;
+ wire _11333_;
+ wire _11334_;
+ wire _11335_;
+ wire _11336_;
+ wire _11337_;
+ wire _11338_;
+ wire _11339_;
+ wire _11340_;
+ wire _11341_;
+ wire _11342_;
+ wire _11343_;
+ wire _11344_;
+ wire _11345_;
+ wire _11346_;
+ wire _11347_;
+ wire _11348_;
+ wire _11349_;
+ wire _11350_;
+ wire _11351_;
+ wire _11352_;
+ wire _11353_;
+ wire _11354_;
+ wire _11355_;
+ wire _11356_;
+ wire _11357_;
+ wire _11358_;
+ wire _11359_;
+ wire _11360_;
+ wire _11361_;
+ wire _11362_;
+ wire _11363_;
+ wire _11364_;
+ wire _11365_;
+ wire _11366_;
+ wire _11367_;
+ wire _11368_;
+ wire _11369_;
+ wire _11370_;
+ wire _11371_;
+ wire _11372_;
+ wire _11373_;
+ wire _11374_;
+ wire _11375_;
+ wire _11376_;
+ wire _11377_;
+ wire _11378_;
+ wire _11379_;
+ wire _11380_;
+ wire _11381_;
+ wire _11382_;
+ wire _11383_;
+ wire _11384_;
+ wire _11385_;
+ wire _11386_;
+ wire _11387_;
+ wire _11388_;
+ wire _11389_;
+ wire _11390_;
+ wire _11391_;
+ wire _11392_;
+ wire _11393_;
+ wire _11394_;
+ wire _11395_;
+ wire _11396_;
+ wire _11397_;
+ wire _11398_;
+ wire _11399_;
+ wire _11400_;
+ wire _11401_;
+ wire _11402_;
+ wire _11403_;
+ wire _11404_;
+ wire _11405_;
+ wire _11406_;
+ wire _11407_;
+ wire _11408_;
+ wire _11409_;
+ wire _11410_;
+ wire _11411_;
+ wire _11412_;
+ wire _11413_;
+ wire _11414_;
+ wire _11415_;
+ wire _11416_;
+ wire _11417_;
+ wire _11418_;
+ wire _11419_;
+ wire _11420_;
+ wire _11421_;
+ wire _11422_;
+ wire _11423_;
+ wire _11424_;
+ wire _11425_;
+ wire _11426_;
+ wire _11427_;
+ wire _11428_;
+ wire _11429_;
+ wire _11430_;
+ wire _11431_;
+ wire _11432_;
+ wire _11433_;
+ wire _11434_;
+ wire _11435_;
+ wire _11436_;
+ wire _11437_;
+ wire _11438_;
+ wire _11439_;
+ wire _11440_;
+ wire _11441_;
+ wire _11442_;
+ wire _11443_;
+ wire _11444_;
+ wire _11445_;
+ wire _11446_;
+ wire _11447_;
+ wire _11448_;
+ wire _11449_;
+ wire _11450_;
+ wire _11451_;
+ wire _11452_;
+ wire _11453_;
+ wire _11454_;
+ wire _11455_;
+ wire _11456_;
+ wire _11457_;
+ wire _11458_;
+ wire _11459_;
+ wire _11460_;
+ wire _11461_;
+ wire _11462_;
+ wire _11463_;
+ wire _11464_;
+ wire _11465_;
+ wire _11466_;
+ wire _11467_;
+ wire _11468_;
+ wire _11469_;
+ wire _11470_;
+ wire _11471_;
+ wire _11472_;
+ wire _11473_;
+ wire _11474_;
+ wire _11475_;
+ wire _11476_;
+ wire _11477_;
+ wire _11478_;
+ wire _11479_;
+ wire _11480_;
+ wire _11481_;
+ wire _11482_;
+ wire _11483_;
+ wire _11484_;
+ wire _11485_;
+ wire _11486_;
+ wire _11487_;
+ wire _11488_;
+ wire _11489_;
+ wire _11490_;
+ wire _11491_;
+ wire _11492_;
+ wire _11493_;
+ wire _11494_;
+ wire _11495_;
+ wire _11496_;
+ wire _11497_;
+ wire _11498_;
+ wire _11499_;
+ wire _11500_;
+ wire _11501_;
+ wire _11502_;
+ wire _11503_;
+ wire _11504_;
+ wire _11505_;
+ wire _11506_;
+ wire _11507_;
+ wire _11508_;
+ wire _11509_;
+ wire _11510_;
+ wire _11511_;
+ wire _11512_;
+ wire _11513_;
+ wire _11514_;
+ wire _11515_;
+ wire _11516_;
+ wire _11517_;
+ wire _11518_;
+ wire _11519_;
+ wire _11520_;
+ wire _11521_;
+ wire _11522_;
+ wire _11523_;
+ wire _11524_;
+ wire _11525_;
+ wire _11526_;
+ wire _11527_;
+ wire _11528_;
+ wire _11529_;
+ wire _11530_;
+ wire _11531_;
+ wire _11532_;
+ wire _11533_;
+ wire _11534_;
+ wire _11535_;
+ wire _11536_;
+ wire _11537_;
+ wire _11538_;
+ wire _11539_;
+ wire _11540_;
+ wire _11541_;
+ wire _11542_;
+ wire _11543_;
+ wire _11544_;
+ wire _11545_;
+ wire _11546_;
+ wire _11547_;
+ wire _11548_;
+ wire _11549_;
+ wire _11550_;
+ wire _11551_;
+ wire _11552_;
+ wire _11553_;
+ wire _11554_;
+ wire _11555_;
+ wire _11556_;
+ wire _11557_;
+ wire _11558_;
+ wire _11559_;
+ wire _11560_;
+ wire _11561_;
+ wire _11562_;
+ wire _11563_;
+ wire _11564_;
+ wire _11565_;
+ wire _11566_;
+ wire _11567_;
+ wire _11568_;
+ wire _11569_;
+ wire _11570_;
+ wire _11571_;
+ wire _11572_;
+ wire _11573_;
+ wire _11574_;
+ wire _11575_;
+ wire _11576_;
+ wire _11577_;
+ wire _11578_;
+ wire _11579_;
+ wire _11580_;
+ wire _11581_;
+ wire _11582_;
+ wire _11583_;
+ wire _11584_;
+ wire _11585_;
+ wire _11586_;
+ wire _11587_;
+ wire _11588_;
+ wire _11589_;
+ wire _11590_;
+ wire _11591_;
+ wire _11592_;
+ wire _11593_;
+ wire _11594_;
+ wire _11595_;
+ wire _11596_;
+ wire _11597_;
+ wire _11598_;
+ wire _11599_;
+ wire _11600_;
+ wire _11601_;
+ wire _11602_;
+ wire _11603_;
+ wire _11604_;
+ wire _11605_;
+ wire _11606_;
+ wire _11607_;
+ wire _11608_;
+ wire _11609_;
+ wire _11610_;
+ wire _11611_;
+ wire _11612_;
+ wire _11613_;
+ wire _11614_;
+ wire _11615_;
+ wire _11616_;
+ wire _11617_;
+ wire _11618_;
+ wire _11619_;
+ wire _11620_;
+ wire _11621_;
+ wire _11622_;
+ wire _11623_;
+ wire _11624_;
+ wire _11625_;
+ wire _11626_;
+ wire _11627_;
+ wire _11628_;
+ wire _11629_;
+ wire _11630_;
+ wire _11631_;
+ wire _11632_;
+ wire _11633_;
+ wire _11634_;
+ wire _11635_;
+ wire _11636_;
+ wire _11637_;
+ wire _11638_;
+ wire _11639_;
+ wire _11640_;
+ wire _11641_;
+ wire _11642_;
+ wire _11643_;
+ wire _11644_;
+ wire _11645_;
+ wire _11646_;
+ wire _11647_;
+ wire _11648_;
+ wire _11649_;
+ wire _11650_;
+ wire _11651_;
+ wire _11652_;
+ wire _11653_;
+ wire _11654_;
+ wire _11655_;
+ wire _11656_;
+ wire _11657_;
+ wire _11658_;
+ wire _11659_;
+ wire _11660_;
+ wire _11661_;
+ wire _11662_;
+ wire _11663_;
+ wire _11664_;
+ wire _11665_;
+ wire _11666_;
+ wire _11667_;
+ wire _11668_;
+ wire _11669_;
+ wire _11670_;
+ wire _11671_;
+ wire _11672_;
+ wire _11673_;
+ wire _11674_;
+ wire _11675_;
+ wire _11676_;
+ wire _11677_;
+ wire _11678_;
+ wire _11679_;
+ wire _11680_;
+ wire _11681_;
+ wire _11682_;
+ wire _11683_;
+ wire _11684_;
+ wire _11685_;
+ wire _11686_;
+ wire _11687_;
+ wire _11688_;
+ wire _11689_;
+ wire _11690_;
+ wire _11691_;
+ wire _11692_;
+ wire _11693_;
+ wire _11694_;
+ wire _11695_;
+ wire _11696_;
+ wire _11697_;
+ wire _11698_;
+ wire _11699_;
+ wire _11700_;
+ wire _11701_;
+ wire _11702_;
+ wire _11703_;
+ wire _11704_;
+ wire _11705_;
+ wire _11706_;
+ wire _11707_;
+ wire _11708_;
+ wire _11709_;
+ wire _11710_;
+ wire _11711_;
+ wire _11712_;
+ wire _11713_;
+ wire _11714_;
+ wire _11715_;
+ wire _11716_;
+ wire _11717_;
+ wire _11718_;
+ wire _11719_;
+ wire _11720_;
+ wire _11721_;
+ wire _11722_;
+ wire _11723_;
+ wire _11724_;
+ wire _11725_;
+ wire _11726_;
+ wire _11727_;
+ wire _11728_;
+ wire _11729_;
+ wire _11730_;
+ wire _11731_;
+ wire _11732_;
+ wire _11733_;
+ wire _11734_;
+ wire _11735_;
+ wire _11736_;
+ wire _11737_;
+ wire _11738_;
+ wire _11739_;
+ wire _11740_;
+ wire _11741_;
+ wire _11742_;
+ wire _11743_;
+ wire _11744_;
+ wire _11745_;
+ wire _11746_;
+ wire _11747_;
+ wire _11748_;
+ wire _11749_;
+ wire _11750_;
+ wire _11751_;
+ wire _11752_;
+ wire _11753_;
+ wire _11754_;
+ wire _11755_;
+ wire _11756_;
+ wire _11757_;
+ wire _11758_;
+ wire _11759_;
+ wire _11760_;
+ wire _11761_;
+ wire _11762_;
+ wire _11763_;
+ wire _11764_;
+ wire _11765_;
+ wire _11766_;
+ wire _11767_;
+ wire _11768_;
+ wire _11769_;
+ wire _11770_;
+ wire _11771_;
+ wire _11772_;
+ wire _11773_;
+ wire _11774_;
+ wire _11775_;
+ wire _11776_;
+ wire _11777_;
+ wire _11778_;
+ wire _11779_;
+ wire _11780_;
+ wire _11781_;
+ wire _11782_;
+ wire _11783_;
+ wire _11784_;
+ wire _11785_;
+ wire _11786_;
+ wire _11787_;
+ wire _11788_;
+ wire _11789_;
+ wire _11790_;
+ wire _11791_;
+ wire _11792_;
+ wire _11793_;
+ wire _11794_;
+ wire _11795_;
+ wire _11796_;
+ wire _11797_;
+ wire _11798_;
+ wire _11799_;
+ wire _11800_;
+ wire _11801_;
+ wire _11802_;
+ wire _11803_;
+ wire _11804_;
+ wire _11805_;
+ wire _11806_;
+ wire _11807_;
+ wire _11808_;
+ wire _11809_;
+ wire _11810_;
+ wire _11811_;
+ wire _11812_;
+ wire _11813_;
+ wire _11814_;
+ wire _11815_;
+ wire _11816_;
+ wire _11817_;
+ wire _11818_;
+ wire _11819_;
+ wire _11820_;
+ wire _11821_;
+ wire _11822_;
+ wire _11823_;
+ wire _11824_;
+ wire _11825_;
+ wire _11826_;
+ wire _11827_;
+ wire _11828_;
+ wire _11829_;
+ wire _11830_;
+ wire _11831_;
+ wire _11832_;
+ wire _11833_;
+ wire _11834_;
+ wire _11835_;
+ wire _11836_;
+ wire _11837_;
+ wire _11838_;
+ wire _11839_;
+ wire _11840_;
+ wire _11841_;
+ wire _11842_;
+ wire _11843_;
+ wire _11844_;
+ wire _11845_;
+ wire _11846_;
+ wire _11847_;
+ wire _11848_;
+ wire _11849_;
+ wire _11850_;
+ wire _11851_;
+ wire _11852_;
+ wire _11853_;
+ wire _11854_;
+ wire _11855_;
+ wire _11856_;
+ wire _11857_;
+ wire _11858_;
+ wire _11859_;
+ wire _11860_;
+ wire _11861_;
+ wire _11862_;
+ wire _11863_;
+ wire _11864_;
+ wire _11865_;
+ wire _11866_;
+ wire _11867_;
+ wire _11868_;
+ wire _11869_;
+ wire _11870_;
+ wire _11871_;
+ wire _11872_;
+ wire _11873_;
+ wire _11874_;
+ wire _11875_;
+ wire _11876_;
+ wire _11877_;
+ wire _11878_;
+ wire _11879_;
+ wire _11880_;
+ wire _11881_;
+ wire _11882_;
+ wire _11883_;
+ wire _11884_;
+ wire _11885_;
+ wire _11886_;
+ wire _11887_;
+ wire _11888_;
+ wire _11889_;
+ wire _11890_;
+ wire _11891_;
+ wire _11892_;
+ wire _11893_;
+ wire _11894_;
+ wire _11895_;
+ wire _11896_;
+ wire _11897_;
+ wire _11898_;
+ wire _11899_;
+ wire _11900_;
+ wire _11901_;
+ wire _11902_;
+ wire _11903_;
+ wire _11904_;
+ wire _11905_;
+ wire _11906_;
+ wire _11907_;
+ wire _11908_;
+ wire _11909_;
+ wire _11910_;
+ wire _11911_;
+ wire _11912_;
+ wire _11913_;
+ wire _11914_;
+ wire _11915_;
+ wire _11916_;
+ wire _11917_;
+ wire _11918_;
+ wire _11919_;
+ wire _11920_;
+ wire _11921_;
+ wire _11922_;
+ wire _11923_;
+ wire _11924_;
+ wire _11925_;
+ wire _11926_;
+ wire _11927_;
+ wire _11928_;
+ wire _11929_;
+ wire _11930_;
+ wire _11931_;
+ wire _11932_;
+ wire _11933_;
+ wire _11934_;
+ wire _11935_;
+ wire _11936_;
+ wire _11937_;
+ wire _11938_;
+ wire _11939_;
+ wire _11940_;
+ wire _11941_;
+ wire _11942_;
+ wire _11943_;
+ wire _11944_;
+ wire _11945_;
+ wire _11946_;
+ wire _11947_;
+ wire _11948_;
+ wire _11949_;
+ wire _11950_;
+ wire _11951_;
+ wire _11952_;
+ wire _11953_;
+ wire _11954_;
+ wire _11955_;
+ wire _11956_;
+ wire _11957_;
+ wire _11958_;
+ wire _11959_;
+ wire _11960_;
+ wire _11961_;
+ wire _11962_;
+ wire _11963_;
+ wire _11964_;
+ wire _11965_;
+ wire _11966_;
+ wire _11967_;
+ wire _11968_;
+ wire _11969_;
+ wire _11970_;
+ wire _11971_;
+ wire _11972_;
+ wire _11973_;
+ wire _11974_;
+ wire _11975_;
+ wire _11976_;
+ wire _11977_;
+ wire _11978_;
+ wire _11979_;
+ wire _11980_;
+ wire _11981_;
+ wire _11982_;
+ wire _11983_;
+ wire _11984_;
+ wire _11985_;
+ wire _11986_;
+ wire _11987_;
+ wire _11988_;
+ wire _11989_;
+ wire _11990_;
+ wire _11991_;
+ wire _11992_;
+ wire _11993_;
+ wire _11994_;
+ wire _11995_;
+ wire _11996_;
+ wire _11997_;
+ wire _11998_;
+ wire _11999_;
+ wire _12000_;
+ wire _12001_;
+ wire _12002_;
+ wire _12003_;
+ wire _12004_;
+ wire _12005_;
+ wire _12006_;
+ wire _12007_;
+ wire _12008_;
+ wire _12009_;
+ wire _12010_;
+ wire _12011_;
+ wire _12012_;
+ wire _12013_;
+ wire _12014_;
+ wire _12015_;
+ wire _12016_;
+ wire _12017_;
+ wire _12018_;
+ wire _12019_;
+ wire _12020_;
+ wire _12021_;
+ wire _12022_;
+ wire _12023_;
+ wire _12024_;
+ wire _12025_;
+ wire _12026_;
+ wire _12027_;
+ wire _12028_;
+ wire _12029_;
+ wire _12030_;
+ wire _12031_;
+ wire _12032_;
+ wire _12033_;
+ wire _12034_;
+ wire _12035_;
+ wire _12036_;
+ wire _12037_;
+ wire _12038_;
+ wire _12039_;
+ wire _12040_;
+ wire _12041_;
+ wire _12042_;
+ wire _12043_;
+ wire _12044_;
+ wire _12045_;
+ wire _12046_;
+ wire _12047_;
+ wire _12048_;
+ wire _12049_;
+ wire _12050_;
+ wire _12051_;
+ wire _12052_;
+ wire _12053_;
+ wire _12054_;
+ wire _12055_;
+ wire _12056_;
+ wire _12057_;
+ wire _12058_;
+ wire _12059_;
+ wire _12060_;
+ wire _12061_;
+ wire _12062_;
+ wire _12063_;
+ wire _12064_;
+ wire _12065_;
+ wire _12066_;
+ wire _12067_;
+ wire _12068_;
+ wire _12069_;
+ wire _12070_;
+ wire _12071_;
+ wire _12072_;
+ wire _12073_;
+ wire _12074_;
+ wire _12075_;
+ wire _12076_;
+ wire _12077_;
+ wire _12078_;
+ wire _12079_;
+ wire _12080_;
+ wire _12081_;
+ wire _12082_;
+ wire _12083_;
+ wire _12084_;
+ wire _12085_;
+ wire _12086_;
+ wire _12087_;
+ wire _12088_;
+ wire _12089_;
+ wire _12090_;
+ wire _12091_;
+ wire _12092_;
+ wire _12093_;
+ wire _12094_;
+ wire _12095_;
+ wire _12096_;
+ wire _12097_;
+ wire _12098_;
+ wire _12099_;
+ wire _12100_;
+ wire _12101_;
+ wire _12102_;
+ wire _12103_;
+ wire _12104_;
+ wire _12105_;
+ wire _12106_;
+ wire _12107_;
+ wire _12108_;
+ wire _12109_;
+ wire _12110_;
+ wire _12111_;
+ wire _12112_;
+ wire _12113_;
+ wire _12114_;
+ wire _12115_;
+ wire _12116_;
+ wire _12117_;
+ wire _12118_;
+ wire _12119_;
+ wire _12120_;
+ wire _12121_;
+ wire _12122_;
+ wire _12123_;
+ wire _12124_;
+ wire _12125_;
+ wire _12126_;
+ wire _12127_;
+ wire _12128_;
+ wire _12129_;
+ wire _12130_;
+ wire _12131_;
+ wire _12132_;
+ wire _12133_;
+ wire _12134_;
+ wire _12135_;
+ wire _12136_;
+ wire _12137_;
+ wire _12138_;
+ wire _12139_;
+ wire _12140_;
+ wire _12141_;
+ wire _12142_;
+ wire _12143_;
+ wire _12144_;
+ wire _12145_;
+ wire _12146_;
+ wire _12147_;
+ wire _12148_;
+ wire _12149_;
+ wire _12150_;
+ wire _12151_;
+ wire _12152_;
+ wire _12153_;
+ wire _12154_;
+ wire _12155_;
+ wire _12156_;
+ wire _12157_;
+ wire _12158_;
+ wire _12159_;
+ wire _12160_;
+ wire _12161_;
+ wire _12162_;
+ wire _12163_;
+ wire _12164_;
+ wire _12165_;
+ wire _12166_;
+ wire _12167_;
+ wire _12168_;
+ wire _12169_;
+ wire _12170_;
+ wire _12171_;
+ wire _12172_;
+ wire _12173_;
+ wire _12174_;
+ wire _12175_;
+ wire _12176_;
+ wire _12177_;
+ wire _12178_;
+ wire _12179_;
+ wire _12180_;
+ wire _12181_;
+ wire _12182_;
+ wire _12183_;
+ wire _12184_;
+ wire _12185_;
+ wire _12186_;
+ wire _12187_;
+ wire _12188_;
+ wire _12189_;
+ wire _12190_;
+ wire _12191_;
+ wire _12192_;
+ wire _12193_;
+ wire _12194_;
+ wire _12195_;
+ wire _12196_;
+ wire _12197_;
+ wire _12198_;
+ wire _12199_;
+ wire _12200_;
+ wire _12201_;
+ wire _12202_;
+ wire _12203_;
+ wire _12204_;
+ wire _12205_;
+ wire _12206_;
+ wire _12207_;
+ wire _12208_;
+ wire _12209_;
+ wire _12210_;
+ wire _12211_;
+ wire _12212_;
+ wire _12213_;
+ wire _12214_;
+ wire _12215_;
+ wire _12216_;
+ wire _12217_;
+ wire _12218_;
+ wire _12219_;
+ wire _12220_;
+ wire _12221_;
+ wire _12222_;
+ wire _12223_;
+ wire _12224_;
+ wire _12225_;
+ wire _12226_;
+ wire _12227_;
+ wire _12228_;
+ wire _12229_;
+ wire _12230_;
+ wire _12231_;
+ wire _12232_;
+ wire _12233_;
+ wire _12234_;
+ wire _12235_;
+ wire _12236_;
+ wire _12237_;
+ wire _12238_;
+ wire _12239_;
+ wire _12240_;
+ wire _12241_;
+ wire _12242_;
+ wire _12243_;
+ wire _12244_;
+ wire _12245_;
+ wire _12246_;
+ wire _12247_;
+ wire _12248_;
+ wire _12249_;
+ wire _12250_;
+ wire _12251_;
+ wire _12252_;
+ wire _12253_;
+ wire _12254_;
+ wire _12255_;
+ wire _12256_;
+ wire _12257_;
+ wire _12258_;
+ wire _12259_;
+ wire _12260_;
+ wire _12261_;
+ wire _12262_;
+ wire _12263_;
+ wire _12264_;
+ wire _12265_;
+ wire _12266_;
+ wire _12267_;
+ wire _12268_;
+ wire _12269_;
+ wire _12270_;
+ wire _12271_;
+ wire _12272_;
+ wire _12273_;
+ wire _12274_;
+ wire _12275_;
+ wire _12276_;
+ wire _12277_;
+ wire _12278_;
+ wire _12279_;
+ wire _12280_;
+ wire _12281_;
+ wire _12282_;
+ wire _12283_;
+ wire _12284_;
+ wire _12285_;
+ wire _12286_;
+ wire _12287_;
+ wire _12288_;
+ wire _12289_;
+ wire _12290_;
+ wire _12291_;
+ wire _12292_;
+ wire _12293_;
+ wire _12294_;
+ wire _12295_;
+ wire _12296_;
+ wire _12297_;
+ wire _12298_;
+ wire _12299_;
+ wire _12300_;
+ wire _12301_;
+ wire _12302_;
+ wire _12303_;
+ wire _12304_;
+ wire _12305_;
+ wire _12306_;
+ wire _12307_;
+ wire _12308_;
+ wire _12309_;
+ wire _12310_;
+ wire _12311_;
+ wire _12312_;
+ wire _12313_;
+ wire _12314_;
+ wire _12315_;
+ wire _12316_;
+ wire _12317_;
+ wire _12318_;
+ wire _12319_;
+ wire _12320_;
+ wire _12321_;
+ wire _12322_;
+ wire _12323_;
+ wire _12324_;
+ wire _12325_;
+ wire _12326_;
+ wire _12327_;
+ wire _12328_;
+ wire _12329_;
+ wire _12330_;
+ wire _12331_;
+ wire _12332_;
+ wire _12333_;
+ wire _12334_;
+ wire _12335_;
+ wire _12336_;
+ wire _12337_;
+ wire _12338_;
+ wire _12339_;
+ wire _12340_;
+ wire _12341_;
+ wire _12342_;
+ wire _12343_;
+ wire _12344_;
+ wire _12345_;
+ wire _12346_;
+ wire _12347_;
+ wire _12348_;
+ wire _12349_;
+ wire _12350_;
+ wire _12351_;
+ wire _12352_;
+ wire _12353_;
+ wire _12354_;
+ wire _12355_;
+ wire _12356_;
+ wire _12357_;
+ wire _12358_;
+ wire _12359_;
+ wire _12360_;
+ wire _12361_;
+ wire _12362_;
+ wire _12363_;
+ wire _12364_;
+ wire _12365_;
+ wire _12366_;
+ wire _12367_;
+ wire _12368_;
+ wire _12369_;
+ wire _12370_;
+ wire _12371_;
+ wire _12372_;
+ wire _12373_;
+ wire _12374_;
+ wire _12375_;
+ wire _12376_;
+ wire _12377_;
+ wire _12378_;
+ wire _12379_;
+ wire _12380_;
+ wire _12381_;
+ wire _12382_;
+ wire _12383_;
+ wire _12384_;
+ wire _12385_;
+ wire _12386_;
+ wire _12387_;
+ wire _12388_;
+ wire _12389_;
+ wire _12390_;
+ wire _12391_;
+ wire _12392_;
+ wire _12393_;
+ wire _12394_;
+ wire _12395_;
+ wire _12396_;
+ wire _12397_;
+ wire _12398_;
+ wire _12399_;
+ wire _12400_;
+ wire _12401_;
+ wire _12402_;
+ wire _12403_;
+ wire _12404_;
+ wire _12405_;
+ wire _12406_;
+ wire _12407_;
+ wire _12408_;
+ wire _12409_;
+ wire _12410_;
+ wire _12411_;
+ wire _12412_;
+ wire _12413_;
+ wire _12414_;
+ wire _12415_;
+ wire _12416_;
+ wire _12417_;
+ wire _12418_;
+ wire _12419_;
+ wire _12420_;
+ wire _12421_;
+ wire _12422_;
+ wire _12423_;
+ wire _12424_;
+ wire _12425_;
+ wire _12426_;
+ wire _12427_;
+ wire _12428_;
+ wire _12429_;
+ wire _12430_;
+ wire _12431_;
+ wire _12432_;
+ wire _12433_;
+ wire _12434_;
+ wire _12435_;
+ wire _12436_;
+ wire _12437_;
+ wire _12438_;
+ wire _12439_;
+ wire _12440_;
+ wire _12441_;
+ wire _12442_;
+ wire _12443_;
+ wire _12444_;
+ wire _12445_;
+ wire _12446_;
+ wire _12447_;
+ wire _12448_;
+ wire _12449_;
+ wire _12450_;
+ wire _12451_;
+ wire _12452_;
+ wire _12453_;
+ wire _12454_;
+ wire _12455_;
+ wire _12456_;
+ wire _12457_;
+ wire _12458_;
+ wire _12459_;
+ wire _12460_;
+ wire _12461_;
+ wire _12462_;
+ wire _12463_;
+ wire _12464_;
+ wire _12465_;
+ wire _12466_;
+ wire _12467_;
+ wire _12468_;
+ wire _12469_;
+ wire _12470_;
+ wire _12471_;
+ wire _12472_;
+ wire _12473_;
+ wire _12474_;
+ wire _12475_;
+ wire _12476_;
+ wire _12477_;
+ wire _12478_;
+ wire _12479_;
+ wire _12480_;
+ wire _12481_;
+ wire _12482_;
+ wire _12483_;
+ wire _12484_;
+ wire _12485_;
+ wire _12486_;
+ wire _12487_;
+ wire _12488_;
+ wire _12489_;
+ wire _12490_;
+ wire _12491_;
+ wire _12492_;
+ wire _12493_;
+ wire _12494_;
+ wire _12495_;
+ wire _12496_;
+ wire _12497_;
+ wire _12498_;
+ wire _12499_;
+ wire _12500_;
+ wire _12501_;
+ wire _12502_;
+ wire _12503_;
+ wire _12504_;
+ wire _12505_;
+ wire _12506_;
+ wire _12507_;
+ wire _12508_;
+ wire _12509_;
+ wire _12510_;
+ wire _12511_;
+ wire _12512_;
+ wire _12513_;
+ wire _12514_;
+ wire _12515_;
+ wire _12516_;
+ wire _12517_;
+ wire _12518_;
+ wire _12519_;
+ wire _12520_;
+ wire _12521_;
+ wire _12522_;
+ wire _12523_;
+ wire _12524_;
+ wire _12525_;
+ wire _12526_;
+ wire _12527_;
+ wire _12528_;
+ wire _12529_;
+ wire _12530_;
+ wire _12531_;
+ wire _12532_;
+ wire _12533_;
+ wire _12534_;
+ wire _12535_;
+ wire _12536_;
+ wire _12537_;
+ wire _12538_;
+ wire _12539_;
+ wire _12540_;
+ wire _12541_;
+ wire _12542_;
+ wire _12543_;
+ wire _12544_;
+ wire _12545_;
+ wire _12546_;
+ wire _12547_;
+ wire _12548_;
+ wire _12549_;
+ wire _12550_;
+ wire _12551_;
+ wire _12552_;
+ wire _12553_;
+ wire _12554_;
+ wire _12555_;
+ wire _12556_;
+ wire _12557_;
+ wire _12558_;
+ wire _12559_;
+ wire _12560_;
+ wire _12561_;
+ wire _12562_;
+ wire _12563_;
+ wire _12564_;
+ wire _12565_;
+ wire _12566_;
+ wire _12567_;
+ wire _12568_;
+ wire _12569_;
+ wire _12570_;
+ wire _12571_;
+ wire _12572_;
+ wire _12573_;
+ wire _12574_;
+ wire _12575_;
+ wire _12576_;
+ wire _12577_;
+ wire _12578_;
+ wire _12579_;
+ wire _12580_;
+ wire _12581_;
+ wire _12582_;
+ wire _12583_;
+ wire _12584_;
+ wire _12585_;
+ wire _12586_;
+ wire _12587_;
+ wire _12588_;
+ wire _12589_;
+ wire _12590_;
+ wire _12591_;
+ wire _12592_;
+ wire _12593_;
+ wire _12594_;
+ wire _12595_;
+ wire _12596_;
+ wire _12597_;
+ wire _12598_;
+ wire _12599_;
+ wire _12600_;
+ wire _12601_;
+ wire _12602_;
+ wire _12603_;
+ wire _12604_;
+ wire _12605_;
+ wire _12606_;
+ wire _12607_;
+ wire _12608_;
+ wire _12609_;
+ wire _12610_;
+ wire _12611_;
+ wire _12612_;
+ wire _12613_;
+ wire _12614_;
+ wire _12615_;
+ wire _12616_;
+ wire _12617_;
+ wire _12618_;
+ wire _12619_;
+ wire _12620_;
+ wire _12621_;
+ wire _12622_;
+ wire _12623_;
+ wire _12624_;
+ wire _12625_;
+ wire _12626_;
+ wire _12627_;
+ wire _12628_;
+ wire _12629_;
+ wire _12630_;
+ wire _12631_;
+ wire _12632_;
+ wire _12633_;
+ wire _12634_;
+ wire _12635_;
+ wire _12636_;
+ wire _12637_;
+ wire _12638_;
+ wire _12639_;
+ wire _12640_;
+ wire _12641_;
+ wire _12642_;
+ wire _12643_;
+ wire _12644_;
+ wire _12645_;
+ wire _12646_;
+ wire _12647_;
+ wire _12648_;
+ wire _12649_;
+ wire _12650_;
+ wire _12651_;
+ wire _12652_;
+ wire _12653_;
+ wire _12654_;
+ wire _12655_;
+ wire _12656_;
+ wire _12657_;
+ wire _12658_;
+ wire _12659_;
+ wire _12660_;
+ wire _12661_;
+ wire _12662_;
+ wire _12663_;
+ wire _12664_;
+ wire _12665_;
+ wire _12666_;
+ wire _12667_;
+ wire _12668_;
+ wire _12669_;
+ wire _12670_;
+ wire _12671_;
+ wire _12672_;
+ wire _12673_;
+ wire _12674_;
+ wire _12675_;
+ wire _12676_;
+ wire _12677_;
+ wire _12678_;
+ wire _12679_;
+ wire _12680_;
+ wire _12681_;
+ wire _12682_;
+ wire _12683_;
+ wire _12684_;
+ wire _12685_;
+ wire _12686_;
+ wire _12687_;
+ wire _12688_;
+ wire _12689_;
+ wire _12690_;
+ wire _12691_;
+ wire _12692_;
+ wire _12693_;
+ wire _12694_;
+ wire _12695_;
+ wire _12696_;
+ wire _12697_;
+ wire _12698_;
+ wire _12699_;
+ wire _12700_;
+ wire _12701_;
+ wire _12702_;
+ wire _12703_;
+ wire _12704_;
+ wire _12705_;
+ wire _12706_;
+ wire _12707_;
+ wire _12708_;
+ wire _12709_;
+ wire _12710_;
+ wire _12711_;
+ wire _12712_;
+ wire _12713_;
+ wire _12714_;
+ wire _12715_;
+ wire _12716_;
+ wire _12717_;
+ wire _12718_;
+ wire _12719_;
+ wire _12720_;
+ wire _12721_;
+ wire _12722_;
+ wire _12723_;
+ wire _12724_;
+ wire _12725_;
+ wire _12726_;
+ wire _12727_;
+ wire _12728_;
+ wire _12729_;
+ wire _12730_;
+ wire _12731_;
+ wire _12732_;
+ wire _12733_;
+ wire _12734_;
+ wire _12735_;
+ wire _12736_;
+ wire _12737_;
+ wire _12738_;
+ wire _12739_;
+ wire _12740_;
+ wire _12741_;
+ wire _12742_;
+ wire _12743_;
+ wire _12744_;
+ wire _12745_;
+ wire _12746_;
+ wire _12747_;
+ wire _12748_;
+ wire _12749_;
+ wire _12750_;
+ wire _12751_;
+ wire _12752_;
+ wire _12753_;
+ wire _12754_;
+ wire _12755_;
+ wire _12756_;
+ wire _12757_;
+ wire _12758_;
+ wire _12759_;
+ wire _12760_;
+ wire _12761_;
+ wire _12762_;
+ wire _12763_;
+ wire _12764_;
+ wire _12765_;
+ wire _12766_;
+ wire _12767_;
+ wire _12768_;
+ wire _12769_;
+ wire _12770_;
+ wire _12771_;
+ wire _12772_;
+ wire _12773_;
+ wire _12774_;
+ wire _12775_;
+ wire _12776_;
+ wire _12777_;
+ wire _12778_;
+ wire _12779_;
+ wire _12780_;
+ wire _12781_;
+ wire _12782_;
+ wire _12783_;
+ wire _12784_;
+ wire _12785_;
+ wire _12786_;
+ wire _12787_;
+ wire _12788_;
+ wire _12789_;
+ wire _12790_;
+ wire _12791_;
+ wire _12792_;
+ wire _12793_;
+ wire _12794_;
+ wire _12795_;
+ wire _12796_;
+ wire _12797_;
+ wire _12798_;
+ wire _12799_;
+ wire _12800_;
+ wire _12801_;
+ wire _12802_;
+ wire _12803_;
+ wire _12804_;
+ wire _12805_;
+ wire _12806_;
+ wire _12807_;
+ wire _12808_;
+ wire _12809_;
+ wire _12810_;
+ wire _12811_;
+ wire _12812_;
+ wire _12813_;
+ wire _12814_;
+ wire _12815_;
+ wire _12816_;
+ wire _12817_;
+ wire _12818_;
+ wire _12819_;
+ wire _12820_;
+ wire _12821_;
+ wire _12822_;
+ wire _12823_;
+ wire _12824_;
+ wire _12825_;
+ wire _12826_;
+ wire _12827_;
+ wire _12828_;
+ wire _12829_;
+ wire _12830_;
+ wire _12831_;
+ wire _12832_;
+ wire _12833_;
+ wire _12834_;
+ wire _12835_;
+ wire _12836_;
+ wire _12837_;
+ wire _12838_;
+ wire _12839_;
+ wire _12840_;
+ wire _12841_;
+ wire _12842_;
+ wire _12843_;
+ wire _12844_;
+ wire _12845_;
+ wire _12846_;
+ wire _12847_;
+ wire _12848_;
+ wire _12849_;
+ wire _12850_;
+ wire _12851_;
+ wire _12852_;
+ wire _12853_;
+ wire _12854_;
+ wire _12855_;
+ wire _12856_;
+ wire _12857_;
+ wire _12858_;
+ wire _12859_;
+ wire _12860_;
+ wire _12861_;
+ wire _12862_;
+ wire _12863_;
+ wire _12864_;
+ wire _12865_;
+ wire _12866_;
+ wire _12867_;
+ wire _12868_;
+ wire _12869_;
+ wire _12870_;
+ wire _12871_;
+ wire _12872_;
+ wire _12873_;
+ wire _12874_;
+ wire _12875_;
+ wire _12876_;
+ wire _12877_;
+ wire _12878_;
+ wire _12879_;
+ wire _12880_;
+ wire _12881_;
+ wire _12882_;
+ wire _12883_;
+ wire _12884_;
+ wire _12885_;
+ wire _12886_;
+ wire _12887_;
+ wire _12888_;
+ wire _12889_;
+ wire _12890_;
+ wire _12891_;
+ wire _12892_;
+ wire _12893_;
+ wire _12894_;
+ wire _12895_;
+ wire _12896_;
+ wire _12897_;
+ wire _12898_;
+ wire _12899_;
+ wire _12900_;
+ wire _12901_;
+ wire _12902_;
+ wire _12903_;
+ wire _12904_;
+ wire _12905_;
+ wire _12906_;
+ wire _12907_;
+ wire _12908_;
+ wire _12909_;
+ wire _12910_;
+ wire _12911_;
+ wire _12912_;
+ wire _12913_;
+ wire _12914_;
+ wire _12915_;
+ wire _12916_;
+ wire _12917_;
+ wire _12918_;
+ wire _12919_;
+ wire _12920_;
+ wire _12921_;
+ wire _12922_;
+ wire _12923_;
+ wire _12924_;
+ wire _12925_;
+ wire _12926_;
+ wire _12927_;
+ wire _12928_;
+ wire _12929_;
+ wire _12930_;
+ wire _12931_;
+ wire _12932_;
+ wire _12933_;
+ wire _12934_;
+ wire _12935_;
+ wire _12936_;
+ wire _12937_;
+ wire _12938_;
+ wire _12939_;
+ wire _12940_;
+ wire _12941_;
+ wire _12942_;
+ wire _12943_;
+ wire _12944_;
+ wire _12945_;
+ wire _12946_;
+ wire _12947_;
+ wire _12948_;
+ wire _12949_;
+ wire _12950_;
+ wire _12951_;
+ wire _12952_;
+ wire _12953_;
+ wire _12954_;
+ wire _12955_;
+ wire _12956_;
+ wire _12957_;
+ wire _12958_;
+ wire _12959_;
+ wire _12960_;
+ wire _12961_;
+ wire _12962_;
+ wire _12963_;
+ wire _12964_;
+ wire _12965_;
+ wire _12966_;
+ wire _12967_;
+ wire _12968_;
+ wire _12969_;
+ wire _12970_;
+ wire _12971_;
+ wire _12972_;
+ wire _12973_;
+ wire _12974_;
+ wire _12975_;
+ wire _12976_;
+ wire _12977_;
+ wire _12978_;
+ wire _12979_;
+ wire _12980_;
+ wire _12981_;
+ wire _12982_;
+ wire _12983_;
+ wire _12984_;
+ wire _12985_;
+ wire _12986_;
+ wire _12987_;
+ wire _12988_;
+ wire _12989_;
+ wire _12990_;
+ wire _12991_;
+ wire _12992_;
+ wire _12993_;
+ wire _12994_;
+ wire _12995_;
+ wire _12996_;
+ wire _12997_;
+ wire _12998_;
+ wire _12999_;
+ wire _13000_;
+ wire _13001_;
+ wire _13002_;
+ wire _13003_;
+ wire _13004_;
+ wire _13005_;
+ wire _13006_;
+ wire _13007_;
+ wire _13008_;
+ wire _13009_;
+ wire _13010_;
+ wire _13011_;
+ wire _13012_;
+ wire _13013_;
+ wire _13014_;
+ wire _13015_;
+ wire _13016_;
+ wire _13017_;
+ wire _13018_;
+ wire _13019_;
+ wire _13020_;
+ wire _13021_;
+ wire _13022_;
+ wire _13023_;
+ wire _13024_;
+ wire _13025_;
+ wire _13026_;
+ wire _13027_;
+ wire _13028_;
+ wire _13029_;
+ wire _13030_;
+ wire _13031_;
+ wire _13032_;
+ wire _13033_;
+ wire _13034_;
+ wire _13035_;
+ wire _13036_;
+ wire _13037_;
+ wire _13038_;
+ wire _13039_;
+ wire _13040_;
+ wire _13041_;
+ wire _13042_;
+ wire _13043_;
+ wire _13044_;
+ wire _13045_;
+ wire _13046_;
+ wire _13047_;
+ wire _13048_;
+ wire _13049_;
+ wire _13050_;
+ wire _13051_;
+ wire _13052_;
+ wire _13053_;
+ wire _13054_;
+ wire _13055_;
+ wire _13056_;
+ wire _13057_;
+ wire _13058_;
+ wire _13059_;
+ wire _13060_;
+ wire _13061_;
+ wire _13062_;
+ wire _13063_;
+ wire _13064_;
+ wire _13065_;
+ wire _13066_;
+ wire _13067_;
+ wire _13068_;
+ wire _13069_;
+ wire _13070_;
+ wire _13071_;
+ wire _13072_;
+ wire _13073_;
+ wire _13074_;
+ wire _13075_;
+ wire _13076_;
+ wire _13077_;
+ wire _13078_;
+ wire _13079_;
+ wire _13080_;
+ wire _13081_;
+ wire _13082_;
+ wire _13083_;
+ wire _13084_;
+ wire _13085_;
+ wire _13086_;
+ wire _13087_;
+ wire _13088_;
+ wire _13089_;
+ wire _13090_;
+ wire _13091_;
+ wire _13092_;
+ wire _13093_;
+ wire _13094_;
+ wire _13095_;
+ wire _13096_;
+ wire _13097_;
+ wire _13098_;
+ wire _13099_;
+ wire _13100_;
+ wire _13101_;
+ wire _13102_;
+ wire _13103_;
+ wire _13104_;
+ wire _13105_;
+ wire _13106_;
+ wire _13107_;
+ wire _13108_;
+ wire _13109_;
+ wire _13110_;
+ wire _13111_;
+ wire _13112_;
+ wire _13113_;
+ wire _13114_;
+ wire _13115_;
+ wire _13116_;
+ wire _13117_;
+ wire _13118_;
+ wire _13119_;
+ wire _13120_;
+ wire _13121_;
+ wire _13122_;
+ wire _13123_;
+ wire _13124_;
+ wire _13125_;
+ wire _13126_;
+ wire _13127_;
+ wire _13128_;
+ wire _13129_;
+ wire _13130_;
+ wire _13131_;
+ wire _13132_;
+ wire _13133_;
+ wire _13134_;
+ wire _13135_;
+ wire _13136_;
+ wire _13137_;
+ wire _13138_;
+ wire _13139_;
+ wire _13140_;
+ wire _13141_;
+ wire _13142_;
+ wire _13143_;
+ wire _13144_;
+ wire _13145_;
+ wire _13146_;
+ wire _13147_;
+ wire _13148_;
+ wire _13149_;
+ wire _13150_;
+ wire _13151_;
+ wire _13152_;
+ wire _13153_;
+ wire _13154_;
+ wire _13155_;
+ wire _13156_;
+ wire _13157_;
+ wire _13158_;
+ wire _13159_;
+ wire _13160_;
+ wire _13161_;
+ wire _13162_;
+ wire _13163_;
+ wire _13164_;
+ wire _13165_;
+ wire _13166_;
+ wire _13167_;
+ wire _13168_;
+ wire _13169_;
+ wire _13170_;
+ wire _13171_;
+ wire _13172_;
+ wire _13173_;
+ wire _13174_;
+ wire _13175_;
+ wire _13176_;
+ wire _13177_;
+ wire _13178_;
+ wire _13179_;
+ wire _13180_;
+ wire _13181_;
+ wire _13182_;
+ wire _13183_;
+ wire _13184_;
+ wire _13185_;
+ wire _13186_;
+ wire _13187_;
+ wire _13188_;
+ wire _13189_;
+ wire _13190_;
+ wire _13191_;
+ wire _13192_;
+ wire _13193_;
+ wire _13194_;
+ wire _13195_;
+ wire _13196_;
+ wire _13197_;
+ wire _13198_;
+ wire _13199_;
+ wire _13200_;
+ wire _13201_;
+ wire _13202_;
+ wire _13203_;
+ wire _13204_;
+ wire _13205_;
+ wire _13206_;
+ wire _13207_;
+ wire _13208_;
+ wire _13209_;
+ wire _13210_;
+ wire _13211_;
+ wire _13212_;
+ wire _13213_;
+ wire _13214_;
+ wire _13215_;
+ wire _13216_;
+ wire _13217_;
+ wire _13218_;
+ wire _13219_;
+ wire _13220_;
+ wire _13221_;
+ wire _13222_;
+ wire _13223_;
+ wire _13224_;
+ wire _13225_;
+ wire _13226_;
+ wire _13227_;
+ wire _13228_;
+ wire _13229_;
+ wire _13230_;
+ wire _13231_;
+ wire _13232_;
+ wire _13233_;
+ wire _13234_;
+ wire _13235_;
+ wire _13236_;
+ wire _13237_;
+ wire _13238_;
+ wire _13239_;
+ wire _13240_;
+ wire _13241_;
+ wire _13242_;
+ wire _13243_;
+ wire _13244_;
+ wire _13245_;
+ wire _13246_;
+ wire _13247_;
+ wire _13248_;
+ wire _13249_;
+ wire _13250_;
+ wire _13251_;
+ wire _13252_;
+ wire _13253_;
+ wire _13254_;
+ wire _13255_;
+ wire _13256_;
+ wire _13257_;
+ wire _13258_;
+ wire _13259_;
+ wire _13260_;
+ wire _13261_;
+ wire _13262_;
+ wire _13263_;
+ wire _13264_;
+ wire _13265_;
+ wire _13266_;
+ wire _13267_;
+ wire _13268_;
+ wire _13269_;
+ wire _13270_;
+ wire _13271_;
+ wire _13272_;
+ wire _13273_;
+ wire _13274_;
+ wire _13275_;
+ wire _13276_;
+ wire _13277_;
+ wire _13278_;
+ wire _13279_;
+ wire _13280_;
+ wire _13281_;
+ wire _13282_;
+ wire _13283_;
+ wire _13284_;
+ wire _13285_;
+ wire _13286_;
+ wire _13287_;
+ wire _13288_;
+ wire _13289_;
+ wire _13290_;
+ wire _13291_;
+ wire _13292_;
+ wire _13293_;
+ wire _13294_;
+ wire _13295_;
+ wire _13296_;
+ wire _13297_;
+ wire _13298_;
+ wire _13299_;
+ wire _13300_;
+ wire _13301_;
+ wire _13302_;
+ wire _13303_;
+ wire _13304_;
+ wire _13305_;
+ wire _13306_;
+ wire _13307_;
+ wire _13308_;
+ wire _13309_;
+ wire _13310_;
+ wire _13311_;
+ wire _13312_;
+ wire _13313_;
+ wire _13314_;
+ wire _13315_;
+ wire _13316_;
+ wire _13317_;
+ wire _13318_;
+ wire _13319_;
+ wire _13320_;
+ wire _13321_;
+ wire _13322_;
+ wire _13323_;
+ wire _13324_;
+ wire _13325_;
+ wire _13326_;
+ wire _13327_;
+ wire _13328_;
+ wire _13329_;
+ wire _13330_;
+ wire _13331_;
+ wire _13332_;
+ wire _13333_;
+ wire _13334_;
+ wire _13335_;
+ wire _13336_;
+ wire _13337_;
+ wire _13338_;
+ wire _13339_;
+ wire _13340_;
+ wire _13341_;
+ wire _13342_;
+ wire _13343_;
+ wire _13344_;
+ wire _13345_;
+ wire _13346_;
+ wire _13347_;
+ wire _13348_;
+ wire _13349_;
+ wire _13350_;
+ wire _13351_;
+ wire _13352_;
+ wire _13353_;
+ wire _13354_;
+ wire _13355_;
+ wire _13356_;
+ wire _13357_;
+ wire _13358_;
+ wire _13359_;
+ wire _13360_;
+ wire _13361_;
+ wire _13362_;
+ wire _13363_;
+ wire _13364_;
+ wire _13365_;
+ wire _13366_;
+ wire _13367_;
+ wire _13368_;
+ wire _13369_;
+ wire _13370_;
+ wire _13371_;
+ wire _13372_;
+ wire _13373_;
+ wire _13374_;
+ wire _13375_;
+ wire _13376_;
+ wire _13377_;
+ wire _13378_;
+ wire _13379_;
+ wire _13380_;
+ wire _13381_;
+ wire _13382_;
+ wire _13383_;
+ wire _13384_;
+ wire _13385_;
+ wire _13386_;
+ wire _13387_;
+ wire _13388_;
+ wire _13389_;
+ wire _13390_;
+ wire _13391_;
+ wire _13392_;
+ wire _13393_;
+ wire _13394_;
+ wire _13395_;
+ wire _13396_;
+ wire _13397_;
+ wire _13398_;
+ wire _13399_;
+ wire _13400_;
+ wire _13401_;
+ wire _13402_;
+ wire _13403_;
+ wire _13404_;
+ wire _13405_;
+ wire _13406_;
+ wire _13407_;
+ wire _13408_;
+ wire _13409_;
+ wire _13410_;
+ wire _13411_;
+ wire _13412_;
+ wire _13413_;
+ wire _13414_;
+ wire _13415_;
+ wire _13416_;
+ wire _13417_;
+ wire _13418_;
+ wire _13419_;
+ wire _13420_;
+ wire _13421_;
+ wire _13422_;
+ wire _13423_;
+ wire _13424_;
+ wire _13425_;
+ wire _13426_;
+ wire _13427_;
+ wire _13428_;
+ wire _13429_;
+ wire _13430_;
+ wire _13431_;
+ wire _13432_;
+ wire _13433_;
+ wire _13434_;
+ wire _13435_;
+ wire _13436_;
+ wire _13437_;
+ wire _13438_;
+ wire _13439_;
+ wire _13440_;
+ wire _13441_;
+ wire _13442_;
+ wire _13443_;
+ wire _13444_;
+ wire _13445_;
+ wire _13446_;
+ wire _13447_;
+ wire _13448_;
+ wire _13449_;
+ wire _13450_;
+ wire _13451_;
+ wire _13452_;
+ wire _13453_;
+ wire _13454_;
+ wire _13455_;
+ wire _13456_;
+ wire _13457_;
+ wire _13458_;
+ wire _13459_;
+ wire _13460_;
+ wire _13461_;
+ wire _13462_;
+ wire _13463_;
+ wire _13464_;
+ wire _13465_;
+ wire _13466_;
+ wire _13467_;
+ wire _13468_;
+ wire _13469_;
+ wire _13470_;
+ wire _13471_;
+ wire _13472_;
+ wire _13473_;
+ wire _13474_;
+ wire _13475_;
+ wire _13476_;
+ wire _13477_;
+ wire _13478_;
+ wire _13479_;
+ wire _13480_;
+ wire _13481_;
+ wire _13482_;
+ wire _13483_;
+ wire _13484_;
+ wire _13485_;
+ wire _13486_;
+ wire _13487_;
+ wire _13488_;
+ wire _13489_;
+ wire _13490_;
+ wire _13491_;
+ wire _13492_;
+ wire _13493_;
+ wire _13494_;
+ wire _13495_;
+ wire _13496_;
+ wire _13497_;
+ wire _13498_;
+ wire _13499_;
+ wire _13500_;
+ wire _13501_;
+ wire _13502_;
+ wire _13503_;
+ wire _13504_;
+ wire _13505_;
+ wire _13506_;
+ wire _13507_;
+ wire _13508_;
+ wire _13509_;
+ wire _13510_;
+ wire _13511_;
+ wire _13512_;
+ wire _13513_;
+ wire _13514_;
+ wire _13515_;
+ wire _13516_;
+ wire _13517_;
+ wire _13518_;
+ wire _13519_;
+ wire _13520_;
+ wire _13521_;
+ wire _13522_;
+ wire _13523_;
+ wire _13524_;
+ wire _13525_;
+ wire _13526_;
+ wire _13527_;
+ wire _13528_;
+ wire _13529_;
+ wire _13530_;
+ wire _13531_;
+ wire _13532_;
+ wire _13533_;
+ wire _13534_;
+ wire _13535_;
+ wire _13536_;
+ wire _13537_;
+ wire _13538_;
+ wire _13539_;
+ wire _13540_;
+ wire _13541_;
+ wire _13542_;
+ wire _13543_;
+ wire _13544_;
+ wire _13545_;
+ wire _13546_;
+ wire _13547_;
+ wire _13548_;
+ wire _13549_;
+ wire _13550_;
+ wire _13551_;
+ wire _13552_;
+ wire _13553_;
+ wire _13554_;
+ wire _13555_;
+ wire _13556_;
+ wire _13557_;
+ wire _13558_;
+ wire _13559_;
+ wire _13560_;
+ wire _13561_;
+ wire _13562_;
+ wire _13563_;
+ wire _13564_;
+ wire _13565_;
+ wire _13566_;
+ wire _13567_;
+ wire _13568_;
+ wire _13569_;
+ wire _13570_;
+ wire _13571_;
+ wire _13572_;
+ wire _13573_;
+ wire _13574_;
+ wire _13575_;
+ wire _13576_;
+ wire _13577_;
+ wire _13578_;
+ wire _13579_;
+ wire _13580_;
+ wire _13581_;
+ wire _13582_;
+ wire _13583_;
+ wire _13584_;
+ wire _13585_;
+ wire _13586_;
+ wire _13587_;
+ wire _13588_;
+ wire _13589_;
+ wire _13590_;
+ wire _13591_;
+ wire _13592_;
+ wire _13593_;
+ wire _13594_;
+ wire _13595_;
+ wire _13596_;
+ wire _13597_;
+ wire _13598_;
+ wire _13599_;
+ wire _13600_;
+ wire _13601_;
+ wire _13602_;
+ wire _13603_;
+ wire _13604_;
+ wire _13605_;
+ wire _13606_;
+ wire _13607_;
+ wire _13608_;
+ wire _13609_;
+ wire _13610_;
+ wire _13611_;
+ wire _13612_;
+ wire _13613_;
+ wire _13614_;
+ wire _13615_;
+ wire _13616_;
+ wire _13617_;
+ wire _13618_;
+ wire _13619_;
+ wire _13620_;
+ wire _13621_;
+ wire _13622_;
+ wire _13623_;
+ wire _13624_;
+ wire _13625_;
+ wire _13626_;
+ wire _13627_;
+ wire _13628_;
+ wire _13629_;
+ wire _13630_;
+ wire _13631_;
+ wire _13632_;
+ wire _13633_;
+ wire _13634_;
+ wire _13635_;
+ wire _13636_;
+ wire _13637_;
+ wire _13638_;
+ wire _13639_;
+ wire _13640_;
+ wire _13641_;
+ wire _13642_;
+ wire _13643_;
+ wire _13644_;
+ wire _13645_;
+ wire _13646_;
+ wire _13647_;
+ wire _13648_;
+ wire _13649_;
+ wire _13650_;
+ wire _13651_;
+ wire _13652_;
+ wire _13653_;
+ wire _13654_;
+ wire _13655_;
+ wire _13656_;
+ wire _13657_;
+ wire _13658_;
+ wire _13659_;
+ wire _13660_;
+ wire _13661_;
+ wire _13662_;
+ wire _13663_;
+ wire _13664_;
+ wire _13665_;
+ wire _13666_;
+ wire _13667_;
+ wire _13668_;
+ wire _13669_;
+ wire _13670_;
+ wire _13671_;
+ wire _13672_;
+ wire _13673_;
+ wire _13674_;
+ wire _13675_;
+ wire _13676_;
+ wire _13677_;
+ wire _13678_;
+ wire _13679_;
+ wire _13680_;
+ wire _13681_;
+ wire _13682_;
+ wire _13683_;
+ wire _13684_;
+ wire _13685_;
+ wire _13686_;
+ wire _13687_;
+ wire _13688_;
+ wire _13689_;
+ wire _13690_;
+ wire _13691_;
+ wire _13692_;
+ wire _13693_;
+ wire _13694_;
+ wire _13695_;
+ wire _13696_;
+ wire _13697_;
+ wire _13698_;
+ wire _13699_;
+ wire _13700_;
+ wire _13701_;
+ wire _13702_;
+ wire _13703_;
+ wire _13704_;
+ wire _13705_;
+ wire _13706_;
+ wire _13707_;
+ wire _13708_;
+ wire _13709_;
+ wire _13710_;
+ wire _13711_;
+ wire _13712_;
+ wire _13713_;
+ wire _13714_;
+ wire _13715_;
+ wire _13716_;
+ wire _13717_;
+ wire _13718_;
+ wire _13719_;
+ wire _13720_;
+ wire _13721_;
+ wire _13722_;
+ wire _13723_;
+ wire _13724_;
+ wire _13725_;
+ wire _13726_;
+ wire _13727_;
+ wire _13728_;
+ wire _13729_;
+ wire _13730_;
+ wire _13731_;
+ wire _13732_;
+ wire _13733_;
+ wire _13734_;
+ wire _13735_;
+ wire _13736_;
+ wire _13737_;
+ wire _13738_;
+ wire _13739_;
+ wire _13740_;
+ wire _13741_;
+ wire _13742_;
+ wire _13743_;
+ wire _13744_;
+ wire _13745_;
+ wire _13746_;
+ wire _13747_;
+ wire _13748_;
+ wire _13749_;
+ wire _13750_;
+ wire _13751_;
+ wire _13752_;
+ wire _13753_;
+ wire _13754_;
+ wire _13755_;
+ wire _13756_;
+ wire _13757_;
+ wire _13758_;
+ wire _13759_;
+ wire _13760_;
+ wire _13761_;
+ wire _13762_;
+ wire _13763_;
+ wire _13764_;
+ wire _13765_;
+ wire _13766_;
+ wire _13767_;
+ wire _13768_;
+ wire _13769_;
+ wire _13770_;
+ wire _13771_;
+ wire _13772_;
+ wire _13773_;
+ wire _13774_;
+ wire _13775_;
+ wire _13776_;
+ wire _13777_;
+ wire _13778_;
+ wire _13779_;
+ wire _13780_;
+ wire _13781_;
+ wire _13782_;
+ wire _13783_;
+ wire _13784_;
+ wire _13785_;
+ wire _13786_;
+ wire _13787_;
+ wire _13788_;
+ wire _13789_;
+ wire _13790_;
+ wire _13791_;
+ wire _13792_;
+ wire _13793_;
+ wire _13794_;
+ wire _13795_;
+ wire _13796_;
+ wire _13797_;
+ wire _13798_;
+ wire _13799_;
+ wire _13800_;
+ wire _13801_;
+ wire _13802_;
+ wire _13803_;
+ wire _13804_;
+ wire _13805_;
+ wire _13806_;
+ wire _13807_;
+ wire _13808_;
+ wire _13809_;
+ wire _13810_;
+ wire _13811_;
+ wire _13812_;
+ wire _13813_;
+ wire _13814_;
+ wire _13815_;
+ wire _13816_;
+ wire _13817_;
+ wire _13818_;
+ wire _13819_;
+ wire _13820_;
+ wire _13821_;
+ wire _13822_;
+ wire _13823_;
+ wire _13824_;
+ wire _13825_;
+ wire _13826_;
+ wire _13827_;
+ wire _13828_;
+ wire _13829_;
+ wire _13830_;
+ wire _13831_;
+ wire _13832_;
+ wire _13833_;
+ wire _13834_;
+ wire _13835_;
+ wire _13836_;
+ wire _13837_;
+ wire _13838_;
+ wire _13839_;
+ wire _13840_;
+ wire _13841_;
+ wire _13842_;
+ wire _13843_;
+ wire _13844_;
+ wire _13845_;
+ wire _13846_;
+ wire _13847_;
+ wire _13848_;
+ wire _13849_;
+ wire _13850_;
+ wire _13851_;
+ wire _13852_;
+ wire _13853_;
+ wire _13854_;
+ wire _13855_;
+ wire _13856_;
+ wire _13857_;
+ wire _13858_;
+ wire _13859_;
+ wire _13860_;
+ wire _13861_;
+ wire _13862_;
+ wire _13863_;
+ wire _13864_;
+ wire _13865_;
+ wire _13866_;
+ wire _13867_;
+ wire _13868_;
+ wire _13869_;
+ wire _13870_;
+ wire _13871_;
+ wire _13872_;
+ wire _13873_;
+ wire _13874_;
+ wire _13875_;
+ wire _13876_;
+ wire _13877_;
+ wire _13878_;
+ wire _13879_;
+ wire _13880_;
+ wire _13881_;
+ wire _13882_;
+ wire _13883_;
+ wire _13884_;
+ wire _13885_;
+ wire _13886_;
+ wire _13887_;
+ wire _13888_;
+ wire _13889_;
+ wire _13890_;
+ wire _13891_;
+ wire _13892_;
+ wire _13893_;
+ wire _13894_;
+ wire _13895_;
+ wire _13896_;
+ wire _13897_;
+ wire _13898_;
+ wire _13899_;
+ wire _13900_;
+ wire _13901_;
+ wire _13902_;
+ wire _13903_;
+ wire _13904_;
+ wire _13905_;
+ wire _13906_;
+ wire _13907_;
+ wire _13908_;
+ wire _13909_;
+ wire _13910_;
+ wire _13911_;
+ wire _13912_;
+ wire _13913_;
+ wire _13914_;
+ wire _13915_;
+ wire _13916_;
+ wire _13917_;
+ wire _13918_;
+ wire _13919_;
+ wire _13920_;
+ wire _13921_;
+ wire _13922_;
+ wire _13923_;
+ wire _13924_;
+ wire _13925_;
+ wire _13926_;
+ wire _13927_;
+ wire _13928_;
+ wire _13929_;
+ wire _13930_;
+ wire _13931_;
+ wire _13932_;
+ wire _13933_;
+ wire _13934_;
+ wire _13935_;
+ wire _13936_;
+ wire _13937_;
+ wire _13938_;
+ wire _13939_;
+ wire _13940_;
+ wire _13941_;
+ wire _13942_;
+ wire _13943_;
+ wire _13944_;
+ wire _13945_;
+ wire _13946_;
+ wire _13947_;
+ wire _13948_;
+ wire _13949_;
+ wire _13950_;
+ wire _13951_;
+ wire _13952_;
+ wire _13953_;
+ wire _13954_;
+ wire _13955_;
+ wire _13956_;
+ wire _13957_;
+ wire _13958_;
+ wire _13959_;
+ wire _13960_;
+ wire _13961_;
+ wire _13962_;
+ wire _13963_;
+ wire _13964_;
+ wire _13965_;
+ wire _13966_;
+ wire _13967_;
+ wire _13968_;
+ wire _13969_;
+ wire _13970_;
+ wire _13971_;
+ wire _13972_;
+ wire _13973_;
+ wire _13974_;
+ wire _13975_;
+ wire _13976_;
+ wire _13977_;
+ wire _13978_;
+ wire _13979_;
+ wire _13980_;
+ wire _13981_;
+ wire _13982_;
+ wire _13983_;
+ wire _13984_;
+ wire _13985_;
+ wire _13986_;
+ wire _13987_;
+ wire _13988_;
+ wire _13989_;
+ wire _13990_;
+ wire _13991_;
+ wire _13992_;
+ wire _13993_;
+ wire _13994_;
+ wire _13995_;
+ wire _13996_;
+ wire _13997_;
+ wire _13998_;
+ wire _13999_;
+ wire _14000_;
+ wire _14001_;
+ wire _14002_;
+ wire _14003_;
+ wire _14004_;
+ wire _14005_;
+ wire _14006_;
+ wire _14007_;
+ wire _14008_;
+ wire _14009_;
+ wire _14010_;
+ wire _14011_;
+ wire _14012_;
+ wire _14013_;
+ wire _14014_;
+ wire _14015_;
+ wire _14016_;
+ wire _14017_;
+ wire _14018_;
+ wire _14019_;
+ wire _14020_;
+ wire _14021_;
+ wire _14022_;
+ wire _14023_;
+ wire _14024_;
+ wire _14025_;
+ wire _14026_;
+ wire _14027_;
+ wire _14028_;
+ wire _14029_;
+ wire _14030_;
+ wire _14031_;
+ wire _14032_;
+ wire _14033_;
+ wire _14034_;
+ wire _14035_;
+ wire _14036_;
+ wire _14037_;
+ wire _14038_;
+ wire _14039_;
+ wire _14040_;
+ wire _14041_;
+ wire _14042_;
+ wire _14043_;
+ wire _14044_;
+ wire _14045_;
+ wire _14046_;
+ wire _14047_;
+ wire _14048_;
+ wire _14049_;
+ wire _14050_;
+ wire _14051_;
+ wire _14052_;
+ wire _14053_;
+ wire _14054_;
+ wire _14055_;
+ wire _14056_;
+ wire _14057_;
+ wire _14058_;
+ wire _14059_;
+ wire _14060_;
+ wire _14061_;
+ wire _14062_;
+ wire _14063_;
+ wire _14064_;
+ wire _14065_;
+ wire _14066_;
+ wire _14067_;
+ wire _14068_;
+ wire _14069_;
+ wire _14070_;
+ wire _14071_;
+ wire _14072_;
+ wire _14073_;
+ wire _14074_;
+ wire _14075_;
+ wire _14076_;
+ wire _14077_;
+ wire _14078_;
+ wire _14079_;
+ wire _14080_;
+ wire _14081_;
+ wire _14082_;
+ wire _14083_;
+ wire _14084_;
+ wire _14085_;
+ wire _14086_;
+ wire _14087_;
+ wire _14088_;
+ wire _14089_;
+ wire _14090_;
+ wire _14091_;
+ wire _14092_;
+ wire _14093_;
+ wire _14094_;
+ wire _14095_;
+ wire _14096_;
+ wire _14097_;
+ wire _14098_;
+ wire _14099_;
+ wire _14100_;
+ wire _14101_;
+ wire _14102_;
+ wire _14103_;
+ wire _14104_;
+ wire _14105_;
+ wire _14106_;
+ wire _14107_;
+ wire _14108_;
+ wire _14109_;
+ wire _14110_;
+ wire _14111_;
+ wire _14112_;
+ wire _14113_;
+ wire _14114_;
+ wire _14115_;
+ wire _14116_;
+ wire _14117_;
+ wire _14118_;
+ wire _14119_;
+ wire _14120_;
+ wire _14121_;
+ wire _14122_;
+ wire _14123_;
+ wire _14124_;
+ wire _14125_;
+ wire _14126_;
+ wire _14127_;
+ wire _14128_;
+ wire _14129_;
+ wire _14130_;
+ wire _14131_;
+ wire _14132_;
+ wire _14133_;
+ wire _14134_;
+ wire _14135_;
+ wire _14136_;
+ wire _14137_;
+ wire _14138_;
+ wire _14139_;
+ wire _14140_;
+ wire _14141_;
+ wire _14142_;
+ wire _14143_;
+ wire _14144_;
+ wire _14145_;
+ wire _14146_;
+ wire _14147_;
+ wire _14148_;
+ wire _14149_;
+ wire _14150_;
+ wire _14151_;
+ wire _14152_;
+ wire _14153_;
+ wire _14154_;
+ wire _14155_;
+ wire _14156_;
+ wire _14157_;
+ wire _14158_;
+ wire _14159_;
+ wire _14160_;
+ wire _14161_;
+ wire _14162_;
+ wire _14163_;
+ wire _14164_;
+ wire _14165_;
+ wire _14166_;
+ wire _14167_;
+ wire _14168_;
+ wire _14169_;
+ wire _14170_;
+ wire _14171_;
+ wire _14172_;
+ wire _14173_;
+ wire _14174_;
+ wire _14175_;
+ wire _14176_;
+ wire _14177_;
+ wire _14178_;
+ wire _14179_;
+ wire _14180_;
+ wire _14181_;
+ wire _14182_;
+ wire _14183_;
+ wire _14184_;
+ wire _14185_;
+ wire _14186_;
+ wire _14187_;
+ wire _14188_;
+ wire _14189_;
+ wire _14190_;
+ wire _14191_;
+ wire _14192_;
+ wire _14193_;
+ wire _14194_;
+ wire _14195_;
+ wire _14196_;
+ wire _14197_;
+ wire _14198_;
+ wire _14199_;
+ wire _14200_;
+ wire _14201_;
+ wire _14202_;
+ wire _14203_;
+ wire _14204_;
+ wire _14205_;
+ wire _14206_;
+ wire _14207_;
+ wire _14208_;
+ wire _14209_;
+ wire _14210_;
+ wire _14211_;
+ wire _14212_;
+ wire _14213_;
+ wire _14214_;
+ wire _14215_;
+ wire _14216_;
+ wire _14217_;
+ wire _14218_;
+ wire _14219_;
+ wire _14220_;
+ wire _14221_;
+ wire _14222_;
+ wire _14223_;
+ wire _14224_;
+ wire _14225_;
+ wire _14226_;
+ wire _14227_;
+ wire _14228_;
+ wire _14229_;
+ wire _14230_;
+ wire _14231_;
+ wire _14232_;
+ wire _14233_;
+ wire _14234_;
+ wire _14235_;
+ wire _14236_;
+ wire _14237_;
+ wire _14238_;
+ wire _14239_;
+ wire _14240_;
+ wire _14241_;
+ wire _14242_;
+ wire _14243_;
+ wire _14244_;
+ wire _14245_;
+ wire _14246_;
+ wire _14247_;
+ wire _14248_;
+ wire _14249_;
+ wire _14250_;
+ wire _14251_;
+ wire _14252_;
+ wire _14253_;
+ wire _14254_;
+ wire _14255_;
+ wire _14256_;
+ wire _14257_;
+ wire _14258_;
+ wire _14259_;
+ wire _14260_;
+ wire _14261_;
+ wire _14262_;
+ wire _14263_;
+ wire _14264_;
+ wire _14265_;
+ wire _14266_;
+ wire _14267_;
+ wire _14268_;
+ wire _14269_;
+ wire _14270_;
+ wire _14271_;
+ wire _14272_;
+ wire _14273_;
+ wire _14274_;
+ wire _14275_;
+ wire _14276_;
+ wire _14277_;
+ wire _14278_;
+ wire _14279_;
+ wire _14280_;
+ wire _14281_;
+ wire _14282_;
+ wire _14283_;
+ wire _14284_;
+ wire _14285_;
+ wire _14286_;
+ wire _14287_;
+ wire _14288_;
+ wire _14289_;
+ wire _14290_;
+ wire _14291_;
+ wire _14292_;
+ wire _14293_;
+ wire _14294_;
+ wire _14295_;
+ wire _14296_;
+ wire _14297_;
+ wire _14298_;
+ wire _14299_;
+ wire _14300_;
+ wire _14301_;
+ wire _14302_;
+ wire _14303_;
+ wire _14304_;
+ wire _14305_;
+ wire _14306_;
+ wire _14307_;
+ wire _14308_;
+ wire _14309_;
+ wire _14310_;
+ wire _14311_;
+ wire _14312_;
+ wire _14313_;
+ wire _14314_;
+ wire _14315_;
+ wire _14316_;
+ wire _14317_;
+ wire _14318_;
+ wire _14319_;
+ wire _14320_;
+ wire _14321_;
+ wire _14322_;
+ wire _14323_;
+ wire _14324_;
+ wire _14325_;
+ wire _14326_;
+ wire _14327_;
+ wire _14328_;
+ wire _14329_;
+ wire _14330_;
+ wire _14331_;
+ wire _14332_;
+ wire _14333_;
+ wire _14334_;
+ wire _14335_;
+ wire _14336_;
+ wire _14337_;
+ wire _14338_;
+ wire _14339_;
+ wire _14340_;
+ wire _14341_;
+ wire _14342_;
+ wire _14343_;
+ wire _14344_;
+ wire _14345_;
+ wire _14346_;
+ wire _14347_;
+ wire _14348_;
+ wire _14349_;
+ wire _14350_;
+ wire _14351_;
+ wire _14352_;
+ wire _14353_;
+ wire _14354_;
+ wire _14355_;
+ wire _14356_;
+ wire _14357_;
+ wire _14358_;
+ wire _14359_;
+ wire _14360_;
+ wire _14361_;
+ wire _14362_;
+ wire _14363_;
+ wire _14364_;
+ wire _14365_;
+ wire _14366_;
+ wire _14367_;
+ wire _14368_;
+ wire _14369_;
+ wire _14370_;
+ wire _14371_;
+ wire _14372_;
+ wire _14373_;
+ wire _14374_;
+ wire _14375_;
+ wire _14376_;
+ wire _14377_;
+ wire _14378_;
+ wire _14379_;
+ wire _14380_;
+ wire _14381_;
+ wire _14382_;
+ wire _14383_;
+ wire _14384_;
+ wire _14385_;
+ wire _14386_;
+ wire _14387_;
+ wire _14388_;
+ wire _14389_;
+ wire _14390_;
+ wire _14391_;
+ wire _14392_;
+ wire _14393_;
+ wire _14394_;
+ wire _14395_;
+ wire _14396_;
+ wire _14397_;
+ wire _14398_;
+ wire _14399_;
+ wire _14400_;
+ wire _14401_;
+ wire _14402_;
+ wire _14403_;
+ wire _14404_;
+ wire _14405_;
+ wire _14406_;
+ wire _14407_;
+ wire _14408_;
+ wire _14409_;
+ wire _14410_;
+ wire _14411_;
+ wire _14412_;
+ wire _14413_;
+ wire _14414_;
+ wire _14415_;
+ wire _14416_;
+ wire _14417_;
+ wire _14418_;
+ wire _14419_;
+ wire _14420_;
+ wire _14421_;
+ wire _14422_;
+ wire _14423_;
+ wire _14424_;
+ wire _14425_;
+ wire _14426_;
+ wire _14427_;
+ wire _14428_;
+ wire _14429_;
+ wire _14430_;
+ wire _14431_;
+ wire _14432_;
+ wire _14433_;
+ wire _14434_;
+ wire _14435_;
+ wire _14436_;
+ wire _14437_;
+ wire _14438_;
+ wire _14439_;
+ wire _14440_;
+ wire _14441_;
+ wire _14442_;
+ wire _14443_;
+ wire _14444_;
+ wire _14445_;
+ wire _14446_;
+ wire _14447_;
+ wire _14448_;
+ wire _14449_;
+ wire _14450_;
+ wire _14451_;
+ wire _14452_;
+ wire _14453_;
+ wire _14454_;
+ wire _14455_;
+ wire _14456_;
+ wire _14457_;
+ wire _14458_;
+ wire _14459_;
+ wire _14460_;
+ wire _14461_;
+ wire _14462_;
+ wire _14463_;
+ wire _14464_;
+ wire _14465_;
+ wire _14466_;
+ wire _14467_;
+ wire _14468_;
+ wire _14469_;
+ wire _14470_;
+ wire _14471_;
+ wire _14472_;
+ wire _14473_;
+ wire _14474_;
+ wire _14475_;
+ wire _14476_;
+ wire _14477_;
+ wire _14478_;
+ wire _14479_;
+ wire _14480_;
+ wire _14481_;
+ wire _14482_;
+ wire _14483_;
+ wire _14484_;
+ wire _14485_;
+ wire _14486_;
+ wire _14487_;
+ wire _14488_;
+ wire _14489_;
+ wire _14490_;
+ wire _14491_;
+ wire _14492_;
+ wire _14493_;
+ wire _14494_;
+ wire _14495_;
+ wire _14496_;
+ wire _14497_;
+ wire _14498_;
+ wire _14499_;
+ wire _14500_;
+ wire _14501_;
+ wire _14502_;
+ wire _14503_;
+ wire _14504_;
+ wire _14505_;
+ wire _14506_;
+ wire _14507_;
+ wire _14508_;
+ wire _14509_;
+ wire _14510_;
+ wire _14511_;
+ wire _14512_;
+ wire _14513_;
+ wire _14514_;
+ wire _14515_;
+ wire _14516_;
+ wire _14517_;
+ wire _14518_;
+ wire _14519_;
+ wire _14520_;
+ wire _14521_;
+ wire _14522_;
+ wire _14523_;
+ wire _14524_;
+ wire _14525_;
+ wire _14526_;
+ wire _14527_;
+ wire _14528_;
+ wire _14529_;
+ wire _14530_;
+ wire _14531_;
+ wire _14532_;
+ wire _14533_;
+ wire _14534_;
+ wire _14535_;
+ wire _14536_;
+ wire _14537_;
+ wire _14538_;
+ wire _14539_;
+ wire _14540_;
+ wire _14541_;
+ wire _14542_;
+ wire _14543_;
+ wire _14544_;
+ wire _14545_;
+ wire _14546_;
+ wire _14547_;
+ wire _14548_;
+ wire _14549_;
+ wire _14550_;
+ wire _14551_;
+ wire _14552_;
+ wire _14553_;
+ wire _14554_;
+ wire _14555_;
+ wire _14556_;
+ wire _14557_;
+ wire _14558_;
+ wire _14559_;
+ wire _14560_;
+ wire _14561_;
+ wire _14562_;
+ wire _14563_;
+ wire _14564_;
+ wire _14565_;
+ wire _14566_;
+ wire _14567_;
+ wire _14568_;
+ wire _14569_;
+ wire _14570_;
+ wire _14571_;
+ wire _14572_;
+ wire _14573_;
+ wire _14574_;
+ wire _14575_;
+ wire _14576_;
+ wire _14577_;
+ wire _14578_;
+ wire _14579_;
+ wire _14580_;
+ wire _14581_;
+ wire _14582_;
+ wire _14583_;
+ wire _14584_;
+ wire _14585_;
+ wire _14586_;
+ wire _14587_;
+ wire _14588_;
+ wire _14589_;
+ wire _14590_;
+ wire _14591_;
+ wire _14592_;
+ wire _14593_;
+ wire _14594_;
+ wire _14595_;
+ wire _14596_;
+ wire _14597_;
+ wire _14598_;
+ wire _14599_;
+ wire _14600_;
+ wire _14601_;
+ wire _14602_;
+ wire _14603_;
+ wire _14604_;
+ wire _14605_;
+ wire _14606_;
+ wire _14607_;
+ wire _14608_;
+ wire _14609_;
+ wire _14610_;
+ wire _14611_;
+ wire _14612_;
+ wire _14613_;
+ wire _14614_;
+ wire _14615_;
+ wire _14616_;
+ wire _14617_;
+ wire _14618_;
+ wire _14619_;
+ wire _14620_;
+ wire _14621_;
+ wire _14622_;
+ wire _14623_;
+ wire _14624_;
+ wire _14625_;
+ wire _14626_;
+ wire _14627_;
+ wire _14628_;
+ wire _14629_;
+ wire _14630_;
+ wire _14631_;
+ wire _14632_;
+ wire _14633_;
+ wire _14634_;
+ wire _14635_;
+ wire _14636_;
+ wire _14637_;
+ wire _14638_;
+ wire _14639_;
+ wire _14640_;
+ wire _14641_;
+ wire _14642_;
+ wire _14643_;
+ wire _14644_;
+ wire _14645_;
+ wire _14646_;
+ wire _14647_;
+ wire _14648_;
+ wire _14649_;
+ wire _14650_;
+ wire _14651_;
+ wire _14652_;
+ wire _14653_;
+ wire _14654_;
+ wire _14655_;
+ wire _14656_;
+ wire _14657_;
+ wire _14658_;
+ wire _14659_;
+ wire _14660_;
+ wire _14661_;
+ wire _14662_;
+ wire _14663_;
+ wire _14664_;
+ wire _14665_;
+ wire _14666_;
+ wire _14667_;
+ wire _14668_;
+ wire _14669_;
+ wire _14670_;
+ wire _14671_;
+ wire _14672_;
+ wire _14673_;
+ wire _14674_;
+ wire _14675_;
+ wire _14676_;
+ wire _14677_;
+ wire _14678_;
+ wire _14679_;
+ wire _14680_;
+ wire _14681_;
+ wire _14682_;
+ wire _14683_;
+ wire _14684_;
+ wire _14685_;
+ wire _14686_;
+ wire _14687_;
+ wire _14688_;
+ wire _14689_;
+ wire _14690_;
+ wire _14691_;
+ wire _14692_;
+ wire _14693_;
+ wire _14694_;
+ wire _14695_;
+ wire _14696_;
+ wire _14697_;
+ wire _14698_;
+ wire _14699_;
+ wire _14700_;
+ wire _14701_;
+ wire _14702_;
+ wire _14703_;
+ wire _14704_;
+ wire _14705_;
+ wire _14706_;
+ wire _14707_;
+ wire _14708_;
+ wire _14709_;
+ wire _14710_;
+ wire _14711_;
+ wire _14712_;
+ wire _14713_;
+ wire _14714_;
+ wire _14715_;
+ wire _14716_;
+ wire _14717_;
+ wire _14718_;
+ wire _14719_;
+ wire _14720_;
+ wire _14721_;
+ wire _14722_;
+ wire _14723_;
+ wire _14724_;
+ wire _14725_;
+ wire _14726_;
+ wire _14727_;
+ wire _14728_;
+ wire _14729_;
+ wire _14730_;
+ wire _14731_;
+ wire _14732_;
+ wire _14733_;
+ wire _14734_;
+ wire _14735_;
+ wire _14736_;
+ wire _14737_;
+ wire _14738_;
+ wire _14739_;
+ wire _14740_;
+ wire _14741_;
+ wire _14742_;
+ wire _14743_;
+ wire _14744_;
+ wire _14745_;
+ wire _14746_;
+ wire _14747_;
+ wire _14748_;
+ wire _14749_;
+ wire _14750_;
+ wire _14751_;
+ wire _14752_;
+ wire _14753_;
+ wire _14754_;
+ wire _14755_;
+ wire _14756_;
+ wire _14757_;
+ wire _14758_;
+ wire _14759_;
+ wire _14760_;
+ wire _14761_;
+ wire _14762_;
+ wire _14763_;
+ wire _14764_;
+ wire _14765_;
+ wire _14766_;
+ wire _14767_;
+ wire _14768_;
+ wire _14769_;
+ wire _14770_;
+ wire _14771_;
+ wire _14772_;
+ wire _14773_;
+ wire _14774_;
+ wire _14775_;
+ wire _14776_;
+ wire _14777_;
+ wire _14778_;
+ wire _14779_;
+ wire _14780_;
+ wire _14781_;
+ wire _14782_;
+ wire _14783_;
+ wire _14784_;
+ wire _14785_;
+ wire _14786_;
+ wire _14787_;
+ wire _14788_;
+ wire _14789_;
+ wire _14790_;
+ wire _14791_;
+ wire _14792_;
+ wire _14793_;
+ wire _14794_;
+ wire _14795_;
+ wire _14796_;
+ wire _14797_;
+ wire _14798_;
+ wire _14799_;
+ wire _14800_;
+ wire _14801_;
+ wire _14802_;
+ wire _14803_;
+ wire _14804_;
+ wire _14805_;
+ wire _14806_;
+ wire _14807_;
+ wire _14808_;
+ wire _14809_;
+ wire _14810_;
+ wire _14811_;
+ wire _14812_;
+ wire _14813_;
+ wire _14814_;
+ wire _14815_;
+ wire _14816_;
+ wire _14817_;
+ wire _14818_;
+ wire _14819_;
+ wire _14820_;
+ wire _14821_;
+ wire _14822_;
+ wire _14823_;
+ wire _14824_;
+ wire _14825_;
+ wire _14826_;
+ wire _14827_;
+ wire _14828_;
+ wire _14829_;
+ wire _14830_;
+ wire _14831_;
+ wire _14832_;
+ wire _14833_;
+ wire _14834_;
+ wire _14835_;
+ wire _14836_;
+ wire _14837_;
+ wire _14838_;
+ wire _14839_;
+ wire _14840_;
+ wire _14841_;
+ wire _14842_;
+ wire _14843_;
+ wire _14844_;
+ wire _14845_;
+ wire _14846_;
+ wire _14847_;
+ wire _14848_;
+ wire _14849_;
+ wire _14850_;
+ wire _14851_;
+ wire _14852_;
+ wire _14853_;
+ wire _14854_;
+ wire _14855_;
+ wire _14856_;
+ wire _14857_;
+ wire _14858_;
+ wire _14859_;
+ wire _14860_;
+ wire _14861_;
+ wire _14862_;
+ wire _14863_;
+ wire _14864_;
+ wire _14865_;
+ wire _14866_;
+ wire _14867_;
+ wire _14868_;
+ wire _14869_;
+ wire _14870_;
+ wire _14871_;
+ wire _14872_;
+ wire _14873_;
+ wire _14874_;
+ wire _14875_;
+ wire _14876_;
+ wire _14877_;
+ wire _14878_;
+ wire _14879_;
+ wire _14880_;
+ wire _14881_;
+ wire _14882_;
+ wire _14883_;
+ wire _14884_;
+ wire _14885_;
+ wire _14886_;
+ wire _14887_;
+ wire _14888_;
+ wire _14889_;
+ wire _14890_;
+ wire _14891_;
+ wire _14892_;
+ wire _14893_;
+ wire _14894_;
+ wire _14895_;
+ wire _14896_;
+ wire _14897_;
+ wire _14898_;
+ wire _14899_;
+ wire _14900_;
+ wire _14901_;
+ wire _14902_;
+ wire _14903_;
+ wire _14904_;
+ wire _14905_;
+ wire _14906_;
+ wire _14907_;
+ wire _14908_;
+ wire _14909_;
+ wire _14910_;
+ wire _14911_;
+ wire _14912_;
+ wire _14913_;
+ wire _14914_;
+ wire _14915_;
+ wire _14916_;
+ wire _14917_;
+ wire _14918_;
+ wire _14919_;
+ wire _14920_;
+ wire _14921_;
+ wire _14922_;
+ wire _14923_;
+ wire _14924_;
+ wire _14925_;
+ wire _14926_;
+ wire _14927_;
+ wire _14928_;
+ wire _14929_;
+ wire _14930_;
+ wire _14931_;
+ wire _14932_;
+ wire _14933_;
+ wire _14934_;
+ wire _14935_;
+ wire _14936_;
+ wire _14937_;
+ wire _14938_;
+ wire _14939_;
+ wire _14940_;
+ wire _14941_;
+ wire _14942_;
+ wire _14943_;
+ wire _14944_;
+ wire _14945_;
+ wire _14946_;
+ wire _14947_;
+ wire _14948_;
+ wire _14949_;
+ wire _14950_;
+ wire _14951_;
+ wire _14952_;
+ wire _14953_;
+ wire _14954_;
+ wire _14955_;
+ wire _14956_;
+ wire _14957_;
+ wire _14958_;
+ wire _14959_;
+ wire _14960_;
+ wire _14961_;
+ wire _14962_;
+ wire _14963_;
+ wire _14964_;
+ wire _14965_;
+ wire _14966_;
+ wire _14967_;
+ wire _14968_;
+ wire _14969_;
+ wire _14970_;
+ wire _14971_;
+ wire _14972_;
+ wire _14973_;
+ wire _14974_;
+ wire _14975_;
+ wire _14976_;
+ wire _14977_;
+ wire _14978_;
+ wire _14979_;
+ wire _14980_;
+ wire _14981_;
+ wire _14982_;
+ wire _14983_;
+ wire _14984_;
+ wire _14985_;
+ wire _14986_;
+ wire _14987_;
+ wire _14988_;
+ wire _14989_;
+ wire _14990_;
+ wire _14991_;
+ wire _14992_;
+ wire _14993_;
+ wire _14994_;
+ wire _14995_;
+ wire _14996_;
+ wire _14997_;
+ wire _14998_;
+ wire _14999_;
+ wire _15000_;
+ wire _15001_;
+ wire _15002_;
+ wire _15003_;
+ wire _15004_;
+ wire _15005_;
+ wire _15006_;
+ wire _15007_;
+ wire _15008_;
+ wire _15009_;
+ wire _15010_;
+ wire _15011_;
+ wire _15012_;
+ wire _15013_;
+ wire _15014_;
+ wire _15015_;
+ wire _15016_;
+ wire _15017_;
+ wire _15018_;
+ wire _15019_;
+ wire _15020_;
+ wire _15021_;
+ wire _15022_;
+ wire _15023_;
+ wire _15024_;
+ wire _15025_;
+ wire _15026_;
+ wire _15027_;
+ wire _15028_;
+ wire _15029_;
+ wire _15030_;
+ wire _15031_;
+ wire _15032_;
+ wire _15033_;
+ wire _15034_;
+ wire _15035_;
+ wire _15036_;
+ wire _15037_;
+ wire _15038_;
+ wire _15039_;
+ wire _15040_;
+ wire _15041_;
+ wire _15042_;
+ wire _15043_;
+ wire _15044_;
+ wire _15045_;
+ wire _15046_;
+ wire _15047_;
+ wire _15048_;
+ wire _15049_;
+ wire _15050_;
+ wire _15051_;
+ wire _15052_;
+ wire _15053_;
+ wire _15054_;
+ wire _15055_;
+ wire _15056_;
+ wire _15057_;
+ wire _15058_;
+ wire _15059_;
+ wire _15060_;
+ wire _15061_;
+ wire _15062_;
+ wire _15063_;
+ wire _15064_;
+ wire _15065_;
+ wire _15066_;
+ wire _15067_;
+ wire _15068_;
+ wire _15069_;
+ wire _15070_;
+ wire _15071_;
+ wire _15072_;
+ wire _15073_;
+ wire _15074_;
+ wire _15075_;
+ wire _15076_;
+ wire _15077_;
+ wire _15078_;
+ wire _15079_;
+ wire _15080_;
+ wire _15081_;
+ wire _15082_;
+ wire _15083_;
+ wire _15084_;
+ wire _15085_;
+ wire _15086_;
+ wire _15087_;
+ wire _15088_;
+ wire _15089_;
+ wire _15090_;
+ wire _15091_;
+ wire _15092_;
+ wire _15093_;
+ wire _15094_;
+ wire _15095_;
+ wire _15096_;
+ wire _15097_;
+ wire _15098_;
+ wire _15099_;
+ wire _15100_;
+ wire _15101_;
+ wire _15102_;
+ wire _15103_;
+ wire _15104_;
+ wire _15105_;
+ wire _15106_;
+ wire _15107_;
+ wire _15108_;
+ wire _15109_;
+ wire _15110_;
+ wire _15111_;
+ wire _15112_;
+ wire _15113_;
+ wire _15114_;
+ wire _15115_;
+ wire _15116_;
+ wire _15117_;
+ wire _15118_;
+ wire _15119_;
+ wire _15120_;
+ wire _15121_;
+ wire _15122_;
+ wire _15123_;
+ wire _15124_;
+ wire _15125_;
+ wire _15126_;
+ wire _15127_;
+ wire _15128_;
+ wire _15129_;
+ wire _15130_;
+ wire _15131_;
+ wire _15132_;
+ wire _15133_;
+ wire _15134_;
+ wire _15135_;
+ wire _15136_;
+ wire _15137_;
+ wire _15138_;
+ wire _15139_;
+ wire _15140_;
+ wire _15141_;
+ wire _15142_;
+ wire _15143_;
+ wire _15144_;
+ wire _15145_;
+ wire _15146_;
+ wire _15147_;
+ wire _15148_;
+ wire _15149_;
+ wire _15150_;
+ wire _15151_;
+ wire _15152_;
+ wire _15153_;
+ wire _15154_;
+ wire _15155_;
+ wire _15156_;
+ wire _15157_;
+ wire _15158_;
+ wire _15159_;
+ wire _15160_;
+ wire _15161_;
+ wire _15162_;
+ wire _15163_;
+ wire _15164_;
+ wire _15165_;
+ wire _15166_;
+ wire _15167_;
+ wire _15168_;
+ wire _15169_;
+ wire _15170_;
+ wire _15171_;
+ wire _15172_;
+ wire _15173_;
+ wire _15174_;
+ wire _15175_;
+ wire _15176_;
+ wire _15177_;
+ wire _15178_;
+ wire _15179_;
+ wire _15180_;
+ wire _15181_;
+ wire _15182_;
+ wire _15183_;
+ wire _15184_;
+ wire _15185_;
+ wire _15186_;
+ wire _15187_;
+ wire _15188_;
+ wire _15189_;
+ wire _15190_;
+ wire _15191_;
+ wire _15192_;
+ wire _15193_;
+ wire _15194_;
+ wire _15195_;
+ wire _15196_;
+ wire _15197_;
+ wire _15198_;
+ wire _15199_;
+ wire _15200_;
+ wire _15201_;
+ wire _15202_;
+ wire _15203_;
+ wire _15204_;
+ wire _15205_;
+ wire _15206_;
+ wire _15207_;
+ wire _15208_;
+ wire _15209_;
+ wire _15210_;
+ wire _15211_;
+ wire _15212_;
+ wire _15213_;
+ wire _15214_;
+ wire _15215_;
+ wire _15216_;
+ wire _15217_;
+ wire _15218_;
+ wire _15219_;
+ wire _15220_;
+ wire _15221_;
+ wire _15222_;
+ wire _15223_;
+ wire _15224_;
+ wire _15225_;
+ wire _15226_;
+ wire _15227_;
+ wire _15228_;
+ wire _15229_;
+ wire _15230_;
+ wire _15231_;
+ wire _15232_;
+ wire _15233_;
+ wire _15234_;
+ wire _15235_;
+ wire _15236_;
+ wire _15237_;
+ wire _15238_;
+ wire _15239_;
+ wire _15240_;
+ wire _15241_;
+ wire _15242_;
+ wire _15243_;
+ wire _15244_;
+ wire _15245_;
+ wire _15246_;
+ wire _15247_;
+ wire _15248_;
+ wire _15249_;
+ wire _15250_;
+ wire _15251_;
+ wire _15252_;
+ wire _15253_;
+ wire _15254_;
+ wire _15255_;
+ wire _15256_;
+ wire _15257_;
+ wire _15258_;
+ wire _15259_;
+ wire _15260_;
+ wire _15261_;
+ wire _15262_;
+ wire _15263_;
+ wire _15264_;
+ wire _15265_;
+ wire _15266_;
+ wire _15267_;
+ wire _15268_;
+ wire _15269_;
+ wire _15270_;
+ wire _15271_;
+ wire _15272_;
+ wire _15273_;
+ wire _15274_;
+ wire _15275_;
+ wire _15276_;
+ wire _15277_;
+ wire _15278_;
+ wire _15279_;
+ wire _15280_;
+ wire _15281_;
+ wire _15282_;
+ wire _15283_;
+ wire _15284_;
+ wire _15285_;
+ wire _15286_;
+ wire _15287_;
+ wire _15288_;
+ wire _15289_;
+ wire _15290_;
+ wire _15291_;
+ wire _15292_;
+ wire _15293_;
+ wire _15294_;
+ wire _15295_;
+ wire _15296_;
+ wire _15297_;
+ wire _15298_;
+ wire _15299_;
+ wire _15300_;
+ wire _15301_;
+ wire _15302_;
+ wire _15303_;
+ wire _15304_;
+ wire _15305_;
+ wire _15306_;
+ wire _15307_;
+ wire _15308_;
+ wire _15309_;
+ wire _15310_;
+ wire _15311_;
+ wire _15312_;
+ wire _15313_;
+ wire _15314_;
+ wire _15315_;
+ wire _15316_;
+ wire _15317_;
+ wire _15318_;
+ wire _15319_;
+ wire _15320_;
+ wire _15321_;
+ wire _15322_;
+ wire _15323_;
+ wire _15324_;
+ wire _15325_;
+ wire _15326_;
+ wire _15327_;
+ wire _15328_;
+ wire _15329_;
+ wire _15330_;
+ wire _15331_;
+ wire _15332_;
+ wire _15333_;
+ wire _15334_;
+ wire _15335_;
+ wire _15336_;
+ wire _15337_;
+ wire _15338_;
+ wire _15339_;
+ wire _15340_;
+ wire _15341_;
+ wire _15342_;
+ wire _15343_;
+ wire _15344_;
+ wire _15345_;
+ wire _15346_;
+ wire _15347_;
+ wire _15348_;
+ wire _15349_;
+ wire _15350_;
+ wire _15351_;
+ wire _15352_;
+ wire _15353_;
+ wire _15354_;
+ wire _15355_;
+ wire _15356_;
+ wire _15357_;
+ wire _15358_;
+ wire _15359_;
+ wire _15360_;
+ wire _15361_;
+ wire _15362_;
+ wire _15363_;
+ wire _15364_;
+ wire _15365_;
+ wire _15366_;
+ wire _15367_;
+ wire _15368_;
+ wire _15369_;
+ wire _15370_;
+ wire _15371_;
+ wire _15372_;
+ wire _15373_;
+ wire _15374_;
+ wire _15375_;
+ wire _15376_;
+ wire _15377_;
+ wire _15378_;
+ wire _15379_;
+ wire _15380_;
+ wire _15381_;
+ wire _15382_;
+ wire _15383_;
+ wire _15384_;
+ wire _15385_;
+ wire _15386_;
+ wire _15387_;
+ wire _15388_;
+ wire _15389_;
+ wire _15390_;
+ wire _15391_;
+ wire _15392_;
+ wire _15393_;
+ wire _15394_;
+ wire _15395_;
+ wire _15396_;
+ wire _15397_;
+ wire _15398_;
+ wire _15399_;
+ wire _15400_;
+ wire _15401_;
+ wire _15402_;
+ wire _15403_;
+ wire _15404_;
+ wire _15405_;
+ wire _15406_;
+ wire _15407_;
+ wire _15408_;
+ wire _15409_;
+ wire _15410_;
+ wire _15411_;
+ wire _15412_;
+ wire _15413_;
+ wire _15414_;
+ wire _15415_;
+ wire _15416_;
+ wire _15417_;
+ wire _15418_;
+ wire _15419_;
+ wire _15420_;
+ wire _15421_;
+ wire _15422_;
+ wire _15423_;
+ wire _15424_;
+ wire _15425_;
+ wire _15426_;
+ wire _15427_;
+ wire _15428_;
+ wire _15429_;
+ wire _15430_;
+ wire _15431_;
+ wire _15432_;
+ wire _15433_;
+ wire _15434_;
+ wire _15435_;
+ wire _15436_;
+ wire _15437_;
+ wire _15438_;
+ wire _15439_;
+ wire _15440_;
+ wire _15441_;
+ wire _15442_;
+ wire _15443_;
+ wire _15444_;
+ wire _15445_;
+ wire _15446_;
+ wire _15447_;
+ wire _15448_;
+ wire _15449_;
+ wire _15450_;
+ wire _15451_;
+ wire _15452_;
+ wire _15453_;
+ wire _15454_;
+ wire _15455_;
+ wire _15456_;
+ wire _15457_;
+ wire _15458_;
+ wire _15459_;
+ wire _15460_;
+ wire _15461_;
+ wire _15462_;
+ wire _15463_;
+ wire _15464_;
+ wire _15465_;
+ wire _15466_;
+ wire _15467_;
+ wire _15468_;
+ wire _15469_;
+ wire _15470_;
+ wire _15471_;
+ wire _15472_;
+ wire _15473_;
+ wire _15474_;
+ wire _15475_;
+ wire _15476_;
+ wire _15477_;
+ wire _15478_;
+ wire _15479_;
+ wire _15480_;
+ wire _15481_;
+ wire _15482_;
+ wire _15483_;
+ wire _15484_;
+ wire _15485_;
+ wire _15486_;
+ wire _15487_;
+ wire _15488_;
+ wire _15489_;
+ wire _15490_;
+ wire _15491_;
+ wire _15492_;
+ wire _15493_;
+ wire _15494_;
+ wire _15495_;
+ wire _15496_;
+ wire _15497_;
+ wire _15498_;
+ wire _15499_;
+ wire _15500_;
+ wire _15501_;
+ wire _15502_;
+ wire _15503_;
+ wire _15504_;
+ wire _15505_;
+ wire _15506_;
+ wire _15507_;
+ wire _15508_;
+ wire _15509_;
+ wire _15510_;
+ wire _15511_;
+ wire _15512_;
+ wire _15513_;
+ wire _15514_;
+ wire _15515_;
+ wire _15516_;
+ wire _15517_;
+ wire _15518_;
+ wire _15519_;
+ wire _15520_;
+ wire _15521_;
+ wire _15522_;
+ wire _15523_;
+ wire _15524_;
+ wire _15525_;
+ wire _15526_;
+ wire _15527_;
+ wire _15528_;
+ wire _15529_;
+ wire _15530_;
+ wire _15531_;
+ wire _15532_;
+ wire _15533_;
+ wire _15534_;
+ wire _15535_;
+ wire _15536_;
+ wire _15537_;
+ wire _15538_;
+ wire _15539_;
+ wire _15540_;
+ wire _15541_;
+ wire _15542_;
+ wire _15543_;
+ wire _15544_;
+ wire _15545_;
+ wire _15546_;
+ wire _15547_;
+ wire _15548_;
+ wire _15549_;
+ wire _15550_;
+ wire _15551_;
+ wire _15552_;
+ wire _15553_;
+ wire _15554_;
+ wire _15555_;
+ wire _15556_;
+ wire _15557_;
+ wire _15558_;
+ wire _15559_;
+ wire _15560_;
+ wire _15561_;
+ wire _15562_;
+ wire _15563_;
+ wire _15564_;
+ wire _15565_;
+ wire _15566_;
+ wire _15567_;
+ wire _15568_;
+ wire _15569_;
+ wire _15570_;
+ wire _15571_;
+ wire _15572_;
+ wire _15573_;
+ wire _15574_;
+ wire _15575_;
+ wire _15576_;
+ wire _15577_;
+ wire _15578_;
+ wire _15579_;
+ wire _15580_;
+ wire _15581_;
+ wire _15582_;
+ wire _15583_;
+ wire _15584_;
+ wire _15585_;
+ wire _15586_;
+ wire _15587_;
+ wire _15588_;
+ wire _15589_;
+ wire _15590_;
+ wire _15591_;
+ wire _15592_;
+ wire _15593_;
+ wire _15594_;
+ wire _15595_;
+ wire _15596_;
+ wire _15597_;
+ wire _15598_;
+ wire _15599_;
+ wire _15600_;
+ wire _15601_;
+ wire _15602_;
+ wire _15603_;
+ wire _15604_;
+ wire _15605_;
+ wire _15606_;
+ wire _15607_;
+ wire _15608_;
+ wire _15609_;
+ wire _15610_;
+ wire _15611_;
+ wire _15612_;
+ wire _15613_;
+ wire _15614_;
+ wire _15615_;
+ wire _15616_;
+ wire _15617_;
+ wire _15618_;
+ wire _15619_;
+ wire _15620_;
+ wire _15621_;
+ wire _15622_;
+ wire _15623_;
+ wire _15624_;
+ wire _15625_;
+ wire _15626_;
+ wire _15627_;
+ wire _15628_;
+ wire _15629_;
+ wire _15630_;
+ wire _15631_;
+ wire _15632_;
+ wire _15633_;
+ wire _15634_;
+ wire _15635_;
+ wire _15636_;
+ wire _15637_;
+ wire _15638_;
+ wire _15639_;
+ wire _15640_;
+ wire _15641_;
+ wire _15642_;
+ wire _15643_;
+ wire _15644_;
+ wire _15645_;
+ wire _15646_;
+ wire _15647_;
+ wire _15648_;
+ wire _15649_;
+ wire _15650_;
+ wire _15651_;
+ wire _15652_;
+ wire _15653_;
+ wire _15654_;
+ wire _15655_;
+ wire _15656_;
+ wire _15657_;
+ wire _15658_;
+ wire _15659_;
+ wire _15660_;
+ wire _15661_;
+ wire _15662_;
+ wire _15663_;
+ wire _15664_;
+ wire _15665_;
+ wire _15666_;
+ wire _15667_;
+ wire _15668_;
+ wire _15669_;
+ wire _15670_;
+ wire _15671_;
+ wire _15672_;
+ wire _15673_;
+ wire _15674_;
+ wire _15675_;
+ wire _15676_;
+ wire _15677_;
+ wire _15678_;
+ wire _15679_;
+ wire _15680_;
+ wire _15681_;
+ wire _15682_;
+ wire _15683_;
+ wire _15684_;
+ wire _15685_;
+ wire _15686_;
+ wire _15687_;
+ wire _15688_;
+ wire _15689_;
+ wire _15690_;
+ wire _15691_;
+ wire _15692_;
+ wire _15693_;
+ wire _15694_;
+ wire _15695_;
+ wire _15696_;
+ wire _15697_;
+ wire _15698_;
+ wire _15699_;
+ wire _15700_;
+ wire _15701_;
+ wire _15702_;
+ wire _15703_;
+ wire _15704_;
+ wire _15705_;
+ wire _15706_;
+ wire _15707_;
+ wire _15708_;
+ wire _15709_;
+ wire _15710_;
+ wire _15711_;
+ wire _15712_;
+ wire _15713_;
+ wire _15714_;
+ wire _15715_;
+ wire _15716_;
+ wire _15717_;
+ wire _15718_;
+ wire _15719_;
+ wire _15720_;
+ wire _15721_;
+ wire _15722_;
+ wire _15723_;
+ wire _15724_;
+ wire _15725_;
+ wire _15726_;
+ wire _15727_;
+ wire _15728_;
+ wire _15729_;
+ wire _15730_;
+ wire _15731_;
+ wire _15732_;
+ wire _15733_;
+ wire _15734_;
+ wire _15735_;
+ wire _15736_;
+ wire _15737_;
+ wire _15738_;
+ wire _15739_;
+ wire _15740_;
+ wire _15741_;
+ wire _15742_;
+ wire _15743_;
+ wire _15744_;
+ wire _15745_;
+ wire _15746_;
+ wire _15747_;
+ wire _15748_;
+ wire _15749_;
+ wire _15750_;
+ wire _15751_;
+ wire _15752_;
+ wire _15753_;
+ wire _15754_;
+ wire _15755_;
+ wire _15756_;
+ wire _15757_;
+ wire _15758_;
+ wire _15759_;
+ wire _15760_;
+ wire _15761_;
+ wire _15762_;
+ wire _15763_;
+ wire _15764_;
+ wire _15765_;
+ wire _15766_;
+ wire _15767_;
+ wire _15768_;
+ wire _15769_;
+ wire _15770_;
+ wire _15771_;
+ wire _15772_;
+ wire _15773_;
+ wire _15774_;
+ wire _15775_;
+ wire _15776_;
+ wire _15777_;
+ wire _15778_;
+ wire _15779_;
+ wire _15780_;
+ wire _15781_;
+ wire _15782_;
+ wire _15783_;
+ wire _15784_;
+ wire _15785_;
+ wire _15786_;
+ wire _15787_;
+ wire _15788_;
+ wire _15789_;
+ wire _15790_;
+ wire _15791_;
+ wire _15792_;
+ wire _15793_;
+ wire _15794_;
+ wire _15795_;
+ wire _15796_;
+ wire _15797_;
+ wire _15798_;
+ wire _15799_;
+ wire _15800_;
+ wire _15801_;
+ wire _15802_;
+ wire _15803_;
+ wire _15804_;
+ wire _15805_;
+ wire _15806_;
+ wire _15807_;
+ wire _15808_;
+ wire _15809_;
+ wire _15810_;
+ wire _15811_;
+ wire _15812_;
+ wire _15813_;
+ wire _15814_;
+ wire _15815_;
+ wire _15816_;
+ wire _15817_;
+ wire _15818_;
+ wire _15819_;
+ wire _15820_;
+ wire _15821_;
+ wire _15822_;
+ wire _15823_;
+ wire _15824_;
+ wire _15825_;
+ wire _15826_;
+ wire _15827_;
+ wire _15828_;
+ wire _15829_;
+ wire _15830_;
+ wire _15831_;
+ wire _15832_;
+ wire _15833_;
+ wire _15834_;
+ wire _15835_;
+ wire _15836_;
+ wire _15837_;
+ wire _15838_;
+ wire _15839_;
+ wire _15840_;
+ wire _15841_;
+ wire _15842_;
+ wire _15843_;
+ wire _15844_;
+ wire _15845_;
+ wire _15846_;
+ wire _15847_;
+ wire _15848_;
+ wire _15849_;
+ wire _15850_;
+ wire _15851_;
+ wire _15852_;
+ wire _15853_;
+ wire _15854_;
+ wire _15855_;
+ wire _15856_;
+ wire _15857_;
+ wire _15858_;
+ wire _15859_;
+ wire _15860_;
+ wire _15861_;
+ wire _15862_;
+ wire _15863_;
+ wire _15864_;
+ wire _15865_;
+ wire _15866_;
+ wire _15867_;
+ wire _15868_;
+ wire _15869_;
+ wire _15870_;
+ wire _15871_;
+ wire _15872_;
+ wire _15873_;
+ wire _15874_;
+ wire _15875_;
+ wire _15876_;
+ wire _15877_;
+ wire _15878_;
+ wire _15879_;
+ wire _15880_;
+ wire _15881_;
+ wire _15882_;
+ wire _15883_;
+ wire _15884_;
+ wire _15885_;
+ wire _15886_;
+ wire _15887_;
+ wire _15888_;
+ wire _15889_;
+ wire _15890_;
+ wire _15891_;
+ wire _15892_;
+ wire _15893_;
+ wire _15894_;
+ wire _15895_;
+ wire _15896_;
+ wire _15897_;
+ wire _15898_;
+ wire _15899_;
+ wire _15900_;
+ wire _15901_;
+ wire _15902_;
+ wire _15903_;
+ wire _15904_;
+ wire _15905_;
+ wire _15906_;
+ wire _15907_;
+ wire _15908_;
+ wire _15909_;
+ wire _15910_;
+ wire _15911_;
+ wire _15912_;
+ wire _15913_;
+ wire _15914_;
+ wire _15915_;
+ wire _15916_;
+ wire _15917_;
+ wire _15918_;
+ wire _15919_;
+ wire _15920_;
+ wire _15921_;
+ wire _15922_;
+ wire _15923_;
+ wire _15924_;
+ wire _15925_;
+ wire _15926_;
+ wire _15927_;
+ wire _15928_;
+ wire _15929_;
+ wire _15930_;
+ wire _15931_;
+ wire _15932_;
+ wire _15933_;
+ wire _15934_;
+ wire _15935_;
+ wire _15936_;
+ wire _15937_;
+ wire _15938_;
+ wire _15939_;
+ wire _15940_;
+ wire _15941_;
+ wire _15942_;
+ wire _15943_;
+ wire _15944_;
+ wire _15945_;
+ wire _15946_;
+ wire _15947_;
+ wire _15948_;
+ wire _15949_;
+ wire _15950_;
+ wire _15951_;
+ wire _15952_;
+ wire _15953_;
+ wire _15954_;
+ wire _15955_;
+ wire _15956_;
+ wire _15957_;
+ wire _15958_;
+ wire _15959_;
+ wire _15960_;
+ wire _15961_;
+ wire _15962_;
+ wire _15963_;
+ wire _15964_;
+ wire _15965_;
+ wire _15966_;
+ wire _15967_;
+ wire _15968_;
+ wire _15969_;
+ wire _15970_;
+ wire _15971_;
+ wire _15972_;
+ wire _15973_;
+ wire _15974_;
+ wire _15975_;
+ wire _15976_;
+ wire _15977_;
+ wire _15978_;
+ wire _15979_;
+ wire _15980_;
+ wire _15981_;
+ wire _15982_;
+ wire _15983_;
+ wire _15984_;
+ wire _15985_;
+ wire _15986_;
+ wire _15987_;
+ wire _15988_;
+ wire _15989_;
+ wire _15990_;
+ wire _15991_;
+ wire _15992_;
+ wire _15993_;
+ wire _15994_;
+ wire _15995_;
+ wire _15996_;
+ wire _15997_;
+ wire _15998_;
+ wire _15999_;
+ wire _16000_;
+ wire _16001_;
+ wire _16002_;
+ wire _16003_;
+ wire _16004_;
+ wire _16005_;
+ wire _16006_;
+ wire _16007_;
+ wire _16008_;
+ wire _16009_;
+ wire _16010_;
+ wire _16011_;
+ wire _16012_;
+ wire _16013_;
+ wire _16014_;
+ wire _16015_;
+ wire _16016_;
+ wire _16017_;
+ wire _16018_;
+ wire _16019_;
+ wire _16020_;
+ wire _16021_;
+ wire _16022_;
+ wire _16023_;
+ wire _16024_;
+ wire _16025_;
+ wire _16026_;
+ wire _16027_;
+ wire _16028_;
+ wire _16029_;
+ wire _16030_;
+ wire _16031_;
+ wire _16032_;
+ wire _16033_;
+ wire _16034_;
+ wire _16035_;
+ wire _16036_;
+ wire _16037_;
+ wire _16038_;
+ wire _16039_;
+ wire _16040_;
+ wire _16041_;
+ wire _16042_;
+ wire _16043_;
+ wire _16044_;
+ wire _16045_;
+ wire _16046_;
+ wire _16047_;
+ wire _16048_;
+ wire _16049_;
+ wire _16050_;
+ wire _16051_;
+ wire _16052_;
+ wire _16053_;
+ wire _16054_;
+ wire _16055_;
+ wire _16056_;
+ wire _16057_;
+ wire _16058_;
+ wire _16059_;
+ wire _16060_;
+ wire _16061_;
+ wire _16062_;
+ wire _16063_;
+ wire _16064_;
+ wire _16065_;
+ wire _16066_;
+ wire _16067_;
+ wire _16068_;
+ wire _16069_;
+ wire _16070_;
+ wire _16071_;
+ wire _16072_;
+ wire _16073_;
+ wire _16074_;
+ wire _16075_;
+ wire _16076_;
+ wire _16077_;
+ wire _16078_;
+ wire _16079_;
+ wire _16080_;
+ wire _16081_;
+ wire _16082_;
+ wire _16083_;
+ wire _16084_;
+ wire _16085_;
+ wire _16086_;
+ wire _16087_;
+ wire _16088_;
+ wire _16089_;
+ wire _16090_;
+ wire _16091_;
+ wire _16092_;
+ wire _16093_;
+ wire _16094_;
+ wire _16095_;
+ wire _16096_;
+ wire _16097_;
+ wire _16098_;
+ wire _16099_;
+ wire _16100_;
+ wire _16101_;
+ wire _16102_;
+ wire _16103_;
+ wire _16104_;
+ wire _16105_;
+ wire _16106_;
+ wire _16107_;
+ wire _16108_;
+ wire _16109_;
+ wire _16110_;
+ wire _16111_;
+ wire _16112_;
+ wire _16113_;
+ wire _16114_;
+ wire _16115_;
+ wire _16116_;
+ wire _16117_;
+ wire _16118_;
+ wire _16119_;
+ wire _16120_;
+ wire _16121_;
+ wire _16122_;
+ wire _16123_;
+ wire _16124_;
+ wire _16125_;
+ wire _16126_;
+ wire _16127_;
+ wire _16128_;
+ wire _16129_;
+ wire _16130_;
+ wire _16131_;
+ wire _16132_;
+ wire _16133_;
+ wire _16134_;
+ wire _16135_;
+ wire _16136_;
+ wire _16137_;
+ wire _16138_;
+ wire _16139_;
+ wire _16140_;
+ wire _16141_;
+ wire _16142_;
+ wire _16143_;
+ wire _16144_;
+ wire _16145_;
+ wire _16146_;
+ wire _16147_;
+ wire _16148_;
+ wire _16149_;
+ wire _16150_;
+ wire _16151_;
+ wire _16152_;
+ wire _16153_;
+ wire _16154_;
+ wire _16155_;
+ wire _16156_;
+ wire _16157_;
+ wire _16158_;
+ wire _16159_;
+ wire _16160_;
+ wire _16161_;
+ wire _16162_;
+ wire _16163_;
+ wire _16164_;
+ wire _16165_;
+ wire _16166_;
+ wire _16167_;
+ wire _16168_;
+ wire _16169_;
+ wire _16170_;
+ wire _16171_;
+ wire _16172_;
+ wire _16173_;
+ wire _16174_;
+ wire _16175_;
+ wire _16176_;
+ wire _16177_;
+ wire _16178_;
+ wire _16179_;
+ wire _16180_;
+ wire _16181_;
+ wire _16182_;
+ wire _16183_;
+ wire _16184_;
+ wire _16185_;
+ wire _16186_;
+ wire _16187_;
+ wire _16188_;
+ wire _16189_;
+ wire _16190_;
+ wire _16191_;
+ wire _16192_;
+ wire _16193_;
+ wire _16194_;
+ wire _16195_;
+ wire _16196_;
+ wire _16197_;
+ wire _16198_;
+ wire _16199_;
+ wire _16200_;
+ wire _16201_;
+ wire _16202_;
+ wire _16203_;
+ wire _16204_;
+ wire _16205_;
+ wire _16206_;
+ wire _16207_;
+ wire _16208_;
+ wire _16209_;
+ wire _16210_;
+ wire _16211_;
+ wire _16212_;
+ wire _16213_;
+ wire _16214_;
+ wire _16215_;
+ wire _16216_;
+ wire _16217_;
+ wire _16218_;
+ wire _16219_;
+ wire _16220_;
+ wire _16221_;
+ wire _16222_;
+ wire _16223_;
+ wire _16224_;
+ wire _16225_;
+ wire _16226_;
+ wire _16227_;
+ wire _16228_;
+ wire _16229_;
+ wire _16230_;
+ wire _16231_;
+ wire _16232_;
+ wire _16233_;
+ wire _16234_;
+ wire _16235_;
+ wire _16236_;
+ wire _16237_;
+ wire _16238_;
+ wire _16239_;
+ wire _16240_;
+ wire _16241_;
+ wire _16242_;
+ wire _16243_;
+ wire _16244_;
+ wire _16245_;
+ wire _16246_;
+ wire _16247_;
+ wire _16248_;
+ wire _16249_;
+ wire _16250_;
+ wire _16251_;
+ wire _16252_;
+ wire _16253_;
+ wire _16254_;
+ wire _16255_;
+ wire _16256_;
+ wire _16257_;
+ wire _16258_;
+ wire _16259_;
+ wire _16260_;
+ wire _16261_;
+ wire _16262_;
+ wire _16263_;
+ wire _16264_;
+ wire _16265_;
+ wire _16266_;
+ wire _16267_;
+ wire _16268_;
+ wire _16269_;
+ wire _16270_;
+ wire _16271_;
+ wire _16272_;
+ wire _16273_;
+ wire _16274_;
+ wire _16275_;
+ wire _16276_;
+ wire _16277_;
+ wire _16278_;
+ wire _16279_;
+ wire _16280_;
+ wire _16281_;
+ wire _16282_;
+ wire _16283_;
+ wire _16284_;
+ wire _16285_;
+ wire _16286_;
+ wire _16287_;
+ wire _16288_;
+ wire _16289_;
+ wire _16290_;
+ wire _16291_;
+ wire _16292_;
+ wire _16293_;
+ wire _16294_;
+ wire _16295_;
+ wire _16296_;
+ wire _16297_;
+ wire _16298_;
+ wire _16299_;
+ wire _16300_;
+ wire _16301_;
+ wire _16302_;
+ wire _16303_;
+ wire _16304_;
+ wire _16305_;
+ wire _16306_;
+ wire _16307_;
+ wire _16308_;
+ wire _16309_;
+ wire _16310_;
+ wire _16311_;
+ wire _16312_;
+ wire _16313_;
+ wire _16314_;
+ wire _16315_;
+ wire _16316_;
+ wire _16317_;
+ wire _16318_;
+ wire _16319_;
+ wire _16320_;
+ wire _16321_;
+ wire _16322_;
+ wire _16323_;
+ wire _16324_;
+ wire _16325_;
+ wire _16326_;
+ wire _16327_;
+ wire _16328_;
+ wire _16329_;
+ wire _16330_;
+ wire _16331_;
+ wire _16332_;
+ wire _16333_;
+ wire _16334_;
+ wire _16335_;
+ wire _16336_;
+ wire _16337_;
+ wire _16338_;
+ wire _16339_;
+ wire _16340_;
+ wire _16341_;
+ wire _16342_;
+ wire _16343_;
+ wire _16344_;
+ wire _16345_;
+ wire _16346_;
+ wire _16347_;
+ wire _16348_;
+ wire _16349_;
+ wire _16350_;
+ wire _16351_;
+ wire _16352_;
+ wire _16353_;
+ wire _16354_;
+ wire _16355_;
+ wire _16356_;
+ wire _16357_;
+ wire _16358_;
+ wire _16359_;
+ wire _16360_;
+ wire _16361_;
+ wire _16362_;
+ wire _16363_;
+ wire _16364_;
+ wire _16365_;
+ wire _16366_;
+ wire _16367_;
+ wire _16368_;
+ wire _16369_;
+ wire _16370_;
+ wire _16371_;
+ wire _16372_;
+ wire _16373_;
+ wire _16374_;
+ wire _16375_;
+ wire _16376_;
+ wire _16377_;
+ wire _16378_;
+ wire _16379_;
+ wire _16380_;
+ wire _16381_;
+ wire _16382_;
+ wire _16383_;
+ wire _16384_;
+ wire _16385_;
+ wire _16386_;
+ wire _16387_;
+ wire _16388_;
+ wire _16389_;
+ wire _16390_;
+ wire _16391_;
+ wire _16392_;
+ wire _16393_;
+ wire _16394_;
+ wire _16395_;
+ wire _16396_;
+ wire _16397_;
+ wire _16398_;
+ wire _16399_;
+ wire _16400_;
+ wire _16401_;
+ wire _16402_;
+ wire _16403_;
+ wire _16404_;
+ wire _16405_;
+ wire _16406_;
+ wire _16407_;
+ wire _16408_;
+ wire _16409_;
+ wire _16410_;
+ wire _16411_;
+ wire _16412_;
+ wire _16413_;
+ wire _16414_;
+ wire _16415_;
+ wire _16416_;
+ wire _16417_;
+ wire _16418_;
+ wire _16419_;
+ wire _16420_;
+ wire _16421_;
+ wire _16422_;
+ wire _16423_;
+ wire _16424_;
+ wire _16425_;
+ wire _16426_;
+ wire _16427_;
+ wire _16428_;
+ wire _16429_;
+ wire _16430_;
+ wire _16431_;
+ wire _16432_;
+ wire _16433_;
+ wire _16434_;
+ wire _16435_;
+ wire _16436_;
+ wire _16437_;
+ wire _16438_;
+ wire _16439_;
+ wire _16440_;
+ wire _16441_;
+ wire _16442_;
+ wire _16443_;
+ wire _16444_;
+ wire _16445_;
+ wire _16446_;
+ wire _16447_;
+ wire _16448_;
+ wire _16449_;
+ wire _16450_;
+ wire _16451_;
+ wire _16452_;
+ wire _16453_;
+ wire _16454_;
+ wire _16455_;
+ wire _16456_;
+ wire _16457_;
+ wire _16458_;
+ wire _16459_;
+ wire _16460_;
+ wire _16461_;
+ wire _16462_;
+ wire _16463_;
+ wire net2341;
+ wire net2342;
+ wire net2343;
+ wire net2287;
+ wire net2288;
+ wire net2289;
+ wire net2290;
+ wire net2291;
+ wire net2292;
+ wire net2293;
+ wire net2294;
+ wire net2295;
+ wire net2296;
+ wire net2297;
+ wire \clock_ctrl.core_clk ;
+ wire \clock_ctrl.divider.N[0] ;
+ wire \clock_ctrl.divider.N[1] ;
+ wire \clock_ctrl.divider.N[2] ;
+ wire \clock_ctrl.divider.even_0.N[0] ;
+ wire \clock_ctrl.divider.even_0.N[1] ;
+ wire \clock_ctrl.divider.even_0.N[2] ;
+ wire \clock_ctrl.divider.even_0.clk ;
+ wire \clock_ctrl.divider.even_0.counter[0] ;
+ wire \clock_ctrl.divider.even_0.counter[1] ;
+ wire \clock_ctrl.divider.even_0.counter[2] ;
+ wire \clock_ctrl.divider.even_0.out_counter ;
+ wire \clock_ctrl.divider.even_0.resetb ;
+ wire \clock_ctrl.divider.odd_0.counter2[0] ;
+ wire \clock_ctrl.divider.odd_0.counter2[1] ;
+ wire \clock_ctrl.divider.odd_0.counter2[2] ;
+ wire \clock_ctrl.divider.odd_0.counter[0] ;
+ wire \clock_ctrl.divider.odd_0.counter[1] ;
+ wire \clock_ctrl.divider.odd_0.counter[2] ;
+ wire \clock_ctrl.divider.odd_0.initial_begin[0] ;
+ wire \clock_ctrl.divider.odd_0.initial_begin[1] ;
+ wire \clock_ctrl.divider.odd_0.initial_begin[2] ;
+ wire \clock_ctrl.divider.odd_0.old_N[0] ;
+ wire \clock_ctrl.divider.odd_0.old_N[1] ;
+ wire \clock_ctrl.divider.odd_0.old_N[2] ;
+ wire \clock_ctrl.divider.odd_0.out_counter ;
+ wire \clock_ctrl.divider.odd_0.out_counter2 ;
+ wire \clock_ctrl.divider.odd_0.rst_pulse ;
+ wire \clock_ctrl.divider.out ;
+ wire \clock_ctrl.divider.syncNp[0] ;
+ wire \clock_ctrl.divider.syncNp[1] ;
+ wire \clock_ctrl.divider.syncNp[2] ;
+ wire \clock_ctrl.divider2.N[0] ;
+ wire \clock_ctrl.divider2.N[1] ;
+ wire \clock_ctrl.divider2.N[2] ;
+ wire \clock_ctrl.divider2.even_0.N[0] ;
+ wire \clock_ctrl.divider2.even_0.N[1] ;
+ wire \clock_ctrl.divider2.even_0.N[2] ;
+ wire \clock_ctrl.divider2.even_0.clk ;
+ wire \clock_ctrl.divider2.even_0.counter[0] ;
+ wire \clock_ctrl.divider2.even_0.counter[1] ;
+ wire \clock_ctrl.divider2.even_0.counter[2] ;
+ wire \clock_ctrl.divider2.even_0.out_counter ;
+ wire \clock_ctrl.divider2.odd_0.counter2[0] ;
+ wire \clock_ctrl.divider2.odd_0.counter2[1] ;
+ wire \clock_ctrl.divider2.odd_0.counter2[2] ;
+ wire \clock_ctrl.divider2.odd_0.counter[0] ;
+ wire \clock_ctrl.divider2.odd_0.counter[1] ;
+ wire \clock_ctrl.divider2.odd_0.counter[2] ;
+ wire \clock_ctrl.divider2.odd_0.initial_begin[0] ;
+ wire \clock_ctrl.divider2.odd_0.initial_begin[1] ;
+ wire \clock_ctrl.divider2.odd_0.initial_begin[2] ;
+ wire \clock_ctrl.divider2.odd_0.old_N[0] ;
+ wire \clock_ctrl.divider2.odd_0.old_N[1] ;
+ wire \clock_ctrl.divider2.odd_0.old_N[2] ;
+ wire \clock_ctrl.divider2.odd_0.out_counter ;
+ wire \clock_ctrl.divider2.odd_0.out_counter2 ;
+ wire \clock_ctrl.divider2.odd_0.rst_pulse ;
+ wire \clock_ctrl.divider2.out ;
+ wire \clock_ctrl.divider2.syncNp[0] ;
+ wire \clock_ctrl.divider2.syncNp[1] ;
+ wire \clock_ctrl.divider2.syncNp[2] ;
+ wire \clock_ctrl.ext_clk_sel ;
+ wire \clock_ctrl.ext_clk_syncd ;
+ wire \clock_ctrl.ext_clk_syncd_pre ;
+ wire \clock_ctrl.ext_reset ;
+ wire \clock_ctrl.pll_clk_sel ;
+ wire \clock_ctrl.porb ;
+ wire \clock_ctrl.reset_delay[0] ;
+ wire \clock_ctrl.reset_delay[1] ;
+ wire \clock_ctrl.reset_delay[2] ;
+ wire \clock_ctrl.resetb_sync ;
+ wire \clock_ctrl.use_pll_first ;
+ wire \clock_ctrl.use_pll_second ;
+ wire \clock_ctrl.user_clk ;
+ wire net2344;
+ wire \clknet_leaf_0_clock_ctrl.core_clk ;
+ wire net2298;
+ wire net2299;
+ wire net2300;
+ wire net2301;
+ wire net2302;
+ wire net2303;
+ wire net2304;
+ wire net2305;
+ wire net2306;
+ wire \clknet_leaf_3_clock_ctrl.core_clk ;
+ wire \gpio_buf_mgmt_io_in_buf[0] ;
+ wire \gpio_buf_mgmt_io_in_buf[10] ;
+ wire \gpio_buf_mgmt_io_in_buf[11] ;
+ wire \gpio_buf_mgmt_io_in_buf[12] ;
+ wire \gpio_buf_mgmt_io_in_buf[13] ;
+ wire \gpio_buf_mgmt_io_in_buf[14] ;
+ wire \gpio_buf_mgmt_io_in_buf[15] ;
+ wire \gpio_buf_mgmt_io_in_buf[16] ;
+ wire \gpio_buf_mgmt_io_in_buf[17] ;
+ wire \gpio_buf_mgmt_io_in_buf[1] ;
+ wire \gpio_buf_mgmt_io_in_buf[2] ;
+ wire \gpio_buf_mgmt_io_in_buf[3] ;
+ wire \gpio_buf_mgmt_io_in_buf[4] ;
+ wire \gpio_buf_mgmt_io_in_buf[5] ;
+ wire \gpio_buf_mgmt_io_in_buf[6] ;
+ wire \gpio_buf_mgmt_io_in_buf[7] ;
+ wire \gpio_buf_mgmt_io_in_buf[8] ;
+ wire \gpio_buf_mgmt_io_in_buf[9] ;
+ wire \gpio_buf_mgmt_io_oeb[0] ;
+ wire \gpio_buf_mgmt_io_oeb[1] ;
+ wire \gpio_buf_mgmt_io_oeb[2] ;
+ wire \gpio_buf_mgmt_io_oeb_buf[0] ;
+ wire \gpio_buf_mgmt_io_oeb_buf[1] ;
+ wire \gpio_buf_mgmt_io_oeb_buf[2] ;
+ wire \gpio_buf_mgmt_io_out_buf[0] ;
+ wire \gpio_buf_mgmt_io_out_buf[10] ;
+ wire \gpio_buf_mgmt_io_out_buf[11] ;
+ wire \gpio_buf_mgmt_io_out_buf[12] ;
+ wire \gpio_buf_mgmt_io_out_buf[13] ;
+ wire \gpio_buf_mgmt_io_out_buf[14] ;
+ wire \gpio_buf_mgmt_io_out_buf[15] ;
+ wire \gpio_buf_mgmt_io_out_buf[16] ;
+ wire \gpio_buf_mgmt_io_out_buf[17] ;
+ wire \gpio_buf_mgmt_io_out_buf[1] ;
+ wire \gpio_buf_mgmt_io_out_buf[2] ;
+ wire \gpio_buf_mgmt_io_out_buf[3] ;
+ wire \gpio_buf_mgmt_io_out_buf[4] ;
+ wire \gpio_buf_mgmt_io_out_buf[5] ;
+ wire \gpio_buf_mgmt_io_out_buf[6] ;
+ wire \gpio_buf_mgmt_io_out_buf[7] ;
+ wire \gpio_buf_mgmt_io_out_buf[8] ;
+ wire \gpio_buf_mgmt_io_out_buf[9] ;
+ wire \gpio_control_bidir_1[0].gpio_defaults[0] ;
+ wire \gpio_control_bidir_1[0].gpio_defaults[1] ;
+ wire \gpio_control_bidir_1[0].gpio_defaults[2] ;
+ wire \gpio_control_bidir_1[0].gpio_defaults[3] ;
+ wire \gpio_control_bidir_1[0].gpio_defaults[4] ;
+ wire \gpio_control_bidir_1[0].gpio_defaults[5] ;
+ wire \gpio_control_bidir_1[0].gpio_defaults[6] ;
+ wire \gpio_control_bidir_1[0].gpio_defaults[7] ;
+ wire \gpio_control_bidir_1[0].gpio_defaults[8] ;
+ wire \gpio_control_bidir_1[0].gpio_defaults[9] ;
+ wire \gpio_control_bidir_1[0].gpio_inen ;
+ wire \gpio_control_bidir_1[0].gpio_oe_override ;
+ wire \gpio_control_bidir_1[0].gpio_outen ;
+ wire \gpio_control_bidir_1[0].gpio_pulldown_sel ;
+ wire \gpio_control_bidir_1[0].gpio_pullup_sel ;
+ wire \gpio_control_bidir_1[0].gpio_schmitt_sel ;
+ wire \gpio_control_bidir_1[0].gpio_slew_sel ;
+ wire \gpio_control_bidir_1[0].mgmt_ena ;
+ wire \gpio_control_bidir_1[0].mgmt_gpio_oeb ;
+ wire \gpio_control_bidir_1[0].pad_gpio_out ;
+ wire \gpio_control_bidir_1[0].pad_gpio_outen ;
+ wire \gpio_control_bidir_1[0].resetn ;
+ wire \gpio_control_bidir_1[0].resetn_out ;
+ wire \gpio_control_bidir_1[0].serial_clock ;
+ wire \gpio_control_bidir_1[0].serial_clock_out ;
+ wire \gpio_control_bidir_1[0].serial_data_in ;
+ wire \gpio_control_bidir_1[0].serial_data_out ;
+ wire \gpio_control_bidir_1[0].serial_load ;
+ wire \gpio_control_bidir_1[0].serial_load_out ;
+ wire \gpio_control_bidir_1[0].shift_register[0] ;
+ wire \gpio_control_bidir_1[0].shift_register[1] ;
+ wire \gpio_control_bidir_1[0].shift_register[2] ;
+ wire \gpio_control_bidir_1[0].shift_register[3] ;
+ wire \gpio_control_bidir_1[0].shift_register[4] ;
+ wire \gpio_control_bidir_1[0].shift_register[5] ;
+ wire \gpio_control_bidir_1[0].shift_register[6] ;
+ wire \gpio_control_bidir_1[0].shift_register[7] ;
+ wire \gpio_control_bidir_1[0].shift_register[8] ;
+ wire \gpio_control_bidir_1[0].shift_register[9] ;
+ wire \gpio_control_bidir_1[1].gpio_defaults[0] ;
+ wire \gpio_control_bidir_1[1].gpio_defaults[1] ;
+ wire \gpio_control_bidir_1[1].gpio_defaults[2] ;
+ wire \gpio_control_bidir_1[1].gpio_defaults[3] ;
+ wire \gpio_control_bidir_1[1].gpio_defaults[4] ;
+ wire \gpio_control_bidir_1[1].gpio_defaults[5] ;
+ wire \gpio_control_bidir_1[1].gpio_defaults[6] ;
+ wire \gpio_control_bidir_1[1].gpio_defaults[7] ;
+ wire \gpio_control_bidir_1[1].gpio_defaults[8] ;
+ wire \gpio_control_bidir_1[1].gpio_defaults[9] ;
+ wire \gpio_control_bidir_1[1].gpio_inen ;
+ wire \gpio_control_bidir_1[1].gpio_oe_override ;
+ wire \gpio_control_bidir_1[1].gpio_outen ;
+ wire \gpio_control_bidir_1[1].gpio_pulldown_sel ;
+ wire \gpio_control_bidir_1[1].gpio_pullup_sel ;
+ wire \gpio_control_bidir_1[1].gpio_schmitt_sel ;
+ wire \gpio_control_bidir_1[1].gpio_slew_sel ;
+ wire \gpio_control_bidir_1[1].mgmt_ena ;
+ wire \gpio_control_bidir_1[1].mgmt_gpio_oeb ;
+ wire \gpio_control_bidir_1[1].pad_gpio_out ;
+ wire \gpio_control_bidir_1[1].pad_gpio_outen ;
+ wire \gpio_control_bidir_1[1].resetn_out ;
+ wire \gpio_control_bidir_1[1].serial_clock_out ;
+ wire \gpio_control_bidir_1[1].serial_data_out ;
+ wire \gpio_control_bidir_1[1].serial_load_out ;
+ wire \gpio_control_bidir_1[1].shift_register[0] ;
+ wire \gpio_control_bidir_1[1].shift_register[1] ;
+ wire \gpio_control_bidir_1[1].shift_register[2] ;
+ wire \gpio_control_bidir_1[1].shift_register[3] ;
+ wire \gpio_control_bidir_1[1].shift_register[4] ;
+ wire \gpio_control_bidir_1[1].shift_register[5] ;
+ wire \gpio_control_bidir_1[1].shift_register[6] ;
+ wire \gpio_control_bidir_1[1].shift_register[7] ;
+ wire \gpio_control_bidir_1[1].shift_register[8] ;
+ wire \gpio_control_bidir_1[1].shift_register[9] ;
+ wire \gpio_control_bidir_2[0].gpio_defaults[0] ;
+ wire \gpio_control_bidir_2[0].gpio_defaults[1] ;
+ wire \gpio_control_bidir_2[0].gpio_defaults[2] ;
+ wire \gpio_control_bidir_2[0].gpio_defaults[3] ;
+ wire \gpio_control_bidir_2[0].gpio_defaults[4] ;
+ wire \gpio_control_bidir_2[0].gpio_defaults[5] ;
+ wire \gpio_control_bidir_2[0].gpio_defaults[6] ;
+ wire \gpio_control_bidir_2[0].gpio_defaults[7] ;
+ wire \gpio_control_bidir_2[0].gpio_defaults[8] ;
+ wire \gpio_control_bidir_2[0].gpio_defaults[9] ;
+ wire \gpio_control_bidir_2[0].gpio_inen ;
+ wire \gpio_control_bidir_2[0].gpio_oe_override ;
+ wire \gpio_control_bidir_2[0].gpio_outen ;
+ wire \gpio_control_bidir_2[0].gpio_pulldown_sel ;
+ wire \gpio_control_bidir_2[0].gpio_pullup_sel ;
+ wire \gpio_control_bidir_2[0].gpio_schmitt_sel ;
+ wire \gpio_control_bidir_2[0].gpio_slew_sel ;
+ wire \gpio_control_bidir_2[0].mgmt_ena ;
+ wire \gpio_control_bidir_2[0].pad_gpio_out ;
+ wire \gpio_control_bidir_2[0].pad_gpio_outen ;
+ wire \gpio_control_bidir_2[0].resetn ;
+ wire \gpio_control_bidir_2[0].resetn_out ;
+ wire \gpio_control_bidir_2[0].serial_clock ;
+ wire \gpio_control_bidir_2[0].serial_clock_out ;
+ wire \gpio_control_bidir_2[0].serial_data_in ;
+ wire \gpio_control_bidir_2[0].serial_data_out ;
+ wire \gpio_control_bidir_2[0].serial_load ;
+ wire \gpio_control_bidir_2[0].serial_load_out ;
+ wire \gpio_control_bidir_2[0].shift_register[0] ;
+ wire \gpio_control_bidir_2[0].shift_register[1] ;
+ wire \gpio_control_bidir_2[0].shift_register[2] ;
+ wire \gpio_control_bidir_2[0].shift_register[3] ;
+ wire \gpio_control_bidir_2[0].shift_register[4] ;
+ wire \gpio_control_bidir_2[0].shift_register[5] ;
+ wire \gpio_control_bidir_2[0].shift_register[6] ;
+ wire \gpio_control_bidir_2[0].shift_register[7] ;
+ wire \gpio_control_bidir_2[0].shift_register[8] ;
+ wire \gpio_control_bidir_2[0].shift_register[9] ;
+ wire \gpio_control_bidir_2[1].gpio_defaults[0] ;
+ wire \gpio_control_bidir_2[1].gpio_defaults[1] ;
+ wire \gpio_control_bidir_2[1].gpio_defaults[2] ;
+ wire \gpio_control_bidir_2[1].gpio_defaults[3] ;
+ wire \gpio_control_bidir_2[1].gpio_defaults[4] ;
+ wire \gpio_control_bidir_2[1].gpio_defaults[5] ;
+ wire \gpio_control_bidir_2[1].gpio_defaults[6] ;
+ wire \gpio_control_bidir_2[1].gpio_defaults[7] ;
+ wire \gpio_control_bidir_2[1].gpio_defaults[8] ;
+ wire \gpio_control_bidir_2[1].gpio_defaults[9] ;
+ wire \gpio_control_bidir_2[1].gpio_inen ;
+ wire \gpio_control_bidir_2[1].gpio_oe_override ;
+ wire \gpio_control_bidir_2[1].gpio_outen ;
+ wire \gpio_control_bidir_2[1].gpio_pulldown_sel ;
+ wire \gpio_control_bidir_2[1].gpio_pullup_sel ;
+ wire \gpio_control_bidir_2[1].gpio_schmitt_sel ;
+ wire \gpio_control_bidir_2[1].gpio_slew_sel ;
+ wire \gpio_control_bidir_2[1].mgmt_ena ;
+ wire \gpio_control_bidir_2[1].pad_gpio_out ;
+ wire \gpio_control_bidir_2[1].pad_gpio_outen ;
+ wire \gpio_control_bidir_2[1].resetn ;
+ wire \gpio_control_bidir_2[1].serial_clock ;
+ wire \gpio_control_bidir_2[1].serial_data_in ;
+ wire \gpio_control_bidir_2[1].serial_load ;
+ wire \gpio_control_bidir_2[1].shift_register[0] ;
+ wire \gpio_control_bidir_2[1].shift_register[1] ;
+ wire \gpio_control_bidir_2[1].shift_register[2] ;
+ wire \gpio_control_bidir_2[1].shift_register[3] ;
+ wire \gpio_control_bidir_2[1].shift_register[4] ;
+ wire \gpio_control_bidir_2[1].shift_register[5] ;
+ wire \gpio_control_bidir_2[1].shift_register[6] ;
+ wire \gpio_control_bidir_2[1].shift_register[7] ;
+ wire \gpio_control_bidir_2[1].shift_register[8] ;
+ wire \gpio_control_bidir_2[1].shift_register[9] ;
+ wire \gpio_control_bidir_2[2].gpio_defaults[0] ;
+ wire \gpio_control_bidir_2[2].gpio_defaults[1] ;
+ wire \gpio_control_bidir_2[2].gpio_defaults[2] ;
+ wire \gpio_control_bidir_2[2].gpio_defaults[3] ;
+ wire \gpio_control_bidir_2[2].gpio_defaults[4] ;
+ wire \gpio_control_bidir_2[2].gpio_defaults[5] ;
+ wire \gpio_control_bidir_2[2].gpio_defaults[6] ;
+ wire \gpio_control_bidir_2[2].gpio_defaults[7] ;
+ wire \gpio_control_bidir_2[2].gpio_defaults[8] ;
+ wire \gpio_control_bidir_2[2].gpio_defaults[9] ;
+ wire \gpio_control_bidir_2[2].gpio_inen ;
+ wire \gpio_control_bidir_2[2].gpio_oe_override ;
+ wire \gpio_control_bidir_2[2].gpio_outen ;
+ wire \gpio_control_bidir_2[2].gpio_pulldown_sel ;
+ wire \gpio_control_bidir_2[2].gpio_pullup_sel ;
+ wire \gpio_control_bidir_2[2].gpio_schmitt_sel ;
+ wire \gpio_control_bidir_2[2].gpio_slew_sel ;
+ wire \gpio_control_bidir_2[2].mgmt_ena ;
+ wire \gpio_control_bidir_2[2].pad_gpio_out ;
+ wire \gpio_control_bidir_2[2].pad_gpio_outen ;
+ wire \gpio_control_bidir_2[2].serial_data_in ;
+ wire \gpio_control_bidir_2[2].shift_register[0] ;
+ wire \gpio_control_bidir_2[2].shift_register[1] ;
+ wire \gpio_control_bidir_2[2].shift_register[2] ;
+ wire \gpio_control_bidir_2[2].shift_register[3] ;
+ wire \gpio_control_bidir_2[2].shift_register[4] ;
+ wire \gpio_control_bidir_2[2].shift_register[5] ;
+ wire \gpio_control_bidir_2[2].shift_register[6] ;
+ wire \gpio_control_bidir_2[2].shift_register[7] ;
+ wire \gpio_control_bidir_2[2].shift_register[8] ;
+ wire \gpio_control_bidir_2[2].shift_register[9] ;
+ wire \gpio_control_in_1[0].gpio_defaults[0] ;
+ wire \gpio_control_in_1[0].gpio_defaults[1] ;
+ wire \gpio_control_in_1[0].gpio_defaults[2] ;
+ wire \gpio_control_in_1[0].gpio_defaults[3] ;
+ wire \gpio_control_in_1[0].gpio_defaults[4] ;
+ wire \gpio_control_in_1[0].gpio_defaults[5] ;
+ wire \gpio_control_in_1[0].gpio_defaults[6] ;
+ wire \gpio_control_in_1[0].gpio_defaults[7] ;
+ wire \gpio_control_in_1[0].gpio_defaults[8] ;
+ wire \gpio_control_in_1[0].gpio_defaults[9] ;
+ wire \gpio_control_in_1[0].gpio_inen ;
+ wire \gpio_control_in_1[0].gpio_oe_override ;
+ wire \gpio_control_in_1[0].gpio_outen ;
+ wire \gpio_control_in_1[0].gpio_pulldown_sel ;
+ wire \gpio_control_in_1[0].gpio_pullup_sel ;
+ wire \gpio_control_in_1[0].gpio_schmitt_sel ;
+ wire \gpio_control_in_1[0].gpio_slew_sel ;
+ wire \gpio_control_in_1[0].mgmt_ena ;
+ wire net2308;
+ wire \gpio_control_in_1[0].pad_gpio_out ;
+ wire \gpio_control_in_1[0].pad_gpio_outen ;
+ wire \gpio_control_in_1[0].resetn ;
+ wire \gpio_control_in_1[0].resetn_out ;
+ wire \gpio_control_in_1[0].serial_clock ;
+ wire \gpio_control_in_1[0].serial_clock_out ;
+ wire \gpio_control_in_1[0].serial_data_in ;
+ wire \gpio_control_in_1[0].serial_data_out ;
+ wire \gpio_control_in_1[0].serial_load ;
+ wire \gpio_control_in_1[0].serial_load_out ;
+ wire \gpio_control_in_1[0].shift_register[0] ;
+ wire \gpio_control_in_1[0].shift_register[1] ;
+ wire \gpio_control_in_1[0].shift_register[2] ;
+ wire \gpio_control_in_1[0].shift_register[3] ;
+ wire \gpio_control_in_1[0].shift_register[4] ;
+ wire \gpio_control_in_1[0].shift_register[5] ;
+ wire \gpio_control_in_1[0].shift_register[6] ;
+ wire \gpio_control_in_1[0].shift_register[7] ;
+ wire \gpio_control_in_1[0].shift_register[8] ;
+ wire \gpio_control_in_1[0].shift_register[9] ;
+ wire \gpio_control_in_1[10].gpio_defaults[0] ;
+ wire \gpio_control_in_1[10].gpio_defaults[1] ;
+ wire \gpio_control_in_1[10].gpio_defaults[2] ;
+ wire \gpio_control_in_1[10].gpio_defaults[3] ;
+ wire \gpio_control_in_1[10].gpio_defaults[4] ;
+ wire \gpio_control_in_1[10].gpio_defaults[5] ;
+ wire \gpio_control_in_1[10].gpio_defaults[6] ;
+ wire \gpio_control_in_1[10].gpio_defaults[7] ;
+ wire \gpio_control_in_1[10].gpio_defaults[8] ;
+ wire \gpio_control_in_1[10].gpio_defaults[9] ;
+ wire \gpio_control_in_1[10].gpio_inen ;
+ wire \gpio_control_in_1[10].gpio_oe_override ;
+ wire \gpio_control_in_1[10].gpio_outen ;
+ wire \gpio_control_in_1[10].gpio_pulldown_sel ;
+ wire \gpio_control_in_1[10].gpio_pullup_sel ;
+ wire \gpio_control_in_1[10].gpio_schmitt_sel ;
+ wire \gpio_control_in_1[10].gpio_slew_sel ;
+ wire \gpio_control_in_1[10].mgmt_ena ;
+ wire net2309;
+ wire \gpio_control_in_1[10].pad_gpio_out ;
+ wire \gpio_control_in_1[10].pad_gpio_outen ;
+ wire \gpio_control_in_1[10].resetn ;
+ wire \gpio_control_in_1[10].resetn_out ;
+ wire \gpio_control_in_1[10].serial_clock ;
+ wire \gpio_control_in_1[10].serial_clock_out ;
+ wire \gpio_control_in_1[10].serial_data_in ;
+ wire \gpio_control_in_1[10].serial_load ;
+ wire \gpio_control_in_1[10].serial_load_out ;
+ wire \gpio_control_in_1[10].shift_register[0] ;
+ wire \gpio_control_in_1[10].shift_register[1] ;
+ wire \gpio_control_in_1[10].shift_register[2] ;
+ wire \gpio_control_in_1[10].shift_register[3] ;
+ wire \gpio_control_in_1[10].shift_register[4] ;
+ wire \gpio_control_in_1[10].shift_register[5] ;
+ wire \gpio_control_in_1[10].shift_register[6] ;
+ wire \gpio_control_in_1[10].shift_register[7] ;
+ wire \gpio_control_in_1[10].shift_register[8] ;
+ wire \gpio_control_in_1[10].shift_register[9] ;
+ wire \gpio_control_in_1[1].gpio_defaults[0] ;
+ wire \gpio_control_in_1[1].gpio_defaults[1] ;
+ wire \gpio_control_in_1[1].gpio_defaults[2] ;
+ wire \gpio_control_in_1[1].gpio_defaults[3] ;
+ wire \gpio_control_in_1[1].gpio_defaults[4] ;
+ wire \gpio_control_in_1[1].gpio_defaults[5] ;
+ wire \gpio_control_in_1[1].gpio_defaults[6] ;
+ wire \gpio_control_in_1[1].gpio_defaults[7] ;
+ wire \gpio_control_in_1[1].gpio_defaults[8] ;
+ wire \gpio_control_in_1[1].gpio_defaults[9] ;
+ wire \gpio_control_in_1[1].gpio_inen ;
+ wire \gpio_control_in_1[1].gpio_oe_override ;
+ wire \gpio_control_in_1[1].gpio_outen ;
+ wire \gpio_control_in_1[1].gpio_pulldown_sel ;
+ wire \gpio_control_in_1[1].gpio_pullup_sel ;
+ wire \gpio_control_in_1[1].gpio_schmitt_sel ;
+ wire \gpio_control_in_1[1].gpio_slew_sel ;
+ wire \gpio_control_in_1[1].mgmt_ena ;
+ wire net2310;
+ wire \gpio_control_in_1[1].pad_gpio_out ;
+ wire \gpio_control_in_1[1].pad_gpio_outen ;
+ wire \gpio_control_in_1[1].resetn_out ;
+ wire \gpio_control_in_1[1].serial_clock_out ;
+ wire \gpio_control_in_1[1].serial_data_out ;
+ wire \gpio_control_in_1[1].serial_load_out ;
+ wire \gpio_control_in_1[1].shift_register[0] ;
+ wire \gpio_control_in_1[1].shift_register[1] ;
+ wire \gpio_control_in_1[1].shift_register[2] ;
+ wire \gpio_control_in_1[1].shift_register[3] ;
+ wire \gpio_control_in_1[1].shift_register[4] ;
+ wire \gpio_control_in_1[1].shift_register[5] ;
+ wire \gpio_control_in_1[1].shift_register[6] ;
+ wire \gpio_control_in_1[1].shift_register[7] ;
+ wire \gpio_control_in_1[1].shift_register[8] ;
+ wire \gpio_control_in_1[1].shift_register[9] ;
+ wire \gpio_control_in_1[2].gpio_defaults[0] ;
+ wire \gpio_control_in_1[2].gpio_defaults[1] ;
+ wire \gpio_control_in_1[2].gpio_defaults[2] ;
+ wire \gpio_control_in_1[2].gpio_defaults[3] ;
+ wire \gpio_control_in_1[2].gpio_defaults[4] ;
+ wire \gpio_control_in_1[2].gpio_defaults[5] ;
+ wire \gpio_control_in_1[2].gpio_defaults[6] ;
+ wire \gpio_control_in_1[2].gpio_defaults[7] ;
+ wire \gpio_control_in_1[2].gpio_defaults[8] ;
+ wire \gpio_control_in_1[2].gpio_defaults[9] ;
+ wire \gpio_control_in_1[2].gpio_inen ;
+ wire \gpio_control_in_1[2].gpio_oe_override ;
+ wire \gpio_control_in_1[2].gpio_outen ;
+ wire \gpio_control_in_1[2].gpio_pulldown_sel ;
+ wire \gpio_control_in_1[2].gpio_pullup_sel ;
+ wire \gpio_control_in_1[2].gpio_schmitt_sel ;
+ wire \gpio_control_in_1[2].gpio_slew_sel ;
+ wire \gpio_control_in_1[2].mgmt_ena ;
+ wire net2311;
+ wire \gpio_control_in_1[2].pad_gpio_out ;
+ wire \gpio_control_in_1[2].pad_gpio_outen ;
+ wire \gpio_control_in_1[2].resetn_out ;
+ wire \gpio_control_in_1[2].serial_clock_out ;
+ wire \gpio_control_in_1[2].serial_data_out ;
+ wire \gpio_control_in_1[2].serial_load_out ;
+ wire \gpio_control_in_1[2].shift_register[0] ;
+ wire \gpio_control_in_1[2].shift_register[1] ;
+ wire \gpio_control_in_1[2].shift_register[2] ;
+ wire \gpio_control_in_1[2].shift_register[3] ;
+ wire \gpio_control_in_1[2].shift_register[4] ;
+ wire \gpio_control_in_1[2].shift_register[5] ;
+ wire \gpio_control_in_1[2].shift_register[6] ;
+ wire \gpio_control_in_1[2].shift_register[7] ;
+ wire \gpio_control_in_1[2].shift_register[8] ;
+ wire \gpio_control_in_1[2].shift_register[9] ;
+ wire \gpio_control_in_1[3].gpio_defaults[0] ;
+ wire \gpio_control_in_1[3].gpio_defaults[1] ;
+ wire \gpio_control_in_1[3].gpio_defaults[2] ;
+ wire \gpio_control_in_1[3].gpio_defaults[3] ;
+ wire \gpio_control_in_1[3].gpio_defaults[4] ;
+ wire \gpio_control_in_1[3].gpio_defaults[5] ;
+ wire \gpio_control_in_1[3].gpio_defaults[6] ;
+ wire \gpio_control_in_1[3].gpio_defaults[7] ;
+ wire \gpio_control_in_1[3].gpio_defaults[8] ;
+ wire \gpio_control_in_1[3].gpio_defaults[9] ;
+ wire \gpio_control_in_1[3].gpio_inen ;
+ wire \gpio_control_in_1[3].gpio_oe_override ;
+ wire \gpio_control_in_1[3].gpio_outen ;
+ wire \gpio_control_in_1[3].gpio_pulldown_sel ;
+ wire \gpio_control_in_1[3].gpio_pullup_sel ;
+ wire \gpio_control_in_1[3].gpio_schmitt_sel ;
+ wire \gpio_control_in_1[3].gpio_slew_sel ;
+ wire \gpio_control_in_1[3].mgmt_ena ;
+ wire net2312;
+ wire \gpio_control_in_1[3].pad_gpio_out ;
+ wire \gpio_control_in_1[3].pad_gpio_outen ;
+ wire \gpio_control_in_1[3].resetn_out ;
+ wire \gpio_control_in_1[3].serial_clock_out ;
+ wire \gpio_control_in_1[3].serial_data_out ;
+ wire \gpio_control_in_1[3].serial_load_out ;
+ wire \gpio_control_in_1[3].shift_register[0] ;
+ wire \gpio_control_in_1[3].shift_register[1] ;
+ wire \gpio_control_in_1[3].shift_register[2] ;
+ wire \gpio_control_in_1[3].shift_register[3] ;
+ wire \gpio_control_in_1[3].shift_register[4] ;
+ wire \gpio_control_in_1[3].shift_register[5] ;
+ wire \gpio_control_in_1[3].shift_register[6] ;
+ wire \gpio_control_in_1[3].shift_register[7] ;
+ wire \gpio_control_in_1[3].shift_register[8] ;
+ wire \gpio_control_in_1[3].shift_register[9] ;
+ wire \gpio_control_in_1[4].gpio_defaults[0] ;
+ wire \gpio_control_in_1[4].gpio_defaults[1] ;
+ wire \gpio_control_in_1[4].gpio_defaults[2] ;
+ wire \gpio_control_in_1[4].gpio_defaults[3] ;
+ wire \gpio_control_in_1[4].gpio_defaults[4] ;
+ wire \gpio_control_in_1[4].gpio_defaults[5] ;
+ wire \gpio_control_in_1[4].gpio_defaults[6] ;
+ wire \gpio_control_in_1[4].gpio_defaults[7] ;
+ wire \gpio_control_in_1[4].gpio_defaults[8] ;
+ wire \gpio_control_in_1[4].gpio_defaults[9] ;
+ wire \gpio_control_in_1[4].gpio_inen ;
+ wire \gpio_control_in_1[4].gpio_oe_override ;
+ wire \gpio_control_in_1[4].gpio_outen ;
+ wire \gpio_control_in_1[4].gpio_pulldown_sel ;
+ wire \gpio_control_in_1[4].gpio_pullup_sel ;
+ wire \gpio_control_in_1[4].gpio_schmitt_sel ;
+ wire \gpio_control_in_1[4].gpio_slew_sel ;
+ wire \gpio_control_in_1[4].mgmt_ena ;
+ wire net2313;
+ wire \gpio_control_in_1[4].pad_gpio_out ;
+ wire \gpio_control_in_1[4].pad_gpio_outen ;
+ wire \gpio_control_in_1[4].resetn_out ;
+ wire \gpio_control_in_1[4].serial_clock_out ;
+ wire \gpio_control_in_1[4].serial_data_out ;
+ wire \gpio_control_in_1[4].serial_load_out ;
+ wire \gpio_control_in_1[4].shift_register[0] ;
+ wire \gpio_control_in_1[4].shift_register[1] ;
+ wire \gpio_control_in_1[4].shift_register[2] ;
+ wire \gpio_control_in_1[4].shift_register[3] ;
+ wire \gpio_control_in_1[4].shift_register[4] ;
+ wire \gpio_control_in_1[4].shift_register[5] ;
+ wire \gpio_control_in_1[4].shift_register[6] ;
+ wire \gpio_control_in_1[4].shift_register[7] ;
+ wire \gpio_control_in_1[4].shift_register[8] ;
+ wire \gpio_control_in_1[4].shift_register[9] ;
+ wire \gpio_control_in_1[5].gpio_defaults[0] ;
+ wire \gpio_control_in_1[5].gpio_defaults[1] ;
+ wire \gpio_control_in_1[5].gpio_defaults[2] ;
+ wire \gpio_control_in_1[5].gpio_defaults[3] ;
+ wire \gpio_control_in_1[5].gpio_defaults[4] ;
+ wire \gpio_control_in_1[5].gpio_defaults[5] ;
+ wire \gpio_control_in_1[5].gpio_defaults[6] ;
+ wire \gpio_control_in_1[5].gpio_defaults[7] ;
+ wire \gpio_control_in_1[5].gpio_defaults[8] ;
+ wire \gpio_control_in_1[5].gpio_defaults[9] ;
+ wire \gpio_control_in_1[5].gpio_inen ;
+ wire \gpio_control_in_1[5].gpio_oe_override ;
+ wire \gpio_control_in_1[5].gpio_outen ;
+ wire \gpio_control_in_1[5].gpio_pulldown_sel ;
+ wire \gpio_control_in_1[5].gpio_pullup_sel ;
+ wire \gpio_control_in_1[5].gpio_schmitt_sel ;
+ wire \gpio_control_in_1[5].gpio_slew_sel ;
+ wire \gpio_control_in_1[5].mgmt_ena ;
+ wire net2314;
+ wire \gpio_control_in_1[5].pad_gpio_out ;
+ wire \gpio_control_in_1[5].pad_gpio_outen ;
+ wire \gpio_control_in_1[5].resetn_out ;
+ wire \gpio_control_in_1[5].serial_clock_out ;
+ wire \gpio_control_in_1[5].serial_data_out ;
+ wire \gpio_control_in_1[5].serial_load_out ;
+ wire \gpio_control_in_1[5].shift_register[0] ;
+ wire \gpio_control_in_1[5].shift_register[1] ;
+ wire \gpio_control_in_1[5].shift_register[2] ;
+ wire \gpio_control_in_1[5].shift_register[3] ;
+ wire \gpio_control_in_1[5].shift_register[4] ;
+ wire \gpio_control_in_1[5].shift_register[5] ;
+ wire \gpio_control_in_1[5].shift_register[6] ;
+ wire \gpio_control_in_1[5].shift_register[7] ;
+ wire \gpio_control_in_1[5].shift_register[8] ;
+ wire \gpio_control_in_1[5].shift_register[9] ;
+ wire \gpio_control_in_1[6].gpio_defaults[0] ;
+ wire \gpio_control_in_1[6].gpio_defaults[1] ;
+ wire \gpio_control_in_1[6].gpio_defaults[2] ;
+ wire \gpio_control_in_1[6].gpio_defaults[3] ;
+ wire \gpio_control_in_1[6].gpio_defaults[4] ;
+ wire \gpio_control_in_1[6].gpio_defaults[5] ;
+ wire \gpio_control_in_1[6].gpio_defaults[6] ;
+ wire \gpio_control_in_1[6].gpio_defaults[7] ;
+ wire \gpio_control_in_1[6].gpio_defaults[8] ;
+ wire \gpio_control_in_1[6].gpio_defaults[9] ;
+ wire \gpio_control_in_1[6].gpio_inen ;
+ wire \gpio_control_in_1[6].gpio_oe_override ;
+ wire \gpio_control_in_1[6].gpio_outen ;
+ wire \gpio_control_in_1[6].gpio_pulldown_sel ;
+ wire \gpio_control_in_1[6].gpio_pullup_sel ;
+ wire \gpio_control_in_1[6].gpio_schmitt_sel ;
+ wire \gpio_control_in_1[6].gpio_slew_sel ;
+ wire \gpio_control_in_1[6].mgmt_ena ;
+ wire net2315;
+ wire \gpio_control_in_1[6].pad_gpio_out ;
+ wire \gpio_control_in_1[6].pad_gpio_outen ;
+ wire \gpio_control_in_1[6].resetn_out ;
+ wire \gpio_control_in_1[6].serial_clock_out ;
+ wire \gpio_control_in_1[6].serial_data_out ;
+ wire \gpio_control_in_1[6].serial_load_out ;
+ wire \gpio_control_in_1[6].shift_register[0] ;
+ wire \gpio_control_in_1[6].shift_register[1] ;
+ wire \gpio_control_in_1[6].shift_register[2] ;
+ wire \gpio_control_in_1[6].shift_register[3] ;
+ wire \gpio_control_in_1[6].shift_register[4] ;
+ wire \gpio_control_in_1[6].shift_register[5] ;
+ wire \gpio_control_in_1[6].shift_register[6] ;
+ wire \gpio_control_in_1[6].shift_register[7] ;
+ wire \gpio_control_in_1[6].shift_register[8] ;
+ wire \gpio_control_in_1[6].shift_register[9] ;
+ wire \gpio_control_in_1[7].gpio_defaults[0] ;
+ wire \gpio_control_in_1[7].gpio_defaults[1] ;
+ wire \gpio_control_in_1[7].gpio_defaults[2] ;
+ wire \gpio_control_in_1[7].gpio_defaults[3] ;
+ wire \gpio_control_in_1[7].gpio_defaults[4] ;
+ wire \gpio_control_in_1[7].gpio_defaults[5] ;
+ wire \gpio_control_in_1[7].gpio_defaults[6] ;
+ wire \gpio_control_in_1[7].gpio_defaults[7] ;
+ wire \gpio_control_in_1[7].gpio_defaults[8] ;
+ wire \gpio_control_in_1[7].gpio_defaults[9] ;
+ wire \gpio_control_in_1[7].gpio_inen ;
+ wire \gpio_control_in_1[7].gpio_oe_override ;
+ wire \gpio_control_in_1[7].gpio_outen ;
+ wire \gpio_control_in_1[7].gpio_pulldown_sel ;
+ wire \gpio_control_in_1[7].gpio_pullup_sel ;
+ wire \gpio_control_in_1[7].gpio_schmitt_sel ;
+ wire \gpio_control_in_1[7].gpio_slew_sel ;
+ wire \gpio_control_in_1[7].mgmt_ena ;
+ wire net2316;
+ wire \gpio_control_in_1[7].pad_gpio_out ;
+ wire \gpio_control_in_1[7].pad_gpio_outen ;
+ wire \gpio_control_in_1[7].resetn_out ;
+ wire \gpio_control_in_1[7].serial_clock_out ;
+ wire \gpio_control_in_1[7].serial_data_out ;
+ wire \gpio_control_in_1[7].serial_load_out ;
+ wire \gpio_control_in_1[7].shift_register[0] ;
+ wire \gpio_control_in_1[7].shift_register[1] ;
+ wire \gpio_control_in_1[7].shift_register[2] ;
+ wire \gpio_control_in_1[7].shift_register[3] ;
+ wire \gpio_control_in_1[7].shift_register[4] ;
+ wire \gpio_control_in_1[7].shift_register[5] ;
+ wire \gpio_control_in_1[7].shift_register[6] ;
+ wire \gpio_control_in_1[7].shift_register[7] ;
+ wire \gpio_control_in_1[7].shift_register[8] ;
+ wire \gpio_control_in_1[7].shift_register[9] ;
+ wire \gpio_control_in_1[8].gpio_defaults[0] ;
+ wire \gpio_control_in_1[8].gpio_defaults[1] ;
+ wire \gpio_control_in_1[8].gpio_defaults[2] ;
+ wire \gpio_control_in_1[8].gpio_defaults[3] ;
+ wire \gpio_control_in_1[8].gpio_defaults[4] ;
+ wire \gpio_control_in_1[8].gpio_defaults[5] ;
+ wire \gpio_control_in_1[8].gpio_defaults[6] ;
+ wire \gpio_control_in_1[8].gpio_defaults[7] ;
+ wire \gpio_control_in_1[8].gpio_defaults[8] ;
+ wire \gpio_control_in_1[8].gpio_defaults[9] ;
+ wire \gpio_control_in_1[8].gpio_inen ;
+ wire \gpio_control_in_1[8].gpio_oe_override ;
+ wire \gpio_control_in_1[8].gpio_outen ;
+ wire \gpio_control_in_1[8].gpio_pulldown_sel ;
+ wire \gpio_control_in_1[8].gpio_pullup_sel ;
+ wire \gpio_control_in_1[8].gpio_schmitt_sel ;
+ wire \gpio_control_in_1[8].gpio_slew_sel ;
+ wire \gpio_control_in_1[8].mgmt_ena ;
+ wire net2317;
+ wire \gpio_control_in_1[8].pad_gpio_out ;
+ wire \gpio_control_in_1[8].pad_gpio_outen ;
+ wire \gpio_control_in_1[8].resetn_out ;
+ wire \gpio_control_in_1[8].serial_clock_out ;
+ wire \gpio_control_in_1[8].serial_data_out ;
+ wire \gpio_control_in_1[8].serial_load_out ;
+ wire \gpio_control_in_1[8].shift_register[0] ;
+ wire \gpio_control_in_1[8].shift_register[1] ;
+ wire \gpio_control_in_1[8].shift_register[2] ;
+ wire \gpio_control_in_1[8].shift_register[3] ;
+ wire \gpio_control_in_1[8].shift_register[4] ;
+ wire \gpio_control_in_1[8].shift_register[5] ;
+ wire \gpio_control_in_1[8].shift_register[6] ;
+ wire \gpio_control_in_1[8].shift_register[7] ;
+ wire \gpio_control_in_1[8].shift_register[8] ;
+ wire \gpio_control_in_1[8].shift_register[9] ;
+ wire \gpio_control_in_1[9].gpio_defaults[0] ;
+ wire \gpio_control_in_1[9].gpio_defaults[1] ;
+ wire \gpio_control_in_1[9].gpio_defaults[2] ;
+ wire \gpio_control_in_1[9].gpio_defaults[3] ;
+ wire \gpio_control_in_1[9].gpio_defaults[4] ;
+ wire \gpio_control_in_1[9].gpio_defaults[5] ;
+ wire \gpio_control_in_1[9].gpio_defaults[6] ;
+ wire \gpio_control_in_1[9].gpio_defaults[7] ;
+ wire \gpio_control_in_1[9].gpio_defaults[8] ;
+ wire \gpio_control_in_1[9].gpio_defaults[9] ;
+ wire \gpio_control_in_1[9].gpio_inen ;
+ wire \gpio_control_in_1[9].gpio_oe_override ;
+ wire \gpio_control_in_1[9].gpio_outen ;
+ wire \gpio_control_in_1[9].gpio_pulldown_sel ;
+ wire \gpio_control_in_1[9].gpio_pullup_sel ;
+ wire \gpio_control_in_1[9].gpio_schmitt_sel ;
+ wire \gpio_control_in_1[9].gpio_slew_sel ;
+ wire \gpio_control_in_1[9].mgmt_ena ;
+ wire net2318;
+ wire \gpio_control_in_1[9].pad_gpio_out ;
+ wire \gpio_control_in_1[9].pad_gpio_outen ;
+ wire \gpio_control_in_1[9].shift_register[0] ;
+ wire \gpio_control_in_1[9].shift_register[1] ;
+ wire \gpio_control_in_1[9].shift_register[2] ;
+ wire \gpio_control_in_1[9].shift_register[3] ;
+ wire \gpio_control_in_1[9].shift_register[4] ;
+ wire \gpio_control_in_1[9].shift_register[5] ;
+ wire \gpio_control_in_1[9].shift_register[6] ;
+ wire \gpio_control_in_1[9].shift_register[7] ;
+ wire \gpio_control_in_1[9].shift_register[8] ;
+ wire \gpio_control_in_1[9].shift_register[9] ;
+ wire \gpio_control_in_1a[0].gpio_defaults[0] ;
+ wire \gpio_control_in_1a[0].gpio_defaults[1] ;
+ wire \gpio_control_in_1a[0].gpio_defaults[2] ;
+ wire \gpio_control_in_1a[0].gpio_defaults[3] ;
+ wire \gpio_control_in_1a[0].gpio_defaults[4] ;
+ wire \gpio_control_in_1a[0].gpio_defaults[5] ;
+ wire \gpio_control_in_1a[0].gpio_defaults[6] ;
+ wire \gpio_control_in_1a[0].gpio_defaults[7] ;
+ wire \gpio_control_in_1a[0].gpio_defaults[8] ;
+ wire \gpio_control_in_1a[0].gpio_defaults[9] ;
+ wire \gpio_control_in_1a[0].gpio_inen ;
+ wire \gpio_control_in_1a[0].gpio_oe_override ;
+ wire \gpio_control_in_1a[0].gpio_outen ;
+ wire \gpio_control_in_1a[0].gpio_pulldown_sel ;
+ wire \gpio_control_in_1a[0].gpio_pullup_sel ;
+ wire \gpio_control_in_1a[0].gpio_schmitt_sel ;
+ wire \gpio_control_in_1a[0].gpio_slew_sel ;
+ wire \gpio_control_in_1a[0].mgmt_ena ;
+ wire net2319;
+ wire \gpio_control_in_1a[0].pad_gpio_out ;
+ wire \gpio_control_in_1a[0].pad_gpio_outen ;
+ wire \gpio_control_in_1a[0].resetn_out ;
+ wire \gpio_control_in_1a[0].serial_clock_out ;
+ wire \gpio_control_in_1a[0].serial_data_out ;
+ wire \gpio_control_in_1a[0].serial_load_out ;
+ wire \gpio_control_in_1a[0].shift_register[0] ;
+ wire \gpio_control_in_1a[0].shift_register[1] ;
+ wire \gpio_control_in_1a[0].shift_register[2] ;
+ wire \gpio_control_in_1a[0].shift_register[3] ;
+ wire \gpio_control_in_1a[0].shift_register[4] ;
+ wire \gpio_control_in_1a[0].shift_register[5] ;
+ wire \gpio_control_in_1a[0].shift_register[6] ;
+ wire \gpio_control_in_1a[0].shift_register[7] ;
+ wire \gpio_control_in_1a[0].shift_register[8] ;
+ wire \gpio_control_in_1a[0].shift_register[9] ;
+ wire \gpio_control_in_1a[1].gpio_defaults[0] ;
+ wire \gpio_control_in_1a[1].gpio_defaults[1] ;
+ wire \gpio_control_in_1a[1].gpio_defaults[2] ;
+ wire \gpio_control_in_1a[1].gpio_defaults[3] ;
+ wire \gpio_control_in_1a[1].gpio_defaults[4] ;
+ wire \gpio_control_in_1a[1].gpio_defaults[5] ;
+ wire \gpio_control_in_1a[1].gpio_defaults[6] ;
+ wire \gpio_control_in_1a[1].gpio_defaults[7] ;
+ wire \gpio_control_in_1a[1].gpio_defaults[8] ;
+ wire \gpio_control_in_1a[1].gpio_defaults[9] ;
+ wire \gpio_control_in_1a[1].gpio_inen ;
+ wire \gpio_control_in_1a[1].gpio_oe_override ;
+ wire \gpio_control_in_1a[1].gpio_outen ;
+ wire \gpio_control_in_1a[1].gpio_pulldown_sel ;
+ wire \gpio_control_in_1a[1].gpio_pullup_sel ;
+ wire \gpio_control_in_1a[1].gpio_schmitt_sel ;
+ wire \gpio_control_in_1a[1].gpio_slew_sel ;
+ wire \gpio_control_in_1a[1].mgmt_ena ;
+ wire net2320;
+ wire \gpio_control_in_1a[1].pad_gpio_out ;
+ wire \gpio_control_in_1a[1].pad_gpio_outen ;
+ wire \gpio_control_in_1a[1].resetn_out ;
+ wire \gpio_control_in_1a[1].serial_clock_out ;
+ wire \gpio_control_in_1a[1].serial_data_out ;
+ wire \gpio_control_in_1a[1].serial_load_out ;
+ wire \gpio_control_in_1a[1].shift_register[0] ;
+ wire \gpio_control_in_1a[1].shift_register[1] ;
+ wire \gpio_control_in_1a[1].shift_register[2] ;
+ wire \gpio_control_in_1a[1].shift_register[3] ;
+ wire \gpio_control_in_1a[1].shift_register[4] ;
+ wire \gpio_control_in_1a[1].shift_register[5] ;
+ wire \gpio_control_in_1a[1].shift_register[6] ;
+ wire \gpio_control_in_1a[1].shift_register[7] ;
+ wire \gpio_control_in_1a[1].shift_register[8] ;
+ wire \gpio_control_in_1a[1].shift_register[9] ;
+ wire \gpio_control_in_1a[2].gpio_defaults[0] ;
+ wire \gpio_control_in_1a[2].gpio_defaults[1] ;
+ wire \gpio_control_in_1a[2].gpio_defaults[2] ;
+ wire \gpio_control_in_1a[2].gpio_defaults[3] ;
+ wire \gpio_control_in_1a[2].gpio_defaults[4] ;
+ wire \gpio_control_in_1a[2].gpio_defaults[5] ;
+ wire \gpio_control_in_1a[2].gpio_defaults[6] ;
+ wire \gpio_control_in_1a[2].gpio_defaults[7] ;
+ wire \gpio_control_in_1a[2].gpio_defaults[8] ;
+ wire \gpio_control_in_1a[2].gpio_defaults[9] ;
+ wire \gpio_control_in_1a[2].gpio_inen ;
+ wire \gpio_control_in_1a[2].gpio_oe_override ;
+ wire \gpio_control_in_1a[2].gpio_outen ;
+ wire \gpio_control_in_1a[2].gpio_pulldown_sel ;
+ wire \gpio_control_in_1a[2].gpio_pullup_sel ;
+ wire \gpio_control_in_1a[2].gpio_schmitt_sel ;
+ wire \gpio_control_in_1a[2].gpio_slew_sel ;
+ wire \gpio_control_in_1a[2].mgmt_ena ;
+ wire net2321;
+ wire \gpio_control_in_1a[2].pad_gpio_out ;
+ wire \gpio_control_in_1a[2].pad_gpio_outen ;
+ wire \gpio_control_in_1a[2].resetn_out ;
+ wire \gpio_control_in_1a[2].serial_clock_out ;
+ wire \gpio_control_in_1a[2].serial_data_out ;
+ wire \gpio_control_in_1a[2].serial_load_out ;
+ wire \gpio_control_in_1a[2].shift_register[0] ;
+ wire \gpio_control_in_1a[2].shift_register[1] ;
+ wire \gpio_control_in_1a[2].shift_register[2] ;
+ wire \gpio_control_in_1a[2].shift_register[3] ;
+ wire \gpio_control_in_1a[2].shift_register[4] ;
+ wire \gpio_control_in_1a[2].shift_register[5] ;
+ wire \gpio_control_in_1a[2].shift_register[6] ;
+ wire \gpio_control_in_1a[2].shift_register[7] ;
+ wire \gpio_control_in_1a[2].shift_register[8] ;
+ wire \gpio_control_in_1a[2].shift_register[9] ;
+ wire \gpio_control_in_1a[3].gpio_defaults[0] ;
+ wire \gpio_control_in_1a[3].gpio_defaults[1] ;
+ wire \gpio_control_in_1a[3].gpio_defaults[2] ;
+ wire \gpio_control_in_1a[3].gpio_defaults[3] ;
+ wire \gpio_control_in_1a[3].gpio_defaults[4] ;
+ wire \gpio_control_in_1a[3].gpio_defaults[5] ;
+ wire \gpio_control_in_1a[3].gpio_defaults[6] ;
+ wire \gpio_control_in_1a[3].gpio_defaults[7] ;
+ wire \gpio_control_in_1a[3].gpio_defaults[8] ;
+ wire \gpio_control_in_1a[3].gpio_defaults[9] ;
+ wire \gpio_control_in_1a[3].gpio_inen ;
+ wire \gpio_control_in_1a[3].gpio_oe_override ;
+ wire \gpio_control_in_1a[3].gpio_outen ;
+ wire \gpio_control_in_1a[3].gpio_pulldown_sel ;
+ wire \gpio_control_in_1a[3].gpio_pullup_sel ;
+ wire \gpio_control_in_1a[3].gpio_schmitt_sel ;
+ wire \gpio_control_in_1a[3].gpio_slew_sel ;
+ wire \gpio_control_in_1a[3].mgmt_ena ;
+ wire net2322;
+ wire \gpio_control_in_1a[3].pad_gpio_out ;
+ wire \gpio_control_in_1a[3].pad_gpio_outen ;
+ wire \gpio_control_in_1a[3].resetn_out ;
+ wire \gpio_control_in_1a[3].serial_clock_out ;
+ wire \gpio_control_in_1a[3].serial_data_out ;
+ wire \gpio_control_in_1a[3].serial_load_out ;
+ wire \gpio_control_in_1a[3].shift_register[0] ;
+ wire \gpio_control_in_1a[3].shift_register[1] ;
+ wire \gpio_control_in_1a[3].shift_register[2] ;
+ wire \gpio_control_in_1a[3].shift_register[3] ;
+ wire \gpio_control_in_1a[3].shift_register[4] ;
+ wire \gpio_control_in_1a[3].shift_register[5] ;
+ wire \gpio_control_in_1a[3].shift_register[6] ;
+ wire \gpio_control_in_1a[3].shift_register[7] ;
+ wire \gpio_control_in_1a[3].shift_register[8] ;
+ wire \gpio_control_in_1a[3].shift_register[9] ;
+ wire \gpio_control_in_1a[4].gpio_defaults[0] ;
+ wire \gpio_control_in_1a[4].gpio_defaults[1] ;
+ wire \gpio_control_in_1a[4].gpio_defaults[2] ;
+ wire \gpio_control_in_1a[4].gpio_defaults[3] ;
+ wire \gpio_control_in_1a[4].gpio_defaults[4] ;
+ wire \gpio_control_in_1a[4].gpio_defaults[5] ;
+ wire \gpio_control_in_1a[4].gpio_defaults[6] ;
+ wire \gpio_control_in_1a[4].gpio_defaults[7] ;
+ wire \gpio_control_in_1a[4].gpio_defaults[8] ;
+ wire \gpio_control_in_1a[4].gpio_defaults[9] ;
+ wire \gpio_control_in_1a[4].gpio_inen ;
+ wire \gpio_control_in_1a[4].gpio_oe_override ;
+ wire \gpio_control_in_1a[4].gpio_outen ;
+ wire \gpio_control_in_1a[4].gpio_pulldown_sel ;
+ wire \gpio_control_in_1a[4].gpio_pullup_sel ;
+ wire \gpio_control_in_1a[4].gpio_schmitt_sel ;
+ wire \gpio_control_in_1a[4].gpio_slew_sel ;
+ wire \gpio_control_in_1a[4].mgmt_ena ;
+ wire net2323;
+ wire \gpio_control_in_1a[4].pad_gpio_out ;
+ wire \gpio_control_in_1a[4].pad_gpio_outen ;
+ wire \gpio_control_in_1a[4].resetn_out ;
+ wire \gpio_control_in_1a[4].serial_clock_out ;
+ wire \gpio_control_in_1a[4].serial_data_out ;
+ wire \gpio_control_in_1a[4].serial_load_out ;
+ wire \gpio_control_in_1a[4].shift_register[0] ;
+ wire \gpio_control_in_1a[4].shift_register[1] ;
+ wire \gpio_control_in_1a[4].shift_register[2] ;
+ wire \gpio_control_in_1a[4].shift_register[3] ;
+ wire \gpio_control_in_1a[4].shift_register[4] ;
+ wire \gpio_control_in_1a[4].shift_register[5] ;
+ wire \gpio_control_in_1a[4].shift_register[6] ;
+ wire \gpio_control_in_1a[4].shift_register[7] ;
+ wire \gpio_control_in_1a[4].shift_register[8] ;
+ wire \gpio_control_in_1a[4].shift_register[9] ;
+ wire \gpio_control_in_1a[5].gpio_defaults[0] ;
+ wire \gpio_control_in_1a[5].gpio_defaults[1] ;
+ wire \gpio_control_in_1a[5].gpio_defaults[2] ;
+ wire \gpio_control_in_1a[5].gpio_defaults[3] ;
+ wire \gpio_control_in_1a[5].gpio_defaults[4] ;
+ wire \gpio_control_in_1a[5].gpio_defaults[5] ;
+ wire \gpio_control_in_1a[5].gpio_defaults[6] ;
+ wire \gpio_control_in_1a[5].gpio_defaults[7] ;
+ wire \gpio_control_in_1a[5].gpio_defaults[8] ;
+ wire \gpio_control_in_1a[5].gpio_defaults[9] ;
+ wire \gpio_control_in_1a[5].gpio_inen ;
+ wire \gpio_control_in_1a[5].gpio_oe_override ;
+ wire \gpio_control_in_1a[5].gpio_outen ;
+ wire \gpio_control_in_1a[5].gpio_pulldown_sel ;
+ wire \gpio_control_in_1a[5].gpio_pullup_sel ;
+ wire \gpio_control_in_1a[5].gpio_schmitt_sel ;
+ wire \gpio_control_in_1a[5].gpio_slew_sel ;
+ wire \gpio_control_in_1a[5].mgmt_ena ;
+ wire net2324;
+ wire \gpio_control_in_1a[5].pad_gpio_out ;
+ wire \gpio_control_in_1a[5].pad_gpio_outen ;
+ wire \gpio_control_in_1a[5].shift_register[0] ;
+ wire \gpio_control_in_1a[5].shift_register[1] ;
+ wire \gpio_control_in_1a[5].shift_register[2] ;
+ wire \gpio_control_in_1a[5].shift_register[3] ;
+ wire \gpio_control_in_1a[5].shift_register[4] ;
+ wire \gpio_control_in_1a[5].shift_register[5] ;
+ wire \gpio_control_in_1a[5].shift_register[6] ;
+ wire \gpio_control_in_1a[5].shift_register[7] ;
+ wire \gpio_control_in_1a[5].shift_register[8] ;
+ wire \gpio_control_in_1a[5].shift_register[9] ;
+ wire \gpio_control_in_2[0].gpio_defaults[0] ;
+ wire \gpio_control_in_2[0].gpio_defaults[1] ;
+ wire \gpio_control_in_2[0].gpio_defaults[2] ;
+ wire \gpio_control_in_2[0].gpio_defaults[3] ;
+ wire \gpio_control_in_2[0].gpio_defaults[4] ;
+ wire \gpio_control_in_2[0].gpio_defaults[5] ;
+ wire \gpio_control_in_2[0].gpio_defaults[6] ;
+ wire \gpio_control_in_2[0].gpio_defaults[7] ;
+ wire \gpio_control_in_2[0].gpio_defaults[8] ;
+ wire \gpio_control_in_2[0].gpio_defaults[9] ;
+ wire \gpio_control_in_2[0].gpio_inen ;
+ wire \gpio_control_in_2[0].gpio_oe_override ;
+ wire \gpio_control_in_2[0].gpio_outen ;
+ wire \gpio_control_in_2[0].gpio_pulldown_sel ;
+ wire \gpio_control_in_2[0].gpio_pullup_sel ;
+ wire \gpio_control_in_2[0].gpio_schmitt_sel ;
+ wire \gpio_control_in_2[0].gpio_slew_sel ;
+ wire \gpio_control_in_2[0].mgmt_ena ;
+ wire net2325;
+ wire \gpio_control_in_2[0].pad_gpio_out ;
+ wire \gpio_control_in_2[0].pad_gpio_outen ;
+ wire \gpio_control_in_2[0].resetn ;
+ wire \gpio_control_in_2[0].resetn_out ;
+ wire \gpio_control_in_2[0].serial_clock ;
+ wire \gpio_control_in_2[0].serial_clock_out ;
+ wire \gpio_control_in_2[0].serial_data_in ;
+ wire \gpio_control_in_2[0].serial_load ;
+ wire \gpio_control_in_2[0].serial_load_out ;
+ wire \gpio_control_in_2[0].shift_register[0] ;
+ wire \gpio_control_in_2[0].shift_register[1] ;
+ wire \gpio_control_in_2[0].shift_register[2] ;
+ wire \gpio_control_in_2[0].shift_register[3] ;
+ wire \gpio_control_in_2[0].shift_register[4] ;
+ wire \gpio_control_in_2[0].shift_register[5] ;
+ wire \gpio_control_in_2[0].shift_register[6] ;
+ wire \gpio_control_in_2[0].shift_register[7] ;
+ wire \gpio_control_in_2[0].shift_register[8] ;
+ wire \gpio_control_in_2[0].shift_register[9] ;
+ wire \gpio_control_in_2[10].gpio_defaults[0] ;
+ wire \gpio_control_in_2[10].gpio_defaults[1] ;
+ wire \gpio_control_in_2[10].gpio_defaults[2] ;
+ wire \gpio_control_in_2[10].gpio_defaults[3] ;
+ wire \gpio_control_in_2[10].gpio_defaults[4] ;
+ wire \gpio_control_in_2[10].gpio_defaults[5] ;
+ wire \gpio_control_in_2[10].gpio_defaults[6] ;
+ wire \gpio_control_in_2[10].gpio_defaults[7] ;
+ wire \gpio_control_in_2[10].gpio_defaults[8] ;
+ wire \gpio_control_in_2[10].gpio_defaults[9] ;
+ wire \gpio_control_in_2[10].gpio_inen ;
+ wire \gpio_control_in_2[10].gpio_oe_override ;
+ wire \gpio_control_in_2[10].gpio_outen ;
+ wire \gpio_control_in_2[10].gpio_pulldown_sel ;
+ wire \gpio_control_in_2[10].gpio_pullup_sel ;
+ wire \gpio_control_in_2[10].gpio_schmitt_sel ;
+ wire \gpio_control_in_2[10].gpio_slew_sel ;
+ wire \gpio_control_in_2[10].mgmt_ena ;
+ wire net2326;
+ wire \gpio_control_in_2[10].pad_gpio_out ;
+ wire \gpio_control_in_2[10].pad_gpio_outen ;
+ wire \gpio_control_in_2[10].resetn ;
+ wire \gpio_control_in_2[10].resetn_out ;
+ wire \gpio_control_in_2[10].serial_clock ;
+ wire \gpio_control_in_2[10].serial_clock_out ;
+ wire \gpio_control_in_2[10].serial_data_in ;
+ wire \gpio_control_in_2[10].serial_data_out ;
+ wire \gpio_control_in_2[10].serial_load ;
+ wire \gpio_control_in_2[10].serial_load_out ;
+ wire \gpio_control_in_2[10].shift_register[0] ;
+ wire \gpio_control_in_2[10].shift_register[1] ;
+ wire \gpio_control_in_2[10].shift_register[2] ;
+ wire \gpio_control_in_2[10].shift_register[3] ;
+ wire \gpio_control_in_2[10].shift_register[4] ;
+ wire \gpio_control_in_2[10].shift_register[5] ;
+ wire \gpio_control_in_2[10].shift_register[6] ;
+ wire \gpio_control_in_2[10].shift_register[7] ;
+ wire \gpio_control_in_2[10].shift_register[8] ;
+ wire \gpio_control_in_2[10].shift_register[9] ;
+ wire \gpio_control_in_2[11].gpio_defaults[0] ;
+ wire \gpio_control_in_2[11].gpio_defaults[1] ;
+ wire \gpio_control_in_2[11].gpio_defaults[2] ;
+ wire \gpio_control_in_2[11].gpio_defaults[3] ;
+ wire \gpio_control_in_2[11].gpio_defaults[4] ;
+ wire \gpio_control_in_2[11].gpio_defaults[5] ;
+ wire \gpio_control_in_2[11].gpio_defaults[6] ;
+ wire \gpio_control_in_2[11].gpio_defaults[7] ;
+ wire \gpio_control_in_2[11].gpio_defaults[8] ;
+ wire \gpio_control_in_2[11].gpio_defaults[9] ;
+ wire \gpio_control_in_2[11].gpio_inen ;
+ wire \gpio_control_in_2[11].gpio_oe_override ;
+ wire \gpio_control_in_2[11].gpio_outen ;
+ wire \gpio_control_in_2[11].gpio_pulldown_sel ;
+ wire \gpio_control_in_2[11].gpio_pullup_sel ;
+ wire \gpio_control_in_2[11].gpio_schmitt_sel ;
+ wire \gpio_control_in_2[11].gpio_slew_sel ;
+ wire \gpio_control_in_2[11].mgmt_ena ;
+ wire net2327;
+ wire \gpio_control_in_2[11].pad_gpio_out ;
+ wire \gpio_control_in_2[11].pad_gpio_outen ;
+ wire \gpio_control_in_2[11].resetn ;
+ wire \gpio_control_in_2[11].serial_clock ;
+ wire \gpio_control_in_2[11].serial_data_in ;
+ wire \gpio_control_in_2[11].serial_load ;
+ wire \gpio_control_in_2[11].shift_register[0] ;
+ wire \gpio_control_in_2[11].shift_register[1] ;
+ wire \gpio_control_in_2[11].shift_register[2] ;
+ wire \gpio_control_in_2[11].shift_register[3] ;
+ wire \gpio_control_in_2[11].shift_register[4] ;
+ wire \gpio_control_in_2[11].shift_register[5] ;
+ wire \gpio_control_in_2[11].shift_register[6] ;
+ wire \gpio_control_in_2[11].shift_register[7] ;
+ wire \gpio_control_in_2[11].shift_register[8] ;
+ wire \gpio_control_in_2[11].shift_register[9] ;
+ wire \gpio_control_in_2[12].gpio_defaults[0] ;
+ wire \gpio_control_in_2[12].gpio_defaults[1] ;
+ wire \gpio_control_in_2[12].gpio_defaults[2] ;
+ wire \gpio_control_in_2[12].gpio_defaults[3] ;
+ wire \gpio_control_in_2[12].gpio_defaults[4] ;
+ wire \gpio_control_in_2[12].gpio_defaults[5] ;
+ wire \gpio_control_in_2[12].gpio_defaults[6] ;
+ wire \gpio_control_in_2[12].gpio_defaults[7] ;
+ wire \gpio_control_in_2[12].gpio_defaults[8] ;
+ wire \gpio_control_in_2[12].gpio_defaults[9] ;
+ wire \gpio_control_in_2[12].gpio_inen ;
+ wire \gpio_control_in_2[12].gpio_oe_override ;
+ wire \gpio_control_in_2[12].gpio_outen ;
+ wire \gpio_control_in_2[12].gpio_pulldown_sel ;
+ wire \gpio_control_in_2[12].gpio_pullup_sel ;
+ wire \gpio_control_in_2[12].gpio_schmitt_sel ;
+ wire \gpio_control_in_2[12].gpio_slew_sel ;
+ wire \gpio_control_in_2[12].mgmt_ena ;
+ wire net2328;
+ wire \gpio_control_in_2[12].pad_gpio_out ;
+ wire \gpio_control_in_2[12].pad_gpio_outen ;
+ wire \gpio_control_in_2[12].resetn ;
+ wire \gpio_control_in_2[12].serial_clock ;
+ wire \gpio_control_in_2[12].serial_data_in ;
+ wire \gpio_control_in_2[12].serial_load ;
+ wire \gpio_control_in_2[12].shift_register[0] ;
+ wire \gpio_control_in_2[12].shift_register[1] ;
+ wire \gpio_control_in_2[12].shift_register[2] ;
+ wire \gpio_control_in_2[12].shift_register[3] ;
+ wire \gpio_control_in_2[12].shift_register[4] ;
+ wire \gpio_control_in_2[12].shift_register[5] ;
+ wire \gpio_control_in_2[12].shift_register[6] ;
+ wire \gpio_control_in_2[12].shift_register[7] ;
+ wire \gpio_control_in_2[12].shift_register[8] ;
+ wire \gpio_control_in_2[12].shift_register[9] ;
+ wire \gpio_control_in_2[13].gpio_defaults[0] ;
+ wire \gpio_control_in_2[13].gpio_defaults[1] ;
+ wire \gpio_control_in_2[13].gpio_defaults[2] ;
+ wire \gpio_control_in_2[13].gpio_defaults[3] ;
+ wire \gpio_control_in_2[13].gpio_defaults[4] ;
+ wire \gpio_control_in_2[13].gpio_defaults[5] ;
+ wire \gpio_control_in_2[13].gpio_defaults[6] ;
+ wire \gpio_control_in_2[13].gpio_defaults[7] ;
+ wire \gpio_control_in_2[13].gpio_defaults[8] ;
+ wire \gpio_control_in_2[13].gpio_defaults[9] ;
+ wire \gpio_control_in_2[13].gpio_inen ;
+ wire \gpio_control_in_2[13].gpio_oe_override ;
+ wire \gpio_control_in_2[13].gpio_outen ;
+ wire \gpio_control_in_2[13].gpio_pulldown_sel ;
+ wire \gpio_control_in_2[13].gpio_pullup_sel ;
+ wire \gpio_control_in_2[13].gpio_schmitt_sel ;
+ wire \gpio_control_in_2[13].gpio_slew_sel ;
+ wire \gpio_control_in_2[13].mgmt_ena ;
+ wire net2329;
+ wire \gpio_control_in_2[13].pad_gpio_out ;
+ wire \gpio_control_in_2[13].pad_gpio_outen ;
+ wire \gpio_control_in_2[13].resetn ;
+ wire \gpio_control_in_2[13].serial_clock ;
+ wire \gpio_control_in_2[13].serial_data_in ;
+ wire \gpio_control_in_2[13].serial_load ;
+ wire \gpio_control_in_2[13].shift_register[0] ;
+ wire \gpio_control_in_2[13].shift_register[1] ;
+ wire \gpio_control_in_2[13].shift_register[2] ;
+ wire \gpio_control_in_2[13].shift_register[3] ;
+ wire \gpio_control_in_2[13].shift_register[4] ;
+ wire \gpio_control_in_2[13].shift_register[5] ;
+ wire \gpio_control_in_2[13].shift_register[6] ;
+ wire \gpio_control_in_2[13].shift_register[7] ;
+ wire \gpio_control_in_2[13].shift_register[8] ;
+ wire \gpio_control_in_2[13].shift_register[9] ;
+ wire \gpio_control_in_2[14].gpio_defaults[0] ;
+ wire \gpio_control_in_2[14].gpio_defaults[1] ;
+ wire \gpio_control_in_2[14].gpio_defaults[2] ;
+ wire \gpio_control_in_2[14].gpio_defaults[3] ;
+ wire \gpio_control_in_2[14].gpio_defaults[4] ;
+ wire \gpio_control_in_2[14].gpio_defaults[5] ;
+ wire \gpio_control_in_2[14].gpio_defaults[6] ;
+ wire \gpio_control_in_2[14].gpio_defaults[7] ;
+ wire \gpio_control_in_2[14].gpio_defaults[8] ;
+ wire \gpio_control_in_2[14].gpio_defaults[9] ;
+ wire \gpio_control_in_2[14].gpio_inen ;
+ wire \gpio_control_in_2[14].gpio_oe_override ;
+ wire \gpio_control_in_2[14].gpio_outen ;
+ wire \gpio_control_in_2[14].gpio_pulldown_sel ;
+ wire \gpio_control_in_2[14].gpio_pullup_sel ;
+ wire \gpio_control_in_2[14].gpio_schmitt_sel ;
+ wire \gpio_control_in_2[14].gpio_slew_sel ;
+ wire \gpio_control_in_2[14].mgmt_ena ;
+ wire net2330;
+ wire \gpio_control_in_2[14].pad_gpio_out ;
+ wire \gpio_control_in_2[14].pad_gpio_outen ;
+ wire \gpio_control_in_2[14].resetn ;
+ wire \gpio_control_in_2[14].serial_clock ;
+ wire \gpio_control_in_2[14].serial_data_in ;
+ wire \gpio_control_in_2[14].serial_load ;
+ wire \gpio_control_in_2[14].shift_register[0] ;
+ wire \gpio_control_in_2[14].shift_register[1] ;
+ wire \gpio_control_in_2[14].shift_register[2] ;
+ wire \gpio_control_in_2[14].shift_register[3] ;
+ wire \gpio_control_in_2[14].shift_register[4] ;
+ wire \gpio_control_in_2[14].shift_register[5] ;
+ wire \gpio_control_in_2[14].shift_register[6] ;
+ wire \gpio_control_in_2[14].shift_register[7] ;
+ wire \gpio_control_in_2[14].shift_register[8] ;
+ wire \gpio_control_in_2[14].shift_register[9] ;
+ wire \gpio_control_in_2[15].gpio_defaults[0] ;
+ wire \gpio_control_in_2[15].gpio_defaults[1] ;
+ wire \gpio_control_in_2[15].gpio_defaults[2] ;
+ wire \gpio_control_in_2[15].gpio_defaults[3] ;
+ wire \gpio_control_in_2[15].gpio_defaults[4] ;
+ wire \gpio_control_in_2[15].gpio_defaults[5] ;
+ wire \gpio_control_in_2[15].gpio_defaults[6] ;
+ wire \gpio_control_in_2[15].gpio_defaults[7] ;
+ wire \gpio_control_in_2[15].gpio_defaults[8] ;
+ wire \gpio_control_in_2[15].gpio_defaults[9] ;
+ wire \gpio_control_in_2[15].gpio_inen ;
+ wire \gpio_control_in_2[15].gpio_oe_override ;
+ wire \gpio_control_in_2[15].gpio_outen ;
+ wire \gpio_control_in_2[15].gpio_pulldown_sel ;
+ wire \gpio_control_in_2[15].gpio_pullup_sel ;
+ wire \gpio_control_in_2[15].gpio_schmitt_sel ;
+ wire \gpio_control_in_2[15].gpio_slew_sel ;
+ wire \gpio_control_in_2[15].mgmt_ena ;
+ wire net2331;
+ wire \gpio_control_in_2[15].pad_gpio_out ;
+ wire \gpio_control_in_2[15].pad_gpio_outen ;
+ wire \gpio_control_in_2[15].shift_register[0] ;
+ wire \gpio_control_in_2[15].shift_register[1] ;
+ wire \gpio_control_in_2[15].shift_register[2] ;
+ wire \gpio_control_in_2[15].shift_register[3] ;
+ wire \gpio_control_in_2[15].shift_register[4] ;
+ wire \gpio_control_in_2[15].shift_register[5] ;
+ wire \gpio_control_in_2[15].shift_register[6] ;
+ wire \gpio_control_in_2[15].shift_register[7] ;
+ wire \gpio_control_in_2[15].shift_register[8] ;
+ wire \gpio_control_in_2[15].shift_register[9] ;
+ wire \gpio_control_in_2[1].gpio_defaults[0] ;
+ wire \gpio_control_in_2[1].gpio_defaults[1] ;
+ wire \gpio_control_in_2[1].gpio_defaults[2] ;
+ wire \gpio_control_in_2[1].gpio_defaults[3] ;
+ wire \gpio_control_in_2[1].gpio_defaults[4] ;
+ wire \gpio_control_in_2[1].gpio_defaults[5] ;
+ wire \gpio_control_in_2[1].gpio_defaults[6] ;
+ wire \gpio_control_in_2[1].gpio_defaults[7] ;
+ wire \gpio_control_in_2[1].gpio_defaults[8] ;
+ wire \gpio_control_in_2[1].gpio_defaults[9] ;
+ wire \gpio_control_in_2[1].gpio_inen ;
+ wire \gpio_control_in_2[1].gpio_oe_override ;
+ wire \gpio_control_in_2[1].gpio_outen ;
+ wire \gpio_control_in_2[1].gpio_pulldown_sel ;
+ wire \gpio_control_in_2[1].gpio_pullup_sel ;
+ wire \gpio_control_in_2[1].gpio_schmitt_sel ;
+ wire \gpio_control_in_2[1].gpio_slew_sel ;
+ wire \gpio_control_in_2[1].mgmt_ena ;
+ wire net2332;
+ wire \gpio_control_in_2[1].pad_gpio_out ;
+ wire \gpio_control_in_2[1].pad_gpio_outen ;
+ wire \gpio_control_in_2[1].resetn ;
+ wire \gpio_control_in_2[1].serial_clock ;
+ wire \gpio_control_in_2[1].serial_data_in ;
+ wire \gpio_control_in_2[1].serial_load ;
+ wire \gpio_control_in_2[1].shift_register[0] ;
+ wire \gpio_control_in_2[1].shift_register[1] ;
+ wire \gpio_control_in_2[1].shift_register[2] ;
+ wire \gpio_control_in_2[1].shift_register[3] ;
+ wire \gpio_control_in_2[1].shift_register[4] ;
+ wire \gpio_control_in_2[1].shift_register[5] ;
+ wire \gpio_control_in_2[1].shift_register[6] ;
+ wire \gpio_control_in_2[1].shift_register[7] ;
+ wire \gpio_control_in_2[1].shift_register[8] ;
+ wire \gpio_control_in_2[1].shift_register[9] ;
+ wire \gpio_control_in_2[2].gpio_defaults[0] ;
+ wire \gpio_control_in_2[2].gpio_defaults[1] ;
+ wire \gpio_control_in_2[2].gpio_defaults[2] ;
+ wire \gpio_control_in_2[2].gpio_defaults[3] ;
+ wire \gpio_control_in_2[2].gpio_defaults[4] ;
+ wire \gpio_control_in_2[2].gpio_defaults[5] ;
+ wire \gpio_control_in_2[2].gpio_defaults[6] ;
+ wire \gpio_control_in_2[2].gpio_defaults[7] ;
+ wire \gpio_control_in_2[2].gpio_defaults[8] ;
+ wire \gpio_control_in_2[2].gpio_defaults[9] ;
+ wire \gpio_control_in_2[2].gpio_inen ;
+ wire \gpio_control_in_2[2].gpio_oe_override ;
+ wire \gpio_control_in_2[2].gpio_outen ;
+ wire \gpio_control_in_2[2].gpio_pulldown_sel ;
+ wire \gpio_control_in_2[2].gpio_pullup_sel ;
+ wire \gpio_control_in_2[2].gpio_schmitt_sel ;
+ wire \gpio_control_in_2[2].gpio_slew_sel ;
+ wire \gpio_control_in_2[2].mgmt_ena ;
+ wire net2333;
+ wire \gpio_control_in_2[2].pad_gpio_out ;
+ wire \gpio_control_in_2[2].pad_gpio_outen ;
+ wire \gpio_control_in_2[2].resetn ;
+ wire \gpio_control_in_2[2].serial_clock ;
+ wire \gpio_control_in_2[2].serial_data_in ;
+ wire \gpio_control_in_2[2].serial_load ;
+ wire \gpio_control_in_2[2].shift_register[0] ;
+ wire \gpio_control_in_2[2].shift_register[1] ;
+ wire \gpio_control_in_2[2].shift_register[2] ;
+ wire \gpio_control_in_2[2].shift_register[3] ;
+ wire \gpio_control_in_2[2].shift_register[4] ;
+ wire \gpio_control_in_2[2].shift_register[5] ;
+ wire \gpio_control_in_2[2].shift_register[6] ;
+ wire \gpio_control_in_2[2].shift_register[7] ;
+ wire \gpio_control_in_2[2].shift_register[8] ;
+ wire \gpio_control_in_2[2].shift_register[9] ;
+ wire \gpio_control_in_2[3].gpio_defaults[0] ;
+ wire \gpio_control_in_2[3].gpio_defaults[1] ;
+ wire \gpio_control_in_2[3].gpio_defaults[2] ;
+ wire \gpio_control_in_2[3].gpio_defaults[3] ;
+ wire \gpio_control_in_2[3].gpio_defaults[4] ;
+ wire \gpio_control_in_2[3].gpio_defaults[5] ;
+ wire \gpio_control_in_2[3].gpio_defaults[6] ;
+ wire \gpio_control_in_2[3].gpio_defaults[7] ;
+ wire \gpio_control_in_2[3].gpio_defaults[8] ;
+ wire \gpio_control_in_2[3].gpio_defaults[9] ;
+ wire \gpio_control_in_2[3].gpio_inen ;
+ wire \gpio_control_in_2[3].gpio_oe_override ;
+ wire \gpio_control_in_2[3].gpio_outen ;
+ wire \gpio_control_in_2[3].gpio_pulldown_sel ;
+ wire \gpio_control_in_2[3].gpio_pullup_sel ;
+ wire \gpio_control_in_2[3].gpio_schmitt_sel ;
+ wire \gpio_control_in_2[3].gpio_slew_sel ;
+ wire \gpio_control_in_2[3].mgmt_ena ;
+ wire net2334;
+ wire \gpio_control_in_2[3].pad_gpio_out ;
+ wire \gpio_control_in_2[3].pad_gpio_outen ;
+ wire \gpio_control_in_2[3].resetn ;
+ wire \gpio_control_in_2[3].serial_clock ;
+ wire \gpio_control_in_2[3].serial_data_in ;
+ wire \gpio_control_in_2[3].serial_load ;
+ wire \gpio_control_in_2[3].shift_register[0] ;
+ wire \gpio_control_in_2[3].shift_register[1] ;
+ wire \gpio_control_in_2[3].shift_register[2] ;
+ wire \gpio_control_in_2[3].shift_register[3] ;
+ wire \gpio_control_in_2[3].shift_register[4] ;
+ wire \gpio_control_in_2[3].shift_register[5] ;
+ wire \gpio_control_in_2[3].shift_register[6] ;
+ wire \gpio_control_in_2[3].shift_register[7] ;
+ wire \gpio_control_in_2[3].shift_register[8] ;
+ wire \gpio_control_in_2[3].shift_register[9] ;
+ wire \gpio_control_in_2[4].gpio_defaults[0] ;
+ wire \gpio_control_in_2[4].gpio_defaults[1] ;
+ wire \gpio_control_in_2[4].gpio_defaults[2] ;
+ wire \gpio_control_in_2[4].gpio_defaults[3] ;
+ wire \gpio_control_in_2[4].gpio_defaults[4] ;
+ wire \gpio_control_in_2[4].gpio_defaults[5] ;
+ wire \gpio_control_in_2[4].gpio_defaults[6] ;
+ wire \gpio_control_in_2[4].gpio_defaults[7] ;
+ wire \gpio_control_in_2[4].gpio_defaults[8] ;
+ wire \gpio_control_in_2[4].gpio_defaults[9] ;
+ wire \gpio_control_in_2[4].gpio_inen ;
+ wire \gpio_control_in_2[4].gpio_oe_override ;
+ wire \gpio_control_in_2[4].gpio_outen ;
+ wire \gpio_control_in_2[4].gpio_pulldown_sel ;
+ wire \gpio_control_in_2[4].gpio_pullup_sel ;
+ wire \gpio_control_in_2[4].gpio_schmitt_sel ;
+ wire \gpio_control_in_2[4].gpio_slew_sel ;
+ wire \gpio_control_in_2[4].mgmt_ena ;
+ wire net2335;
+ wire \gpio_control_in_2[4].pad_gpio_out ;
+ wire \gpio_control_in_2[4].pad_gpio_outen ;
+ wire \gpio_control_in_2[4].resetn ;
+ wire \gpio_control_in_2[4].serial_clock ;
+ wire \gpio_control_in_2[4].serial_data_in ;
+ wire \gpio_control_in_2[4].serial_load ;
+ wire \gpio_control_in_2[4].shift_register[0] ;
+ wire \gpio_control_in_2[4].shift_register[1] ;
+ wire \gpio_control_in_2[4].shift_register[2] ;
+ wire \gpio_control_in_2[4].shift_register[3] ;
+ wire \gpio_control_in_2[4].shift_register[4] ;
+ wire \gpio_control_in_2[4].shift_register[5] ;
+ wire \gpio_control_in_2[4].shift_register[6] ;
+ wire \gpio_control_in_2[4].shift_register[7] ;
+ wire \gpio_control_in_2[4].shift_register[8] ;
+ wire \gpio_control_in_2[4].shift_register[9] ;
+ wire \gpio_control_in_2[5].gpio_defaults[0] ;
+ wire \gpio_control_in_2[5].gpio_defaults[1] ;
+ wire \gpio_control_in_2[5].gpio_defaults[2] ;
+ wire \gpio_control_in_2[5].gpio_defaults[3] ;
+ wire \gpio_control_in_2[5].gpio_defaults[4] ;
+ wire \gpio_control_in_2[5].gpio_defaults[5] ;
+ wire \gpio_control_in_2[5].gpio_defaults[6] ;
+ wire \gpio_control_in_2[5].gpio_defaults[7] ;
+ wire \gpio_control_in_2[5].gpio_defaults[8] ;
+ wire \gpio_control_in_2[5].gpio_defaults[9] ;
+ wire \gpio_control_in_2[5].gpio_inen ;
+ wire \gpio_control_in_2[5].gpio_oe_override ;
+ wire \gpio_control_in_2[5].gpio_outen ;
+ wire \gpio_control_in_2[5].gpio_pulldown_sel ;
+ wire \gpio_control_in_2[5].gpio_pullup_sel ;
+ wire \gpio_control_in_2[5].gpio_schmitt_sel ;
+ wire \gpio_control_in_2[5].gpio_slew_sel ;
+ wire \gpio_control_in_2[5].mgmt_ena ;
+ wire net2336;
+ wire \gpio_control_in_2[5].pad_gpio_out ;
+ wire \gpio_control_in_2[5].pad_gpio_outen ;
+ wire \gpio_control_in_2[5].resetn ;
+ wire \gpio_control_in_2[5].serial_clock ;
+ wire \gpio_control_in_2[5].serial_data_in ;
+ wire \gpio_control_in_2[5].serial_load ;
+ wire \gpio_control_in_2[5].shift_register[0] ;
+ wire \gpio_control_in_2[5].shift_register[1] ;
+ wire \gpio_control_in_2[5].shift_register[2] ;
+ wire \gpio_control_in_2[5].shift_register[3] ;
+ wire \gpio_control_in_2[5].shift_register[4] ;
+ wire \gpio_control_in_2[5].shift_register[5] ;
+ wire \gpio_control_in_2[5].shift_register[6] ;
+ wire \gpio_control_in_2[5].shift_register[7] ;
+ wire \gpio_control_in_2[5].shift_register[8] ;
+ wire \gpio_control_in_2[5].shift_register[9] ;
+ wire \gpio_control_in_2[6].gpio_defaults[0] ;
+ wire \gpio_control_in_2[6].gpio_defaults[1] ;
+ wire \gpio_control_in_2[6].gpio_defaults[2] ;
+ wire \gpio_control_in_2[6].gpio_defaults[3] ;
+ wire \gpio_control_in_2[6].gpio_defaults[4] ;
+ wire \gpio_control_in_2[6].gpio_defaults[5] ;
+ wire \gpio_control_in_2[6].gpio_defaults[6] ;
+ wire \gpio_control_in_2[6].gpio_defaults[7] ;
+ wire \gpio_control_in_2[6].gpio_defaults[8] ;
+ wire \gpio_control_in_2[6].gpio_defaults[9] ;
+ wire \gpio_control_in_2[6].gpio_inen ;
+ wire \gpio_control_in_2[6].gpio_oe_override ;
+ wire \gpio_control_in_2[6].gpio_outen ;
+ wire \gpio_control_in_2[6].gpio_pulldown_sel ;
+ wire \gpio_control_in_2[6].gpio_pullup_sel ;
+ wire \gpio_control_in_2[6].gpio_schmitt_sel ;
+ wire \gpio_control_in_2[6].gpio_slew_sel ;
+ wire \gpio_control_in_2[6].mgmt_ena ;
+ wire net2337;
+ wire \gpio_control_in_2[6].pad_gpio_out ;
+ wire \gpio_control_in_2[6].pad_gpio_outen ;
+ wire \gpio_control_in_2[6].resetn ;
+ wire \gpio_control_in_2[6].serial_clock ;
+ wire \gpio_control_in_2[6].serial_data_in ;
+ wire \gpio_control_in_2[6].serial_load ;
+ wire \gpio_control_in_2[6].shift_register[0] ;
+ wire \gpio_control_in_2[6].shift_register[1] ;
+ wire \gpio_control_in_2[6].shift_register[2] ;
+ wire \gpio_control_in_2[6].shift_register[3] ;
+ wire \gpio_control_in_2[6].shift_register[4] ;
+ wire \gpio_control_in_2[6].shift_register[5] ;
+ wire \gpio_control_in_2[6].shift_register[6] ;
+ wire \gpio_control_in_2[6].shift_register[7] ;
+ wire \gpio_control_in_2[6].shift_register[8] ;
+ wire \gpio_control_in_2[6].shift_register[9] ;
+ wire \gpio_control_in_2[7].gpio_defaults[0] ;
+ wire \gpio_control_in_2[7].gpio_defaults[1] ;
+ wire \gpio_control_in_2[7].gpio_defaults[2] ;
+ wire \gpio_control_in_2[7].gpio_defaults[3] ;
+ wire \gpio_control_in_2[7].gpio_defaults[4] ;
+ wire \gpio_control_in_2[7].gpio_defaults[5] ;
+ wire \gpio_control_in_2[7].gpio_defaults[6] ;
+ wire \gpio_control_in_2[7].gpio_defaults[7] ;
+ wire \gpio_control_in_2[7].gpio_defaults[8] ;
+ wire \gpio_control_in_2[7].gpio_defaults[9] ;
+ wire \gpio_control_in_2[7].gpio_inen ;
+ wire \gpio_control_in_2[7].gpio_oe_override ;
+ wire \gpio_control_in_2[7].gpio_outen ;
+ wire \gpio_control_in_2[7].gpio_pulldown_sel ;
+ wire \gpio_control_in_2[7].gpio_pullup_sel ;
+ wire \gpio_control_in_2[7].gpio_schmitt_sel ;
+ wire \gpio_control_in_2[7].gpio_slew_sel ;
+ wire \gpio_control_in_2[7].mgmt_ena ;
+ wire net2338;
+ wire \gpio_control_in_2[7].pad_gpio_out ;
+ wire \gpio_control_in_2[7].pad_gpio_outen ;
+ wire \gpio_control_in_2[7].resetn ;
+ wire \gpio_control_in_2[7].serial_clock ;
+ wire \gpio_control_in_2[7].serial_data_in ;
+ wire \gpio_control_in_2[7].serial_load ;
+ wire \gpio_control_in_2[7].shift_register[0] ;
+ wire \gpio_control_in_2[7].shift_register[1] ;
+ wire \gpio_control_in_2[7].shift_register[2] ;
+ wire \gpio_control_in_2[7].shift_register[3] ;
+ wire \gpio_control_in_2[7].shift_register[4] ;
+ wire \gpio_control_in_2[7].shift_register[5] ;
+ wire \gpio_control_in_2[7].shift_register[6] ;
+ wire \gpio_control_in_2[7].shift_register[7] ;
+ wire \gpio_control_in_2[7].shift_register[8] ;
+ wire \gpio_control_in_2[7].shift_register[9] ;
+ wire \gpio_control_in_2[8].gpio_defaults[0] ;
+ wire \gpio_control_in_2[8].gpio_defaults[1] ;
+ wire \gpio_control_in_2[8].gpio_defaults[2] ;
+ wire \gpio_control_in_2[8].gpio_defaults[3] ;
+ wire \gpio_control_in_2[8].gpio_defaults[4] ;
+ wire \gpio_control_in_2[8].gpio_defaults[5] ;
+ wire \gpio_control_in_2[8].gpio_defaults[6] ;
+ wire \gpio_control_in_2[8].gpio_defaults[7] ;
+ wire \gpio_control_in_2[8].gpio_defaults[8] ;
+ wire \gpio_control_in_2[8].gpio_defaults[9] ;
+ wire \gpio_control_in_2[8].gpio_inen ;
+ wire \gpio_control_in_2[8].gpio_oe_override ;
+ wire \gpio_control_in_2[8].gpio_outen ;
+ wire \gpio_control_in_2[8].gpio_pulldown_sel ;
+ wire \gpio_control_in_2[8].gpio_pullup_sel ;
+ wire \gpio_control_in_2[8].gpio_schmitt_sel ;
+ wire \gpio_control_in_2[8].gpio_slew_sel ;
+ wire \gpio_control_in_2[8].mgmt_ena ;
+ wire net2339;
+ wire \gpio_control_in_2[8].pad_gpio_out ;
+ wire \gpio_control_in_2[8].pad_gpio_outen ;
+ wire \gpio_control_in_2[8].resetn ;
+ wire \gpio_control_in_2[8].serial_clock ;
+ wire \gpio_control_in_2[8].serial_data_in ;
+ wire \gpio_control_in_2[8].serial_load ;
+ wire \gpio_control_in_2[8].shift_register[0] ;
+ wire \gpio_control_in_2[8].shift_register[1] ;
+ wire \gpio_control_in_2[8].shift_register[2] ;
+ wire \gpio_control_in_2[8].shift_register[3] ;
+ wire \gpio_control_in_2[8].shift_register[4] ;
+ wire \gpio_control_in_2[8].shift_register[5] ;
+ wire \gpio_control_in_2[8].shift_register[6] ;
+ wire \gpio_control_in_2[8].shift_register[7] ;
+ wire \gpio_control_in_2[8].shift_register[8] ;
+ wire \gpio_control_in_2[8].shift_register[9] ;
+ wire \gpio_control_in_2[9].gpio_defaults[0] ;
+ wire \gpio_control_in_2[9].gpio_defaults[1] ;
+ wire \gpio_control_in_2[9].gpio_defaults[2] ;
+ wire \gpio_control_in_2[9].gpio_defaults[3] ;
+ wire \gpio_control_in_2[9].gpio_defaults[4] ;
+ wire \gpio_control_in_2[9].gpio_defaults[5] ;
+ wire \gpio_control_in_2[9].gpio_defaults[6] ;
+ wire \gpio_control_in_2[9].gpio_defaults[7] ;
+ wire \gpio_control_in_2[9].gpio_defaults[8] ;
+ wire \gpio_control_in_2[9].gpio_defaults[9] ;
+ wire \gpio_control_in_2[9].gpio_inen ;
+ wire \gpio_control_in_2[9].gpio_oe_override ;
+ wire \gpio_control_in_2[9].gpio_outen ;
+ wire \gpio_control_in_2[9].gpio_pulldown_sel ;
+ wire \gpio_control_in_2[9].gpio_pullup_sel ;
+ wire \gpio_control_in_2[9].gpio_schmitt_sel ;
+ wire \gpio_control_in_2[9].gpio_slew_sel ;
+ wire \gpio_control_in_2[9].mgmt_ena ;
+ wire net2340;
+ wire \gpio_control_in_2[9].pad_gpio_out ;
+ wire \gpio_control_in_2[9].pad_gpio_outen ;
+ wire \gpio_control_in_2[9].shift_register[0] ;
+ wire \gpio_control_in_2[9].shift_register[1] ;
+ wire \gpio_control_in_2[9].shift_register[2] ;
+ wire \gpio_control_in_2[9].shift_register[3] ;
+ wire \gpio_control_in_2[9].shift_register[4] ;
+ wire \gpio_control_in_2[9].shift_register[5] ;
+ wire \gpio_control_in_2[9].shift_register[6] ;
+ wire \gpio_control_in_2[9].shift_register[7] ;
+ wire \gpio_control_in_2[9].shift_register[8] ;
+ wire \gpio_control_in_2[9].shift_register[9] ;
+ wire \irq_spi[0] ;
+ wire \irq_spi[1] ;
+ wire \irq_spi[2] ;
+ wire \mask_rev[0] ;
+ wire \mask_rev[10] ;
+ wire \mask_rev[11] ;
+ wire \mask_rev[12] ;
+ wire \mask_rev[13] ;
+ wire \mask_rev[14] ;
+ wire \mask_rev[15] ;
+ wire \mask_rev[16] ;
+ wire \mask_rev[17] ;
+ wire \mask_rev[18] ;
+ wire \mask_rev[19] ;
+ wire \mask_rev[1] ;
+ wire \mask_rev[20] ;
+ wire \mask_rev[21] ;
+ wire \mask_rev[22] ;
+ wire \mask_rev[23] ;
+ wire \mask_rev[24] ;
+ wire \mask_rev[25] ;
+ wire \mask_rev[26] ;
+ wire \mask_rev[27] ;
+ wire \mask_rev[28] ;
+ wire \mask_rev[29] ;
+ wire \mask_rev[2] ;
+ wire \mask_rev[30] ;
+ wire \mask_rev[31] ;
+ wire \mask_rev[3] ;
+ wire \mask_rev[4] ;
+ wire \mask_rev[5] ;
+ wire \mask_rev[6] ;
+ wire \mask_rev[7] ;
+ wire \mask_rev[8] ;
+ wire \mask_rev[9] ;
+ wire \mgmt_buffers.la_data_in_core[0] ;
+ wire \mgmt_buffers.la_data_in_core[10] ;
+ wire \mgmt_buffers.la_data_in_core[11] ;
+ wire \mgmt_buffers.la_data_in_core[12] ;
+ wire \mgmt_buffers.la_data_in_core[13] ;
+ wire \mgmt_buffers.la_data_in_core[14] ;
+ wire \mgmt_buffers.la_data_in_core[15] ;
+ wire \mgmt_buffers.la_data_in_core[16] ;
+ wire \mgmt_buffers.la_data_in_core[17] ;
+ wire \mgmt_buffers.la_data_in_core[18] ;
+ wire \mgmt_buffers.la_data_in_core[19] ;
+ wire \mgmt_buffers.la_data_in_core[1] ;
+ wire \mgmt_buffers.la_data_in_core[20] ;
+ wire \mgmt_buffers.la_data_in_core[21] ;
+ wire \mgmt_buffers.la_data_in_core[22] ;
+ wire \mgmt_buffers.la_data_in_core[23] ;
+ wire \mgmt_buffers.la_data_in_core[24] ;
+ wire \mgmt_buffers.la_data_in_core[25] ;
+ wire \mgmt_buffers.la_data_in_core[26] ;
+ wire \mgmt_buffers.la_data_in_core[27] ;
+ wire \mgmt_buffers.la_data_in_core[28] ;
+ wire \mgmt_buffers.la_data_in_core[29] ;
+ wire \mgmt_buffers.la_data_in_core[2] ;
+ wire \mgmt_buffers.la_data_in_core[30] ;
+ wire \mgmt_buffers.la_data_in_core[31] ;
+ wire \mgmt_buffers.la_data_in_core[32] ;
+ wire \mgmt_buffers.la_data_in_core[33] ;
+ wire \mgmt_buffers.la_data_in_core[34] ;
+ wire \mgmt_buffers.la_data_in_core[35] ;
+ wire \mgmt_buffers.la_data_in_core[36] ;
+ wire \mgmt_buffers.la_data_in_core[37] ;
+ wire \mgmt_buffers.la_data_in_core[38] ;
+ wire \mgmt_buffers.la_data_in_core[39] ;
+ wire \mgmt_buffers.la_data_in_core[3] ;
+ wire \mgmt_buffers.la_data_in_core[40] ;
+ wire \mgmt_buffers.la_data_in_core[41] ;
+ wire \mgmt_buffers.la_data_in_core[42] ;
+ wire \mgmt_buffers.la_data_in_core[43] ;
+ wire \mgmt_buffers.la_data_in_core[44] ;
+ wire \mgmt_buffers.la_data_in_core[45] ;
+ wire \mgmt_buffers.la_data_in_core[46] ;
+ wire \mgmt_buffers.la_data_in_core[47] ;
+ wire \mgmt_buffers.la_data_in_core[48] ;
+ wire \mgmt_buffers.la_data_in_core[49] ;
+ wire \mgmt_buffers.la_data_in_core[4] ;
+ wire \mgmt_buffers.la_data_in_core[50] ;
+ wire \mgmt_buffers.la_data_in_core[51] ;
+ wire \mgmt_buffers.la_data_in_core[52] ;
+ wire \mgmt_buffers.la_data_in_core[53] ;
+ wire \mgmt_buffers.la_data_in_core[54] ;
+ wire \mgmt_buffers.la_data_in_core[55] ;
+ wire \mgmt_buffers.la_data_in_core[56] ;
+ wire \mgmt_buffers.la_data_in_core[57] ;
+ wire \mgmt_buffers.la_data_in_core[58] ;
+ wire \mgmt_buffers.la_data_in_core[59] ;
+ wire \mgmt_buffers.la_data_in_core[5] ;
+ wire \mgmt_buffers.la_data_in_core[60] ;
+ wire \mgmt_buffers.la_data_in_core[61] ;
+ wire \mgmt_buffers.la_data_in_core[62] ;
+ wire \mgmt_buffers.la_data_in_core[63] ;
+ wire \mgmt_buffers.la_data_in_core[6] ;
+ wire \mgmt_buffers.la_data_in_core[7] ;
+ wire \mgmt_buffers.la_data_in_core[8] ;
+ wire \mgmt_buffers.la_data_in_core[9] ;
+ wire \mgmt_buffers.la_data_in_enable[0] ;
+ wire \mgmt_buffers.la_data_in_enable[10] ;
+ wire \mgmt_buffers.la_data_in_enable[11] ;
+ wire \mgmt_buffers.la_data_in_enable[12] ;
+ wire \mgmt_buffers.la_data_in_enable[13] ;
+ wire \mgmt_buffers.la_data_in_enable[14] ;
+ wire \mgmt_buffers.la_data_in_enable[15] ;
+ wire \mgmt_buffers.la_data_in_enable[16] ;
+ wire \mgmt_buffers.la_data_in_enable[17] ;
+ wire \mgmt_buffers.la_data_in_enable[18] ;
+ wire \mgmt_buffers.la_data_in_enable[19] ;
+ wire \mgmt_buffers.la_data_in_enable[1] ;
+ wire \mgmt_buffers.la_data_in_enable[20] ;
+ wire \mgmt_buffers.la_data_in_enable[21] ;
+ wire \mgmt_buffers.la_data_in_enable[22] ;
+ wire \mgmt_buffers.la_data_in_enable[23] ;
+ wire \mgmt_buffers.la_data_in_enable[24] ;
+ wire \mgmt_buffers.la_data_in_enable[25] ;
+ wire \mgmt_buffers.la_data_in_enable[26] ;
+ wire \mgmt_buffers.la_data_in_enable[27] ;
+ wire \mgmt_buffers.la_data_in_enable[28] ;
+ wire \mgmt_buffers.la_data_in_enable[29] ;
+ wire \mgmt_buffers.la_data_in_enable[2] ;
+ wire \mgmt_buffers.la_data_in_enable[30] ;
+ wire \mgmt_buffers.la_data_in_enable[31] ;
+ wire \mgmt_buffers.la_data_in_enable[32] ;
+ wire \mgmt_buffers.la_data_in_enable[33] ;
+ wire \mgmt_buffers.la_data_in_enable[34] ;
+ wire \mgmt_buffers.la_data_in_enable[35] ;
+ wire \mgmt_buffers.la_data_in_enable[36] ;
+ wire \mgmt_buffers.la_data_in_enable[37] ;
+ wire \mgmt_buffers.la_data_in_enable[38] ;
+ wire \mgmt_buffers.la_data_in_enable[39] ;
+ wire \mgmt_buffers.la_data_in_enable[3] ;
+ wire \mgmt_buffers.la_data_in_enable[40] ;
+ wire \mgmt_buffers.la_data_in_enable[41] ;
+ wire \mgmt_buffers.la_data_in_enable[42] ;
+ wire \mgmt_buffers.la_data_in_enable[43] ;
+ wire \mgmt_buffers.la_data_in_enable[44] ;
+ wire \mgmt_buffers.la_data_in_enable[45] ;
+ wire \mgmt_buffers.la_data_in_enable[46] ;
+ wire \mgmt_buffers.la_data_in_enable[47] ;
+ wire \mgmt_buffers.la_data_in_enable[48] ;
+ wire \mgmt_buffers.la_data_in_enable[49] ;
+ wire \mgmt_buffers.la_data_in_enable[4] ;
+ wire \mgmt_buffers.la_data_in_enable[50] ;
+ wire \mgmt_buffers.la_data_in_enable[51] ;
+ wire \mgmt_buffers.la_data_in_enable[52] ;
+ wire \mgmt_buffers.la_data_in_enable[53] ;
+ wire \mgmt_buffers.la_data_in_enable[54] ;
+ wire \mgmt_buffers.la_data_in_enable[55] ;
+ wire \mgmt_buffers.la_data_in_enable[56] ;
+ wire \mgmt_buffers.la_data_in_enable[57] ;
+ wire \mgmt_buffers.la_data_in_enable[58] ;
+ wire \mgmt_buffers.la_data_in_enable[59] ;
+ wire \mgmt_buffers.la_data_in_enable[5] ;
+ wire \mgmt_buffers.la_data_in_enable[60] ;
+ wire \mgmt_buffers.la_data_in_enable[61] ;
+ wire \mgmt_buffers.la_data_in_enable[62] ;
+ wire \mgmt_buffers.la_data_in_enable[63] ;
+ wire \mgmt_buffers.la_data_in_enable[6] ;
+ wire \mgmt_buffers.la_data_in_enable[7] ;
+ wire \mgmt_buffers.la_data_in_enable[8] ;
+ wire \mgmt_buffers.la_data_in_enable[9] ;
+ wire \mgmt_buffers.la_data_in_mprj[0] ;
+ wire \mgmt_buffers.la_data_in_mprj[10] ;
+ wire \mgmt_buffers.la_data_in_mprj[11] ;
+ wire \mgmt_buffers.la_data_in_mprj[12] ;
+ wire \mgmt_buffers.la_data_in_mprj[13] ;
+ wire \mgmt_buffers.la_data_in_mprj[14] ;
+ wire \mgmt_buffers.la_data_in_mprj[15] ;
+ wire \mgmt_buffers.la_data_in_mprj[16] ;
+ wire \mgmt_buffers.la_data_in_mprj[17] ;
+ wire \mgmt_buffers.la_data_in_mprj[18] ;
+ wire \mgmt_buffers.la_data_in_mprj[19] ;
+ wire \mgmt_buffers.la_data_in_mprj[1] ;
+ wire \mgmt_buffers.la_data_in_mprj[20] ;
+ wire \mgmt_buffers.la_data_in_mprj[21] ;
+ wire \mgmt_buffers.la_data_in_mprj[22] ;
+ wire \mgmt_buffers.la_data_in_mprj[23] ;
+ wire \mgmt_buffers.la_data_in_mprj[24] ;
+ wire \mgmt_buffers.la_data_in_mprj[25] ;
+ wire \mgmt_buffers.la_data_in_mprj[26] ;
+ wire \mgmt_buffers.la_data_in_mprj[27] ;
+ wire \mgmt_buffers.la_data_in_mprj[28] ;
+ wire \mgmt_buffers.la_data_in_mprj[29] ;
+ wire \mgmt_buffers.la_data_in_mprj[2] ;
+ wire \mgmt_buffers.la_data_in_mprj[30] ;
+ wire \mgmt_buffers.la_data_in_mprj[31] ;
+ wire \mgmt_buffers.la_data_in_mprj[32] ;
+ wire \mgmt_buffers.la_data_in_mprj[33] ;
+ wire \mgmt_buffers.la_data_in_mprj[34] ;
+ wire \mgmt_buffers.la_data_in_mprj[35] ;
+ wire \mgmt_buffers.la_data_in_mprj[36] ;
+ wire \mgmt_buffers.la_data_in_mprj[37] ;
+ wire \mgmt_buffers.la_data_in_mprj[38] ;
+ wire \mgmt_buffers.la_data_in_mprj[39] ;
+ wire \mgmt_buffers.la_data_in_mprj[3] ;
+ wire \mgmt_buffers.la_data_in_mprj[40] ;
+ wire \mgmt_buffers.la_data_in_mprj[41] ;
+ wire \mgmt_buffers.la_data_in_mprj[42] ;
+ wire \mgmt_buffers.la_data_in_mprj[43] ;
+ wire \mgmt_buffers.la_data_in_mprj[44] ;
+ wire \mgmt_buffers.la_data_in_mprj[45] ;
+ wire \mgmt_buffers.la_data_in_mprj[46] ;
+ wire \mgmt_buffers.la_data_in_mprj[47] ;
+ wire \mgmt_buffers.la_data_in_mprj[48] ;
+ wire \mgmt_buffers.la_data_in_mprj[49] ;
+ wire \mgmt_buffers.la_data_in_mprj[4] ;
+ wire \mgmt_buffers.la_data_in_mprj[50] ;
+ wire \mgmt_buffers.la_data_in_mprj[51] ;
+ wire \mgmt_buffers.la_data_in_mprj[52] ;
+ wire \mgmt_buffers.la_data_in_mprj[53] ;
+ wire \mgmt_buffers.la_data_in_mprj[54] ;
+ wire \mgmt_buffers.la_data_in_mprj[55] ;
+ wire \mgmt_buffers.la_data_in_mprj[56] ;
+ wire \mgmt_buffers.la_data_in_mprj[57] ;
+ wire \mgmt_buffers.la_data_in_mprj[58] ;
+ wire \mgmt_buffers.la_data_in_mprj[59] ;
+ wire \mgmt_buffers.la_data_in_mprj[5] ;
+ wire \mgmt_buffers.la_data_in_mprj[60] ;
+ wire \mgmt_buffers.la_data_in_mprj[61] ;
+ wire \mgmt_buffers.la_data_in_mprj[62] ;
+ wire \mgmt_buffers.la_data_in_mprj[63] ;
+ wire \mgmt_buffers.la_data_in_mprj[6] ;
+ wire \mgmt_buffers.la_data_in_mprj[7] ;
+ wire \mgmt_buffers.la_data_in_mprj[8] ;
+ wire \mgmt_buffers.la_data_in_mprj[9] ;
+ wire \mgmt_buffers.la_data_in_mprj_bar[0] ;
+ wire \mgmt_buffers.la_data_in_mprj_bar[10] ;
+ wire \mgmt_buffers.la_data_in_mprj_bar[11] ;
+ wire \mgmt_buffers.la_data_in_mprj_bar[12] ;
+ wire \mgmt_buffers.la_data_in_mprj_bar[13] ;
+ wire \mgmt_buffers.la_data_in_mprj_bar[14] ;
+ wire \mgmt_buffers.la_data_in_mprj_bar[15] ;
+ wire \mgmt_buffers.la_data_in_mprj_bar[16] ;
+ wire \mgmt_buffers.la_data_in_mprj_bar[17] ;
+ wire \mgmt_buffers.la_data_in_mprj_bar[18] ;
+ wire \mgmt_buffers.la_data_in_mprj_bar[19] ;
+ wire \mgmt_buffers.la_data_in_mprj_bar[1] ;
+ wire \mgmt_buffers.la_data_in_mprj_bar[20] ;
+ wire \mgmt_buffers.la_data_in_mprj_bar[21] ;
+ wire \mgmt_buffers.la_data_in_mprj_bar[22] ;
+ wire \mgmt_buffers.la_data_in_mprj_bar[23] ;
+ wire \mgmt_buffers.la_data_in_mprj_bar[24] ;
+ wire \mgmt_buffers.la_data_in_mprj_bar[25] ;
+ wire \mgmt_buffers.la_data_in_mprj_bar[26] ;
+ wire \mgmt_buffers.la_data_in_mprj_bar[27] ;
+ wire \mgmt_buffers.la_data_in_mprj_bar[28] ;
+ wire \mgmt_buffers.la_data_in_mprj_bar[29] ;
+ wire \mgmt_buffers.la_data_in_mprj_bar[2] ;
+ wire \mgmt_buffers.la_data_in_mprj_bar[30] ;
+ wire \mgmt_buffers.la_data_in_mprj_bar[31] ;
+ wire \mgmt_buffers.la_data_in_mprj_bar[32] ;
+ wire \mgmt_buffers.la_data_in_mprj_bar[33] ;
+ wire \mgmt_buffers.la_data_in_mprj_bar[34] ;
+ wire \mgmt_buffers.la_data_in_mprj_bar[35] ;
+ wire \mgmt_buffers.la_data_in_mprj_bar[36] ;
+ wire \mgmt_buffers.la_data_in_mprj_bar[37] ;
+ wire \mgmt_buffers.la_data_in_mprj_bar[38] ;
+ wire \mgmt_buffers.la_data_in_mprj_bar[39] ;
+ wire \mgmt_buffers.la_data_in_mprj_bar[3] ;
+ wire \mgmt_buffers.la_data_in_mprj_bar[40] ;
+ wire \mgmt_buffers.la_data_in_mprj_bar[41] ;
+ wire \mgmt_buffers.la_data_in_mprj_bar[42] ;
+ wire \mgmt_buffers.la_data_in_mprj_bar[43] ;
+ wire \mgmt_buffers.la_data_in_mprj_bar[44] ;
+ wire \mgmt_buffers.la_data_in_mprj_bar[45] ;
+ wire \mgmt_buffers.la_data_in_mprj_bar[46] ;
+ wire \mgmt_buffers.la_data_in_mprj_bar[47] ;
+ wire \mgmt_buffers.la_data_in_mprj_bar[48] ;
+ wire \mgmt_buffers.la_data_in_mprj_bar[49] ;
+ wire \mgmt_buffers.la_data_in_mprj_bar[4] ;
+ wire \mgmt_buffers.la_data_in_mprj_bar[50] ;
+ wire \mgmt_buffers.la_data_in_mprj_bar[51] ;
+ wire \mgmt_buffers.la_data_in_mprj_bar[52] ;
+ wire \mgmt_buffers.la_data_in_mprj_bar[53] ;
+ wire \mgmt_buffers.la_data_in_mprj_bar[54] ;
+ wire \mgmt_buffers.la_data_in_mprj_bar[55] ;
+ wire \mgmt_buffers.la_data_in_mprj_bar[56] ;
+ wire \mgmt_buffers.la_data_in_mprj_bar[57] ;
+ wire \mgmt_buffers.la_data_in_mprj_bar[58] ;
+ wire \mgmt_buffers.la_data_in_mprj_bar[59] ;
+ wire \mgmt_buffers.la_data_in_mprj_bar[5] ;
+ wire \mgmt_buffers.la_data_in_mprj_bar[60] ;
+ wire \mgmt_buffers.la_data_in_mprj_bar[61] ;
+ wire \mgmt_buffers.la_data_in_mprj_bar[62] ;
+ wire \mgmt_buffers.la_data_in_mprj_bar[63] ;
+ wire \mgmt_buffers.la_data_in_mprj_bar[6] ;
+ wire \mgmt_buffers.la_data_in_mprj_bar[7] ;
+ wire \mgmt_buffers.la_data_in_mprj_bar[8] ;
+ wire \mgmt_buffers.la_data_in_mprj_bar[9] ;
+ wire \mgmt_buffers.la_data_out_core[0] ;
+ wire \mgmt_buffers.la_data_out_core[10] ;
+ wire \mgmt_buffers.la_data_out_core[11] ;
+ wire \mgmt_buffers.la_data_out_core[12] ;
+ wire \mgmt_buffers.la_data_out_core[13] ;
+ wire \mgmt_buffers.la_data_out_core[14] ;
+ wire \mgmt_buffers.la_data_out_core[15] ;
+ wire \mgmt_buffers.la_data_out_core[16] ;
+ wire \mgmt_buffers.la_data_out_core[17] ;
+ wire \mgmt_buffers.la_data_out_core[18] ;
+ wire \mgmt_buffers.la_data_out_core[19] ;
+ wire \mgmt_buffers.la_data_out_core[1] ;
+ wire \mgmt_buffers.la_data_out_core[20] ;
+ wire \mgmt_buffers.la_data_out_core[21] ;
+ wire \mgmt_buffers.la_data_out_core[22] ;
+ wire \mgmt_buffers.la_data_out_core[23] ;
+ wire \mgmt_buffers.la_data_out_core[24] ;
+ wire \mgmt_buffers.la_data_out_core[25] ;
+ wire \mgmt_buffers.la_data_out_core[26] ;
+ wire \mgmt_buffers.la_data_out_core[27] ;
+ wire \mgmt_buffers.la_data_out_core[28] ;
+ wire \mgmt_buffers.la_data_out_core[29] ;
+ wire \mgmt_buffers.la_data_out_core[2] ;
+ wire \mgmt_buffers.la_data_out_core[30] ;
+ wire \mgmt_buffers.la_data_out_core[31] ;
+ wire \mgmt_buffers.la_data_out_core[32] ;
+ wire \mgmt_buffers.la_data_out_core[33] ;
+ wire \mgmt_buffers.la_data_out_core[34] ;
+ wire \mgmt_buffers.la_data_out_core[35] ;
+ wire \mgmt_buffers.la_data_out_core[36] ;
+ wire \mgmt_buffers.la_data_out_core[37] ;
+ wire \mgmt_buffers.la_data_out_core[38] ;
+ wire \mgmt_buffers.la_data_out_core[39] ;
+ wire \mgmt_buffers.la_data_out_core[3] ;
+ wire \mgmt_buffers.la_data_out_core[40] ;
+ wire \mgmt_buffers.la_data_out_core[41] ;
+ wire \mgmt_buffers.la_data_out_core[42] ;
+ wire \mgmt_buffers.la_data_out_core[43] ;
+ wire \mgmt_buffers.la_data_out_core[44] ;
+ wire \mgmt_buffers.la_data_out_core[45] ;
+ wire \mgmt_buffers.la_data_out_core[46] ;
+ wire \mgmt_buffers.la_data_out_core[47] ;
+ wire \mgmt_buffers.la_data_out_core[48] ;
+ wire \mgmt_buffers.la_data_out_core[49] ;
+ wire \mgmt_buffers.la_data_out_core[4] ;
+ wire \mgmt_buffers.la_data_out_core[50] ;
+ wire \mgmt_buffers.la_data_out_core[51] ;
+ wire \mgmt_buffers.la_data_out_core[52] ;
+ wire \mgmt_buffers.la_data_out_core[53] ;
+ wire \mgmt_buffers.la_data_out_core[54] ;
+ wire \mgmt_buffers.la_data_out_core[55] ;
+ wire \mgmt_buffers.la_data_out_core[56] ;
+ wire \mgmt_buffers.la_data_out_core[57] ;
+ wire \mgmt_buffers.la_data_out_core[58] ;
+ wire \mgmt_buffers.la_data_out_core[59] ;
+ wire \mgmt_buffers.la_data_out_core[5] ;
+ wire \mgmt_buffers.la_data_out_core[60] ;
+ wire \mgmt_buffers.la_data_out_core[61] ;
+ wire \mgmt_buffers.la_data_out_core[62] ;
+ wire \mgmt_buffers.la_data_out_core[63] ;
+ wire \mgmt_buffers.la_data_out_core[6] ;
+ wire \mgmt_buffers.la_data_out_core[7] ;
+ wire \mgmt_buffers.la_data_out_core[8] ;
+ wire \mgmt_buffers.la_data_out_core[9] ;
+ wire \mgmt_buffers.la_oenb_core[0] ;
+ wire \mgmt_buffers.la_oenb_core[10] ;
+ wire \mgmt_buffers.la_oenb_core[11] ;
+ wire \mgmt_buffers.la_oenb_core[12] ;
+ wire \mgmt_buffers.la_oenb_core[13] ;
+ wire \mgmt_buffers.la_oenb_core[14] ;
+ wire \mgmt_buffers.la_oenb_core[15] ;
+ wire \mgmt_buffers.la_oenb_core[16] ;
+ wire \mgmt_buffers.la_oenb_core[17] ;
+ wire \mgmt_buffers.la_oenb_core[18] ;
+ wire \mgmt_buffers.la_oenb_core[19] ;
+ wire \mgmt_buffers.la_oenb_core[1] ;
+ wire \mgmt_buffers.la_oenb_core[20] ;
+ wire \mgmt_buffers.la_oenb_core[21] ;
+ wire \mgmt_buffers.la_oenb_core[22] ;
+ wire \mgmt_buffers.la_oenb_core[23] ;
+ wire \mgmt_buffers.la_oenb_core[24] ;
+ wire \mgmt_buffers.la_oenb_core[25] ;
+ wire \mgmt_buffers.la_oenb_core[26] ;
+ wire \mgmt_buffers.la_oenb_core[27] ;
+ wire \mgmt_buffers.la_oenb_core[28] ;
+ wire \mgmt_buffers.la_oenb_core[29] ;
+ wire \mgmt_buffers.la_oenb_core[2] ;
+ wire \mgmt_buffers.la_oenb_core[30] ;
+ wire \mgmt_buffers.la_oenb_core[31] ;
+ wire \mgmt_buffers.la_oenb_core[32] ;
+ wire \mgmt_buffers.la_oenb_core[33] ;
+ wire \mgmt_buffers.la_oenb_core[34] ;
+ wire \mgmt_buffers.la_oenb_core[35] ;
+ wire \mgmt_buffers.la_oenb_core[36] ;
+ wire \mgmt_buffers.la_oenb_core[37] ;
+ wire \mgmt_buffers.la_oenb_core[38] ;
+ wire \mgmt_buffers.la_oenb_core[39] ;
+ wire \mgmt_buffers.la_oenb_core[3] ;
+ wire \mgmt_buffers.la_oenb_core[40] ;
+ wire \mgmt_buffers.la_oenb_core[41] ;
+ wire \mgmt_buffers.la_oenb_core[42] ;
+ wire \mgmt_buffers.la_oenb_core[43] ;
+ wire \mgmt_buffers.la_oenb_core[44] ;
+ wire \mgmt_buffers.la_oenb_core[45] ;
+ wire \mgmt_buffers.la_oenb_core[46] ;
+ wire \mgmt_buffers.la_oenb_core[47] ;
+ wire \mgmt_buffers.la_oenb_core[48] ;
+ wire \mgmt_buffers.la_oenb_core[49] ;
+ wire \mgmt_buffers.la_oenb_core[4] ;
+ wire \mgmt_buffers.la_oenb_core[50] ;
+ wire \mgmt_buffers.la_oenb_core[51] ;
+ wire \mgmt_buffers.la_oenb_core[52] ;
+ wire \mgmt_buffers.la_oenb_core[53] ;
+ wire \mgmt_buffers.la_oenb_core[54] ;
+ wire \mgmt_buffers.la_oenb_core[55] ;
+ wire \mgmt_buffers.la_oenb_core[56] ;
+ wire \mgmt_buffers.la_oenb_core[57] ;
+ wire \mgmt_buffers.la_oenb_core[58] ;
+ wire \mgmt_buffers.la_oenb_core[59] ;
+ wire \mgmt_buffers.la_oenb_core[5] ;
+ wire \mgmt_buffers.la_oenb_core[60] ;
+ wire \mgmt_buffers.la_oenb_core[61] ;
+ wire \mgmt_buffers.la_oenb_core[62] ;
+ wire \mgmt_buffers.la_oenb_core[63] ;
+ wire \mgmt_buffers.la_oenb_core[6] ;
+ wire \mgmt_buffers.la_oenb_core[7] ;
+ wire \mgmt_buffers.la_oenb_core[8] ;
+ wire \mgmt_buffers.la_oenb_core[9] ;
+ wire \mgmt_buffers.mprj_ack_i_core_bar ;
+ wire \mgmt_buffers.mprj_ack_i_user ;
+ wire \mgmt_buffers.mprj_adr_o_core[10] ;
+ wire \mgmt_buffers.mprj_adr_o_core[11] ;
+ wire \mgmt_buffers.mprj_adr_o_core[12] ;
+ wire \mgmt_buffers.mprj_adr_o_core[13] ;
+ wire \mgmt_buffers.mprj_adr_o_core[14] ;
+ wire \mgmt_buffers.mprj_adr_o_core[15] ;
+ wire \mgmt_buffers.mprj_adr_o_core[16] ;
+ wire \mgmt_buffers.mprj_adr_o_core[17] ;
+ wire \mgmt_buffers.mprj_adr_o_core[18] ;
+ wire \mgmt_buffers.mprj_adr_o_core[19] ;
+ wire \mgmt_buffers.mprj_adr_o_core[20] ;
+ wire \mgmt_buffers.mprj_adr_o_core[21] ;
+ wire \mgmt_buffers.mprj_adr_o_core[22] ;
+ wire \mgmt_buffers.mprj_adr_o_core[23] ;
+ wire \mgmt_buffers.mprj_adr_o_core[24] ;
+ wire \mgmt_buffers.mprj_adr_o_core[25] ;
+ wire \mgmt_buffers.mprj_adr_o_core[26] ;
+ wire \mgmt_buffers.mprj_adr_o_core[27] ;
+ wire \mgmt_buffers.mprj_adr_o_core[28] ;
+ wire \mgmt_buffers.mprj_adr_o_core[29] ;
+ wire \mgmt_buffers.mprj_adr_o_core[2] ;
+ wire \mgmt_buffers.mprj_adr_o_core[30] ;
+ wire \mgmt_buffers.mprj_adr_o_core[31] ;
+ wire \mgmt_buffers.mprj_adr_o_core[3] ;
+ wire \mgmt_buffers.mprj_adr_o_core[4] ;
+ wire \mgmt_buffers.mprj_adr_o_core[5] ;
+ wire \mgmt_buffers.mprj_adr_o_core[6] ;
+ wire \mgmt_buffers.mprj_adr_o_core[7] ;
+ wire \mgmt_buffers.mprj_adr_o_core[8] ;
+ wire \mgmt_buffers.mprj_adr_o_core[9] ;
+ wire \mgmt_buffers.mprj_cyc_o_core ;
+ wire \mgmt_buffers.mprj_dat_i_core_bar[0] ;
+ wire \mgmt_buffers.mprj_dat_i_core_bar[10] ;
+ wire \mgmt_buffers.mprj_dat_i_core_bar[11] ;
+ wire \mgmt_buffers.mprj_dat_i_core_bar[12] ;
+ wire \mgmt_buffers.mprj_dat_i_core_bar[13] ;
+ wire \mgmt_buffers.mprj_dat_i_core_bar[14] ;
+ wire \mgmt_buffers.mprj_dat_i_core_bar[15] ;
+ wire \mgmt_buffers.mprj_dat_i_core_bar[16] ;
+ wire \mgmt_buffers.mprj_dat_i_core_bar[17] ;
+ wire \mgmt_buffers.mprj_dat_i_core_bar[18] ;
+ wire \mgmt_buffers.mprj_dat_i_core_bar[19] ;
+ wire \mgmt_buffers.mprj_dat_i_core_bar[1] ;
+ wire \mgmt_buffers.mprj_dat_i_core_bar[20] ;
+ wire \mgmt_buffers.mprj_dat_i_core_bar[21] ;
+ wire \mgmt_buffers.mprj_dat_i_core_bar[22] ;
+ wire \mgmt_buffers.mprj_dat_i_core_bar[23] ;
+ wire \mgmt_buffers.mprj_dat_i_core_bar[24] ;
+ wire \mgmt_buffers.mprj_dat_i_core_bar[25] ;
+ wire \mgmt_buffers.mprj_dat_i_core_bar[26] ;
+ wire \mgmt_buffers.mprj_dat_i_core_bar[27] ;
+ wire \mgmt_buffers.mprj_dat_i_core_bar[28] ;
+ wire \mgmt_buffers.mprj_dat_i_core_bar[29] ;
+ wire \mgmt_buffers.mprj_dat_i_core_bar[2] ;
+ wire \mgmt_buffers.mprj_dat_i_core_bar[30] ;
+ wire \mgmt_buffers.mprj_dat_i_core_bar[31] ;
+ wire \mgmt_buffers.mprj_dat_i_core_bar[3] ;
+ wire \mgmt_buffers.mprj_dat_i_core_bar[4] ;
+ wire \mgmt_buffers.mprj_dat_i_core_bar[5] ;
+ wire \mgmt_buffers.mprj_dat_i_core_bar[6] ;
+ wire \mgmt_buffers.mprj_dat_i_core_bar[7] ;
+ wire \mgmt_buffers.mprj_dat_i_core_bar[8] ;
+ wire \mgmt_buffers.mprj_dat_i_core_bar[9] ;
+ wire \mgmt_buffers.mprj_dat_i_user[0] ;
+ wire \mgmt_buffers.mprj_dat_i_user[10] ;
+ wire \mgmt_buffers.mprj_dat_i_user[11] ;
+ wire \mgmt_buffers.mprj_dat_i_user[12] ;
+ wire \mgmt_buffers.mprj_dat_i_user[13] ;
+ wire \mgmt_buffers.mprj_dat_i_user[14] ;
+ wire \mgmt_buffers.mprj_dat_i_user[15] ;
+ wire \mgmt_buffers.mprj_dat_i_user[16] ;
+ wire \mgmt_buffers.mprj_dat_i_user[17] ;
+ wire \mgmt_buffers.mprj_dat_i_user[18] ;
+ wire \mgmt_buffers.mprj_dat_i_user[19] ;
+ wire \mgmt_buffers.mprj_dat_i_user[1] ;
+ wire \mgmt_buffers.mprj_dat_i_user[20] ;
+ wire \mgmt_buffers.mprj_dat_i_user[21] ;
+ wire \mgmt_buffers.mprj_dat_i_user[22] ;
+ wire \mgmt_buffers.mprj_dat_i_user[23] ;
+ wire \mgmt_buffers.mprj_dat_i_user[24] ;
+ wire \mgmt_buffers.mprj_dat_i_user[25] ;
+ wire \mgmt_buffers.mprj_dat_i_user[26] ;
+ wire \mgmt_buffers.mprj_dat_i_user[27] ;
+ wire \mgmt_buffers.mprj_dat_i_user[28] ;
+ wire \mgmt_buffers.mprj_dat_i_user[29] ;
+ wire \mgmt_buffers.mprj_dat_i_user[2] ;
+ wire \mgmt_buffers.mprj_dat_i_user[30] ;
+ wire \mgmt_buffers.mprj_dat_i_user[31] ;
+ wire \mgmt_buffers.mprj_dat_i_user[3] ;
+ wire \mgmt_buffers.mprj_dat_i_user[4] ;
+ wire \mgmt_buffers.mprj_dat_i_user[5] ;
+ wire \mgmt_buffers.mprj_dat_i_user[6] ;
+ wire \mgmt_buffers.mprj_dat_i_user[7] ;
+ wire \mgmt_buffers.mprj_dat_i_user[8] ;
+ wire \mgmt_buffers.mprj_dat_i_user[9] ;
+ wire \mgmt_buffers.mprj_dat_o_core[0] ;
+ wire \mgmt_buffers.mprj_dat_o_core[10] ;
+ wire \mgmt_buffers.mprj_dat_o_core[11] ;
+ wire \mgmt_buffers.mprj_dat_o_core[12] ;
+ wire \mgmt_buffers.mprj_dat_o_core[13] ;
+ wire \mgmt_buffers.mprj_dat_o_core[14] ;
+ wire \mgmt_buffers.mprj_dat_o_core[15] ;
+ wire \mgmt_buffers.mprj_dat_o_core[16] ;
+ wire \mgmt_buffers.mprj_dat_o_core[17] ;
+ wire \mgmt_buffers.mprj_dat_o_core[18] ;
+ wire \mgmt_buffers.mprj_dat_o_core[19] ;
+ wire \mgmt_buffers.mprj_dat_o_core[1] ;
+ wire \mgmt_buffers.mprj_dat_o_core[20] ;
+ wire \mgmt_buffers.mprj_dat_o_core[21] ;
+ wire \mgmt_buffers.mprj_dat_o_core[22] ;
+ wire \mgmt_buffers.mprj_dat_o_core[23] ;
+ wire \mgmt_buffers.mprj_dat_o_core[24] ;
+ wire \mgmt_buffers.mprj_dat_o_core[25] ;
+ wire \mgmt_buffers.mprj_dat_o_core[26] ;
+ wire \mgmt_buffers.mprj_dat_o_core[27] ;
+ wire \mgmt_buffers.mprj_dat_o_core[28] ;
+ wire \mgmt_buffers.mprj_dat_o_core[29] ;
+ wire \mgmt_buffers.mprj_dat_o_core[2] ;
+ wire \mgmt_buffers.mprj_dat_o_core[30] ;
+ wire \mgmt_buffers.mprj_dat_o_core[31] ;
+ wire \mgmt_buffers.mprj_dat_o_core[3] ;
+ wire \mgmt_buffers.mprj_dat_o_core[4] ;
+ wire \mgmt_buffers.mprj_dat_o_core[5] ;
+ wire \mgmt_buffers.mprj_dat_o_core[6] ;
+ wire \mgmt_buffers.mprj_dat_o_core[7] ;
+ wire \mgmt_buffers.mprj_dat_o_core[8] ;
+ wire \mgmt_buffers.mprj_dat_o_core[9] ;
+ wire \mgmt_buffers.mprj_sel_o_core[0] ;
+ wire \mgmt_buffers.mprj_sel_o_core[1] ;
+ wire \mgmt_buffers.mprj_sel_o_core[2] ;
+ wire \mgmt_buffers.mprj_sel_o_core[3] ;
+ wire \mgmt_buffers.mprj_stb_o_core ;
+ wire \mgmt_buffers.mprj_we_o_core ;
+ wire \mgmt_buffers.user_irq[0] ;
+ wire \mgmt_buffers.user_irq[1] ;
+ wire \mgmt_buffers.user_irq[2] ;
+ wire \mgmt_buffers.user_irq_bar[0] ;
+ wire \mgmt_buffers.user_irq_bar[1] ;
+ wire \mgmt_buffers.user_irq_bar[2] ;
+ wire \mgmt_buffers.user_irq_core[0] ;
+ wire \mgmt_buffers.user_irq_core[1] ;
+ wire \mgmt_buffers.user_irq_core[2] ;
+ wire \mgmt_io_nc[0] ;
+ wire \mgmt_io_nc[10] ;
+ wire \mgmt_io_nc[11] ;
+ wire \mgmt_io_nc[12] ;
+ wire \mgmt_io_nc[13] ;
+ wire \mgmt_io_nc[14] ;
+ wire \mgmt_io_nc[15] ;
+ wire \mgmt_io_nc[16] ;
+ wire \mgmt_io_nc[17] ;
+ wire \mgmt_io_nc[18] ;
+ wire \mgmt_io_nc[19] ;
+ wire \mgmt_io_nc[1] ;
+ wire \mgmt_io_nc[20] ;
+ wire \mgmt_io_nc[21] ;
+ wire \mgmt_io_nc[22] ;
+ wire \mgmt_io_nc[23] ;
+ wire \mgmt_io_nc[24] ;
+ wire \mgmt_io_nc[25] ;
+ wire \mgmt_io_nc[26] ;
+ wire \mgmt_io_nc[27] ;
+ wire \mgmt_io_nc[28] ;
+ wire \mgmt_io_nc[29] ;
+ wire \mgmt_io_nc[2] ;
+ wire \mgmt_io_nc[30] ;
+ wire \mgmt_io_nc[31] ;
+ wire \mgmt_io_nc[32] ;
+ wire \mgmt_io_nc[3] ;
+ wire \mgmt_io_nc[4] ;
+ wire \mgmt_io_nc[5] ;
+ wire \mgmt_io_nc[6] ;
+ wire \mgmt_io_nc[7] ;
+ wire \mgmt_io_nc[8] ;
+ wire \mgmt_io_nc[9] ;
+ wire \mgmt_io_out_hk[0] ;
+ wire \mgmt_io_out_hk[10] ;
+ wire \mgmt_io_out_hk[11] ;
+ wire \mgmt_io_out_hk[12] ;
+ wire \mgmt_io_out_hk[13] ;
+ wire \mgmt_io_out_hk[14] ;
+ wire \mgmt_io_out_hk[15] ;
+ wire \mgmt_io_out_hk[16] ;
+ wire \mgmt_io_out_hk[17] ;
+ wire \mgmt_io_out_hk[18] ;
+ wire \mgmt_io_out_hk[19] ;
+ wire \mgmt_io_out_hk[1] ;
+ wire \mgmt_io_out_hk[20] ;
+ wire \mgmt_io_out_hk[21] ;
+ wire \mgmt_io_out_hk[22] ;
+ wire \mgmt_io_out_hk[23] ;
+ wire \mgmt_io_out_hk[24] ;
+ wire \mgmt_io_out_hk[25] ;
+ wire \mgmt_io_out_hk[26] ;
+ wire \mgmt_io_out_hk[27] ;
+ wire \mgmt_io_out_hk[28] ;
+ wire \mgmt_io_out_hk[29] ;
+ wire \mgmt_io_out_hk[2] ;
+ wire \mgmt_io_out_hk[30] ;
+ wire \mgmt_io_out_hk[31] ;
+ wire \mgmt_io_out_hk[32] ;
+ wire \mgmt_io_out_hk[33] ;
+ wire \mgmt_io_out_hk[34] ;
+ wire \mgmt_io_out_hk[35] ;
+ wire \mgmt_io_out_hk[36] ;
+ wire \mgmt_io_out_hk[37] ;
+ wire \mgmt_io_out_hk[3] ;
+ wire \mgmt_io_out_hk[4] ;
+ wire \mgmt_io_out_hk[5] ;
+ wire \mgmt_io_out_hk[6] ;
+ wire \mgmt_io_out_hk[7] ;
+ wire \mgmt_io_out_hk[8] ;
+ wire \mgmt_io_out_hk[9] ;
+ wire \pll.dco ;
+ wire \pll.div[0] ;
+ wire \pll.div[1] ;
+ wire \pll.div[2] ;
+ wire \pll.div[3] ;
+ wire \pll.div[4] ;
+ wire \pll.enable ;
+ wire \pll.ext_trim[0] ;
+ wire \pll.ext_trim[10] ;
+ wire \pll.ext_trim[11] ;
+ wire \pll.ext_trim[12] ;
+ wire \pll.ext_trim[13] ;
+ wire \pll.ext_trim[14] ;
+ wire \pll.ext_trim[15] ;
+ wire \pll.ext_trim[16] ;
+ wire \pll.ext_trim[17] ;
+ wire \pll.ext_trim[18] ;
+ wire \pll.ext_trim[19] ;
+ wire \pll.ext_trim[1] ;
+ wire \pll.ext_trim[20] ;
+ wire \pll.ext_trim[21] ;
+ wire \pll.ext_trim[22] ;
+ wire \pll.ext_trim[23] ;
+ wire \pll.ext_trim[24] ;
+ wire \pll.ext_trim[25] ;
+ wire \pll.ext_trim[2] ;
+ wire \pll.ext_trim[3] ;
+ wire \pll.ext_trim[4] ;
+ wire \pll.ext_trim[5] ;
+ wire \pll.ext_trim[6] ;
+ wire \pll.ext_trim[7] ;
+ wire \pll.ext_trim[8] ;
+ wire \pll.ext_trim[9] ;
+ wire \pll.ireset ;
+ wire \pll.itrim[0] ;
+ wire \pll.itrim[10] ;
+ wire \pll.itrim[11] ;
+ wire \pll.itrim[12] ;
+ wire \pll.itrim[13] ;
+ wire \pll.itrim[14] ;
+ wire \pll.itrim[15] ;
+ wire \pll.itrim[16] ;
+ wire \pll.itrim[17] ;
+ wire \pll.itrim[18] ;
+ wire \pll.itrim[19] ;
+ wire \pll.itrim[1] ;
+ wire \pll.itrim[20] ;
+ wire \pll.itrim[21] ;
+ wire \pll.itrim[22] ;
+ wire \pll.itrim[23] ;
+ wire \pll.itrim[24] ;
+ wire \pll.itrim[25] ;
+ wire \pll.itrim[2] ;
+ wire \pll.itrim[3] ;
+ wire \pll.itrim[4] ;
+ wire \pll.itrim[5] ;
+ wire \pll.itrim[6] ;
+ wire \pll.itrim[7] ;
+ wire \pll.itrim[8] ;
+ wire \pll.itrim[9] ;
+ wire \pll.pll_control.count0[0] ;
+ wire \pll.pll_control.count0[1] ;
+ wire \pll.pll_control.count0[2] ;
+ wire \pll.pll_control.count0[3] ;
+ wire \pll.pll_control.count0[4] ;
+ wire \pll.pll_control.count1[0] ;
+ wire \pll.pll_control.count1[1] ;
+ wire \pll.pll_control.count1[2] ;
+ wire \pll.pll_control.count1[3] ;
+ wire \pll.pll_control.count1[4] ;
+ wire \pll.pll_control.oscbuf[0] ;
+ wire \pll.pll_control.oscbuf[1] ;
+ wire \pll.pll_control.oscbuf[2] ;
+ wire \pll.pll_control.prep[0] ;
+ wire \pll.pll_control.prep[1] ;
+ wire \pll.pll_control.prep[2] ;
+ wire \pll.pll_control.tint[0] ;
+ wire \pll.pll_control.tint[1] ;
+ wire \pll.pll_control.tint[2] ;
+ wire \pll.pll_control.tint[3] ;
+ wire \pll.pll_control.tint[4] ;
+ wire \pll.pll_control.tval[0] ;
+ wire \pll.pll_control.tval[1] ;
+ wire \pll.ringosc.c[0] ;
+ wire \pll.ringosc.c[1] ;
+ wire \pll.ringosc.dstage[0].id.d0 ;
+ wire \pll.ringosc.dstage[0].id.d1 ;
+ wire \pll.ringosc.dstage[0].id.d2 ;
+ wire \pll.ringosc.dstage[0].id.in ;
+ wire \pll.ringosc.dstage[0].id.out ;
+ wire \pll.ringosc.dstage[0].id.trim0b ;
+ wire \pll.ringosc.dstage[0].id.trim1b ;
+ wire \pll.ringosc.dstage[0].id.ts ;
+ wire \pll.ringosc.dstage[10].id.d0 ;
+ wire \pll.ringosc.dstage[10].id.d1 ;
+ wire \pll.ringosc.dstage[10].id.d2 ;
+ wire \pll.ringosc.dstage[10].id.in ;
+ wire \pll.ringosc.dstage[10].id.out ;
+ wire \pll.ringosc.dstage[10].id.trim0b ;
+ wire \pll.ringosc.dstage[10].id.trim1b ;
+ wire \pll.ringosc.dstage[10].id.ts ;
+ wire \pll.ringosc.dstage[11].id.d0 ;
+ wire \pll.ringosc.dstage[11].id.d1 ;
+ wire \pll.ringosc.dstage[11].id.d2 ;
+ wire \pll.ringosc.dstage[11].id.out ;
+ wire \pll.ringosc.dstage[11].id.trim0b ;
+ wire \pll.ringosc.dstage[11].id.trim1b ;
+ wire \pll.ringosc.dstage[11].id.ts ;
+ wire \pll.ringosc.dstage[1].id.d0 ;
+ wire \pll.ringosc.dstage[1].id.d1 ;
+ wire \pll.ringosc.dstage[1].id.d2 ;
+ wire \pll.ringosc.dstage[1].id.out ;
+ wire \pll.ringosc.dstage[1].id.trim0b ;
+ wire \pll.ringosc.dstage[1].id.trim1b ;
+ wire \pll.ringosc.dstage[1].id.ts ;
+ wire \pll.ringosc.dstage[2].id.d0 ;
+ wire \pll.ringosc.dstage[2].id.d1 ;
+ wire \pll.ringosc.dstage[2].id.d2 ;
+ wire \pll.ringosc.dstage[2].id.out ;
+ wire \pll.ringosc.dstage[2].id.trim0b ;
+ wire \pll.ringosc.dstage[2].id.trim1b ;
+ wire \pll.ringosc.dstage[2].id.ts ;
+ wire \pll.ringosc.dstage[3].id.d0 ;
+ wire \pll.ringosc.dstage[3].id.d1 ;
+ wire \pll.ringosc.dstage[3].id.d2 ;
+ wire \pll.ringosc.dstage[3].id.out ;
+ wire \pll.ringosc.dstage[3].id.trim0b ;
+ wire \pll.ringosc.dstage[3].id.trim1b ;
+ wire \pll.ringosc.dstage[3].id.ts ;
+ wire \pll.ringosc.dstage[4].id.d0 ;
+ wire \pll.ringosc.dstage[4].id.d1 ;
+ wire \pll.ringosc.dstage[4].id.d2 ;
+ wire \pll.ringosc.dstage[4].id.out ;
+ wire \pll.ringosc.dstage[4].id.trim0b ;
+ wire \pll.ringosc.dstage[4].id.trim1b ;
+ wire \pll.ringosc.dstage[4].id.ts ;
+ wire \pll.ringosc.dstage[5].id.d0 ;
+ wire \pll.ringosc.dstage[5].id.d1 ;
+ wire \pll.ringosc.dstage[5].id.d2 ;
+ wire \pll.ringosc.dstage[5].id.out ;
+ wire \pll.ringosc.dstage[5].id.trim0b ;
+ wire \pll.ringosc.dstage[5].id.trim1b ;
+ wire \pll.ringosc.dstage[5].id.ts ;
+ wire \pll.ringosc.dstage[6].id.d0 ;
+ wire \pll.ringosc.dstage[6].id.d1 ;
+ wire \pll.ringosc.dstage[6].id.d2 ;
+ wire \pll.ringosc.dstage[6].id.out ;
+ wire \pll.ringosc.dstage[6].id.trim0b ;
+ wire \pll.ringosc.dstage[6].id.trim1b ;
+ wire \pll.ringosc.dstage[6].id.ts ;
+ wire \pll.ringosc.dstage[7].id.d0 ;
+ wire \pll.ringosc.dstage[7].id.d1 ;
+ wire \pll.ringosc.dstage[7].id.d2 ;
+ wire \pll.ringosc.dstage[7].id.out ;
+ wire \pll.ringosc.dstage[7].id.trim0b ;
+ wire \pll.ringosc.dstage[7].id.trim1b ;
+ wire \pll.ringosc.dstage[7].id.ts ;
+ wire \pll.ringosc.dstage[8].id.d0 ;
+ wire \pll.ringosc.dstage[8].id.d1 ;
+ wire \pll.ringosc.dstage[8].id.d2 ;
+ wire \pll.ringosc.dstage[8].id.out ;
+ wire \pll.ringosc.dstage[8].id.trim0b ;
+ wire \pll.ringosc.dstage[8].id.trim1b ;
+ wire \pll.ringosc.dstage[8].id.ts ;
+ wire \pll.ringosc.dstage[9].id.d0 ;
+ wire \pll.ringosc.dstage[9].id.d1 ;
+ wire \pll.ringosc.dstage[9].id.d2 ;
+ wire \pll.ringosc.dstage[9].id.trim0b ;
+ wire \pll.ringosc.dstage[9].id.trim1b ;
+ wire \pll.ringosc.dstage[9].id.ts ;
+ wire \pll.ringosc.iss.ctrl0b ;
+ wire \pll.ringosc.iss.d0 ;
+ wire \pll.ringosc.iss.d1 ;
+ wire \pll.ringosc.iss.d2 ;
+ wire \pll.ringosc.iss.one ;
+ wire \pll.ringosc.iss.trim1b ;
+ wire por;
+ wire pwr_ctrl_nc;
+ wire \soc.core.VexRiscv.BranchPlugin_branchExceptionPort_payload_badAddr[10] ;
+ wire \soc.core.VexRiscv.BranchPlugin_branchExceptionPort_payload_badAddr[11] ;
+ wire \soc.core.VexRiscv.BranchPlugin_branchExceptionPort_payload_badAddr[12] ;
+ wire \soc.core.VexRiscv.BranchPlugin_branchExceptionPort_payload_badAddr[13] ;
+ wire \soc.core.VexRiscv.BranchPlugin_branchExceptionPort_payload_badAddr[14] ;
+ wire \soc.core.VexRiscv.BranchPlugin_branchExceptionPort_payload_badAddr[15] ;
+ wire \soc.core.VexRiscv.BranchPlugin_branchExceptionPort_payload_badAddr[16] ;
+ wire \soc.core.VexRiscv.BranchPlugin_branchExceptionPort_payload_badAddr[17] ;
+ wire \soc.core.VexRiscv.BranchPlugin_branchExceptionPort_payload_badAddr[18] ;
+ wire \soc.core.VexRiscv.BranchPlugin_branchExceptionPort_payload_badAddr[19] ;
+ wire \soc.core.VexRiscv.BranchPlugin_branchExceptionPort_payload_badAddr[1] ;
+ wire \soc.core.VexRiscv.BranchPlugin_branchExceptionPort_payload_badAddr[20] ;
+ wire \soc.core.VexRiscv.BranchPlugin_branchExceptionPort_payload_badAddr[21] ;
+ wire \soc.core.VexRiscv.BranchPlugin_branchExceptionPort_payload_badAddr[22] ;
+ wire \soc.core.VexRiscv.BranchPlugin_branchExceptionPort_payload_badAddr[23] ;
+ wire \soc.core.VexRiscv.BranchPlugin_branchExceptionPort_payload_badAddr[24] ;
+ wire \soc.core.VexRiscv.BranchPlugin_branchExceptionPort_payload_badAddr[25] ;
+ wire \soc.core.VexRiscv.BranchPlugin_branchExceptionPort_payload_badAddr[26] ;
+ wire \soc.core.VexRiscv.BranchPlugin_branchExceptionPort_payload_badAddr[27] ;
+ wire \soc.core.VexRiscv.BranchPlugin_branchExceptionPort_payload_badAddr[28] ;
+ wire \soc.core.VexRiscv.BranchPlugin_branchExceptionPort_payload_badAddr[29] ;
+ wire \soc.core.VexRiscv.BranchPlugin_branchExceptionPort_payload_badAddr[2] ;
+ wire \soc.core.VexRiscv.BranchPlugin_branchExceptionPort_payload_badAddr[30] ;
+ wire \soc.core.VexRiscv.BranchPlugin_branchExceptionPort_payload_badAddr[31] ;
+ wire \soc.core.VexRiscv.BranchPlugin_branchExceptionPort_payload_badAddr[3] ;
+ wire \soc.core.VexRiscv.BranchPlugin_branchExceptionPort_payload_badAddr[4] ;
+ wire \soc.core.VexRiscv.BranchPlugin_branchExceptionPort_payload_badAddr[5] ;
+ wire \soc.core.VexRiscv.BranchPlugin_branchExceptionPort_payload_badAddr[6] ;
+ wire \soc.core.VexRiscv.BranchPlugin_branchExceptionPort_payload_badAddr[7] ;
+ wire \soc.core.VexRiscv.BranchPlugin_branchExceptionPort_payload_badAddr[8] ;
+ wire \soc.core.VexRiscv.BranchPlugin_branchExceptionPort_payload_badAddr[9] ;
+ wire \soc.core.VexRiscv.CsrPlugin_exceptionPendings_0 ;
+ wire \soc.core.VexRiscv.CsrPlugin_exceptionPendings_1 ;
+ wire \soc.core.VexRiscv.CsrPlugin_exceptionPendings_2 ;
+ wire \soc.core.VexRiscv.CsrPlugin_exceptionPendings_3 ;
+ wire \soc.core.VexRiscv.CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[0] ;
+ wire \soc.core.VexRiscv.CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[10] ;
+ wire \soc.core.VexRiscv.CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[11] ;
+ wire \soc.core.VexRiscv.CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[12] ;
+ wire \soc.core.VexRiscv.CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[13] ;
+ wire \soc.core.VexRiscv.CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[14] ;
+ wire \soc.core.VexRiscv.CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[15] ;
+ wire \soc.core.VexRiscv.CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[16] ;
+ wire \soc.core.VexRiscv.CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[17] ;
+ wire \soc.core.VexRiscv.CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[18] ;
+ wire \soc.core.VexRiscv.CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[19] ;
+ wire \soc.core.VexRiscv.CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[1] ;
+ wire \soc.core.VexRiscv.CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[20] ;
+ wire \soc.core.VexRiscv.CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[21] ;
+ wire \soc.core.VexRiscv.CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[22] ;
+ wire \soc.core.VexRiscv.CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[23] ;
+ wire \soc.core.VexRiscv.CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[24] ;
+ wire \soc.core.VexRiscv.CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[25] ;
+ wire \soc.core.VexRiscv.CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[26] ;
+ wire \soc.core.VexRiscv.CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[27] ;
+ wire \soc.core.VexRiscv.CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[28] ;
+ wire \soc.core.VexRiscv.CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[29] ;
+ wire \soc.core.VexRiscv.CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[2] ;
+ wire \soc.core.VexRiscv.CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[30] ;
+ wire \soc.core.VexRiscv.CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[31] ;
+ wire \soc.core.VexRiscv.CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[3] ;
+ wire \soc.core.VexRiscv.CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[4] ;
+ wire \soc.core.VexRiscv.CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[5] ;
+ wire \soc.core.VexRiscv.CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[6] ;
+ wire \soc.core.VexRiscv.CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[7] ;
+ wire \soc.core.VexRiscv.CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[8] ;
+ wire \soc.core.VexRiscv.CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[9] ;
+ wire \soc.core.VexRiscv.CsrPlugin_exceptionPortCtrl_exceptionContext_code[0] ;
+ wire \soc.core.VexRiscv.CsrPlugin_exceptionPortCtrl_exceptionContext_code[1] ;
+ wire \soc.core.VexRiscv.CsrPlugin_exceptionPortCtrl_exceptionContext_code[2] ;
+ wire \soc.core.VexRiscv.CsrPlugin_hadException ;
+ wire \soc.core.VexRiscv.CsrPlugin_interrupt_code[3] ;
+ wire \soc.core.VexRiscv.CsrPlugin_interrupt_valid ;
+ wire \soc.core.VexRiscv.CsrPlugin_mcause_exceptionCode[0] ;
+ wire \soc.core.VexRiscv.CsrPlugin_mcause_exceptionCode[1] ;
+ wire \soc.core.VexRiscv.CsrPlugin_mcause_exceptionCode[2] ;
+ wire \soc.core.VexRiscv.CsrPlugin_mcause_exceptionCode[3] ;
+ wire \soc.core.VexRiscv.CsrPlugin_mcause_interrupt ;
+ wire \soc.core.VexRiscv.CsrPlugin_mepc[0] ;
+ wire \soc.core.VexRiscv.CsrPlugin_mepc[10] ;
+ wire \soc.core.VexRiscv.CsrPlugin_mepc[11] ;
+ wire \soc.core.VexRiscv.CsrPlugin_mepc[12] ;
+ wire \soc.core.VexRiscv.CsrPlugin_mepc[13] ;
+ wire \soc.core.VexRiscv.CsrPlugin_mepc[14] ;
+ wire \soc.core.VexRiscv.CsrPlugin_mepc[15] ;
+ wire \soc.core.VexRiscv.CsrPlugin_mepc[16] ;
+ wire \soc.core.VexRiscv.CsrPlugin_mepc[17] ;
+ wire \soc.core.VexRiscv.CsrPlugin_mepc[18] ;
+ wire \soc.core.VexRiscv.CsrPlugin_mepc[19] ;
+ wire \soc.core.VexRiscv.CsrPlugin_mepc[1] ;
+ wire \soc.core.VexRiscv.CsrPlugin_mepc[20] ;
+ wire \soc.core.VexRiscv.CsrPlugin_mepc[21] ;
+ wire \soc.core.VexRiscv.CsrPlugin_mepc[22] ;
+ wire \soc.core.VexRiscv.CsrPlugin_mepc[23] ;
+ wire \soc.core.VexRiscv.CsrPlugin_mepc[24] ;
+ wire \soc.core.VexRiscv.CsrPlugin_mepc[25] ;
+ wire \soc.core.VexRiscv.CsrPlugin_mepc[26] ;
+ wire \soc.core.VexRiscv.CsrPlugin_mepc[27] ;
+ wire \soc.core.VexRiscv.CsrPlugin_mepc[28] ;
+ wire \soc.core.VexRiscv.CsrPlugin_mepc[29] ;
+ wire \soc.core.VexRiscv.CsrPlugin_mepc[2] ;
+ wire \soc.core.VexRiscv.CsrPlugin_mepc[30] ;
+ wire \soc.core.VexRiscv.CsrPlugin_mepc[31] ;
+ wire \soc.core.VexRiscv.CsrPlugin_mepc[3] ;
+ wire \soc.core.VexRiscv.CsrPlugin_mepc[4] ;
+ wire \soc.core.VexRiscv.CsrPlugin_mepc[5] ;
+ wire \soc.core.VexRiscv.CsrPlugin_mepc[6] ;
+ wire \soc.core.VexRiscv.CsrPlugin_mepc[7] ;
+ wire \soc.core.VexRiscv.CsrPlugin_mepc[8] ;
+ wire \soc.core.VexRiscv.CsrPlugin_mepc[9] ;
+ wire \soc.core.VexRiscv.CsrPlugin_mie_MEIE ;
+ wire \soc.core.VexRiscv.CsrPlugin_mie_MSIE ;
+ wire \soc.core.VexRiscv.CsrPlugin_mie_MTIE ;
+ wire \soc.core.VexRiscv.CsrPlugin_mip_MEIP ;
+ wire \soc.core.VexRiscv.CsrPlugin_mip_MSIP ;
+ wire \soc.core.VexRiscv.CsrPlugin_mstatus_MIE ;
+ wire \soc.core.VexRiscv.CsrPlugin_mstatus_MPIE ;
+ wire \soc.core.VexRiscv.CsrPlugin_mstatus_MPP[0] ;
+ wire \soc.core.VexRiscv.CsrPlugin_mstatus_MPP[1] ;
+ wire \soc.core.VexRiscv.CsrPlugin_mtval[0] ;
+ wire \soc.core.VexRiscv.CsrPlugin_mtval[10] ;
+ wire \soc.core.VexRiscv.CsrPlugin_mtval[11] ;
+ wire \soc.core.VexRiscv.CsrPlugin_mtval[12] ;
+ wire \soc.core.VexRiscv.CsrPlugin_mtval[13] ;
+ wire \soc.core.VexRiscv.CsrPlugin_mtval[14] ;
+ wire \soc.core.VexRiscv.CsrPlugin_mtval[15] ;
+ wire \soc.core.VexRiscv.CsrPlugin_mtval[16] ;
+ wire \soc.core.VexRiscv.CsrPlugin_mtval[17] ;
+ wire \soc.core.VexRiscv.CsrPlugin_mtval[18] ;
+ wire \soc.core.VexRiscv.CsrPlugin_mtval[19] ;
+ wire \soc.core.VexRiscv.CsrPlugin_mtval[1] ;
+ wire \soc.core.VexRiscv.CsrPlugin_mtval[20] ;
+ wire \soc.core.VexRiscv.CsrPlugin_mtval[21] ;
+ wire \soc.core.VexRiscv.CsrPlugin_mtval[22] ;
+ wire \soc.core.VexRiscv.CsrPlugin_mtval[23] ;
+ wire \soc.core.VexRiscv.CsrPlugin_mtval[24] ;
+ wire \soc.core.VexRiscv.CsrPlugin_mtval[25] ;
+ wire \soc.core.VexRiscv.CsrPlugin_mtval[26] ;
+ wire \soc.core.VexRiscv.CsrPlugin_mtval[27] ;
+ wire \soc.core.VexRiscv.CsrPlugin_mtval[28] ;
+ wire \soc.core.VexRiscv.CsrPlugin_mtval[29] ;
+ wire \soc.core.VexRiscv.CsrPlugin_mtval[2] ;
+ wire \soc.core.VexRiscv.CsrPlugin_mtval[30] ;
+ wire \soc.core.VexRiscv.CsrPlugin_mtval[31] ;
+ wire \soc.core.VexRiscv.CsrPlugin_mtval[3] ;
+ wire \soc.core.VexRiscv.CsrPlugin_mtval[4] ;
+ wire \soc.core.VexRiscv.CsrPlugin_mtval[5] ;
+ wire \soc.core.VexRiscv.CsrPlugin_mtval[6] ;
+ wire \soc.core.VexRiscv.CsrPlugin_mtval[7] ;
+ wire \soc.core.VexRiscv.CsrPlugin_mtval[8] ;
+ wire \soc.core.VexRiscv.CsrPlugin_mtval[9] ;
+ wire \soc.core.VexRiscv.CsrPlugin_mtvec_base[0] ;
+ wire \soc.core.VexRiscv.CsrPlugin_mtvec_base[10] ;
+ wire \soc.core.VexRiscv.CsrPlugin_mtvec_base[11] ;
+ wire \soc.core.VexRiscv.CsrPlugin_mtvec_base[12] ;
+ wire \soc.core.VexRiscv.CsrPlugin_mtvec_base[13] ;
+ wire \soc.core.VexRiscv.CsrPlugin_mtvec_base[14] ;
+ wire \soc.core.VexRiscv.CsrPlugin_mtvec_base[15] ;
+ wire \soc.core.VexRiscv.CsrPlugin_mtvec_base[16] ;
+ wire \soc.core.VexRiscv.CsrPlugin_mtvec_base[17] ;
+ wire \soc.core.VexRiscv.CsrPlugin_mtvec_base[18] ;
+ wire \soc.core.VexRiscv.CsrPlugin_mtvec_base[19] ;
+ wire \soc.core.VexRiscv.CsrPlugin_mtvec_base[1] ;
+ wire \soc.core.VexRiscv.CsrPlugin_mtvec_base[20] ;
+ wire \soc.core.VexRiscv.CsrPlugin_mtvec_base[21] ;
+ wire \soc.core.VexRiscv.CsrPlugin_mtvec_base[22] ;
+ wire \soc.core.VexRiscv.CsrPlugin_mtvec_base[23] ;
+ wire \soc.core.VexRiscv.CsrPlugin_mtvec_base[24] ;
+ wire \soc.core.VexRiscv.CsrPlugin_mtvec_base[25] ;
+ wire \soc.core.VexRiscv.CsrPlugin_mtvec_base[26] ;
+ wire \soc.core.VexRiscv.CsrPlugin_mtvec_base[27] ;
+ wire \soc.core.VexRiscv.CsrPlugin_mtvec_base[28] ;
+ wire \soc.core.VexRiscv.CsrPlugin_mtvec_base[29] ;
+ wire \soc.core.VexRiscv.CsrPlugin_mtvec_base[2] ;
+ wire \soc.core.VexRiscv.CsrPlugin_mtvec_base[3] ;
+ wire \soc.core.VexRiscv.CsrPlugin_mtvec_base[4] ;
+ wire \soc.core.VexRiscv.CsrPlugin_mtvec_base[5] ;
+ wire \soc.core.VexRiscv.CsrPlugin_mtvec_base[6] ;
+ wire \soc.core.VexRiscv.CsrPlugin_mtvec_base[7] ;
+ wire \soc.core.VexRiscv.CsrPlugin_mtvec_base[8] ;
+ wire \soc.core.VexRiscv.CsrPlugin_mtvec_base[9] ;
+ wire \soc.core.VexRiscv.CsrPlugin_pipelineLiberator_pcValids_0 ;
+ wire \soc.core.VexRiscv.CsrPlugin_pipelineLiberator_pcValids_1 ;
+ wire \soc.core.VexRiscv.CsrPlugin_pipelineLiberator_pcValids_2 ;
+ wire \soc.core.VexRiscv.CsrPlugin_selfException_payload_badAddr[0] ;
+ wire \soc.core.VexRiscv.CsrPlugin_selfException_payload_badAddr[10] ;
+ wire \soc.core.VexRiscv.CsrPlugin_selfException_payload_badAddr[11] ;
+ wire \soc.core.VexRiscv.CsrPlugin_selfException_payload_badAddr[12] ;
+ wire \soc.core.VexRiscv.CsrPlugin_selfException_payload_badAddr[13] ;
+ wire \soc.core.VexRiscv.CsrPlugin_selfException_payload_badAddr[14] ;
+ wire \soc.core.VexRiscv.CsrPlugin_selfException_payload_badAddr[15] ;
+ wire \soc.core.VexRiscv.CsrPlugin_selfException_payload_badAddr[16] ;
+ wire \soc.core.VexRiscv.CsrPlugin_selfException_payload_badAddr[17] ;
+ wire \soc.core.VexRiscv.CsrPlugin_selfException_payload_badAddr[18] ;
+ wire \soc.core.VexRiscv.CsrPlugin_selfException_payload_badAddr[19] ;
+ wire \soc.core.VexRiscv.CsrPlugin_selfException_payload_badAddr[1] ;
+ wire \soc.core.VexRiscv.CsrPlugin_selfException_payload_badAddr[20] ;
+ wire \soc.core.VexRiscv.CsrPlugin_selfException_payload_badAddr[21] ;
+ wire \soc.core.VexRiscv.CsrPlugin_selfException_payload_badAddr[22] ;
+ wire \soc.core.VexRiscv.CsrPlugin_selfException_payload_badAddr[23] ;
+ wire \soc.core.VexRiscv.CsrPlugin_selfException_payload_badAddr[24] ;
+ wire \soc.core.VexRiscv.CsrPlugin_selfException_payload_badAddr[25] ;
+ wire \soc.core.VexRiscv.CsrPlugin_selfException_payload_badAddr[26] ;
+ wire \soc.core.VexRiscv.CsrPlugin_selfException_payload_badAddr[27] ;
+ wire \soc.core.VexRiscv.CsrPlugin_selfException_payload_badAddr[28] ;
+ wire \soc.core.VexRiscv.CsrPlugin_selfException_payload_badAddr[29] ;
+ wire \soc.core.VexRiscv.CsrPlugin_selfException_payload_badAddr[2] ;
+ wire \soc.core.VexRiscv.CsrPlugin_selfException_payload_badAddr[30] ;
+ wire \soc.core.VexRiscv.CsrPlugin_selfException_payload_badAddr[31] ;
+ wire \soc.core.VexRiscv.CsrPlugin_selfException_payload_badAddr[3] ;
+ wire \soc.core.VexRiscv.CsrPlugin_selfException_payload_badAddr[4] ;
+ wire \soc.core.VexRiscv.CsrPlugin_selfException_payload_badAddr[5] ;
+ wire \soc.core.VexRiscv.CsrPlugin_selfException_payload_badAddr[6] ;
+ wire \soc.core.VexRiscv.CsrPlugin_selfException_payload_badAddr[7] ;
+ wire \soc.core.VexRiscv.CsrPlugin_selfException_payload_badAddr[8] ;
+ wire \soc.core.VexRiscv.CsrPlugin_selfException_payload_badAddr[9] ;
+ wire \soc.core.VexRiscv.DBusSimplePlugin_memoryExceptionPort_payload_badAddr[0] ;
+ wire \soc.core.VexRiscv.DBusSimplePlugin_memoryExceptionPort_payload_badAddr[10] ;
+ wire \soc.core.VexRiscv.DBusSimplePlugin_memoryExceptionPort_payload_badAddr[11] ;
+ wire \soc.core.VexRiscv.DBusSimplePlugin_memoryExceptionPort_payload_badAddr[12] ;
+ wire \soc.core.VexRiscv.DBusSimplePlugin_memoryExceptionPort_payload_badAddr[13] ;
+ wire \soc.core.VexRiscv.DBusSimplePlugin_memoryExceptionPort_payload_badAddr[14] ;
+ wire \soc.core.VexRiscv.DBusSimplePlugin_memoryExceptionPort_payload_badAddr[15] ;
+ wire \soc.core.VexRiscv.DBusSimplePlugin_memoryExceptionPort_payload_badAddr[16] ;
+ wire \soc.core.VexRiscv.DBusSimplePlugin_memoryExceptionPort_payload_badAddr[17] ;
+ wire \soc.core.VexRiscv.DBusSimplePlugin_memoryExceptionPort_payload_badAddr[18] ;
+ wire \soc.core.VexRiscv.DBusSimplePlugin_memoryExceptionPort_payload_badAddr[19] ;
+ wire \soc.core.VexRiscv.DBusSimplePlugin_memoryExceptionPort_payload_badAddr[1] ;
+ wire \soc.core.VexRiscv.DBusSimplePlugin_memoryExceptionPort_payload_badAddr[20] ;
+ wire \soc.core.VexRiscv.DBusSimplePlugin_memoryExceptionPort_payload_badAddr[21] ;
+ wire \soc.core.VexRiscv.DBusSimplePlugin_memoryExceptionPort_payload_badAddr[22] ;
+ wire \soc.core.VexRiscv.DBusSimplePlugin_memoryExceptionPort_payload_badAddr[23] ;
+ wire \soc.core.VexRiscv.DBusSimplePlugin_memoryExceptionPort_payload_badAddr[24] ;
+ wire \soc.core.VexRiscv.DBusSimplePlugin_memoryExceptionPort_payload_badAddr[25] ;
+ wire \soc.core.VexRiscv.DBusSimplePlugin_memoryExceptionPort_payload_badAddr[26] ;
+ wire \soc.core.VexRiscv.DBusSimplePlugin_memoryExceptionPort_payload_badAddr[27] ;
+ wire \soc.core.VexRiscv.DBusSimplePlugin_memoryExceptionPort_payload_badAddr[28] ;
+ wire \soc.core.VexRiscv.DBusSimplePlugin_memoryExceptionPort_payload_badAddr[29] ;
+ wire \soc.core.VexRiscv.DBusSimplePlugin_memoryExceptionPort_payload_badAddr[2] ;
+ wire \soc.core.VexRiscv.DBusSimplePlugin_memoryExceptionPort_payload_badAddr[30] ;
+ wire \soc.core.VexRiscv.DBusSimplePlugin_memoryExceptionPort_payload_badAddr[31] ;
+ wire \soc.core.VexRiscv.DBusSimplePlugin_memoryExceptionPort_payload_badAddr[3] ;
+ wire \soc.core.VexRiscv.DBusSimplePlugin_memoryExceptionPort_payload_badAddr[4] ;
+ wire \soc.core.VexRiscv.DBusSimplePlugin_memoryExceptionPort_payload_badAddr[5] ;
+ wire \soc.core.VexRiscv.DBusSimplePlugin_memoryExceptionPort_payload_badAddr[6] ;
+ wire \soc.core.VexRiscv.DBusSimplePlugin_memoryExceptionPort_payload_badAddr[7] ;
+ wire \soc.core.VexRiscv.DBusSimplePlugin_memoryExceptionPort_payload_badAddr[8] ;
+ wire \soc.core.VexRiscv.DBusSimplePlugin_memoryExceptionPort_payload_badAddr[9] ;
+ wire \soc.core.VexRiscv.DebugPlugin_busReadDataReg[0] ;
+ wire \soc.core.VexRiscv.DebugPlugin_busReadDataReg[10] ;
+ wire \soc.core.VexRiscv.DebugPlugin_busReadDataReg[11] ;
+ wire \soc.core.VexRiscv.DebugPlugin_busReadDataReg[12] ;
+ wire \soc.core.VexRiscv.DebugPlugin_busReadDataReg[13] ;
+ wire \soc.core.VexRiscv.DebugPlugin_busReadDataReg[14] ;
+ wire \soc.core.VexRiscv.DebugPlugin_busReadDataReg[15] ;
+ wire \soc.core.VexRiscv.DebugPlugin_busReadDataReg[16] ;
+ wire \soc.core.VexRiscv.DebugPlugin_busReadDataReg[17] ;
+ wire \soc.core.VexRiscv.DebugPlugin_busReadDataReg[18] ;
+ wire \soc.core.VexRiscv.DebugPlugin_busReadDataReg[19] ;
+ wire \soc.core.VexRiscv.DebugPlugin_busReadDataReg[1] ;
+ wire \soc.core.VexRiscv.DebugPlugin_busReadDataReg[20] ;
+ wire \soc.core.VexRiscv.DebugPlugin_busReadDataReg[21] ;
+ wire \soc.core.VexRiscv.DebugPlugin_busReadDataReg[22] ;
+ wire \soc.core.VexRiscv.DebugPlugin_busReadDataReg[23] ;
+ wire \soc.core.VexRiscv.DebugPlugin_busReadDataReg[24] ;
+ wire \soc.core.VexRiscv.DebugPlugin_busReadDataReg[25] ;
+ wire \soc.core.VexRiscv.DebugPlugin_busReadDataReg[26] ;
+ wire \soc.core.VexRiscv.DebugPlugin_busReadDataReg[27] ;
+ wire \soc.core.VexRiscv.DebugPlugin_busReadDataReg[28] ;
+ wire \soc.core.VexRiscv.DebugPlugin_busReadDataReg[29] ;
+ wire \soc.core.VexRiscv.DebugPlugin_busReadDataReg[2] ;
+ wire \soc.core.VexRiscv.DebugPlugin_busReadDataReg[30] ;
+ wire \soc.core.VexRiscv.DebugPlugin_busReadDataReg[31] ;
+ wire \soc.core.VexRiscv.DebugPlugin_busReadDataReg[3] ;
+ wire \soc.core.VexRiscv.DebugPlugin_busReadDataReg[4] ;
+ wire \soc.core.VexRiscv.DebugPlugin_busReadDataReg[5] ;
+ wire \soc.core.VexRiscv.DebugPlugin_busReadDataReg[6] ;
+ wire \soc.core.VexRiscv.DebugPlugin_busReadDataReg[7] ;
+ wire \soc.core.VexRiscv.DebugPlugin_busReadDataReg[8] ;
+ wire \soc.core.VexRiscv.DebugPlugin_busReadDataReg[9] ;
+ wire \soc.core.VexRiscv.DebugPlugin_debugUsed ;
+ wire \soc.core.VexRiscv.DebugPlugin_disableEbreak ;
+ wire \soc.core.VexRiscv.DebugPlugin_godmode ;
+ wire \soc.core.VexRiscv.DebugPlugin_haltIt ;
+ wire \soc.core.VexRiscv.DebugPlugin_haltedByBreak ;
+ wire \soc.core.VexRiscv.DebugPlugin_isPipBusy ;
+ wire \soc.core.VexRiscv.DebugPlugin_resetIt ;
+ wire \soc.core.VexRiscv.DebugPlugin_resetIt_regNext ;
+ wire \soc.core.VexRiscv.DebugPlugin_stepIt ;
+ wire \soc.core.VexRiscv.HazardSimplePlugin_writeBackBuffer_payload_address[0] ;
+ wire \soc.core.VexRiscv.HazardSimplePlugin_writeBackBuffer_payload_address[1] ;
+ wire \soc.core.VexRiscv.HazardSimplePlugin_writeBackBuffer_payload_address[2] ;
+ wire \soc.core.VexRiscv.HazardSimplePlugin_writeBackBuffer_payload_address[3] ;
+ wire \soc.core.VexRiscv.HazardSimplePlugin_writeBackBuffer_payload_address[4] ;
+ wire \soc.core.VexRiscv.HazardSimplePlugin_writeBackBuffer_valid ;
+ wire \soc.core.VexRiscv.HazardSimplePlugin_writeBackWrites_payload_address[0] ;
+ wire \soc.core.VexRiscv.HazardSimplePlugin_writeBackWrites_payload_address[1] ;
+ wire \soc.core.VexRiscv.HazardSimplePlugin_writeBackWrites_payload_address[2] ;
+ wire \soc.core.VexRiscv.HazardSimplePlugin_writeBackWrites_payload_address[3] ;
+ wire \soc.core.VexRiscv.HazardSimplePlugin_writeBackWrites_payload_address[4] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache._zz_1 ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache._zz_banks_0_port1[0] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache._zz_banks_0_port1[10] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache._zz_banks_0_port1[11] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache._zz_banks_0_port1[12] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache._zz_banks_0_port1[13] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache._zz_banks_0_port1[14] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache._zz_banks_0_port1[15] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache._zz_banks_0_port1[16] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache._zz_banks_0_port1[17] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache._zz_banks_0_port1[18] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache._zz_banks_0_port1[19] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache._zz_banks_0_port1[1] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache._zz_banks_0_port1[20] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache._zz_banks_0_port1[21] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache._zz_banks_0_port1[22] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache._zz_banks_0_port1[23] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache._zz_banks_0_port1[24] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache._zz_banks_0_port1[25] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache._zz_banks_0_port1[26] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache._zz_banks_0_port1[27] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache._zz_banks_0_port1[28] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache._zz_banks_0_port1[29] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache._zz_banks_0_port1[2] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache._zz_banks_0_port1[30] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache._zz_banks_0_port1[31] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache._zz_banks_0_port1[3] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache._zz_banks_0_port1[4] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache._zz_banks_0_port1[5] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache._zz_banks_0_port1[6] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache._zz_banks_0_port1[7] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache._zz_banks_0_port1[8] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache._zz_banks_0_port1[9] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[0] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[10] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[11] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[12] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[13] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[14] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[15] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[16] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[17] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[18] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[19] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[20] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[21] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[22] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[23] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[24] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[25] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[26] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[27] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[2] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[3] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[4] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[5] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[6] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[7] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[8] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[9] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache._zz_when_Fetcher_l398[0] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache._zz_when_Fetcher_l398[1] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache._zz_when_Fetcher_l398[2] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache._zz_when_InstructionCache_l342 ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[0][0] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[0][10] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[0][11] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[0][12] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[0][13] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[0][14] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[0][15] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[0][16] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[0][17] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[0][18] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[0][19] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[0][1] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[0][20] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[0][21] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[0][22] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[0][23] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[0][24] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[0][25] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[0][26] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[0][27] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[0][28] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[0][29] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[0][2] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[0][30] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[0][31] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[0][3] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[0][4] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[0][5] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[0][6] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[0][7] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[0][8] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[0][9] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[10][0] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[10][10] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[10][11] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[10][12] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[10][13] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[10][14] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[10][15] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[10][16] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[10][17] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[10][18] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[10][19] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[10][1] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[10][20] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[10][21] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[10][22] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[10][23] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[10][24] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[10][25] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[10][26] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[10][27] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[10][28] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[10][29] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[10][2] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[10][30] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[10][31] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[10][3] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[10][4] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[10][5] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[10][6] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[10][7] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[10][8] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[10][9] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[11][0] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[11][10] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[11][11] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[11][12] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[11][13] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[11][14] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[11][15] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[11][16] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[11][17] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[11][18] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[11][19] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[11][1] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[11][20] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[11][21] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[11][22] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[11][23] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[11][24] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[11][25] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[11][26] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[11][27] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[11][28] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[11][29] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[11][2] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[11][30] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[11][31] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[11][3] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[11][4] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[11][5] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[11][6] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[11][7] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[11][8] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[11][9] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[12][0] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[12][10] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[12][11] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[12][12] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[12][13] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[12][14] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[12][15] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[12][16] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[12][17] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[12][18] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[12][19] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[12][1] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[12][20] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[12][21] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[12][22] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[12][23] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[12][24] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[12][25] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[12][26] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[12][27] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[12][28] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[12][29] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[12][2] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[12][30] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[12][31] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[12][3] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[12][4] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[12][5] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[12][6] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[12][7] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[12][8] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[12][9] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[13][0] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[13][10] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[13][11] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[13][12] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[13][13] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[13][14] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[13][15] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[13][16] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[13][17] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[13][18] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[13][19] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[13][1] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[13][20] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[13][21] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[13][22] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[13][23] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[13][24] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[13][25] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[13][26] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[13][27] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[13][28] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[13][29] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[13][2] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[13][30] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[13][31] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[13][3] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[13][4] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[13][5] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[13][6] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[13][7] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[13][8] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[13][9] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[14][0] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[14][10] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[14][11] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[14][12] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[14][13] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[14][14] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[14][15] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[14][16] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[14][17] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[14][18] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[14][19] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[14][1] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[14][20] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[14][21] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[14][22] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[14][23] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[14][24] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[14][25] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[14][26] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[14][27] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[14][28] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[14][29] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[14][2] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[14][30] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[14][31] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[14][3] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[14][4] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[14][5] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[14][6] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[14][7] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[14][8] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[14][9] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[15][0] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[15][10] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[15][11] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[15][12] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[15][13] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[15][14] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[15][15] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[15][16] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[15][17] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[15][18] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[15][19] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[15][1] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[15][20] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[15][21] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[15][22] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[15][23] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[15][24] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[15][25] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[15][26] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[15][27] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[15][28] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[15][29] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[15][2] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[15][30] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[15][31] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[15][3] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[15][4] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[15][5] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[15][6] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[15][7] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[15][8] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[15][9] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[1][0] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[1][10] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[1][11] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[1][12] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[1][13] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[1][14] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[1][15] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[1][16] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[1][17] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[1][18] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[1][19] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[1][1] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[1][20] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[1][21] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[1][22] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[1][23] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[1][24] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[1][25] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[1][26] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[1][27] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[1][28] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[1][29] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[1][2] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[1][30] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[1][31] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[1][3] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[1][4] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[1][5] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[1][6] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[1][7] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[1][8] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[1][9] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[2][0] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[2][10] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[2][11] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[2][12] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[2][13] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[2][14] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[2][15] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[2][16] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[2][17] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[2][18] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[2][19] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[2][1] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[2][20] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[2][21] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[2][22] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[2][23] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[2][24] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[2][25] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[2][26] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[2][27] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[2][28] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[2][29] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[2][2] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[2][30] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[2][31] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[2][3] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[2][4] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[2][5] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[2][6] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[2][7] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[2][8] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[2][9] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[3][0] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[3][10] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[3][11] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[3][12] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[3][13] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[3][14] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[3][15] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[3][16] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[3][17] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[3][18] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[3][19] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[3][1] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[3][20] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[3][21] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[3][22] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[3][23] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[3][24] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[3][25] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[3][26] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[3][27] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[3][28] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[3][29] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[3][2] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[3][30] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[3][31] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[3][3] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[3][4] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[3][5] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[3][6] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[3][7] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[3][8] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[3][9] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[4][0] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[4][10] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[4][11] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[4][12] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[4][13] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[4][14] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[4][15] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[4][16] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[4][17] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[4][18] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[4][19] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[4][1] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[4][20] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[4][21] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[4][22] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[4][23] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[4][24] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[4][25] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[4][26] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[4][27] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[4][28] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[4][29] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[4][2] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[4][30] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[4][31] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[4][3] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[4][4] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[4][5] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[4][6] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[4][7] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[4][8] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[4][9] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[5][0] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[5][10] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[5][11] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[5][12] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[5][13] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[5][14] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[5][15] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[5][16] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[5][17] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[5][18] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[5][19] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[5][1] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[5][20] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[5][21] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[5][22] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[5][23] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[5][24] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[5][25] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[5][26] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[5][27] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[5][28] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[5][29] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[5][2] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[5][30] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[5][31] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[5][3] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[5][4] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[5][5] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[5][6] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[5][7] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[5][8] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[5][9] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[6][0] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[6][10] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[6][11] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[6][12] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[6][13] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[6][14] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[6][15] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[6][16] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[6][17] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[6][18] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[6][19] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[6][1] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[6][20] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[6][21] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[6][22] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[6][23] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[6][24] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[6][25] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[6][26] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[6][27] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[6][28] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[6][29] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[6][2] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[6][30] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[6][31] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[6][3] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[6][4] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[6][5] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[6][6] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[6][7] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[6][8] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[6][9] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[7][0] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[7][10] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[7][11] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[7][12] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[7][13] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[7][14] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[7][15] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[7][16] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[7][17] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[7][18] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[7][19] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[7][1] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[7][20] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[7][21] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[7][22] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[7][23] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[7][24] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[7][25] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[7][26] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[7][27] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[7][28] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[7][29] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[7][2] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[7][30] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[7][31] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[7][3] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[7][4] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[7][5] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[7][6] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[7][7] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[7][8] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[7][9] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[8][0] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[8][10] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[8][11] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[8][12] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[8][13] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[8][14] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[8][15] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[8][16] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[8][17] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[8][18] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[8][19] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[8][1] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[8][20] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[8][21] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[8][22] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[8][23] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[8][24] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[8][25] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[8][26] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[8][27] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[8][28] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[8][29] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[8][2] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[8][30] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[8][31] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[8][3] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[8][4] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[8][5] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[8][6] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[8][7] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[8][8] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[8][9] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[9][0] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[9][10] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[9][11] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[9][12] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[9][13] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[9][14] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[9][15] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[9][16] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[9][17] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[9][18] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[9][19] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[9][1] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[9][20] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[9][21] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[9][22] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[9][23] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[9][24] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[9][25] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[9][26] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[9][27] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[9][28] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[9][29] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[9][2] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[9][30] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[9][31] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[9][3] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[9][4] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[9][5] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[9][6] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[9][7] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[9][8] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.banks_0[9][9] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.decodeStage_hit_valid ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[10] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[11] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[12] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[13] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[14] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[15] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[16] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[17] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[18] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[19] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[20] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[21] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[22] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[23] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[24] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[25] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[26] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[27] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[28] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[29] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[2] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[30] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[31] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[3] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[4] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[5] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[6] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[7] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[8] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[9] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.io_cpu_decode_data[0] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.io_cpu_decode_data[10] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.io_cpu_decode_data[11] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.io_cpu_decode_data[12] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.io_cpu_decode_data[13] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.io_cpu_decode_data[14] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.io_cpu_decode_data[15] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.io_cpu_decode_data[16] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.io_cpu_decode_data[17] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.io_cpu_decode_data[18] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.io_cpu_decode_data[19] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.io_cpu_decode_data[1] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.io_cpu_decode_data[20] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.io_cpu_decode_data[21] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.io_cpu_decode_data[22] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.io_cpu_decode_data[23] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.io_cpu_decode_data[24] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.io_cpu_decode_data[25] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.io_cpu_decode_data[26] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.io_cpu_decode_data[27] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.io_cpu_decode_data[28] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.io_cpu_decode_data[29] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.io_cpu_decode_data[2] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.io_cpu_decode_data[30] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.io_cpu_decode_data[31] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.io_cpu_decode_data[3] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.io_cpu_decode_data[4] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.io_cpu_decode_data[5] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.io_cpu_decode_data[6] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.io_cpu_decode_data[7] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.io_cpu_decode_data[8] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.io_cpu_decode_data[9] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.io_cpu_decode_isValid ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.io_cpu_fetch_isValid ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_isIoAccess ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[10] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[11] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[12] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[13] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[14] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[15] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[16] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[17] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[18] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[19] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[20] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[21] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[22] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[23] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[24] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[25] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[26] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[27] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[28] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[29] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[2] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[30] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[3] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[4] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[5] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[6] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[7] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[8] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[9] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.io_mem_rsp_payload_data[0] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.io_mem_rsp_payload_data[10] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.io_mem_rsp_payload_data[11] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.io_mem_rsp_payload_data[12] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.io_mem_rsp_payload_data[13] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.io_mem_rsp_payload_data[14] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.io_mem_rsp_payload_data[15] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.io_mem_rsp_payload_data[16] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.io_mem_rsp_payload_data[17] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.io_mem_rsp_payload_data[18] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.io_mem_rsp_payload_data[19] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.io_mem_rsp_payload_data[1] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.io_mem_rsp_payload_data[20] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.io_mem_rsp_payload_data[21] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.io_mem_rsp_payload_data[22] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.io_mem_rsp_payload_data[23] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.io_mem_rsp_payload_data[24] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.io_mem_rsp_payload_data[25] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.io_mem_rsp_payload_data[26] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.io_mem_rsp_payload_data[27] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.io_mem_rsp_payload_data[28] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.io_mem_rsp_payload_data[29] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.io_mem_rsp_payload_data[2] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.io_mem_rsp_payload_data[30] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.io_mem_rsp_payload_data[31] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.io_mem_rsp_payload_data[3] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.io_mem_rsp_payload_data[4] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.io_mem_rsp_payload_data[5] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.io_mem_rsp_payload_data[6] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.io_mem_rsp_payload_data[7] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.io_mem_rsp_payload_data[8] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.io_mem_rsp_payload_data[9] ;
+ wire \clknet_leaf_2_clock_ctrl.core_clk ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.lineLoader_address[10] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.lineLoader_address[11] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.lineLoader_address[12] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.lineLoader_address[13] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.lineLoader_address[14] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.lineLoader_address[15] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.lineLoader_address[16] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.lineLoader_address[17] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.lineLoader_address[18] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.lineLoader_address[19] ;
+ wire net2307;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.lineLoader_address[20] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.lineLoader_address[21] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.lineLoader_address[22] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.lineLoader_address[23] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.lineLoader_address[24] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.lineLoader_address[25] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.lineLoader_address[26] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.lineLoader_address[27] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.lineLoader_address[28] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.lineLoader_address[29] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.lineLoader_address[2] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.lineLoader_address[30] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.lineLoader_address[31] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.lineLoader_address[3] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.lineLoader_address[4] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.lineLoader_address[5] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.lineLoader_address[6] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.lineLoader_address[7] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.lineLoader_address[8] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.lineLoader_address[9] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.lineLoader_cmdSent ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.lineLoader_flushCounter[0] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.lineLoader_flushCounter[1] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.lineLoader_flushPending ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.lineLoader_valid ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.lineLoader_wordIndex[0] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.lineLoader_wordIndex[1] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.lineLoader_wordIndex[2] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.reset ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.ways_0_tags[0][0] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.ways_0_tags[0][10] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.ways_0_tags[0][11] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.ways_0_tags[0][12] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.ways_0_tags[0][13] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.ways_0_tags[0][14] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.ways_0_tags[0][15] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.ways_0_tags[0][16] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.ways_0_tags[0][17] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.ways_0_tags[0][18] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.ways_0_tags[0][19] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.ways_0_tags[0][20] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.ways_0_tags[0][21] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.ways_0_tags[0][22] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.ways_0_tags[0][23] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.ways_0_tags[0][24] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.ways_0_tags[0][25] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.ways_0_tags[0][26] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.ways_0_tags[0][27] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.ways_0_tags[0][2] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.ways_0_tags[0][3] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.ways_0_tags[0][4] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.ways_0_tags[0][5] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.ways_0_tags[0][6] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.ways_0_tags[0][7] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.ways_0_tags[0][8] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.ways_0_tags[0][9] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.ways_0_tags[1][0] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.ways_0_tags[1][10] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.ways_0_tags[1][11] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.ways_0_tags[1][12] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.ways_0_tags[1][13] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.ways_0_tags[1][14] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.ways_0_tags[1][15] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.ways_0_tags[1][16] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.ways_0_tags[1][17] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.ways_0_tags[1][18] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.ways_0_tags[1][19] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.ways_0_tags[1][20] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.ways_0_tags[1][21] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.ways_0_tags[1][22] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.ways_0_tags[1][23] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.ways_0_tags[1][24] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.ways_0_tags[1][25] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.ways_0_tags[1][26] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.ways_0_tags[1][27] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.ways_0_tags[1][2] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.ways_0_tags[1][3] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.ways_0_tags[1][4] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.ways_0_tags[1][5] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.ways_0_tags[1][6] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.ways_0_tags[1][7] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.ways_0_tags[1][8] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_cache.ways_0_tags[1][9] ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_fetchPc_booted ;
+ wire \soc.core.VexRiscv.IBusCachedPlugin_fetchPc_inc ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[0][0] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[0][10] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[0][11] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[0][12] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[0][13] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[0][14] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[0][15] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[0][16] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[0][17] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[0][18] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[0][19] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[0][1] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[0][20] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[0][21] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[0][22] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[0][23] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[0][24] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[0][25] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[0][26] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[0][27] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[0][28] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[0][29] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[0][2] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[0][30] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[0][31] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[0][3] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[0][4] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[0][5] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[0][6] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[0][7] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[0][8] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[0][9] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[10][0] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[10][10] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[10][11] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[10][12] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[10][13] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[10][14] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[10][15] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[10][16] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[10][17] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[10][18] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[10][19] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[10][1] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[10][20] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[10][21] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[10][22] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[10][23] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[10][24] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[10][25] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[10][26] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[10][27] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[10][28] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[10][29] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[10][2] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[10][30] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[10][31] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[10][3] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[10][4] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[10][5] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[10][6] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[10][7] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[10][8] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[10][9] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[11][0] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[11][10] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[11][11] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[11][12] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[11][13] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[11][14] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[11][15] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[11][16] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[11][17] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[11][18] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[11][19] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[11][1] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[11][20] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[11][21] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[11][22] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[11][23] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[11][24] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[11][25] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[11][26] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[11][27] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[11][28] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[11][29] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[11][2] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[11][30] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[11][31] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[11][3] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[11][4] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[11][5] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[11][6] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[11][7] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[11][8] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[11][9] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[12][0] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[12][10] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[12][11] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[12][12] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[12][13] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[12][14] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[12][15] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[12][16] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[12][17] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[12][18] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[12][19] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[12][1] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[12][20] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[12][21] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[12][22] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[12][23] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[12][24] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[12][25] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[12][26] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[12][27] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[12][28] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[12][29] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[12][2] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[12][30] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[12][31] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[12][3] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[12][4] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[12][5] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[12][6] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[12][7] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[12][8] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[12][9] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[13][0] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[13][10] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[13][11] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[13][12] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[13][13] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[13][14] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[13][15] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[13][16] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[13][17] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[13][18] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[13][19] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[13][1] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[13][20] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[13][21] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[13][22] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[13][23] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[13][24] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[13][25] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[13][26] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[13][27] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[13][28] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[13][29] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[13][2] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[13][30] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[13][31] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[13][3] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[13][4] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[13][5] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[13][6] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[13][7] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[13][8] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[13][9] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[14][0] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[14][10] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[14][11] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[14][12] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[14][13] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[14][14] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[14][15] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[14][16] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[14][17] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[14][18] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[14][19] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[14][1] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[14][20] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[14][21] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[14][22] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[14][23] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[14][24] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[14][25] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[14][26] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[14][27] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[14][28] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[14][29] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[14][2] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[14][30] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[14][31] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[14][3] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[14][4] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[14][5] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[14][6] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[14][7] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[14][8] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[14][9] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[15][0] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[15][10] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[15][11] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[15][12] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[15][13] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[15][14] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[15][15] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[15][16] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[15][17] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[15][18] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[15][19] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[15][1] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[15][20] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[15][21] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[15][22] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[15][23] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[15][24] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[15][25] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[15][26] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[15][27] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[15][28] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[15][29] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[15][2] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[15][30] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[15][31] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[15][3] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[15][4] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[15][5] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[15][6] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[15][7] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[15][8] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[15][9] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[16][0] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[16][10] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[16][11] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[16][12] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[16][13] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[16][14] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[16][15] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[16][16] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[16][17] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[16][18] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[16][19] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[16][1] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[16][20] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[16][21] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[16][22] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[16][23] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[16][24] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[16][25] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[16][26] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[16][27] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[16][28] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[16][29] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[16][2] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[16][30] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[16][31] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[16][3] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[16][4] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[16][5] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[16][6] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[16][7] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[16][8] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[16][9] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[17][0] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[17][10] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[17][11] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[17][12] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[17][13] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[17][14] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[17][15] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[17][16] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[17][17] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[17][18] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[17][19] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[17][1] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[17][20] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[17][21] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[17][22] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[17][23] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[17][24] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[17][25] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[17][26] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[17][27] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[17][28] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[17][29] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[17][2] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[17][30] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[17][31] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[17][3] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[17][4] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[17][5] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[17][6] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[17][7] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[17][8] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[17][9] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[18][0] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[18][10] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[18][11] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[18][12] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[18][13] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[18][14] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[18][15] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[18][16] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[18][17] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[18][18] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[18][19] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[18][1] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[18][20] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[18][21] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[18][22] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[18][23] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[18][24] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[18][25] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[18][26] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[18][27] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[18][28] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[18][29] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[18][2] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[18][30] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[18][31] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[18][3] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[18][4] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[18][5] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[18][6] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[18][7] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[18][8] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[18][9] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[19][0] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[19][10] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[19][11] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[19][12] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[19][13] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[19][14] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[19][15] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[19][16] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[19][17] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[19][18] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[19][19] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[19][1] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[19][20] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[19][21] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[19][22] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[19][23] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[19][24] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[19][25] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[19][26] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[19][27] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[19][28] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[19][29] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[19][2] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[19][30] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[19][31] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[19][3] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[19][4] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[19][5] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[19][6] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[19][7] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[19][8] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[19][9] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[1][0] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[1][10] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[1][11] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[1][12] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[1][13] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[1][14] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[1][15] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[1][16] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[1][17] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[1][18] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[1][19] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[1][1] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[1][20] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[1][21] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[1][22] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[1][23] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[1][24] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[1][25] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[1][26] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[1][27] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[1][28] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[1][29] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[1][2] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[1][30] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[1][31] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[1][3] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[1][4] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[1][5] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[1][6] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[1][7] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[1][8] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[1][9] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[20][0] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[20][10] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[20][11] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[20][12] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[20][13] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[20][14] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[20][15] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[20][16] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[20][17] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[20][18] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[20][19] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[20][1] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[20][20] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[20][21] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[20][22] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[20][23] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[20][24] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[20][25] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[20][26] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[20][27] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[20][28] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[20][29] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[20][2] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[20][30] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[20][31] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[20][3] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[20][4] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[20][5] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[20][6] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[20][7] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[20][8] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[20][9] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[21][0] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[21][10] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[21][11] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[21][12] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[21][13] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[21][14] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[21][15] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[21][16] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[21][17] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[21][18] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[21][19] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[21][1] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[21][20] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[21][21] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[21][22] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[21][23] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[21][24] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[21][25] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[21][26] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[21][27] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[21][28] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[21][29] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[21][2] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[21][30] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[21][31] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[21][3] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[21][4] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[21][5] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[21][6] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[21][7] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[21][8] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[21][9] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[22][0] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[22][10] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[22][11] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[22][12] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[22][13] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[22][14] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[22][15] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[22][16] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[22][17] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[22][18] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[22][19] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[22][1] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[22][20] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[22][21] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[22][22] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[22][23] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[22][24] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[22][25] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[22][26] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[22][27] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[22][28] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[22][29] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[22][2] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[22][30] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[22][31] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[22][3] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[22][4] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[22][5] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[22][6] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[22][7] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[22][8] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[22][9] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[23][0] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[23][10] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[23][11] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[23][12] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[23][13] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[23][14] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[23][15] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[23][16] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[23][17] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[23][18] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[23][19] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[23][1] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[23][20] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[23][21] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[23][22] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[23][23] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[23][24] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[23][25] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[23][26] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[23][27] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[23][28] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[23][29] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[23][2] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[23][30] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[23][31] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[23][3] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[23][4] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[23][5] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[23][6] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[23][7] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[23][8] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[23][9] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[24][0] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[24][10] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[24][11] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[24][12] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[24][13] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[24][14] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[24][15] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[24][16] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[24][17] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[24][18] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[24][19] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[24][1] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[24][20] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[24][21] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[24][22] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[24][23] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[24][24] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[24][25] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[24][26] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[24][27] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[24][28] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[24][29] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[24][2] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[24][30] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[24][31] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[24][3] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[24][4] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[24][5] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[24][6] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[24][7] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[24][8] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[24][9] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[25][0] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[25][10] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[25][11] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[25][12] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[25][13] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[25][14] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[25][15] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[25][16] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[25][17] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[25][18] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[25][19] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[25][1] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[25][20] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[25][21] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[25][22] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[25][23] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[25][24] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[25][25] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[25][26] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[25][27] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[25][28] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[25][29] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[25][2] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[25][30] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[25][31] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[25][3] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[25][4] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[25][5] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[25][6] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[25][7] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[25][8] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[25][9] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[26][0] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[26][10] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[26][11] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[26][12] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[26][13] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[26][14] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[26][15] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[26][16] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[26][17] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[26][18] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[26][19] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[26][1] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[26][20] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[26][21] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[26][22] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[26][23] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[26][24] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[26][25] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[26][26] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[26][27] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[26][28] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[26][29] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[26][2] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[26][30] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[26][31] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[26][3] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[26][4] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[26][5] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[26][6] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[26][7] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[26][8] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[26][9] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[27][0] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[27][10] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[27][11] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[27][12] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[27][13] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[27][14] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[27][15] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[27][16] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[27][17] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[27][18] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[27][19] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[27][1] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[27][20] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[27][21] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[27][22] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[27][23] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[27][24] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[27][25] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[27][26] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[27][27] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[27][28] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[27][29] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[27][2] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[27][30] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[27][31] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[27][3] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[27][4] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[27][5] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[27][6] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[27][7] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[27][8] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[27][9] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[28][0] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[28][10] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[28][11] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[28][12] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[28][13] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[28][14] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[28][15] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[28][16] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[28][17] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[28][18] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[28][19] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[28][1] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[28][20] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[28][21] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[28][22] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[28][23] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[28][24] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[28][25] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[28][26] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[28][27] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[28][28] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[28][29] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[28][2] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[28][30] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[28][31] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[28][3] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[28][4] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[28][5] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[28][6] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[28][7] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[28][8] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[28][9] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[29][0] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[29][10] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[29][11] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[29][12] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[29][13] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[29][14] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[29][15] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[29][16] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[29][17] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[29][18] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[29][19] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[29][1] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[29][20] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[29][21] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[29][22] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[29][23] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[29][24] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[29][25] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[29][26] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[29][27] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[29][28] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[29][29] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[29][2] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[29][30] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[29][31] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[29][3] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[29][4] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[29][5] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[29][6] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[29][7] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[29][8] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[29][9] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[2][0] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[2][10] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[2][11] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[2][12] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[2][13] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[2][14] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[2][15] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[2][16] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[2][17] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[2][18] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[2][19] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[2][1] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[2][20] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[2][21] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[2][22] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[2][23] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[2][24] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[2][25] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[2][26] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[2][27] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[2][28] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[2][29] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[2][2] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[2][30] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[2][31] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[2][3] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[2][4] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[2][5] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[2][6] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[2][7] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[2][8] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[2][9] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[30][0] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[30][10] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[30][11] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[30][12] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[30][13] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[30][14] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[30][15] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[30][16] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[30][17] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[30][18] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[30][19] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[30][1] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[30][20] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[30][21] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[30][22] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[30][23] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[30][24] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[30][25] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[30][26] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[30][27] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[30][28] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[30][29] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[30][2] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[30][30] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[30][31] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[30][3] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[30][4] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[30][5] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[30][6] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[30][7] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[30][8] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[30][9] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[31][0] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[31][10] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[31][11] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[31][12] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[31][13] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[31][14] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[31][15] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[31][16] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[31][17] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[31][18] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[31][19] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[31][1] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[31][20] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[31][21] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[31][22] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[31][23] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[31][24] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[31][25] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[31][26] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[31][27] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[31][28] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[31][29] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[31][2] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[31][30] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[31][31] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[31][3] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[31][4] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[31][5] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[31][6] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[31][7] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[31][8] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[31][9] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[3][0] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[3][10] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[3][11] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[3][12] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[3][13] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[3][14] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[3][15] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[3][16] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[3][17] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[3][18] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[3][19] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[3][1] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[3][20] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[3][21] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[3][22] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[3][23] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[3][24] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[3][25] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[3][26] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[3][27] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[3][28] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[3][29] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[3][2] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[3][30] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[3][31] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[3][3] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[3][4] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[3][5] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[3][6] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[3][7] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[3][8] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[3][9] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[4][0] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[4][10] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[4][11] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[4][12] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[4][13] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[4][14] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[4][15] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[4][16] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[4][17] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[4][18] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[4][19] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[4][1] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[4][20] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[4][21] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[4][22] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[4][23] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[4][24] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[4][25] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[4][26] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[4][27] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[4][28] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[4][29] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[4][2] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[4][30] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[4][31] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[4][3] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[4][4] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[4][5] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[4][6] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[4][7] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[4][8] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[4][9] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[5][0] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[5][10] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[5][11] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[5][12] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[5][13] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[5][14] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[5][15] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[5][16] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[5][17] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[5][18] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[5][19] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[5][1] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[5][20] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[5][21] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[5][22] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[5][23] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[5][24] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[5][25] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[5][26] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[5][27] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[5][28] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[5][29] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[5][2] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[5][30] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[5][31] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[5][3] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[5][4] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[5][5] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[5][6] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[5][7] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[5][8] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[5][9] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[6][0] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[6][10] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[6][11] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[6][12] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[6][13] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[6][14] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[6][15] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[6][16] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[6][17] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[6][18] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[6][19] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[6][1] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[6][20] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[6][21] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[6][22] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[6][23] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[6][24] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[6][25] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[6][26] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[6][27] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[6][28] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[6][29] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[6][2] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[6][30] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[6][31] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[6][3] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[6][4] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[6][5] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[6][6] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[6][7] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[6][8] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[6][9] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[7][0] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[7][10] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[7][11] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[7][12] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[7][13] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[7][14] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[7][15] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[7][16] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[7][17] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[7][18] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[7][19] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[7][1] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[7][20] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[7][21] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[7][22] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[7][23] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[7][24] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[7][25] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[7][26] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[7][27] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[7][28] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[7][29] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[7][2] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[7][30] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[7][31] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[7][3] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[7][4] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[7][5] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[7][6] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[7][7] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[7][8] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[7][9] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[8][0] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[8][10] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[8][11] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[8][12] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[8][13] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[8][14] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[8][15] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[8][16] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[8][17] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[8][18] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[8][19] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[8][1] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[8][20] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[8][21] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[8][22] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[8][23] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[8][24] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[8][25] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[8][26] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[8][27] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[8][28] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[8][29] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[8][2] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[8][30] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[8][31] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[8][3] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[8][4] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[8][5] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[8][6] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[8][7] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[8][8] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[8][9] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[9][0] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[9][10] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[9][11] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[9][12] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[9][13] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[9][14] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[9][15] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[9][16] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[9][17] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[9][18] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[9][19] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[9][1] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[9][20] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[9][21] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[9][22] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[9][23] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[9][24] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[9][25] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[9][26] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[9][27] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[9][28] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[9][29] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[9][2] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[9][30] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[9][31] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[9][3] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[9][4] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[9][5] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[9][6] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[9][7] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[9][8] ;
+ wire \soc.core.VexRiscv.RegFilePlugin_regFile[9][9] ;
+ wire \soc.core.VexRiscv._zz_2 ;
+ wire \soc.core.VexRiscv._zz_CsrPlugin_csrMapping_readDataInit[0] ;
+ wire \soc.core.VexRiscv._zz_CsrPlugin_csrMapping_readDataInit[10] ;
+ wire \soc.core.VexRiscv._zz_CsrPlugin_csrMapping_readDataInit[11] ;
+ wire \soc.core.VexRiscv._zz_CsrPlugin_csrMapping_readDataInit[12] ;
+ wire \soc.core.VexRiscv._zz_CsrPlugin_csrMapping_readDataInit[13] ;
+ wire \soc.core.VexRiscv._zz_CsrPlugin_csrMapping_readDataInit[14] ;
+ wire \soc.core.VexRiscv._zz_CsrPlugin_csrMapping_readDataInit[15] ;
+ wire \soc.core.VexRiscv._zz_CsrPlugin_csrMapping_readDataInit[16] ;
+ wire \soc.core.VexRiscv._zz_CsrPlugin_csrMapping_readDataInit[17] ;
+ wire \soc.core.VexRiscv._zz_CsrPlugin_csrMapping_readDataInit[18] ;
+ wire \soc.core.VexRiscv._zz_CsrPlugin_csrMapping_readDataInit[19] ;
+ wire \soc.core.VexRiscv._zz_CsrPlugin_csrMapping_readDataInit[1] ;
+ wire \soc.core.VexRiscv._zz_CsrPlugin_csrMapping_readDataInit[20] ;
+ wire \soc.core.VexRiscv._zz_CsrPlugin_csrMapping_readDataInit[21] ;
+ wire \soc.core.VexRiscv._zz_CsrPlugin_csrMapping_readDataInit[22] ;
+ wire \soc.core.VexRiscv._zz_CsrPlugin_csrMapping_readDataInit[23] ;
+ wire \soc.core.VexRiscv._zz_CsrPlugin_csrMapping_readDataInit[24] ;
+ wire \soc.core.VexRiscv._zz_CsrPlugin_csrMapping_readDataInit[25] ;
+ wire \soc.core.VexRiscv._zz_CsrPlugin_csrMapping_readDataInit[26] ;
+ wire \soc.core.VexRiscv._zz_CsrPlugin_csrMapping_readDataInit[27] ;
+ wire \soc.core.VexRiscv._zz_CsrPlugin_csrMapping_readDataInit[28] ;
+ wire \soc.core.VexRiscv._zz_CsrPlugin_csrMapping_readDataInit[29] ;
+ wire \soc.core.VexRiscv._zz_CsrPlugin_csrMapping_readDataInit[2] ;
+ wire \soc.core.VexRiscv._zz_CsrPlugin_csrMapping_readDataInit[30] ;
+ wire \soc.core.VexRiscv._zz_CsrPlugin_csrMapping_readDataInit[31] ;
+ wire \soc.core.VexRiscv._zz_CsrPlugin_csrMapping_readDataInit[3] ;
+ wire \soc.core.VexRiscv._zz_CsrPlugin_csrMapping_readDataInit[4] ;
+ wire \soc.core.VexRiscv._zz_CsrPlugin_csrMapping_readDataInit[5] ;
+ wire \soc.core.VexRiscv._zz_CsrPlugin_csrMapping_readDataInit[6] ;
+ wire \soc.core.VexRiscv._zz_CsrPlugin_csrMapping_readDataInit[7] ;
+ wire \soc.core.VexRiscv._zz_CsrPlugin_csrMapping_readDataInit[8] ;
+ wire \soc.core.VexRiscv._zz_CsrPlugin_csrMapping_readDataInit[9] ;
+ wire \soc.core.VexRiscv._zz_RegFilePlugin_regFile_port0[0] ;
+ wire \soc.core.VexRiscv._zz_RegFilePlugin_regFile_port0[10] ;
+ wire \soc.core.VexRiscv._zz_RegFilePlugin_regFile_port0[11] ;
+ wire \soc.core.VexRiscv._zz_RegFilePlugin_regFile_port0[12] ;
+ wire \soc.core.VexRiscv._zz_RegFilePlugin_regFile_port0[13] ;
+ wire \soc.core.VexRiscv._zz_RegFilePlugin_regFile_port0[14] ;
+ wire \soc.core.VexRiscv._zz_RegFilePlugin_regFile_port0[15] ;
+ wire \soc.core.VexRiscv._zz_RegFilePlugin_regFile_port0[16] ;
+ wire \soc.core.VexRiscv._zz_RegFilePlugin_regFile_port0[17] ;
+ wire \soc.core.VexRiscv._zz_RegFilePlugin_regFile_port0[18] ;
+ wire \soc.core.VexRiscv._zz_RegFilePlugin_regFile_port0[19] ;
+ wire \soc.core.VexRiscv._zz_RegFilePlugin_regFile_port0[1] ;
+ wire \soc.core.VexRiscv._zz_RegFilePlugin_regFile_port0[20] ;
+ wire \soc.core.VexRiscv._zz_RegFilePlugin_regFile_port0[21] ;
+ wire \soc.core.VexRiscv._zz_RegFilePlugin_regFile_port0[22] ;
+ wire \soc.core.VexRiscv._zz_RegFilePlugin_regFile_port0[23] ;
+ wire \soc.core.VexRiscv._zz_RegFilePlugin_regFile_port0[24] ;
+ wire \soc.core.VexRiscv._zz_RegFilePlugin_regFile_port0[25] ;
+ wire \soc.core.VexRiscv._zz_RegFilePlugin_regFile_port0[26] ;
+ wire \soc.core.VexRiscv._zz_RegFilePlugin_regFile_port0[27] ;
+ wire \soc.core.VexRiscv._zz_RegFilePlugin_regFile_port0[28] ;
+ wire \soc.core.VexRiscv._zz_RegFilePlugin_regFile_port0[29] ;
+ wire \soc.core.VexRiscv._zz_RegFilePlugin_regFile_port0[2] ;
+ wire \soc.core.VexRiscv._zz_RegFilePlugin_regFile_port0[30] ;
+ wire \soc.core.VexRiscv._zz_RegFilePlugin_regFile_port0[31] ;
+ wire \soc.core.VexRiscv._zz_RegFilePlugin_regFile_port0[3] ;
+ wire \soc.core.VexRiscv._zz_RegFilePlugin_regFile_port0[4] ;
+ wire \soc.core.VexRiscv._zz_RegFilePlugin_regFile_port0[5] ;
+ wire \soc.core.VexRiscv._zz_RegFilePlugin_regFile_port0[6] ;
+ wire \soc.core.VexRiscv._zz_RegFilePlugin_regFile_port0[7] ;
+ wire \soc.core.VexRiscv._zz_RegFilePlugin_regFile_port0[8] ;
+ wire \soc.core.VexRiscv._zz_RegFilePlugin_regFile_port0[9] ;
+ wire \soc.core.VexRiscv._zz_RegFilePlugin_regFile_port1[0] ;
+ wire \soc.core.VexRiscv._zz_RegFilePlugin_regFile_port1[10] ;
+ wire \soc.core.VexRiscv._zz_RegFilePlugin_regFile_port1[11] ;
+ wire \soc.core.VexRiscv._zz_RegFilePlugin_regFile_port1[12] ;
+ wire \soc.core.VexRiscv._zz_RegFilePlugin_regFile_port1[13] ;
+ wire \soc.core.VexRiscv._zz_RegFilePlugin_regFile_port1[14] ;
+ wire \soc.core.VexRiscv._zz_RegFilePlugin_regFile_port1[15] ;
+ wire \soc.core.VexRiscv._zz_RegFilePlugin_regFile_port1[16] ;
+ wire \soc.core.VexRiscv._zz_RegFilePlugin_regFile_port1[17] ;
+ wire \soc.core.VexRiscv._zz_RegFilePlugin_regFile_port1[18] ;
+ wire \soc.core.VexRiscv._zz_RegFilePlugin_regFile_port1[19] ;
+ wire \soc.core.VexRiscv._zz_RegFilePlugin_regFile_port1[1] ;
+ wire \soc.core.VexRiscv._zz_RegFilePlugin_regFile_port1[20] ;
+ wire \soc.core.VexRiscv._zz_RegFilePlugin_regFile_port1[21] ;
+ wire \soc.core.VexRiscv._zz_RegFilePlugin_regFile_port1[22] ;
+ wire \soc.core.VexRiscv._zz_RegFilePlugin_regFile_port1[23] ;
+ wire \soc.core.VexRiscv._zz_RegFilePlugin_regFile_port1[24] ;
+ wire \soc.core.VexRiscv._zz_RegFilePlugin_regFile_port1[25] ;
+ wire \soc.core.VexRiscv._zz_RegFilePlugin_regFile_port1[26] ;
+ wire \soc.core.VexRiscv._zz_RegFilePlugin_regFile_port1[27] ;
+ wire \soc.core.VexRiscv._zz_RegFilePlugin_regFile_port1[28] ;
+ wire \soc.core.VexRiscv._zz_RegFilePlugin_regFile_port1[29] ;
+ wire \soc.core.VexRiscv._zz_RegFilePlugin_regFile_port1[2] ;
+ wire \soc.core.VexRiscv._zz_RegFilePlugin_regFile_port1[30] ;
+ wire \soc.core.VexRiscv._zz_RegFilePlugin_regFile_port1[31] ;
+ wire \soc.core.VexRiscv._zz_RegFilePlugin_regFile_port1[3] ;
+ wire \soc.core.VexRiscv._zz_RegFilePlugin_regFile_port1[4] ;
+ wire \soc.core.VexRiscv._zz_RegFilePlugin_regFile_port1[5] ;
+ wire \soc.core.VexRiscv._zz_RegFilePlugin_regFile_port1[6] ;
+ wire \soc.core.VexRiscv._zz_RegFilePlugin_regFile_port1[7] ;
+ wire \soc.core.VexRiscv._zz_RegFilePlugin_regFile_port1[8] ;
+ wire \soc.core.VexRiscv._zz_RegFilePlugin_regFile_port1[9] ;
+ wire \soc.core.VexRiscv._zz_dBus_cmd_payload_data[0] ;
+ wire \soc.core.VexRiscv._zz_dBus_cmd_payload_data[1] ;
+ wire \soc.core.VexRiscv._zz_dBus_cmd_payload_data[2] ;
+ wire \soc.core.VexRiscv._zz_dBus_cmd_payload_data[3] ;
+ wire \soc.core.VexRiscv._zz_dBus_cmd_payload_data[4] ;
+ wire \soc.core.VexRiscv._zz_dBus_cmd_payload_data[5] ;
+ wire \soc.core.VexRiscv._zz_dBus_cmd_payload_data[6] ;
+ wire \soc.core.VexRiscv._zz_dBus_cmd_payload_data[7] ;
+ wire \soc.core.VexRiscv._zz_execute_ALU_BITWISE_CTRL[0] ;
+ wire \soc.core.VexRiscv._zz_execute_ALU_CTRL[0] ;
+ wire \soc.core.VexRiscv._zz_execute_ALU_CTRL[1] ;
+ wire \soc.core.VexRiscv._zz_execute_BRANCH_CTRL[0] ;
+ wire \soc.core.VexRiscv._zz_execute_BRANCH_CTRL[1] ;
+ wire \soc.core.VexRiscv._zz_execute_ENV_CTRL[0] ;
+ wire \soc.core.VexRiscv._zz_execute_ENV_CTRL[1] ;
+ wire \soc.core.VexRiscv._zz_execute_SHIFT_CTRL[0] ;
+ wire \soc.core.VexRiscv._zz_execute_SHIFT_CTRL[1] ;
+ wire \soc.core.VexRiscv._zz_execute_SRC1_CTRL[0] ;
+ wire \soc.core.VexRiscv._zz_execute_SRC1_CTRL[1] ;
+ wire \soc.core.VexRiscv._zz_execute_SRC2[10] ;
+ wire \soc.core.VexRiscv._zz_execute_SRC2[11] ;
+ wire \soc.core.VexRiscv._zz_execute_SRC2[12] ;
+ wire \soc.core.VexRiscv._zz_execute_SRC2[13] ;
+ wire \soc.core.VexRiscv._zz_execute_SRC2[14] ;
+ wire \soc.core.VexRiscv._zz_execute_SRC2[15] ;
+ wire \soc.core.VexRiscv._zz_execute_SRC2[16] ;
+ wire \soc.core.VexRiscv._zz_execute_SRC2[17] ;
+ wire \soc.core.VexRiscv._zz_execute_SRC2[18] ;
+ wire \soc.core.VexRiscv._zz_execute_SRC2[19] ;
+ wire \soc.core.VexRiscv._zz_execute_SRC2[20] ;
+ wire \soc.core.VexRiscv._zz_execute_SRC2[21] ;
+ wire \soc.core.VexRiscv._zz_execute_SRC2[22] ;
+ wire \soc.core.VexRiscv._zz_execute_SRC2[23] ;
+ wire \soc.core.VexRiscv._zz_execute_SRC2[24] ;
+ wire \soc.core.VexRiscv._zz_execute_SRC2[25] ;
+ wire \soc.core.VexRiscv._zz_execute_SRC2[26] ;
+ wire \soc.core.VexRiscv._zz_execute_SRC2[27] ;
+ wire \soc.core.VexRiscv._zz_execute_SRC2[28] ;
+ wire \soc.core.VexRiscv._zz_execute_SRC2[29] ;
+ wire \soc.core.VexRiscv._zz_execute_SRC2[2] ;
+ wire \soc.core.VexRiscv._zz_execute_SRC2[30] ;
+ wire \soc.core.VexRiscv._zz_execute_SRC2[31] ;
+ wire \soc.core.VexRiscv._zz_execute_SRC2[3] ;
+ wire \soc.core.VexRiscv._zz_execute_SRC2[4] ;
+ wire \soc.core.VexRiscv._zz_execute_SRC2[5] ;
+ wire \soc.core.VexRiscv._zz_execute_SRC2[6] ;
+ wire \soc.core.VexRiscv._zz_execute_SRC2[7] ;
+ wire \soc.core.VexRiscv._zz_execute_SRC2[8] ;
+ wire \soc.core.VexRiscv._zz_execute_SRC2[9] ;
+ wire \soc.core.VexRiscv._zz_execute_SRC2_CTRL[0] ;
+ wire \soc.core.VexRiscv._zz_execute_SRC2_CTRL[1] ;
+ wire \soc.core.VexRiscv._zz_iBusWishbone_ADR[0] ;
+ wire \soc.core.VexRiscv._zz_iBusWishbone_ADR[1] ;
+ wire \soc.core.VexRiscv._zz_iBusWishbone_ADR[2] ;
+ wire \soc.core.VexRiscv._zz_lastStageRegFileWrite_payload_address[12] ;
+ wire \soc.core.VexRiscv._zz_lastStageRegFileWrite_payload_address[13] ;
+ wire \soc.core.VexRiscv._zz_lastStageRegFileWrite_payload_address[14] ;
+ wire \soc.core.VexRiscv._zz_lastStageRegFileWrite_payload_address[28] ;
+ wire \soc.core.VexRiscv._zz_lastStageRegFileWrite_payload_address[29] ;
+ wire \soc.core.VexRiscv._zz_lastStageRegFileWrite_valid ;
+ wire \soc.core.VexRiscv._zz_memory_ENV_CTRL[0] ;
+ wire \soc.core.VexRiscv._zz_memory_ENV_CTRL[1] ;
+ wire \soc.core.VexRiscv._zz_when_DebugPlugin_l244 ;
+ wire \soc.core.VexRiscv._zz_writeBack_ENV_CTRL[0] ;
+ wire \soc.core.VexRiscv._zz_writeBack_ENV_CTRL[1] ;
+ wire \soc.core.VexRiscv.dBusWishbone_ADR[0] ;
+ wire \soc.core.VexRiscv.dBusWishbone_ADR[10] ;
+ wire \soc.core.VexRiscv.dBusWishbone_ADR[11] ;
+ wire \soc.core.VexRiscv.dBusWishbone_ADR[12] ;
+ wire \soc.core.VexRiscv.dBusWishbone_ADR[13] ;
+ wire \soc.core.VexRiscv.dBusWishbone_ADR[14] ;
+ wire \soc.core.VexRiscv.dBusWishbone_ADR[15] ;
+ wire \soc.core.VexRiscv.dBusWishbone_ADR[16] ;
+ wire \soc.core.VexRiscv.dBusWishbone_ADR[17] ;
+ wire \soc.core.VexRiscv.dBusWishbone_ADR[18] ;
+ wire \soc.core.VexRiscv.dBusWishbone_ADR[19] ;
+ wire \soc.core.VexRiscv.dBusWishbone_ADR[1] ;
+ wire \soc.core.VexRiscv.dBusWishbone_ADR[20] ;
+ wire \soc.core.VexRiscv.dBusWishbone_ADR[21] ;
+ wire \soc.core.VexRiscv.dBusWishbone_ADR[22] ;
+ wire \soc.core.VexRiscv.dBusWishbone_ADR[23] ;
+ wire \soc.core.VexRiscv.dBusWishbone_ADR[24] ;
+ wire \soc.core.VexRiscv.dBusWishbone_ADR[25] ;
+ wire \soc.core.VexRiscv.dBusWishbone_ADR[26] ;
+ wire \soc.core.VexRiscv.dBusWishbone_ADR[27] ;
+ wire \soc.core.VexRiscv.dBusWishbone_ADR[28] ;
+ wire \soc.core.VexRiscv.dBusWishbone_ADR[29] ;
+ wire \soc.core.VexRiscv.dBusWishbone_ADR[2] ;
+ wire \soc.core.VexRiscv.dBusWishbone_ADR[3] ;
+ wire \soc.core.VexRiscv.dBusWishbone_ADR[4] ;
+ wire \soc.core.VexRiscv.dBusWishbone_ADR[5] ;
+ wire \soc.core.VexRiscv.dBusWishbone_ADR[6] ;
+ wire \soc.core.VexRiscv.dBusWishbone_ADR[7] ;
+ wire \soc.core.VexRiscv.dBusWishbone_ADR[8] ;
+ wire \soc.core.VexRiscv.dBusWishbone_ADR[9] ;
+ wire \soc.core.VexRiscv.dBusWishbone_CYC ;
+ wire \soc.core.VexRiscv.dBusWishbone_DAT_MISO[0] ;
+ wire \soc.core.VexRiscv.dBusWishbone_DAT_MISO[10] ;
+ wire \soc.core.VexRiscv.dBusWishbone_DAT_MISO[11] ;
+ wire \soc.core.VexRiscv.dBusWishbone_DAT_MISO[12] ;
+ wire \soc.core.VexRiscv.dBusWishbone_DAT_MISO[13] ;
+ wire \soc.core.VexRiscv.dBusWishbone_DAT_MISO[14] ;
+ wire \soc.core.VexRiscv.dBusWishbone_DAT_MISO[15] ;
+ wire \soc.core.VexRiscv.dBusWishbone_DAT_MISO[16] ;
+ wire \soc.core.VexRiscv.dBusWishbone_DAT_MISO[17] ;
+ wire \soc.core.VexRiscv.dBusWishbone_DAT_MISO[18] ;
+ wire \soc.core.VexRiscv.dBusWishbone_DAT_MISO[19] ;
+ wire \soc.core.VexRiscv.dBusWishbone_DAT_MISO[1] ;
+ wire \soc.core.VexRiscv.dBusWishbone_DAT_MISO[20] ;
+ wire \soc.core.VexRiscv.dBusWishbone_DAT_MISO[21] ;
+ wire \soc.core.VexRiscv.dBusWishbone_DAT_MISO[22] ;
+ wire \soc.core.VexRiscv.dBusWishbone_DAT_MISO[23] ;
+ wire \soc.core.VexRiscv.dBusWishbone_DAT_MISO[24] ;
+ wire \soc.core.VexRiscv.dBusWishbone_DAT_MISO[25] ;
+ wire \soc.core.VexRiscv.dBusWishbone_DAT_MISO[26] ;
+ wire \soc.core.VexRiscv.dBusWishbone_DAT_MISO[27] ;
+ wire \soc.core.VexRiscv.dBusWishbone_DAT_MISO[28] ;
+ wire \soc.core.VexRiscv.dBusWishbone_DAT_MISO[29] ;
+ wire \soc.core.VexRiscv.dBusWishbone_DAT_MISO[2] ;
+ wire \soc.core.VexRiscv.dBusWishbone_DAT_MISO[30] ;
+ wire \soc.core.VexRiscv.dBusWishbone_DAT_MISO[31] ;
+ wire \soc.core.VexRiscv.dBusWishbone_DAT_MISO[3] ;
+ wire \soc.core.VexRiscv.dBusWishbone_DAT_MISO[4] ;
+ wire \soc.core.VexRiscv.dBusWishbone_DAT_MISO[5] ;
+ wire \soc.core.VexRiscv.dBusWishbone_DAT_MISO[6] ;
+ wire \soc.core.VexRiscv.dBusWishbone_DAT_MISO[7] ;
+ wire \soc.core.VexRiscv.dBusWishbone_DAT_MISO[8] ;
+ wire \soc.core.VexRiscv.dBusWishbone_DAT_MISO[9] ;
+ wire \soc.core.VexRiscv.dBusWishbone_DAT_MOSI[0] ;
+ wire \soc.core.VexRiscv.dBusWishbone_DAT_MOSI[10] ;
+ wire \soc.core.VexRiscv.dBusWishbone_DAT_MOSI[11] ;
+ wire \soc.core.VexRiscv.dBusWishbone_DAT_MOSI[12] ;
+ wire \soc.core.VexRiscv.dBusWishbone_DAT_MOSI[13] ;
+ wire \soc.core.VexRiscv.dBusWishbone_DAT_MOSI[14] ;
+ wire \soc.core.VexRiscv.dBusWishbone_DAT_MOSI[15] ;
+ wire \soc.core.VexRiscv.dBusWishbone_DAT_MOSI[16] ;
+ wire \soc.core.VexRiscv.dBusWishbone_DAT_MOSI[17] ;
+ wire \soc.core.VexRiscv.dBusWishbone_DAT_MOSI[18] ;
+ wire \soc.core.VexRiscv.dBusWishbone_DAT_MOSI[19] ;
+ wire \soc.core.VexRiscv.dBusWishbone_DAT_MOSI[1] ;
+ wire \soc.core.VexRiscv.dBusWishbone_DAT_MOSI[20] ;
+ wire \soc.core.VexRiscv.dBusWishbone_DAT_MOSI[21] ;
+ wire \soc.core.VexRiscv.dBusWishbone_DAT_MOSI[22] ;
+ wire \soc.core.VexRiscv.dBusWishbone_DAT_MOSI[23] ;
+ wire \soc.core.VexRiscv.dBusWishbone_DAT_MOSI[24] ;
+ wire \soc.core.VexRiscv.dBusWishbone_DAT_MOSI[25] ;
+ wire \soc.core.VexRiscv.dBusWishbone_DAT_MOSI[26] ;
+ wire \soc.core.VexRiscv.dBusWishbone_DAT_MOSI[27] ;
+ wire \soc.core.VexRiscv.dBusWishbone_DAT_MOSI[28] ;
+ wire \soc.core.VexRiscv.dBusWishbone_DAT_MOSI[29] ;
+ wire \soc.core.VexRiscv.dBusWishbone_DAT_MOSI[2] ;
+ wire \soc.core.VexRiscv.dBusWishbone_DAT_MOSI[30] ;
+ wire \soc.core.VexRiscv.dBusWishbone_DAT_MOSI[31] ;
+ wire \soc.core.VexRiscv.dBusWishbone_DAT_MOSI[3] ;
+ wire \soc.core.VexRiscv.dBusWishbone_DAT_MOSI[4] ;
+ wire \soc.core.VexRiscv.dBusWishbone_DAT_MOSI[5] ;
+ wire \soc.core.VexRiscv.dBusWishbone_DAT_MOSI[6] ;
+ wire \soc.core.VexRiscv.dBusWishbone_DAT_MOSI[7] ;
+ wire \soc.core.VexRiscv.dBusWishbone_DAT_MOSI[8] ;
+ wire \soc.core.VexRiscv.dBusWishbone_DAT_MOSI[9] ;
+ wire \soc.core.VexRiscv.dBusWishbone_WE ;
+ wire \soc.core.VexRiscv.dBus_cmd_halfPipe_payload_address[0] ;
+ wire \soc.core.VexRiscv.dBus_cmd_halfPipe_payload_address[1] ;
+ wire \soc.core.VexRiscv.dBus_cmd_halfPipe_payload_size[0] ;
+ wire \soc.core.VexRiscv.dBus_cmd_halfPipe_payload_size[1] ;
+ wire \soc.core.VexRiscv.debug_bus_rsp_data[0] ;
+ wire \soc.core.VexRiscv.debug_bus_rsp_data[1] ;
+ wire \soc.core.VexRiscv.debug_bus_rsp_data[2] ;
+ wire \soc.core.VexRiscv.debug_bus_rsp_data[3] ;
+ wire \soc.core.VexRiscv.debug_bus_rsp_data[4] ;
+ wire \soc.core.VexRiscv.decode_to_execute_CSR_WRITE_OPCODE ;
+ wire \soc.core.VexRiscv.decode_to_execute_DO_EBREAK ;
+ wire \soc.core.VexRiscv.decode_to_execute_IS_CSR ;
+ wire \soc.core.VexRiscv.decode_to_execute_MEMORY_ENABLE ;
+ wire \soc.core.VexRiscv.decode_to_execute_REGFILE_WRITE_VALID ;
+ wire \soc.core.VexRiscv.decode_to_execute_RS1[0] ;
+ wire \soc.core.VexRiscv.decode_to_execute_RS1[10] ;
+ wire \soc.core.VexRiscv.decode_to_execute_RS1[11] ;
+ wire \soc.core.VexRiscv.decode_to_execute_RS1[12] ;
+ wire \soc.core.VexRiscv.decode_to_execute_RS1[13] ;
+ wire \soc.core.VexRiscv.decode_to_execute_RS1[14] ;
+ wire \soc.core.VexRiscv.decode_to_execute_RS1[15] ;
+ wire \soc.core.VexRiscv.decode_to_execute_RS1[16] ;
+ wire \soc.core.VexRiscv.decode_to_execute_RS1[17] ;
+ wire \soc.core.VexRiscv.decode_to_execute_RS1[18] ;
+ wire \soc.core.VexRiscv.decode_to_execute_RS1[19] ;
+ wire \soc.core.VexRiscv.decode_to_execute_RS1[1] ;
+ wire \soc.core.VexRiscv.decode_to_execute_RS1[20] ;
+ wire \soc.core.VexRiscv.decode_to_execute_RS1[21] ;
+ wire \soc.core.VexRiscv.decode_to_execute_RS1[22] ;
+ wire \soc.core.VexRiscv.decode_to_execute_RS1[23] ;
+ wire \soc.core.VexRiscv.decode_to_execute_RS1[24] ;
+ wire \soc.core.VexRiscv.decode_to_execute_RS1[25] ;
+ wire \soc.core.VexRiscv.decode_to_execute_RS1[26] ;
+ wire \soc.core.VexRiscv.decode_to_execute_RS1[27] ;
+ wire \soc.core.VexRiscv.decode_to_execute_RS1[28] ;
+ wire \soc.core.VexRiscv.decode_to_execute_RS1[29] ;
+ wire \soc.core.VexRiscv.decode_to_execute_RS1[2] ;
+ wire \soc.core.VexRiscv.decode_to_execute_RS1[30] ;
+ wire \soc.core.VexRiscv.decode_to_execute_RS1[31] ;
+ wire \soc.core.VexRiscv.decode_to_execute_RS1[3] ;
+ wire \soc.core.VexRiscv.decode_to_execute_RS1[4] ;
+ wire \soc.core.VexRiscv.decode_to_execute_RS1[5] ;
+ wire \soc.core.VexRiscv.decode_to_execute_RS1[6] ;
+ wire \soc.core.VexRiscv.decode_to_execute_RS1[7] ;
+ wire \soc.core.VexRiscv.decode_to_execute_RS1[8] ;
+ wire \soc.core.VexRiscv.decode_to_execute_RS1[9] ;
+ wire \soc.core.VexRiscv.decode_to_execute_RS2[10] ;
+ wire \soc.core.VexRiscv.decode_to_execute_RS2[11] ;
+ wire \soc.core.VexRiscv.decode_to_execute_RS2[12] ;
+ wire \soc.core.VexRiscv.decode_to_execute_RS2[13] ;
+ wire \soc.core.VexRiscv.decode_to_execute_RS2[14] ;
+ wire \soc.core.VexRiscv.decode_to_execute_RS2[15] ;
+ wire \soc.core.VexRiscv.decode_to_execute_RS2[16] ;
+ wire \soc.core.VexRiscv.decode_to_execute_RS2[17] ;
+ wire \soc.core.VexRiscv.decode_to_execute_RS2[18] ;
+ wire \soc.core.VexRiscv.decode_to_execute_RS2[19] ;
+ wire \soc.core.VexRiscv.decode_to_execute_RS2[20] ;
+ wire \soc.core.VexRiscv.decode_to_execute_RS2[21] ;
+ wire \soc.core.VexRiscv.decode_to_execute_RS2[22] ;
+ wire \soc.core.VexRiscv.decode_to_execute_RS2[23] ;
+ wire \soc.core.VexRiscv.decode_to_execute_RS2[24] ;
+ wire \soc.core.VexRiscv.decode_to_execute_RS2[25] ;
+ wire \soc.core.VexRiscv.decode_to_execute_RS2[26] ;
+ wire \soc.core.VexRiscv.decode_to_execute_RS2[27] ;
+ wire \soc.core.VexRiscv.decode_to_execute_RS2[28] ;
+ wire \soc.core.VexRiscv.decode_to_execute_RS2[29] ;
+ wire \soc.core.VexRiscv.decode_to_execute_RS2[30] ;
+ wire \soc.core.VexRiscv.decode_to_execute_RS2[31] ;
+ wire \soc.core.VexRiscv.decode_to_execute_RS2[8] ;
+ wire \soc.core.VexRiscv.decode_to_execute_RS2[9] ;
+ wire \soc.core.VexRiscv.decode_to_execute_SRC2_FORCE_ZERO ;
+ wire \soc.core.VexRiscv.decode_to_execute_SRC_LESS_UNSIGNED ;
+ wire \soc.core.VexRiscv.decode_to_execute_SRC_USE_SUB_LESS ;
+ wire \soc.core.VexRiscv.execute_CsrPlugin_csr_3008 ;
+ wire \soc.core.VexRiscv.execute_CsrPlugin_csr_4032 ;
+ wire \soc.core.VexRiscv.execute_CsrPlugin_csr_768 ;
+ wire \soc.core.VexRiscv.execute_CsrPlugin_csr_772 ;
+ wire \soc.core.VexRiscv.execute_CsrPlugin_csr_773 ;
+ wire \soc.core.VexRiscv.execute_CsrPlugin_csr_833 ;
+ wire \soc.core.VexRiscv.execute_CsrPlugin_csr_834 ;
+ wire \soc.core.VexRiscv.execute_CsrPlugin_csr_835 ;
+ wire \soc.core.VexRiscv.execute_CsrPlugin_csr_836 ;
+ wire \soc.core.VexRiscv.execute_LightShifterPlugin_amplitudeReg[0] ;
+ wire \soc.core.VexRiscv.execute_LightShifterPlugin_amplitudeReg[1] ;
+ wire \soc.core.VexRiscv.execute_LightShifterPlugin_amplitudeReg[2] ;
+ wire \soc.core.VexRiscv.execute_LightShifterPlugin_amplitudeReg[3] ;
+ wire \soc.core.VexRiscv.execute_LightShifterPlugin_amplitudeReg[4] ;
+ wire \soc.core.VexRiscv.execute_LightShifterPlugin_isActive ;
+ wire \soc.core.VexRiscv.execute_arbitration_isValid ;
+ wire \soc.core.VexRiscv.execute_to_memory_ALIGNEMENT_FAULT ;
+ wire \soc.core.VexRiscv.execute_to_memory_BRANCH_DO ;
+ wire \soc.core.VexRiscv.execute_to_memory_INSTRUCTION[10] ;
+ wire \soc.core.VexRiscv.execute_to_memory_INSTRUCTION[11] ;
+ wire \soc.core.VexRiscv.execute_to_memory_INSTRUCTION[12] ;
+ wire \soc.core.VexRiscv.execute_to_memory_INSTRUCTION[13] ;
+ wire \soc.core.VexRiscv.execute_to_memory_INSTRUCTION[14] ;
+ wire \soc.core.VexRiscv.execute_to_memory_INSTRUCTION[28] ;
+ wire \soc.core.VexRiscv.execute_to_memory_INSTRUCTION[29] ;
+ wire \soc.core.VexRiscv.execute_to_memory_INSTRUCTION[5] ;
+ wire \soc.core.VexRiscv.execute_to_memory_INSTRUCTION[7] ;
+ wire \soc.core.VexRiscv.execute_to_memory_INSTRUCTION[8] ;
+ wire \soc.core.VexRiscv.execute_to_memory_INSTRUCTION[9] ;
+ wire \soc.core.VexRiscv.execute_to_memory_MEMORY_ADDRESS_LOW[0] ;
+ wire \soc.core.VexRiscv.execute_to_memory_MEMORY_ADDRESS_LOW[1] ;
+ wire \soc.core.VexRiscv.execute_to_memory_MEMORY_ENABLE ;
+ wire \soc.core.VexRiscv.execute_to_memory_PC[10] ;
+ wire \soc.core.VexRiscv.execute_to_memory_PC[11] ;
+ wire \soc.core.VexRiscv.execute_to_memory_PC[12] ;
+ wire \soc.core.VexRiscv.execute_to_memory_PC[13] ;
+ wire \soc.core.VexRiscv.execute_to_memory_PC[14] ;
+ wire \soc.core.VexRiscv.execute_to_memory_PC[15] ;
+ wire \soc.core.VexRiscv.execute_to_memory_PC[16] ;
+ wire \soc.core.VexRiscv.execute_to_memory_PC[17] ;
+ wire \soc.core.VexRiscv.execute_to_memory_PC[18] ;
+ wire \soc.core.VexRiscv.execute_to_memory_PC[19] ;
+ wire \soc.core.VexRiscv.execute_to_memory_PC[20] ;
+ wire \soc.core.VexRiscv.execute_to_memory_PC[21] ;
+ wire \soc.core.VexRiscv.execute_to_memory_PC[22] ;
+ wire \soc.core.VexRiscv.execute_to_memory_PC[23] ;
+ wire \soc.core.VexRiscv.execute_to_memory_PC[24] ;
+ wire \soc.core.VexRiscv.execute_to_memory_PC[25] ;
+ wire \soc.core.VexRiscv.execute_to_memory_PC[26] ;
+ wire \soc.core.VexRiscv.execute_to_memory_PC[27] ;
+ wire \soc.core.VexRiscv.execute_to_memory_PC[28] ;
+ wire \soc.core.VexRiscv.execute_to_memory_PC[29] ;
+ wire \soc.core.VexRiscv.execute_to_memory_PC[2] ;
+ wire \soc.core.VexRiscv.execute_to_memory_PC[30] ;
+ wire \soc.core.VexRiscv.execute_to_memory_PC[31] ;
+ wire \soc.core.VexRiscv.execute_to_memory_PC[3] ;
+ wire \soc.core.VexRiscv.execute_to_memory_PC[4] ;
+ wire \soc.core.VexRiscv.execute_to_memory_PC[5] ;
+ wire \soc.core.VexRiscv.execute_to_memory_PC[6] ;
+ wire \soc.core.VexRiscv.execute_to_memory_PC[7] ;
+ wire \soc.core.VexRiscv.execute_to_memory_PC[8] ;
+ wire \soc.core.VexRiscv.execute_to_memory_PC[9] ;
+ wire \soc.core.VexRiscv.execute_to_memory_REGFILE_WRITE_VALID ;
+ wire \soc.core.VexRiscv.externalInterrupt ;
+ wire \soc.core.VexRiscv.externalInterruptArray_regNext[0] ;
+ wire \soc.core.VexRiscv.externalInterruptArray_regNext[1] ;
+ wire \soc.core.VexRiscv.externalInterruptArray_regNext[2] ;
+ wire \soc.core.VexRiscv.externalInterruptArray_regNext[3] ;
+ wire \soc.core.VexRiscv.externalInterruptArray_regNext[4] ;
+ wire \soc.core.VexRiscv.externalInterruptArray_regNext[5] ;
+ wire \soc.core.VexRiscv.externalInterruptArray_regNext[6] ;
+ wire \soc.core.VexRiscv.externalInterruptArray_regNext[7] ;
+ wire \soc.core.VexRiscv.lastStageIsFiring ;
+ wire \soc.core.VexRiscv.lastStagePc[10] ;
+ wire \soc.core.VexRiscv.lastStagePc[11] ;
+ wire \soc.core.VexRiscv.lastStagePc[12] ;
+ wire \soc.core.VexRiscv.lastStagePc[13] ;
+ wire \soc.core.VexRiscv.lastStagePc[14] ;
+ wire \soc.core.VexRiscv.lastStagePc[15] ;
+ wire \soc.core.VexRiscv.lastStagePc[16] ;
+ wire \soc.core.VexRiscv.lastStagePc[17] ;
+ wire \soc.core.VexRiscv.lastStagePc[18] ;
+ wire \soc.core.VexRiscv.lastStagePc[19] ;
+ wire \soc.core.VexRiscv.lastStagePc[20] ;
+ wire \soc.core.VexRiscv.lastStagePc[21] ;
+ wire \soc.core.VexRiscv.lastStagePc[22] ;
+ wire \soc.core.VexRiscv.lastStagePc[23] ;
+ wire \soc.core.VexRiscv.lastStagePc[24] ;
+ wire \soc.core.VexRiscv.lastStagePc[25] ;
+ wire \soc.core.VexRiscv.lastStagePc[26] ;
+ wire \soc.core.VexRiscv.lastStagePc[27] ;
+ wire \soc.core.VexRiscv.lastStagePc[28] ;
+ wire \soc.core.VexRiscv.lastStagePc[29] ;
+ wire \soc.core.VexRiscv.lastStagePc[2] ;
+ wire \soc.core.VexRiscv.lastStagePc[30] ;
+ wire \soc.core.VexRiscv.lastStagePc[31] ;
+ wire \soc.core.VexRiscv.lastStagePc[3] ;
+ wire \soc.core.VexRiscv.lastStagePc[4] ;
+ wire \soc.core.VexRiscv.lastStagePc[5] ;
+ wire \soc.core.VexRiscv.lastStagePc[6] ;
+ wire \soc.core.VexRiscv.lastStagePc[7] ;
+ wire \soc.core.VexRiscv.lastStagePc[8] ;
+ wire \soc.core.VexRiscv.lastStagePc[9] ;
+ wire \soc.core.VexRiscv.memory_arbitration_isValid ;
+ wire \soc.core.VexRiscv.memory_to_writeBack_MEMORY_ADDRESS_LOW[0] ;
+ wire \soc.core.VexRiscv.memory_to_writeBack_MEMORY_ADDRESS_LOW[1] ;
+ wire \soc.core.VexRiscv.memory_to_writeBack_MEMORY_ENABLE ;
+ wire \soc.core.VexRiscv.memory_to_writeBack_REGFILE_WRITE_DATA[0] ;
+ wire \soc.core.VexRiscv.memory_to_writeBack_REGFILE_WRITE_DATA[10] ;
+ wire \soc.core.VexRiscv.memory_to_writeBack_REGFILE_WRITE_DATA[11] ;
+ wire \soc.core.VexRiscv.memory_to_writeBack_REGFILE_WRITE_DATA[12] ;
+ wire \soc.core.VexRiscv.memory_to_writeBack_REGFILE_WRITE_DATA[13] ;
+ wire \soc.core.VexRiscv.memory_to_writeBack_REGFILE_WRITE_DATA[14] ;
+ wire \soc.core.VexRiscv.memory_to_writeBack_REGFILE_WRITE_DATA[15] ;
+ wire \soc.core.VexRiscv.memory_to_writeBack_REGFILE_WRITE_DATA[16] ;
+ wire \soc.core.VexRiscv.memory_to_writeBack_REGFILE_WRITE_DATA[17] ;
+ wire \soc.core.VexRiscv.memory_to_writeBack_REGFILE_WRITE_DATA[18] ;
+ wire \soc.core.VexRiscv.memory_to_writeBack_REGFILE_WRITE_DATA[19] ;
+ wire \soc.core.VexRiscv.memory_to_writeBack_REGFILE_WRITE_DATA[1] ;
+ wire \soc.core.VexRiscv.memory_to_writeBack_REGFILE_WRITE_DATA[20] ;
+ wire \soc.core.VexRiscv.memory_to_writeBack_REGFILE_WRITE_DATA[21] ;
+ wire \soc.core.VexRiscv.memory_to_writeBack_REGFILE_WRITE_DATA[22] ;
+ wire \soc.core.VexRiscv.memory_to_writeBack_REGFILE_WRITE_DATA[23] ;
+ wire \soc.core.VexRiscv.memory_to_writeBack_REGFILE_WRITE_DATA[24] ;
+ wire \soc.core.VexRiscv.memory_to_writeBack_REGFILE_WRITE_DATA[25] ;
+ wire \soc.core.VexRiscv.memory_to_writeBack_REGFILE_WRITE_DATA[26] ;
+ wire \soc.core.VexRiscv.memory_to_writeBack_REGFILE_WRITE_DATA[27] ;
+ wire \soc.core.VexRiscv.memory_to_writeBack_REGFILE_WRITE_DATA[28] ;
+ wire \soc.core.VexRiscv.memory_to_writeBack_REGFILE_WRITE_DATA[29] ;
+ wire \soc.core.VexRiscv.memory_to_writeBack_REGFILE_WRITE_DATA[2] ;
+ wire \soc.core.VexRiscv.memory_to_writeBack_REGFILE_WRITE_DATA[30] ;
+ wire \soc.core.VexRiscv.memory_to_writeBack_REGFILE_WRITE_DATA[31] ;
+ wire \soc.core.VexRiscv.memory_to_writeBack_REGFILE_WRITE_DATA[3] ;
+ wire \soc.core.VexRiscv.memory_to_writeBack_REGFILE_WRITE_DATA[4] ;
+ wire \soc.core.VexRiscv.memory_to_writeBack_REGFILE_WRITE_DATA[5] ;
+ wire \soc.core.VexRiscv.memory_to_writeBack_REGFILE_WRITE_DATA[6] ;
+ wire \soc.core.VexRiscv.memory_to_writeBack_REGFILE_WRITE_DATA[7] ;
+ wire \soc.core.VexRiscv.memory_to_writeBack_REGFILE_WRITE_DATA[8] ;
+ wire \soc.core.VexRiscv.memory_to_writeBack_REGFILE_WRITE_DATA[9] ;
+ wire \soc.core.VexRiscv.when_DebugPlugin_l260 ;
+ wire \soc.core.VexRiscv.when_DebugPlugin_l260_1 ;
+ wire \soc.core.VexRiscv.when_DebugPlugin_l261 ;
+ wire \soc.core.VexRiscv.when_DebugPlugin_l261_1 ;
+ wire \soc.core.VexRiscv.when_DebugPlugin_l264 ;
+ wire \soc.core.VexRiscv.when_DebugPlugin_l264_1 ;
+ wire \soc.core.bus_ack ;
+ wire \soc.core.bus_dat_r[0] ;
+ wire \soc.core.bus_dat_r[10] ;
+ wire \soc.core.bus_dat_r[11] ;
+ wire \soc.core.bus_dat_r[12] ;
+ wire \soc.core.bus_dat_r[13] ;
+ wire \soc.core.bus_dat_r[14] ;
+ wire \soc.core.bus_dat_r[15] ;
+ wire \soc.core.bus_dat_r[16] ;
+ wire \soc.core.bus_dat_r[17] ;
+ wire \soc.core.bus_dat_r[18] ;
+ wire \soc.core.bus_dat_r[19] ;
+ wire \soc.core.bus_dat_r[1] ;
+ wire \soc.core.bus_dat_r[20] ;
+ wire \soc.core.bus_dat_r[21] ;
+ wire \soc.core.bus_dat_r[22] ;
+ wire \soc.core.bus_dat_r[23] ;
+ wire \soc.core.bus_dat_r[24] ;
+ wire \soc.core.bus_dat_r[25] ;
+ wire \soc.core.bus_dat_r[26] ;
+ wire \soc.core.bus_dat_r[27] ;
+ wire \soc.core.bus_dat_r[28] ;
+ wire \soc.core.bus_dat_r[29] ;
+ wire \soc.core.bus_dat_r[2] ;
+ wire \soc.core.bus_dat_r[30] ;
+ wire \soc.core.bus_dat_r[31] ;
+ wire \soc.core.bus_dat_r[3] ;
+ wire \soc.core.bus_dat_r[4] ;
+ wire \soc.core.bus_dat_r[5] ;
+ wire \soc.core.bus_dat_r[6] ;
+ wire \soc.core.bus_dat_r[7] ;
+ wire \soc.core.bus_dat_r[8] ;
+ wire \soc.core.bus_dat_r[9] ;
+ wire \soc.core.count[0] ;
+ wire \soc.core.count[10] ;
+ wire \soc.core.count[11] ;
+ wire \soc.core.count[12] ;
+ wire \soc.core.count[13] ;
+ wire \soc.core.count[14] ;
+ wire \soc.core.count[15] ;
+ wire \soc.core.count[16] ;
+ wire \soc.core.count[17] ;
+ wire \soc.core.count[18] ;
+ wire \soc.core.count[19] ;
+ wire \soc.core.count[1] ;
+ wire \soc.core.count[2] ;
+ wire \soc.core.count[3] ;
+ wire \soc.core.count[4] ;
+ wire \soc.core.count[5] ;
+ wire \soc.core.count[6] ;
+ wire \soc.core.count[7] ;
+ wire \soc.core.count[8] ;
+ wire \soc.core.count[9] ;
+ wire \soc.core.dbg_uart_address[0] ;
+ wire \soc.core.dbg_uart_address[10] ;
+ wire \soc.core.dbg_uart_address[11] ;
+ wire \soc.core.dbg_uart_address[12] ;
+ wire \soc.core.dbg_uart_address[13] ;
+ wire \soc.core.dbg_uart_address[14] ;
+ wire \soc.core.dbg_uart_address[15] ;
+ wire \soc.core.dbg_uart_address[16] ;
+ wire \soc.core.dbg_uart_address[17] ;
+ wire \soc.core.dbg_uart_address[18] ;
+ wire \soc.core.dbg_uart_address[19] ;
+ wire \soc.core.dbg_uart_address[1] ;
+ wire \soc.core.dbg_uart_address[20] ;
+ wire \soc.core.dbg_uart_address[21] ;
+ wire \soc.core.dbg_uart_address[22] ;
+ wire \soc.core.dbg_uart_address[23] ;
+ wire \soc.core.dbg_uart_address[24] ;
+ wire \soc.core.dbg_uart_address[25] ;
+ wire \soc.core.dbg_uart_address[26] ;
+ wire \soc.core.dbg_uart_address[27] ;
+ wire \soc.core.dbg_uart_address[28] ;
+ wire \soc.core.dbg_uart_address[29] ;
+ wire \soc.core.dbg_uart_address[2] ;
+ wire \soc.core.dbg_uart_address[3] ;
+ wire \soc.core.dbg_uart_address[4] ;
+ wire \soc.core.dbg_uart_address[5] ;
+ wire \soc.core.dbg_uart_address[6] ;
+ wire \soc.core.dbg_uart_address[7] ;
+ wire \soc.core.dbg_uart_address[8] ;
+ wire \soc.core.dbg_uart_address[9] ;
+ wire \soc.core.dbg_uart_bytes_count[0] ;
+ wire \soc.core.dbg_uart_bytes_count[1] ;
+ wire \soc.core.dbg_uart_cmd[0] ;
+ wire \soc.core.dbg_uart_cmd[1] ;
+ wire \soc.core.dbg_uart_cmd[2] ;
+ wire \soc.core.dbg_uart_cmd[3] ;
+ wire \soc.core.dbg_uart_cmd[4] ;
+ wire \soc.core.dbg_uart_cmd[5] ;
+ wire \soc.core.dbg_uart_cmd[6] ;
+ wire \soc.core.dbg_uart_cmd[7] ;
+ wire \soc.core.dbg_uart_count[0] ;
+ wire \soc.core.dbg_uart_count[10] ;
+ wire \soc.core.dbg_uart_count[11] ;
+ wire \soc.core.dbg_uart_count[12] ;
+ wire \soc.core.dbg_uart_count[13] ;
+ wire \soc.core.dbg_uart_count[14] ;
+ wire \soc.core.dbg_uart_count[15] ;
+ wire \soc.core.dbg_uart_count[16] ;
+ wire \soc.core.dbg_uart_count[17] ;
+ wire \soc.core.dbg_uart_count[18] ;
+ wire \soc.core.dbg_uart_count[19] ;
+ wire \soc.core.dbg_uart_count[1] ;
+ wire \soc.core.dbg_uart_count[2] ;
+ wire \soc.core.dbg_uart_count[3] ;
+ wire \soc.core.dbg_uart_count[4] ;
+ wire \soc.core.dbg_uart_count[5] ;
+ wire \soc.core.dbg_uart_count[6] ;
+ wire \soc.core.dbg_uart_count[7] ;
+ wire \soc.core.dbg_uart_count[8] ;
+ wire \soc.core.dbg_uart_count[9] ;
+ wire \soc.core.dbg_uart_data[0] ;
+ wire \soc.core.dbg_uart_data[10] ;
+ wire \soc.core.dbg_uart_data[11] ;
+ wire \soc.core.dbg_uart_data[12] ;
+ wire \soc.core.dbg_uart_data[13] ;
+ wire \soc.core.dbg_uart_data[14] ;
+ wire \soc.core.dbg_uart_data[15] ;
+ wire \soc.core.dbg_uart_data[16] ;
+ wire \soc.core.dbg_uart_data[17] ;
+ wire \soc.core.dbg_uart_data[18] ;
+ wire \soc.core.dbg_uart_data[19] ;
+ wire \soc.core.dbg_uart_data[1] ;
+ wire \soc.core.dbg_uart_data[20] ;
+ wire \soc.core.dbg_uart_data[21] ;
+ wire \soc.core.dbg_uart_data[22] ;
+ wire \soc.core.dbg_uart_data[23] ;
+ wire \soc.core.dbg_uart_data[24] ;
+ wire \soc.core.dbg_uart_data[25] ;
+ wire \soc.core.dbg_uart_data[26] ;
+ wire \soc.core.dbg_uart_data[27] ;
+ wire \soc.core.dbg_uart_data[28] ;
+ wire \soc.core.dbg_uart_data[29] ;
+ wire \soc.core.dbg_uart_data[2] ;
+ wire \soc.core.dbg_uart_data[30] ;
+ wire \soc.core.dbg_uart_data[31] ;
+ wire \soc.core.dbg_uart_data[3] ;
+ wire \soc.core.dbg_uart_data[4] ;
+ wire \soc.core.dbg_uart_data[5] ;
+ wire \soc.core.dbg_uart_data[6] ;
+ wire \soc.core.dbg_uart_data[7] ;
+ wire \soc.core.dbg_uart_data[8] ;
+ wire \soc.core.dbg_uart_data[9] ;
+ wire \soc.core.dbg_uart_dbg_uart_tx ;
+ wire \soc.core.dbg_uart_incr ;
+ wire \soc.core.dbg_uart_length[0] ;
+ wire \soc.core.dbg_uart_length[1] ;
+ wire \soc.core.dbg_uart_length[2] ;
+ wire \soc.core.dbg_uart_length[3] ;
+ wire \soc.core.dbg_uart_length[4] ;
+ wire \soc.core.dbg_uart_length[5] ;
+ wire \soc.core.dbg_uart_length[6] ;
+ wire \soc.core.dbg_uart_length[7] ;
+ wire \soc.core.dbg_uart_rx_count[0] ;
+ wire \soc.core.dbg_uart_rx_count[1] ;
+ wire \soc.core.dbg_uart_rx_count[2] ;
+ wire \soc.core.dbg_uart_rx_count[3] ;
+ wire \soc.core.dbg_uart_rx_data[0] ;
+ wire \soc.core.dbg_uart_rx_data[1] ;
+ wire \soc.core.dbg_uart_rx_data[2] ;
+ wire \soc.core.dbg_uart_rx_data[3] ;
+ wire \soc.core.dbg_uart_rx_data[4] ;
+ wire \soc.core.dbg_uart_rx_data[5] ;
+ wire \soc.core.dbg_uart_rx_data[6] ;
+ wire \soc.core.dbg_uart_rx_data[7] ;
+ wire \soc.core.dbg_uart_rx_phase[0] ;
+ wire \soc.core.dbg_uart_rx_phase[10] ;
+ wire \soc.core.dbg_uart_rx_phase[11] ;
+ wire \soc.core.dbg_uart_rx_phase[12] ;
+ wire \soc.core.dbg_uart_rx_phase[13] ;
+ wire \soc.core.dbg_uart_rx_phase[14] ;
+ wire \soc.core.dbg_uart_rx_phase[15] ;
+ wire \soc.core.dbg_uart_rx_phase[16] ;
+ wire \soc.core.dbg_uart_rx_phase[17] ;
+ wire \soc.core.dbg_uart_rx_phase[18] ;
+ wire \soc.core.dbg_uart_rx_phase[19] ;
+ wire \soc.core.dbg_uart_rx_phase[1] ;
+ wire \soc.core.dbg_uart_rx_phase[20] ;
+ wire \soc.core.dbg_uart_rx_phase[21] ;
+ wire \soc.core.dbg_uart_rx_phase[22] ;
+ wire \soc.core.dbg_uart_rx_phase[23] ;
+ wire \soc.core.dbg_uart_rx_phase[24] ;
+ wire \soc.core.dbg_uart_rx_phase[25] ;
+ wire \soc.core.dbg_uart_rx_phase[26] ;
+ wire \soc.core.dbg_uart_rx_phase[27] ;
+ wire \soc.core.dbg_uart_rx_phase[28] ;
+ wire \soc.core.dbg_uart_rx_phase[29] ;
+ wire \soc.core.dbg_uart_rx_phase[2] ;
+ wire \soc.core.dbg_uart_rx_phase[30] ;
+ wire \soc.core.dbg_uart_rx_phase[31] ;
+ wire \soc.core.dbg_uart_rx_phase[3] ;
+ wire \soc.core.dbg_uart_rx_phase[4] ;
+ wire \soc.core.dbg_uart_rx_phase[5] ;
+ wire \soc.core.dbg_uart_rx_phase[6] ;
+ wire \soc.core.dbg_uart_rx_phase[7] ;
+ wire \soc.core.dbg_uart_rx_phase[8] ;
+ wire \soc.core.dbg_uart_rx_phase[9] ;
+ wire \soc.core.dbg_uart_rx_rx_d ;
+ wire \soc.core.dbg_uart_rx_tick ;
+ wire \soc.core.dbg_uart_tx_count[0] ;
+ wire \soc.core.dbg_uart_tx_count[1] ;
+ wire \soc.core.dbg_uart_tx_count[2] ;
+ wire \soc.core.dbg_uart_tx_count[3] ;
+ wire \soc.core.dbg_uart_tx_data[0] ;
+ wire \soc.core.dbg_uart_tx_data[1] ;
+ wire \soc.core.dbg_uart_tx_data[2] ;
+ wire \soc.core.dbg_uart_tx_data[3] ;
+ wire \soc.core.dbg_uart_tx_data[4] ;
+ wire \soc.core.dbg_uart_tx_data[5] ;
+ wire \soc.core.dbg_uart_tx_data[6] ;
+ wire \soc.core.dbg_uart_tx_data[7] ;
+ wire \soc.core.dbg_uart_tx_phase[0] ;
+ wire \soc.core.dbg_uart_tx_phase[10] ;
+ wire \soc.core.dbg_uart_tx_phase[11] ;
+ wire \soc.core.dbg_uart_tx_phase[12] ;
+ wire \soc.core.dbg_uart_tx_phase[13] ;
+ wire \soc.core.dbg_uart_tx_phase[14] ;
+ wire \soc.core.dbg_uart_tx_phase[15] ;
+ wire \soc.core.dbg_uart_tx_phase[16] ;
+ wire \soc.core.dbg_uart_tx_phase[17] ;
+ wire \soc.core.dbg_uart_tx_phase[18] ;
+ wire \soc.core.dbg_uart_tx_phase[19] ;
+ wire \soc.core.dbg_uart_tx_phase[1] ;
+ wire \soc.core.dbg_uart_tx_phase[20] ;
+ wire \soc.core.dbg_uart_tx_phase[21] ;
+ wire \soc.core.dbg_uart_tx_phase[22] ;
+ wire \soc.core.dbg_uart_tx_phase[23] ;
+ wire \soc.core.dbg_uart_tx_phase[24] ;
+ wire \soc.core.dbg_uart_tx_phase[25] ;
+ wire \soc.core.dbg_uart_tx_phase[26] ;
+ wire \soc.core.dbg_uart_tx_phase[27] ;
+ wire \soc.core.dbg_uart_tx_phase[28] ;
+ wire \soc.core.dbg_uart_tx_phase[29] ;
+ wire \soc.core.dbg_uart_tx_phase[2] ;
+ wire \soc.core.dbg_uart_tx_phase[30] ;
+ wire \soc.core.dbg_uart_tx_phase[31] ;
+ wire \soc.core.dbg_uart_tx_phase[3] ;
+ wire \soc.core.dbg_uart_tx_phase[4] ;
+ wire \soc.core.dbg_uart_tx_phase[5] ;
+ wire \soc.core.dbg_uart_tx_phase[6] ;
+ wire \soc.core.dbg_uart_tx_phase[7] ;
+ wire \soc.core.dbg_uart_tx_phase[8] ;
+ wire \soc.core.dbg_uart_tx_phase[9] ;
+ wire \soc.core.dbg_uart_tx_tick ;
+ wire \soc.core.dbg_uart_words_count[0] ;
+ wire \soc.core.dbg_uart_words_count[1] ;
+ wire \soc.core.dbg_uart_words_count[2] ;
+ wire \soc.core.dbg_uart_words_count[3] ;
+ wire \soc.core.dbg_uart_words_count[4] ;
+ wire \soc.core.dbg_uart_words_count[5] ;
+ wire \soc.core.dbg_uart_words_count[6] ;
+ wire \soc.core.dbg_uart_words_count[7] ;
+ wire \soc.core.debug_in ;
+ wire \soc.core.debug_mode_storage ;
+ wire \soc.core.debug_oeb_storage ;
+ wire \soc.core.flash_clk ;
+ wire \soc.core.flash_cs_n ;
+ wire \soc.core.flash_io0_di ;
+ wire \soc.core.flash_io0_do ;
+ wire \soc.core.flash_io0_oeb ;
+ wire \soc.core.flash_io1_di ;
+ wire \soc.core.flash_io2_di ;
+ wire \soc.core.flash_io3_di ;
+ wire \soc.core.gpio_ien_storage ;
+ wire \soc.core.gpio_mode0_storage ;
+ wire \soc.core.gpio_mode1_storage ;
+ wire \soc.core.gpio_oe_storage ;
+ wire \soc.core.gpioin0_enable_storage ;
+ wire \soc.core.gpioin0_gpioin0_edge_storage ;
+ wire \soc.core.gpioin0_gpioin0_in_pads_n_d ;
+ wire \soc.core.gpioin0_gpioin0_irq ;
+ wire \soc.core.gpioin0_gpioin0_mode_storage ;
+ wire \soc.core.gpioin0_gpioin0_pending ;
+ wire \soc.core.gpioin0_gpioin0_trigger_d ;
+ wire \soc.core.gpioin0_pending_r ;
+ wire \soc.core.gpioin0_pending_re ;
+ wire \soc.core.gpioin1_enable_storage ;
+ wire \soc.core.gpioin1_gpioin1_edge_storage ;
+ wire \soc.core.gpioin1_gpioin1_in_pads_n_d ;
+ wire \soc.core.gpioin1_gpioin1_irq ;
+ wire \soc.core.gpioin1_gpioin1_mode_storage ;
+ wire \soc.core.gpioin1_gpioin1_pending ;
+ wire \soc.core.gpioin1_gpioin1_trigger_d ;
+ wire \soc.core.gpioin1_pending_r ;
+ wire \soc.core.gpioin1_pending_re ;
+ wire \soc.core.gpioin2_enable_storage ;
+ wire \soc.core.gpioin2_gpioin2_edge_storage ;
+ wire \soc.core.gpioin2_gpioin2_in_pads_n_d ;
+ wire \soc.core.gpioin2_gpioin2_irq ;
+ wire \soc.core.gpioin2_gpioin2_mode_storage ;
+ wire \soc.core.gpioin2_gpioin2_pending ;
+ wire \soc.core.gpioin2_gpioin2_trigger_d ;
+ wire \soc.core.gpioin2_pending_r ;
+ wire \soc.core.gpioin2_pending_re ;
+ wire \soc.core.gpioin3_enable_storage ;
+ wire \soc.core.gpioin3_gpioin3_edge_storage ;
+ wire \soc.core.gpioin3_gpioin3_in_pads_n_d ;
+ wire \soc.core.gpioin3_gpioin3_irq ;
+ wire \soc.core.gpioin3_gpioin3_mode_storage ;
+ wire \soc.core.gpioin3_gpioin3_pending ;
+ wire \soc.core.gpioin3_gpioin3_trigger_d ;
+ wire \soc.core.gpioin3_pending_r ;
+ wire \soc.core.gpioin3_pending_re ;
+ wire \soc.core.gpioin4_enable_storage ;
+ wire \soc.core.gpioin4_gpioin4_edge_storage ;
+ wire \soc.core.gpioin4_gpioin4_in_pads_n_d ;
+ wire \soc.core.gpioin4_gpioin4_irq ;
+ wire \soc.core.gpioin4_gpioin4_mode_storage ;
+ wire \soc.core.gpioin4_gpioin4_pending ;
+ wire \soc.core.gpioin4_gpioin4_trigger_d ;
+ wire \soc.core.gpioin4_pending_r ;
+ wire \soc.core.gpioin4_pending_re ;
+ wire \soc.core.gpioin5_enable_storage ;
+ wire \soc.core.gpioin5_gpioin5_edge_storage ;
+ wire \soc.core.gpioin5_gpioin5_in_pads_n_d ;
+ wire \soc.core.gpioin5_gpioin5_irq ;
+ wire \soc.core.gpioin5_gpioin5_mode_storage ;
+ wire \soc.core.gpioin5_gpioin5_pending ;
+ wire \soc.core.gpioin5_gpioin5_trigger_d ;
+ wire \soc.core.gpioin5_pending_r ;
+ wire \soc.core.gpioin5_pending_re ;
+ wire \soc.core.grant[0] ;
+ wire \soc.core.grant[1] ;
+ wire \soc.core.hk_ack ;
+ wire \soc.core.hk_cyc ;
+ wire \soc.core.hk_dat_i[0] ;
+ wire \soc.core.hk_dat_i[10] ;
+ wire \soc.core.hk_dat_i[11] ;
+ wire \soc.core.hk_dat_i[12] ;
+ wire \soc.core.hk_dat_i[13] ;
+ wire \soc.core.hk_dat_i[14] ;
+ wire \soc.core.hk_dat_i[15] ;
+ wire \soc.core.hk_dat_i[16] ;
+ wire \soc.core.hk_dat_i[17] ;
+ wire \soc.core.hk_dat_i[18] ;
+ wire \soc.core.hk_dat_i[19] ;
+ wire \soc.core.hk_dat_i[1] ;
+ wire \soc.core.hk_dat_i[20] ;
+ wire \soc.core.hk_dat_i[21] ;
+ wire \soc.core.hk_dat_i[22] ;
+ wire \soc.core.hk_dat_i[23] ;
+ wire \soc.core.hk_dat_i[24] ;
+ wire \soc.core.hk_dat_i[25] ;
+ wire \soc.core.hk_dat_i[26] ;
+ wire \soc.core.hk_dat_i[27] ;
+ wire \soc.core.hk_dat_i[28] ;
+ wire \soc.core.hk_dat_i[29] ;
+ wire \soc.core.hk_dat_i[2] ;
+ wire \soc.core.hk_dat_i[30] ;
+ wire \soc.core.hk_dat_i[31] ;
+ wire \soc.core.hk_dat_i[3] ;
+ wire \soc.core.hk_dat_i[4] ;
+ wire \soc.core.hk_dat_i[5] ;
+ wire \soc.core.hk_dat_i[6] ;
+ wire \soc.core.hk_dat_i[7] ;
+ wire \soc.core.hk_dat_i[8] ;
+ wire \soc.core.hk_dat_i[9] ;
+ wire \soc.core.int_rst ;
+ wire \soc.core.interface0_bank_bus_dat_r[0] ;
+ wire \soc.core.interface0_bank_bus_dat_r[10] ;
+ wire \soc.core.interface0_bank_bus_dat_r[11] ;
+ wire \soc.core.interface0_bank_bus_dat_r[12] ;
+ wire \soc.core.interface0_bank_bus_dat_r[13] ;
+ wire \soc.core.interface0_bank_bus_dat_r[14] ;
+ wire \soc.core.interface0_bank_bus_dat_r[15] ;
+ wire \soc.core.interface0_bank_bus_dat_r[16] ;
+ wire \soc.core.interface0_bank_bus_dat_r[17] ;
+ wire \soc.core.interface0_bank_bus_dat_r[18] ;
+ wire \soc.core.interface0_bank_bus_dat_r[19] ;
+ wire \soc.core.interface0_bank_bus_dat_r[1] ;
+ wire \soc.core.interface0_bank_bus_dat_r[20] ;
+ wire \soc.core.interface0_bank_bus_dat_r[21] ;
+ wire \soc.core.interface0_bank_bus_dat_r[22] ;
+ wire \soc.core.interface0_bank_bus_dat_r[23] ;
+ wire \soc.core.interface0_bank_bus_dat_r[24] ;
+ wire \soc.core.interface0_bank_bus_dat_r[25] ;
+ wire \soc.core.interface0_bank_bus_dat_r[26] ;
+ wire \soc.core.interface0_bank_bus_dat_r[27] ;
+ wire \soc.core.interface0_bank_bus_dat_r[28] ;
+ wire \soc.core.interface0_bank_bus_dat_r[29] ;
+ wire \soc.core.interface0_bank_bus_dat_r[2] ;
+ wire \soc.core.interface0_bank_bus_dat_r[30] ;
+ wire \soc.core.interface0_bank_bus_dat_r[31] ;
+ wire \soc.core.interface0_bank_bus_dat_r[3] ;
+ wire \soc.core.interface0_bank_bus_dat_r[4] ;
+ wire \soc.core.interface0_bank_bus_dat_r[5] ;
+ wire \soc.core.interface0_bank_bus_dat_r[6] ;
+ wire \soc.core.interface0_bank_bus_dat_r[7] ;
+ wire \soc.core.interface0_bank_bus_dat_r[8] ;
+ wire \soc.core.interface0_bank_bus_dat_r[9] ;
+ wire \soc.core.interface10_bank_bus_dat_r[0] ;
+ wire \soc.core.interface10_bank_bus_dat_r[10] ;
+ wire \soc.core.interface10_bank_bus_dat_r[11] ;
+ wire \soc.core.interface10_bank_bus_dat_r[12] ;
+ wire \soc.core.interface10_bank_bus_dat_r[13] ;
+ wire \soc.core.interface10_bank_bus_dat_r[14] ;
+ wire \soc.core.interface10_bank_bus_dat_r[15] ;
+ wire \soc.core.interface10_bank_bus_dat_r[16] ;
+ wire \soc.core.interface10_bank_bus_dat_r[17] ;
+ wire \soc.core.interface10_bank_bus_dat_r[18] ;
+ wire \soc.core.interface10_bank_bus_dat_r[19] ;
+ wire \soc.core.interface10_bank_bus_dat_r[1] ;
+ wire \soc.core.interface10_bank_bus_dat_r[20] ;
+ wire \soc.core.interface10_bank_bus_dat_r[21] ;
+ wire \soc.core.interface10_bank_bus_dat_r[22] ;
+ wire \soc.core.interface10_bank_bus_dat_r[23] ;
+ wire \soc.core.interface10_bank_bus_dat_r[24] ;
+ wire \soc.core.interface10_bank_bus_dat_r[25] ;
+ wire \soc.core.interface10_bank_bus_dat_r[26] ;
+ wire \soc.core.interface10_bank_bus_dat_r[27] ;
+ wire \soc.core.interface10_bank_bus_dat_r[28] ;
+ wire \soc.core.interface10_bank_bus_dat_r[29] ;
+ wire \soc.core.interface10_bank_bus_dat_r[2] ;
+ wire \soc.core.interface10_bank_bus_dat_r[30] ;
+ wire \soc.core.interface10_bank_bus_dat_r[31] ;
+ wire \soc.core.interface10_bank_bus_dat_r[3] ;
+ wire \soc.core.interface10_bank_bus_dat_r[4] ;
+ wire \soc.core.interface10_bank_bus_dat_r[5] ;
+ wire \soc.core.interface10_bank_bus_dat_r[6] ;
+ wire \soc.core.interface10_bank_bus_dat_r[7] ;
+ wire \soc.core.interface10_bank_bus_dat_r[8] ;
+ wire \soc.core.interface10_bank_bus_dat_r[9] ;
+ wire \soc.core.interface11_bank_bus_dat_r[0] ;
+ wire \soc.core.interface11_bank_bus_dat_r[1] ;
+ wire \soc.core.interface11_bank_bus_dat_r[2] ;
+ wire \soc.core.interface11_bank_bus_dat_r[3] ;
+ wire \soc.core.interface11_bank_bus_dat_r[4] ;
+ wire \soc.core.interface11_bank_bus_dat_r[5] ;
+ wire \soc.core.interface11_bank_bus_dat_r[6] ;
+ wire \soc.core.interface11_bank_bus_dat_r[7] ;
+ wire \soc.core.interface12_bank_bus_dat_r[0] ;
+ wire \soc.core.interface13_bank_bus_dat_r[0] ;
+ wire \soc.core.interface14_bank_bus_dat_r[0] ;
+ wire \soc.core.interface15_bank_bus_dat_r[0] ;
+ wire \soc.core.interface16_bank_bus_dat_r[0] ;
+ wire \soc.core.interface17_bank_bus_dat_r[0] ;
+ wire \soc.core.interface18_bank_bus_dat_r[0] ;
+ wire \soc.core.interface19_bank_bus_dat_r[0] ;
+ wire \soc.core.interface19_bank_bus_dat_r[1] ;
+ wire \soc.core.interface19_bank_bus_dat_r[2] ;
+ wire \soc.core.interface1_bank_bus_dat_r[0] ;
+ wire \soc.core.interface2_bank_bus_dat_r[0] ;
+ wire \soc.core.interface3_bank_bus_dat_r[0] ;
+ wire \soc.core.interface3_bank_bus_dat_r[10] ;
+ wire \soc.core.interface3_bank_bus_dat_r[11] ;
+ wire \soc.core.interface3_bank_bus_dat_r[12] ;
+ wire \soc.core.interface3_bank_bus_dat_r[13] ;
+ wire \soc.core.interface3_bank_bus_dat_r[14] ;
+ wire \soc.core.interface3_bank_bus_dat_r[15] ;
+ wire \soc.core.interface3_bank_bus_dat_r[16] ;
+ wire \soc.core.interface3_bank_bus_dat_r[17] ;
+ wire \soc.core.interface3_bank_bus_dat_r[18] ;
+ wire \soc.core.interface3_bank_bus_dat_r[19] ;
+ wire \soc.core.interface3_bank_bus_dat_r[1] ;
+ wire \soc.core.interface3_bank_bus_dat_r[20] ;
+ wire \soc.core.interface3_bank_bus_dat_r[21] ;
+ wire \soc.core.interface3_bank_bus_dat_r[22] ;
+ wire \soc.core.interface3_bank_bus_dat_r[23] ;
+ wire \soc.core.interface3_bank_bus_dat_r[24] ;
+ wire \soc.core.interface3_bank_bus_dat_r[25] ;
+ wire \soc.core.interface3_bank_bus_dat_r[26] ;
+ wire \soc.core.interface3_bank_bus_dat_r[27] ;
+ wire \soc.core.interface3_bank_bus_dat_r[28] ;
+ wire \soc.core.interface3_bank_bus_dat_r[29] ;
+ wire \soc.core.interface3_bank_bus_dat_r[2] ;
+ wire \soc.core.interface3_bank_bus_dat_r[30] ;
+ wire \soc.core.interface3_bank_bus_dat_r[31] ;
+ wire \soc.core.interface3_bank_bus_dat_r[3] ;
+ wire \soc.core.interface3_bank_bus_dat_r[4] ;
+ wire \soc.core.interface3_bank_bus_dat_r[5] ;
+ wire \soc.core.interface3_bank_bus_dat_r[6] ;
+ wire \soc.core.interface3_bank_bus_dat_r[7] ;
+ wire \soc.core.interface3_bank_bus_dat_r[8] ;
+ wire \soc.core.interface3_bank_bus_dat_r[9] ;
+ wire \soc.core.interface4_bank_bus_dat_r[0] ;
+ wire \soc.core.interface4_bank_bus_dat_r[1] ;
+ wire \soc.core.interface4_bank_bus_dat_r[2] ;
+ wire \soc.core.interface4_bank_bus_dat_r[3] ;
+ wire \soc.core.interface4_bank_bus_dat_r[4] ;
+ wire \soc.core.interface4_bank_bus_dat_r[5] ;
+ wire \soc.core.interface4_bank_bus_dat_r[6] ;
+ wire \soc.core.interface4_bank_bus_dat_r[7] ;
+ wire \soc.core.interface5_bank_bus_dat_r[0] ;
+ wire \soc.core.interface6_bank_bus_dat_r[0] ;
+ wire \soc.core.interface6_bank_bus_dat_r[10] ;
+ wire \soc.core.interface6_bank_bus_dat_r[11] ;
+ wire \soc.core.interface6_bank_bus_dat_r[12] ;
+ wire \soc.core.interface6_bank_bus_dat_r[13] ;
+ wire \soc.core.interface6_bank_bus_dat_r[14] ;
+ wire \soc.core.interface6_bank_bus_dat_r[15] ;
+ wire \soc.core.interface6_bank_bus_dat_r[16] ;
+ wire \soc.core.interface6_bank_bus_dat_r[17] ;
+ wire \soc.core.interface6_bank_bus_dat_r[18] ;
+ wire \soc.core.interface6_bank_bus_dat_r[19] ;
+ wire \soc.core.interface6_bank_bus_dat_r[1] ;
+ wire \soc.core.interface6_bank_bus_dat_r[20] ;
+ wire \soc.core.interface6_bank_bus_dat_r[21] ;
+ wire \soc.core.interface6_bank_bus_dat_r[22] ;
+ wire \soc.core.interface6_bank_bus_dat_r[23] ;
+ wire \soc.core.interface6_bank_bus_dat_r[24] ;
+ wire \soc.core.interface6_bank_bus_dat_r[25] ;
+ wire \soc.core.interface6_bank_bus_dat_r[26] ;
+ wire \soc.core.interface6_bank_bus_dat_r[27] ;
+ wire \soc.core.interface6_bank_bus_dat_r[28] ;
+ wire \soc.core.interface6_bank_bus_dat_r[29] ;
+ wire \soc.core.interface6_bank_bus_dat_r[2] ;
+ wire \soc.core.interface6_bank_bus_dat_r[30] ;
+ wire \soc.core.interface6_bank_bus_dat_r[31] ;
+ wire \soc.core.interface6_bank_bus_dat_r[3] ;
+ wire \soc.core.interface6_bank_bus_dat_r[4] ;
+ wire \soc.core.interface6_bank_bus_dat_r[5] ;
+ wire \soc.core.interface6_bank_bus_dat_r[6] ;
+ wire \soc.core.interface6_bank_bus_dat_r[7] ;
+ wire \soc.core.interface6_bank_bus_dat_r[8] ;
+ wire \soc.core.interface6_bank_bus_dat_r[9] ;
+ wire \soc.core.interface7_bank_bus_dat_r[0] ;
+ wire \soc.core.interface8_bank_bus_dat_r[0] ;
+ wire \soc.core.interface9_bank_bus_dat_r[0] ;
+ wire \soc.core.interface9_bank_bus_dat_r[10] ;
+ wire \soc.core.interface9_bank_bus_dat_r[11] ;
+ wire \soc.core.interface9_bank_bus_dat_r[12] ;
+ wire \soc.core.interface9_bank_bus_dat_r[13] ;
+ wire \soc.core.interface9_bank_bus_dat_r[14] ;
+ wire \soc.core.interface9_bank_bus_dat_r[15] ;
+ wire \soc.core.interface9_bank_bus_dat_r[16] ;
+ wire \soc.core.interface9_bank_bus_dat_r[1] ;
+ wire \soc.core.interface9_bank_bus_dat_r[2] ;
+ wire \soc.core.interface9_bank_bus_dat_r[3] ;
+ wire \soc.core.interface9_bank_bus_dat_r[4] ;
+ wire \soc.core.interface9_bank_bus_dat_r[5] ;
+ wire \soc.core.interface9_bank_bus_dat_r[6] ;
+ wire \soc.core.interface9_bank_bus_dat_r[7] ;
+ wire \soc.core.interface9_bank_bus_dat_r[8] ;
+ wire \soc.core.interface9_bank_bus_dat_r[9] ;
+ wire \soc.core.la_ien_storage[0] ;
+ wire \soc.core.la_ien_storage[10] ;
+ wire \soc.core.la_ien_storage[11] ;
+ wire \soc.core.la_ien_storage[12] ;
+ wire \soc.core.la_ien_storage[13] ;
+ wire \soc.core.la_ien_storage[14] ;
+ wire \soc.core.la_ien_storage[15] ;
+ wire \soc.core.la_ien_storage[16] ;
+ wire \soc.core.la_ien_storage[17] ;
+ wire \soc.core.la_ien_storage[18] ;
+ wire \soc.core.la_ien_storage[19] ;
+ wire \soc.core.la_ien_storage[1] ;
+ wire \soc.core.la_ien_storage[20] ;
+ wire \soc.core.la_ien_storage[21] ;
+ wire \soc.core.la_ien_storage[22] ;
+ wire \soc.core.la_ien_storage[23] ;
+ wire \soc.core.la_ien_storage[24] ;
+ wire \soc.core.la_ien_storage[25] ;
+ wire \soc.core.la_ien_storage[26] ;
+ wire \soc.core.la_ien_storage[27] ;
+ wire \soc.core.la_ien_storage[28] ;
+ wire \soc.core.la_ien_storage[29] ;
+ wire \soc.core.la_ien_storage[2] ;
+ wire \soc.core.la_ien_storage[30] ;
+ wire \soc.core.la_ien_storage[31] ;
+ wire \soc.core.la_ien_storage[32] ;
+ wire \soc.core.la_ien_storage[33] ;
+ wire \soc.core.la_ien_storage[34] ;
+ wire \soc.core.la_ien_storage[35] ;
+ wire \soc.core.la_ien_storage[36] ;
+ wire \soc.core.la_ien_storage[37] ;
+ wire \soc.core.la_ien_storage[38] ;
+ wire \soc.core.la_ien_storage[39] ;
+ wire \soc.core.la_ien_storage[3] ;
+ wire \soc.core.la_ien_storage[40] ;
+ wire \soc.core.la_ien_storage[41] ;
+ wire \soc.core.la_ien_storage[42] ;
+ wire \soc.core.la_ien_storage[43] ;
+ wire \soc.core.la_ien_storage[44] ;
+ wire \soc.core.la_ien_storage[45] ;
+ wire \soc.core.la_ien_storage[46] ;
+ wire \soc.core.la_ien_storage[47] ;
+ wire \soc.core.la_ien_storage[48] ;
+ wire \soc.core.la_ien_storage[49] ;
+ wire \soc.core.la_ien_storage[4] ;
+ wire \soc.core.la_ien_storage[50] ;
+ wire \soc.core.la_ien_storage[51] ;
+ wire \soc.core.la_ien_storage[52] ;
+ wire \soc.core.la_ien_storage[53] ;
+ wire \soc.core.la_ien_storage[54] ;
+ wire \soc.core.la_ien_storage[55] ;
+ wire \soc.core.la_ien_storage[56] ;
+ wire \soc.core.la_ien_storage[57] ;
+ wire \soc.core.la_ien_storage[58] ;
+ wire \soc.core.la_ien_storage[59] ;
+ wire \soc.core.la_ien_storage[5] ;
+ wire \soc.core.la_ien_storage[60] ;
+ wire \soc.core.la_ien_storage[61] ;
+ wire \soc.core.la_ien_storage[62] ;
+ wire \soc.core.la_ien_storage[63] ;
+ wire \soc.core.la_ien_storage[6] ;
+ wire \soc.core.la_ien_storage[7] ;
+ wire \soc.core.la_ien_storage[8] ;
+ wire \soc.core.la_ien_storage[9] ;
+ wire \soc.core.la_oe_storage[0] ;
+ wire \soc.core.la_oe_storage[10] ;
+ wire \soc.core.la_oe_storage[11] ;
+ wire \soc.core.la_oe_storage[12] ;
+ wire \soc.core.la_oe_storage[13] ;
+ wire \soc.core.la_oe_storage[14] ;
+ wire \soc.core.la_oe_storage[15] ;
+ wire \soc.core.la_oe_storage[16] ;
+ wire \soc.core.la_oe_storage[17] ;
+ wire \soc.core.la_oe_storage[18] ;
+ wire \soc.core.la_oe_storage[19] ;
+ wire \soc.core.la_oe_storage[1] ;
+ wire \soc.core.la_oe_storage[20] ;
+ wire \soc.core.la_oe_storage[21] ;
+ wire \soc.core.la_oe_storage[22] ;
+ wire \soc.core.la_oe_storage[23] ;
+ wire \soc.core.la_oe_storage[24] ;
+ wire \soc.core.la_oe_storage[25] ;
+ wire \soc.core.la_oe_storage[26] ;
+ wire \soc.core.la_oe_storage[27] ;
+ wire \soc.core.la_oe_storage[28] ;
+ wire \soc.core.la_oe_storage[29] ;
+ wire \soc.core.la_oe_storage[2] ;
+ wire \soc.core.la_oe_storage[30] ;
+ wire \soc.core.la_oe_storage[31] ;
+ wire \soc.core.la_oe_storage[32] ;
+ wire \soc.core.la_oe_storage[33] ;
+ wire \soc.core.la_oe_storage[34] ;
+ wire \soc.core.la_oe_storage[35] ;
+ wire \soc.core.la_oe_storage[36] ;
+ wire \soc.core.la_oe_storage[37] ;
+ wire \soc.core.la_oe_storage[38] ;
+ wire \soc.core.la_oe_storage[39] ;
+ wire \soc.core.la_oe_storage[3] ;
+ wire \soc.core.la_oe_storage[40] ;
+ wire \soc.core.la_oe_storage[41] ;
+ wire \soc.core.la_oe_storage[42] ;
+ wire \soc.core.la_oe_storage[43] ;
+ wire \soc.core.la_oe_storage[44] ;
+ wire \soc.core.la_oe_storage[45] ;
+ wire \soc.core.la_oe_storage[46] ;
+ wire \soc.core.la_oe_storage[47] ;
+ wire \soc.core.la_oe_storage[48] ;
+ wire \soc.core.la_oe_storage[49] ;
+ wire \soc.core.la_oe_storage[4] ;
+ wire \soc.core.la_oe_storage[50] ;
+ wire \soc.core.la_oe_storage[51] ;
+ wire \soc.core.la_oe_storage[52] ;
+ wire \soc.core.la_oe_storage[53] ;
+ wire \soc.core.la_oe_storage[54] ;
+ wire \soc.core.la_oe_storage[55] ;
+ wire \soc.core.la_oe_storage[56] ;
+ wire \soc.core.la_oe_storage[57] ;
+ wire \soc.core.la_oe_storage[58] ;
+ wire \soc.core.la_oe_storage[59] ;
+ wire \soc.core.la_oe_storage[5] ;
+ wire \soc.core.la_oe_storage[60] ;
+ wire \soc.core.la_oe_storage[61] ;
+ wire \soc.core.la_oe_storage[62] ;
+ wire \soc.core.la_oe_storage[63] ;
+ wire \soc.core.la_oe_storage[6] ;
+ wire \soc.core.la_oe_storage[7] ;
+ wire \soc.core.la_oe_storage[8] ;
+ wire \soc.core.la_oe_storage[9] ;
+ wire \soc.core.la_out_storage[0] ;
+ wire \soc.core.la_out_storage[10] ;
+ wire \soc.core.la_out_storage[11] ;
+ wire \soc.core.la_out_storage[12] ;
+ wire \soc.core.la_out_storage[13] ;
+ wire \soc.core.la_out_storage[14] ;
+ wire \soc.core.la_out_storage[15] ;
+ wire \soc.core.la_out_storage[16] ;
+ wire \soc.core.la_out_storage[17] ;
+ wire \soc.core.la_out_storage[18] ;
+ wire \soc.core.la_out_storage[19] ;
+ wire \soc.core.la_out_storage[1] ;
+ wire \soc.core.la_out_storage[20] ;
+ wire \soc.core.la_out_storage[21] ;
+ wire \soc.core.la_out_storage[22] ;
+ wire \soc.core.la_out_storage[23] ;
+ wire \soc.core.la_out_storage[24] ;
+ wire \soc.core.la_out_storage[25] ;
+ wire \soc.core.la_out_storage[26] ;
+ wire \soc.core.la_out_storage[27] ;
+ wire \soc.core.la_out_storage[28] ;
+ wire \soc.core.la_out_storage[29] ;
+ wire \soc.core.la_out_storage[2] ;
+ wire \soc.core.la_out_storage[30] ;
+ wire \soc.core.la_out_storage[31] ;
+ wire \soc.core.la_out_storage[32] ;
+ wire \soc.core.la_out_storage[33] ;
+ wire \soc.core.la_out_storage[34] ;
+ wire \soc.core.la_out_storage[35] ;
+ wire \soc.core.la_out_storage[36] ;
+ wire \soc.core.la_out_storage[37] ;
+ wire \soc.core.la_out_storage[38] ;
+ wire \soc.core.la_out_storage[39] ;
+ wire \soc.core.la_out_storage[3] ;
+ wire \soc.core.la_out_storage[40] ;
+ wire \soc.core.la_out_storage[41] ;
+ wire \soc.core.la_out_storage[42] ;
+ wire \soc.core.la_out_storage[43] ;
+ wire \soc.core.la_out_storage[44] ;
+ wire \soc.core.la_out_storage[45] ;
+ wire \soc.core.la_out_storage[46] ;
+ wire \soc.core.la_out_storage[47] ;
+ wire \soc.core.la_out_storage[48] ;
+ wire \soc.core.la_out_storage[49] ;
+ wire \soc.core.la_out_storage[4] ;
+ wire \soc.core.la_out_storage[50] ;
+ wire \soc.core.la_out_storage[51] ;
+ wire \soc.core.la_out_storage[52] ;
+ wire \soc.core.la_out_storage[53] ;
+ wire \soc.core.la_out_storage[54] ;
+ wire \soc.core.la_out_storage[55] ;
+ wire \soc.core.la_out_storage[56] ;
+ wire \soc.core.la_out_storage[57] ;
+ wire \soc.core.la_out_storage[58] ;
+ wire \soc.core.la_out_storage[59] ;
+ wire \soc.core.la_out_storage[5] ;
+ wire \soc.core.la_out_storage[60] ;
+ wire \soc.core.la_out_storage[61] ;
+ wire \soc.core.la_out_storage[62] ;
+ wire \soc.core.la_out_storage[63] ;
+ wire \soc.core.la_out_storage[6] ;
+ wire \soc.core.la_out_storage[7] ;
+ wire \soc.core.la_out_storage[8] ;
+ wire \soc.core.la_out_storage[9] ;
+ wire \soc.core.litespi_grant ;
+ wire \soc.core.litespi_state[0] ;
+ wire \soc.core.litespi_state[1] ;
+ wire \soc.core.litespi_state[2] ;
+ wire \soc.core.litespi_state[3] ;
+ wire \soc.core.litespiphy_state[0] ;
+ wire \soc.core.litespiphy_state[1] ;
+ wire \soc.core.memdat_1[0] ;
+ wire \soc.core.memdat_1[1] ;
+ wire \soc.core.memdat_1[2] ;
+ wire \soc.core.memdat_1[3] ;
+ wire \soc.core.memdat_1[4] ;
+ wire \soc.core.memdat_1[5] ;
+ wire \soc.core.memdat_1[6] ;
+ wire \soc.core.memdat_1[7] ;
+ wire \soc.core.memdat_3[0] ;
+ wire \soc.core.memdat_3[1] ;
+ wire \soc.core.memdat_3[2] ;
+ wire \soc.core.memdat_3[3] ;
+ wire \soc.core.memdat_3[4] ;
+ wire \soc.core.memdat_3[5] ;
+ wire \soc.core.memdat_3[6] ;
+ wire \soc.core.memdat_3[7] ;
+ wire \soc.core.mgmtsoc_bus_errors[0] ;
+ wire \soc.core.mgmtsoc_bus_errors[10] ;
+ wire \soc.core.mgmtsoc_bus_errors[11] ;
+ wire \soc.core.mgmtsoc_bus_errors[12] ;
+ wire \soc.core.mgmtsoc_bus_errors[13] ;
+ wire \soc.core.mgmtsoc_bus_errors[14] ;
+ wire \soc.core.mgmtsoc_bus_errors[15] ;
+ wire \soc.core.mgmtsoc_bus_errors[16] ;
+ wire \soc.core.mgmtsoc_bus_errors[17] ;
+ wire \soc.core.mgmtsoc_bus_errors[18] ;
+ wire \soc.core.mgmtsoc_bus_errors[19] ;
+ wire \soc.core.mgmtsoc_bus_errors[1] ;
+ wire \soc.core.mgmtsoc_bus_errors[20] ;
+ wire \soc.core.mgmtsoc_bus_errors[21] ;
+ wire \soc.core.mgmtsoc_bus_errors[22] ;
+ wire \soc.core.mgmtsoc_bus_errors[23] ;
+ wire \soc.core.mgmtsoc_bus_errors[24] ;
+ wire \soc.core.mgmtsoc_bus_errors[25] ;
+ wire \soc.core.mgmtsoc_bus_errors[26] ;
+ wire \soc.core.mgmtsoc_bus_errors[27] ;
+ wire \soc.core.mgmtsoc_bus_errors[28] ;
+ wire \soc.core.mgmtsoc_bus_errors[29] ;
+ wire \soc.core.mgmtsoc_bus_errors[2] ;
+ wire \soc.core.mgmtsoc_bus_errors[30] ;
+ wire \soc.core.mgmtsoc_bus_errors[31] ;
+ wire \soc.core.mgmtsoc_bus_errors[3] ;
+ wire \soc.core.mgmtsoc_bus_errors[4] ;
+ wire \soc.core.mgmtsoc_bus_errors[5] ;
+ wire \soc.core.mgmtsoc_bus_errors[6] ;
+ wire \soc.core.mgmtsoc_bus_errors[7] ;
+ wire \soc.core.mgmtsoc_bus_errors[8] ;
+ wire \soc.core.mgmtsoc_bus_errors[9] ;
+ wire \soc.core.mgmtsoc_cpu_rst ;
+ wire \soc.core.mgmtsoc_en_storage ;
+ wire \soc.core.mgmtsoc_enable_storage ;
+ wire \soc.core.mgmtsoc_irq ;
+ wire \soc.core.mgmtsoc_litespimmap_burst_adr[0] ;
+ wire \soc.core.mgmtsoc_litespimmap_burst_adr[10] ;
+ wire \soc.core.mgmtsoc_litespimmap_burst_adr[11] ;
+ wire \soc.core.mgmtsoc_litespimmap_burst_adr[12] ;
+ wire \soc.core.mgmtsoc_litespimmap_burst_adr[13] ;
+ wire \soc.core.mgmtsoc_litespimmap_burst_adr[14] ;
+ wire \soc.core.mgmtsoc_litespimmap_burst_adr[15] ;
+ wire \soc.core.mgmtsoc_litespimmap_burst_adr[16] ;
+ wire \soc.core.mgmtsoc_litespimmap_burst_adr[17] ;
+ wire \soc.core.mgmtsoc_litespimmap_burst_adr[18] ;
+ wire \soc.core.mgmtsoc_litespimmap_burst_adr[19] ;
+ wire \soc.core.mgmtsoc_litespimmap_burst_adr[1] ;
+ wire \soc.core.mgmtsoc_litespimmap_burst_adr[20] ;
+ wire \soc.core.mgmtsoc_litespimmap_burst_adr[21] ;
+ wire \soc.core.mgmtsoc_litespimmap_burst_adr[22] ;
+ wire \soc.core.mgmtsoc_litespimmap_burst_adr[23] ;
+ wire \soc.core.mgmtsoc_litespimmap_burst_adr[24] ;
+ wire \soc.core.mgmtsoc_litespimmap_burst_adr[25] ;
+ wire \soc.core.mgmtsoc_litespimmap_burst_adr[26] ;
+ wire \soc.core.mgmtsoc_litespimmap_burst_adr[27] ;
+ wire \soc.core.mgmtsoc_litespimmap_burst_adr[28] ;
+ wire \soc.core.mgmtsoc_litespimmap_burst_adr[29] ;
+ wire \soc.core.mgmtsoc_litespimmap_burst_adr[2] ;
+ wire \soc.core.mgmtsoc_litespimmap_burst_adr[3] ;
+ wire \soc.core.mgmtsoc_litespimmap_burst_adr[4] ;
+ wire \soc.core.mgmtsoc_litespimmap_burst_adr[5] ;
+ wire \soc.core.mgmtsoc_litespimmap_burst_adr[6] ;
+ wire \soc.core.mgmtsoc_litespimmap_burst_adr[7] ;
+ wire \soc.core.mgmtsoc_litespimmap_burst_adr[8] ;
+ wire \soc.core.mgmtsoc_litespimmap_burst_adr[9] ;
+ wire \soc.core.mgmtsoc_litespimmap_burst_cs ;
+ wire \soc.core.mgmtsoc_litespimmap_count[0] ;
+ wire \soc.core.mgmtsoc_litespimmap_count[1] ;
+ wire \soc.core.mgmtsoc_litespimmap_count[2] ;
+ wire \soc.core.mgmtsoc_litespimmap_count[3] ;
+ wire \soc.core.mgmtsoc_litespimmap_count[4] ;
+ wire \soc.core.mgmtsoc_litespimmap_count[5] ;
+ wire \soc.core.mgmtsoc_litespimmap_count[6] ;
+ wire \soc.core.mgmtsoc_litespimmap_count[7] ;
+ wire \soc.core.mgmtsoc_litespimmap_count[8] ;
+ wire \soc.core.mgmtsoc_litespimmap_storage[0] ;
+ wire \soc.core.mgmtsoc_litespimmap_storage[1] ;
+ wire \soc.core.mgmtsoc_litespimmap_storage[2] ;
+ wire \soc.core.mgmtsoc_litespimmap_storage[3] ;
+ wire \soc.core.mgmtsoc_litespimmap_storage[4] ;
+ wire \soc.core.mgmtsoc_litespimmap_storage[5] ;
+ wire \soc.core.mgmtsoc_litespimmap_storage[6] ;
+ wire \soc.core.mgmtsoc_litespimmap_storage[7] ;
+ wire \soc.core.mgmtsoc_litespisdrphycore_clk ;
+ wire \soc.core.mgmtsoc_litespisdrphycore_cnt[0] ;
+ wire \soc.core.mgmtsoc_litespisdrphycore_cnt[1] ;
+ wire \soc.core.mgmtsoc_litespisdrphycore_cnt[2] ;
+ wire \soc.core.mgmtsoc_litespisdrphycore_cnt[3] ;
+ wire \soc.core.mgmtsoc_litespisdrphycore_cnt[4] ;
+ wire \soc.core.mgmtsoc_litespisdrphycore_cnt[5] ;
+ wire \soc.core.mgmtsoc_litespisdrphycore_cnt[6] ;
+ wire \soc.core.mgmtsoc_litespisdrphycore_cnt[7] ;
+ wire \soc.core.mgmtsoc_litespisdrphycore_count[0] ;
+ wire \soc.core.mgmtsoc_litespisdrphycore_count[1] ;
+ wire \soc.core.mgmtsoc_litespisdrphycore_count[2] ;
+ wire \soc.core.mgmtsoc_litespisdrphycore_count[3] ;
+ wire \soc.core.mgmtsoc_litespisdrphycore_dq_i[1] ;
+ wire \soc.core.mgmtsoc_litespisdrphycore_dq_o ;
+ wire \soc.core.mgmtsoc_litespisdrphycore_posedge_reg ;
+ wire \soc.core.mgmtsoc_litespisdrphycore_posedge_reg2 ;
+ wire \soc.core.mgmtsoc_litespisdrphycore_sr_cnt[0] ;
+ wire \soc.core.mgmtsoc_litespisdrphycore_sr_cnt[1] ;
+ wire \soc.core.mgmtsoc_litespisdrphycore_sr_cnt[2] ;
+ wire \soc.core.mgmtsoc_litespisdrphycore_sr_cnt[3] ;
+ wire \soc.core.mgmtsoc_litespisdrphycore_sr_cnt[4] ;
+ wire \soc.core.mgmtsoc_litespisdrphycore_sr_cnt[5] ;
+ wire \soc.core.mgmtsoc_litespisdrphycore_sr_cnt[6] ;
+ wire \soc.core.mgmtsoc_litespisdrphycore_sr_cnt[7] ;
+ wire \soc.core.mgmtsoc_litespisdrphycore_sr_in[0] ;
+ wire \soc.core.mgmtsoc_litespisdrphycore_sr_in[10] ;
+ wire \soc.core.mgmtsoc_litespisdrphycore_sr_in[11] ;
+ wire \soc.core.mgmtsoc_litespisdrphycore_sr_in[12] ;
+ wire \soc.core.mgmtsoc_litespisdrphycore_sr_in[13] ;
+ wire \soc.core.mgmtsoc_litespisdrphycore_sr_in[14] ;
+ wire \soc.core.mgmtsoc_litespisdrphycore_sr_in[15] ;
+ wire \soc.core.mgmtsoc_litespisdrphycore_sr_in[16] ;
+ wire \soc.core.mgmtsoc_litespisdrphycore_sr_in[17] ;
+ wire \soc.core.mgmtsoc_litespisdrphycore_sr_in[18] ;
+ wire \soc.core.mgmtsoc_litespisdrphycore_sr_in[19] ;
+ wire \soc.core.mgmtsoc_litespisdrphycore_sr_in[1] ;
+ wire \soc.core.mgmtsoc_litespisdrphycore_sr_in[20] ;
+ wire \soc.core.mgmtsoc_litespisdrphycore_sr_in[21] ;
+ wire \soc.core.mgmtsoc_litespisdrphycore_sr_in[22] ;
+ wire \soc.core.mgmtsoc_litespisdrphycore_sr_in[23] ;
+ wire \soc.core.mgmtsoc_litespisdrphycore_sr_in[24] ;
+ wire \soc.core.mgmtsoc_litespisdrphycore_sr_in[25] ;
+ wire \soc.core.mgmtsoc_litespisdrphycore_sr_in[26] ;
+ wire \soc.core.mgmtsoc_litespisdrphycore_sr_in[27] ;
+ wire \soc.core.mgmtsoc_litespisdrphycore_sr_in[28] ;
+ wire \soc.core.mgmtsoc_litespisdrphycore_sr_in[29] ;
+ wire \soc.core.mgmtsoc_litespisdrphycore_sr_in[2] ;
+ wire \soc.core.mgmtsoc_litespisdrphycore_sr_in[30] ;
+ wire \soc.core.mgmtsoc_litespisdrphycore_sr_in[31] ;
+ wire \soc.core.mgmtsoc_litespisdrphycore_sr_in[3] ;
+ wire \soc.core.mgmtsoc_litespisdrphycore_sr_in[4] ;
+ wire \soc.core.mgmtsoc_litespisdrphycore_sr_in[5] ;
+ wire \soc.core.mgmtsoc_litespisdrphycore_sr_in[6] ;
+ wire \soc.core.mgmtsoc_litespisdrphycore_sr_in[7] ;
+ wire \soc.core.mgmtsoc_litespisdrphycore_sr_in[8] ;
+ wire \soc.core.mgmtsoc_litespisdrphycore_sr_in[9] ;
+ wire \soc.core.mgmtsoc_litespisdrphycore_sr_out[0] ;
+ wire \soc.core.mgmtsoc_litespisdrphycore_sr_out[10] ;
+ wire \soc.core.mgmtsoc_litespisdrphycore_sr_out[11] ;
+ wire \soc.core.mgmtsoc_litespisdrphycore_sr_out[12] ;
+ wire \soc.core.mgmtsoc_litespisdrphycore_sr_out[13] ;
+ wire \soc.core.mgmtsoc_litespisdrphycore_sr_out[14] ;
+ wire \soc.core.mgmtsoc_litespisdrphycore_sr_out[15] ;
+ wire \soc.core.mgmtsoc_litespisdrphycore_sr_out[16] ;
+ wire \soc.core.mgmtsoc_litespisdrphycore_sr_out[17] ;
+ wire \soc.core.mgmtsoc_litespisdrphycore_sr_out[18] ;
+ wire \soc.core.mgmtsoc_litespisdrphycore_sr_out[19] ;
+ wire \soc.core.mgmtsoc_litespisdrphycore_sr_out[1] ;
+ wire \soc.core.mgmtsoc_litespisdrphycore_sr_out[20] ;
+ wire \soc.core.mgmtsoc_litespisdrphycore_sr_out[21] ;
+ wire \soc.core.mgmtsoc_litespisdrphycore_sr_out[22] ;
+ wire \soc.core.mgmtsoc_litespisdrphycore_sr_out[23] ;
+ wire \soc.core.mgmtsoc_litespisdrphycore_sr_out[24] ;
+ wire \soc.core.mgmtsoc_litespisdrphycore_sr_out[25] ;
+ wire \soc.core.mgmtsoc_litespisdrphycore_sr_out[26] ;
+ wire \soc.core.mgmtsoc_litespisdrphycore_sr_out[27] ;
+ wire \soc.core.mgmtsoc_litespisdrphycore_sr_out[28] ;
+ wire \soc.core.mgmtsoc_litespisdrphycore_sr_out[29] ;
+ wire \soc.core.mgmtsoc_litespisdrphycore_sr_out[2] ;
+ wire \soc.core.mgmtsoc_litespisdrphycore_sr_out[30] ;
+ wire \soc.core.mgmtsoc_litespisdrphycore_sr_out[31] ;
+ wire \soc.core.mgmtsoc_litespisdrphycore_sr_out[3] ;
+ wire \soc.core.mgmtsoc_litespisdrphycore_sr_out[4] ;
+ wire \soc.core.mgmtsoc_litespisdrphycore_sr_out[5] ;
+ wire \soc.core.mgmtsoc_litespisdrphycore_sr_out[6] ;
+ wire \soc.core.mgmtsoc_litespisdrphycore_sr_out[7] ;
+ wire \soc.core.mgmtsoc_litespisdrphycore_sr_out[8] ;
+ wire \soc.core.mgmtsoc_litespisdrphycore_sr_out[9] ;
+ wire \soc.core.mgmtsoc_litespisdrphycore_storage[0] ;
+ wire \soc.core.mgmtsoc_litespisdrphycore_storage[1] ;
+ wire \soc.core.mgmtsoc_litespisdrphycore_storage[2] ;
+ wire \soc.core.mgmtsoc_litespisdrphycore_storage[3] ;
+ wire \soc.core.mgmtsoc_litespisdrphycore_storage[4] ;
+ wire \soc.core.mgmtsoc_litespisdrphycore_storage[5] ;
+ wire \soc.core.mgmtsoc_litespisdrphycore_storage[6] ;
+ wire \soc.core.mgmtsoc_litespisdrphycore_storage[7] ;
+ wire \soc.core.mgmtsoc_load_storage[0] ;
+ wire \soc.core.mgmtsoc_load_storage[10] ;
+ wire \soc.core.mgmtsoc_load_storage[11] ;
+ wire \soc.core.mgmtsoc_load_storage[12] ;
+ wire \soc.core.mgmtsoc_load_storage[13] ;
+ wire \soc.core.mgmtsoc_load_storage[14] ;
+ wire \soc.core.mgmtsoc_load_storage[15] ;
+ wire \soc.core.mgmtsoc_load_storage[16] ;
+ wire \soc.core.mgmtsoc_load_storage[17] ;
+ wire \soc.core.mgmtsoc_load_storage[18] ;
+ wire \soc.core.mgmtsoc_load_storage[19] ;
+ wire \soc.core.mgmtsoc_load_storage[1] ;
+ wire \soc.core.mgmtsoc_load_storage[20] ;
+ wire \soc.core.mgmtsoc_load_storage[21] ;
+ wire \soc.core.mgmtsoc_load_storage[22] ;
+ wire \soc.core.mgmtsoc_load_storage[23] ;
+ wire \soc.core.mgmtsoc_load_storage[24] ;
+ wire \soc.core.mgmtsoc_load_storage[25] ;
+ wire \soc.core.mgmtsoc_load_storage[26] ;
+ wire \soc.core.mgmtsoc_load_storage[27] ;
+ wire \soc.core.mgmtsoc_load_storage[28] ;
+ wire \soc.core.mgmtsoc_load_storage[29] ;
+ wire \soc.core.mgmtsoc_load_storage[2] ;
+ wire \soc.core.mgmtsoc_load_storage[30] ;
+ wire \soc.core.mgmtsoc_load_storage[31] ;
+ wire \soc.core.mgmtsoc_load_storage[3] ;
+ wire \soc.core.mgmtsoc_load_storage[4] ;
+ wire \soc.core.mgmtsoc_load_storage[5] ;
+ wire \soc.core.mgmtsoc_load_storage[6] ;
+ wire \soc.core.mgmtsoc_load_storage[7] ;
+ wire \soc.core.mgmtsoc_load_storage[8] ;
+ wire \soc.core.mgmtsoc_load_storage[9] ;
+ wire \soc.core.mgmtsoc_master_cs_storage ;
+ wire \soc.core.mgmtsoc_master_phyconfig_storage[0] ;
+ wire \soc.core.mgmtsoc_master_phyconfig_storage[10] ;
+ wire \soc.core.mgmtsoc_master_phyconfig_storage[11] ;
+ wire \soc.core.mgmtsoc_master_phyconfig_storage[12] ;
+ wire \soc.core.mgmtsoc_master_phyconfig_storage[13] ;
+ wire \soc.core.mgmtsoc_master_phyconfig_storage[14] ;
+ wire \soc.core.mgmtsoc_master_phyconfig_storage[15] ;
+ wire \soc.core.mgmtsoc_master_phyconfig_storage[16] ;
+ wire \soc.core.mgmtsoc_master_phyconfig_storage[17] ;
+ wire \soc.core.mgmtsoc_master_phyconfig_storage[18] ;
+ wire \soc.core.mgmtsoc_master_phyconfig_storage[19] ;
+ wire \soc.core.mgmtsoc_master_phyconfig_storage[1] ;
+ wire \soc.core.mgmtsoc_master_phyconfig_storage[20] ;
+ wire \soc.core.mgmtsoc_master_phyconfig_storage[21] ;
+ wire \soc.core.mgmtsoc_master_phyconfig_storage[22] ;
+ wire \soc.core.mgmtsoc_master_phyconfig_storage[23] ;
+ wire \soc.core.mgmtsoc_master_phyconfig_storage[2] ;
+ wire \soc.core.mgmtsoc_master_phyconfig_storage[3] ;
+ wire \soc.core.mgmtsoc_master_phyconfig_storage[4] ;
+ wire \soc.core.mgmtsoc_master_phyconfig_storage[5] ;
+ wire \soc.core.mgmtsoc_master_phyconfig_storage[6] ;
+ wire \soc.core.mgmtsoc_master_phyconfig_storage[7] ;
+ wire \soc.core.mgmtsoc_master_phyconfig_storage[8] ;
+ wire \soc.core.mgmtsoc_master_phyconfig_storage[9] ;
+ wire \soc.core.mgmtsoc_master_rx_fifo_source_payload_data[0] ;
+ wire \soc.core.mgmtsoc_master_rx_fifo_source_payload_data[10] ;
+ wire \soc.core.mgmtsoc_master_rx_fifo_source_payload_data[11] ;
+ wire \soc.core.mgmtsoc_master_rx_fifo_source_payload_data[12] ;
+ wire \soc.core.mgmtsoc_master_rx_fifo_source_payload_data[13] ;
+ wire \soc.core.mgmtsoc_master_rx_fifo_source_payload_data[14] ;
+ wire \soc.core.mgmtsoc_master_rx_fifo_source_payload_data[15] ;
+ wire \soc.core.mgmtsoc_master_rx_fifo_source_payload_data[16] ;
+ wire \soc.core.mgmtsoc_master_rx_fifo_source_payload_data[17] ;
+ wire \soc.core.mgmtsoc_master_rx_fifo_source_payload_data[18] ;
+ wire \soc.core.mgmtsoc_master_rx_fifo_source_payload_data[19] ;
+ wire \soc.core.mgmtsoc_master_rx_fifo_source_payload_data[1] ;
+ wire \soc.core.mgmtsoc_master_rx_fifo_source_payload_data[20] ;
+ wire \soc.core.mgmtsoc_master_rx_fifo_source_payload_data[21] ;
+ wire \soc.core.mgmtsoc_master_rx_fifo_source_payload_data[22] ;
+ wire \soc.core.mgmtsoc_master_rx_fifo_source_payload_data[23] ;
+ wire \soc.core.mgmtsoc_master_rx_fifo_source_payload_data[24] ;
+ wire \soc.core.mgmtsoc_master_rx_fifo_source_payload_data[25] ;
+ wire \soc.core.mgmtsoc_master_rx_fifo_source_payload_data[26] ;
+ wire \soc.core.mgmtsoc_master_rx_fifo_source_payload_data[27] ;
+ wire \soc.core.mgmtsoc_master_rx_fifo_source_payload_data[28] ;
+ wire \soc.core.mgmtsoc_master_rx_fifo_source_payload_data[29] ;
+ wire \soc.core.mgmtsoc_master_rx_fifo_source_payload_data[2] ;
+ wire \soc.core.mgmtsoc_master_rx_fifo_source_payload_data[30] ;
+ wire \soc.core.mgmtsoc_master_rx_fifo_source_payload_data[31] ;
+ wire \soc.core.mgmtsoc_master_rx_fifo_source_payload_data[3] ;
+ wire \soc.core.mgmtsoc_master_rx_fifo_source_payload_data[4] ;
+ wire \soc.core.mgmtsoc_master_rx_fifo_source_payload_data[5] ;
+ wire \soc.core.mgmtsoc_master_rx_fifo_source_payload_data[6] ;
+ wire \soc.core.mgmtsoc_master_rx_fifo_source_payload_data[7] ;
+ wire \soc.core.mgmtsoc_master_rx_fifo_source_payload_data[8] ;
+ wire \soc.core.mgmtsoc_master_rx_fifo_source_payload_data[9] ;
+ wire \soc.core.mgmtsoc_master_rx_fifo_source_valid ;
+ wire \soc.core.mgmtsoc_master_tx_fifo_source_payload_data[0] ;
+ wire \soc.core.mgmtsoc_master_tx_fifo_source_payload_data[10] ;
+ wire \soc.core.mgmtsoc_master_tx_fifo_source_payload_data[11] ;
+ wire \soc.core.mgmtsoc_master_tx_fifo_source_payload_data[12] ;
+ wire \soc.core.mgmtsoc_master_tx_fifo_source_payload_data[13] ;
+ wire \soc.core.mgmtsoc_master_tx_fifo_source_payload_data[14] ;
+ wire \soc.core.mgmtsoc_master_tx_fifo_source_payload_data[15] ;
+ wire \soc.core.mgmtsoc_master_tx_fifo_source_payload_data[16] ;
+ wire \soc.core.mgmtsoc_master_tx_fifo_source_payload_data[17] ;
+ wire \soc.core.mgmtsoc_master_tx_fifo_source_payload_data[18] ;
+ wire \soc.core.mgmtsoc_master_tx_fifo_source_payload_data[19] ;
+ wire \soc.core.mgmtsoc_master_tx_fifo_source_payload_data[1] ;
+ wire \soc.core.mgmtsoc_master_tx_fifo_source_payload_data[20] ;
+ wire \soc.core.mgmtsoc_master_tx_fifo_source_payload_data[21] ;
+ wire \soc.core.mgmtsoc_master_tx_fifo_source_payload_data[22] ;
+ wire \soc.core.mgmtsoc_master_tx_fifo_source_payload_data[23] ;
+ wire \soc.core.mgmtsoc_master_tx_fifo_source_payload_data[24] ;
+ wire \soc.core.mgmtsoc_master_tx_fifo_source_payload_data[25] ;
+ wire \soc.core.mgmtsoc_master_tx_fifo_source_payload_data[26] ;
+ wire \soc.core.mgmtsoc_master_tx_fifo_source_payload_data[27] ;
+ wire \soc.core.mgmtsoc_master_tx_fifo_source_payload_data[28] ;
+ wire \soc.core.mgmtsoc_master_tx_fifo_source_payload_data[29] ;
+ wire \soc.core.mgmtsoc_master_tx_fifo_source_payload_data[2] ;
+ wire \soc.core.mgmtsoc_master_tx_fifo_source_payload_data[30] ;
+ wire \soc.core.mgmtsoc_master_tx_fifo_source_payload_data[31] ;
+ wire \soc.core.mgmtsoc_master_tx_fifo_source_payload_data[3] ;
+ wire \soc.core.mgmtsoc_master_tx_fifo_source_payload_data[4] ;
+ wire \soc.core.mgmtsoc_master_tx_fifo_source_payload_data[5] ;
+ wire \soc.core.mgmtsoc_master_tx_fifo_source_payload_data[6] ;
+ wire \soc.core.mgmtsoc_master_tx_fifo_source_payload_data[7] ;
+ wire \soc.core.mgmtsoc_master_tx_fifo_source_payload_data[8] ;
+ wire \soc.core.mgmtsoc_master_tx_fifo_source_payload_data[9] ;
+ wire \soc.core.mgmtsoc_master_tx_fifo_source_payload_len[0] ;
+ wire \soc.core.mgmtsoc_master_tx_fifo_source_payload_len[1] ;
+ wire \soc.core.mgmtsoc_master_tx_fifo_source_payload_len[2] ;
+ wire \soc.core.mgmtsoc_master_tx_fifo_source_payload_len[3] ;
+ wire \soc.core.mgmtsoc_master_tx_fifo_source_payload_len[4] ;
+ wire \soc.core.mgmtsoc_master_tx_fifo_source_payload_len[5] ;
+ wire \soc.core.mgmtsoc_master_tx_fifo_source_payload_mask[0] ;
+ wire \soc.core.mgmtsoc_master_tx_fifo_source_payload_width[0] ;
+ wire \soc.core.mgmtsoc_master_tx_fifo_source_payload_width[1] ;
+ wire \soc.core.mgmtsoc_master_tx_fifo_source_payload_width[2] ;
+ wire \soc.core.mgmtsoc_master_tx_fifo_source_payload_width[3] ;
+ wire \soc.core.mgmtsoc_master_tx_fifo_source_valid ;
+ wire \soc.core.mgmtsoc_pending_r ;
+ wire \soc.core.mgmtsoc_pending_re ;
+ wire \soc.core.mgmtsoc_reload_storage[0] ;
+ wire \soc.core.mgmtsoc_reload_storage[10] ;
+ wire \soc.core.mgmtsoc_reload_storage[11] ;
+ wire \soc.core.mgmtsoc_reload_storage[12] ;
+ wire \soc.core.mgmtsoc_reload_storage[13] ;
+ wire \soc.core.mgmtsoc_reload_storage[14] ;
+ wire \soc.core.mgmtsoc_reload_storage[15] ;
+ wire \soc.core.mgmtsoc_reload_storage[16] ;
+ wire \soc.core.mgmtsoc_reload_storage[17] ;
+ wire \soc.core.mgmtsoc_reload_storage[18] ;
+ wire \soc.core.mgmtsoc_reload_storage[19] ;
+ wire \soc.core.mgmtsoc_reload_storage[1] ;
+ wire \soc.core.mgmtsoc_reload_storage[20] ;
+ wire \soc.core.mgmtsoc_reload_storage[21] ;
+ wire \soc.core.mgmtsoc_reload_storage[22] ;
+ wire \soc.core.mgmtsoc_reload_storage[23] ;
+ wire \soc.core.mgmtsoc_reload_storage[24] ;
+ wire \soc.core.mgmtsoc_reload_storage[25] ;
+ wire \soc.core.mgmtsoc_reload_storage[26] ;
+ wire \soc.core.mgmtsoc_reload_storage[27] ;
+ wire \soc.core.mgmtsoc_reload_storage[28] ;
+ wire \soc.core.mgmtsoc_reload_storage[29] ;
+ wire \soc.core.mgmtsoc_reload_storage[2] ;
+ wire \soc.core.mgmtsoc_reload_storage[30] ;
+ wire \soc.core.mgmtsoc_reload_storage[31] ;
+ wire \soc.core.mgmtsoc_reload_storage[3] ;
+ wire \soc.core.mgmtsoc_reload_storage[4] ;
+ wire \soc.core.mgmtsoc_reload_storage[5] ;
+ wire \soc.core.mgmtsoc_reload_storage[6] ;
+ wire \soc.core.mgmtsoc_reload_storage[7] ;
+ wire \soc.core.mgmtsoc_reload_storage[8] ;
+ wire \soc.core.mgmtsoc_reload_storage[9] ;
+ wire \soc.core.mgmtsoc_reset_re ;
+ wire \soc.core.mgmtsoc_reset_storage[0] ;
+ wire \soc.core.mgmtsoc_scratch_storage[0] ;
+ wire \soc.core.mgmtsoc_scratch_storage[10] ;
+ wire \soc.core.mgmtsoc_scratch_storage[11] ;
+ wire \soc.core.mgmtsoc_scratch_storage[12] ;
+ wire \soc.core.mgmtsoc_scratch_storage[13] ;
+ wire \soc.core.mgmtsoc_scratch_storage[14] ;
+ wire \soc.core.mgmtsoc_scratch_storage[15] ;
+ wire \soc.core.mgmtsoc_scratch_storage[16] ;
+ wire \soc.core.mgmtsoc_scratch_storage[17] ;
+ wire \soc.core.mgmtsoc_scratch_storage[18] ;
+ wire \soc.core.mgmtsoc_scratch_storage[19] ;
+ wire \soc.core.mgmtsoc_scratch_storage[1] ;
+ wire \soc.core.mgmtsoc_scratch_storage[20] ;
+ wire \soc.core.mgmtsoc_scratch_storage[21] ;
+ wire \soc.core.mgmtsoc_scratch_storage[22] ;
+ wire \soc.core.mgmtsoc_scratch_storage[23] ;
+ wire \soc.core.mgmtsoc_scratch_storage[24] ;
+ wire \soc.core.mgmtsoc_scratch_storage[25] ;
+ wire \soc.core.mgmtsoc_scratch_storage[26] ;
+ wire \soc.core.mgmtsoc_scratch_storage[27] ;
+ wire \soc.core.mgmtsoc_scratch_storage[28] ;
+ wire \soc.core.mgmtsoc_scratch_storage[29] ;
+ wire \soc.core.mgmtsoc_scratch_storage[2] ;
+ wire \soc.core.mgmtsoc_scratch_storage[30] ;
+ wire \soc.core.mgmtsoc_scratch_storage[31] ;
+ wire \soc.core.mgmtsoc_scratch_storage[3] ;
+ wire \soc.core.mgmtsoc_scratch_storage[4] ;
+ wire \soc.core.mgmtsoc_scratch_storage[5] ;
+ wire \soc.core.mgmtsoc_scratch_storage[6] ;
+ wire \soc.core.mgmtsoc_scratch_storage[7] ;
+ wire \soc.core.mgmtsoc_scratch_storage[8] ;
+ wire \soc.core.mgmtsoc_scratch_storage[9] ;
+ wire \soc.core.mgmtsoc_update_value_re ;
+ wire \soc.core.mgmtsoc_update_value_storage ;
+ wire \soc.core.mgmtsoc_value[0] ;
+ wire \soc.core.mgmtsoc_value[10] ;
+ wire \soc.core.mgmtsoc_value[11] ;
+ wire \soc.core.mgmtsoc_value[12] ;
+ wire \soc.core.mgmtsoc_value[13] ;
+ wire \soc.core.mgmtsoc_value[14] ;
+ wire \soc.core.mgmtsoc_value[15] ;
+ wire \soc.core.mgmtsoc_value[16] ;
+ wire \soc.core.mgmtsoc_value[17] ;
+ wire \soc.core.mgmtsoc_value[18] ;
+ wire \soc.core.mgmtsoc_value[19] ;
+ wire \soc.core.mgmtsoc_value[1] ;
+ wire \soc.core.mgmtsoc_value[20] ;
+ wire \soc.core.mgmtsoc_value[21] ;
+ wire \soc.core.mgmtsoc_value[22] ;
+ wire \soc.core.mgmtsoc_value[23] ;
+ wire \soc.core.mgmtsoc_value[24] ;
+ wire \soc.core.mgmtsoc_value[25] ;
+ wire \soc.core.mgmtsoc_value[26] ;
+ wire \soc.core.mgmtsoc_value[27] ;
+ wire \soc.core.mgmtsoc_value[28] ;
+ wire \soc.core.mgmtsoc_value[29] ;
+ wire \soc.core.mgmtsoc_value[2] ;
+ wire \soc.core.mgmtsoc_value[30] ;
+ wire \soc.core.mgmtsoc_value[31] ;
+ wire \soc.core.mgmtsoc_value[3] ;
+ wire \soc.core.mgmtsoc_value[4] ;
+ wire \soc.core.mgmtsoc_value[5] ;
+ wire \soc.core.mgmtsoc_value[6] ;
+ wire \soc.core.mgmtsoc_value[7] ;
+ wire \soc.core.mgmtsoc_value[8] ;
+ wire \soc.core.mgmtsoc_value[9] ;
+ wire \soc.core.mgmtsoc_value_status[0] ;
+ wire \soc.core.mgmtsoc_value_status[10] ;
+ wire \soc.core.mgmtsoc_value_status[11] ;
+ wire \soc.core.mgmtsoc_value_status[12] ;
+ wire \soc.core.mgmtsoc_value_status[13] ;
+ wire \soc.core.mgmtsoc_value_status[14] ;
+ wire \soc.core.mgmtsoc_value_status[15] ;
+ wire \soc.core.mgmtsoc_value_status[16] ;
+ wire \soc.core.mgmtsoc_value_status[17] ;
+ wire \soc.core.mgmtsoc_value_status[18] ;
+ wire \soc.core.mgmtsoc_value_status[19] ;
+ wire \soc.core.mgmtsoc_value_status[1] ;
+ wire \soc.core.mgmtsoc_value_status[20] ;
+ wire \soc.core.mgmtsoc_value_status[21] ;
+ wire \soc.core.mgmtsoc_value_status[22] ;
+ wire \soc.core.mgmtsoc_value_status[23] ;
+ wire \soc.core.mgmtsoc_value_status[24] ;
+ wire \soc.core.mgmtsoc_value_status[25] ;
+ wire \soc.core.mgmtsoc_value_status[26] ;
+ wire \soc.core.mgmtsoc_value_status[27] ;
+ wire \soc.core.mgmtsoc_value_status[28] ;
+ wire \soc.core.mgmtsoc_value_status[29] ;
+ wire \soc.core.mgmtsoc_value_status[2] ;
+ wire \soc.core.mgmtsoc_value_status[30] ;
+ wire \soc.core.mgmtsoc_value_status[31] ;
+ wire \soc.core.mgmtsoc_value_status[3] ;
+ wire \soc.core.mgmtsoc_value_status[4] ;
+ wire \soc.core.mgmtsoc_value_status[5] ;
+ wire \soc.core.mgmtsoc_value_status[6] ;
+ wire \soc.core.mgmtsoc_value_status[7] ;
+ wire \soc.core.mgmtsoc_value_status[8] ;
+ wire \soc.core.mgmtsoc_value_status[9] ;
+ wire \soc.core.mgmtsoc_vexriscv_debug_bus_ack ;
+ wire \soc.core.mgmtsoc_vexriscv_debug_bus_dat_r[0] ;
+ wire \soc.core.mgmtsoc_vexriscv_debug_bus_dat_r[10] ;
+ wire \soc.core.mgmtsoc_vexriscv_debug_bus_dat_r[11] ;
+ wire \soc.core.mgmtsoc_vexriscv_debug_bus_dat_r[12] ;
+ wire \soc.core.mgmtsoc_vexriscv_debug_bus_dat_r[13] ;
+ wire \soc.core.mgmtsoc_vexriscv_debug_bus_dat_r[14] ;
+ wire \soc.core.mgmtsoc_vexriscv_debug_bus_dat_r[15] ;
+ wire \soc.core.mgmtsoc_vexriscv_debug_bus_dat_r[16] ;
+ wire \soc.core.mgmtsoc_vexriscv_debug_bus_dat_r[17] ;
+ wire \soc.core.mgmtsoc_vexriscv_debug_bus_dat_r[18] ;
+ wire \soc.core.mgmtsoc_vexriscv_debug_bus_dat_r[19] ;
+ wire \soc.core.mgmtsoc_vexriscv_debug_bus_dat_r[1] ;
+ wire \soc.core.mgmtsoc_vexriscv_debug_bus_dat_r[20] ;
+ wire \soc.core.mgmtsoc_vexriscv_debug_bus_dat_r[21] ;
+ wire \soc.core.mgmtsoc_vexriscv_debug_bus_dat_r[22] ;
+ wire \soc.core.mgmtsoc_vexriscv_debug_bus_dat_r[23] ;
+ wire \soc.core.mgmtsoc_vexriscv_debug_bus_dat_r[24] ;
+ wire \soc.core.mgmtsoc_vexriscv_debug_bus_dat_r[25] ;
+ wire \soc.core.mgmtsoc_vexriscv_debug_bus_dat_r[26] ;
+ wire \soc.core.mgmtsoc_vexriscv_debug_bus_dat_r[27] ;
+ wire \soc.core.mgmtsoc_vexriscv_debug_bus_dat_r[28] ;
+ wire \soc.core.mgmtsoc_vexriscv_debug_bus_dat_r[29] ;
+ wire \soc.core.mgmtsoc_vexriscv_debug_bus_dat_r[2] ;
+ wire \soc.core.mgmtsoc_vexriscv_debug_bus_dat_r[30] ;
+ wire \soc.core.mgmtsoc_vexriscv_debug_bus_dat_r[31] ;
+ wire \soc.core.mgmtsoc_vexriscv_debug_bus_dat_r[3] ;
+ wire \soc.core.mgmtsoc_vexriscv_debug_bus_dat_r[4] ;
+ wire \soc.core.mgmtsoc_vexriscv_debug_bus_dat_r[5] ;
+ wire \soc.core.mgmtsoc_vexriscv_debug_bus_dat_r[6] ;
+ wire \soc.core.mgmtsoc_vexriscv_debug_bus_dat_r[7] ;
+ wire \soc.core.mgmtsoc_vexriscv_debug_bus_dat_r[8] ;
+ wire \soc.core.mgmtsoc_vexriscv_debug_bus_dat_r[9] ;
+ wire \soc.core.mgmtsoc_vexriscv_debug_reset ;
+ wire \soc.core.mgmtsoc_vexriscv_i_cmd_payload_address[2] ;
+ wire \soc.core.mgmtsoc_vexriscv_i_cmd_payload_address[3] ;
+ wire \soc.core.mgmtsoc_vexriscv_i_cmd_payload_address[4] ;
+ wire \soc.core.mgmtsoc_vexriscv_i_cmd_payload_address[5] ;
+ wire \soc.core.mgmtsoc_vexriscv_i_cmd_payload_address[6] ;
+ wire \soc.core.mgmtsoc_vexriscv_i_cmd_payload_address[7] ;
+ wire \soc.core.mgmtsoc_vexriscv_i_cmd_payload_data[0] ;
+ wire \soc.core.mgmtsoc_vexriscv_i_cmd_payload_data[10] ;
+ wire \soc.core.mgmtsoc_vexriscv_i_cmd_payload_data[11] ;
+ wire \soc.core.mgmtsoc_vexriscv_i_cmd_payload_data[12] ;
+ wire \soc.core.mgmtsoc_vexriscv_i_cmd_payload_data[13] ;
+ wire \soc.core.mgmtsoc_vexriscv_i_cmd_payload_data[14] ;
+ wire \soc.core.mgmtsoc_vexriscv_i_cmd_payload_data[15] ;
+ wire \soc.core.mgmtsoc_vexriscv_i_cmd_payload_data[19] ;
+ wire \soc.core.mgmtsoc_vexriscv_i_cmd_payload_data[1] ;
+ wire \soc.core.mgmtsoc_vexriscv_i_cmd_payload_data[20] ;
+ wire \soc.core.mgmtsoc_vexriscv_i_cmd_payload_data[21] ;
+ wire \soc.core.mgmtsoc_vexriscv_i_cmd_payload_data[22] ;
+ wire \soc.core.mgmtsoc_vexriscv_i_cmd_payload_data[23] ;
+ wire \soc.core.mgmtsoc_vexriscv_i_cmd_payload_data[27] ;
+ wire \soc.core.mgmtsoc_vexriscv_i_cmd_payload_data[28] ;
+ wire \soc.core.mgmtsoc_vexriscv_i_cmd_payload_data[29] ;
+ wire \soc.core.mgmtsoc_vexriscv_i_cmd_payload_data[2] ;
+ wire \soc.core.mgmtsoc_vexriscv_i_cmd_payload_data[30] ;
+ wire \soc.core.mgmtsoc_vexriscv_i_cmd_payload_data[31] ;
+ wire \soc.core.mgmtsoc_vexriscv_i_cmd_payload_data[3] ;
+ wire \soc.core.mgmtsoc_vexriscv_i_cmd_payload_data[4] ;
+ wire \soc.core.mgmtsoc_vexriscv_i_cmd_payload_data[5] ;
+ wire \soc.core.mgmtsoc_vexriscv_i_cmd_payload_data[6] ;
+ wire \soc.core.mgmtsoc_vexriscv_i_cmd_payload_data[7] ;
+ wire \soc.core.mgmtsoc_vexriscv_i_cmd_payload_data[8] ;
+ wire \soc.core.mgmtsoc_vexriscv_i_cmd_payload_data[9] ;
+ wire \soc.core.mgmtsoc_vexriscv_i_cmd_payload_wr ;
+ wire \soc.core.mgmtsoc_vexriscv_i_cmd_valid ;
+ wire \soc.core.mgmtsoc_vexriscv_reset_debug_logic ;
+ wire \soc.core.mgmtsoc_vexriscv_transfer_complete ;
+ wire \soc.core.mgmtsoc_vexriscv_transfer_in_progress ;
+ wire \soc.core.mgmtsoc_vexriscv_transfer_wait_for_ack ;
+ wire \soc.core.mgmtsoc_zero_pending ;
+ wire \soc.core.mgmtsoc_zero_trigger_d ;
+ wire \soc.core.mprj_wb_iena_storage ;
+ wire \soc.core.multiregimpl0_regs0 ;
+ wire \soc.core.multiregimpl0_regs1 ;
+ wire \soc.core.multiregimpl10_regs0 ;
+ wire \soc.core.multiregimpl10_regs1 ;
+ wire \soc.core.multiregimpl11_regs0 ;
+ wire \soc.core.multiregimpl11_regs1 ;
+ wire \soc.core.multiregimpl12_regs0 ;
+ wire \soc.core.multiregimpl12_regs1 ;
+ wire \soc.core.multiregimpl13_regs0 ;
+ wire \soc.core.multiregimpl13_regs1 ;
+ wire \soc.core.multiregimpl14_regs0 ;
+ wire \soc.core.multiregimpl14_regs1 ;
+ wire \soc.core.multiregimpl15_regs0 ;
+ wire \soc.core.multiregimpl15_regs1 ;
+ wire \soc.core.multiregimpl16_regs0 ;
+ wire \soc.core.multiregimpl16_regs1 ;
+ wire \soc.core.multiregimpl17_regs0 ;
+ wire \soc.core.multiregimpl17_regs1 ;
+ wire \soc.core.multiregimpl18_regs0 ;
+ wire \soc.core.multiregimpl18_regs1 ;
+ wire \soc.core.multiregimpl19_regs0 ;
+ wire \soc.core.multiregimpl19_regs1 ;
+ wire \soc.core.multiregimpl1_regs0 ;
+ wire \soc.core.multiregimpl1_regs1 ;
+ wire \soc.core.multiregimpl20_regs0 ;
+ wire \soc.core.multiregimpl20_regs1 ;
+ wire \soc.core.multiregimpl21_regs0 ;
+ wire \soc.core.multiregimpl21_regs1 ;
+ wire \soc.core.multiregimpl22_regs0 ;
+ wire \soc.core.multiregimpl22_regs1 ;
+ wire \soc.core.multiregimpl23_regs0 ;
+ wire \soc.core.multiregimpl23_regs1 ;
+ wire \soc.core.multiregimpl24_regs0 ;
+ wire \soc.core.multiregimpl24_regs1 ;
+ wire \soc.core.multiregimpl25_regs0 ;
+ wire \soc.core.multiregimpl25_regs1 ;
+ wire \soc.core.multiregimpl26_regs0 ;
+ wire \soc.core.multiregimpl26_regs1 ;
+ wire \soc.core.multiregimpl27_regs0 ;
+ wire \soc.core.multiregimpl27_regs1 ;
+ wire \soc.core.multiregimpl28_regs0 ;
+ wire \soc.core.multiregimpl28_regs1 ;
+ wire \soc.core.multiregimpl29_regs0 ;
+ wire \soc.core.multiregimpl29_regs1 ;
+ wire \soc.core.multiregimpl2_regs0 ;
+ wire \soc.core.multiregimpl2_regs1 ;
+ wire \soc.core.multiregimpl30_regs0 ;
+ wire \soc.core.multiregimpl30_regs1 ;
+ wire \soc.core.multiregimpl31_regs0 ;
+ wire \soc.core.multiregimpl31_regs1 ;
+ wire \soc.core.multiregimpl32_regs0 ;
+ wire \soc.core.multiregimpl32_regs1 ;
+ wire \soc.core.multiregimpl33_regs0 ;
+ wire \soc.core.multiregimpl33_regs1 ;
+ wire \soc.core.multiregimpl34_regs0 ;
+ wire \soc.core.multiregimpl34_regs1 ;
+ wire \soc.core.multiregimpl35_regs0 ;
+ wire \soc.core.multiregimpl35_regs1 ;
+ wire \soc.core.multiregimpl36_regs0 ;
+ wire \soc.core.multiregimpl36_regs1 ;
+ wire \soc.core.multiregimpl37_regs0 ;
+ wire \soc.core.multiregimpl37_regs1 ;
+ wire \soc.core.multiregimpl38_regs0 ;
+ wire \soc.core.multiregimpl38_regs1 ;
+ wire \soc.core.multiregimpl39_regs0 ;
+ wire \soc.core.multiregimpl39_regs1 ;
+ wire \soc.core.multiregimpl3_regs0 ;
+ wire \soc.core.multiregimpl3_regs1 ;
+ wire \soc.core.multiregimpl40_regs0 ;
+ wire \soc.core.multiregimpl40_regs1 ;
+ wire \soc.core.multiregimpl41_regs0 ;
+ wire \soc.core.multiregimpl41_regs1 ;
+ wire \soc.core.multiregimpl42_regs0 ;
+ wire \soc.core.multiregimpl42_regs1 ;
+ wire \soc.core.multiregimpl43_regs0 ;
+ wire \soc.core.multiregimpl43_regs1 ;
+ wire \soc.core.multiregimpl44_regs0 ;
+ wire \soc.core.multiregimpl44_regs1 ;
+ wire \soc.core.multiregimpl45_regs0 ;
+ wire \soc.core.multiregimpl45_regs1 ;
+ wire \soc.core.multiregimpl46_regs0 ;
+ wire \soc.core.multiregimpl46_regs1 ;
+ wire \soc.core.multiregimpl47_regs0 ;
+ wire \soc.core.multiregimpl47_regs1 ;
+ wire \soc.core.multiregimpl48_regs0 ;
+ wire \soc.core.multiregimpl48_regs1 ;
+ wire \soc.core.multiregimpl49_regs0 ;
+ wire \soc.core.multiregimpl49_regs1 ;
+ wire \soc.core.multiregimpl4_regs0 ;
+ wire \soc.core.multiregimpl4_regs1 ;
+ wire \soc.core.multiregimpl50_regs0 ;
+ wire \soc.core.multiregimpl50_regs1 ;
+ wire \soc.core.multiregimpl51_regs0 ;
+ wire \soc.core.multiregimpl51_regs1 ;
+ wire \soc.core.multiregimpl52_regs0 ;
+ wire \soc.core.multiregimpl52_regs1 ;
+ wire \soc.core.multiregimpl53_regs0 ;
+ wire \soc.core.multiregimpl53_regs1 ;
+ wire \soc.core.multiregimpl54_regs0 ;
+ wire \soc.core.multiregimpl54_regs1 ;
+ wire \soc.core.multiregimpl55_regs0 ;
+ wire \soc.core.multiregimpl55_regs1 ;
+ wire \soc.core.multiregimpl56_regs0 ;
+ wire \soc.core.multiregimpl56_regs1 ;
+ wire \soc.core.multiregimpl57_regs0 ;
+ wire \soc.core.multiregimpl57_regs1 ;
+ wire \soc.core.multiregimpl58_regs0 ;
+ wire \soc.core.multiregimpl58_regs1 ;
+ wire \soc.core.multiregimpl59_regs0 ;
+ wire \soc.core.multiregimpl59_regs1 ;
+ wire \soc.core.multiregimpl5_regs0 ;
+ wire \soc.core.multiregimpl5_regs1 ;
+ wire \soc.core.multiregimpl60_regs0 ;
+ wire \soc.core.multiregimpl60_regs1 ;
+ wire \soc.core.multiregimpl61_regs0 ;
+ wire \soc.core.multiregimpl61_regs1 ;
+ wire \soc.core.multiregimpl62_regs0 ;
+ wire \soc.core.multiregimpl62_regs1 ;
+ wire \soc.core.multiregimpl63_regs0 ;
+ wire \soc.core.multiregimpl63_regs1 ;
+ wire \soc.core.multiregimpl64_regs0 ;
+ wire \soc.core.multiregimpl64_regs1 ;
+ wire \soc.core.multiregimpl65_regs0 ;
+ wire \soc.core.multiregimpl65_regs1 ;
+ wire \soc.core.multiregimpl66_regs0 ;
+ wire \soc.core.multiregimpl66_regs1 ;
+ wire \soc.core.multiregimpl67_regs0 ;
+ wire \soc.core.multiregimpl67_regs1 ;
+ wire \soc.core.multiregimpl68_regs0 ;
+ wire \soc.core.multiregimpl68_regs1 ;
+ wire \soc.core.multiregimpl69_regs0 ;
+ wire \soc.core.multiregimpl69_regs1 ;
+ wire \soc.core.multiregimpl6_regs0 ;
+ wire \soc.core.multiregimpl6_regs1 ;
+ wire \soc.core.multiregimpl70_regs0 ;
+ wire \soc.core.multiregimpl70_regs1 ;
+ wire \soc.core.multiregimpl71_regs0 ;
+ wire \soc.core.multiregimpl71_regs1 ;
+ wire \soc.core.multiregimpl72_regs0 ;
+ wire \soc.core.multiregimpl72_regs1 ;
+ wire \soc.core.multiregimpl7_regs0 ;
+ wire \soc.core.multiregimpl7_regs1 ;
+ wire \soc.core.multiregimpl8_regs0 ;
+ wire \soc.core.multiregimpl8_regs1 ;
+ wire \soc.core.multiregimpl9_regs0 ;
+ wire \soc.core.multiregimpl9_regs1 ;
+ wire \soc.core.rs232phy_rs232phyrx_state ;
+ wire \soc.core.rs232phy_rs232phytx_state ;
+ wire \soc.core.serial_rx ;
+ wire \soc.core.serial_tx ;
+ wire \soc.core.slave_sel_r[0] ;
+ wire \soc.core.slave_sel_r[1] ;
+ wire \soc.core.slave_sel_r[2] ;
+ wire \soc.core.slave_sel_r[3] ;
+ wire \soc.core.slave_sel_r[4] ;
+ wire \soc.core.slave_sel_r[5] ;
+ wire \soc.core.spi_clk ;
+ wire \soc.core.spi_cs_n ;
+ wire \soc.core.spi_enabled_storage ;
+ wire \soc.core.spi_master_clk_divider1[0] ;
+ wire \soc.core.spi_master_clk_divider1[10] ;
+ wire \soc.core.spi_master_clk_divider1[11] ;
+ wire \soc.core.spi_master_clk_divider1[12] ;
+ wire \soc.core.spi_master_clk_divider1[13] ;
+ wire \soc.core.spi_master_clk_divider1[14] ;
+ wire \soc.core.spi_master_clk_divider1[15] ;
+ wire \soc.core.spi_master_clk_divider1[1] ;
+ wire \soc.core.spi_master_clk_divider1[2] ;
+ wire \soc.core.spi_master_clk_divider1[3] ;
+ wire \soc.core.spi_master_clk_divider1[4] ;
+ wire \soc.core.spi_master_clk_divider1[5] ;
+ wire \soc.core.spi_master_clk_divider1[6] ;
+ wire \soc.core.spi_master_clk_divider1[7] ;
+ wire \soc.core.spi_master_clk_divider1[8] ;
+ wire \soc.core.spi_master_clk_divider1[9] ;
+ wire \soc.core.spi_master_control_re ;
+ wire \soc.core.spi_master_control_storage[0] ;
+ wire \soc.core.spi_master_control_storage[10] ;
+ wire \soc.core.spi_master_control_storage[11] ;
+ wire \soc.core.spi_master_control_storage[12] ;
+ wire \soc.core.spi_master_control_storage[13] ;
+ wire \soc.core.spi_master_control_storage[14] ;
+ wire \soc.core.spi_master_control_storage[15] ;
+ wire \soc.core.spi_master_control_storage[1] ;
+ wire \soc.core.spi_master_control_storage[2] ;
+ wire \soc.core.spi_master_control_storage[3] ;
+ wire \soc.core.spi_master_control_storage[4] ;
+ wire \soc.core.spi_master_control_storage[5] ;
+ wire \soc.core.spi_master_control_storage[6] ;
+ wire \soc.core.spi_master_control_storage[7] ;
+ wire \soc.core.spi_master_control_storage[8] ;
+ wire \soc.core.spi_master_control_storage[9] ;
+ wire \soc.core.spi_master_count[0] ;
+ wire \soc.core.spi_master_count[1] ;
+ wire \soc.core.spi_master_count[2] ;
+ wire \soc.core.spi_master_cs ;
+ wire \soc.core.spi_master_cs_mode ;
+ wire \soc.core.spi_master_cs_storage[10] ;
+ wire \soc.core.spi_master_cs_storage[11] ;
+ wire \soc.core.spi_master_cs_storage[12] ;
+ wire \soc.core.spi_master_cs_storage[13] ;
+ wire \soc.core.spi_master_cs_storage[14] ;
+ wire \soc.core.spi_master_cs_storage[15] ;
+ wire \soc.core.spi_master_cs_storage[1] ;
+ wire \soc.core.spi_master_cs_storage[2] ;
+ wire \soc.core.spi_master_cs_storage[3] ;
+ wire \soc.core.spi_master_cs_storage[4] ;
+ wire \soc.core.spi_master_cs_storage[5] ;
+ wire \soc.core.spi_master_cs_storage[6] ;
+ wire \soc.core.spi_master_cs_storage[7] ;
+ wire \soc.core.spi_master_cs_storage[8] ;
+ wire \soc.core.spi_master_cs_storage[9] ;
+ wire \soc.core.spi_master_loopback_storage ;
+ wire \soc.core.spi_master_miso[0] ;
+ wire \soc.core.spi_master_miso[1] ;
+ wire \soc.core.spi_master_miso[2] ;
+ wire \soc.core.spi_master_miso[3] ;
+ wire \soc.core.spi_master_miso[4] ;
+ wire \soc.core.spi_master_miso[5] ;
+ wire \soc.core.spi_master_miso[6] ;
+ wire \soc.core.spi_master_miso[7] ;
+ wire \soc.core.spi_master_miso_data[0] ;
+ wire \soc.core.spi_master_miso_data[1] ;
+ wire \soc.core.spi_master_miso_data[2] ;
+ wire \soc.core.spi_master_miso_data[3] ;
+ wire \soc.core.spi_master_miso_data[4] ;
+ wire \soc.core.spi_master_miso_data[5] ;
+ wire \soc.core.spi_master_miso_data[6] ;
+ wire \soc.core.spi_master_miso_data[7] ;
+ wire \soc.core.spi_master_mosi_data[0] ;
+ wire \soc.core.spi_master_mosi_data[1] ;
+ wire \soc.core.spi_master_mosi_data[2] ;
+ wire \soc.core.spi_master_mosi_data[3] ;
+ wire \soc.core.spi_master_mosi_data[4] ;
+ wire \soc.core.spi_master_mosi_data[5] ;
+ wire \soc.core.spi_master_mosi_data[6] ;
+ wire \soc.core.spi_master_mosi_data[7] ;
+ wire \soc.core.spi_master_mosi_sel[0] ;
+ wire \soc.core.spi_master_mosi_sel[1] ;
+ wire \soc.core.spi_master_mosi_sel[2] ;
+ wire \soc.core.spi_master_mosi_storage[0] ;
+ wire \soc.core.spi_master_mosi_storage[1] ;
+ wire \soc.core.spi_master_mosi_storage[2] ;
+ wire \soc.core.spi_master_mosi_storage[3] ;
+ wire \soc.core.spi_master_mosi_storage[4] ;
+ wire \soc.core.spi_master_mosi_storage[5] ;
+ wire \soc.core.spi_master_mosi_storage[6] ;
+ wire \soc.core.spi_master_mosi_storage[7] ;
+ wire \soc.core.spi_miso ;
+ wire \soc.core.spi_mosi ;
+ wire \soc.core.spi_sdoenb ;
+ wire \soc.core.spimaster_state[0] ;
+ wire \soc.core.spimaster_state[1] ;
+ wire \soc.core.spimaster_storage[0] ;
+ wire \soc.core.spimaster_storage[10] ;
+ wire \soc.core.spimaster_storage[11] ;
+ wire \soc.core.spimaster_storage[12] ;
+ wire \soc.core.spimaster_storage[13] ;
+ wire \soc.core.spimaster_storage[14] ;
+ wire \soc.core.spimaster_storage[15] ;
+ wire \soc.core.spimaster_storage[1] ;
+ wire \soc.core.spimaster_storage[2] ;
+ wire \soc.core.spimaster_storage[3] ;
+ wire \soc.core.spimaster_storage[4] ;
+ wire \soc.core.spimaster_storage[5] ;
+ wire \soc.core.spimaster_storage[6] ;
+ wire \soc.core.spimaster_storage[7] ;
+ wire \soc.core.spimaster_storage[8] ;
+ wire \soc.core.spimaster_storage[9] ;
+ wire \soc.core.sram.ram512x32.GWEN ;
+ wire \soc.core.sram.ram512x32.WEN[0] ;
+ wire \soc.core.sram.ram512x32.WEN[1] ;
+ wire \soc.core.sram.ram512x32.WEN[2] ;
+ wire \soc.core.sram.ram512x32.WEN[3] ;
+ wire \soc.core.state ;
+ wire \soc.core.storage[0][0] ;
+ wire \soc.core.storage[0][1] ;
+ wire \soc.core.storage[0][2] ;
+ wire \soc.core.storage[0][3] ;
+ wire \soc.core.storage[0][4] ;
+ wire \soc.core.storage[0][5] ;
+ wire \soc.core.storage[0][6] ;
+ wire \soc.core.storage[0][7] ;
+ wire \soc.core.storage[10][0] ;
+ wire \soc.core.storage[10][1] ;
+ wire \soc.core.storage[10][2] ;
+ wire \soc.core.storage[10][3] ;
+ wire \soc.core.storage[10][4] ;
+ wire \soc.core.storage[10][5] ;
+ wire \soc.core.storage[10][6] ;
+ wire \soc.core.storage[10][7] ;
+ wire \soc.core.storage[11][0] ;
+ wire \soc.core.storage[11][1] ;
+ wire \soc.core.storage[11][2] ;
+ wire \soc.core.storage[11][3] ;
+ wire \soc.core.storage[11][4] ;
+ wire \soc.core.storage[11][5] ;
+ wire \soc.core.storage[11][6] ;
+ wire \soc.core.storage[11][7] ;
+ wire \soc.core.storage[12][0] ;
+ wire \soc.core.storage[12][1] ;
+ wire \soc.core.storage[12][2] ;
+ wire \soc.core.storage[12][3] ;
+ wire \soc.core.storage[12][4] ;
+ wire \soc.core.storage[12][5] ;
+ wire \soc.core.storage[12][6] ;
+ wire \soc.core.storage[12][7] ;
+ wire \soc.core.storage[13][0] ;
+ wire \soc.core.storage[13][1] ;
+ wire \soc.core.storage[13][2] ;
+ wire \soc.core.storage[13][3] ;
+ wire \soc.core.storage[13][4] ;
+ wire \soc.core.storage[13][5] ;
+ wire \soc.core.storage[13][6] ;
+ wire \soc.core.storage[13][7] ;
+ wire \soc.core.storage[14][0] ;
+ wire \soc.core.storage[14][1] ;
+ wire \soc.core.storage[14][2] ;
+ wire \soc.core.storage[14][3] ;
+ wire \soc.core.storage[14][4] ;
+ wire \soc.core.storage[14][5] ;
+ wire \soc.core.storage[14][6] ;
+ wire \soc.core.storage[14][7] ;
+ wire \soc.core.storage[15][0] ;
+ wire \soc.core.storage[15][1] ;
+ wire \soc.core.storage[15][2] ;
+ wire \soc.core.storage[15][3] ;
+ wire \soc.core.storage[15][4] ;
+ wire \soc.core.storage[15][5] ;
+ wire \soc.core.storage[15][6] ;
+ wire \soc.core.storage[15][7] ;
+ wire \soc.core.storage[1][0] ;
+ wire \soc.core.storage[1][1] ;
+ wire \soc.core.storage[1][2] ;
+ wire \soc.core.storage[1][3] ;
+ wire \soc.core.storage[1][4] ;
+ wire \soc.core.storage[1][5] ;
+ wire \soc.core.storage[1][6] ;
+ wire \soc.core.storage[1][7] ;
+ wire \soc.core.storage[2][0] ;
+ wire \soc.core.storage[2][1] ;
+ wire \soc.core.storage[2][2] ;
+ wire \soc.core.storage[2][3] ;
+ wire \soc.core.storage[2][4] ;
+ wire \soc.core.storage[2][5] ;
+ wire \soc.core.storage[2][6] ;
+ wire \soc.core.storage[2][7] ;
+ wire \soc.core.storage[3][0] ;
+ wire \soc.core.storage[3][1] ;
+ wire \soc.core.storage[3][2] ;
+ wire \soc.core.storage[3][3] ;
+ wire \soc.core.storage[3][4] ;
+ wire \soc.core.storage[3][5] ;
+ wire \soc.core.storage[3][6] ;
+ wire \soc.core.storage[3][7] ;
+ wire \soc.core.storage[4][0] ;
+ wire \soc.core.storage[4][1] ;
+ wire \soc.core.storage[4][2] ;
+ wire \soc.core.storage[4][3] ;
+ wire \soc.core.storage[4][4] ;
+ wire \soc.core.storage[4][5] ;
+ wire \soc.core.storage[4][6] ;
+ wire \soc.core.storage[4][7] ;
+ wire \soc.core.storage[5][0] ;
+ wire \soc.core.storage[5][1] ;
+ wire \soc.core.storage[5][2] ;
+ wire \soc.core.storage[5][3] ;
+ wire \soc.core.storage[5][4] ;
+ wire \soc.core.storage[5][5] ;
+ wire \soc.core.storage[5][6] ;
+ wire \soc.core.storage[5][7] ;
+ wire \soc.core.storage[6][0] ;
+ wire \soc.core.storage[6][1] ;
+ wire \soc.core.storage[6][2] ;
+ wire \soc.core.storage[6][3] ;
+ wire \soc.core.storage[6][4] ;
+ wire \soc.core.storage[6][5] ;
+ wire \soc.core.storage[6][6] ;
+ wire \soc.core.storage[6][7] ;
+ wire \soc.core.storage[7][0] ;
+ wire \soc.core.storage[7][1] ;
+ wire \soc.core.storage[7][2] ;
+ wire \soc.core.storage[7][3] ;
+ wire \soc.core.storage[7][4] ;
+ wire \soc.core.storage[7][5] ;
+ wire \soc.core.storage[7][6] ;
+ wire \soc.core.storage[7][7] ;
+ wire \soc.core.storage[8][0] ;
+ wire \soc.core.storage[8][1] ;
+ wire \soc.core.storage[8][2] ;
+ wire \soc.core.storage[8][3] ;
+ wire \soc.core.storage[8][4] ;
+ wire \soc.core.storage[8][5] ;
+ wire \soc.core.storage[8][6] ;
+ wire \soc.core.storage[8][7] ;
+ wire \soc.core.storage[9][0] ;
+ wire \soc.core.storage[9][1] ;
+ wire \soc.core.storage[9][2] ;
+ wire \soc.core.storage[9][3] ;
+ wire \soc.core.storage[9][4] ;
+ wire \soc.core.storage[9][5] ;
+ wire \soc.core.storage[9][6] ;
+ wire \soc.core.storage[9][7] ;
+ wire \soc.core.storage_1[0][0] ;
+ wire \soc.core.storage_1[0][1] ;
+ wire \soc.core.storage_1[0][2] ;
+ wire \soc.core.storage_1[0][3] ;
+ wire \soc.core.storage_1[0][4] ;
+ wire \soc.core.storage_1[0][5] ;
+ wire \soc.core.storage_1[0][6] ;
+ wire \soc.core.storage_1[0][7] ;
+ wire \soc.core.storage_1[10][0] ;
+ wire \soc.core.storage_1[10][1] ;
+ wire \soc.core.storage_1[10][2] ;
+ wire \soc.core.storage_1[10][3] ;
+ wire \soc.core.storage_1[10][4] ;
+ wire \soc.core.storage_1[10][5] ;
+ wire \soc.core.storage_1[10][6] ;
+ wire \soc.core.storage_1[10][7] ;
+ wire \soc.core.storage_1[11][0] ;
+ wire \soc.core.storage_1[11][1] ;
+ wire \soc.core.storage_1[11][2] ;
+ wire \soc.core.storage_1[11][3] ;
+ wire \soc.core.storage_1[11][4] ;
+ wire \soc.core.storage_1[11][5] ;
+ wire \soc.core.storage_1[11][6] ;
+ wire \soc.core.storage_1[11][7] ;
+ wire \soc.core.storage_1[12][0] ;
+ wire \soc.core.storage_1[12][1] ;
+ wire \soc.core.storage_1[12][2] ;
+ wire \soc.core.storage_1[12][3] ;
+ wire \soc.core.storage_1[12][4] ;
+ wire \soc.core.storage_1[12][5] ;
+ wire \soc.core.storage_1[12][6] ;
+ wire \soc.core.storage_1[12][7] ;
+ wire \soc.core.storage_1[13][0] ;
+ wire \soc.core.storage_1[13][1] ;
+ wire \soc.core.storage_1[13][2] ;
+ wire \soc.core.storage_1[13][3] ;
+ wire \soc.core.storage_1[13][4] ;
+ wire \soc.core.storage_1[13][5] ;
+ wire \soc.core.storage_1[13][6] ;
+ wire \soc.core.storage_1[13][7] ;
+ wire \soc.core.storage_1[14][0] ;
+ wire \soc.core.storage_1[14][1] ;
+ wire \soc.core.storage_1[14][2] ;
+ wire \soc.core.storage_1[14][3] ;
+ wire \soc.core.storage_1[14][4] ;
+ wire \soc.core.storage_1[14][5] ;
+ wire \soc.core.storage_1[14][6] ;
+ wire \soc.core.storage_1[14][7] ;
+ wire \soc.core.storage_1[15][0] ;
+ wire \soc.core.storage_1[15][1] ;
+ wire \soc.core.storage_1[15][2] ;
+ wire \soc.core.storage_1[15][3] ;
+ wire \soc.core.storage_1[15][4] ;
+ wire \soc.core.storage_1[15][5] ;
+ wire \soc.core.storage_1[15][6] ;
+ wire \soc.core.storage_1[15][7] ;
+ wire \soc.core.storage_1[1][0] ;
+ wire \soc.core.storage_1[1][1] ;
+ wire \soc.core.storage_1[1][2] ;
+ wire \soc.core.storage_1[1][3] ;
+ wire \soc.core.storage_1[1][4] ;
+ wire \soc.core.storage_1[1][5] ;
+ wire \soc.core.storage_1[1][6] ;
+ wire \soc.core.storage_1[1][7] ;
+ wire \soc.core.storage_1[2][0] ;
+ wire \soc.core.storage_1[2][1] ;
+ wire \soc.core.storage_1[2][2] ;
+ wire \soc.core.storage_1[2][3] ;
+ wire \soc.core.storage_1[2][4] ;
+ wire \soc.core.storage_1[2][5] ;
+ wire \soc.core.storage_1[2][6] ;
+ wire \soc.core.storage_1[2][7] ;
+ wire \soc.core.storage_1[3][0] ;
+ wire \soc.core.storage_1[3][1] ;
+ wire \soc.core.storage_1[3][2] ;
+ wire \soc.core.storage_1[3][3] ;
+ wire \soc.core.storage_1[3][4] ;
+ wire \soc.core.storage_1[3][5] ;
+ wire \soc.core.storage_1[3][6] ;
+ wire \soc.core.storage_1[3][7] ;
+ wire \soc.core.storage_1[4][0] ;
+ wire \soc.core.storage_1[4][1] ;
+ wire \soc.core.storage_1[4][2] ;
+ wire \soc.core.storage_1[4][3] ;
+ wire \soc.core.storage_1[4][4] ;
+ wire \soc.core.storage_1[4][5] ;
+ wire \soc.core.storage_1[4][6] ;
+ wire \soc.core.storage_1[4][7] ;
+ wire \soc.core.storage_1[5][0] ;
+ wire \soc.core.storage_1[5][1] ;
+ wire \soc.core.storage_1[5][2] ;
+ wire \soc.core.storage_1[5][3] ;
+ wire \soc.core.storage_1[5][4] ;
+ wire \soc.core.storage_1[5][5] ;
+ wire \soc.core.storage_1[5][6] ;
+ wire \soc.core.storage_1[5][7] ;
+ wire \soc.core.storage_1[6][0] ;
+ wire \soc.core.storage_1[6][1] ;
+ wire \soc.core.storage_1[6][2] ;
+ wire \soc.core.storage_1[6][3] ;
+ wire \soc.core.storage_1[6][4] ;
+ wire \soc.core.storage_1[6][5] ;
+ wire \soc.core.storage_1[6][6] ;
+ wire \soc.core.storage_1[6][7] ;
+ wire \soc.core.storage_1[7][0] ;
+ wire \soc.core.storage_1[7][1] ;
+ wire \soc.core.storage_1[7][2] ;
+ wire \soc.core.storage_1[7][3] ;
+ wire \soc.core.storage_1[7][4] ;
+ wire \soc.core.storage_1[7][5] ;
+ wire \soc.core.storage_1[7][6] ;
+ wire \soc.core.storage_1[7][7] ;
+ wire \soc.core.storage_1[8][0] ;
+ wire \soc.core.storage_1[8][1] ;
+ wire \soc.core.storage_1[8][2] ;
+ wire \soc.core.storage_1[8][3] ;
+ wire \soc.core.storage_1[8][4] ;
+ wire \soc.core.storage_1[8][5] ;
+ wire \soc.core.storage_1[8][6] ;
+ wire \soc.core.storage_1[8][7] ;
+ wire \soc.core.storage_1[9][0] ;
+ wire \soc.core.storage_1[9][1] ;
+ wire \soc.core.storage_1[9][2] ;
+ wire \soc.core.storage_1[9][3] ;
+ wire \soc.core.storage_1[9][4] ;
+ wire \soc.core.storage_1[9][5] ;
+ wire \soc.core.storage_1[9][6] ;
+ wire \soc.core.storage_1[9][7] ;
+ wire \soc.core.sys_uart_tx ;
+ wire \soc.core.uart_enabled ;
+ wire \soc.core.uart_enabled_storage ;
+ wire \soc.core.uart_irq ;
+ wire \soc.core.uart_pending_r[0] ;
+ wire \soc.core.uart_pending_r[1] ;
+ wire \soc.core.uart_pending_re ;
+ wire \soc.core.uart_phy_rx_count[0] ;
+ wire \soc.core.uart_phy_rx_count[1] ;
+ wire \soc.core.uart_phy_rx_count[2] ;
+ wire \soc.core.uart_phy_rx_count[3] ;
+ wire \soc.core.uart_phy_rx_data[0] ;
+ wire \soc.core.uart_phy_rx_data[1] ;
+ wire \soc.core.uart_phy_rx_data[2] ;
+ wire \soc.core.uart_phy_rx_data[3] ;
+ wire \soc.core.uart_phy_rx_data[4] ;
+ wire \soc.core.uart_phy_rx_data[5] ;
+ wire \soc.core.uart_phy_rx_data[6] ;
+ wire \soc.core.uart_phy_rx_data[7] ;
+ wire \soc.core.uart_phy_rx_phase[10] ;
+ wire \soc.core.uart_phy_rx_phase[11] ;
+ wire \soc.core.uart_phy_rx_phase[12] ;
+ wire \soc.core.uart_phy_rx_phase[13] ;
+ wire \soc.core.uart_phy_rx_phase[14] ;
+ wire \soc.core.uart_phy_rx_phase[15] ;
+ wire \soc.core.uart_phy_rx_phase[16] ;
+ wire \soc.core.uart_phy_rx_phase[17] ;
+ wire \soc.core.uart_phy_rx_phase[18] ;
+ wire \soc.core.uart_phy_rx_phase[19] ;
+ wire \soc.core.uart_phy_rx_phase[20] ;
+ wire \soc.core.uart_phy_rx_phase[21] ;
+ wire \soc.core.uart_phy_rx_phase[22] ;
+ wire \soc.core.uart_phy_rx_phase[23] ;
+ wire \soc.core.uart_phy_rx_phase[24] ;
+ wire \soc.core.uart_phy_rx_phase[25] ;
+ wire \soc.core.uart_phy_rx_phase[26] ;
+ wire \soc.core.uart_phy_rx_phase[27] ;
+ wire \soc.core.uart_phy_rx_phase[28] ;
+ wire \soc.core.uart_phy_rx_phase[29] ;
+ wire \soc.core.uart_phy_rx_phase[30] ;
+ wire \soc.core.uart_phy_rx_phase[31] ;
+ wire \soc.core.uart_phy_rx_phase[5] ;
+ wire \soc.core.uart_phy_rx_phase[6] ;
+ wire \soc.core.uart_phy_rx_phase[7] ;
+ wire \soc.core.uart_phy_rx_phase[8] ;
+ wire \soc.core.uart_phy_rx_phase[9] ;
+ wire \soc.core.uart_phy_rx_rx_d ;
+ wire \soc.core.uart_phy_rx_tick ;
+ wire \soc.core.uart_phy_tx_count[0] ;
+ wire \soc.core.uart_phy_tx_count[1] ;
+ wire \soc.core.uart_phy_tx_count[2] ;
+ wire \soc.core.uart_phy_tx_count[3] ;
+ wire \soc.core.uart_phy_tx_data[0] ;
+ wire \soc.core.uart_phy_tx_data[1] ;
+ wire \soc.core.uart_phy_tx_data[2] ;
+ wire \soc.core.uart_phy_tx_data[3] ;
+ wire \soc.core.uart_phy_tx_data[4] ;
+ wire \soc.core.uart_phy_tx_data[5] ;
+ wire \soc.core.uart_phy_tx_data[6] ;
+ wire \soc.core.uart_phy_tx_data[7] ;
+ wire \soc.core.uart_phy_tx_phase[10] ;
+ wire \soc.core.uart_phy_tx_phase[11] ;
+ wire \soc.core.uart_phy_tx_phase[12] ;
+ wire \soc.core.uart_phy_tx_phase[13] ;
+ wire \soc.core.uart_phy_tx_phase[14] ;
+ wire \soc.core.uart_phy_tx_phase[15] ;
+ wire \soc.core.uart_phy_tx_phase[16] ;
+ wire \soc.core.uart_phy_tx_phase[17] ;
+ wire \soc.core.uart_phy_tx_phase[18] ;
+ wire \soc.core.uart_phy_tx_phase[19] ;
+ wire \soc.core.uart_phy_tx_phase[20] ;
+ wire \soc.core.uart_phy_tx_phase[21] ;
+ wire \soc.core.uart_phy_tx_phase[22] ;
+ wire \soc.core.uart_phy_tx_phase[23] ;
+ wire \soc.core.uart_phy_tx_phase[24] ;
+ wire \soc.core.uart_phy_tx_phase[25] ;
+ wire \soc.core.uart_phy_tx_phase[26] ;
+ wire \soc.core.uart_phy_tx_phase[27] ;
+ wire \soc.core.uart_phy_tx_phase[28] ;
+ wire \soc.core.uart_phy_tx_phase[29] ;
+ wire \soc.core.uart_phy_tx_phase[30] ;
+ wire \soc.core.uart_phy_tx_phase[31] ;
+ wire \soc.core.uart_phy_tx_phase[5] ;
+ wire \soc.core.uart_phy_tx_phase[6] ;
+ wire \soc.core.uart_phy_tx_phase[7] ;
+ wire \soc.core.uart_phy_tx_phase[8] ;
+ wire \soc.core.uart_phy_tx_phase[9] ;
+ wire \soc.core.uart_phy_tx_tick ;
+ wire \soc.core.uart_rx2 ;
+ wire \soc.core.uart_rx_fifo_consume[0] ;
+ wire \soc.core.uart_rx_fifo_consume[1] ;
+ wire \soc.core.uart_rx_fifo_consume[2] ;
+ wire \soc.core.uart_rx_fifo_consume[3] ;
+ wire \soc.core.uart_rx_fifo_level0[0] ;
+ wire \soc.core.uart_rx_fifo_level0[1] ;
+ wire \soc.core.uart_rx_fifo_level0[2] ;
+ wire \soc.core.uart_rx_fifo_level0[3] ;
+ wire \soc.core.uart_rx_fifo_level0[4] ;
+ wire \soc.core.uart_rx_fifo_produce[0] ;
+ wire \soc.core.uart_rx_fifo_produce[1] ;
+ wire \soc.core.uart_rx_fifo_produce[2] ;
+ wire \soc.core.uart_rx_fifo_produce[3] ;
+ wire \soc.core.uart_rx_fifo_readable ;
+ wire \soc.core.uart_rx_pending ;
+ wire \soc.core.uart_rx_trigger_d ;
+ wire \soc.core.uart_tx2 ;
+ wire \soc.core.uart_tx_fifo_consume[0] ;
+ wire \soc.core.uart_tx_fifo_consume[1] ;
+ wire \soc.core.uart_tx_fifo_consume[2] ;
+ wire \soc.core.uart_tx_fifo_consume[3] ;
+ wire \soc.core.uart_tx_fifo_level0[0] ;
+ wire \soc.core.uart_tx_fifo_level0[1] ;
+ wire \soc.core.uart_tx_fifo_level0[2] ;
+ wire \soc.core.uart_tx_fifo_level0[3] ;
+ wire \soc.core.uart_tx_fifo_level0[4] ;
+ wire \soc.core.uart_tx_fifo_produce[0] ;
+ wire \soc.core.uart_tx_fifo_produce[1] ;
+ wire \soc.core.uart_tx_fifo_produce[2] ;
+ wire \soc.core.uart_tx_fifo_produce[3] ;
+ wire \soc.core.uart_tx_fifo_readable ;
+ wire \soc.core.uart_tx_pending ;
+ wire \soc.core.uart_tx_trigger_d ;
+ wire \soc.core.uartwishbonebridge_rs232phyrx_state ;
+ wire \soc.core.uartwishbonebridge_rs232phytx_state ;
+ wire \soc.core.uartwishbonebridge_state[0] ;
+ wire \soc.core.uartwishbonebridge_state[1] ;
+ wire \soc.core.uartwishbonebridge_state[2] ;
+ wire \soc.core.user_irq_ena_storage[0] ;
+ wire \soc.core.user_irq_ena_storage[1] ;
+ wire \soc.core.user_irq_ena_storage[2] ;
+ wire \spare_xfq_nc[0] ;
+ wire \spare_xfq_nc[1] ;
+ wire \spare_xfq_nc[2] ;
+ wire \spare_xfq_nc[3] ;
+ wire \spare_xfq_nc[4] ;
+ wire \spare_xfq_nc[5] ;
+ wire \spare_xfq_nc[6] ;
+ wire \spare_xfq_nc[7] ;
+ wire \spare_xi_nc[0] ;
+ wire \spare_xi_nc[10] ;
+ wire \spare_xi_nc[11] ;
+ wire \spare_xi_nc[12] ;
+ wire \spare_xi_nc[13] ;
+ wire \spare_xi_nc[14] ;
+ wire \spare_xi_nc[15] ;
+ wire \spare_xi_nc[1] ;
+ wire \spare_xi_nc[2] ;
+ wire \spare_xi_nc[3] ;
+ wire \spare_xi_nc[4] ;
+ wire \spare_xi_nc[5] ;
+ wire \spare_xi_nc[6] ;
+ wire \spare_xi_nc[7] ;
+ wire \spare_xi_nc[8] ;
+ wire \spare_xi_nc[9] ;
+ wire \spare_xib_nc[0] ;
+ wire \spare_xib_nc[1] ;
+ wire \spare_xib_nc[2] ;
+ wire \spare_xib_nc[3] ;
+ wire \spare_xmx_nc[0] ;
+ wire \spare_xmx_nc[1] ;
+ wire \spare_xmx_nc[2] ;
+ wire \spare_xmx_nc[3] ;
+ wire \spare_xmx_nc[4] ;
+ wire \spare_xmx_nc[5] ;
+ wire \spare_xmx_nc[6] ;
+ wire \spare_xmx_nc[7] ;
+ wire \spare_xna_nc[0] ;
+ wire \spare_xna_nc[1] ;
+ wire \spare_xna_nc[2] ;
+ wire \spare_xna_nc[3] ;
+ wire \spare_xna_nc[4] ;
+ wire \spare_xna_nc[5] ;
+ wire \spare_xna_nc[6] ;
+ wire \spare_xna_nc[7] ;
+ wire \spare_xno_nc[0] ;
+ wire \spare_xno_nc[1] ;
+ wire \spare_xno_nc[2] ;
+ wire \spare_xno_nc[3] ;
+ wire \spare_xno_nc[4] ;
+ wire \spare_xno_nc[5] ;
+ wire \spare_xno_nc[6] ;
+ wire \spare_xno_nc[7] ;
+ wire \spare_xz_nc[0] ;
+ wire \spare_xz_nc[100] ;
+ wire \spare_xz_nc[101] ;
+ wire \spare_xz_nc[102] ;
+ wire \spare_xz_nc[103] ;
+ wire \spare_xz_nc[104] ;
+ wire \spare_xz_nc[105] ;
+ wire \spare_xz_nc[106] ;
+ wire \spare_xz_nc[107] ;
+ wire \spare_xz_nc[108] ;
+ wire \spare_xz_nc[109] ;
+ wire \spare_xz_nc[10] ;
+ wire \spare_xz_nc[110] ;
+ wire \spare_xz_nc[111] ;
+ wire \spare_xz_nc[112] ;
+ wire \spare_xz_nc[113] ;
+ wire \spare_xz_nc[114] ;
+ wire \spare_xz_nc[115] ;
+ wire \spare_xz_nc[116] ;
+ wire \spare_xz_nc[117] ;
+ wire \spare_xz_nc[118] ;
+ wire \spare_xz_nc[119] ;
+ wire \spare_xz_nc[11] ;
+ wire \spare_xz_nc[120] ;
+ wire \spare_xz_nc[121] ;
+ wire \spare_xz_nc[122] ;
+ wire \spare_xz_nc[123] ;
+ wire \spare_xz_nc[12] ;
+ wire \spare_xz_nc[13] ;
+ wire \spare_xz_nc[14] ;
+ wire \spare_xz_nc[15] ;
+ wire \spare_xz_nc[16] ;
+ wire \spare_xz_nc[17] ;
+ wire \spare_xz_nc[18] ;
+ wire \spare_xz_nc[19] ;
+ wire \spare_xz_nc[1] ;
+ wire \spare_xz_nc[20] ;
+ wire \spare_xz_nc[21] ;
+ wire \spare_xz_nc[22] ;
+ wire \spare_xz_nc[23] ;
+ wire \spare_xz_nc[24] ;
+ wire \spare_xz_nc[25] ;
+ wire \spare_xz_nc[26] ;
+ wire \spare_xz_nc[27] ;
+ wire \spare_xz_nc[28] ;
+ wire \spare_xz_nc[29] ;
+ wire \spare_xz_nc[2] ;
+ wire \spare_xz_nc[30] ;
+ wire \spare_xz_nc[31] ;
+ wire \spare_xz_nc[32] ;
+ wire \spare_xz_nc[33] ;
+ wire \spare_xz_nc[34] ;
+ wire \spare_xz_nc[35] ;
+ wire \spare_xz_nc[36] ;
+ wire \spare_xz_nc[37] ;
+ wire \spare_xz_nc[38] ;
+ wire \spare_xz_nc[39] ;
+ wire \spare_xz_nc[3] ;
+ wire \spare_xz_nc[40] ;
+ wire \spare_xz_nc[41] ;
+ wire \spare_xz_nc[42] ;
+ wire \spare_xz_nc[43] ;
+ wire \spare_xz_nc[44] ;
+ wire \spare_xz_nc[45] ;
+ wire \spare_xz_nc[46] ;
+ wire \spare_xz_nc[47] ;
+ wire \spare_xz_nc[48] ;
+ wire \spare_xz_nc[49] ;
+ wire \spare_xz_nc[4] ;
+ wire \spare_xz_nc[50] ;
+ wire \spare_xz_nc[51] ;
+ wire \spare_xz_nc[52] ;
+ wire \spare_xz_nc[53] ;
+ wire \spare_xz_nc[54] ;
+ wire \spare_xz_nc[55] ;
+ wire \spare_xz_nc[56] ;
+ wire \spare_xz_nc[57] ;
+ wire \spare_xz_nc[58] ;
+ wire \spare_xz_nc[59] ;
+ wire \spare_xz_nc[5] ;
+ wire \spare_xz_nc[60] ;
+ wire \spare_xz_nc[61] ;
+ wire \spare_xz_nc[62] ;
+ wire \spare_xz_nc[63] ;
+ wire \spare_xz_nc[64] ;
+ wire \spare_xz_nc[65] ;
+ wire \spare_xz_nc[66] ;
+ wire \spare_xz_nc[67] ;
+ wire \spare_xz_nc[68] ;
+ wire \spare_xz_nc[69] ;
+ wire \spare_xz_nc[6] ;
+ wire \spare_xz_nc[70] ;
+ wire \spare_xz_nc[71] ;
+ wire \spare_xz_nc[72] ;
+ wire \spare_xz_nc[73] ;
+ wire \spare_xz_nc[74] ;
+ wire \spare_xz_nc[75] ;
+ wire \spare_xz_nc[76] ;
+ wire \spare_xz_nc[77] ;
+ wire \spare_xz_nc[78] ;
+ wire \spare_xz_nc[79] ;
+ wire \spare_xz_nc[7] ;
+ wire \spare_xz_nc[80] ;
+ wire \spare_xz_nc[81] ;
+ wire \spare_xz_nc[82] ;
+ wire \spare_xz_nc[83] ;
+ wire \spare_xz_nc[84] ;
+ wire \spare_xz_nc[85] ;
+ wire \spare_xz_nc[86] ;
+ wire \spare_xz_nc[87] ;
+ wire \spare_xz_nc[88] ;
+ wire \spare_xz_nc[89] ;
+ wire \spare_xz_nc[8] ;
+ wire \spare_xz_nc[90] ;
+ wire \spare_xz_nc[91] ;
+ wire \spare_xz_nc[92] ;
+ wire \spare_xz_nc[93] ;
+ wire \spare_xz_nc[94] ;
+ wire \spare_xz_nc[95] ;
+ wire \spare_xz_nc[96] ;
+ wire \spare_xz_nc[97] ;
+ wire \spare_xz_nc[98] ;
+ wire \spare_xz_nc[99] ;
+ wire \spare_xz_nc[9] ;
+ wire \user_io_oeb[0] ;
+ wire \user_io_oeb[10] ;
+ wire \user_io_oeb[11] ;
+ wire \user_io_oeb[12] ;
+ wire \user_io_oeb[13] ;
+ wire \user_io_oeb[14] ;
+ wire \user_io_oeb[15] ;
+ wire \user_io_oeb[16] ;
+ wire \user_io_oeb[17] ;
+ wire \user_io_oeb[18] ;
+ wire \user_io_oeb[19] ;
+ wire \user_io_oeb[1] ;
+ wire \user_io_oeb[20] ;
+ wire \user_io_oeb[21] ;
+ wire \user_io_oeb[22] ;
+ wire \user_io_oeb[23] ;
+ wire \user_io_oeb[24] ;
+ wire \user_io_oeb[25] ;
+ wire \user_io_oeb[26] ;
+ wire \user_io_oeb[27] ;
+ wire \user_io_oeb[28] ;
+ wire \user_io_oeb[29] ;
+ wire \user_io_oeb[2] ;
+ wire \user_io_oeb[30] ;
+ wire \user_io_oeb[31] ;
+ wire \user_io_oeb[32] ;
+ wire \user_io_oeb[33] ;
+ wire \user_io_oeb[34] ;
+ wire \user_io_oeb[35] ;
+ wire \user_io_oeb[36] ;
+ wire \user_io_oeb[37] ;
+ wire \user_io_oeb[3] ;
+ wire \user_io_oeb[4] ;
+ wire \user_io_oeb[5] ;
+ wire \user_io_oeb[6] ;
+ wire \user_io_oeb[7] ;
+ wire \user_io_oeb[8] ;
+ wire \user_io_oeb[9] ;
+ wire \user_io_out[0] ;
+ wire \user_io_out[10] ;
+ wire \user_io_out[11] ;
+ wire \user_io_out[12] ;
+ wire \user_io_out[13] ;
+ wire \user_io_out[14] ;
+ wire \user_io_out[15] ;
+ wire \user_io_out[16] ;
+ wire \user_io_out[17] ;
+ wire \user_io_out[18] ;
+ wire \user_io_out[19] ;
+ wire \user_io_out[1] ;
+ wire \user_io_out[20] ;
+ wire \user_io_out[21] ;
+ wire \user_io_out[22] ;
+ wire \user_io_out[23] ;
+ wire \user_io_out[24] ;
+ wire \user_io_out[25] ;
+ wire \user_io_out[26] ;
+ wire \user_io_out[27] ;
+ wire \user_io_out[28] ;
+ wire \user_io_out[29] ;
+ wire \user_io_out[2] ;
+ wire \user_io_out[30] ;
+ wire \user_io_out[31] ;
+ wire \user_io_out[32] ;
+ wire \user_io_out[33] ;
+ wire \user_io_out[34] ;
+ wire \user_io_out[35] ;
+ wire \user_io_out[36] ;
+ wire \user_io_out[37] ;
+ wire \user_io_out[3] ;
+ wire \user_io_out[4] ;
+ wire \user_io_out[5] ;
+ wire \user_io_out[6] ;
+ wire \user_io_out[7] ;
+ wire \user_io_out[8] ;
+ wire \user_io_out[9] ;
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+ wire net1734;
+ wire net1735;
+ wire net1736;
+ wire net1737;
+ wire net1738;
+ wire net1739;
+ wire net1740;
+ wire net1741;
+ wire net1742;
+ wire net1743;
+ wire net1744;
+ wire net1745;
+ wire net1746;
+ wire net1747;
+ wire net1748;
+ wire net1749;
+ wire net1750;
+ wire net1751;
+ wire net1752;
+ wire net1753;
+ wire net1754;
+ wire net1755;
+ wire net1756;
+ wire net1757;
+ wire net1758;
+ wire net1759;
+ wire net1760;
+ wire net1761;
+ wire net1762;
+ wire net1763;
+ wire net1764;
+ wire net1765;
+ wire net1766;
+ wire net1767;
+ wire net1768;
+ wire net1769;
+ wire net1770;
+ wire net1771;
+ wire net1772;
+ wire net1773;
+ wire net1774;
+ wire net1775;
+ wire net1776;
+ wire net1777;
+ wire net1778;
+ wire net1779;
+ wire net1780;
+ wire net1781;
+ wire net1782;
+ wire net1783;
+ wire net1784;
+ wire net1785;
+ wire net1786;
+ wire net1787;
+ wire net1788;
+ wire net1789;
+ wire net1790;
+ wire net1791;
+ wire net1792;
+ wire net1793;
+ wire net1794;
+ wire net1795;
+ wire net1796;
+ wire net1797;
+ wire net1798;
+ wire net1799;
+ wire net1800;
+ wire net1801;
+ wire net1802;
+ wire net1803;
+ wire net1804;
+ wire net1805;
+ wire net1806;
+ wire net1807;
+ wire net1808;
+ wire net1809;
+ wire net1810;
+ wire net1811;
+ wire net1812;
+ wire net1813;
+ wire net1814;
+ wire net1815;
+ wire net1816;
+ wire net1817;
+ wire net1818;
+ wire net1819;
+ wire net1820;
+ wire net1821;
+ wire net1822;
+ wire net1823;
+ wire net1824;
+ wire net1825;
+ wire net1826;
+ wire net1827;
+ wire net1828;
+ wire net1829;
+ wire net1830;
+ wire net1831;
+ wire net1832;
+ wire net1833;
+ wire net1834;
+ wire net1835;
+ wire net1836;
+ wire net1837;
+ wire net1838;
+ wire net1839;
+ wire net1840;
+ wire net1841;
+ wire net1842;
+ wire net1843;
+ wire net1844;
+ wire net1845;
+ wire net1846;
+ wire net1847;
+ wire net1848;
+ wire net1849;
+ wire net1850;
+ wire net1851;
+ wire net1852;
+ wire net1853;
+ wire net1854;
+ wire net1855;
+ wire net1856;
+ wire net1857;
+ wire net1858;
+ wire net1859;
+ wire net1860;
+ wire net1861;
+ wire net1862;
+ wire net1863;
+ wire net1864;
+ wire net1865;
+ wire net1866;
+ wire net1867;
+ wire net1868;
+ wire net1869;
+ wire net1870;
+ wire net1871;
+ wire net1872;
+ wire net1873;
+ wire net1874;
+ wire net1875;
+ wire net1876;
+ wire net1877;
+ wire net1878;
+ wire net1879;
+ wire net1880;
+ wire net1881;
+ wire net1882;
+ wire net1883;
+ wire net1884;
+ wire net1885;
+ wire net1886;
+ wire net1887;
+ wire net1888;
+ wire net1889;
+ wire net1890;
+ wire net1891;
+ wire net1892;
+ wire net1893;
+ wire net1894;
+ wire net1895;
+ wire net1896;
+ wire net1897;
+ wire net1898;
+ wire net1899;
+ wire net1900;
+ wire net1901;
+ wire net1902;
+ wire net1903;
+ wire net1904;
+ wire net1905;
+ wire net1906;
+ wire net1907;
+ wire net1908;
+ wire net1909;
+ wire net1910;
+ wire net1911;
+ wire net1912;
+ wire net1913;
+ wire net1914;
+ wire net1915;
+ wire net1916;
+ wire net1917;
+ wire net1918;
+ wire net1919;
+ wire net1920;
+ wire net1921;
+ wire net1922;
+ wire net1923;
+ wire net1924;
+ wire net1925;
+ wire net1926;
+ wire net1927;
+ wire net1928;
+ wire net1929;
+ wire net1930;
+ wire net1931;
+ wire net1932;
+ wire net1933;
+ wire net1934;
+ wire net1935;
+ wire net1936;
+ wire net1937;
+ wire net1938;
+ wire net1939;
+ wire net1940;
+ wire net1941;
+ wire net1942;
+ wire net1943;
+ wire net1944;
+ wire net1945;
+ wire net1946;
+ wire net1947;
+ wire net1948;
+ wire net1949;
+ wire net1950;
+ wire net1951;
+ wire net1952;
+ wire net1953;
+ wire net1954;
+ wire net1955;
+ wire net1956;
+ wire net1957;
+ wire net1958;
+ wire net1959;
+ wire net1960;
+ wire net1961;
+ wire net1962;
+ wire net1963;
+ wire net1964;
+ wire net1965;
+ wire net1966;
+ wire net1967;
+ wire net1968;
+ wire net1969;
+ wire net1970;
+ wire net1971;
+ wire net1972;
+ wire net1973;
+ wire net1974;
+ wire net1975;
+ wire net1976;
+ wire net1977;
+ wire net1978;
+ wire net1979;
+ wire net1980;
+ wire net1981;
+ wire net1982;
+ wire net1983;
+ wire net1984;
+ wire net1985;
+ wire net1986;
+ wire net1987;
+ wire net1988;
+ wire net1989;
+ wire net1990;
+ wire net1991;
+ wire net1992;
+ wire net1993;
+ wire net1994;
+ wire net1995;
+ wire net1996;
+ wire net1997;
+ wire net1998;
+ wire net1999;
+ wire net2000;
+ wire net2001;
+ wire net2002;
+ wire net2003;
+ wire net2004;
+ wire net2005;
+ wire net2006;
+ wire net2007;
+ wire net2008;
+ wire net2009;
+ wire net2010;
+ wire net2011;
+ wire net2012;
+ wire net2013;
+ wire net2014;
+ wire net2015;
+ wire net2016;
+ wire net2017;
+ wire net2018;
+ wire net2019;
+ wire net2020;
+ wire net2021;
+ wire net2022;
+ wire net2023;
+ wire net2024;
+ wire net2025;
+ wire net2026;
+ wire net2027;
+ wire net2028;
+ wire net2029;
+ wire net2030;
+ wire net2031;
+ wire net2032;
+ wire net2033;
+ wire net2034;
+ wire net2035;
+ wire net2036;
+ wire net2037;
+ wire net2038;
+ wire net2039;
+ wire net2040;
+ wire net2041;
+ wire net2042;
+ wire net2043;
+ wire net2044;
+ wire net2045;
+ wire net2046;
+ wire net2047;
+ wire net2048;
+ wire net2049;
+ wire net2050;
+ wire net2051;
+ wire net2052;
+ wire net2053;
+ wire net2054;
+ wire net2055;
+ wire net2056;
+ wire net2057;
+ wire net2058;
+ wire net2059;
+ wire net2060;
+ wire net2061;
+ wire net2062;
+ wire net2063;
+ wire net2064;
+ wire net2065;
+ wire net2066;
+ wire net2067;
+ wire net2068;
+ wire net2069;
+ wire net2070;
+ wire net2071;
+ wire net2072;
+ wire net2073;
+ wire net2074;
+ wire net2075;
+ wire net2076;
+ wire net2077;
+ wire net2078;
+ wire net2079;
+ wire net2080;
+ wire net2081;
+ wire net2082;
+ wire net2083;
+ wire net2084;
+ wire net2085;
+ wire net2086;
+ wire net2087;
+ wire net2088;
+ wire net2089;
+ wire net2090;
+ wire net2091;
+ wire net2092;
+ wire net2093;
+ wire net2094;
+ wire net2095;
+ wire net2096;
+ wire net2097;
+ wire net2098;
+ wire net2099;
+ wire net2100;
+ wire net2101;
+ wire net2102;
+ wire net2103;
+ wire net2104;
+ wire net2105;
+ wire net2106;
+ wire net2107;
+ wire net2108;
+ wire net2109;
+ wire net2110;
+ wire net2111;
+ wire net2112;
+ wire net2113;
+ wire net2114;
+ wire net2115;
+ wire net2116;
+ wire net2117;
+ wire net2118;
+ wire net2119;
+ wire net2120;
+ wire net2121;
+ wire net2122;
+ wire net2123;
+ wire net2124;
+ wire net2125;
+ wire net2126;
+ wire net2127;
+ wire net2128;
+ wire net2129;
+ wire net2130;
+ wire net2131;
+ wire net2132;
+ wire net2133;
+ wire net2134;
+ wire net2135;
+ wire net2136;
+ wire net2137;
+ wire net2138;
+ wire net2139;
+ wire net2140;
+ wire net2141;
+ wire net2142;
+ wire net2143;
+ wire net2144;
+ wire net2145;
+ wire net2146;
+ wire net2147;
+ wire net2148;
+ wire net2149;
+ wire net2150;
+ wire net2151;
+ wire net2152;
+ wire net2153;
+ wire net2154;
+ wire net2155;
+ wire net2156;
+ wire net2157;
+ wire net2158;
+ wire net2159;
+ wire net2160;
+ wire net2161;
+ wire net2162;
+ wire net2163;
+ wire net2164;
+ wire net2165;
+ wire net2166;
+ wire net2167;
+ wire net2168;
+ wire net2169;
+ wire net2170;
+ wire net2171;
+ wire net2172;
+ wire net2173;
+ wire net2174;
+ wire net2175;
+ wire net2176;
+ wire net2177;
+ wire net2178;
+ wire net2179;
+ wire net2180;
+ wire net2181;
+ wire net2182;
+ wire net2183;
+ wire net2184;
+ wire net2185;
+ wire net2186;
+ wire net2187;
+ wire net2188;
+ wire net2189;
+ wire net2190;
+ wire net2191;
+ wire net2192;
+ wire net2193;
+ wire net2194;
+ wire net2195;
+ wire net2196;
+ wire net2197;
+ wire net2198;
+ wire net2199;
+ wire net2200;
+ wire net2201;
+ wire net2202;
+ wire net2203;
+ wire net2204;
+ wire net2205;
+ wire net2206;
+ wire net2207;
+ wire net2208;
+ wire net2209;
+ wire net2210;
+ wire net2211;
+ wire net2212;
+ wire net2213;
+ wire net2214;
+ wire net2215;
+ wire net2216;
+ wire net2217;
+ wire net2218;
+ wire net2219;
+ wire net2220;
+ wire net2221;
+ wire net2222;
+ wire net2223;
+ wire net2224;
+ wire net2225;
+ wire net2226;
+ wire net2227;
+ wire net2228;
+ wire net2229;
+ wire net2230;
+ wire net2231;
+ wire net2232;
+ wire net2233;
+ wire net2234;
+ wire net2235;
+ wire net2236;
+ wire net2237;
+ wire net2238;
+ wire net2239;
+ wire net2240;
+ wire net2241;
+ wire net2242;
+ wire net2243;
+ wire net2244;
+ wire net2245;
+ wire net2246;
+ wire net2247;
+ wire net2248;
+ wire net2249;
+ wire net2250;
+ wire net2251;
+ wire net2252;
+ wire net2253;
+ wire net2254;
+ wire net2255;
+ wire net2256;
+ wire net2257;
+ wire net2258;
+ wire net2259;
+ wire net2260;
+ wire net2261;
+ wire net2262;
+ wire net2263;
+ wire net2264;
+ wire net2265;
+ wire net2266;
+ wire net2267;
+ wire net2268;
+ wire net2269;
+ wire net2270;
+ wire net2271;
+ wire net2272;
+ wire net2273;
+ wire net2274;
+ wire net2275;
+ wire net2276;
+ wire net2277;
+ wire net2278;
+ wire net2279;
+ wire net2280;
+ wire net2281;
+ wire net2282;
+ wire net2283;
+ wire net2284;
+ wire net2285;
+ wire net2286;
+ wire \clknet_leaf_4_clock_ctrl.core_clk ;
+ wire \clknet_leaf_5_clock_ctrl.core_clk ;
+ wire \clknet_leaf_6_clock_ctrl.core_clk ;
+ wire \clknet_leaf_7_clock_ctrl.core_clk ;
+ wire \clknet_leaf_8_clock_ctrl.core_clk ;
+ wire \clknet_leaf_9_clock_ctrl.core_clk ;
+ wire \clknet_leaf_10_clock_ctrl.core_clk ;
+ wire \clknet_leaf_11_clock_ctrl.core_clk ;
+ wire \clknet_leaf_12_clock_ctrl.core_clk ;
+ wire \clknet_leaf_13_clock_ctrl.core_clk ;
+ wire \clknet_leaf_14_clock_ctrl.core_clk ;
+ wire \clknet_leaf_15_clock_ctrl.core_clk ;
+ wire \clknet_leaf_16_clock_ctrl.core_clk ;
+ wire \clknet_leaf_17_clock_ctrl.core_clk ;
+ wire \clknet_leaf_18_clock_ctrl.core_clk ;
+ wire \clknet_leaf_19_clock_ctrl.core_clk ;
+ wire \clknet_leaf_20_clock_ctrl.core_clk ;
+ wire \clknet_leaf_23_clock_ctrl.core_clk ;
+ wire \clknet_leaf_24_clock_ctrl.core_clk ;
+ wire \clknet_leaf_25_clock_ctrl.core_clk ;
+ wire \clknet_leaf_26_clock_ctrl.core_clk ;
+ wire \clknet_leaf_27_clock_ctrl.core_clk ;
+ wire \clknet_leaf_28_clock_ctrl.core_clk ;
+ wire \clknet_leaf_30_clock_ctrl.core_clk ;
+ wire \clknet_leaf_31_clock_ctrl.core_clk ;
+ wire \clknet_leaf_33_clock_ctrl.core_clk ;
+ wire \clknet_leaf_34_clock_ctrl.core_clk ;
+ wire \clknet_leaf_35_clock_ctrl.core_clk ;
+ wire \clknet_leaf_36_clock_ctrl.core_clk ;
+ wire \clknet_leaf_37_clock_ctrl.core_clk ;
+ wire \clknet_leaf_38_clock_ctrl.core_clk ;
+ wire \clknet_leaf_39_clock_ctrl.core_clk ;
+ wire \clknet_leaf_40_clock_ctrl.core_clk ;
+ wire \clknet_leaf_41_clock_ctrl.core_clk ;
+ wire \clknet_leaf_42_clock_ctrl.core_clk ;
+ wire \clknet_leaf_43_clock_ctrl.core_clk ;
+ wire \clknet_leaf_44_clock_ctrl.core_clk ;
+ wire \clknet_leaf_45_clock_ctrl.core_clk ;
+ wire \clknet_leaf_46_clock_ctrl.core_clk ;
+ wire \clknet_leaf_48_clock_ctrl.core_clk ;
+ wire \clknet_leaf_49_clock_ctrl.core_clk ;
+ wire \clknet_leaf_50_clock_ctrl.core_clk ;
+ wire \clknet_leaf_51_clock_ctrl.core_clk ;
+ wire \clknet_leaf_52_clock_ctrl.core_clk ;
+ wire \clknet_leaf_53_clock_ctrl.core_clk ;
+ wire \clknet_leaf_54_clock_ctrl.core_clk ;
+ wire \clknet_leaf_55_clock_ctrl.core_clk ;
+ wire \clknet_leaf_56_clock_ctrl.core_clk ;
+ wire \clknet_leaf_57_clock_ctrl.core_clk ;
+ wire \clknet_leaf_58_clock_ctrl.core_clk ;
+ wire \clknet_leaf_59_clock_ctrl.core_clk ;
+ wire \clknet_leaf_60_clock_ctrl.core_clk ;
+ wire \clknet_leaf_61_clock_ctrl.core_clk ;
+ wire \clknet_leaf_62_clock_ctrl.core_clk ;
+ wire \clknet_leaf_63_clock_ctrl.core_clk ;
+ wire \clknet_leaf_64_clock_ctrl.core_clk ;
+ wire \clknet_leaf_66_clock_ctrl.core_clk ;
+ wire \clknet_leaf_67_clock_ctrl.core_clk ;
+ wire \clknet_leaf_68_clock_ctrl.core_clk ;
+ wire \clknet_leaf_69_clock_ctrl.core_clk ;
+ wire \clknet_leaf_70_clock_ctrl.core_clk ;
+ wire \clknet_leaf_71_clock_ctrl.core_clk ;
+ wire \clknet_leaf_72_clock_ctrl.core_clk ;
+ wire \clknet_leaf_73_clock_ctrl.core_clk ;
+ wire \clknet_leaf_74_clock_ctrl.core_clk ;
+ wire \clknet_leaf_75_clock_ctrl.core_clk ;
+ wire \clknet_leaf_76_clock_ctrl.core_clk ;
+ wire \clknet_leaf_77_clock_ctrl.core_clk ;
+ wire \clknet_leaf_79_clock_ctrl.core_clk ;
+ wire \clknet_leaf_80_clock_ctrl.core_clk ;
+ wire \clknet_leaf_81_clock_ctrl.core_clk ;
+ wire \clknet_leaf_82_clock_ctrl.core_clk ;
+ wire \clknet_leaf_83_clock_ctrl.core_clk ;
+ wire \clknet_leaf_84_clock_ctrl.core_clk ;
+ wire \clknet_leaf_85_clock_ctrl.core_clk ;
+ wire \clknet_leaf_86_clock_ctrl.core_clk ;
+ wire \clknet_leaf_87_clock_ctrl.core_clk ;
+ wire \clknet_leaf_88_clock_ctrl.core_clk ;
+ wire \clknet_leaf_89_clock_ctrl.core_clk ;
+ wire \clknet_leaf_90_clock_ctrl.core_clk ;
+ wire \clknet_leaf_91_clock_ctrl.core_clk ;
+ wire \clknet_leaf_92_clock_ctrl.core_clk ;
+ wire \clknet_leaf_93_clock_ctrl.core_clk ;
+ wire \clknet_leaf_94_clock_ctrl.core_clk ;
+ wire \clknet_leaf_95_clock_ctrl.core_clk ;
+ wire \clknet_leaf_98_clock_ctrl.core_clk ;
+ wire \clknet_leaf_99_clock_ctrl.core_clk ;
+ wire \clknet_leaf_100_clock_ctrl.core_clk ;
+ wire \clknet_leaf_101_clock_ctrl.core_clk ;
+ wire \clknet_leaf_102_clock_ctrl.core_clk ;
+ wire \clknet_leaf_103_clock_ctrl.core_clk ;
+ wire \clknet_leaf_104_clock_ctrl.core_clk ;
+ wire \clknet_leaf_105_clock_ctrl.core_clk ;
+ wire \clknet_leaf_106_clock_ctrl.core_clk ;
+ wire \clknet_leaf_107_clock_ctrl.core_clk ;
+ wire \clknet_leaf_108_clock_ctrl.core_clk ;
+ wire \clknet_leaf_109_clock_ctrl.core_clk ;
+ wire \clknet_leaf_110_clock_ctrl.core_clk ;
+ wire \clknet_leaf_111_clock_ctrl.core_clk ;
+ wire \clknet_leaf_112_clock_ctrl.core_clk ;
+ wire \clknet_leaf_113_clock_ctrl.core_clk ;
+ wire \clknet_leaf_114_clock_ctrl.core_clk ;
+ wire \clknet_leaf_115_clock_ctrl.core_clk ;
+ wire \clknet_leaf_117_clock_ctrl.core_clk ;
+ wire \clknet_leaf_118_clock_ctrl.core_clk ;
+ wire \clknet_leaf_119_clock_ctrl.core_clk ;
+ wire \clknet_leaf_120_clock_ctrl.core_clk ;
+ wire \clknet_leaf_121_clock_ctrl.core_clk ;
+ wire \clknet_leaf_122_clock_ctrl.core_clk ;
+ wire \clknet_leaf_123_clock_ctrl.core_clk ;
+ wire \clknet_leaf_124_clock_ctrl.core_clk ;
+ wire \clknet_leaf_125_clock_ctrl.core_clk ;
+ wire \clknet_leaf_126_clock_ctrl.core_clk ;
+ wire \clknet_leaf_127_clock_ctrl.core_clk ;
+ wire \clknet_leaf_128_clock_ctrl.core_clk ;
+ wire \clknet_leaf_129_clock_ctrl.core_clk ;
+ wire \clknet_leaf_130_clock_ctrl.core_clk ;
+ wire \clknet_leaf_131_clock_ctrl.core_clk ;
+ wire \clknet_leaf_132_clock_ctrl.core_clk ;
+ wire \clknet_leaf_133_clock_ctrl.core_clk ;
+ wire \clknet_leaf_134_clock_ctrl.core_clk ;
+ wire \clknet_leaf_135_clock_ctrl.core_clk ;
+ wire \clknet_leaf_136_clock_ctrl.core_clk ;
+ wire \clknet_leaf_137_clock_ctrl.core_clk ;
+ wire \clknet_leaf_138_clock_ctrl.core_clk ;
+ wire \clknet_leaf_139_clock_ctrl.core_clk ;
+ wire \clknet_leaf_140_clock_ctrl.core_clk ;
+ wire \clknet_leaf_141_clock_ctrl.core_clk ;
+ wire \clknet_leaf_142_clock_ctrl.core_clk ;
+ wire \clknet_leaf_143_clock_ctrl.core_clk ;
+ wire \clknet_leaf_144_clock_ctrl.core_clk ;
+ wire \clknet_leaf_145_clock_ctrl.core_clk ;
+ wire \clknet_leaf_147_clock_ctrl.core_clk ;
+ wire \clknet_leaf_149_clock_ctrl.core_clk ;
+ wire \clknet_leaf_150_clock_ctrl.core_clk ;
+ wire \clknet_leaf_151_clock_ctrl.core_clk ;
+ wire \clknet_leaf_152_clock_ctrl.core_clk ;
+ wire \clknet_leaf_153_clock_ctrl.core_clk ;
+ wire \clknet_leaf_154_clock_ctrl.core_clk ;
+ wire \clknet_leaf_155_clock_ctrl.core_clk ;
+ wire \clknet_leaf_156_clock_ctrl.core_clk ;
+ wire \clknet_leaf_157_clock_ctrl.core_clk ;
+ wire \clknet_leaf_159_clock_ctrl.core_clk ;
+ wire \clknet_leaf_160_clock_ctrl.core_clk ;
+ wire \clknet_leaf_161_clock_ctrl.core_clk ;
+ wire \clknet_leaf_162_clock_ctrl.core_clk ;
+ wire \clknet_leaf_163_clock_ctrl.core_clk ;
+ wire \clknet_leaf_164_clock_ctrl.core_clk ;
+ wire \clknet_leaf_165_clock_ctrl.core_clk ;
+ wire \clknet_leaf_166_clock_ctrl.core_clk ;
+ wire \clknet_leaf_167_clock_ctrl.core_clk ;
+ wire \clknet_leaf_168_clock_ctrl.core_clk ;
+ wire \clknet_leaf_169_clock_ctrl.core_clk ;
+ wire \clknet_leaf_170_clock_ctrl.core_clk ;
+ wire \clknet_leaf_171_clock_ctrl.core_clk ;
+ wire \clknet_leaf_172_clock_ctrl.core_clk ;
+ wire \clknet_leaf_173_clock_ctrl.core_clk ;
+ wire \clknet_leaf_174_clock_ctrl.core_clk ;
+ wire \clknet_leaf_176_clock_ctrl.core_clk ;
+ wire \clknet_leaf_177_clock_ctrl.core_clk ;
+ wire \clknet_leaf_178_clock_ctrl.core_clk ;
+ wire \clknet_leaf_179_clock_ctrl.core_clk ;
+ wire \clknet_leaf_180_clock_ctrl.core_clk ;
+ wire \clknet_leaf_181_clock_ctrl.core_clk ;
+ wire \clknet_leaf_182_clock_ctrl.core_clk ;
+ wire \clknet_leaf_183_clock_ctrl.core_clk ;
+ wire \clknet_leaf_185_clock_ctrl.core_clk ;
+ wire \clknet_leaf_186_clock_ctrl.core_clk ;
+ wire \clknet_leaf_188_clock_ctrl.core_clk ;
+ wire \clknet_leaf_189_clock_ctrl.core_clk ;
+ wire \clknet_leaf_190_clock_ctrl.core_clk ;
+ wire \clknet_leaf_191_clock_ctrl.core_clk ;
+ wire \clknet_leaf_192_clock_ctrl.core_clk ;
+ wire \clknet_leaf_193_clock_ctrl.core_clk ;
+ wire \clknet_leaf_194_clock_ctrl.core_clk ;
+ wire \clknet_leaf_195_clock_ctrl.core_clk ;
+ wire \clknet_leaf_196_clock_ctrl.core_clk ;
+ wire \clknet_leaf_197_clock_ctrl.core_clk ;
+ wire \clknet_leaf_198_clock_ctrl.core_clk ;
+ wire \clknet_leaf_199_clock_ctrl.core_clk ;
+ wire \clknet_leaf_200_clock_ctrl.core_clk ;
+ wire \clknet_leaf_201_clock_ctrl.core_clk ;
+ wire \clknet_leaf_202_clock_ctrl.core_clk ;
+ wire \clknet_leaf_204_clock_ctrl.core_clk ;
+ wire \clknet_leaf_205_clock_ctrl.core_clk ;
+ wire \clknet_leaf_206_clock_ctrl.core_clk ;
+ wire \clknet_leaf_207_clock_ctrl.core_clk ;
+ wire \clknet_leaf_208_clock_ctrl.core_clk ;
+ wire \clknet_leaf_209_clock_ctrl.core_clk ;
+ wire \clknet_leaf_210_clock_ctrl.core_clk ;
+ wire \clknet_leaf_211_clock_ctrl.core_clk ;
+ wire \clknet_leaf_212_clock_ctrl.core_clk ;
+ wire \clknet_leaf_213_clock_ctrl.core_clk ;
+ wire \clknet_leaf_214_clock_ctrl.core_clk ;
+ wire \clknet_leaf_215_clock_ctrl.core_clk ;
+ wire \clknet_leaf_216_clock_ctrl.core_clk ;
+ wire \clknet_leaf_217_clock_ctrl.core_clk ;
+ wire \clknet_leaf_218_clock_ctrl.core_clk ;
+ wire \clknet_leaf_219_clock_ctrl.core_clk ;
+ wire \clknet_leaf_220_clock_ctrl.core_clk ;
+ wire \clknet_leaf_221_clock_ctrl.core_clk ;
+ wire \clknet_leaf_223_clock_ctrl.core_clk ;
+ wire \clknet_leaf_224_clock_ctrl.core_clk ;
+ wire \clknet_leaf_225_clock_ctrl.core_clk ;
+ wire \clknet_leaf_226_clock_ctrl.core_clk ;
+ wire \clknet_leaf_227_clock_ctrl.core_clk ;
+ wire \clknet_leaf_228_clock_ctrl.core_clk ;
+ wire \clknet_leaf_229_clock_ctrl.core_clk ;
+ wire \clknet_leaf_230_clock_ctrl.core_clk ;
+ wire \clknet_leaf_231_clock_ctrl.core_clk ;
+ wire \clknet_leaf_232_clock_ctrl.core_clk ;
+ wire \clknet_leaf_233_clock_ctrl.core_clk ;
+ wire \clknet_leaf_235_clock_ctrl.core_clk ;
+ wire \clknet_leaf_237_clock_ctrl.core_clk ;
+ wire \clknet_leaf_238_clock_ctrl.core_clk ;
+ wire \clknet_leaf_239_clock_ctrl.core_clk ;
+ wire \clknet_leaf_240_clock_ctrl.core_clk ;
+ wire \clknet_leaf_241_clock_ctrl.core_clk ;
+ wire \clknet_leaf_242_clock_ctrl.core_clk ;
+ wire \clknet_leaf_243_clock_ctrl.core_clk ;
+ wire \clknet_leaf_245_clock_ctrl.core_clk ;
+ wire \clknet_leaf_246_clock_ctrl.core_clk ;
+ wire \clknet_leaf_247_clock_ctrl.core_clk ;
+ wire \clknet_leaf_248_clock_ctrl.core_clk ;
+ wire \clknet_leaf_249_clock_ctrl.core_clk ;
+ wire \clknet_leaf_250_clock_ctrl.core_clk ;
+ wire \clknet_leaf_251_clock_ctrl.core_clk ;
+ wire \clknet_leaf_252_clock_ctrl.core_clk ;
+ wire \clknet_leaf_253_clock_ctrl.core_clk ;
+ wire \clknet_leaf_254_clock_ctrl.core_clk ;
+ wire \clknet_leaf_255_clock_ctrl.core_clk ;
+ wire \clknet_leaf_256_clock_ctrl.core_clk ;
+ wire \clknet_leaf_257_clock_ctrl.core_clk ;
+ wire \clknet_leaf_258_clock_ctrl.core_clk ;
+ wire \clknet_leaf_260_clock_ctrl.core_clk ;
+ wire \clknet_leaf_261_clock_ctrl.core_clk ;
+ wire \clknet_leaf_262_clock_ctrl.core_clk ;
+ wire \clknet_leaf_263_clock_ctrl.core_clk ;
+ wire \clknet_leaf_264_clock_ctrl.core_clk ;
+ wire \clknet_leaf_265_clock_ctrl.core_clk ;
+ wire \clknet_leaf_266_clock_ctrl.core_clk ;
+ wire \clknet_leaf_267_clock_ctrl.core_clk ;
+ wire \clknet_leaf_268_clock_ctrl.core_clk ;
+ wire \clknet_leaf_269_clock_ctrl.core_clk ;
+ wire \clknet_leaf_270_clock_ctrl.core_clk ;
+ wire \clknet_leaf_271_clock_ctrl.core_clk ;
+ wire \clknet_leaf_272_clock_ctrl.core_clk ;
+ wire \clknet_leaf_273_clock_ctrl.core_clk ;
+ wire \clknet_leaf_274_clock_ctrl.core_clk ;
+ wire \clknet_leaf_275_clock_ctrl.core_clk ;
+ wire \clknet_leaf_276_clock_ctrl.core_clk ;
+ wire \clknet_leaf_277_clock_ctrl.core_clk ;
+ wire \clknet_leaf_278_clock_ctrl.core_clk ;
+ wire \clknet_leaf_279_clock_ctrl.core_clk ;
+ wire \clknet_leaf_280_clock_ctrl.core_clk ;
+ wire \clknet_leaf_281_clock_ctrl.core_clk ;
+ wire \clknet_leaf_282_clock_ctrl.core_clk ;
+ wire \clknet_leaf_284_clock_ctrl.core_clk ;
+ wire \clknet_leaf_285_clock_ctrl.core_clk ;
+ wire \clknet_leaf_286_clock_ctrl.core_clk ;
+ wire \clknet_leaf_287_clock_ctrl.core_clk ;
+ wire \clknet_leaf_288_clock_ctrl.core_clk ;
+ wire \clknet_leaf_289_clock_ctrl.core_clk ;
+ wire \clknet_leaf_290_clock_ctrl.core_clk ;
+ wire \clknet_leaf_291_clock_ctrl.core_clk ;
+ wire \clknet_leaf_292_clock_ctrl.core_clk ;
+ wire \clknet_leaf_293_clock_ctrl.core_clk ;
+ wire \clknet_leaf_294_clock_ctrl.core_clk ;
+ wire \clknet_leaf_295_clock_ctrl.core_clk ;
+ wire \clknet_leaf_296_clock_ctrl.core_clk ;
+ wire \clknet_leaf_297_clock_ctrl.core_clk ;
+ wire \clknet_leaf_298_clock_ctrl.core_clk ;
+ wire \clknet_leaf_299_clock_ctrl.core_clk ;
+ wire \clknet_leaf_300_clock_ctrl.core_clk ;
+ wire \clknet_leaf_301_clock_ctrl.core_clk ;
+ wire \clknet_leaf_302_clock_ctrl.core_clk ;
+ wire \clknet_leaf_303_clock_ctrl.core_clk ;
+ wire \clknet_leaf_304_clock_ctrl.core_clk ;
+ wire \clknet_leaf_305_clock_ctrl.core_clk ;
+ wire \clknet_leaf_306_clock_ctrl.core_clk ;
+ wire \clknet_leaf_307_clock_ctrl.core_clk ;
+ wire \clknet_leaf_308_clock_ctrl.core_clk ;
+ wire \clknet_leaf_309_clock_ctrl.core_clk ;
+ wire \clknet_leaf_310_clock_ctrl.core_clk ;
+ wire \clknet_leaf_311_clock_ctrl.core_clk ;
+ wire \clknet_leaf_313_clock_ctrl.core_clk ;
+ wire \clknet_leaf_314_clock_ctrl.core_clk ;
+ wire \clknet_leaf_315_clock_ctrl.core_clk ;
+ wire \clknet_leaf_316_clock_ctrl.core_clk ;
+ wire \clknet_leaf_318_clock_ctrl.core_clk ;
+ wire \clknet_leaf_319_clock_ctrl.core_clk ;
+ wire \clknet_leaf_320_clock_ctrl.core_clk ;
+ wire \clknet_leaf_321_clock_ctrl.core_clk ;
+ wire \clknet_leaf_322_clock_ctrl.core_clk ;
+ wire \clknet_leaf_323_clock_ctrl.core_clk ;
+ wire \clknet_leaf_324_clock_ctrl.core_clk ;
+ wire \clknet_leaf_325_clock_ctrl.core_clk ;
+ wire \clknet_leaf_326_clock_ctrl.core_clk ;
+ wire \clknet_leaf_327_clock_ctrl.core_clk ;
+ wire \clknet_leaf_328_clock_ctrl.core_clk ;
+ wire \clknet_leaf_329_clock_ctrl.core_clk ;
+ wire \clknet_leaf_330_clock_ctrl.core_clk ;
+ wire \clknet_leaf_331_clock_ctrl.core_clk ;
+ wire \clknet_leaf_332_clock_ctrl.core_clk ;
+ wire \clknet_leaf_333_clock_ctrl.core_clk ;
+ wire \clknet_leaf_334_clock_ctrl.core_clk ;
+ wire \clknet_leaf_335_clock_ctrl.core_clk ;
+ wire \clknet_leaf_336_clock_ctrl.core_clk ;
+ wire \clknet_leaf_337_clock_ctrl.core_clk ;
+ wire \clknet_leaf_338_clock_ctrl.core_clk ;
+ wire \clknet_leaf_340_clock_ctrl.core_clk ;
+ wire \clknet_leaf_341_clock_ctrl.core_clk ;
+ wire \clknet_leaf_342_clock_ctrl.core_clk ;
+ wire \clknet_leaf_343_clock_ctrl.core_clk ;
+ wire \clknet_leaf_344_clock_ctrl.core_clk ;
+ wire \clknet_leaf_346_clock_ctrl.core_clk ;
+ wire \clknet_leaf_347_clock_ctrl.core_clk ;
+ wire \clknet_leaf_348_clock_ctrl.core_clk ;
+ wire \clknet_leaf_349_clock_ctrl.core_clk ;
+ wire \clknet_leaf_350_clock_ctrl.core_clk ;
+ wire \clknet_leaf_351_clock_ctrl.core_clk ;
+ wire \clknet_leaf_352_clock_ctrl.core_clk ;
+ wire \clknet_leaf_353_clock_ctrl.core_clk ;
+ wire \clknet_leaf_354_clock_ctrl.core_clk ;
+ wire \clknet_leaf_355_clock_ctrl.core_clk ;
+ wire \clknet_leaf_356_clock_ctrl.core_clk ;
+ wire \clknet_leaf_358_clock_ctrl.core_clk ;
+ wire \clknet_leaf_360_clock_ctrl.core_clk ;
+ wire \clknet_leaf_361_clock_ctrl.core_clk ;
+ wire \clknet_leaf_362_clock_ctrl.core_clk ;
+ wire \clknet_leaf_363_clock_ctrl.core_clk ;
+ wire \clknet_leaf_364_clock_ctrl.core_clk ;
+ wire \clknet_leaf_365_clock_ctrl.core_clk ;
+ wire \clknet_leaf_366_clock_ctrl.core_clk ;
+ wire \clknet_leaf_367_clock_ctrl.core_clk ;
+ wire \clknet_leaf_368_clock_ctrl.core_clk ;
+ wire \clknet_leaf_369_clock_ctrl.core_clk ;
+ wire \clknet_leaf_370_clock_ctrl.core_clk ;
+ wire \clknet_leaf_371_clock_ctrl.core_clk ;
+ wire \clknet_leaf_372_clock_ctrl.core_clk ;
+ wire \clknet_leaf_373_clock_ctrl.core_clk ;
+ wire \clknet_leaf_374_clock_ctrl.core_clk ;
+ wire \clknet_leaf_375_clock_ctrl.core_clk ;
+ wire \clknet_leaf_376_clock_ctrl.core_clk ;
+ wire \clknet_leaf_377_clock_ctrl.core_clk ;
+ wire \clknet_leaf_378_clock_ctrl.core_clk ;
+ wire \clknet_leaf_379_clock_ctrl.core_clk ;
+ wire \clknet_leaf_380_clock_ctrl.core_clk ;
+ wire \clknet_leaf_381_clock_ctrl.core_clk ;
+ wire \clknet_leaf_382_clock_ctrl.core_clk ;
+ wire \clknet_leaf_383_clock_ctrl.core_clk ;
+ wire \clknet_leaf_385_clock_ctrl.core_clk ;
+ wire \clknet_leaf_386_clock_ctrl.core_clk ;
+ wire \clknet_leaf_388_clock_ctrl.core_clk ;
+ wire \clknet_leaf_389_clock_ctrl.core_clk ;
+ wire \clknet_leaf_390_clock_ctrl.core_clk ;
+ wire \clknet_leaf_391_clock_ctrl.core_clk ;
+ wire \clknet_leaf_392_clock_ctrl.core_clk ;
+ wire \clknet_leaf_393_clock_ctrl.core_clk ;
+ wire \clknet_leaf_394_clock_ctrl.core_clk ;
+ wire \clknet_leaf_395_clock_ctrl.core_clk ;
+ wire \clknet_leaf_396_clock_ctrl.core_clk ;
+ wire \clknet_leaf_399_clock_ctrl.core_clk ;
+ wire \clknet_leaf_400_clock_ctrl.core_clk ;
+ wire \clknet_leaf_401_clock_ctrl.core_clk ;
+ wire \clknet_leaf_402_clock_ctrl.core_clk ;
+ wire \clknet_leaf_403_clock_ctrl.core_clk ;
+ wire \clknet_leaf_404_clock_ctrl.core_clk ;
+ wire \clknet_leaf_405_clock_ctrl.core_clk ;
+ wire \clknet_leaf_406_clock_ctrl.core_clk ;
+ wire \clknet_leaf_407_clock_ctrl.core_clk ;
+ wire \clknet_leaf_410_clock_ctrl.core_clk ;
+ wire \clknet_leaf_411_clock_ctrl.core_clk ;
+ wire \clknet_leaf_412_clock_ctrl.core_clk ;
+ wire \clknet_leaf_413_clock_ctrl.core_clk ;
+ wire \clknet_leaf_414_clock_ctrl.core_clk ;
+ wire \clknet_leaf_416_clock_ctrl.core_clk ;
+ wire \clknet_leaf_417_clock_ctrl.core_clk ;
+ wire \clknet_leaf_418_clock_ctrl.core_clk ;
+ wire \clknet_leaf_419_clock_ctrl.core_clk ;
+ wire \clknet_leaf_420_clock_ctrl.core_clk ;
+ wire \clknet_leaf_422_clock_ctrl.core_clk ;
+ wire \clknet_leaf_423_clock_ctrl.core_clk ;
+ wire \clknet_leaf_424_clock_ctrl.core_clk ;
+ wire \clknet_leaf_425_clock_ctrl.core_clk ;
+ wire \clknet_leaf_427_clock_ctrl.core_clk ;
+ wire \clknet_leaf_428_clock_ctrl.core_clk ;
+ wire \clknet_leaf_429_clock_ctrl.core_clk ;
+ wire \clknet_leaf_430_clock_ctrl.core_clk ;
+ wire \clknet_leaf_431_clock_ctrl.core_clk ;
+ wire \clknet_leaf_432_clock_ctrl.core_clk ;
+ wire \clknet_leaf_433_clock_ctrl.core_clk ;
+ wire \clknet_leaf_434_clock_ctrl.core_clk ;
+ wire \clknet_leaf_436_clock_ctrl.core_clk ;
+ wire \clknet_leaf_437_clock_ctrl.core_clk ;
+ wire \clknet_leaf_438_clock_ctrl.core_clk ;
+ wire \clknet_leaf_439_clock_ctrl.core_clk ;
+ wire \clknet_leaf_440_clock_ctrl.core_clk ;
+ wire \clknet_leaf_441_clock_ctrl.core_clk ;
+ wire \clknet_leaf_442_clock_ctrl.core_clk ;
+ wire \clknet_leaf_443_clock_ctrl.core_clk ;
+ wire \clknet_leaf_444_clock_ctrl.core_clk ;
+ wire \clknet_leaf_445_clock_ctrl.core_clk ;
+ wire \clknet_leaf_446_clock_ctrl.core_clk ;
+ wire \clknet_leaf_447_clock_ctrl.core_clk ;
+ wire \clknet_leaf_448_clock_ctrl.core_clk ;
+ wire \clknet_leaf_449_clock_ctrl.core_clk ;
+ wire \clknet_leaf_450_clock_ctrl.core_clk ;
+ wire \clknet_leaf_451_clock_ctrl.core_clk ;
+ wire \clknet_leaf_452_clock_ctrl.core_clk ;
+ wire \clknet_leaf_453_clock_ctrl.core_clk ;
+ wire \clknet_leaf_454_clock_ctrl.core_clk ;
+ wire \clknet_leaf_455_clock_ctrl.core_clk ;
+ wire \clknet_leaf_456_clock_ctrl.core_clk ;
+ wire \clknet_leaf_457_clock_ctrl.core_clk ;
+ wire \clknet_leaf_458_clock_ctrl.core_clk ;
+ wire \clknet_leaf_459_clock_ctrl.core_clk ;
+ wire \clknet_leaf_460_clock_ctrl.core_clk ;
+ wire \clknet_leaf_461_clock_ctrl.core_clk ;
+ wire \clknet_leaf_462_clock_ctrl.core_clk ;
+ wire \clknet_leaf_463_clock_ctrl.core_clk ;
+ wire \clknet_leaf_464_clock_ctrl.core_clk ;
+ wire \clknet_leaf_465_clock_ctrl.core_clk ;
+ wire \clknet_leaf_466_clock_ctrl.core_clk ;
+ wire \clknet_leaf_467_clock_ctrl.core_clk ;
+ wire \clknet_leaf_468_clock_ctrl.core_clk ;
+ wire \clknet_leaf_469_clock_ctrl.core_clk ;
+ wire \clknet_leaf_470_clock_ctrl.core_clk ;
+ wire \clknet_leaf_471_clock_ctrl.core_clk ;
+ wire \clknet_leaf_472_clock_ctrl.core_clk ;
+ wire \clknet_leaf_473_clock_ctrl.core_clk ;
+ wire \clknet_leaf_474_clock_ctrl.core_clk ;
+ wire \clknet_leaf_476_clock_ctrl.core_clk ;
+ wire \clknet_leaf_477_clock_ctrl.core_clk ;
+ wire \clknet_leaf_478_clock_ctrl.core_clk ;
+ wire \clknet_leaf_479_clock_ctrl.core_clk ;
+ wire \clknet_leaf_480_clock_ctrl.core_clk ;
+ wire \clknet_leaf_482_clock_ctrl.core_clk ;
+ wire \clknet_leaf_484_clock_ctrl.core_clk ;
+ wire \clknet_leaf_485_clock_ctrl.core_clk ;
+ wire \clknet_leaf_487_clock_ctrl.core_clk ;
+ wire \clknet_leaf_488_clock_ctrl.core_clk ;
+ wire \clknet_leaf_489_clock_ctrl.core_clk ;
+ wire \clknet_leaf_490_clock_ctrl.core_clk ;
+ wire \clknet_leaf_491_clock_ctrl.core_clk ;
+ wire \clknet_leaf_492_clock_ctrl.core_clk ;
+ wire \clknet_leaf_493_clock_ctrl.core_clk ;
+ wire \clknet_leaf_494_clock_ctrl.core_clk ;
+ wire \clknet_leaf_495_clock_ctrl.core_clk ;
+ wire \clknet_leaf_496_clock_ctrl.core_clk ;
+ wire \clknet_leaf_497_clock_ctrl.core_clk ;
+ wire \clknet_leaf_498_clock_ctrl.core_clk ;
+ wire \clknet_leaf_499_clock_ctrl.core_clk ;
+ wire \clknet_leaf_500_clock_ctrl.core_clk ;
+ wire \clknet_leaf_501_clock_ctrl.core_clk ;
+ wire \clknet_leaf_502_clock_ctrl.core_clk ;
+ wire \clknet_leaf_503_clock_ctrl.core_clk ;
+ wire \clknet_leaf_504_clock_ctrl.core_clk ;
+ wire \clknet_leaf_505_clock_ctrl.core_clk ;
+ wire \clknet_leaf_506_clock_ctrl.core_clk ;
+ wire \clknet_leaf_507_clock_ctrl.core_clk ;
+ wire \clknet_leaf_508_clock_ctrl.core_clk ;
+ wire \clknet_leaf_509_clock_ctrl.core_clk ;
+ wire \clknet_leaf_510_clock_ctrl.core_clk ;
+ wire \clknet_leaf_511_clock_ctrl.core_clk ;
+ wire \clknet_leaf_512_clock_ctrl.core_clk ;
+ wire \clknet_leaf_513_clock_ctrl.core_clk ;
+ wire \clknet_leaf_514_clock_ctrl.core_clk ;
+ wire \clknet_leaf_515_clock_ctrl.core_clk ;
+ wire \clknet_leaf_516_clock_ctrl.core_clk ;
+ wire \clknet_leaf_519_clock_ctrl.core_clk ;
+ wire \clknet_leaf_520_clock_ctrl.core_clk ;
+ wire \clknet_leaf_521_clock_ctrl.core_clk ;
+ wire \clknet_leaf_522_clock_ctrl.core_clk ;
+ wire \clknet_leaf_523_clock_ctrl.core_clk ;
+ wire \clknet_leaf_524_clock_ctrl.core_clk ;
+ wire \clknet_leaf_525_clock_ctrl.core_clk ;
+ wire \clknet_leaf_526_clock_ctrl.core_clk ;
+ wire \clknet_leaf_527_clock_ctrl.core_clk ;
+ wire \clknet_leaf_528_clock_ctrl.core_clk ;
+ wire \clknet_leaf_529_clock_ctrl.core_clk ;
+ wire \clknet_leaf_530_clock_ctrl.core_clk ;
+ wire \clknet_leaf_531_clock_ctrl.core_clk ;
+ wire \clknet_leaf_532_clock_ctrl.core_clk ;
+ wire \clknet_leaf_533_clock_ctrl.core_clk ;
+ wire \clknet_leaf_534_clock_ctrl.core_clk ;
+ wire \clknet_leaf_535_clock_ctrl.core_clk ;
+ wire \clknet_leaf_536_clock_ctrl.core_clk ;
+ wire \clknet_leaf_537_clock_ctrl.core_clk ;
+ wire \clknet_leaf_538_clock_ctrl.core_clk ;
+ wire \clknet_leaf_539_clock_ctrl.core_clk ;
+ wire \clknet_leaf_540_clock_ctrl.core_clk ;
+ wire \clknet_leaf_542_clock_ctrl.core_clk ;
+ wire \clknet_leaf_543_clock_ctrl.core_clk ;
+ wire \clknet_leaf_544_clock_ctrl.core_clk ;
+ wire \clknet_leaf_545_clock_ctrl.core_clk ;
+ wire \clknet_leaf_546_clock_ctrl.core_clk ;
+ wire \clknet_leaf_547_clock_ctrl.core_clk ;
+ wire \clknet_leaf_548_clock_ctrl.core_clk ;
+ wire \clknet_leaf_549_clock_ctrl.core_clk ;
+ wire \clknet_leaf_550_clock_ctrl.core_clk ;
+ wire \clknet_leaf_551_clock_ctrl.core_clk ;
+ wire \clknet_leaf_552_clock_ctrl.core_clk ;
+ wire \clknet_leaf_553_clock_ctrl.core_clk ;
+ wire \clknet_leaf_554_clock_ctrl.core_clk ;
+ wire \clknet_leaf_555_clock_ctrl.core_clk ;
+ wire \clknet_leaf_556_clock_ctrl.core_clk ;
+ wire \clknet_leaf_557_clock_ctrl.core_clk ;
+ wire \clknet_leaf_558_clock_ctrl.core_clk ;
+ wire \clknet_leaf_559_clock_ctrl.core_clk ;
+ wire \clknet_leaf_560_clock_ctrl.core_clk ;
+ wire \clknet_leaf_561_clock_ctrl.core_clk ;
+ wire \clknet_leaf_562_clock_ctrl.core_clk ;
+ wire \clknet_leaf_563_clock_ctrl.core_clk ;
+ wire \clknet_leaf_565_clock_ctrl.core_clk ;
+ wire \clknet_leaf_566_clock_ctrl.core_clk ;
+ wire \clknet_leaf_567_clock_ctrl.core_clk ;
+ wire \clknet_leaf_568_clock_ctrl.core_clk ;
+ wire \clknet_leaf_569_clock_ctrl.core_clk ;
+ wire \clknet_leaf_570_clock_ctrl.core_clk ;
+ wire \clknet_leaf_571_clock_ctrl.core_clk ;
+ wire \clknet_leaf_572_clock_ctrl.core_clk ;
+ wire \clknet_leaf_573_clock_ctrl.core_clk ;
+ wire \clknet_leaf_574_clock_ctrl.core_clk ;
+ wire \clknet_leaf_575_clock_ctrl.core_clk ;
+ wire \clknet_leaf_576_clock_ctrl.core_clk ;
+ wire \clknet_leaf_578_clock_ctrl.core_clk ;
+ wire \clknet_leaf_579_clock_ctrl.core_clk ;
+ wire \clknet_leaf_580_clock_ctrl.core_clk ;
+ wire \clknet_leaf_581_clock_ctrl.core_clk ;
+ wire \clknet_leaf_582_clock_ctrl.core_clk ;
+ wire \clknet_leaf_583_clock_ctrl.core_clk ;
+ wire \clknet_leaf_585_clock_ctrl.core_clk ;
+ wire \clknet_leaf_587_clock_ctrl.core_clk ;
+ wire \clknet_leaf_588_clock_ctrl.core_clk ;
+ wire \clknet_leaf_589_clock_ctrl.core_clk ;
+ wire \clknet_leaf_590_clock_ctrl.core_clk ;
+ wire \clknet_leaf_591_clock_ctrl.core_clk ;
+ wire \clknet_leaf_592_clock_ctrl.core_clk ;
+ wire \clknet_leaf_593_clock_ctrl.core_clk ;
+ wire \clknet_leaf_594_clock_ctrl.core_clk ;
+ wire \clknet_leaf_595_clock_ctrl.core_clk ;
+ wire \clknet_leaf_596_clock_ctrl.core_clk ;
+ wire \clknet_leaf_597_clock_ctrl.core_clk ;
+ wire \clknet_leaf_598_clock_ctrl.core_clk ;
+ wire \clknet_leaf_599_clock_ctrl.core_clk ;
+ wire \clknet_leaf_600_clock_ctrl.core_clk ;
+ wire \clknet_leaf_601_clock_ctrl.core_clk ;
+ wire \clknet_leaf_602_clock_ctrl.core_clk ;
+ wire \clknet_leaf_605_clock_ctrl.core_clk ;
+ wire \clknet_leaf_606_clock_ctrl.core_clk ;
+ wire \clknet_leaf_607_clock_ctrl.core_clk ;
+ wire \clknet_leaf_608_clock_ctrl.core_clk ;
+ wire \clknet_leaf_609_clock_ctrl.core_clk ;
+ wire \clknet_leaf_610_clock_ctrl.core_clk ;
+ wire \clknet_leaf_612_clock_ctrl.core_clk ;
+ wire \clknet_leaf_613_clock_ctrl.core_clk ;
+ wire \clknet_leaf_614_clock_ctrl.core_clk ;
+ wire \clknet_leaf_615_clock_ctrl.core_clk ;
+ wire \clknet_leaf_616_clock_ctrl.core_clk ;
+ wire \clknet_leaf_617_clock_ctrl.core_clk ;
+ wire \clknet_leaf_618_clock_ctrl.core_clk ;
+ wire \clknet_leaf_619_clock_ctrl.core_clk ;
+ wire \clknet_leaf_620_clock_ctrl.core_clk ;
+ wire \clknet_leaf_621_clock_ctrl.core_clk ;
+ wire \clknet_leaf_622_clock_ctrl.core_clk ;
+ wire \clknet_leaf_623_clock_ctrl.core_clk ;
+ wire \clknet_leaf_624_clock_ctrl.core_clk ;
+ wire \clknet_leaf_625_clock_ctrl.core_clk ;
+ wire \clknet_leaf_626_clock_ctrl.core_clk ;
+ wire \clknet_leaf_627_clock_ctrl.core_clk ;
+ wire \clknet_leaf_628_clock_ctrl.core_clk ;
+ wire \clknet_leaf_629_clock_ctrl.core_clk ;
+ wire \clknet_leaf_630_clock_ctrl.core_clk ;
+ wire \clknet_leaf_631_clock_ctrl.core_clk ;
+ wire \clknet_leaf_632_clock_ctrl.core_clk ;
+ wire \clknet_leaf_633_clock_ctrl.core_clk ;
+ wire \clknet_leaf_634_clock_ctrl.core_clk ;
+ wire \clknet_leaf_635_clock_ctrl.core_clk ;
+ wire \clknet_leaf_637_clock_ctrl.core_clk ;
+ wire \clknet_leaf_638_clock_ctrl.core_clk ;
+ wire \clknet_leaf_640_clock_ctrl.core_clk ;
+ wire \clknet_leaf_641_clock_ctrl.core_clk ;
+ wire \clknet_leaf_642_clock_ctrl.core_clk ;
+ wire \clknet_leaf_643_clock_ctrl.core_clk ;
+ wire \clknet_leaf_644_clock_ctrl.core_clk ;
+ wire \clknet_leaf_645_clock_ctrl.core_clk ;
+ wire \clknet_leaf_646_clock_ctrl.core_clk ;
+ wire \clknet_leaf_647_clock_ctrl.core_clk ;
+ wire \clknet_leaf_648_clock_ctrl.core_clk ;
+ wire \clknet_leaf_649_clock_ctrl.core_clk ;
+ wire \clknet_leaf_650_clock_ctrl.core_clk ;
+ wire \clknet_leaf_651_clock_ctrl.core_clk ;
+ wire \clknet_leaf_652_clock_ctrl.core_clk ;
+ wire \clknet_leaf_653_clock_ctrl.core_clk ;
+ wire \clknet_leaf_654_clock_ctrl.core_clk ;
+ wire \clknet_leaf_655_clock_ctrl.core_clk ;
+ wire \clknet_leaf_656_clock_ctrl.core_clk ;
+ wire \clknet_leaf_657_clock_ctrl.core_clk ;
+ wire \clknet_leaf_658_clock_ctrl.core_clk ;
+ wire \clknet_leaf_659_clock_ctrl.core_clk ;
+ wire \clknet_leaf_660_clock_ctrl.core_clk ;
+ wire \clknet_leaf_661_clock_ctrl.core_clk ;
+ wire \clknet_leaf_662_clock_ctrl.core_clk ;
+ wire \clknet_leaf_663_clock_ctrl.core_clk ;
+ wire \clknet_leaf_664_clock_ctrl.core_clk ;
+ wire \clknet_leaf_665_clock_ctrl.core_clk ;
+ wire \clknet_leaf_666_clock_ctrl.core_clk ;
+ wire \clknet_leaf_667_clock_ctrl.core_clk ;
+ wire \clknet_leaf_668_clock_ctrl.core_clk ;
+ wire \clknet_leaf_669_clock_ctrl.core_clk ;
+ wire \clknet_leaf_670_clock_ctrl.core_clk ;
+ wire \clknet_leaf_671_clock_ctrl.core_clk ;
+ wire \clknet_leaf_673_clock_ctrl.core_clk ;
+ wire \clknet_leaf_674_clock_ctrl.core_clk ;
+ wire \clknet_leaf_675_clock_ctrl.core_clk ;
+ wire \clknet_leaf_676_clock_ctrl.core_clk ;
+ wire \clknet_leaf_677_clock_ctrl.core_clk ;
+ wire \clknet_leaf_678_clock_ctrl.core_clk ;
+ wire \clknet_leaf_679_clock_ctrl.core_clk ;
+ wire \clknet_leaf_680_clock_ctrl.core_clk ;
+ wire \clknet_leaf_681_clock_ctrl.core_clk ;
+ wire \clknet_leaf_683_clock_ctrl.core_clk ;
+ wire \clknet_leaf_684_clock_ctrl.core_clk ;
+ wire \clknet_leaf_686_clock_ctrl.core_clk ;
+ wire \clknet_leaf_687_clock_ctrl.core_clk ;
+ wire \clknet_leaf_688_clock_ctrl.core_clk ;
+ wire \clknet_leaf_689_clock_ctrl.core_clk ;
+ wire \clknet_leaf_690_clock_ctrl.core_clk ;
+ wire \clknet_leaf_691_clock_ctrl.core_clk ;
+ wire \clknet_leaf_692_clock_ctrl.core_clk ;
+ wire \clknet_leaf_693_clock_ctrl.core_clk ;
+ wire \clknet_leaf_694_clock_ctrl.core_clk ;
+ wire \clknet_leaf_695_clock_ctrl.core_clk ;
+ wire \clknet_leaf_696_clock_ctrl.core_clk ;
+ wire \clknet_leaf_697_clock_ctrl.core_clk ;
+ wire \clknet_leaf_698_clock_ctrl.core_clk ;
+ wire \clknet_leaf_699_clock_ctrl.core_clk ;
+ wire \clknet_leaf_700_clock_ctrl.core_clk ;
+ wire \clknet_leaf_701_clock_ctrl.core_clk ;
+ wire \clknet_leaf_702_clock_ctrl.core_clk ;
+ wire \clknet_leaf_703_clock_ctrl.core_clk ;
+ wire \clknet_leaf_704_clock_ctrl.core_clk ;
+ wire \clknet_leaf_705_clock_ctrl.core_clk ;
+ wire \clknet_leaf_706_clock_ctrl.core_clk ;
+ wire \clknet_leaf_707_clock_ctrl.core_clk ;
+ wire \clknet_leaf_709_clock_ctrl.core_clk ;
+ wire \clknet_leaf_710_clock_ctrl.core_clk ;
+ wire \clknet_leaf_711_clock_ctrl.core_clk ;
+ wire \clknet_leaf_712_clock_ctrl.core_clk ;
+ wire \clknet_leaf_713_clock_ctrl.core_clk ;
+ wire \clknet_leaf_715_clock_ctrl.core_clk ;
+ wire \clknet_leaf_716_clock_ctrl.core_clk ;
+ wire \clknet_leaf_717_clock_ctrl.core_clk ;
+ wire \clknet_leaf_718_clock_ctrl.core_clk ;
+ wire \clknet_leaf_719_clock_ctrl.core_clk ;
+ wire \clknet_leaf_720_clock_ctrl.core_clk ;
+ wire \clknet_leaf_721_clock_ctrl.core_clk ;
+ wire \clknet_leaf_722_clock_ctrl.core_clk ;
+ wire \clknet_leaf_723_clock_ctrl.core_clk ;
+ wire \clknet_leaf_724_clock_ctrl.core_clk ;
+ wire \clknet_leaf_725_clock_ctrl.core_clk ;
+ wire \clknet_leaf_726_clock_ctrl.core_clk ;
+ wire \clknet_leaf_727_clock_ctrl.core_clk ;
+ wire \clknet_leaf_728_clock_ctrl.core_clk ;
+ wire \clknet_leaf_729_clock_ctrl.core_clk ;
+ wire \clknet_leaf_730_clock_ctrl.core_clk ;
+ wire \clknet_leaf_731_clock_ctrl.core_clk ;
+ wire \clknet_leaf_732_clock_ctrl.core_clk ;
+ wire \clknet_leaf_733_clock_ctrl.core_clk ;
+ wire \clknet_leaf_734_clock_ctrl.core_clk ;
+ wire \clknet_leaf_735_clock_ctrl.core_clk ;
+ wire \clknet_leaf_736_clock_ctrl.core_clk ;
+ wire \clknet_leaf_737_clock_ctrl.core_clk ;
+ wire \clknet_leaf_738_clock_ctrl.core_clk ;
+ wire \clknet_leaf_739_clock_ctrl.core_clk ;
+ wire \clknet_leaf_740_clock_ctrl.core_clk ;
+ wire \clknet_leaf_741_clock_ctrl.core_clk ;
+ wire \clknet_leaf_742_clock_ctrl.core_clk ;
+ wire \clknet_leaf_743_clock_ctrl.core_clk ;
+ wire \clknet_leaf_744_clock_ctrl.core_clk ;
+ wire \clknet_leaf_745_clock_ctrl.core_clk ;
+ wire \clknet_leaf_746_clock_ctrl.core_clk ;
+ wire \clknet_leaf_747_clock_ctrl.core_clk ;
+ wire \clknet_leaf_748_clock_ctrl.core_clk ;
+ wire \clknet_leaf_749_clock_ctrl.core_clk ;
+ wire \clknet_leaf_750_clock_ctrl.core_clk ;
+ wire \clknet_leaf_751_clock_ctrl.core_clk ;
+ wire \clknet_leaf_752_clock_ctrl.core_clk ;
+ wire \clknet_leaf_753_clock_ctrl.core_clk ;
+ wire \clknet_leaf_754_clock_ctrl.core_clk ;
+ wire \clknet_leaf_755_clock_ctrl.core_clk ;
+ wire \clknet_leaf_756_clock_ctrl.core_clk ;
+ wire \clknet_leaf_758_clock_ctrl.core_clk ;
+ wire \clknet_leaf_759_clock_ctrl.core_clk ;
+ wire \clknet_leaf_760_clock_ctrl.core_clk ;
+ wire \clknet_leaf_761_clock_ctrl.core_clk ;
+ wire \clknet_leaf_762_clock_ctrl.core_clk ;
+ wire \clknet_leaf_765_clock_ctrl.core_clk ;
+ wire \clknet_leaf_767_clock_ctrl.core_clk ;
+ wire \clknet_leaf_768_clock_ctrl.core_clk ;
+ wire \clknet_leaf_769_clock_ctrl.core_clk ;
+ wire \clknet_leaf_770_clock_ctrl.core_clk ;
+ wire \clknet_leaf_771_clock_ctrl.core_clk ;
+ wire \clknet_leaf_772_clock_ctrl.core_clk ;
+ wire \clknet_leaf_773_clock_ctrl.core_clk ;
+ wire \clknet_leaf_774_clock_ctrl.core_clk ;
+ wire \clknet_leaf_775_clock_ctrl.core_clk ;
+ wire \clknet_leaf_776_clock_ctrl.core_clk ;
+ wire \clknet_leaf_777_clock_ctrl.core_clk ;
+ wire \clknet_leaf_778_clock_ctrl.core_clk ;
+ wire \clknet_leaf_779_clock_ctrl.core_clk ;
+ wire \clknet_leaf_780_clock_ctrl.core_clk ;
+ wire \clknet_leaf_782_clock_ctrl.core_clk ;
+ wire \clknet_leaf_783_clock_ctrl.core_clk ;
+ wire \clknet_leaf_784_clock_ctrl.core_clk ;
+ wire \clknet_leaf_785_clock_ctrl.core_clk ;
+ wire \clknet_leaf_786_clock_ctrl.core_clk ;
+ wire \clknet_leaf_787_clock_ctrl.core_clk ;
+ wire \clknet_leaf_789_clock_ctrl.core_clk ;
+ wire \clknet_leaf_790_clock_ctrl.core_clk ;
+ wire \clknet_leaf_791_clock_ctrl.core_clk ;
+ wire \clknet_leaf_792_clock_ctrl.core_clk ;
+ wire \clknet_leaf_793_clock_ctrl.core_clk ;
+ wire \clknet_leaf_794_clock_ctrl.core_clk ;
+ wire \clknet_leaf_795_clock_ctrl.core_clk ;
+ wire \clknet_leaf_796_clock_ctrl.core_clk ;
+ wire \clknet_leaf_797_clock_ctrl.core_clk ;
+ wire \clknet_leaf_800_clock_ctrl.core_clk ;
+ wire \clknet_leaf_801_clock_ctrl.core_clk ;
+ wire \clknet_leaf_802_clock_ctrl.core_clk ;
+ wire \clknet_leaf_803_clock_ctrl.core_clk ;
+ wire \clknet_leaf_804_clock_ctrl.core_clk ;
+ wire \clknet_leaf_806_clock_ctrl.core_clk ;
+ wire \clknet_leaf_807_clock_ctrl.core_clk ;
+ wire \clknet_leaf_808_clock_ctrl.core_clk ;
+ wire \clknet_leaf_809_clock_ctrl.core_clk ;
+ wire \clknet_leaf_810_clock_ctrl.core_clk ;
+ wire \clknet_leaf_811_clock_ctrl.core_clk ;
+ wire \clknet_leaf_812_clock_ctrl.core_clk ;
+ wire \clknet_leaf_813_clock_ctrl.core_clk ;
+ wire \clknet_leaf_814_clock_ctrl.core_clk ;
+ wire \clknet_leaf_815_clock_ctrl.core_clk ;
+ wire \clknet_leaf_816_clock_ctrl.core_clk ;
+ wire \clknet_leaf_817_clock_ctrl.core_clk ;
+ wire \clknet_leaf_818_clock_ctrl.core_clk ;
+ wire \clknet_leaf_819_clock_ctrl.core_clk ;
+ wire \clknet_leaf_820_clock_ctrl.core_clk ;
+ wire \clknet_leaf_821_clock_ctrl.core_clk ;
+ wire \clknet_leaf_822_clock_ctrl.core_clk ;
+ wire \clknet_leaf_823_clock_ctrl.core_clk ;
+ wire \clknet_leaf_824_clock_ctrl.core_clk ;
+ wire \clknet_leaf_826_clock_ctrl.core_clk ;
+ wire \clknet_leaf_827_clock_ctrl.core_clk ;
+ wire \clknet_leaf_828_clock_ctrl.core_clk ;
+ wire \clknet_leaf_829_clock_ctrl.core_clk ;
+ wire \clknet_leaf_830_clock_ctrl.core_clk ;
+ wire \clknet_leaf_832_clock_ctrl.core_clk ;
+ wire \clknet_leaf_833_clock_ctrl.core_clk ;
+ wire \clknet_leaf_835_clock_ctrl.core_clk ;
+ wire \clknet_leaf_837_clock_ctrl.core_clk ;
+ wire \clknet_leaf_838_clock_ctrl.core_clk ;
+ wire \clknet_leaf_839_clock_ctrl.core_clk ;
+ wire \clknet_leaf_840_clock_ctrl.core_clk ;
+ wire \clknet_leaf_842_clock_ctrl.core_clk ;
+ wire \clknet_leaf_843_clock_ctrl.core_clk ;
+ wire \clknet_leaf_844_clock_ctrl.core_clk ;
+ wire \clknet_leaf_846_clock_ctrl.core_clk ;
+ wire \clknet_leaf_847_clock_ctrl.core_clk ;
+ wire \clknet_leaf_848_clock_ctrl.core_clk ;
+ wire \clknet_leaf_849_clock_ctrl.core_clk ;
+ wire \clknet_leaf_850_clock_ctrl.core_clk ;
+ wire \clknet_leaf_851_clock_ctrl.core_clk ;
+ wire \clknet_leaf_852_clock_ctrl.core_clk ;
+ wire \clknet_leaf_853_clock_ctrl.core_clk ;
+ wire \clknet_leaf_854_clock_ctrl.core_clk ;
+ wire \clknet_leaf_855_clock_ctrl.core_clk ;
+ wire \clknet_leaf_856_clock_ctrl.core_clk ;
+ wire \clknet_leaf_857_clock_ctrl.core_clk ;
+ wire \clknet_leaf_858_clock_ctrl.core_clk ;
+ wire \clknet_leaf_859_clock_ctrl.core_clk ;
+ wire \clknet_leaf_860_clock_ctrl.core_clk ;
+ wire \clknet_leaf_861_clock_ctrl.core_clk ;
+ wire \clknet_leaf_862_clock_ctrl.core_clk ;
+ wire \clknet_leaf_863_clock_ctrl.core_clk ;
+ wire \clknet_leaf_864_clock_ctrl.core_clk ;
+ wire \clknet_leaf_865_clock_ctrl.core_clk ;
+ wire \clknet_leaf_866_clock_ctrl.core_clk ;
+ wire \clknet_leaf_867_clock_ctrl.core_clk ;
+ wire \clknet_leaf_868_clock_ctrl.core_clk ;
+ wire \clknet_leaf_869_clock_ctrl.core_clk ;
+ wire \clknet_leaf_870_clock_ctrl.core_clk ;
+ wire \clknet_leaf_871_clock_ctrl.core_clk ;
+ wire \clknet_leaf_872_clock_ctrl.core_clk ;
+ wire \clknet_leaf_873_clock_ctrl.core_clk ;
+ wire \clknet_leaf_875_clock_ctrl.core_clk ;
+ wire \clknet_leaf_876_clock_ctrl.core_clk ;
+ wire \clknet_leaf_877_clock_ctrl.core_clk ;
+ wire \clknet_leaf_879_clock_ctrl.core_clk ;
+ wire \clknet_leaf_881_clock_ctrl.core_clk ;
+ wire \clknet_leaf_882_clock_ctrl.core_clk ;
+ wire \clknet_leaf_883_clock_ctrl.core_clk ;
+ wire \clknet_leaf_884_clock_ctrl.core_clk ;
+ wire \clknet_leaf_885_clock_ctrl.core_clk ;
+ wire \clknet_leaf_886_clock_ctrl.core_clk ;
+ wire \clknet_leaf_887_clock_ctrl.core_clk ;
+ wire \clknet_leaf_888_clock_ctrl.core_clk ;
+ wire \clknet_leaf_889_clock_ctrl.core_clk ;
+ wire \clknet_leaf_890_clock_ctrl.core_clk ;
+ wire \clknet_leaf_891_clock_ctrl.core_clk ;
+ wire \clknet_leaf_892_clock_ctrl.core_clk ;
+ wire \clknet_leaf_893_clock_ctrl.core_clk ;
+ wire \clknet_leaf_894_clock_ctrl.core_clk ;
+ wire \clknet_leaf_895_clock_ctrl.core_clk ;
+ wire \clknet_leaf_896_clock_ctrl.core_clk ;
+ wire \clknet_leaf_897_clock_ctrl.core_clk ;
+ wire \clknet_leaf_898_clock_ctrl.core_clk ;
+ wire \clknet_leaf_899_clock_ctrl.core_clk ;
+ wire \clknet_leaf_900_clock_ctrl.core_clk ;
+ wire \clknet_leaf_901_clock_ctrl.core_clk ;
+ wire \clknet_leaf_902_clock_ctrl.core_clk ;
+ wire \clknet_leaf_903_clock_ctrl.core_clk ;
+ wire \clknet_leaf_904_clock_ctrl.core_clk ;
+ wire \clknet_leaf_905_clock_ctrl.core_clk ;
+ wire \clknet_leaf_906_clock_ctrl.core_clk ;
+ wire \clknet_leaf_908_clock_ctrl.core_clk ;
+ wire \clknet_leaf_909_clock_ctrl.core_clk ;
+ wire \clknet_leaf_910_clock_ctrl.core_clk ;
+ wire \clknet_leaf_911_clock_ctrl.core_clk ;
+ wire \clknet_leaf_912_clock_ctrl.core_clk ;
+ wire \clknet_leaf_913_clock_ctrl.core_clk ;
+ wire \clknet_leaf_914_clock_ctrl.core_clk ;
+ wire \clknet_leaf_915_clock_ctrl.core_clk ;
+ wire \clknet_leaf_916_clock_ctrl.core_clk ;
+ wire \clknet_leaf_917_clock_ctrl.core_clk ;
+ wire \clknet_leaf_918_clock_ctrl.core_clk ;
+ wire \clknet_leaf_920_clock_ctrl.core_clk ;
+ wire \clknet_leaf_921_clock_ctrl.core_clk ;
+ wire \clknet_leaf_922_clock_ctrl.core_clk ;
+ wire \clknet_leaf_923_clock_ctrl.core_clk ;
+ wire \clknet_leaf_924_clock_ctrl.core_clk ;
+ wire \clknet_leaf_925_clock_ctrl.core_clk ;
+ wire \clknet_leaf_926_clock_ctrl.core_clk ;
+ wire \clknet_leaf_927_clock_ctrl.core_clk ;
+ wire \clknet_leaf_928_clock_ctrl.core_clk ;
+ wire \clknet_leaf_929_clock_ctrl.core_clk ;
+ wire \clknet_leaf_930_clock_ctrl.core_clk ;
+ wire \clknet_leaf_931_clock_ctrl.core_clk ;
+ wire \clknet_leaf_932_clock_ctrl.core_clk ;
+ wire \clknet_leaf_933_clock_ctrl.core_clk ;
+ wire \clknet_leaf_934_clock_ctrl.core_clk ;
+ wire \clknet_leaf_935_clock_ctrl.core_clk ;
+ wire \clknet_leaf_936_clock_ctrl.core_clk ;
+ wire \clknet_leaf_937_clock_ctrl.core_clk ;
+ wire \clknet_leaf_939_clock_ctrl.core_clk ;
+ wire \clknet_leaf_940_clock_ctrl.core_clk ;
+ wire \clknet_leaf_941_clock_ctrl.core_clk ;
+ wire \clknet_leaf_942_clock_ctrl.core_clk ;
+ wire \clknet_leaf_943_clock_ctrl.core_clk ;
+ wire \clknet_leaf_944_clock_ctrl.core_clk ;
+ wire \clknet_leaf_945_clock_ctrl.core_clk ;
+ wire \clknet_leaf_946_clock_ctrl.core_clk ;
+ wire \clknet_leaf_947_clock_ctrl.core_clk ;
+ wire \clknet_leaf_948_clock_ctrl.core_clk ;
+ wire \clknet_leaf_949_clock_ctrl.core_clk ;
+ wire \clknet_leaf_950_clock_ctrl.core_clk ;
+ wire \clknet_leaf_951_clock_ctrl.core_clk ;
+ wire \clknet_leaf_953_clock_ctrl.core_clk ;
+ wire \clknet_leaf_954_clock_ctrl.core_clk ;
+ wire \clknet_leaf_955_clock_ctrl.core_clk ;
+ wire \clknet_leaf_956_clock_ctrl.core_clk ;
+ wire \clknet_leaf_957_clock_ctrl.core_clk ;
+ wire \clknet_leaf_958_clock_ctrl.core_clk ;
+ wire \clknet_leaf_959_clock_ctrl.core_clk ;
+ wire \clknet_leaf_960_clock_ctrl.core_clk ;
+ wire \clknet_leaf_961_clock_ctrl.core_clk ;
+ wire \clknet_leaf_962_clock_ctrl.core_clk ;
+ wire \clknet_leaf_963_clock_ctrl.core_clk ;
+ wire \clknet_leaf_964_clock_ctrl.core_clk ;
+ wire \clknet_leaf_965_clock_ctrl.core_clk ;
+ wire \clknet_leaf_966_clock_ctrl.core_clk ;
+ wire \clknet_leaf_967_clock_ctrl.core_clk ;
+ wire \clknet_leaf_968_clock_ctrl.core_clk ;
+ wire \clknet_leaf_970_clock_ctrl.core_clk ;
+ wire \clknet_leaf_971_clock_ctrl.core_clk ;
+ wire \clknet_leaf_972_clock_ctrl.core_clk ;
+ wire \clknet_leaf_973_clock_ctrl.core_clk ;
+ wire \clknet_leaf_974_clock_ctrl.core_clk ;
+ wire \clknet_leaf_975_clock_ctrl.core_clk ;
+ wire \clknet_leaf_976_clock_ctrl.core_clk ;
+ wire \clknet_leaf_977_clock_ctrl.core_clk ;
+ wire \clknet_leaf_978_clock_ctrl.core_clk ;
+ wire \clknet_leaf_979_clock_ctrl.core_clk ;
+ wire \clknet_leaf_980_clock_ctrl.core_clk ;
+ wire \clknet_leaf_981_clock_ctrl.core_clk ;
+ wire \clknet_leaf_982_clock_ctrl.core_clk ;
+ wire \clknet_leaf_984_clock_ctrl.core_clk ;
+ wire \clknet_leaf_985_clock_ctrl.core_clk ;
+ wire \clknet_leaf_986_clock_ctrl.core_clk ;
+ wire \clknet_leaf_987_clock_ctrl.core_clk ;
+ wire \clknet_leaf_988_clock_ctrl.core_clk ;
+ wire \clknet_leaf_990_clock_ctrl.core_clk ;
+ wire \clknet_leaf_991_clock_ctrl.core_clk ;
+ wire \clknet_leaf_992_clock_ctrl.core_clk ;
+ wire \clknet_leaf_993_clock_ctrl.core_clk ;
+ wire \clknet_leaf_994_clock_ctrl.core_clk ;
+ wire \clknet_leaf_995_clock_ctrl.core_clk ;
+ wire \clknet_leaf_996_clock_ctrl.core_clk ;
+ wire \clknet_leaf_997_clock_ctrl.core_clk ;
+ wire \clknet_leaf_998_clock_ctrl.core_clk ;
+ wire \clknet_leaf_999_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1000_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1001_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1002_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1003_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1004_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1005_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1006_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1007_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1008_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1009_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1010_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1011_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1012_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1013_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1014_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1015_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1016_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1017_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1018_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1019_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1020_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1022_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1023_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1024_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1025_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1027_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1028_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1029_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1030_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1031_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1032_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1033_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1034_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1035_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1036_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1037_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1038_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1039_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1040_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1041_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1042_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1043_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1044_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1045_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1046_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1047_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1048_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1050_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1051_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1052_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1053_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1054_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1055_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1056_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1057_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1058_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1059_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1060_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1061_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1062_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1063_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1064_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1065_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1066_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1067_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1068_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1069_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1070_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1071_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1073_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1074_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1076_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1077_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1078_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1079_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1080_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1081_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1082_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1083_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1085_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1086_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1087_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1088_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1089_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1090_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1091_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1092_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1093_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1094_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1095_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1096_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1097_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1098_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1099_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1100_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1101_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1102_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1103_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1104_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1105_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1106_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1107_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1108_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1109_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1110_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1111_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1112_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1113_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1114_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1115_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1116_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1117_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1118_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1120_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1121_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1122_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1123_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1125_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1127_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1128_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1130_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1131_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1132_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1133_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1134_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1135_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1136_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1137_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1138_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1140_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1141_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1142_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1143_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1144_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1145_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1146_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1147_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1148_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1149_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1150_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1151_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1152_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1153_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1154_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1155_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1156_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1157_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1161_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1162_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1163_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1164_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1165_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1166_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1167_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1169_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1170_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1171_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1172_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1173_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1174_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1175_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1176_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1177_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1178_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1179_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1180_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1181_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1182_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1183_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1184_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1185_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1186_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1187_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1188_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1190_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1191_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1192_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1193_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1194_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1195_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1196_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1197_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1198_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1199_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1200_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1201_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1202_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1203_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1204_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1205_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1206_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1207_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1209_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1210_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1211_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1212_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1213_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1214_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1215_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1216_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1217_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1218_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1220_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1221_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1222_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1223_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1224_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1225_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1226_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1227_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1228_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1229_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1230_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1231_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1232_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1233_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1234_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1235_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1236_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1238_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1239_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1240_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1241_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1242_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1243_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1244_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1245_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1246_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1247_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1248_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1249_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1250_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1251_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1252_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1253_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1254_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1255_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1256_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1257_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1258_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1259_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1260_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1261_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1262_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1263_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1264_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1265_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1266_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1267_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1268_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1269_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1270_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1271_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1272_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1273_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1274_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1275_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1276_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1277_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1278_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1279_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1280_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1281_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1282_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1283_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1284_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1285_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1286_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1287_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1288_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1289_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1290_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1291_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1292_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1293_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1294_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1295_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1296_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1297_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1298_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1302_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1303_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1304_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1305_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1306_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1307_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1308_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1309_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1310_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1311_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1312_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1313_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1314_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1315_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1316_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1317_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1318_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1319_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1320_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1321_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1322_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1323_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1324_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1325_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1326_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1327_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1331_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1333_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1334_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1335_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1336_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1337_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1338_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1339_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1340_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1341_clock_ctrl.core_clk ;
+ wire \clknet_leaf_1342_clock_ctrl.core_clk ;
+ wire \clknet_0_clock_ctrl.core_clk ;
+ wire \clknet_1_0_0_clock_ctrl.core_clk ;
+ wire \clknet_1_0_1_clock_ctrl.core_clk ;
+ wire \clknet_1_0_2_clock_ctrl.core_clk ;
+ wire \clknet_1_0_3_clock_ctrl.core_clk ;
+ wire \clknet_1_0_4_clock_ctrl.core_clk ;
+ wire \clknet_1_1_0_clock_ctrl.core_clk ;
+ wire \clknet_1_1_1_clock_ctrl.core_clk ;
+ wire \clknet_1_1_2_clock_ctrl.core_clk ;
+ wire \clknet_1_1_3_clock_ctrl.core_clk ;
+ wire \clknet_1_1_4_clock_ctrl.core_clk ;
+ wire \clknet_2_0_0_clock_ctrl.core_clk ;
+ wire \clknet_2_0_1_clock_ctrl.core_clk ;
+ wire \clknet_2_1_0_clock_ctrl.core_clk ;
+ wire \clknet_2_1_1_clock_ctrl.core_clk ;
+ wire \clknet_2_2_0_clock_ctrl.core_clk ;
+ wire \clknet_2_2_1_clock_ctrl.core_clk ;
+ wire \clknet_2_3_0_clock_ctrl.core_clk ;
+ wire \clknet_2_3_1_clock_ctrl.core_clk ;
+ wire \clknet_3_0_0_clock_ctrl.core_clk ;
+ wire \clknet_3_0_1_clock_ctrl.core_clk ;
+ wire \clknet_3_0_2_clock_ctrl.core_clk ;
+ wire \clknet_3_1_0_clock_ctrl.core_clk ;
+ wire \clknet_3_1_1_clock_ctrl.core_clk ;
+ wire \clknet_3_1_2_clock_ctrl.core_clk ;
+ wire \clknet_3_2_0_clock_ctrl.core_clk ;
+ wire \clknet_3_2_1_clock_ctrl.core_clk ;
+ wire \clknet_3_2_2_clock_ctrl.core_clk ;
+ wire \clknet_3_3_0_clock_ctrl.core_clk ;
+ wire \clknet_3_3_1_clock_ctrl.core_clk ;
+ wire \clknet_3_3_2_clock_ctrl.core_clk ;
+ wire \clknet_3_4_0_clock_ctrl.core_clk ;
+ wire \clknet_3_4_1_clock_ctrl.core_clk ;
+ wire \clknet_3_4_2_clock_ctrl.core_clk ;
+ wire \clknet_3_5_0_clock_ctrl.core_clk ;
+ wire \clknet_3_5_1_clock_ctrl.core_clk ;
+ wire \clknet_3_5_2_clock_ctrl.core_clk ;
+ wire \clknet_3_6_0_clock_ctrl.core_clk ;
+ wire \clknet_3_6_1_clock_ctrl.core_clk ;
+ wire \clknet_3_6_2_clock_ctrl.core_clk ;
+ wire \clknet_3_7_0_clock_ctrl.core_clk ;
+ wire \clknet_3_7_1_clock_ctrl.core_clk ;
+ wire \clknet_3_7_2_clock_ctrl.core_clk ;
+ wire \clknet_4_0_0_clock_ctrl.core_clk ;
+ wire \clknet_4_1_0_clock_ctrl.core_clk ;
+ wire \clknet_4_2_0_clock_ctrl.core_clk ;
+ wire \clknet_4_3_0_clock_ctrl.core_clk ;
+ wire \clknet_4_4_0_clock_ctrl.core_clk ;
+ wire \clknet_4_5_0_clock_ctrl.core_clk ;
+ wire \clknet_4_6_0_clock_ctrl.core_clk ;
+ wire \clknet_4_7_0_clock_ctrl.core_clk ;
+ wire \clknet_4_8_0_clock_ctrl.core_clk ;
+ wire \clknet_4_9_0_clock_ctrl.core_clk ;
+ wire \clknet_4_10_0_clock_ctrl.core_clk ;
+ wire \clknet_4_11_0_clock_ctrl.core_clk ;
+ wire \clknet_4_12_0_clock_ctrl.core_clk ;
+ wire \clknet_4_13_0_clock_ctrl.core_clk ;
+ wire \clknet_4_14_0_clock_ctrl.core_clk ;
+ wire \clknet_4_15_0_clock_ctrl.core_clk ;
+ wire \clknet_5_0_0_clock_ctrl.core_clk ;
+ wire \clknet_5_1_0_clock_ctrl.core_clk ;
+ wire \clknet_5_2_0_clock_ctrl.core_clk ;
+ wire \clknet_5_3_0_clock_ctrl.core_clk ;
+ wire \clknet_5_4_0_clock_ctrl.core_clk ;
+ wire \clknet_5_5_0_clock_ctrl.core_clk ;
+ wire \clknet_5_6_0_clock_ctrl.core_clk ;
+ wire \clknet_5_7_0_clock_ctrl.core_clk ;
+ wire \clknet_5_8_0_clock_ctrl.core_clk ;
+ wire \clknet_5_9_0_clock_ctrl.core_clk ;
+ wire \clknet_5_10_0_clock_ctrl.core_clk ;
+ wire \clknet_5_11_0_clock_ctrl.core_clk ;
+ wire \clknet_5_12_0_clock_ctrl.core_clk ;
+ wire \clknet_5_13_0_clock_ctrl.core_clk ;
+ wire \clknet_5_14_0_clock_ctrl.core_clk ;
+ wire \clknet_5_15_0_clock_ctrl.core_clk ;
+ wire \clknet_5_16_0_clock_ctrl.core_clk ;
+ wire \clknet_5_17_0_clock_ctrl.core_clk ;
+ wire \clknet_5_18_0_clock_ctrl.core_clk ;
+ wire \clknet_5_19_0_clock_ctrl.core_clk ;
+ wire \clknet_5_20_0_clock_ctrl.core_clk ;
+ wire \clknet_5_21_0_clock_ctrl.core_clk ;
+ wire \clknet_5_22_0_clock_ctrl.core_clk ;
+ wire \clknet_5_23_0_clock_ctrl.core_clk ;
+ wire \clknet_5_24_0_clock_ctrl.core_clk ;
+ wire \clknet_5_25_0_clock_ctrl.core_clk ;
+ wire \clknet_5_26_0_clock_ctrl.core_clk ;
+ wire \clknet_5_27_0_clock_ctrl.core_clk ;
+ wire \clknet_5_28_0_clock_ctrl.core_clk ;
+ wire \clknet_5_29_0_clock_ctrl.core_clk ;
+ wire \clknet_5_30_0_clock_ctrl.core_clk ;
+ wire \clknet_5_31_0_clock_ctrl.core_clk ;
+ wire \clknet_6_0_0_clock_ctrl.core_clk ;
+ wire \clknet_6_1_0_clock_ctrl.core_clk ;
+ wire \clknet_6_2_0_clock_ctrl.core_clk ;
+ wire \clknet_6_3_0_clock_ctrl.core_clk ;
+ wire \clknet_6_4_0_clock_ctrl.core_clk ;
+ wire \clknet_6_5_0_clock_ctrl.core_clk ;
+ wire \clknet_6_6_0_clock_ctrl.core_clk ;
+ wire \clknet_6_7_0_clock_ctrl.core_clk ;
+ wire \clknet_6_8_0_clock_ctrl.core_clk ;
+ wire \clknet_6_9_0_clock_ctrl.core_clk ;
+ wire \clknet_6_10_0_clock_ctrl.core_clk ;
+ wire \clknet_6_11_0_clock_ctrl.core_clk ;
+ wire \clknet_6_12_0_clock_ctrl.core_clk ;
+ wire \clknet_6_13_0_clock_ctrl.core_clk ;
+ wire \clknet_6_14_0_clock_ctrl.core_clk ;
+ wire \clknet_6_15_0_clock_ctrl.core_clk ;
+ wire \clknet_6_16_0_clock_ctrl.core_clk ;
+ wire \clknet_6_17_0_clock_ctrl.core_clk ;
+ wire \clknet_6_18_0_clock_ctrl.core_clk ;
+ wire \clknet_6_19_0_clock_ctrl.core_clk ;
+ wire \clknet_6_20_0_clock_ctrl.core_clk ;
+ wire \clknet_6_21_0_clock_ctrl.core_clk ;
+ wire \clknet_6_22_0_clock_ctrl.core_clk ;
+ wire \clknet_6_23_0_clock_ctrl.core_clk ;
+ wire \clknet_6_24_0_clock_ctrl.core_clk ;
+ wire \clknet_6_25_0_clock_ctrl.core_clk ;
+ wire \clknet_6_26_0_clock_ctrl.core_clk ;
+ wire \clknet_6_27_0_clock_ctrl.core_clk ;
+ wire \clknet_6_28_0_clock_ctrl.core_clk ;
+ wire \clknet_6_29_0_clock_ctrl.core_clk ;
+ wire \clknet_6_30_0_clock_ctrl.core_clk ;
+ wire \clknet_6_31_0_clock_ctrl.core_clk ;
+ wire \clknet_6_32_0_clock_ctrl.core_clk ;
+ wire \clknet_6_33_0_clock_ctrl.core_clk ;
+ wire \clknet_6_34_0_clock_ctrl.core_clk ;
+ wire \clknet_6_35_0_clock_ctrl.core_clk ;
+ wire \clknet_6_36_0_clock_ctrl.core_clk ;
+ wire \clknet_6_37_0_clock_ctrl.core_clk ;
+ wire \clknet_6_38_0_clock_ctrl.core_clk ;
+ wire \clknet_6_39_0_clock_ctrl.core_clk ;
+ wire \clknet_6_40_0_clock_ctrl.core_clk ;
+ wire \clknet_6_41_0_clock_ctrl.core_clk ;
+ wire \clknet_6_42_0_clock_ctrl.core_clk ;
+ wire \clknet_6_43_0_clock_ctrl.core_clk ;
+ wire \clknet_6_44_0_clock_ctrl.core_clk ;
+ wire \clknet_6_45_0_clock_ctrl.core_clk ;
+ wire \clknet_6_46_0_clock_ctrl.core_clk ;
+ wire \clknet_6_47_0_clock_ctrl.core_clk ;
+ wire \clknet_6_48_0_clock_ctrl.core_clk ;
+ wire \clknet_6_49_0_clock_ctrl.core_clk ;
+ wire \clknet_6_50_0_clock_ctrl.core_clk ;
+ wire \clknet_6_51_0_clock_ctrl.core_clk ;
+ wire \clknet_6_52_0_clock_ctrl.core_clk ;
+ wire \clknet_6_53_0_clock_ctrl.core_clk ;
+ wire \clknet_6_54_0_clock_ctrl.core_clk ;
+ wire \clknet_6_55_0_clock_ctrl.core_clk ;
+ wire \clknet_6_56_0_clock_ctrl.core_clk ;
+ wire \clknet_6_57_0_clock_ctrl.core_clk ;
+ wire \clknet_6_58_0_clock_ctrl.core_clk ;
+ wire \clknet_6_59_0_clock_ctrl.core_clk ;
+ wire \clknet_6_60_0_clock_ctrl.core_clk ;
+ wire \clknet_6_61_0_clock_ctrl.core_clk ;
+ wire \clknet_6_62_0_clock_ctrl.core_clk ;
+ wire \clknet_6_63_0_clock_ctrl.core_clk ;
+ wire \clknet_7_0_0_clock_ctrl.core_clk ;
+ wire \clknet_7_1_0_clock_ctrl.core_clk ;
+ wire \clknet_7_2_0_clock_ctrl.core_clk ;
+ wire \clknet_7_3_0_clock_ctrl.core_clk ;
+ wire \clknet_7_4_0_clock_ctrl.core_clk ;
+ wire \clknet_7_5_0_clock_ctrl.core_clk ;
+ wire \clknet_7_6_0_clock_ctrl.core_clk ;
+ wire \clknet_7_7_0_clock_ctrl.core_clk ;
+ wire \clknet_7_8_0_clock_ctrl.core_clk ;
+ wire \clknet_7_9_0_clock_ctrl.core_clk ;
+ wire \clknet_7_10_0_clock_ctrl.core_clk ;
+ wire \clknet_7_11_0_clock_ctrl.core_clk ;
+ wire \clknet_7_12_0_clock_ctrl.core_clk ;
+ wire \clknet_7_13_0_clock_ctrl.core_clk ;
+ wire \clknet_7_14_0_clock_ctrl.core_clk ;
+ wire \clknet_7_15_0_clock_ctrl.core_clk ;
+ wire \clknet_7_16_0_clock_ctrl.core_clk ;
+ wire \clknet_7_17_0_clock_ctrl.core_clk ;
+ wire \clknet_7_18_0_clock_ctrl.core_clk ;
+ wire \clknet_7_19_0_clock_ctrl.core_clk ;
+ wire \clknet_7_20_0_clock_ctrl.core_clk ;
+ wire \clknet_7_21_0_clock_ctrl.core_clk ;
+ wire \clknet_7_22_0_clock_ctrl.core_clk ;
+ wire \clknet_7_23_0_clock_ctrl.core_clk ;
+ wire \clknet_7_24_0_clock_ctrl.core_clk ;
+ wire \clknet_7_25_0_clock_ctrl.core_clk ;
+ wire \clknet_7_26_0_clock_ctrl.core_clk ;
+ wire \clknet_7_27_0_clock_ctrl.core_clk ;
+ wire \clknet_7_28_0_clock_ctrl.core_clk ;
+ wire \clknet_7_29_0_clock_ctrl.core_clk ;
+ wire \clknet_7_30_0_clock_ctrl.core_clk ;
+ wire \clknet_7_31_0_clock_ctrl.core_clk ;
+ wire \clknet_7_32_0_clock_ctrl.core_clk ;
+ wire \clknet_7_33_0_clock_ctrl.core_clk ;
+ wire \clknet_7_34_0_clock_ctrl.core_clk ;
+ wire \clknet_7_35_0_clock_ctrl.core_clk ;
+ wire \clknet_7_36_0_clock_ctrl.core_clk ;
+ wire \clknet_7_37_0_clock_ctrl.core_clk ;
+ wire \clknet_7_38_0_clock_ctrl.core_clk ;
+ wire \clknet_7_39_0_clock_ctrl.core_clk ;
+ wire \clknet_7_40_0_clock_ctrl.core_clk ;
+ wire \clknet_7_41_0_clock_ctrl.core_clk ;
+ wire \clknet_7_42_0_clock_ctrl.core_clk ;
+ wire \clknet_7_43_0_clock_ctrl.core_clk ;
+ wire \clknet_7_44_0_clock_ctrl.core_clk ;
+ wire \clknet_7_45_0_clock_ctrl.core_clk ;
+ wire \clknet_7_46_0_clock_ctrl.core_clk ;
+ wire \clknet_7_47_0_clock_ctrl.core_clk ;
+ wire \clknet_7_48_0_clock_ctrl.core_clk ;
+ wire \clknet_7_49_0_clock_ctrl.core_clk ;
+ wire \clknet_7_50_0_clock_ctrl.core_clk ;
+ wire \clknet_7_51_0_clock_ctrl.core_clk ;
+ wire \clknet_7_52_0_clock_ctrl.core_clk ;
+ wire \clknet_7_53_0_clock_ctrl.core_clk ;
+ wire \clknet_7_54_0_clock_ctrl.core_clk ;
+ wire \clknet_7_55_0_clock_ctrl.core_clk ;
+ wire \clknet_7_56_0_clock_ctrl.core_clk ;
+ wire \clknet_7_57_0_clock_ctrl.core_clk ;
+ wire \clknet_7_58_0_clock_ctrl.core_clk ;
+ wire \clknet_7_59_0_clock_ctrl.core_clk ;
+ wire \clknet_7_60_0_clock_ctrl.core_clk ;
+ wire \clknet_7_61_0_clock_ctrl.core_clk ;
+ wire \clknet_7_62_0_clock_ctrl.core_clk ;
+ wire \clknet_7_63_0_clock_ctrl.core_clk ;
+ wire \clknet_7_64_0_clock_ctrl.core_clk ;
+ wire \clknet_7_65_0_clock_ctrl.core_clk ;
+ wire \clknet_7_66_0_clock_ctrl.core_clk ;
+ wire \clknet_7_67_0_clock_ctrl.core_clk ;
+ wire \clknet_7_68_0_clock_ctrl.core_clk ;
+ wire \clknet_7_69_0_clock_ctrl.core_clk ;
+ wire \clknet_7_70_0_clock_ctrl.core_clk ;
+ wire \clknet_7_71_0_clock_ctrl.core_clk ;
+ wire \clknet_7_72_0_clock_ctrl.core_clk ;
+ wire \clknet_7_73_0_clock_ctrl.core_clk ;
+ wire \clknet_7_74_0_clock_ctrl.core_clk ;
+ wire \clknet_7_75_0_clock_ctrl.core_clk ;
+ wire \clknet_7_76_0_clock_ctrl.core_clk ;
+ wire \clknet_7_77_0_clock_ctrl.core_clk ;
+ wire \clknet_7_78_0_clock_ctrl.core_clk ;
+ wire \clknet_7_79_0_clock_ctrl.core_clk ;
+ wire \clknet_7_80_0_clock_ctrl.core_clk ;
+ wire \clknet_7_81_0_clock_ctrl.core_clk ;
+ wire \clknet_7_82_0_clock_ctrl.core_clk ;
+ wire \clknet_7_83_0_clock_ctrl.core_clk ;
+ wire \clknet_7_84_0_clock_ctrl.core_clk ;
+ wire \clknet_7_85_0_clock_ctrl.core_clk ;
+ wire \clknet_7_86_0_clock_ctrl.core_clk ;
+ wire \clknet_7_87_0_clock_ctrl.core_clk ;
+ wire \clknet_7_88_0_clock_ctrl.core_clk ;
+ wire \clknet_7_89_0_clock_ctrl.core_clk ;
+ wire \clknet_7_90_0_clock_ctrl.core_clk ;
+ wire \clknet_7_91_0_clock_ctrl.core_clk ;
+ wire \clknet_7_92_0_clock_ctrl.core_clk ;
+ wire \clknet_7_93_0_clock_ctrl.core_clk ;
+ wire \clknet_7_94_0_clock_ctrl.core_clk ;
+ wire \clknet_7_95_0_clock_ctrl.core_clk ;
+ wire \clknet_7_96_0_clock_ctrl.core_clk ;
+ wire \clknet_7_97_0_clock_ctrl.core_clk ;
+ wire \clknet_7_98_0_clock_ctrl.core_clk ;
+ wire \clknet_7_99_0_clock_ctrl.core_clk ;
+ wire \clknet_7_100_0_clock_ctrl.core_clk ;
+ wire \clknet_7_101_0_clock_ctrl.core_clk ;
+ wire \clknet_7_102_0_clock_ctrl.core_clk ;
+ wire \clknet_7_103_0_clock_ctrl.core_clk ;
+ wire \clknet_7_104_0_clock_ctrl.core_clk ;
+ wire \clknet_7_105_0_clock_ctrl.core_clk ;
+ wire \clknet_7_106_0_clock_ctrl.core_clk ;
+ wire \clknet_7_107_0_clock_ctrl.core_clk ;
+ wire \clknet_7_108_0_clock_ctrl.core_clk ;
+ wire \clknet_7_109_0_clock_ctrl.core_clk ;
+ wire \clknet_7_110_0_clock_ctrl.core_clk ;
+ wire \clknet_7_111_0_clock_ctrl.core_clk ;
+ wire \clknet_7_112_0_clock_ctrl.core_clk ;
+ wire \clknet_7_113_0_clock_ctrl.core_clk ;
+ wire \clknet_7_114_0_clock_ctrl.core_clk ;
+ wire \clknet_7_115_0_clock_ctrl.core_clk ;
+ wire \clknet_7_116_0_clock_ctrl.core_clk ;
+ wire \clknet_7_117_0_clock_ctrl.core_clk ;
+ wire \clknet_7_118_0_clock_ctrl.core_clk ;
+ wire \clknet_7_119_0_clock_ctrl.core_clk ;
+ wire \clknet_7_120_0_clock_ctrl.core_clk ;
+ wire \clknet_7_121_0_clock_ctrl.core_clk ;
+ wire \clknet_7_122_0_clock_ctrl.core_clk ;
+ wire \clknet_7_123_0_clock_ctrl.core_clk ;
+ wire \clknet_7_124_0_clock_ctrl.core_clk ;
+ wire \clknet_7_125_0_clock_ctrl.core_clk ;
+ wire \clknet_7_126_0_clock_ctrl.core_clk ;
+ wire \clknet_7_127_0_clock_ctrl.core_clk ;
+ wire \clknet_opt_1_0_clock_ctrl.core_clk ;
+ wire \clknet_opt_2_0_clock_ctrl.core_clk ;
+ wire \clknet_opt_2_1_clock_ctrl.core_clk ;
+ wire \clknet_opt_3_0_clock_ctrl.core_clk ;
+ wire \clknet_opt_3_1_clock_ctrl.core_clk ;
+ wire \clknet_opt_4_0_clock_ctrl.core_clk ;
+ wire \clknet_opt_4_1_clock_ctrl.core_clk ;
+ wire \clknet_opt_5_0_clock_ctrl.core_clk ;
+ wire net2345;
+ wire net2346;
+ wire net2347;
+ wire net2348;
+ wire net2349;
+ wire net2350;
+ wire net2351;
+ wire net2352;
+ wire net2353;
+ wire net2354;
+ wire net2355;
+ wire net2356;
+ wire net2357;
+ wire net2358;
+ wire net2359;
+ wire net2360;
+ wire net2361;
+ wire net2362;
+ wire net2363;
+ wire net2364;
+ wire net2365;
+ wire net2366;
+ wire net2367;
+ wire net2368;
+ wire net2369;
+ wire net2370;
+ wire net2371;
+ wire net2372;
+ wire net2373;
+ wire net2374;
+ wire net2375;
+ wire net2376;
+ wire net2377;
+ wire net2378;
+ wire net2379;
+ wire net2380;
+ wire net2381;
+ wire net2382;
+ wire net2383;
+ wire net2384;
+ wire net2385;
+ wire net2386;
+ wire net2387;
+ wire net2388;
+ wire net2389;
+ wire net2390;
+ wire net2391;
+ wire net2392;
+ wire net2393;
+ wire net2394;
+ wire net2395;
+ wire net2396;
+ wire net2397;
+ wire net2398;
+ wire net2399;
+ wire net2400;
+ wire net2401;
+ wire net2402;
+ wire net2403;
+ wire net2404;
+ wire net2405;
+ wire net2406;
+ wire net2407;
+ wire net2408;
+ wire net2409;
+ wire net2410;
+ wire net2411;
+ wire net2412;
+ wire net2413;
+ wire net2414;
+ wire net2415;
+ wire net2416;
+ wire net2417;
+ wire net2418;
+ wire net2419;
+ wire net2420;
+ wire net2421;
+ wire net2422;
+ wire net2423;
+ wire net2424;
+ wire net2425;
+ wire net2426;
+ wire net2427;
+ wire net2428;
+ wire net2429;
+ wire net2430;
+ wire net2431;
+ wire net2432;
+ wire net2433;
+ wire net2434;
+ wire net2435;
+ wire net2436;
+ wire net2437;
+ wire net2438;
+ wire net2439;
+ wire net2440;
+ wire net2441;
+ wire net2442;
+ wire net2443;
+ wire net2444;
+ wire net2445;
+ wire net2446;
+ wire net2447;
+ wire net2448;
+ wire net2449;
+ wire net2450;
+ wire net2451;
+ wire net2452;
+ wire net2453;
+ wire net2454;
+ wire net2455;
+ wire net2456;
+ wire net2457;
+ wire net2458;
+ wire net2459;
+ wire net2460;
+ wire net2461;
+ wire net2462;
+ wire net2463;
+ wire net2464;
+ wire net2465;
+ wire net2466;
+ wire net2467;
+ wire net2468;
+ wire net2469;
+ wire net2470;
+ wire net2471;
+ wire net2472;
+ wire net2473;
+ wire net2474;
+ wire net2475;
+ wire net2476;
+ wire net2477;
+ wire net2478;
+ wire net2479;
+ wire net2480;
+ wire net2481;
+ wire net2482;
+ wire net2483;
+ wire net2484;
+ wire net2485;
+ wire net2486;
+ wire net2487;
+ wire net2488;
+ wire net2489;
+ wire net2490;
+ wire net2491;
+ wire net2492;
+ wire net2493;
+ wire net2494;
+ wire net2495;
+ wire net2496;
+ wire net2497;
+ wire net2498;
+ wire net2499;
+ wire net2500;
+ wire net2501;
+ wire net2502;
+ wire net2503;
+ wire net2504;
+ wire net2505;
+ wire net2506;
+ wire net2507;
+ wire net2508;
+ wire net2509;
+ wire net2510;
+ wire net2511;
+ wire net2512;
+ wire net2513;
+ wire net2514;
+ wire net2515;
+ wire net2516;
+ wire net2517;
+ wire net2518;
+ wire net2519;
+ wire net2520;
+ wire net2521;
+ wire net2522;
+ wire net2523;
+ wire net2524;
+ wire net2525;
+ wire net2526;
+ wire net2527;
+ wire net2528;
+ wire net2529;
+ wire net2530;
+ wire net2531;
+ wire net2532;
+ wire net2533;
+ wire net2534;
+ wire net2535;
+ wire net2536;
+ wire net2537;
+ wire net2538;
+ wire net2539;
+ wire net2540;
+ wire net2541;
+ wire net2542;
+ wire net2543;
+ wire net2544;
+ wire net2545;
+ wire net2546;
+ wire net2547;
+ wire net2548;
+ wire net2549;
+ wire net2550;
+ wire net2551;
+ wire net2552;
+ wire net2553;
+ wire net2554;
+ wire net2555;
+ wire net2556;
+ wire net2557;
+ wire net2558;
+ wire net2559;
+ wire net2560;
+ wire net2561;
+ wire net2562;
+ wire net2563;
+ wire net2564;
+ wire net2565;
+ wire net2566;
+ wire net2567;
+ wire net2568;
+ wire net2569;
+ wire net2570;
+ wire net2571;
+ wire net2572;
+ wire net2573;
+ wire net2574;
+ wire net2575;
+ wire net2576;
+ wire net2577;
+ wire net2578;
+ wire net2579;
+ wire net2580;
+ wire net2581;
+ wire net2582;
+ wire net2583;
+ wire net2584;
+ wire net2585;
+ wire net2586;
+ wire net2587;
+ wire net2588;
+ wire net2589;
+ wire net2590;
+ wire net2591;
+ wire net2592;
+ wire net2593;
+ wire net2594;
+ wire net2595;
+ wire net2596;
+ wire net2597;
+ wire net2598;
+ wire net2599;
+ wire net2600;
+ wire net2601;
+ wire net2602;
+ wire net2603;
+ wire net2604;
+ wire net2605;
+ wire net2606;
+ wire net2607;
+ wire net2608;
+ wire net2609;
+ wire net2610;
+ wire net2611;
+ wire net2612;
+ wire net2613;
+ wire net2614;
+ wire net2615;
+ wire net2616;
+ wire net2617;
+ wire net2618;
+ wire net2619;
+ wire net2620;
+ wire net2621;
+ wire net2622;
+ wire net2623;
+ wire net2624;
+ wire net2625;
+ wire net2626;
+ wire net2627;
+ wire net2628;
+ wire net2629;
+ wire net2630;
+ wire net2631;
+ wire net2632;
+ wire net2633;
+ wire net2634;
+ wire net2635;
+ wire net2636;
+ wire net2637;
+ wire net2638;
+ wire net2639;
+ wire net2640;
+ wire net2641;
+ wire net2642;
+ wire net2643;
+ wire net2644;
+ wire net2645;
+ wire net2646;
+ wire net2647;
+ wire net2648;
+ wire net2649;
+ wire net2650;
+ wire net2651;
+ wire net2652;
+ wire net2653;
+ wire net2654;
+ wire net2655;
+ wire net2656;
+ wire net2657;
+ wire net2658;
+ wire net2659;
+ wire net2660;
+ wire net2661;
+ wire net2662;
+ wire net2663;
+ wire net2664;
+ wire net2665;
+ wire net2666;
+ wire net2667;
+ wire net2668;
+ wire net2669;
+ wire net2670;
+ wire net2671;
+ wire net2672;
+ wire net2673;
+ wire net2674;
+ wire net2675;
+ wire net2676;
+ wire net2677;
+ wire net2678;
+ wire net2679;
+ wire net2680;
+ wire net2681;
+ wire net2682;
+ wire net2683;
+ wire net2684;
+ wire net2685;
+ wire net2686;
+ wire net2687;
+ wire net2688;
+ wire net2689;
+ wire net2690;
+ wire net2691;
+ wire net2692;
+ wire net2693;
+ wire net2694;
+ wire net2695;
+ wire net2696;
+ wire net2697;
+ wire net2698;
+ wire net2699;
+ wire net2700;
+ wire net2701;
+ wire net2702;
+ wire net2703;
+ wire net2704;
+ wire net2705;
+ wire net2706;
+ wire net2707;
+ wire net2708;
+ wire net2709;
+ wire net2710;
+ wire net2711;
+ wire net2712;
+ wire net2713;
+ wire net2714;
+ wire net2715;
+ wire net2716;
+ wire net2717;
+ wire net2718;
+ wire net2719;
+ wire net2720;
+ wire net2721;
+ wire net2722;
+ wire net2723;
+ wire net2724;
+ wire net2725;
+ wire net2726;
+ wire net2727;
+ wire net2728;
+ wire net2729;
+ wire net2730;
+ wire net2731;
+ wire net2732;
+ wire net2733;
+ wire net2734;
+ wire net2735;
+ wire net2736;
+ wire net2737;
+ wire net2738;
+ wire net2739;
+ wire net2740;
+ wire net2741;
+ wire net2742;
+ wire net2743;
+ wire net2744;
+ wire net2745;
+ wire net2746;
+ wire net2747;
+ wire net2748;
+ wire net2749;
+ wire net2750;
+ wire net2751;
+ wire net2752;
+ wire net2753;
+ wire net2754;
+ wire net2755;
+ wire net2756;
+ wire net2757;
+ wire net2758;
+ wire net2759;
+ wire net2760;
+ wire net2761;
+ wire net2762;
+ wire net2763;
+ wire net2764;
+ wire net2765;
+ wire net2766;
+ wire net2767;
+ wire net2768;
+ wire net2769;
+ wire net2770;
+ wire net2771;
+ wire net2772;
+ wire net2773;
+ wire net2774;
+ wire net2775;
+ wire net2776;
+ wire net2777;
+ wire net2778;
+ wire net2779;
+ wire net2780;
+ wire net2781;
+ wire net2782;
+ wire net2783;
+ wire net2784;
+ wire net2785;
+ wire net2786;
+ wire net2787;
+ wire net2788;
+ wire net2789;
+ wire net2790;
+ wire net2791;
+ wire net2792;
+ wire net2793;
+ wire net2794;
+ wire net2795;
+ wire net2796;
+ wire net2797;
+ wire net2798;
+ wire net2799;
+ wire net2800;
+ wire net2801;
+ wire net2802;
+ wire net2803;
+ wire net2804;
+ wire net2805;
+ wire net2806;
+ wire net2807;
+ wire net2808;
+ wire net2809;
+ wire net2810;
+ wire net2811;
+ wire net2812;
+ wire net2813;
+ wire net2814;
+ wire net2815;
+ wire net2816;
+ wire net2817;
+ wire net2818;
+ wire net2819;
+ wire net2820;
+ wire net2821;
+ wire net2822;
+ wire net2823;
+ wire net2824;
+ wire net2825;
+ wire net2826;
+ wire net2827;
+ wire net2828;
+ wire net2829;
+ wire net2830;
+ wire net2831;
+ wire net2832;
+ wire net2833;
+ wire net2834;
+ wire net2835;
+ wire net2836;
+ wire net2837;
+ wire net2838;
+ wire net2839;
+ wire net2840;
+ wire net2841;
+ wire net2842;
+ wire net2843;
+ wire net2844;
+ wire net2845;
+ wire net2846;
+ wire net2847;
+ wire net2848;
+ wire net2849;
+ wire net2850;
+ wire net2851;
+ wire net2852;
+ wire net2853;
+ wire net2854;
+ wire net2855;
+ wire net2856;
+ wire net2857;
+ wire net2858;
+ wire net2859;
+ wire net2860;
+ wire net2861;
+ wire net2862;
+ wire net2863;
+ wire net2864;
+ wire net2865;
+ wire net2866;
+ wire net2867;
+ wire net2868;
+ wire net2869;
+ wire net2870;
+ wire net2871;
+ wire net2872;
+ wire net2873;
+ wire net2874;
+ wire net2875;
+ wire net2876;
+ wire net2877;
+ wire net2878;
+ wire net2879;
+ wire net2880;
+ wire net2881;
+ wire net2882;
+ wire net2883;
+ wire net2884;
+ wire net2885;
+ wire net2886;
+ wire net2887;
+ wire net2888;
+ wire net2889;
+ wire net2890;
+ wire net2891;
+ wire net2892;
+ wire net2893;
+ wire net2894;
+ wire net2895;
+ wire net2896;
+ wire net2897;
+ wire net2898;
+ wire net2899;
+ wire net2900;
+ wire net2901;
+ wire net2902;
+ wire net2903;
+ wire net2904;
+ wire net2905;
+ wire net2906;
+ wire net2907;
+ wire net2908;
+ wire net2909;
+ wire net2910;
+ wire net2911;
+ wire net2912;
+ wire net2913;
+ wire net2914;
+ wire net2915;
+ wire net2916;
+ wire net2917;
+ wire net2918;
+ wire net2919;
+ wire net2920;
+ wire net2921;
+ wire net2922;
+ wire net2923;
+ wire net2924;
+ wire net2925;
+ wire net2926;
+ wire net2927;
+ wire net2928;
+ wire net2929;
+ wire net2930;
+ wire net2931;
+ wire net2932;
+ wire net2933;
+ wire net2934;
+ wire net2935;
+ wire net2936;
+ wire net2937;
+ wire net2938;
+ wire net2939;
+ wire net2940;
+ wire net2941;
+ wire net2942;
+ wire net2943;
+ wire net2944;
+ wire net2945;
+ wire net2946;
+ wire net2947;
+ wire net2948;
+ wire net2949;
+ wire net2950;
+ wire net2951;
+ wire net2952;
+ wire net2953;
+ wire net2954;
+ wire net2955;
+ wire net2956;
+ wire net2957;
+ wire net2958;
+ wire net2959;
+ wire net2960;
+ wire net2961;
+ wire net2962;
+ wire net2963;
+ wire net2964;
+ wire net2965;
+ wire net2966;
+ wire net2967;
+ wire net2968;
+ wire net2969;
+ wire net2970;
+ wire net2971;
+ wire net2972;
+ wire net2973;
+ wire net2974;
+ wire net2975;
+
+ gf180mcu_fd_sc_mcu7t5v0__inv_1 _16478_ (.I(\pll.pll_control.count0[4] ),
+ .ZN(_04963_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_2 _16479_ (.I(\pll.pll_control.prep[0] ),
+ .ZN(_04964_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_4 _16480_ (.I(\soc.core.VexRiscv.IBusCachedPlugin_cache.io_cpu_decode_isValid ),
+ .ZN(_04965_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_2 _16481_ (.I(\soc.core.VexRiscv.IBusCachedPlugin_cache.io_cpu_fetch_isValid ),
+ .ZN(_04966_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_3 _16482_ (.I(net1759),
+ .ZN(_04967_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _16483_ (.I(\soc.core.VexRiscv._zz_CsrPlugin_csrMapping_readDataInit[1] ),
+ .ZN(_04968_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_1 _16484_ (.I(\soc.core.VexRiscv._zz_iBusWishbone_ADR[0] ),
+ .ZN(_04969_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_3 _16485_ (.I(\soc.core.VexRiscv.IBusCachedPlugin_cache._zz_when_Fetcher_l398[2] ),
+ .ZN(_04970_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_12 _16486_ (.I(net1786),
+ .ZN(_04971_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_2 _16487_ (.I(\soc.core.VexRiscv.DebugPlugin_disableEbreak ),
+ .ZN(_04972_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_2 _16488_ (.I(\soc.core.VexRiscv.IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_isIoAccess ),
+ .ZN(_04973_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_2 _16489_ (.I(\soc.core.VexRiscv.IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[30] ),
+ .ZN(_04974_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_3 _16490_ (.I(\soc.core.VexRiscv.IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[29] ),
+ .ZN(_04975_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_4 _16491_ (.I(\soc.core.VexRiscv.IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[28] ),
+ .ZN(_04976_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_3 _16492_ (.I(\soc.core.VexRiscv.IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[27] ),
+ .ZN(_04977_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_3 _16493_ (.I(\soc.core.VexRiscv.IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[26] ),
+ .ZN(_04978_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_2 _16494_ (.I(\soc.core.VexRiscv.IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[25] ),
+ .ZN(_04979_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_4 _16495_ (.I(\soc.core.VexRiscv.IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[24] ),
+ .ZN(_04980_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_4 _16496_ (.I(\soc.core.VexRiscv.IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[23] ),
+ .ZN(_04981_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_2 _16497_ (.I(\soc.core.VexRiscv.IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[22] ),
+ .ZN(_04982_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_2 _16498_ (.I(\soc.core.VexRiscv.IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[21] ),
+ .ZN(_04983_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_2 _16499_ (.I(\soc.core.VexRiscv.IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[20] ),
+ .ZN(_04984_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_4 _16500_ (.I(\soc.core.VexRiscv.IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[19] ),
+ .ZN(_04985_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_4 _16501_ (.I(\soc.core.VexRiscv.IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[18] ),
+ .ZN(_04986_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_3 _16502_ (.I(\soc.core.VexRiscv.IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[17] ),
+ .ZN(_04987_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_4 _16503_ (.I(\soc.core.VexRiscv.IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[16] ),
+ .ZN(_04988_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_4 _16504_ (.I(\soc.core.VexRiscv.IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[15] ),
+ .ZN(_04989_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_2 _16505_ (.I(\soc.core.VexRiscv.IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[14] ),
+ .ZN(_04990_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_4 _16506_ (.I(\soc.core.VexRiscv.IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[12] ),
+ .ZN(_04991_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_2 _16507_ (.I(\soc.core.VexRiscv.IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[10] ),
+ .ZN(_04992_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_4 _16508_ (.I(\soc.core.VexRiscv.IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[9] ),
+ .ZN(_04993_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_3 _16509_ (.I(\soc.core.VexRiscv.IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[8] ),
+ .ZN(_04994_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _16510_ (.I(net1791),
+ .ZN(_04995_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_2 _16511_ (.I(\soc.core.VexRiscv.memory_arbitration_isValid ),
+ .ZN(_04996_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_3 _16512_ (.I(net1761),
+ .ZN(_04997_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_2 _16513_ (.I(\soc.core.VexRiscv.CsrPlugin_exceptionPortCtrl_exceptionContext_code[0] ),
+ .ZN(_04998_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_1 _16514_ (.I(\soc.core.VexRiscv.DebugPlugin_resetIt ),
+ .ZN(_04999_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_1 _16515_ (.I(\soc.core.VexRiscv.DebugPlugin_stepIt ),
+ .ZN(_05000_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_2 _16516_ (.I(net2847),
+ .ZN(_05001_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_2 _16517_ (.I(\soc.core.VexRiscv.IBusCachedPlugin_cache.lineLoader_wordIndex[2] ),
+ .ZN(_05002_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _16518_ (.I(\soc.core.VexRiscv.IBusCachedPlugin_cache._zz_1 ),
+ .ZN(_05003_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_2 _16519_ (.I(\soc.core.VexRiscv.IBusCachedPlugin_cache.lineLoader_wordIndex[0] ),
+ .ZN(_05004_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_4 _16520_ (.I(\soc.core.VexRiscv.IBusCachedPlugin_cache.lineLoader_valid ),
+ .ZN(_05005_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _16521_ (.I(\soc.core.VexRiscv.IBusCachedPlugin_cache.lineLoader_flushCounter[0] ),
+ .ZN(_05006_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_2 _16522_ (.I(\soc.core.count[18] ),
+ .ZN(_05007_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_2 _16523_ (.I(\soc.core.count[16] ),
+ .ZN(_05008_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_1 _16524_ (.I(\soc.core.count[15] ),
+ .ZN(_05009_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_1 _16525_ (.I(\soc.core.count[14] ),
+ .ZN(_05010_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _16526_ (.I(\soc.core.count[10] ),
+ .ZN(_05011_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_2 _16527_ (.I(\soc.core.count[8] ),
+ .ZN(_05012_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_2 _16528_ (.I(\soc.core.count[7] ),
+ .ZN(_05013_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _16529_ (.I(\soc.core.count[5] ),
+ .ZN(_05014_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_8 _16530_ (.I(net1826),
+ .ZN(_05015_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_3 _16531_ (.I(\soc.core.grant[0] ),
+ .ZN(_05016_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_4 _16532_ (.I(\soc.core.uartwishbonebridge_state[2] ),
+ .ZN(_05017_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_3 _16533_ (.I(\soc.core.uartwishbonebridge_state[1] ),
+ .ZN(_05018_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_4 _16534_ (.I(\soc.core.uartwishbonebridge_state[0] ),
+ .ZN(_05019_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_4 _16535_ (.I(\soc.core.spimaster_state[1] ),
+ .ZN(_05020_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_4 _16536_ (.I(\soc.core.spimaster_state[0] ),
+ .ZN(_05021_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_4 _16537_ (.I(\soc.core.litespi_state[3] ),
+ .ZN(_05022_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_3 _16538_ (.I(\soc.core.litespi_state[2] ),
+ .ZN(_05023_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_2 _16539_ (.I(\soc.core.litespi_state[1] ),
+ .ZN(_05024_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_2 _16540_ (.I(\soc.core.litespi_state[0] ),
+ .ZN(_05025_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_2 _16541_ (.I(\soc.core.litespiphy_state[1] ),
+ .ZN(_05026_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_4 _16542_ (.I(\soc.core.litespiphy_state[0] ),
+ .ZN(_05027_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_1 _16543_ (.I(\soc.core.gpioin5_gpioin5_edge_storage ),
+ .ZN(_05028_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_1 _16544_ (.I(\soc.core.gpioin4_gpioin4_edge_storage ),
+ .ZN(_05029_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_1 _16545_ (.I(\soc.core.gpioin3_gpioin3_edge_storage ),
+ .ZN(_05030_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_1 _16546_ (.I(\soc.core.gpioin2_gpioin2_edge_storage ),
+ .ZN(_05031_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_1 _16547_ (.I(\soc.core.gpioin1_gpioin1_edge_storage ),
+ .ZN(_05032_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_1 _16548_ (.I(\soc.core.gpioin0_gpioin0_edge_storage ),
+ .ZN(_05033_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _16549_ (.I(\soc.core.la_oe_storage[63] ),
+ .ZN(\mgmt_buffers.la_oenb_core[63] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _16550_ (.I(\soc.core.la_oe_storage[62] ),
+ .ZN(\mgmt_buffers.la_oenb_core[62] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _16551_ (.I(\soc.core.la_oe_storage[61] ),
+ .ZN(\mgmt_buffers.la_oenb_core[61] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _16552_ (.I(\soc.core.la_oe_storage[60] ),
+ .ZN(\mgmt_buffers.la_oenb_core[60] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _16553_ (.I(\soc.core.la_oe_storage[59] ),
+ .ZN(\mgmt_buffers.la_oenb_core[59] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _16554_ (.I(\soc.core.la_oe_storage[58] ),
+ .ZN(\mgmt_buffers.la_oenb_core[58] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _16555_ (.I(\soc.core.la_oe_storage[57] ),
+ .ZN(\mgmt_buffers.la_oenb_core[57] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _16556_ (.I(\soc.core.la_oe_storage[56] ),
+ .ZN(\mgmt_buffers.la_oenb_core[56] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _16557_ (.I(\soc.core.la_oe_storage[55] ),
+ .ZN(\mgmt_buffers.la_oenb_core[55] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _16558_ (.I(\soc.core.la_oe_storage[54] ),
+ .ZN(\mgmt_buffers.la_oenb_core[54] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _16559_ (.I(\soc.core.la_oe_storage[53] ),
+ .ZN(\mgmt_buffers.la_oenb_core[53] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _16560_ (.I(\soc.core.la_oe_storage[52] ),
+ .ZN(\mgmt_buffers.la_oenb_core[52] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _16561_ (.I(\soc.core.la_oe_storage[51] ),
+ .ZN(\mgmt_buffers.la_oenb_core[51] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _16562_ (.I(\soc.core.la_oe_storage[50] ),
+ .ZN(\mgmt_buffers.la_oenb_core[50] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _16563_ (.I(\soc.core.la_oe_storage[49] ),
+ .ZN(\mgmt_buffers.la_oenb_core[49] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _16564_ (.I(\soc.core.la_oe_storage[48] ),
+ .ZN(\mgmt_buffers.la_oenb_core[48] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _16565_ (.I(\soc.core.la_oe_storage[47] ),
+ .ZN(\mgmt_buffers.la_oenb_core[47] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _16566_ (.I(\soc.core.la_oe_storage[46] ),
+ .ZN(\mgmt_buffers.la_oenb_core[46] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _16567_ (.I(\soc.core.la_oe_storage[45] ),
+ .ZN(\mgmt_buffers.la_oenb_core[45] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _16568_ (.I(\soc.core.la_oe_storage[44] ),
+ .ZN(\mgmt_buffers.la_oenb_core[44] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _16569_ (.I(\soc.core.la_oe_storage[43] ),
+ .ZN(\mgmt_buffers.la_oenb_core[43] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _16570_ (.I(\soc.core.la_oe_storage[42] ),
+ .ZN(\mgmt_buffers.la_oenb_core[42] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _16571_ (.I(\soc.core.la_oe_storage[41] ),
+ .ZN(\mgmt_buffers.la_oenb_core[41] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _16572_ (.I(\soc.core.la_oe_storage[40] ),
+ .ZN(\mgmt_buffers.la_oenb_core[40] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _16573_ (.I(\soc.core.la_oe_storage[39] ),
+ .ZN(\mgmt_buffers.la_oenb_core[39] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _16574_ (.I(\soc.core.la_oe_storage[38] ),
+ .ZN(\mgmt_buffers.la_oenb_core[38] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _16575_ (.I(\soc.core.la_oe_storage[37] ),
+ .ZN(\mgmt_buffers.la_oenb_core[37] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _16576_ (.I(\soc.core.la_oe_storage[36] ),
+ .ZN(\mgmt_buffers.la_oenb_core[36] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _16577_ (.I(\soc.core.la_oe_storage[35] ),
+ .ZN(\mgmt_buffers.la_oenb_core[35] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _16578_ (.I(\soc.core.la_oe_storage[34] ),
+ .ZN(\mgmt_buffers.la_oenb_core[34] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _16579_ (.I(\soc.core.la_oe_storage[33] ),
+ .ZN(\mgmt_buffers.la_oenb_core[33] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _16580_ (.I(\soc.core.la_oe_storage[32] ),
+ .ZN(\mgmt_buffers.la_oenb_core[32] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _16581_ (.I(\soc.core.la_ien_storage[63] ),
+ .ZN(\mgmt_buffers.la_data_in_enable[63] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _16582_ (.I(\soc.core.la_ien_storage[62] ),
+ .ZN(\mgmt_buffers.la_data_in_enable[62] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _16583_ (.I(\soc.core.la_ien_storage[61] ),
+ .ZN(\mgmt_buffers.la_data_in_enable[61] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _16584_ (.I(\soc.core.la_ien_storage[60] ),
+ .ZN(\mgmt_buffers.la_data_in_enable[60] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _16585_ (.I(\soc.core.la_ien_storage[59] ),
+ .ZN(\mgmt_buffers.la_data_in_enable[59] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _16586_ (.I(\soc.core.la_ien_storage[58] ),
+ .ZN(\mgmt_buffers.la_data_in_enable[58] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _16587_ (.I(\soc.core.la_ien_storage[57] ),
+ .ZN(\mgmt_buffers.la_data_in_enable[57] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _16588_ (.I(\soc.core.la_ien_storage[56] ),
+ .ZN(\mgmt_buffers.la_data_in_enable[56] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _16589_ (.I(\soc.core.la_ien_storage[55] ),
+ .ZN(\mgmt_buffers.la_data_in_enable[55] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _16590_ (.I(\soc.core.la_ien_storage[54] ),
+ .ZN(\mgmt_buffers.la_data_in_enable[54] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _16591_ (.I(\soc.core.la_ien_storage[53] ),
+ .ZN(\mgmt_buffers.la_data_in_enable[53] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _16592_ (.I(\soc.core.la_ien_storage[52] ),
+ .ZN(\mgmt_buffers.la_data_in_enable[52] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_2 _16593_ (.I(\soc.core.la_ien_storage[51] ),
+ .ZN(\mgmt_buffers.la_data_in_enable[51] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_2 _16594_ (.I(\soc.core.la_ien_storage[50] ),
+ .ZN(\mgmt_buffers.la_data_in_enable[50] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_3 _16595_ (.I(\soc.core.la_ien_storage[49] ),
+ .ZN(\mgmt_buffers.la_data_in_enable[49] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _16596_ (.I(\soc.core.la_ien_storage[48] ),
+ .ZN(\mgmt_buffers.la_data_in_enable[48] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _16597_ (.I(\soc.core.la_ien_storage[47] ),
+ .ZN(\mgmt_buffers.la_data_in_enable[47] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _16598_ (.I(\soc.core.la_ien_storage[46] ),
+ .ZN(\mgmt_buffers.la_data_in_enable[46] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _16599_ (.I(\soc.core.la_ien_storage[45] ),
+ .ZN(\mgmt_buffers.la_data_in_enable[45] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _16600_ (.I(\soc.core.la_ien_storage[44] ),
+ .ZN(\mgmt_buffers.la_data_in_enable[44] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _16601_ (.I(\soc.core.la_ien_storage[43] ),
+ .ZN(\mgmt_buffers.la_data_in_enable[43] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _16602_ (.I(\soc.core.la_ien_storage[42] ),
+ .ZN(\mgmt_buffers.la_data_in_enable[42] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _16603_ (.I(\soc.core.la_ien_storage[41] ),
+ .ZN(\mgmt_buffers.la_data_in_enable[41] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _16604_ (.I(net2891),
+ .ZN(\mgmt_buffers.la_data_in_enable[40] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _16605_ (.I(\soc.core.la_ien_storage[39] ),
+ .ZN(\mgmt_buffers.la_data_in_enable[39] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _16606_ (.I(\soc.core.la_ien_storage[38] ),
+ .ZN(\mgmt_buffers.la_data_in_enable[38] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _16607_ (.I(\soc.core.la_ien_storage[37] ),
+ .ZN(\mgmt_buffers.la_data_in_enable[37] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _16608_ (.I(net2926),
+ .ZN(\mgmt_buffers.la_data_in_enable[36] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _16609_ (.I(\soc.core.la_ien_storage[35] ),
+ .ZN(\mgmt_buffers.la_data_in_enable[35] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _16610_ (.I(net2946),
+ .ZN(\mgmt_buffers.la_data_in_enable[34] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _16611_ (.I(\soc.core.la_ien_storage[33] ),
+ .ZN(\mgmt_buffers.la_data_in_enable[33] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _16612_ (.I(net2867),
+ .ZN(\mgmt_buffers.la_data_in_enable[32] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_4 _16613_ (.I(\soc.core.gpio_oe_storage ),
+ .ZN(net58),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_4 _16614_ (.I(\soc.core.gpio_ien_storage ),
+ .ZN(net56),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _16615_ (.I(\soc.core.dbg_uart_count[19] ),
+ .ZN(_05034_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_1 _16616_ (.I(\soc.core.dbg_uart_count[18] ),
+ .ZN(_05035_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _16617_ (.I(\soc.core.dbg_uart_count[17] ),
+ .ZN(_05036_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _16618_ (.I(\soc.core.dbg_uart_count[15] ),
+ .ZN(_05037_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_1 _16619_ (.I(\soc.core.dbg_uart_count[13] ),
+ .ZN(_05038_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _16620_ (.I(\soc.core.dbg_uart_count[11] ),
+ .ZN(_05039_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _16621_ (.I(\soc.core.dbg_uart_count[2] ),
+ .ZN(_05040_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_1 _16622_ (.I(\soc.core.dbg_uart_count[0] ),
+ .ZN(_05041_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_3 _16623_ (.I(\soc.core.dbg_uart_words_count[6] ),
+ .ZN(_05042_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_1 _16624_ (.I(\soc.core.dbg_uart_words_count[4] ),
+ .ZN(_05043_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_8 _16625_ (.I(\soc.core.dbg_uart_bytes_count[1] ),
+ .ZN(_05044_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_1 _16626_ (.I(\soc.core.dbg_uart_data[30] ),
+ .ZN(_05045_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_1 _16627_ (.I(\soc.core.dbg_uart_data[29] ),
+ .ZN(_05046_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_1 _16628_ (.I(\soc.core.dbg_uart_data[28] ),
+ .ZN(_05047_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_1 _16629_ (.I(\soc.core.dbg_uart_data[27] ),
+ .ZN(_05048_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _16630_ (.I(\soc.core.dbg_uart_data[26] ),
+ .ZN(_05049_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_1 _16631_ (.I(\soc.core.dbg_uart_data[25] ),
+ .ZN(_05050_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_1 _16632_ (.I(\soc.core.dbg_uart_data[24] ),
+ .ZN(_05051_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _16633_ (.I(\soc.core.dbg_uart_data[22] ),
+ .ZN(_05052_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _16634_ (.I(\soc.core.dbg_uart_data[21] ),
+ .ZN(_05053_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _16635_ (.I(\soc.core.dbg_uart_data[19] ),
+ .ZN(_05054_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _16636_ (.I(\soc.core.dbg_uart_data[17] ),
+ .ZN(_05055_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _16637_ (.I(\soc.core.dbg_uart_data[16] ),
+ .ZN(_05056_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_1 _16638_ (.I(\soc.core.dbg_uart_data[7] ),
+ .ZN(_05057_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_2 _16639_ (.I(\soc.core.dbg_uart_data[6] ),
+ .ZN(_05058_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_2 _16640_ (.I(\soc.core.dbg_uart_data[5] ),
+ .ZN(_05059_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_2 _16641_ (.I(\soc.core.dbg_uart_data[4] ),
+ .ZN(_05060_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_1 _16642_ (.I(\soc.core.dbg_uart_data[3] ),
+ .ZN(_05061_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_1 _16643_ (.I(\soc.core.dbg_uart_data[2] ),
+ .ZN(_05062_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_1 _16644_ (.I(\soc.core.dbg_uart_data[1] ),
+ .ZN(_05063_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _16645_ (.I(\soc.core.dbg_uart_data[0] ),
+ .ZN(_05064_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_2 _16646_ (.I(\soc.core.dbg_uart_address[25] ),
+ .ZN(_05065_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_2 _16647_ (.I(\soc.core.dbg_uart_address[22] ),
+ .ZN(_05066_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_1 _16648_ (.I(\soc.core.dbg_uart_address[6] ),
+ .ZN(_05067_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_1 _16649_ (.I(\soc.core.dbg_uart_address[5] ),
+ .ZN(_05068_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _16650_ (.I(\soc.core.dbg_uart_cmd[3] ),
+ .ZN(_05069_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _16651_ (.I(\soc.core.dbg_uart_cmd[1] ),
+ .ZN(_05070_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_1 _16652_ (.I(\soc.core.dbg_uart_cmd[0] ),
+ .ZN(_05071_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_1 _16653_ (.I(\soc.core.multiregimpl1_regs1 ),
+ .ZN(_05072_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_1 _16654_ (.I(net1834),
+ .ZN(_05073_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_1 _16655_ (.I(\soc.core.dbg_uart_rx_data[6] ),
+ .ZN(_05074_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_1 _16656_ (.I(\soc.core.dbg_uart_rx_data[5] ),
+ .ZN(_05075_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_1 _16657_ (.I(\soc.core.dbg_uart_rx_data[4] ),
+ .ZN(_05076_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_1 _16658_ (.I(\soc.core.dbg_uart_rx_data[3] ),
+ .ZN(_05077_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_1 _16659_ (.I(\soc.core.dbg_uart_rx_data[2] ),
+ .ZN(_05078_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_1 _16660_ (.I(\soc.core.dbg_uart_rx_data[1] ),
+ .ZN(_05079_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _16661_ (.I(\soc.core.dbg_uart_tx_count[3] ),
+ .ZN(_05080_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _16662_ (.I(\soc.core.dbg_uart_tx_data[7] ),
+ .ZN(_05081_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_1 _16663_ (.I(\soc.core.dbg_uart_tx_data[6] ),
+ .ZN(_05082_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_1 _16664_ (.I(\soc.core.dbg_uart_tx_data[5] ),
+ .ZN(_05083_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_1 _16665_ (.I(\soc.core.dbg_uart_tx_data[4] ),
+ .ZN(_05084_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_1 _16666_ (.I(\soc.core.dbg_uart_tx_data[3] ),
+ .ZN(_05085_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_1 _16667_ (.I(\soc.core.dbg_uart_tx_data[2] ),
+ .ZN(_05086_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_1 _16668_ (.I(\soc.core.dbg_uart_tx_data[1] ),
+ .ZN(_05087_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_1 _16669_ (.I(\soc.core.dbg_uart_tx_data[0] ),
+ .ZN(_05088_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _16670_ (.I(\soc.core.uart_rx_fifo_consume[3] ),
+ .ZN(_05089_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_2 _16671_ (.I(\soc.core.uart_rx_fifo_consume[1] ),
+ .ZN(_05090_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_8 _16672_ (.I(net1836),
+ .ZN(_05091_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_4 _16673_ (.I(\soc.core.uart_rx_fifo_produce[3] ),
+ .ZN(_05092_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_4 _16674_ (.I(\soc.core.uart_rx_fifo_produce[2] ),
+ .ZN(_05093_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_2 _16675_ (.I(\soc.core.uart_rx_fifo_produce[1] ),
+ .ZN(_05094_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_3 _16676_ (.I(\soc.core.uart_rx_fifo_level0[4] ),
+ .ZN(_05095_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_2 _16677_ (.I(\soc.core.uart_rx_fifo_level0[3] ),
+ .ZN(_05096_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_2 _16678_ (.I(\soc.core.uart_rx_fifo_readable ),
+ .ZN(_05097_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_2 _16679_ (.I(\soc.core.uart_tx_fifo_consume[3] ),
+ .ZN(_05098_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _16680_ (.I(net1840),
+ .ZN(_05099_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_8 _16681_ (.I(\soc.core.uart_tx_fifo_consume[1] ),
+ .ZN(_05100_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_4 _16682_ (.I(net1841),
+ .ZN(_05101_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_3 _16683_ (.I(\soc.core.uart_tx_fifo_produce[3] ),
+ .ZN(_05102_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_2 _16684_ (.I(\soc.core.uart_tx_fifo_produce[2] ),
+ .ZN(_05103_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_3 _16685_ (.I(\soc.core.uart_tx_fifo_produce[1] ),
+ .ZN(_05104_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_3 _16686_ (.I(\soc.core.uart_tx_fifo_produce[0] ),
+ .ZN(_05105_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_1 _16687_ (.I(\soc.core.uart_tx_fifo_readable ),
+ .ZN(_05106_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_2 _16688_ (.I(\soc.core.multiregimpl0_regs1 ),
+ .ZN(_05107_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _16689_ (.I(\soc.core.spimaster_storage[15] ),
+ .ZN(_05108_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_1 _16690_ (.I(\soc.core.spimaster_storage[14] ),
+ .ZN(_05109_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _16691_ (.I(\soc.core.spimaster_storage[13] ),
+ .ZN(_05110_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_2 _16692_ (.I(\soc.core.spimaster_storage[12] ),
+ .ZN(_05111_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_2 _16693_ (.I(\soc.core.spimaster_storage[11] ),
+ .ZN(_05112_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_2 _16694_ (.I(\soc.core.spimaster_storage[10] ),
+ .ZN(_05113_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_2 _16695_ (.I(\soc.core.spimaster_storage[9] ),
+ .ZN(_05114_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_1 _16696_ (.I(\soc.core.spimaster_storage[8] ),
+ .ZN(_05115_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _16697_ (.I(\soc.core.spimaster_storage[7] ),
+ .ZN(_05116_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_2 _16698_ (.I(\soc.core.spimaster_storage[6] ),
+ .ZN(_05117_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_2 _16699_ (.I(\soc.core.spimaster_storage[5] ),
+ .ZN(_05118_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_2 _16700_ (.I(\soc.core.spimaster_storage[4] ),
+ .ZN(_05119_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_2 _16701_ (.I(\soc.core.spimaster_storage[3] ),
+ .ZN(_05120_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_1 _16702_ (.I(\soc.core.spi_master_miso_data[7] ),
+ .ZN(_05121_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_2 _16703_ (.I(\soc.core.spi_master_miso_data[6] ),
+ .ZN(_05122_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_2 _16704_ (.I(\soc.core.spi_master_miso_data[5] ),
+ .ZN(_05123_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_2 _16705_ (.I(\soc.core.spi_master_miso_data[4] ),
+ .ZN(_05124_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_2 _16706_ (.I(\soc.core.spi_master_miso_data[3] ),
+ .ZN(_05125_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_2 _16707_ (.I(\soc.core.spi_master_miso_data[2] ),
+ .ZN(_05126_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_2 _16708_ (.I(\soc.core.spi_master_miso_data[1] ),
+ .ZN(_05127_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_3 _16709_ (.I(\soc.core.spi_master_miso_data[0] ),
+ .ZN(_05128_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _16710_ (.I(\soc.core.spi_master_mosi_sel[2] ),
+ .ZN(_05129_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_2 _16711_ (.I(\soc.core.spi_master_mosi_sel[1] ),
+ .ZN(_05130_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_1 _16712_ (.I(\soc.core.spi_master_mosi_storage[7] ),
+ .ZN(_05131_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_2 _16713_ (.I(\soc.core.spi_master_mosi_data[6] ),
+ .ZN(_05132_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_1 _16714_ (.I(\soc.core.spi_master_mosi_storage[5] ),
+ .ZN(_05133_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_1 _16715_ (.I(\soc.core.spi_master_mosi_storage[4] ),
+ .ZN(_05134_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_1 _16716_ (.I(\soc.core.spi_master_mosi_storage[3] ),
+ .ZN(_05135_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_2 _16717_ (.I(\soc.core.spi_master_mosi_data[2] ),
+ .ZN(_05136_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_1 _16718_ (.I(\soc.core.spi_master_mosi_storage[1] ),
+ .ZN(_05137_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_1 _16719_ (.I(\soc.core.spi_master_mosi_storage[0] ),
+ .ZN(_05138_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_2 _16720_ (.I(\soc.core.spi_master_count[0] ),
+ .ZN(_05139_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_2 _16721_ (.I(\soc.core.spi_master_cs_mode ),
+ .ZN(_05140_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_2 _16722_ (.I(\soc.core.spi_master_control_storage[10] ),
+ .ZN(_05141_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_1 _16723_ (.I(\soc.core.mgmtsoc_master_phyconfig_storage[16] ),
+ .ZN(_05142_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_1 _16724_ (.I(\soc.core.mgmtsoc_master_phyconfig_storage[11] ),
+ .ZN(_05143_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_2 _16725_ (.I(\soc.core.mgmtsoc_master_phyconfig_storage[10] ),
+ .ZN(_05144_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_1 _16726_ (.I(\soc.core.mgmtsoc_master_phyconfig_storage[9] ),
+ .ZN(_05145_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_2 _16727_ (.I(\soc.core.mgmtsoc_master_phyconfig_storage[8] ),
+ .ZN(_05146_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_1 _16728_ (.I(\soc.core.mgmtsoc_master_phyconfig_storage[5] ),
+ .ZN(_05147_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_1 _16729_ (.I(\soc.core.mgmtsoc_master_phyconfig_storage[4] ),
+ .ZN(_05148_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_1 _16730_ (.I(\soc.core.mgmtsoc_master_phyconfig_storage[3] ),
+ .ZN(_05149_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_1 _16731_ (.I(\soc.core.mgmtsoc_master_phyconfig_storage[2] ),
+ .ZN(_05150_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_1 _16732_ (.I(\soc.core.mgmtsoc_master_phyconfig_storage[1] ),
+ .ZN(_05151_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_1 _16733_ (.I(\soc.core.mgmtsoc_master_phyconfig_storage[0] ),
+ .ZN(_05152_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _16734_ (.I(\soc.core.mgmtsoc_master_tx_fifo_source_payload_data[11] ),
+ .ZN(_05153_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _16735_ (.I(\soc.core.mgmtsoc_master_tx_fifo_source_payload_data[2] ),
+ .ZN(_05154_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_2 _16736_ (.I(\soc.core.mgmtsoc_litespimmap_storage[3] ),
+ .ZN(_05155_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _16737_ (.I(\soc.core.mgmtsoc_litespimmap_storage[0] ),
+ .ZN(_05156_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _16738_ (.I(\soc.core.mgmtsoc_litespimmap_count[7] ),
+ .ZN(_05157_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _16739_ (.I(\soc.core.mgmtsoc_litespimmap_count[2] ),
+ .ZN(_05158_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_2 _16740_ (.I(\soc.core.mgmtsoc_litespisdrphycore_count[3] ),
+ .ZN(_05159_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _16741_ (.I(\soc.core.mgmtsoc_litespisdrphycore_count[0] ),
+ .ZN(_05160_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_2 _16742_ (.I(\soc.core.mgmtsoc_litespisdrphycore_clk ),
+ .ZN(_05161_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_4 _16743_ (.I(\soc.core.mgmtsoc_litespisdrphycore_storage[7] ),
+ .ZN(_05162_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_3 _16744_ (.I(\soc.core.mgmtsoc_litespisdrphycore_storage[6] ),
+ .ZN(_05163_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_2 _16745_ (.I(\soc.core.mgmtsoc_litespisdrphycore_storage[3] ),
+ .ZN(_05164_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_2 _16746_ (.I(\soc.core.mgmtsoc_litespisdrphycore_storage[2] ),
+ .ZN(_05165_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_3 _16747_ (.I(\soc.core.mgmtsoc_litespisdrphycore_storage[1] ),
+ .ZN(_05166_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_3 _16748_ (.I(\soc.core.mgmtsoc_litespisdrphycore_storage[0] ),
+ .ZN(_05167_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_1 _16749_ (.I(net1850),
+ .ZN(_05168_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_4 _16750_ (.I(\soc.core.mgmtsoc_value[30] ),
+ .ZN(_05169_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_2 _16751_ (.I(\soc.core.mgmtsoc_value[29] ),
+ .ZN(_05170_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_3 _16752_ (.I(\soc.core.mgmtsoc_value[28] ),
+ .ZN(_05171_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_2 _16753_ (.I(\soc.core.mgmtsoc_value[27] ),
+ .ZN(_05172_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_2 _16754_ (.I(\soc.core.mgmtsoc_value[26] ),
+ .ZN(_05173_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_3 _16755_ (.I(\soc.core.mgmtsoc_value[25] ),
+ .ZN(_05174_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_3 _16756_ (.I(\soc.core.mgmtsoc_value[24] ),
+ .ZN(_05175_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_3 _16757_ (.I(\soc.core.mgmtsoc_value[23] ),
+ .ZN(_05176_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_3 _16758_ (.I(\soc.core.mgmtsoc_value[22] ),
+ .ZN(_05177_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_3 _16759_ (.I(\soc.core.mgmtsoc_value[21] ),
+ .ZN(_05178_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_2 _16760_ (.I(\soc.core.mgmtsoc_value[20] ),
+ .ZN(_05179_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_3 _16761_ (.I(\soc.core.mgmtsoc_value[19] ),
+ .ZN(_05180_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_3 _16762_ (.I(\soc.core.mgmtsoc_value[18] ),
+ .ZN(_05181_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_3 _16763_ (.I(\soc.core.mgmtsoc_value[17] ),
+ .ZN(_05182_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_3 _16764_ (.I(\soc.core.mgmtsoc_value[16] ),
+ .ZN(_05183_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_3 _16765_ (.I(\soc.core.mgmtsoc_value[15] ),
+ .ZN(_05184_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_3 _16766_ (.I(\soc.core.mgmtsoc_value[14] ),
+ .ZN(_05185_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_3 _16767_ (.I(\soc.core.mgmtsoc_value[13] ),
+ .ZN(_05186_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_3 _16768_ (.I(\soc.core.mgmtsoc_value[12] ),
+ .ZN(_05187_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_2 _16769_ (.I(\soc.core.mgmtsoc_value[11] ),
+ .ZN(_05188_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_2 _16770_ (.I(\soc.core.mgmtsoc_value[10] ),
+ .ZN(_05189_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_3 _16771_ (.I(\soc.core.mgmtsoc_value[9] ),
+ .ZN(_05190_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_2 _16772_ (.I(\soc.core.mgmtsoc_value[8] ),
+ .ZN(_05191_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_2 _16773_ (.I(\soc.core.mgmtsoc_value[7] ),
+ .ZN(_05192_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_3 _16774_ (.I(\soc.core.mgmtsoc_value[6] ),
+ .ZN(_05193_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_2 _16775_ (.I(\soc.core.mgmtsoc_value[5] ),
+ .ZN(_05194_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_2 _16776_ (.I(\soc.core.mgmtsoc_value[4] ),
+ .ZN(_05195_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_3 _16777_ (.I(\soc.core.mgmtsoc_value[3] ),
+ .ZN(_05196_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_3 _16778_ (.I(\soc.core.mgmtsoc_value[2] ),
+ .ZN(_05197_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_1 _16779_ (.I(\soc.core.mgmtsoc_value[1] ),
+ .ZN(_05198_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_3 _16780_ (.I(\soc.core.mgmtsoc_value[0] ),
+ .ZN(_05199_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_4 _16781_ (.I(net1855),
+ .ZN(_05200_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _16782_ (.I(\soc.core.mgmtsoc_load_storage[31] ),
+ .ZN(_05201_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _16783_ (.I(\soc.core.mgmtsoc_load_storage[27] ),
+ .ZN(_05202_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_2 _16784_ (.I(\soc.core.mgmtsoc_vexriscv_transfer_complete ),
+ .ZN(_05203_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_1 _16785_ (.I(\soc.core.mgmtsoc_bus_errors[30] ),
+ .ZN(_05204_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_1 _16786_ (.I(\soc.core.mgmtsoc_bus_errors[28] ),
+ .ZN(_05205_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_1 _16787_ (.I(\soc.core.mgmtsoc_bus_errors[24] ),
+ .ZN(_05206_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_1 _16788_ (.I(\soc.core.mgmtsoc_bus_errors[19] ),
+ .ZN(_05207_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_2 _16789_ (.I(\soc.core.mgmtsoc_bus_errors[17] ),
+ .ZN(_05208_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_1 _16790_ (.I(\soc.core.mgmtsoc_bus_errors[15] ),
+ .ZN(_05209_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_1 _16791_ (.I(\soc.core.mgmtsoc_bus_errors[13] ),
+ .ZN(_05210_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_4 _16792_ (.I(\pll.pll_control.tint[4] ),
+ .ZN(_05211_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_2 _16793_ (.I(\pll.pll_control.tint[3] ),
+ .ZN(_05212_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_3 _16794_ (.I(\pll.pll_control.tint[2] ),
+ .ZN(_05213_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_4 _16795_ (.I(\pll.pll_control.tint[1] ),
+ .ZN(_05214_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_4 _16796_ (.I(\pll.pll_control.tint[0] ),
+ .ZN(_05215_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _16797_ (.I(\pll.pll_control.tval[1] ),
+ .ZN(_05216_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _16798_ (.I(\soc.core.la_ien_storage[31] ),
+ .ZN(\mgmt_buffers.la_data_in_enable[31] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _16799_ (.I(\soc.core.la_ien_storage[30] ),
+ .ZN(\mgmt_buffers.la_data_in_enable[30] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _16800_ (.I(\soc.core.la_ien_storage[29] ),
+ .ZN(\mgmt_buffers.la_data_in_enable[29] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _16801_ (.I(\soc.core.la_ien_storage[28] ),
+ .ZN(\mgmt_buffers.la_data_in_enable[28] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _16802_ (.I(\soc.core.la_ien_storage[27] ),
+ .ZN(\mgmt_buffers.la_data_in_enable[27] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _16803_ (.I(\soc.core.la_ien_storage[26] ),
+ .ZN(\mgmt_buffers.la_data_in_enable[26] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _16804_ (.I(\soc.core.la_ien_storage[25] ),
+ .ZN(\mgmt_buffers.la_data_in_enable[25] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _16805_ (.I(\soc.core.la_ien_storage[24] ),
+ .ZN(\mgmt_buffers.la_data_in_enable[24] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _16806_ (.I(\soc.core.la_ien_storage[23] ),
+ .ZN(\mgmt_buffers.la_data_in_enable[23] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _16807_ (.I(\soc.core.la_ien_storage[22] ),
+ .ZN(\mgmt_buffers.la_data_in_enable[22] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _16808_ (.I(\soc.core.la_ien_storage[21] ),
+ .ZN(\mgmt_buffers.la_data_in_enable[21] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _16809_ (.I(\soc.core.la_ien_storage[20] ),
+ .ZN(\mgmt_buffers.la_data_in_enable[20] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _16810_ (.I(\soc.core.la_ien_storage[19] ),
+ .ZN(\mgmt_buffers.la_data_in_enable[19] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _16811_ (.I(\soc.core.la_ien_storage[18] ),
+ .ZN(\mgmt_buffers.la_data_in_enable[18] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _16812_ (.I(\soc.core.la_ien_storage[17] ),
+ .ZN(\mgmt_buffers.la_data_in_enable[17] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _16813_ (.I(\soc.core.la_ien_storage[16] ),
+ .ZN(\mgmt_buffers.la_data_in_enable[16] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _16814_ (.I(\soc.core.la_ien_storage[15] ),
+ .ZN(\mgmt_buffers.la_data_in_enable[15] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _16815_ (.I(\soc.core.la_ien_storage[14] ),
+ .ZN(\mgmt_buffers.la_data_in_enable[14] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _16816_ (.I(\soc.core.la_ien_storage[13] ),
+ .ZN(\mgmt_buffers.la_data_in_enable[13] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _16817_ (.I(\soc.core.la_ien_storage[12] ),
+ .ZN(\mgmt_buffers.la_data_in_enable[12] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _16818_ (.I(\soc.core.la_ien_storage[11] ),
+ .ZN(\mgmt_buffers.la_data_in_enable[11] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _16819_ (.I(\soc.core.la_ien_storage[10] ),
+ .ZN(\mgmt_buffers.la_data_in_enable[10] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _16820_ (.I(\soc.core.la_ien_storage[9] ),
+ .ZN(\mgmt_buffers.la_data_in_enable[9] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _16821_ (.I(\soc.core.la_ien_storage[8] ),
+ .ZN(\mgmt_buffers.la_data_in_enable[8] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _16822_ (.I(\soc.core.la_ien_storage[7] ),
+ .ZN(\mgmt_buffers.la_data_in_enable[7] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _16823_ (.I(\soc.core.la_ien_storage[6] ),
+ .ZN(\mgmt_buffers.la_data_in_enable[6] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _16824_ (.I(\soc.core.la_ien_storage[5] ),
+ .ZN(\mgmt_buffers.la_data_in_enable[5] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _16825_ (.I(\soc.core.la_ien_storage[4] ),
+ .ZN(\mgmt_buffers.la_data_in_enable[4] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _16826_ (.I(\soc.core.la_ien_storage[3] ),
+ .ZN(\mgmt_buffers.la_data_in_enable[3] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _16827_ (.I(\soc.core.la_ien_storage[2] ),
+ .ZN(\mgmt_buffers.la_data_in_enable[2] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _16828_ (.I(\soc.core.la_ien_storage[1] ),
+ .ZN(\mgmt_buffers.la_data_in_enable[1] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _16829_ (.I(\soc.core.la_ien_storage[0] ),
+ .ZN(\mgmt_buffers.la_data_in_enable[0] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _16830_ (.I(\soc.core.la_oe_storage[31] ),
+ .ZN(\mgmt_buffers.la_oenb_core[31] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _16831_ (.I(\soc.core.la_oe_storage[30] ),
+ .ZN(\mgmt_buffers.la_oenb_core[30] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _16832_ (.I(\soc.core.la_oe_storage[29] ),
+ .ZN(\mgmt_buffers.la_oenb_core[29] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _16833_ (.I(\soc.core.la_oe_storage[28] ),
+ .ZN(\mgmt_buffers.la_oenb_core[28] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _16834_ (.I(\soc.core.la_oe_storage[27] ),
+ .ZN(\mgmt_buffers.la_oenb_core[27] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _16835_ (.I(\soc.core.la_oe_storage[26] ),
+ .ZN(\mgmt_buffers.la_oenb_core[26] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _16836_ (.I(\soc.core.la_oe_storage[25] ),
+ .ZN(\mgmt_buffers.la_oenb_core[25] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _16837_ (.I(\soc.core.la_oe_storage[24] ),
+ .ZN(\mgmt_buffers.la_oenb_core[24] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _16838_ (.I(\soc.core.la_oe_storage[23] ),
+ .ZN(\mgmt_buffers.la_oenb_core[23] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _16839_ (.I(\soc.core.la_oe_storage[22] ),
+ .ZN(\mgmt_buffers.la_oenb_core[22] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _16840_ (.I(\soc.core.la_oe_storage[21] ),
+ .ZN(\mgmt_buffers.la_oenb_core[21] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _16841_ (.I(\soc.core.la_oe_storage[20] ),
+ .ZN(\mgmt_buffers.la_oenb_core[20] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _16842_ (.I(\soc.core.la_oe_storage[19] ),
+ .ZN(\mgmt_buffers.la_oenb_core[19] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _16843_ (.I(\soc.core.la_oe_storage[18] ),
+ .ZN(\mgmt_buffers.la_oenb_core[18] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _16844_ (.I(\soc.core.la_oe_storage[17] ),
+ .ZN(\mgmt_buffers.la_oenb_core[17] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _16845_ (.I(\soc.core.la_oe_storage[16] ),
+ .ZN(\mgmt_buffers.la_oenb_core[16] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _16846_ (.I(\soc.core.la_oe_storage[15] ),
+ .ZN(\mgmt_buffers.la_oenb_core[15] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _16847_ (.I(\soc.core.la_oe_storage[14] ),
+ .ZN(\mgmt_buffers.la_oenb_core[14] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _16848_ (.I(\soc.core.la_oe_storage[13] ),
+ .ZN(\mgmt_buffers.la_oenb_core[13] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _16849_ (.I(net1902),
+ .ZN(\mgmt_buffers.la_oenb_core[12] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _16850_ (.I(net1903),
+ .ZN(\mgmt_buffers.la_oenb_core[11] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _16851_ (.I(\soc.core.la_oe_storage[10] ),
+ .ZN(\mgmt_buffers.la_oenb_core[10] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _16852_ (.I(\soc.core.la_oe_storage[9] ),
+ .ZN(\mgmt_buffers.la_oenb_core[9] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _16853_ (.I(\soc.core.la_oe_storage[8] ),
+ .ZN(\mgmt_buffers.la_oenb_core[8] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_3 _16854_ (.I(\soc.core.la_oe_storage[7] ),
+ .ZN(\mgmt_buffers.la_oenb_core[7] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_3 _16855_ (.I(\soc.core.la_oe_storage[6] ),
+ .ZN(\mgmt_buffers.la_oenb_core[6] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _16856_ (.I(net1904),
+ .ZN(\mgmt_buffers.la_oenb_core[5] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _16857_ (.I(net1905),
+ .ZN(\mgmt_buffers.la_oenb_core[4] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _16858_ (.I(net1906),
+ .ZN(\mgmt_buffers.la_oenb_core[3] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _16859_ (.I(net1907),
+ .ZN(\mgmt_buffers.la_oenb_core[2] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _16860_ (.I(net1908),
+ .ZN(\mgmt_buffers.la_oenb_core[1] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _16861_ (.I(net1909),
+ .ZN(\mgmt_buffers.la_oenb_core[0] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_12 _16862_ (.I(net1766),
+ .ZN(_05217_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_12 _16863_ (.I(net1765),
+ .ZN(_05218_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_2 _16864_ (.I(\soc.core.VexRiscv.CsrPlugin_selfException_payload_badAddr[20] ),
+ .ZN(_05219_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_4 _16865_ (.I(\clock_ctrl.divider.even_0.N[2] ),
+ .ZN(_05220_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_3 _16866_ (.I(\clock_ctrl.divider.even_0.N[1] ),
+ .ZN(_05221_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_3 _16867_ (.I(\clock_ctrl.divider.even_0.N[0] ),
+ .ZN(_05222_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_4 _16868_ (.I(\clock_ctrl.divider2.even_0.N[2] ),
+ .ZN(_05223_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_3 _16869_ (.I(\clock_ctrl.divider2.even_0.N[1] ),
+ .ZN(_05224_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_2 _16870_ (.I(\clock_ctrl.divider2.even_0.N[0] ),
+ .ZN(_05225_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _16871_ (.I(\soc.core.uart_phy_tx_count[1] ),
+ .ZN(_05226_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_12 _16872_ (.I(net1830),
+ .ZN(_05227_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_4 _16873_ (.I(\soc.core.state ),
+ .ZN(_05228_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_1 _16874_ (.I(\soc.core.VexRiscv.dBusWishbone_ADR[22] ),
+ .ZN(_05229_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_2 _16875_ (.I(\soc.core.VexRiscv.dBusWishbone_ADR[25] ),
+ .ZN(_05230_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_2 _16876_ (.I(\soc.core.VexRiscv.IBusCachedPlugin_cache.lineLoader_address[5] ),
+ .ZN(_05231_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_2 _16877_ (.I(\soc.core.uart_phy_rx_count[3] ),
+ .ZN(_05232_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_4 _16878_ (.I(net1829),
+ .ZN(_05233_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _16879_ (.I(\soc.core.VexRiscv.DebugPlugin_haltIt ),
+ .ZN(_05234_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_2 _16880_ (.I(\soc.core.VexRiscv.IBusCachedPlugin_cache.decodeStage_hit_valid ),
+ .ZN(_05235_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_1 _16881_ (.I(\soc.core.bus_ack ),
+ .ZN(_05236_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_12 _16882_ (.I(net1831),
+ .ZN(_05237_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _16883_ (.I(\soc.core.VexRiscv.decode_to_execute_MEMORY_ENABLE ),
+ .ZN(_05238_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_16 _16884_ (.I(net1776),
+ .ZN(_05239_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_4 _16885_ (.I(\soc.core.VexRiscv.CsrPlugin_selfException_payload_badAddr[12] ),
+ .ZN(_05240_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_8 _16886_ (.I(\soc.core.VexRiscv._zz_execute_SRC1_CTRL[1] ),
+ .ZN(_05241_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_8 _16887_ (.I(\soc.core.VexRiscv._zz_execute_SRC1_CTRL[0] ),
+ .ZN(_05242_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_4 _16888_ (.I(net1769),
+ .ZN(_05243_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_8 _16889_ (.I(net1750),
+ .ZN(_05244_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_4 _16890_ (.I(\soc.core.VexRiscv.CsrPlugin_selfException_payload_badAddr[8] ),
+ .ZN(_05245_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_2 _16891_ (.I(\soc.core.VexRiscv.CsrPlugin_selfException_payload_badAddr[21] ),
+ .ZN(_05246_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_2 _16892_ (.I(\soc.core.VexRiscv._zz_execute_SHIFT_CTRL[1] ),
+ .ZN(_05247_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_3 _16893_ (.I(\soc.core.VexRiscv._zz_execute_SRC2[4] ),
+ .ZN(_05248_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _16894_ (.I(\soc.core.VexRiscv._zz_dBus_cmd_payload_data[4] ),
+ .ZN(_05249_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_4 _16895_ (.I(net2893),
+ .ZN(_05250_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_4 _16896_ (.I(\soc.core.VexRiscv.CsrPlugin_selfException_payload_badAddr[9] ),
+ .ZN(_05251_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_3 _16897_ (.I(\soc.core.VexRiscv._zz_execute_SRC2[3] ),
+ .ZN(_05252_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_4 _16898_ (.I(\soc.core.VexRiscv.CsrPlugin_selfException_payload_badAddr[10] ),
+ .ZN(_05253_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_1 _16899_ (.I(\soc.core.VexRiscv.CsrPlugin_selfException_payload_badAddr[23] ),
+ .ZN(_05254_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_2 _16900_ (.I(\soc.core.VexRiscv.lastStageIsFiring ),
+ .ZN(_05255_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_4 _16901_ (.I(\soc.core.VexRiscv.IBusCachedPlugin_cache.io_cpu_decode_data[2] ),
+ .ZN(_05256_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_8 _16902_ (.I(\soc.core.VexRiscv.IBusCachedPlugin_cache.io_cpu_decode_data[12] ),
+ .ZN(_05257_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_8 _16903_ (.I(\soc.core.VexRiscv.IBusCachedPlugin_cache.io_cpu_decode_data[14] ),
+ .ZN(_05258_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _16904_ (.I(net1808),
+ .ZN(_05259_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_2 _16905_ (.I(\soc.core.VexRiscv.IBusCachedPlugin_cache.io_cpu_decode_data[3] ),
+ .ZN(_05260_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_4 _16906_ (.I(\soc.core.VexRiscv.IBusCachedPlugin_cache.io_cpu_decode_data[4] ),
+ .ZN(_05261_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_4 _16907_ (.I(net1809),
+ .ZN(_05262_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_2 _16908_ (.I(\soc.core.VexRiscv.HazardSimplePlugin_writeBackBuffer_payload_address[0] ),
+ .ZN(_05263_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_2 _16909_ (.I(\soc.core.VexRiscv.IBusCachedPlugin_cache.io_cpu_decode_data[15] ),
+ .ZN(_05264_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_2 _16910_ (.I(\soc.core.VexRiscv.HazardSimplePlugin_writeBackBuffer_payload_address[1] ),
+ .ZN(_05265_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_4 _16911_ (.I(\soc.core.VexRiscv.IBusCachedPlugin_cache.io_cpu_decode_data[16] ),
+ .ZN(_05266_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_3 _16912_ (.I(\soc.core.VexRiscv.HazardSimplePlugin_writeBackBuffer_payload_address[2] ),
+ .ZN(_05267_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_8 _16913_ (.I(\soc.core.VexRiscv.IBusCachedPlugin_cache.io_cpu_decode_data[17] ),
+ .ZN(_05268_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_3 _16914_ (.I(\soc.core.VexRiscv.IBusCachedPlugin_cache.io_cpu_decode_data[18] ),
+ .ZN(_05269_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_3 _16915_ (.I(\soc.core.VexRiscv.HazardSimplePlugin_writeBackWrites_payload_address[1] ),
+ .ZN(_05270_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_8 _16916_ (.I(\soc.core.VexRiscv.HazardSimplePlugin_writeBackWrites_payload_address[2] ),
+ .ZN(_05271_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_1 _16917_ (.I(\soc.core.VexRiscv.execute_to_memory_INSTRUCTION[9] ),
+ .ZN(_05272_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_2 _16918_ (.I(\soc.core.VexRiscv.execute_to_memory_INSTRUCTION[11] ),
+ .ZN(_05273_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _16919_ (.I(net1810),
+ .ZN(_05274_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_8 _16920_ (.I(\soc.core.VexRiscv.IBusCachedPlugin_cache.io_cpu_decode_data[20] ),
+ .ZN(_05275_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_4 _16921_ (.I(\soc.core.VexRiscv.IBusCachedPlugin_cache.io_cpu_decode_data[21] ),
+ .ZN(_05276_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_2 _16922_ (.I(\soc.core.VexRiscv.IBusCachedPlugin_cache.io_cpu_decode_data[22] ),
+ .ZN(_05277_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_4 _16923_ (.I(\soc.core.VexRiscv.IBusCachedPlugin_cache.io_cpu_decode_data[23] ),
+ .ZN(_05278_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_2 _16924_ (.I(\soc.core.VexRiscv._zz_execute_ENV_CTRL[0] ),
+ .ZN(_05279_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_4 _16925_ (.I(net1865),
+ .ZN(_05280_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_1 _16926_ (.I(\soc.core.VexRiscv.IBusCachedPlugin_cache.io_cpu_decode_data[10] ),
+ .ZN(_05281_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_3 _16927_ (.I(\soc.core.VexRiscv.execute_to_memory_BRANCH_DO ),
+ .ZN(_05282_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_1 _16928_ (.I(\soc.core.VexRiscv.CsrPlugin_exceptionPendings_2 ),
+ .ZN(_05283_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _16929_ (.I(\soc.core.VexRiscv.CsrPlugin_exceptionPendings_0 ),
+ .ZN(_05284_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_1 _16930_ (.I(\soc.core.VexRiscv.execute_CsrPlugin_csr_836 ),
+ .ZN(_05285_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_1 _16931_ (.I(\soc.core.VexRiscv.execute_CsrPlugin_csr_773 ),
+ .ZN(_05286_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_1 _16932_ (.I(\soc.core.VexRiscv.execute_CsrPlugin_csr_772 ),
+ .ZN(_05287_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_2 _16933_ (.I(\soc.core.dbg_uart_rx_count[1] ),
+ .ZN(_05288_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_2 _16934_ (.I(\soc.core.dbg_uart_rx_count[3] ),
+ .ZN(_05289_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_2 _16935_ (.I(\soc.core.uartwishbonebridge_rs232phyrx_state ),
+ .ZN(_05290_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_8 _16936_ (.I(net1828),
+ .ZN(_05291_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_3 _16937_ (.I(\soc.core.spi_master_clk_divider1[4] ),
+ .ZN(_05292_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_2 _16938_ (.I(\soc.core.mgmtsoc_litespisdrphycore_cnt[1] ),
+ .ZN(_05293_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_2 _16939_ (.I(\soc.core.mgmtsoc_litespisdrphycore_cnt[3] ),
+ .ZN(_05294_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_4 _16940_ (.I(\soc.core.mgmtsoc_litespisdrphycore_cnt[2] ),
+ .ZN(_05295_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _16941_ (.I(\soc.core.mgmtsoc_litespisdrphycore_cnt[7] ),
+ .ZN(_05296_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_3 _16942_ (.I(\soc.core.mgmtsoc_litespisdrphycore_cnt[6] ),
+ .ZN(_05297_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_2 _16943_ (.I(\soc.core.mgmtsoc_litespisdrphycore_cnt[5] ),
+ .ZN(_05298_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_2 _16944_ (.I(\soc.core.mgmtsoc_litespisdrphycore_cnt[4] ),
+ .ZN(_05299_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _16945_ (.I(\soc.core.mgmtsoc_litespisdrphycore_sr_cnt[5] ),
+ .ZN(_05300_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _16946_ (.I(\soc.core.mgmtsoc_litespisdrphycore_sr_cnt[7] ),
+ .ZN(_05301_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_1 _16947_ (.I(\soc.core.mgmtsoc_litespisdrphycore_sr_cnt[6] ),
+ .ZN(_05302_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _16948_ (.I(\soc.core.gpioin5_gpioin5_trigger_d ),
+ .ZN(_05303_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _16949_ (.I(\soc.core.gpioin4_gpioin4_trigger_d ),
+ .ZN(_05304_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _16950_ (.I(\soc.core.gpioin3_gpioin3_trigger_d ),
+ .ZN(_05305_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _16951_ (.I(\soc.core.gpioin2_gpioin2_trigger_d ),
+ .ZN(_05306_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _16952_ (.I(\soc.core.gpioin1_gpioin1_trigger_d ),
+ .ZN(_05307_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _16953_ (.I(\soc.core.gpioin0_gpioin0_trigger_d ),
+ .ZN(_05308_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _16954_ (.I(\soc.core.uart_rx_trigger_d ),
+ .ZN(_05309_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _16955_ (.I(\soc.core.uart_tx_trigger_d ),
+ .ZN(_05310_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_2 _16956_ (.I(\soc.core.mgmtsoc_litespimmap_burst_adr[0] ),
+ .ZN(_05311_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_1 _16957_ (.I(\soc.core.mgmtsoc_litespimmap_burst_adr[23] ),
+ .ZN(_05312_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_4 _16958_ (.I(\soc.core.mgmtsoc_vexriscv_transfer_in_progress ),
+ .ZN(_05313_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_4 _16959_ (.I(\clock_ctrl.divider2.odd_0.rst_pulse ),
+ .ZN(_05314_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _16960_ (.I(\clock_ctrl.divider2.odd_0.counter[1] ),
+ .ZN(_05315_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_2 _16961_ (.I(\clock_ctrl.divider2.odd_0.counter[2] ),
+ .ZN(_05316_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _16962_ (.I(\clock_ctrl.divider2.even_0.counter[0] ),
+ .ZN(_05317_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_3 _16963_ (.I(\clock_ctrl.divider.odd_0.rst_pulse ),
+ .ZN(_05318_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _16964_ (.I(\clock_ctrl.divider.odd_0.counter2[1] ),
+ .ZN(_05319_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _16965_ (.I(\clock_ctrl.divider.even_0.counter[0] ),
+ .ZN(_05320_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_2 _16966_ (.I(\soc.core.VexRiscv.IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[2] ),
+ .ZN(_05321_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _16967_ (.I(\soc.core.VexRiscv.IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[6] ),
+ .ZN(_05322_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_2 _16968_ (.I(\soc.core.VexRiscv.IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[9] ),
+ .ZN(_05323_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _16969_ (.I(\soc.core.VexRiscv.IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[10] ),
+ .ZN(_05324_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _16970_ (.I(\soc.core.VexRiscv.IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[13] ),
+ .ZN(_05325_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_1 _16971_ (.I(\soc.core.VexRiscv.IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[16] ),
+ .ZN(_05326_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_2 _16972_ (.I(\soc.core.VexRiscv.IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[22] ),
+ .ZN(_05327_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_3 _16973_ (.I(\soc.core.VexRiscv.IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[23] ),
+ .ZN(_05328_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_1 _16974_ (.I(\soc.core.VexRiscv.IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[27] ),
+ .ZN(_05329_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _16975_ (.I(\soc.core.VexRiscv.IBusCachedPlugin_cache._zz_banks_0_port1[15] ),
+ .ZN(_05330_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _16976_ (.I(\soc.core.VexRiscv.IBusCachedPlugin_cache._zz_banks_0_port1[16] ),
+ .ZN(_05331_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _16977_ (.I(\soc.core.VexRiscv.IBusCachedPlugin_cache._zz_banks_0_port1[18] ),
+ .ZN(_05332_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _16978_ (.I(\soc.core.VexRiscv.IBusCachedPlugin_cache._zz_banks_0_port1[20] ),
+ .ZN(_05333_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _16979_ (.I(\soc.core.VexRiscv.IBusCachedPlugin_cache._zz_banks_0_port1[21] ),
+ .ZN(_05334_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _16980_ (.I(\soc.core.VexRiscv.IBusCachedPlugin_cache._zz_banks_0_port1[23] ),
+ .ZN(_05335_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_2 _16981_ (.I(\soc.core.VexRiscv.BranchPlugin_branchExceptionPort_payload_badAddr[4] ),
+ .ZN(_05336_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_1 _16982_ (.I(\soc.core.VexRiscv.BranchPlugin_branchExceptionPort_payload_badAddr[5] ),
+ .ZN(_05337_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _16983_ (.I(\soc.core.dbg_uart_rx_phase[29] ),
+ .ZN(_05338_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _16984_ (.I(\soc.core.dbg_uart_rx_phase[27] ),
+ .ZN(_05339_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _16985_ (.I(\soc.core.dbg_uart_rx_phase[25] ),
+ .ZN(_05340_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _16986_ (.I(\soc.core.dbg_uart_rx_phase[24] ),
+ .ZN(_05341_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _16987_ (.I(\soc.core.dbg_uart_rx_phase[22] ),
+ .ZN(_05342_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _16988_ (.I(\soc.core.dbg_uart_rx_phase[17] ),
+ .ZN(_05343_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_2 _16989_ (.I(\soc.core.dbg_uart_rx_phase[19] ),
+ .ZN(_05344_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _16990_ (.I(\soc.core.dbg_uart_rx_phase[16] ),
+ .ZN(_05345_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _16991_ (.I(\soc.core.dbg_uart_rx_phase[14] ),
+ .ZN(_05346_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _16992_ (.I(\soc.core.dbg_uart_rx_phase[12] ),
+ .ZN(_05347_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_2 _16993_ (.I(\soc.core.dbg_uart_rx_phase[11] ),
+ .ZN(_05348_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_2 _16994_ (.I(\soc.core.dbg_uart_rx_phase[10] ),
+ .ZN(_05349_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _16995_ (.I(\soc.core.dbg_uart_rx_phase[7] ),
+ .ZN(_05350_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _16996_ (.I(\soc.core.dbg_uart_rx_phase[6] ),
+ .ZN(_05351_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_1 _16997_ (.I(\soc.core.dbg_uart_rx_phase[4] ),
+ .ZN(_05352_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _16998_ (.I(\soc.core.dbg_uart_rx_phase[3] ),
+ .ZN(_05353_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _16999_ (.I(\soc.core.dbg_uart_tx_phase[4] ),
+ .ZN(_05354_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _17000_ (.I(\soc.core.dbg_uart_tx_phase[3] ),
+ .ZN(_05355_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_2 _17001_ (.I(\soc.core.dbg_uart_tx_phase[6] ),
+ .ZN(_05356_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_2 _17002_ (.I(\soc.core.dbg_uart_tx_phase[10] ),
+ .ZN(_05357_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _17003_ (.I(\soc.core.dbg_uart_tx_phase[11] ),
+ .ZN(_05358_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _17004_ (.I(\soc.core.dbg_uart_tx_phase[17] ),
+ .ZN(_05359_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _17005_ (.I(\soc.core.dbg_uart_tx_phase[20] ),
+ .ZN(_05360_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _17006_ (.I(\soc.core.dbg_uart_tx_phase[19] ),
+ .ZN(_05361_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _17007_ (.I(\soc.core.dbg_uart_tx_phase[22] ),
+ .ZN(_05362_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _17008_ (.I(\soc.core.dbg_uart_tx_phase[25] ),
+ .ZN(_05363_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _17009_ (.I(\soc.core.mgmtsoc_litespisdrphycore_sr_out[0] ),
+ .ZN(_05364_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _17010_ (.I(\soc.core.VexRiscv.dBusWishbone_DAT_MOSI[0] ),
+ .ZN(_05365_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _17011_ (.I(\soc.core.VexRiscv.dBusWishbone_DAT_MOSI[1] ),
+ .ZN(_05366_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _17012_ (.I(\soc.core.VexRiscv.dBusWishbone_DAT_MOSI[2] ),
+ .ZN(_05367_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _17013_ (.I(\soc.core.VexRiscv.dBusWishbone_DAT_MOSI[3] ),
+ .ZN(_05368_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _17014_ (.I(\soc.core.VexRiscv.dBusWishbone_DAT_MOSI[4] ),
+ .ZN(_05369_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _17015_ (.I(\soc.core.VexRiscv.dBusWishbone_DAT_MOSI[5] ),
+ .ZN(_05370_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _17016_ (.I(\soc.core.VexRiscv.dBusWishbone_DAT_MOSI[6] ),
+ .ZN(_05371_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _17017_ (.I(\soc.core.VexRiscv.dBusWishbone_DAT_MOSI[7] ),
+ .ZN(_05372_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_3 _17018_ (.I(\mgmt_buffers.mprj_dat_i_core_bar[0] ),
+ .ZN(_05373_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_3 _17019_ (.I(\mgmt_buffers.mprj_dat_i_core_bar[1] ),
+ .ZN(_05374_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_1 _17020_ (.I(\mgmt_buffers.mprj_dat_i_core_bar[2] ),
+ .ZN(_05375_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_1 _17021_ (.I(\mgmt_buffers.mprj_dat_i_core_bar[3] ),
+ .ZN(_05376_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _17022_ (.I(\soc.core.interface11_bank_bus_dat_r[3] ),
+ .ZN(_05377_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_3 _17023_ (.I(\mgmt_buffers.mprj_dat_i_core_bar[4] ),
+ .ZN(_05378_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_1 _17024_ (.I(\soc.core.interface11_bank_bus_dat_r[4] ),
+ .ZN(_05379_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_1 _17025_ (.I(\mgmt_buffers.mprj_dat_i_core_bar[5] ),
+ .ZN(_05380_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _17026_ (.I(\soc.core.interface11_bank_bus_dat_r[5] ),
+ .ZN(_05381_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_3 _17027_ (.I(\mgmt_buffers.mprj_dat_i_core_bar[6] ),
+ .ZN(_05382_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _17028_ (.I(\soc.core.interface11_bank_bus_dat_r[6] ),
+ .ZN(_05383_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_1 _17029_ (.I(\mgmt_buffers.mprj_dat_i_core_bar[7] ),
+ .ZN(_05384_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_1 _17030_ (.I(\soc.core.interface11_bank_bus_dat_r[7] ),
+ .ZN(_05385_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_1 _17031_ (.I(\mgmt_buffers.mprj_dat_i_core_bar[8] ),
+ .ZN(_05386_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_1 _17032_ (.I(\mgmt_buffers.mprj_dat_i_core_bar[9] ),
+ .ZN(_05387_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_1 _17033_ (.I(\mgmt_buffers.mprj_dat_i_core_bar[10] ),
+ .ZN(_05388_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_3 _17034_ (.I(\mgmt_buffers.mprj_dat_i_core_bar[11] ),
+ .ZN(_05389_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_3 _17035_ (.I(\mgmt_buffers.mprj_dat_i_core_bar[12] ),
+ .ZN(_05390_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_1 _17036_ (.I(\mgmt_buffers.mprj_dat_i_core_bar[13] ),
+ .ZN(_05391_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_1 _17037_ (.I(\mgmt_buffers.mprj_dat_i_core_bar[14] ),
+ .ZN(_05392_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_4 _17038_ (.I(\mgmt_buffers.mprj_dat_i_core_bar[15] ),
+ .ZN(_05393_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_1 _17039_ (.I(\mgmt_buffers.mprj_dat_i_core_bar[16] ),
+ .ZN(_05394_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_1 _17040_ (.I(\mgmt_buffers.mprj_dat_i_core_bar[17] ),
+ .ZN(_05395_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_1 _17041_ (.I(\mgmt_buffers.mprj_dat_i_core_bar[18] ),
+ .ZN(_05396_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_1 _17042_ (.I(\mgmt_buffers.mprj_dat_i_core_bar[19] ),
+ .ZN(_05397_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_3 _17043_ (.I(\mgmt_buffers.mprj_dat_i_core_bar[20] ),
+ .ZN(_05398_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_3 _17044_ (.I(\mgmt_buffers.mprj_dat_i_core_bar[21] ),
+ .ZN(_05399_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_3 _17045_ (.I(\mgmt_buffers.mprj_dat_i_core_bar[22] ),
+ .ZN(_05400_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_4 _17046_ (.I(\mgmt_buffers.mprj_dat_i_core_bar[23] ),
+ .ZN(_05401_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_3 _17047_ (.I(\mgmt_buffers.mprj_dat_i_core_bar[24] ),
+ .ZN(_05402_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_1 _17048_ (.I(\mgmt_buffers.mprj_dat_i_core_bar[25] ),
+ .ZN(_05403_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_1 _17049_ (.I(\mgmt_buffers.mprj_dat_i_core_bar[26] ),
+ .ZN(_05404_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_1 _17050_ (.I(\mgmt_buffers.mprj_dat_i_core_bar[27] ),
+ .ZN(_05405_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_4 _17051_ (.I(\mgmt_buffers.mprj_dat_i_core_bar[28] ),
+ .ZN(_05406_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_3 _17052_ (.I(\mgmt_buffers.mprj_dat_i_core_bar[29] ),
+ .ZN(_05407_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_4 _17053_ (.I(\mgmt_buffers.mprj_dat_i_core_bar[30] ),
+ .ZN(_05408_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_2 _17054_ (.I(\mgmt_buffers.mprj_dat_i_core_bar[31] ),
+ .ZN(_05409_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_1 _17055_ (.I(\soc.core.dbg_uart_rx_data[0] ),
+ .ZN(_05410_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_2 _17056_ (.I(\soc.core.VexRiscv._zz_execute_ALU_CTRL[0] ),
+ .ZN(_05411_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_3 _17057_ (.I(\soc.core.VexRiscv._zz_execute_ALU_CTRL[1] ),
+ .ZN(_05412_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_16 _17058_ (.I(net1772),
+ .ZN(_05413_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_8 _17059_ (.I(\soc.core.VexRiscv.CsrPlugin_selfException_payload_badAddr[30] ),
+ .ZN(_05414_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _17060_ (.I(\soc.core.VexRiscv.decode_to_execute_RS1[30] ),
+ .ZN(_05415_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_3 _17061_ (.I(\soc.core.VexRiscv.CsrPlugin_selfException_payload_badAddr[29] ),
+ .ZN(_05416_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_1 _17062_ (.I(\soc.core.VexRiscv.decode_to_execute_RS1[29] ),
+ .ZN(_05417_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_3 _17063_ (.I(\soc.core.VexRiscv.CsrPlugin_selfException_payload_badAddr[27] ),
+ .ZN(_05418_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_3 _17064_ (.I(\soc.core.VexRiscv.CsrPlugin_selfException_payload_badAddr[26] ),
+ .ZN(_05419_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_1 _17065_ (.I(\soc.core.VexRiscv.decode_to_execute_RS1[23] ),
+ .ZN(_05420_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _17066_ (.I(\soc.core.VexRiscv._zz_execute_SRC2[18] ),
+ .ZN(_05421_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _17067_ (.I(\soc.core.VexRiscv.decode_to_execute_RS2[18] ),
+ .ZN(_05422_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_2 _17068_ (.I(\soc.core.VexRiscv.CsrPlugin_selfException_payload_badAddr[17] ),
+ .ZN(_05423_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _17069_ (.I(net1811),
+ .ZN(_05424_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _17070_ (.I(\soc.core.VexRiscv.decode_to_execute_RS2[16] ),
+ .ZN(_05425_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_3 _17071_ (.I(\soc.core.VexRiscv._zz_execute_SRC2[15] ),
+ .ZN(_05426_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _17072_ (.I(\soc.core.VexRiscv.decode_to_execute_RS2[15] ),
+ .ZN(_05427_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_2 _17073_ (.I(\soc.core.VexRiscv.CsrPlugin_selfException_payload_badAddr[14] ),
+ .ZN(_05428_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_1 _17074_ (.I(\soc.core.VexRiscv.decode_to_execute_RS1[14] ),
+ .ZN(_05429_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_1 _17075_ (.I(\soc.core.VexRiscv._zz_execute_SRC2[14] ),
+ .ZN(_05430_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_2 _17076_ (.I(\soc.core.VexRiscv._zz_execute_SRC2[13] ),
+ .ZN(_05431_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _17077_ (.I(\soc.core.VexRiscv.decode_to_execute_RS2[13] ),
+ .ZN(_05432_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_2 _17078_ (.I(\soc.core.VexRiscv._zz_execute_SRC2[12] ),
+ .ZN(_05433_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _17079_ (.I(\soc.core.VexRiscv.decode_to_execute_RS2[12] ),
+ .ZN(_05434_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_1 _17080_ (.I(\soc.core.VexRiscv.decode_to_execute_RS1[11] ),
+ .ZN(_05435_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_3 _17081_ (.I(\soc.core.VexRiscv._zz_execute_SRC2[11] ),
+ .ZN(_05436_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _17082_ (.I(\soc.core.VexRiscv.decode_to_execute_RS2[11] ),
+ .ZN(_05437_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_3 _17083_ (.I(\soc.core.VexRiscv._zz_execute_SRC2[10] ),
+ .ZN(_05438_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _17084_ (.I(\soc.core.VexRiscv.decode_to_execute_RS2[10] ),
+ .ZN(_05439_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_1 _17085_ (.I(\soc.core.VexRiscv._zz_execute_SRC2[9] ),
+ .ZN(_05440_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_1 _17086_ (.I(\soc.core.VexRiscv.decode_to_execute_RS2[9] ),
+ .ZN(_05441_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_1 _17087_ (.I(\soc.core.VexRiscv._zz_execute_SRC2[8] ),
+ .ZN(_05442_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _17088_ (.I(\soc.core.VexRiscv._zz_execute_SRC2[7] ),
+ .ZN(_05443_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _17089_ (.I(net1753),
+ .ZN(_05444_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_3 _17090_ (.I(net2856),
+ .ZN(_05445_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _17091_ (.I(net1754),
+ .ZN(_05446_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_1 _17092_ (.I(\soc.core.VexRiscv._zz_execute_SRC2[5] ),
+ .ZN(_05447_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _17093_ (.I(net1755),
+ .ZN(_05448_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_1 _17094_ (.I(\soc.core.VexRiscv.decode_to_execute_RS1[3] ),
+ .ZN(_05449_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_2 _17095_ (.I(\soc.core.VexRiscv._zz_execute_ALU_BITWISE_CTRL[0] ),
+ .ZN(_05450_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_1 _17096_ (.I(\soc.core.VexRiscv.DBusSimplePlugin_memoryExceptionPort_payload_badAddr[1] ),
+ .ZN(_05451_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_1 _17097_ (.I(\soc.core.VexRiscv.execute_CsrPlugin_csr_834 ),
+ .ZN(_05452_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _17098_ (.I(\soc.core.VexRiscv.CsrPlugin_mcause_exceptionCode[0] ),
+ .ZN(_05453_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _17099_ (.I(net1800),
+ .ZN(_05454_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_2 _17100_ (.I(\soc.core.VexRiscv.execute_CsrPlugin_csr_4032 ),
+ .ZN(_05455_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_3 _17101_ (.I(\soc.core.VexRiscv.DBusSimplePlugin_memoryExceptionPort_payload_badAddr[0] ),
+ .ZN(_05456_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_1 _17102_ (.I(\soc.core.VexRiscv.execute_CsrPlugin_csr_768 ),
+ .ZN(_05457_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_1 _17103_ (.I(\soc.core.VexRiscv.CsrPlugin_mstatus_MPIE ),
+ .ZN(_05458_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_2 _17104_ (.I(\soc.core.VexRiscv.DBusSimplePlugin_memoryExceptionPort_payload_badAddr[31] ),
+ .ZN(_05459_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_4 _17105_ (.I(\soc.core.VexRiscv.memory_to_writeBack_MEMORY_ADDRESS_LOW[0] ),
+ .ZN(_05460_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_3 _17106_ (.I(\soc.core.VexRiscv.memory_to_writeBack_MEMORY_ADDRESS_LOW[1] ),
+ .ZN(_05461_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_2 _17107_ (.I(\soc.core.VexRiscv.IBusCachedPlugin_cache.io_mem_rsp_payload_data[16] ),
+ .ZN(_05462_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_1 _17108_ (.I(net1782),
+ .ZN(_05463_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _17109_ (.I(\soc.core.VexRiscv.IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[30] ),
+ .ZN(_05464_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_8 _17110_ (.I(\soc.core.VexRiscv._zz_2 ),
+ .ZN(_05465_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _17111_ (.I(\soc.core.VexRiscv.IBusCachedPlugin_cache.io_mem_rsp_payload_data[26] ),
+ .ZN(_05466_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_1 _17112_ (.I(net1781),
+ .ZN(_05467_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _17113_ (.I(\soc.core.VexRiscv.IBusCachedPlugin_cache.io_mem_rsp_payload_data[10] ),
+ .ZN(_05468_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _17114_ (.I(\soc.core.VexRiscv.IBusCachedPlugin_cache.io_mem_rsp_payload_data[27] ),
+ .ZN(_05469_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _17115_ (.I(\soc.core.VexRiscv.IBusCachedPlugin_cache.io_mem_rsp_payload_data[11] ),
+ .ZN(_05470_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_2 _17116_ (.I(\soc.core.VexRiscv.IBusCachedPlugin_cache.io_mem_rsp_payload_data[20] ),
+ .ZN(_05471_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _17117_ (.I(\soc.core.VexRiscv.IBusCachedPlugin_cache.io_mem_rsp_payload_data[12] ),
+ .ZN(_05472_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _17118_ (.I(\soc.core.VexRiscv.IBusCachedPlugin_cache.io_mem_rsp_payload_data[21] ),
+ .ZN(_05473_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _17119_ (.I(\soc.core.VexRiscv.IBusCachedPlugin_cache.io_mem_rsp_payload_data[30] ),
+ .ZN(_05474_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_1 _17120_ (.I(\soc.core.VexRiscv.IBusCachedPlugin_cache.io_mem_rsp_payload_data[22] ),
+ .ZN(_05475_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _17121_ (.I(\soc.core.VexRiscv.memory_to_writeBack_REGFILE_WRITE_DATA[7] ),
+ .ZN(_05476_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_1 _17122_ (.I(net1778),
+ .ZN(_05477_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _17123_ (.I(\soc.core.VexRiscv.IBusCachedPlugin_cache.io_mem_rsp_payload_data[15] ),
+ .ZN(_05478_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _17124_ (.I(\clock_ctrl.ext_clk_syncd ),
+ .ZN(_05479_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _17125_ (.I(\clock_ctrl.use_pll_second ),
+ .ZN(_05480_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_8 _17126_ (.I(net2194),
+ .ZN(_05481_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_1 _17127_ (.I(\pll.ext_trim[6] ),
+ .ZN(_05482_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_1 _17128_ (.I(\pll.ext_trim[14] ),
+ .ZN(_05483_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_1 _17129_ (.I(\pll.ext_trim[15] ),
+ .ZN(_05484_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_1 _17130_ (.I(\pll.ext_trim[16] ),
+ .ZN(_05485_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_1 _17131_ (.I(\pll.ext_trim[17] ),
+ .ZN(_05486_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_1 _17132_ (.I(\pll.ext_trim[18] ),
+ .ZN(_05487_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_1 _17133_ (.I(\pll.ext_trim[20] ),
+ .ZN(_05488_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_1 _17134_ (.I(\pll.ext_trim[25] ),
+ .ZN(_05489_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_2 _17135_ (.I(\soc.core.VexRiscv._zz_execute_BRANCH_CTRL[1] ),
+ .ZN(_05490_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _17136_ (.I(\soc.core.VexRiscv._zz_execute_BRANCH_CTRL[0] ),
+ .ZN(_05491_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _17137_ (.I(\soc.core.dbg_uart_length[2] ),
+ .ZN(_05492_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _17138_ (.I(\soc.core.dbg_uart_length[5] ),
+ .ZN(_05493_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _17139_ (.I(\soc.core.spi_cs_n ),
+ .ZN(\soc.core.spi_sdoenb ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _17140_ (.I(\mgmt_buffers.user_irq_bar[0] ),
+ .ZN(\mgmt_buffers.user_irq[0] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _17141_ (.I(\mgmt_buffers.user_irq_bar[1] ),
+ .ZN(\mgmt_buffers.user_irq[1] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _17142_ (.I(\mgmt_buffers.user_irq_bar[2] ),
+ .ZN(\mgmt_buffers.user_irq[2] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _17143_ (.I(\mgmt_buffers.la_data_in_mprj_bar[0] ),
+ .ZN(\mgmt_buffers.la_data_in_mprj[0] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _17144_ (.I(\mgmt_buffers.la_data_in_mprj_bar[1] ),
+ .ZN(\mgmt_buffers.la_data_in_mprj[1] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _17145_ (.I(\mgmt_buffers.la_data_in_mprj_bar[2] ),
+ .ZN(\mgmt_buffers.la_data_in_mprj[2] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _17146_ (.I(\mgmt_buffers.la_data_in_mprj_bar[3] ),
+ .ZN(\mgmt_buffers.la_data_in_mprj[3] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _17147_ (.I(\mgmt_buffers.la_data_in_mprj_bar[4] ),
+ .ZN(\mgmt_buffers.la_data_in_mprj[4] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _17148_ (.I(\mgmt_buffers.la_data_in_mprj_bar[5] ),
+ .ZN(\mgmt_buffers.la_data_in_mprj[5] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _17149_ (.I(\mgmt_buffers.la_data_in_mprj_bar[6] ),
+ .ZN(\mgmt_buffers.la_data_in_mprj[6] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _17150_ (.I(\mgmt_buffers.la_data_in_mprj_bar[7] ),
+ .ZN(\mgmt_buffers.la_data_in_mprj[7] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _17151_ (.I(\mgmt_buffers.la_data_in_mprj_bar[8] ),
+ .ZN(\mgmt_buffers.la_data_in_mprj[8] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _17152_ (.I(\mgmt_buffers.la_data_in_mprj_bar[9] ),
+ .ZN(\mgmt_buffers.la_data_in_mprj[9] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _17153_ (.I(\mgmt_buffers.la_data_in_mprj_bar[10] ),
+ .ZN(\mgmt_buffers.la_data_in_mprj[10] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _17154_ (.I(\mgmt_buffers.la_data_in_mprj_bar[11] ),
+ .ZN(\mgmt_buffers.la_data_in_mprj[11] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _17155_ (.I(\mgmt_buffers.la_data_in_mprj_bar[12] ),
+ .ZN(\mgmt_buffers.la_data_in_mprj[12] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _17156_ (.I(\mgmt_buffers.la_data_in_mprj_bar[13] ),
+ .ZN(\mgmt_buffers.la_data_in_mprj[13] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _17157_ (.I(\mgmt_buffers.la_data_in_mprj_bar[14] ),
+ .ZN(\mgmt_buffers.la_data_in_mprj[14] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _17158_ (.I(\mgmt_buffers.la_data_in_mprj_bar[15] ),
+ .ZN(\mgmt_buffers.la_data_in_mprj[15] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _17159_ (.I(\mgmt_buffers.la_data_in_mprj_bar[16] ),
+ .ZN(\mgmt_buffers.la_data_in_mprj[16] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _17160_ (.I(\mgmt_buffers.la_data_in_mprj_bar[17] ),
+ .ZN(\mgmt_buffers.la_data_in_mprj[17] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _17161_ (.I(\mgmt_buffers.la_data_in_mprj_bar[18] ),
+ .ZN(\mgmt_buffers.la_data_in_mprj[18] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _17162_ (.I(\mgmt_buffers.la_data_in_mprj_bar[19] ),
+ .ZN(\mgmt_buffers.la_data_in_mprj[19] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _17163_ (.I(\mgmt_buffers.la_data_in_mprj_bar[20] ),
+ .ZN(\mgmt_buffers.la_data_in_mprj[20] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _17164_ (.I(\mgmt_buffers.la_data_in_mprj_bar[21] ),
+ .ZN(\mgmt_buffers.la_data_in_mprj[21] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _17165_ (.I(\mgmt_buffers.la_data_in_mprj_bar[22] ),
+ .ZN(\mgmt_buffers.la_data_in_mprj[22] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _17166_ (.I(\mgmt_buffers.la_data_in_mprj_bar[23] ),
+ .ZN(\mgmt_buffers.la_data_in_mprj[23] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _17167_ (.I(\mgmt_buffers.la_data_in_mprj_bar[24] ),
+ .ZN(\mgmt_buffers.la_data_in_mprj[24] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _17168_ (.I(\mgmt_buffers.la_data_in_mprj_bar[25] ),
+ .ZN(\mgmt_buffers.la_data_in_mprj[25] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _17169_ (.I(\mgmt_buffers.la_data_in_mprj_bar[26] ),
+ .ZN(\mgmt_buffers.la_data_in_mprj[26] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _17170_ (.I(\mgmt_buffers.la_data_in_mprj_bar[27] ),
+ .ZN(\mgmt_buffers.la_data_in_mprj[27] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _17171_ (.I(\mgmt_buffers.la_data_in_mprj_bar[28] ),
+ .ZN(\mgmt_buffers.la_data_in_mprj[28] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _17172_ (.I(\mgmt_buffers.la_data_in_mprj_bar[29] ),
+ .ZN(\mgmt_buffers.la_data_in_mprj[29] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _17173_ (.I(\mgmt_buffers.la_data_in_mprj_bar[30] ),
+ .ZN(\mgmt_buffers.la_data_in_mprj[30] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _17174_ (.I(\mgmt_buffers.la_data_in_mprj_bar[31] ),
+ .ZN(\mgmt_buffers.la_data_in_mprj[31] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _17175_ (.I(\mgmt_buffers.la_data_in_mprj_bar[32] ),
+ .ZN(\mgmt_buffers.la_data_in_mprj[32] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _17176_ (.I(\mgmt_buffers.la_data_in_mprj_bar[33] ),
+ .ZN(\mgmt_buffers.la_data_in_mprj[33] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _17177_ (.I(\mgmt_buffers.la_data_in_mprj_bar[34] ),
+ .ZN(\mgmt_buffers.la_data_in_mprj[34] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _17178_ (.I(\mgmt_buffers.la_data_in_mprj_bar[35] ),
+ .ZN(\mgmt_buffers.la_data_in_mprj[35] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _17179_ (.I(\mgmt_buffers.la_data_in_mprj_bar[36] ),
+ .ZN(\mgmt_buffers.la_data_in_mprj[36] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _17180_ (.I(\mgmt_buffers.la_data_in_mprj_bar[37] ),
+ .ZN(\mgmt_buffers.la_data_in_mprj[37] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _17181_ (.I(\mgmt_buffers.la_data_in_mprj_bar[38] ),
+ .ZN(\mgmt_buffers.la_data_in_mprj[38] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _17182_ (.I(\mgmt_buffers.la_data_in_mprj_bar[39] ),
+ .ZN(\mgmt_buffers.la_data_in_mprj[39] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _17183_ (.I(\mgmt_buffers.la_data_in_mprj_bar[40] ),
+ .ZN(\mgmt_buffers.la_data_in_mprj[40] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _17184_ (.I(\mgmt_buffers.la_data_in_mprj_bar[41] ),
+ .ZN(\mgmt_buffers.la_data_in_mprj[41] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _17185_ (.I(\mgmt_buffers.la_data_in_mprj_bar[42] ),
+ .ZN(\mgmt_buffers.la_data_in_mprj[42] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _17186_ (.I(\mgmt_buffers.la_data_in_mprj_bar[43] ),
+ .ZN(\mgmt_buffers.la_data_in_mprj[43] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _17187_ (.I(\mgmt_buffers.la_data_in_mprj_bar[44] ),
+ .ZN(\mgmt_buffers.la_data_in_mprj[44] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _17188_ (.I(\mgmt_buffers.la_data_in_mprj_bar[45] ),
+ .ZN(\mgmt_buffers.la_data_in_mprj[45] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _17189_ (.I(\mgmt_buffers.la_data_in_mprj_bar[46] ),
+ .ZN(\mgmt_buffers.la_data_in_mprj[46] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _17190_ (.I(\mgmt_buffers.la_data_in_mprj_bar[47] ),
+ .ZN(\mgmt_buffers.la_data_in_mprj[47] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _17191_ (.I(\mgmt_buffers.la_data_in_mprj_bar[48] ),
+ .ZN(\mgmt_buffers.la_data_in_mprj[48] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _17192_ (.I(\mgmt_buffers.la_data_in_mprj_bar[49] ),
+ .ZN(\mgmt_buffers.la_data_in_mprj[49] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _17193_ (.I(\mgmt_buffers.la_data_in_mprj_bar[50] ),
+ .ZN(\mgmt_buffers.la_data_in_mprj[50] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _17194_ (.I(\mgmt_buffers.la_data_in_mprj_bar[51] ),
+ .ZN(\mgmt_buffers.la_data_in_mprj[51] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _17195_ (.I(\mgmt_buffers.la_data_in_mprj_bar[52] ),
+ .ZN(\mgmt_buffers.la_data_in_mprj[52] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _17196_ (.I(\mgmt_buffers.la_data_in_mprj_bar[53] ),
+ .ZN(\mgmt_buffers.la_data_in_mprj[53] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _17197_ (.I(\mgmt_buffers.la_data_in_mprj_bar[54] ),
+ .ZN(\mgmt_buffers.la_data_in_mprj[54] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _17198_ (.I(\mgmt_buffers.la_data_in_mprj_bar[55] ),
+ .ZN(\mgmt_buffers.la_data_in_mprj[55] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _17199_ (.I(\mgmt_buffers.la_data_in_mprj_bar[56] ),
+ .ZN(\mgmt_buffers.la_data_in_mprj[56] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _17200_ (.I(\mgmt_buffers.la_data_in_mprj_bar[57] ),
+ .ZN(\mgmt_buffers.la_data_in_mprj[57] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _17201_ (.I(\mgmt_buffers.la_data_in_mprj_bar[58] ),
+ .ZN(\mgmt_buffers.la_data_in_mprj[58] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _17202_ (.I(\mgmt_buffers.la_data_in_mprj_bar[59] ),
+ .ZN(\mgmt_buffers.la_data_in_mprj[59] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _17203_ (.I(\mgmt_buffers.la_data_in_mprj_bar[60] ),
+ .ZN(\mgmt_buffers.la_data_in_mprj[60] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _17204_ (.I(\mgmt_buffers.la_data_in_mprj_bar[61] ),
+ .ZN(\mgmt_buffers.la_data_in_mprj[61] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _17205_ (.I(\mgmt_buffers.la_data_in_mprj_bar[62] ),
+ .ZN(\mgmt_buffers.la_data_in_mprj[62] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _17206_ (.I(\mgmt_buffers.la_data_in_mprj_bar[63] ),
+ .ZN(\mgmt_buffers.la_data_in_mprj[63] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_2 _17207_ (.I(\clock_ctrl.reset_delay[0] ),
+ .ZN(\clock_ctrl.resetb_sync ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _17208_ (.I(\clock_ctrl.ext_clk_sel ),
+ .ZN(\clock_ctrl.pll_clk_sel ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_2 _17209_ (.I(\soc.core.dbg_uart_tx_phase[27] ),
+ .ZN(_05494_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _17210_ (.I(\soc.core.uart_phy_rx_phase[7] ),
+ .ZN(_05495_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_1 _17211_ (.I(\soc.core.uart_phy_rx_phase[8] ),
+ .ZN(_05496_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _17212_ (.I(\soc.core.uart_phy_rx_phase[9] ),
+ .ZN(_05497_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _17213_ (.I(\soc.core.uart_phy_rx_phase[12] ),
+ .ZN(_05498_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _17214_ (.I(\soc.core.uart_phy_rx_phase[13] ),
+ .ZN(_05499_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _17215_ (.I(\soc.core.uart_phy_rx_phase[15] ),
+ .ZN(_05500_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _17216_ (.I(\soc.core.uart_phy_rx_phase[17] ),
+ .ZN(_05501_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _17217_ (.I(\soc.core.uart_phy_rx_phase[20] ),
+ .ZN(_05502_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_2 _17218_ (.I(\soc.core.uart_phy_rx_phase[22] ),
+ .ZN(_05503_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _17219_ (.I(\soc.core.uart_phy_rx_phase[27] ),
+ .ZN(_05504_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _17220_ (.I(\soc.core.uart_phy_rx_phase[29] ),
+ .ZN(_05505_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_1 _17221_ (.I(\soc.core.uart_phy_tx_phase[7] ),
+ .ZN(_05506_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _17222_ (.I(\soc.core.uart_phy_tx_phase[9] ),
+ .ZN(_05507_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_2 _17223_ (.I(\soc.core.uart_phy_tx_phase[10] ),
+ .ZN(_05508_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _17224_ (.I(\soc.core.uart_phy_tx_phase[11] ),
+ .ZN(_05509_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _17225_ (.I(\soc.core.uart_phy_tx_phase[13] ),
+ .ZN(_05510_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _17226_ (.I(\soc.core.uart_phy_tx_phase[17] ),
+ .ZN(_05511_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_2 _17227_ (.I(\soc.core.uart_phy_tx_phase[22] ),
+ .ZN(_05512_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _17228_ (.I(\soc.core.uart_phy_tx_phase[28] ),
+ .ZN(_05513_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _17229_ (.I(\soc.core.uart_phy_tx_phase[30] ),
+ .ZN(_05514_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_1 _17230_ (.I(\soc.core.uart_phy_tx_phase[31] ),
+ .ZN(_05515_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _17231_ (.I(\soc.core.serial_rx ),
+ .ZN(_05516_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_16 _17232_ (.I(net1717),
+ .ZN(_05517_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_4 _17233_ (.I(net1602),
+ .ZN(_05518_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_4 _17234_ (.I(net1536),
+ .ZN(_05519_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_4 _17235_ (.I(net1377),
+ .ZN(_05520_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_4 _17236_ (.I(net1173),
+ .ZN(_05521_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_4 _17237_ (.I(net990),
+ .ZN(_05522_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_4 _17238_ (.I(net943),
+ .ZN(_05523_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_4 _17239_ (.I(net888),
+ .ZN(_05524_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_4 _17240_ (.I(net855),
+ .ZN(_05525_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_4 _17241_ (.I(net823),
+ .ZN(_05526_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_4 _17242_ (.I(net784),
+ .ZN(_05527_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_4 _17243_ (.I(net748),
+ .ZN(_05528_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_4 _17244_ (.I(net457),
+ .ZN(_05529_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_4 _17245_ (.I(net446),
+ .ZN(_05530_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_4 _17246_ (.I(net417),
+ .ZN(_05531_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_4 _17247_ (.I(net407),
+ .ZN(_05532_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_4 _17248_ (.I(net404),
+ .ZN(_05533_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_4 _17249_ (.I(net402),
+ .ZN(_05534_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_4 _17250_ (.I(\gpio_control_in_1[10].resetn ),
+ .ZN(_05535_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_4 _17251_ (.I(net1535),
+ .ZN(_05536_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_4 _17252_ (.I(net1601),
+ .ZN(_05537_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_4 _17253_ (.I(\gpio_control_in_2[0].resetn ),
+ .ZN(_05538_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_4 _17254_ (.I(net401),
+ .ZN(_05539_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_4 _17255_ (.I(net403),
+ .ZN(_05540_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_4 _17256_ (.I(net406),
+ .ZN(_05541_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_4 _17257_ (.I(net416),
+ .ZN(_05542_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_4 _17258_ (.I(net443),
+ .ZN(_05543_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_4 _17259_ (.I(net456),
+ .ZN(_05544_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_4 _17260_ (.I(net747),
+ .ZN(_05545_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_4 _17261_ (.I(net783),
+ .ZN(_05546_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_4 _17262_ (.I(net822),
+ .ZN(_05547_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_4 _17263_ (.I(net854),
+ .ZN(_05548_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_4 _17264_ (.I(net887),
+ .ZN(_05549_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_4 _17265_ (.I(net942),
+ .ZN(_05550_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_4 _17266_ (.I(net989),
+ .ZN(_05551_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_4 _17267_ (.I(net1172),
+ .ZN(_05552_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_4 _17268_ (.I(net1378),
+ .ZN(_05553_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__and2_4 _17269_ (.A1(\pll.pll_control.count0[1] ),
+ .A2(\pll.pll_control.count0[0] ),
+ .Z(_05554_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__and3_4 _17270_ (.A1(\pll.pll_control.count0[3] ),
+ .A2(\pll.pll_control.count0[2] ),
+ .A3(_05554_),
+ .Z(_05555_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _17271_ (.A1(\pll.pll_control.count0[4] ),
+ .A2(_05555_),
+ .ZN(_05556_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__xnor2_2 _17272_ (.A1(\pll.pll_control.oscbuf[1] ),
+ .A2(\pll.pll_control.oscbuf[2] ),
+ .ZN(_05557_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__xor2_4 _17273_ (.A1(\pll.pll_control.oscbuf[1] ),
+ .A2(\pll.pll_control.oscbuf[2] ),
+ .Z(_05558_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _17274_ (.A1(_05556_),
+ .A2(_05558_),
+ .ZN(_04962_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi21_4 _17275_ (.A1(\pll.pll_control.count0[2] ),
+ .A2(_05554_),
+ .B(\pll.pll_control.count0[3] ),
+ .ZN(_05559_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi211_4 _17276_ (.A1(_04963_),
+ .A2(_05555_),
+ .B(_05558_),
+ .C(_05559_),
+ .ZN(_04961_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_4 _17277_ (.A1(\pll.pll_control.count0[4] ),
+ .A2(_05555_),
+ .ZN(_05560_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__xnor2_1 _17278_ (.A1(\pll.pll_control.count0[2] ),
+ .A2(_05554_),
+ .ZN(_05561_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi21_4 _17279_ (.A1(_05560_),
+ .A2(_05561_),
+ .B(_05558_),
+ .ZN(_04960_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__xnor2_1 _17280_ (.A1(\pll.pll_control.count0[1] ),
+ .A2(\pll.pll_control.count0[0] ),
+ .ZN(_05562_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi21_4 _17281_ (.A1(_05560_),
+ .A2(_05562_),
+ .B(_05558_),
+ .ZN(_04959_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand3_4 _17282_ (.A1(_05560_),
+ .A2(_05557_),
+ .A3(\pll.pll_control.count0[0] ),
+ .ZN(_04958_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _17283_ (.A1(_05558_),
+ .A2(\pll.pll_control.prep[1] ),
+ .ZN(_05563_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _17284_ (.I0(\pll.pll_control.prep[2] ),
+ .I1(\pll.pll_control.prep[1] ),
+ .S(_05558_),
+ .Z(_04957_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _17285_ (.I0(\pll.pll_control.prep[1] ),
+ .I1(\pll.pll_control.prep[0] ),
+ .S(_05558_),
+ .Z(_04956_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _17286_ (.A1(_05557_),
+ .A2(_04964_),
+ .ZN(_04955_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _17287_ (.I0(\pll.pll_control.count1[4] ),
+ .I1(\pll.pll_control.count0[4] ),
+ .S(_05558_),
+ .Z(_04953_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _17288_ (.I0(\pll.pll_control.count1[3] ),
+ .I1(\pll.pll_control.count0[3] ),
+ .S(_05558_),
+ .Z(_04952_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _17289_ (.I0(\pll.pll_control.count1[2] ),
+ .I1(\pll.pll_control.count0[2] ),
+ .S(_05558_),
+ .Z(_04951_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _17290_ (.I0(\pll.pll_control.count1[1] ),
+ .I1(\pll.pll_control.count0[1] ),
+ .S(_05558_),
+ .Z(_04950_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _17291_ (.I0(\pll.pll_control.count1[0] ),
+ .I1(\pll.pll_control.count0[0] ),
+ .S(_05558_),
+ .Z(_04949_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_4 _17292_ (.A1(net1825),
+ .A2(\soc.core.grant[0] ),
+ .ZN(_05564_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_4 _17293_ (.A1(_05016_),
+ .A2(net1825),
+ .ZN(_05565_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_4 _17294_ (.A1(_05015_),
+ .A2(\soc.core.grant[0] ),
+ .ZN(_05566_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__and3_4 _17295_ (.A1(_05015_),
+ .A2(\soc.core.grant[0] ),
+ .A3(\soc.core.VexRiscv.dBusWishbone_ADR[5] ),
+ .Z(_05567_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi221_4 _17296_ (.A1(net1825),
+ .A2(\soc.core.dbg_uart_address[5] ),
+ .B1(\soc.core.VexRiscv.IBusCachedPlugin_cache.lineLoader_address[7] ),
+ .B2(net1633),
+ .C(_05567_),
+ .ZN(_05568_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_16 _17297_ (.I(net1529),
+ .ZN(\mgmt_buffers.mprj_adr_o_core[7] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _17298_ (.A1(\soc.core.VexRiscv.dBusWishbone_ADR[4] ),
+ .A2(net1587),
+ .ZN(_05569_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi22_4 _17299_ (.A1(net1825),
+ .A2(\soc.core.dbg_uart_address[4] ),
+ .B1(\soc.core.VexRiscv.IBusCachedPlugin_cache.lineLoader_address[6] ),
+ .B2(net1633),
+ .ZN(_05570_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__and2_4 _17300_ (.A1(_05569_),
+ .A2(_05570_),
+ .Z(_05571_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_8 _17301_ (.I(_05571_),
+ .ZN(\mgmt_buffers.mprj_adr_o_core[6] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__and3_4 _17302_ (.A1(_05015_),
+ .A2(\soc.core.grant[0] ),
+ .A3(\soc.core.VexRiscv.dBusWishbone_ADR[3] ),
+ .Z(_05572_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi221_4 _17303_ (.A1(net1825),
+ .A2(\soc.core.dbg_uart_address[3] ),
+ .B1(\soc.core.VexRiscv.IBusCachedPlugin_cache.lineLoader_address[5] ),
+ .B2(net1633),
+ .C(_05572_),
+ .ZN(_05573_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_16 _17304_ (.I(net1525),
+ .ZN(\mgmt_buffers.mprj_adr_o_core[5] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _17305_ (.A1(\soc.core.VexRiscv.dBusWishbone_ADR[2] ),
+ .A2(net1587),
+ .ZN(_05574_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi22_4 _17306_ (.A1(net1825),
+ .A2(\soc.core.dbg_uart_address[2] ),
+ .B1(net1633),
+ .B2(\soc.core.VexRiscv._zz_iBusWishbone_ADR[2] ),
+ .ZN(_05575_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__and2_4 _17307_ (.A1(_05574_),
+ .A2(_05575_),
+ .Z(_05576_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_16 _17308_ (.I(_05576_),
+ .ZN(\mgmt_buffers.mprj_adr_o_core[4] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _17309_ (.A1(\soc.core.VexRiscv.dBusWishbone_ADR[1] ),
+ .A2(net1587),
+ .ZN(_05577_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi22_4 _17310_ (.A1(net1825),
+ .A2(\soc.core.dbg_uart_address[1] ),
+ .B1(net1633),
+ .B2(\soc.core.VexRiscv._zz_iBusWishbone_ADR[1] ),
+ .ZN(_05578_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__and2_4 _17311_ (.A1(_05577_),
+ .A2(_05578_),
+ .Z(_05579_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_12 _17312_ (.I(_05579_),
+ .ZN(\mgmt_buffers.mprj_adr_o_core[3] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _17313_ (.A1(\soc.core.VexRiscv.dBusWishbone_ADR[0] ),
+ .A2(net1587),
+ .ZN(_05580_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi22_4 _17314_ (.A1(net1825),
+ .A2(\soc.core.dbg_uart_address[0] ),
+ .B1(net1633),
+ .B2(\soc.core.VexRiscv._zz_iBusWishbone_ADR[0] ),
+ .ZN(_05581_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__and2_4 _17315_ (.A1(_05580_),
+ .A2(_05581_),
+ .Z(_05582_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_16 _17316_ (.I(_05582_),
+ .ZN(\mgmt_buffers.mprj_adr_o_core[2] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _17317_ (.A1(\soc.core.mgmtsoc_litespisdrphycore_count[1] ),
+ .A2(\soc.core.mgmtsoc_litespisdrphycore_count[0] ),
+ .ZN(_05583_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_2 _17318_ (.I(_05583_),
+ .ZN(_05584_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_4 _17319_ (.A1(_05584_),
+ .A2(\soc.core.mgmtsoc_litespisdrphycore_count[2] ),
+ .ZN(_05585_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _17320_ (.A1(_05585_),
+ .A2(_05159_),
+ .ZN(\soc.core.flash_cs_n ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_2 _17321_ (.I(\soc.core.flash_cs_n ),
+ .ZN(_05586_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _17322_ (.I0(\soc.core.VexRiscv.dBusWishbone_DAT_MOSI[31] ),
+ .I1(\soc.core.dbg_uart_data[31] ),
+ .S(net1586),
+ .Z(\mgmt_buffers.mprj_dat_o_core[31] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_1 _17323_ (.I(net1523),
+ .ZN(_05587_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _17324_ (.I0(\soc.core.VexRiscv.dBusWishbone_DAT_MOSI[30] ),
+ .I1(\soc.core.dbg_uart_data[30] ),
+ .S(net1586),
+ .Z(\mgmt_buffers.mprj_dat_o_core[30] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_1 _17325_ (.I(net1519),
+ .ZN(_05588_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _17326_ (.I0(\soc.core.VexRiscv.dBusWishbone_DAT_MOSI[29] ),
+ .I1(\soc.core.dbg_uart_data[29] ),
+ .S(net1586),
+ .Z(\mgmt_buffers.mprj_dat_o_core[29] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_1 _17327_ (.I(net1516),
+ .ZN(_05589_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _17328_ (.I0(\soc.core.VexRiscv.dBusWishbone_DAT_MOSI[28] ),
+ .I1(\soc.core.dbg_uart_data[28] ),
+ .S(net1585),
+ .Z(\mgmt_buffers.mprj_dat_o_core[28] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_1 _17329_ (.I(net1513),
+ .ZN(_05590_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _17330_ (.I0(net2871),
+ .I1(\soc.core.dbg_uart_data[27] ),
+ .S(net1585),
+ .Z(\mgmt_buffers.mprj_dat_o_core[27] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_1 _17331_ (.I(\mgmt_buffers.mprj_dat_o_core[27] ),
+ .ZN(_05591_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _17332_ (.I0(net2843),
+ .I1(\soc.core.dbg_uart_data[26] ),
+ .S(net1585),
+ .Z(\mgmt_buffers.mprj_dat_o_core[26] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_1 _17333_ (.I(net1507),
+ .ZN(_05592_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _17334_ (.I0(net2840),
+ .I1(\soc.core.dbg_uart_data[25] ),
+ .S(net1585),
+ .Z(\mgmt_buffers.mprj_dat_o_core[25] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_1 _17335_ (.I(net1504),
+ .ZN(_05593_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _17336_ (.I0(net2829),
+ .I1(\soc.core.dbg_uart_data[24] ),
+ .S(net1586),
+ .Z(\mgmt_buffers.mprj_dat_o_core[24] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_1 _17337_ (.I(net1501),
+ .ZN(_05594_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _17338_ (.I0(\soc.core.VexRiscv.dBusWishbone_DAT_MOSI[23] ),
+ .I1(\soc.core.dbg_uart_data[23] ),
+ .S(net1585),
+ .Z(\mgmt_buffers.mprj_dat_o_core[23] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_1 _17339_ (.I(net1497),
+ .ZN(_05595_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _17340_ (.I0(\soc.core.VexRiscv.dBusWishbone_DAT_MOSI[22] ),
+ .I1(\soc.core.dbg_uart_data[22] ),
+ .S(net1585),
+ .Z(\mgmt_buffers.mprj_dat_o_core[22] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_1 _17341_ (.I(net1494),
+ .ZN(_05596_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _17342_ (.I0(\soc.core.VexRiscv.dBusWishbone_DAT_MOSI[21] ),
+ .I1(\soc.core.dbg_uart_data[21] ),
+ .S(net1586),
+ .Z(\mgmt_buffers.mprj_dat_o_core[21] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_1 _17343_ (.I(net1491),
+ .ZN(_05597_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _17344_ (.I0(\soc.core.VexRiscv.dBusWishbone_DAT_MOSI[20] ),
+ .I1(\soc.core.dbg_uart_data[20] ),
+ .S(net1585),
+ .Z(\mgmt_buffers.mprj_dat_o_core[20] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_1 _17345_ (.I(net1489),
+ .ZN(_05598_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _17346_ (.I0(net2876),
+ .I1(\soc.core.dbg_uart_data[19] ),
+ .S(net1585),
+ .Z(\mgmt_buffers.mprj_dat_o_core[19] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_1 _17347_ (.I(net1485),
+ .ZN(_05599_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _17348_ (.I0(\soc.core.VexRiscv.dBusWishbone_DAT_MOSI[18] ),
+ .I1(\soc.core.dbg_uart_data[18] ),
+ .S(net1585),
+ .Z(\mgmt_buffers.mprj_dat_o_core[18] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_1 _17349_ (.I(net1482),
+ .ZN(_05600_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _17350_ (.I0(\soc.core.VexRiscv.dBusWishbone_DAT_MOSI[17] ),
+ .I1(\soc.core.dbg_uart_data[17] ),
+ .S(net1585),
+ .Z(\mgmt_buffers.mprj_dat_o_core[17] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_1 _17351_ (.I(net1479),
+ .ZN(_05601_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _17352_ (.I0(\soc.core.VexRiscv.dBusWishbone_DAT_MOSI[16] ),
+ .I1(\soc.core.dbg_uart_data[16] ),
+ .S(net1586),
+ .Z(\mgmt_buffers.mprj_dat_o_core[16] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_1 _17353_ (.I(net1477),
+ .ZN(_05602_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _17354_ (.I0(\soc.core.VexRiscv.dBusWishbone_DAT_MOSI[15] ),
+ .I1(\soc.core.dbg_uart_data[15] ),
+ .S(net1586),
+ .Z(\mgmt_buffers.mprj_dat_o_core[15] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_1 _17355_ (.I(net1473),
+ .ZN(_05603_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _17356_ (.I0(\soc.core.VexRiscv.dBusWishbone_DAT_MOSI[14] ),
+ .I1(\soc.core.dbg_uart_data[14] ),
+ .S(net1586),
+ .Z(\mgmt_buffers.mprj_dat_o_core[14] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_1 _17357_ (.I(net1469),
+ .ZN(_05604_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _17358_ (.I0(\soc.core.VexRiscv.dBusWishbone_DAT_MOSI[13] ),
+ .I1(\soc.core.dbg_uart_data[13] ),
+ .S(net1586),
+ .Z(\mgmt_buffers.mprj_dat_o_core[13] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _17359_ (.I(\mgmt_buffers.mprj_dat_o_core[13] ),
+ .ZN(_05605_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _17360_ (.I0(\soc.core.VexRiscv.dBusWishbone_DAT_MOSI[12] ),
+ .I1(\soc.core.dbg_uart_data[12] ),
+ .S(net1586),
+ .Z(\mgmt_buffers.mprj_dat_o_core[12] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_1 _17361_ (.I(net1463),
+ .ZN(_05606_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _17362_ (.I0(\soc.core.VexRiscv.dBusWishbone_DAT_MOSI[11] ),
+ .I1(\soc.core.dbg_uart_data[11] ),
+ .S(net1585),
+ .Z(\mgmt_buffers.mprj_dat_o_core[11] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _17363_ (.I(\mgmt_buffers.mprj_dat_o_core[11] ),
+ .ZN(_05607_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _17364_ (.I0(\soc.core.VexRiscv.dBusWishbone_DAT_MOSI[10] ),
+ .I1(\soc.core.dbg_uart_data[10] ),
+ .S(net1585),
+ .Z(\mgmt_buffers.mprj_dat_o_core[10] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_1 _17365_ (.I(net1456),
+ .ZN(_05608_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _17366_ (.I0(\soc.core.VexRiscv.dBusWishbone_DAT_MOSI[9] ),
+ .I1(\soc.core.dbg_uart_data[9] ),
+ .S(net1585),
+ .Z(\mgmt_buffers.mprj_dat_o_core[9] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_1 _17367_ (.I(\mgmt_buffers.mprj_dat_o_core[9] ),
+ .ZN(_05609_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _17368_ (.I0(\soc.core.VexRiscv.dBusWishbone_DAT_MOSI[8] ),
+ .I1(\soc.core.dbg_uart_data[8] ),
+ .S(net1586),
+ .Z(\mgmt_buffers.mprj_dat_o_core[8] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_1 _17369_ (.I(\mgmt_buffers.mprj_dat_o_core[8] ),
+ .ZN(_05610_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _17370_ (.I0(_05372_),
+ .I1(_05057_),
+ .S(net1585),
+ .Z(_05611_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_12 _17371_ (.I(_05611_),
+ .ZN(\mgmt_buffers.mprj_dat_o_core[7] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _17372_ (.I0(_05371_),
+ .I1(_05058_),
+ .S(net1585),
+ .Z(_05612_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_12 _17373_ (.I(_05612_),
+ .ZN(\mgmt_buffers.mprj_dat_o_core[6] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _17374_ (.I0(_05370_),
+ .I1(_05059_),
+ .S(net1585),
+ .Z(_05613_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_12 _17375_ (.I(_05613_),
+ .ZN(\mgmt_buffers.mprj_dat_o_core[5] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _17376_ (.I0(_05369_),
+ .I1(_05060_),
+ .S(net1585),
+ .Z(_05614_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_8 _17377_ (.I(_05614_),
+ .ZN(\mgmt_buffers.mprj_dat_o_core[4] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _17378_ (.I0(_05368_),
+ .I1(_05061_),
+ .S(net1585),
+ .Z(_05615_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_12 _17379_ (.I(_05615_),
+ .ZN(\mgmt_buffers.mprj_dat_o_core[3] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _17380_ (.I0(_05367_),
+ .I1(_05062_),
+ .S(net1585),
+ .Z(_05616_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_12 _17381_ (.I(_05616_),
+ .ZN(\mgmt_buffers.mprj_dat_o_core[2] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _17382_ (.I0(_05366_),
+ .I1(_05063_),
+ .S(net1585),
+ .Z(_05617_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_12 _17383_ (.I(_05617_),
+ .ZN(\mgmt_buffers.mprj_dat_o_core[1] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _17384_ (.I0(_05365_),
+ .I1(_05064_),
+ .S(net1585),
+ .Z(_05618_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_12 _17385_ (.I(_05618_),
+ .ZN(\mgmt_buffers.mprj_dat_o_core[0] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_4 _17386_ (.A1(\pll.pll_control.tint[3] ),
+ .A2(\pll.pll_control.tint[2] ),
+ .ZN(_05619_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _17387_ (.A1(_05212_),
+ .A2(_05213_),
+ .ZN(_05620_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_4 _17388_ (.A1(\pll.pll_control.tint[1] ),
+ .A2(\pll.pll_control.tint[0] ),
+ .ZN(_05621_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_4 _17389_ (.A1(_05214_),
+ .A2(_05215_),
+ .ZN(_05622_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _17390_ (.A1(\pll.pll_control.count0[4] ),
+ .A2(\pll.pll_control.count1[4] ),
+ .ZN(_05623_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__xor2_1 _17391_ (.A1(\pll.pll_control.count0[4] ),
+ .A2(\pll.pll_control.count1[4] ),
+ .Z(_05624_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _17392_ (.A1(\pll.pll_control.count0[3] ),
+ .A2(\pll.pll_control.count1[3] ),
+ .ZN(_05625_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _17393_ (.A1(\pll.pll_control.count0[3] ),
+ .A2(\pll.pll_control.count1[3] ),
+ .ZN(_05626_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _17394_ (.A1(\pll.pll_control.count0[2] ),
+ .A2(\pll.pll_control.count1[2] ),
+ .ZN(_05627_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _17395_ (.I(_05627_),
+ .ZN(_05628_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__or2_4 _17396_ (.A1(\pll.pll_control.count0[2] ),
+ .A2(\pll.pll_control.count1[2] ),
+ .Z(_05629_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _17397_ (.A1(\pll.pll_control.count0[1] ),
+ .A2(\pll.pll_control.count1[1] ),
+ .ZN(_05630_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _17398_ (.A1(\pll.pll_control.count0[0] ),
+ .A2(\pll.pll_control.count1[0] ),
+ .ZN(_05631_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _17399_ (.A1(\pll.pll_control.count0[1] ),
+ .A2(\pll.pll_control.count1[1] ),
+ .ZN(_05632_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _17400_ (.A1(_05632_),
+ .A2(_05631_),
+ .B(_05630_),
+ .ZN(_05633_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi21_4 _17401_ (.A1(_05629_),
+ .A2(_05633_),
+ .B(_05628_),
+ .ZN(_05634_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _17402_ (.A1(_05625_),
+ .A2(_05634_),
+ .B(_05626_),
+ .ZN(_05635_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _17403_ (.A1(_05624_),
+ .A2(_05635_),
+ .ZN(_05636_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _17404_ (.A1(_05623_),
+ .A2(_05636_),
+ .ZN(_05637_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__xnor2_1 _17405_ (.A1(_05624_),
+ .A2(_05635_),
+ .ZN(_05638_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _17406_ (.A1(_05638_),
+ .A2(\pll.div[4] ),
+ .ZN(_05639_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _17407_ (.A1(_05639_),
+ .A2(_05637_),
+ .ZN(_05640_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__xnor3_2 _17408_ (.A1(\pll.pll_control.count0[2] ),
+ .A2(\pll.pll_control.count1[2] ),
+ .A3(_05633_),
+ .ZN(_05641_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__xor3_2 _17409_ (.A1(\pll.pll_control.count0[3] ),
+ .A2(\pll.pll_control.count1[3] ),
+ .A3(_05634_),
+ .Z(_05642_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi22_4 _17410_ (.A1(\pll.div[2] ),
+ .A2(_05641_),
+ .B1(_05642_),
+ .B2(\pll.div[3] ),
+ .ZN(_05643_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _17411_ (.A1(\pll.div[3] ),
+ .A2(_05642_),
+ .ZN(_05644_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__xor2_1 _17412_ (.A1(\pll.div[2] ),
+ .A2(_05641_),
+ .Z(_05645_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__xor2_1 _17413_ (.A1(\pll.div[3] ),
+ .A2(_05642_),
+ .Z(_05646_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _17414_ (.A1(_05645_),
+ .A2(_05646_),
+ .ZN(_05647_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__xor3_2 _17415_ (.A1(\pll.pll_control.count0[1] ),
+ .A2(\pll.pll_control.count1[1] ),
+ .A3(_05631_),
+ .Z(_05648_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__xnor2_1 _17416_ (.A1(\pll.pll_control.count0[0] ),
+ .A2(\pll.pll_control.count1[0] ),
+ .ZN(_05649_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _17417_ (.A1(_05649_),
+ .A2(\pll.div[0] ),
+ .ZN(_05650_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__xnor2_1 _17418_ (.A1(\pll.div[1] ),
+ .A2(_05648_),
+ .ZN(_05651_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _17419_ (.A1(_05651_),
+ .A2(_05650_),
+ .ZN(_05652_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi21_4 _17420_ (.A1(\pll.div[1] ),
+ .A2(_05648_),
+ .B(_05652_),
+ .ZN(_05653_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _17421_ (.A1(_05638_),
+ .A2(\pll.div[4] ),
+ .ZN(_05654_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _17422_ (.A1(_05653_),
+ .A2(_05647_),
+ .B1(_05644_),
+ .B2(_05643_),
+ .C(_05654_),
+ .ZN(_05655_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_4 _17423_ (.A1(_05655_),
+ .A2(_05640_),
+ .ZN(_05656_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_8 _17424_ (.I(_05656_),
+ .ZN(_05657_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _17425_ (.A1(_05216_),
+ .A2(_05656_),
+ .ZN(_05658_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _17426_ (.A1(\pll.pll_control.tval[1] ),
+ .A2(_05657_),
+ .ZN(_05659_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _17427_ (.A1(_05658_),
+ .A2(\pll.pll_control.tval[0] ),
+ .ZN(_05660_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _17428_ (.A1(_05659_),
+ .A2(_05660_),
+ .ZN(_05661_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__xor2_1 _17429_ (.A1(_05215_),
+ .A2(_05656_),
+ .Z(_05662_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _17430_ (.A1(_05661_),
+ .A2(_05662_),
+ .ZN(_05663_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__and3_4 _17431_ (.A1(\pll.pll_control.tint[0] ),
+ .A2(\pll.pll_control.tval[1] ),
+ .A3(\pll.pll_control.tval[0] ),
+ .Z(_05664_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _17432_ (.A1(_05657_),
+ .A2(_05622_),
+ .ZN(_05665_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi22_4 _17433_ (.A1(_05214_),
+ .A2(_05656_),
+ .B1(_05663_),
+ .B2(_05665_),
+ .ZN(_05666_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__xor2_1 _17434_ (.A1(\pll.pll_control.tint[2] ),
+ .A2(_05656_),
+ .Z(_05667_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_2 _17435_ (.I(_05667_),
+ .ZN(_05668_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__and2_4 _17436_ (.A1(_05666_),
+ .A2(_05668_),
+ .Z(_05669_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__and3_4 _17437_ (.A1(_05666_),
+ .A2(_05213_),
+ .A3(_05657_),
+ .Z(_05670_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__xor2_1 _17438_ (.A1(\pll.pll_control.tint[3] ),
+ .A2(_05656_),
+ .Z(_05671_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _17439_ (.A1(\pll.pll_control.tint[4] ),
+ .A2(\pll.pll_control.tint[1] ),
+ .ZN(_05672_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _17440_ (.A1(\pll.pll_control.tint[3] ),
+ .A2(\pll.pll_control.tint[2] ),
+ .ZN(_05673_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _17441_ (.A1(_05672_),
+ .A2(_05673_),
+ .ZN(_05674_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _17442_ (.A1(_05664_),
+ .A2(_05674_),
+ .ZN(_05675_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _17443_ (.A1(_05649_),
+ .A2(\pll.div[0] ),
+ .ZN(_05676_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__and3_4 _17444_ (.A1(_05640_),
+ .A2(_05652_),
+ .A3(_05676_),
+ .Z(_05677_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__and3_4 _17445_ (.A1(_05645_),
+ .A2(_05646_),
+ .A3(_05654_),
+ .Z(_05678_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi211_4 _17446_ (.A1(_05677_),
+ .A2(_05678_),
+ .B(_04964_),
+ .C(_05563_),
+ .ZN(_05679_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _17447_ (.A1(_05657_),
+ .A2(_05675_),
+ .B(_05679_),
+ .C(\pll.pll_control.prep[2] ),
+ .ZN(_05680_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_4 _17448_ (.A1(_05620_),
+ .A2(\pll.pll_control.tint[4] ),
+ .ZN(_05681_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _17449_ (.A1(_05619_),
+ .A2(_05211_),
+ .ZN(_05682_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _17450_ (.A1(_05621_),
+ .A2(_05681_),
+ .ZN(_05683_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _17451_ (.A1(\pll.pll_control.tval[1] ),
+ .A2(\pll.pll_control.tval[0] ),
+ .ZN(_05684_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__and3_4 _17452_ (.A1(_05621_),
+ .A2(_05681_),
+ .A3(_05684_),
+ .Z(_05685_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi21_4 _17453_ (.A1(_05657_),
+ .A2(_05685_),
+ .B(_05680_),
+ .ZN(_05686_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _17454_ (.A1(_05670_),
+ .A2(_05671_),
+ .ZN(_05687_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _17455_ (.A1(_05619_),
+ .A2(_05669_),
+ .B(_05686_),
+ .C(_05687_),
+ .ZN(_05688_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__xor2_1 _17456_ (.A1(_05211_),
+ .A2(_05688_),
+ .Z(_02845_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi22_4 _17457_ (.A1(_05666_),
+ .A2(_05668_),
+ .B1(\pll.pll_control.tint[2] ),
+ .B2(_05657_),
+ .ZN(_05689_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__xor2_1 _17458_ (.A1(_05671_),
+ .A2(_05689_),
+ .Z(_05690_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _17459_ (.I0(\pll.pll_control.tint[3] ),
+ .I1(_05690_),
+ .S(_05686_),
+ .Z(_02844_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__xor2_1 _17460_ (.A1(_05666_),
+ .A2(_05668_),
+ .Z(_05691_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _17461_ (.I0(\pll.pll_control.tint[2] ),
+ .I1(_05691_),
+ .S(_05686_),
+ .Z(_02843_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _17462_ (.A1(_05684_),
+ .A2(_05215_),
+ .ZN(_05692_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _17463_ (.A1(_05657_),
+ .A2(_05692_),
+ .ZN(_05693_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _17464_ (.A1(_05657_),
+ .A2(_05664_),
+ .B(_05686_),
+ .C(_05693_),
+ .ZN(_05694_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__xor2_1 _17465_ (.A1(_05214_),
+ .A2(_05694_),
+ .Z(_02842_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__xor2_1 _17466_ (.A1(_05661_),
+ .A2(_05662_),
+ .Z(_05695_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _17467_ (.I0(\pll.pll_control.tint[0] ),
+ .I1(_05695_),
+ .S(_05686_),
+ .Z(_02841_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__xor2_2 _17468_ (.A1(_05216_),
+ .A2(_05656_),
+ .Z(_05696_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _17469_ (.A1(\pll.pll_control.tval[0] ),
+ .A2(_05696_),
+ .B(_05686_),
+ .ZN(_05697_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi21_4 _17470_ (.A1(\pll.pll_control.tval[0] ),
+ .A2(_05696_),
+ .B(_05697_),
+ .ZN(_05698_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi21_4 _17471_ (.A1(\pll.pll_control.tval[1] ),
+ .A2(_05680_),
+ .B(_05698_),
+ .ZN(_05699_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _17472_ (.I(_05699_),
+ .ZN(_02840_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _17473_ (.I0(_05686_),
+ .I1(_05680_),
+ .S(\pll.pll_control.tval[0] ),
+ .Z(_02839_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _17474_ (.A1(\soc.core.VexRiscv.dBusWishbone_ADR[29] ),
+ .A2(net1587),
+ .ZN(_05700_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi22_4 _17475_ (.A1(net1826),
+ .A2(\soc.core.dbg_uart_address[29] ),
+ .B1(\soc.core.VexRiscv.IBusCachedPlugin_cache.lineLoader_address[31] ),
+ .B2(net1634),
+ .ZN(_05701_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__and2_4 _17476_ (.A1(_05700_),
+ .A2(_05701_),
+ .Z(_05702_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_12 _17477_ (.I(_05702_),
+ .ZN(\mgmt_buffers.mprj_adr_o_core[31] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _17478_ (.A1(\soc.core.VexRiscv.dBusWishbone_ADR[28] ),
+ .A2(net1587),
+ .ZN(_05703_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi22_4 _17479_ (.A1(net1826),
+ .A2(\soc.core.dbg_uart_address[28] ),
+ .B1(\soc.core.VexRiscv.IBusCachedPlugin_cache.lineLoader_address[30] ),
+ .B2(net1633),
+ .ZN(_05704_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__and2_4 _17480_ (.A1(_05703_),
+ .A2(_05704_),
+ .Z(_05705_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_12 _17481_ (.I(_05705_),
+ .ZN(\mgmt_buffers.mprj_adr_o_core[30] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _17482_ (.A1(\soc.core.VexRiscv.dBusWishbone_ADR[27] ),
+ .A2(net1587),
+ .ZN(_05706_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi22_4 _17483_ (.A1(net1826),
+ .A2(\soc.core.dbg_uart_address[27] ),
+ .B1(\soc.core.VexRiscv.IBusCachedPlugin_cache.lineLoader_address[29] ),
+ .B2(net1633),
+ .ZN(_05707_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_4 _17484_ (.A1(_05706_),
+ .A2(_05707_),
+ .ZN(\mgmt_buffers.mprj_adr_o_core[29] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_3 _17485_ (.I(\mgmt_buffers.mprj_adr_o_core[29] ),
+ .ZN(_05708_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _17486_ (.A1(\soc.core.VexRiscv.dBusWishbone_ADR[26] ),
+ .A2(net1588),
+ .ZN(_05709_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi22_4 _17487_ (.A1(net1826),
+ .A2(\soc.core.dbg_uart_address[26] ),
+ .B1(\soc.core.VexRiscv.IBusCachedPlugin_cache.lineLoader_address[28] ),
+ .B2(net1633),
+ .ZN(_05710_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__and2_4 _17488_ (.A1(_05709_),
+ .A2(_05710_),
+ .Z(_05711_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_12 _17489_ (.I(_05711_),
+ .ZN(\mgmt_buffers.mprj_adr_o_core[28] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _17490_ (.A1(\soc.core.VexRiscv.dBusWishbone_ADR[24] ),
+ .A2(net1587),
+ .ZN(_05712_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi22_4 _17491_ (.A1(net1826),
+ .A2(\soc.core.dbg_uart_address[24] ),
+ .B1(\soc.core.VexRiscv.IBusCachedPlugin_cache.lineLoader_address[26] ),
+ .B2(net1633),
+ .ZN(_05713_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__and2_4 _17492_ (.A1(_05712_),
+ .A2(_05713_),
+ .Z(_05714_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_12 _17493_ (.I(_05714_),
+ .ZN(\mgmt_buffers.mprj_adr_o_core[26] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi222_4 _17494_ (.A1(net1826),
+ .A2(\soc.core.dbg_uart_address[23] ),
+ .B1(\soc.core.VexRiscv.IBusCachedPlugin_cache.lineLoader_address[25] ),
+ .B2(net1633),
+ .C1(net1587),
+ .C2(\soc.core.VexRiscv.dBusWishbone_ADR[23] ),
+ .ZN(_05715_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_12 _17495_ (.I(net1447),
+ .ZN(\mgmt_buffers.mprj_adr_o_core[25] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi222_4 _17496_ (.A1(net1826),
+ .A2(\soc.core.dbg_uart_address[17] ),
+ .B1(\soc.core.VexRiscv.IBusCachedPlugin_cache.lineLoader_address[19] ),
+ .B2(net1633),
+ .C1(net1588),
+ .C2(\soc.core.VexRiscv.dBusWishbone_ADR[17] ),
+ .ZN(_05716_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_12 _17497_ (.I(_05716_),
+ .ZN(\mgmt_buffers.mprj_adr_o_core[19] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _17498_ (.A1(\soc.core.VexRiscv.dBusWishbone_ADR[16] ),
+ .A2(net1588),
+ .ZN(_05717_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi22_4 _17499_ (.A1(net1826),
+ .A2(\soc.core.dbg_uart_address[16] ),
+ .B1(\soc.core.VexRiscv.IBusCachedPlugin_cache.lineLoader_address[18] ),
+ .B2(net1634),
+ .ZN(_05718_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__and2_4 _17500_ (.A1(_05717_),
+ .A2(_05718_),
+ .Z(_05719_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_12 _17501_ (.I(_05719_),
+ .ZN(\mgmt_buffers.mprj_adr_o_core[18] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _17502_ (.A1(\soc.core.VexRiscv.dBusWishbone_ADR[15] ),
+ .A2(net1587),
+ .ZN(_05720_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi22_4 _17503_ (.A1(net1826),
+ .A2(\soc.core.dbg_uart_address[15] ),
+ .B1(\soc.core.VexRiscv.IBusCachedPlugin_cache.lineLoader_address[17] ),
+ .B2(net1634),
+ .ZN(_05721_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_4 _17504_ (.A1(_05720_),
+ .A2(_05721_),
+ .ZN(\mgmt_buffers.mprj_adr_o_core[17] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _17505_ (.A1(\soc.core.VexRiscv.dBusWishbone_ADR[14] ),
+ .A2(net1588),
+ .ZN(_05722_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi22_4 _17506_ (.A1(net1826),
+ .A2(\soc.core.dbg_uart_address[14] ),
+ .B1(\soc.core.VexRiscv.IBusCachedPlugin_cache.lineLoader_address[16] ),
+ .B2(net1634),
+ .ZN(_05723_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_4 _17507_ (.A1(_05722_),
+ .A2(_05723_),
+ .ZN(\mgmt_buffers.mprj_adr_o_core[16] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_1 _17508_ (.I(net1333),
+ .ZN(_05724_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _17509_ (.A1(\soc.core.VexRiscv.dBusWishbone_ADR[9] ),
+ .A2(net1587),
+ .ZN(_05725_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi22_4 _17510_ (.A1(net1825),
+ .A2(\soc.core.dbg_uart_address[9] ),
+ .B1(\soc.core.VexRiscv.IBusCachedPlugin_cache.lineLoader_address[11] ),
+ .B2(net1633),
+ .ZN(_05726_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__and2_4 _17511_ (.A1(_05725_),
+ .A2(_05726_),
+ .Z(_05727_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_8 _17512_ (.I(_05727_),
+ .ZN(\mgmt_buffers.mprj_adr_o_core[11] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _17513_ (.A1(\soc.core.VexRiscv.IBusCachedPlugin_cache.lineLoader_address[24] ),
+ .A2(net1634),
+ .ZN(_05728_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _17514_ (.A1(_05015_),
+ .A2(_05066_),
+ .B1(_05229_),
+ .B2(_05566_),
+ .C(_05728_),
+ .ZN(\mgmt_buffers.mprj_adr_o_core[24] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _17515_ (.A1(\soc.core.VexRiscv.IBusCachedPlugin_cache.lineLoader_address[12] ),
+ .A2(net1633),
+ .ZN(_05729_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi22_4 _17516_ (.A1(net1825),
+ .A2(\soc.core.dbg_uart_address[10] ),
+ .B1(\soc.core.VexRiscv.dBusWishbone_ADR[10] ),
+ .B2(net1587),
+ .ZN(_05730_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__and2_4 _17517_ (.A1(_05730_),
+ .A2(_05729_),
+ .Z(_05731_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_16 _17518_ (.I(_05731_),
+ .ZN(\mgmt_buffers.mprj_adr_o_core[12] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _17519_ (.A1(\soc.core.VexRiscv.dBusWishbone_ADR[11] ),
+ .A2(net1587),
+ .ZN(_05732_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi22_4 _17520_ (.A1(net1825),
+ .A2(\soc.core.dbg_uart_address[11] ),
+ .B1(\soc.core.VexRiscv.IBusCachedPlugin_cache.lineLoader_address[13] ),
+ .B2(net1633),
+ .ZN(_05733_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__and2_4 _17521_ (.A1(_05732_),
+ .A2(_05733_),
+ .Z(_05734_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_12 _17522_ (.I(net1330),
+ .ZN(\mgmt_buffers.mprj_adr_o_core[13] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _17523_ (.A1(\soc.core.VexRiscv.dBusWishbone_ADR[12] ),
+ .A2(net1587),
+ .ZN(_05735_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi22_4 _17524_ (.A1(net1825),
+ .A2(\soc.core.dbg_uart_address[12] ),
+ .B1(\soc.core.VexRiscv.IBusCachedPlugin_cache.lineLoader_address[14] ),
+ .B2(net1633),
+ .ZN(_05736_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__and2_4 _17525_ (.A1(_05735_),
+ .A2(_05736_),
+ .Z(_05737_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_12 _17526_ (.I(_05737_),
+ .ZN(\mgmt_buffers.mprj_adr_o_core[14] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _17527_ (.A1(\soc.core.VexRiscv.dBusWishbone_ADR[13] ),
+ .A2(_05565_),
+ .ZN(_05738_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi22_4 _17528_ (.A1(net1826),
+ .A2(\soc.core.dbg_uart_address[13] ),
+ .B1(\soc.core.VexRiscv.IBusCachedPlugin_cache.lineLoader_address[15] ),
+ .B2(net1634),
+ .ZN(_05739_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__and2_4 _17529_ (.A1(_05738_),
+ .A2(_05739_),
+ .Z(_05740_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_8 _17530_ (.I(_05740_),
+ .ZN(\mgmt_buffers.mprj_adr_o_core[15] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi222_4 _17531_ (.A1(net1825),
+ .A2(net2957),
+ .B1(\soc.core.VexRiscv.IBusCachedPlugin_cache.lineLoader_address[8] ),
+ .B2(net1633),
+ .C1(_05565_),
+ .C2(\soc.core.VexRiscv.dBusWishbone_ADR[6] ),
+ .ZN(_05741_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_8 _17532_ (.I(_05741_),
+ .ZN(\mgmt_buffers.mprj_adr_o_core[8] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi222_4 _17533_ (.A1(net1825),
+ .A2(\soc.core.dbg_uart_address[7] ),
+ .B1(\soc.core.VexRiscv.IBusCachedPlugin_cache.lineLoader_address[9] ),
+ .B2(net1633),
+ .C1(net1588),
+ .C2(\soc.core.VexRiscv.dBusWishbone_ADR[7] ),
+ .ZN(_05742_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_12 _17534_ (.I(net1440),
+ .ZN(\mgmt_buffers.mprj_adr_o_core[9] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__and3_4 _17535_ (.A1(_05015_),
+ .A2(\soc.core.grant[0] ),
+ .A3(\soc.core.VexRiscv.dBusWishbone_ADR[8] ),
+ .Z(_05743_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi221_4 _17536_ (.A1(net1825),
+ .A2(\soc.core.dbg_uart_address[8] ),
+ .B1(\soc.core.VexRiscv.IBusCachedPlugin_cache.lineLoader_address[10] ),
+ .B2(net1633),
+ .C(_05743_),
+ .ZN(_05744_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_12 _17537_ (.I(net1437),
+ .ZN(\mgmt_buffers.mprj_adr_o_core[10] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _17538_ (.A1(\soc.core.VexRiscv.dBusWishbone_WE ),
+ .A2(net1587),
+ .ZN(_05745_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_4 _17539_ (.A1(_05017_),
+ .A2(\soc.core.uartwishbonebridge_state[1] ),
+ .ZN(_05746_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_4 _17540_ (.A1(_05018_),
+ .A2(\soc.core.uartwishbonebridge_state[2] ),
+ .ZN(_05747_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_4 _17541_ (.A1(_05747_),
+ .A2(\soc.core.uartwishbonebridge_state[0] ),
+ .ZN(_05748_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _17542_ (.A1(net1825),
+ .A2(_05748_),
+ .ZN(_05749_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__and2_4 _17543_ (.A1(_05745_),
+ .A2(_05749_),
+ .Z(_05750_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_12 _17544_ (.I(_05750_),
+ .ZN(\mgmt_buffers.mprj_we_o_core ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _17545_ (.A1(\soc.core.VexRiscv.dBus_cmd_halfPipe_payload_address[1] ),
+ .A2(\soc.core.VexRiscv.dBus_cmd_halfPipe_payload_address[0] ),
+ .B(net1587),
+ .C(\soc.core.VexRiscv.dBusWishbone_WE ),
+ .ZN(\mgmt_buffers.mprj_sel_o_core[0] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_4 _17546_ (.I(net1434),
+ .ZN(\soc.core.sram.ram512x32.WEN[0] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _17547_ (.A1(\soc.core.VexRiscv.dBus_cmd_halfPipe_payload_address[0] ),
+ .A2(\soc.core.VexRiscv.dBus_cmd_halfPipe_payload_size[1] ),
+ .ZN(_05751_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _17548_ (.I(_05751_),
+ .ZN(_05752_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_4 _17549_ (.A1(_05752_),
+ .A2(\soc.core.VexRiscv.dBus_cmd_halfPipe_payload_size[0] ),
+ .ZN(_05753_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _17550_ (.A1(\soc.core.VexRiscv.dBus_cmd_halfPipe_payload_address[1] ),
+ .A2(_05753_),
+ .B(net1587),
+ .C(\soc.core.VexRiscv.dBusWishbone_WE ),
+ .ZN(\mgmt_buffers.mprj_sel_o_core[1] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_4 _17551_ (.I(net1318),
+ .ZN(\soc.core.sram.ram512x32.WEN[1] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _17552_ (.A1(\soc.core.VexRiscv.dBus_cmd_halfPipe_payload_address[0] ),
+ .A2(\soc.core.VexRiscv.dBus_cmd_halfPipe_payload_size[0] ),
+ .ZN(_05754_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_4 _17553_ (.A1(\soc.core.VexRiscv.dBus_cmd_halfPipe_payload_address[1] ),
+ .A2(\soc.core.VexRiscv.dBus_cmd_halfPipe_payload_size[1] ),
+ .ZN(_05755_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi22_4 _17554_ (.A1(_05755_),
+ .A2(_05754_),
+ .B1(\soc.core.VexRiscv.dBus_cmd_halfPipe_payload_address[0] ),
+ .B2(\soc.core.VexRiscv.dBus_cmd_halfPipe_payload_address[1] ),
+ .ZN(_05756_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_4 _17555_ (.A1(_05745_),
+ .A2(_05756_),
+ .ZN(\soc.core.sram.ram512x32.WEN[2] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_12 _17556_ (.I(\soc.core.sram.ram512x32.WEN[2] ),
+ .ZN(\mgmt_buffers.mprj_sel_o_core[2] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _17557_ (.A1(_05753_),
+ .A2(_05755_),
+ .B(net2863),
+ .C(net1587),
+ .ZN(\mgmt_buffers.mprj_sel_o_core[3] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_4 _17558_ (.I(net1314),
+ .ZN(\soc.core.sram.ram512x32.WEN[3] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi211_4 _17559_ (.A1(\soc.core.mgmtsoc_reset_storage[0] ),
+ .A2(\soc.core.mgmtsoc_reset_re ),
+ .B(\soc.core.mgmtsoc_vexriscv_debug_reset ),
+ .C(\soc.core.mgmtsoc_cpu_rst ),
+ .ZN(_05757_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_4 _17560_ (.A1(net1632),
+ .A2(net1645),
+ .ZN(\soc.core.VexRiscv.IBusCachedPlugin_cache.reset ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_16 _17561_ (.I(net1580),
+ .ZN(_00130_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _17562_ (.A1(\soc.core.VexRiscv._zz_iBusWishbone_ADR[2] ),
+ .A2(\soc.core.VexRiscv._zz_iBusWishbone_ADR[1] ),
+ .ZN(_05758_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _17563_ (.A1(\soc.core.VexRiscv.IBusCachedPlugin_cache.lineLoader_cmdSent ),
+ .A2(_05005_),
+ .B(_05758_),
+ .C(_04969_),
+ .ZN(_05759_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_1 _17564_ (.I(_05759_),
+ .ZN(_05760_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_4 _17565_ (.A1(_05759_),
+ .A2(net1633),
+ .ZN(_05761_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _17566_ (.I(_05761_),
+ .ZN(_05762_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi21_4 _17567_ (.A1(net1785),
+ .A2(\soc.core.grant[0] ),
+ .B(net1825),
+ .ZN(_05763_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi22_4 _17568_ (.A1(_05761_),
+ .A2(_05763_),
+ .B1(net1825),
+ .B2(_05747_),
+ .ZN(\mgmt_buffers.mprj_stb_o_core ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_1 _17569_ (.I(\mgmt_buffers.mprj_stb_o_core ),
+ .ZN(_05764_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _17570_ (.A1(\soc.core.VexRiscv.IBusCachedPlugin_cache.lineLoader_address[27] ),
+ .A2(net1634),
+ .ZN(_05765_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _17571_ (.A1(_05015_),
+ .A2(_05065_),
+ .B1(_05230_),
+ .B2(_05566_),
+ .C(_05765_),
+ .ZN(\mgmt_buffers.mprj_adr_o_core[27] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi222_4 _17572_ (.A1(net1826),
+ .A2(\soc.core.dbg_uart_address[18] ),
+ .B1(\soc.core.VexRiscv.IBusCachedPlugin_cache.lineLoader_address[20] ),
+ .B2(net1634),
+ .C1(net1588),
+ .C2(\soc.core.VexRiscv.dBusWishbone_ADR[18] ),
+ .ZN(_05766_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_12 _17573_ (.I(net1428),
+ .ZN(\mgmt_buffers.mprj_adr_o_core[20] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _17574_ (.A1(\soc.core.VexRiscv.dBusWishbone_ADR[19] ),
+ .A2(net1587),
+ .ZN(_05767_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi22_4 _17575_ (.A1(net1826),
+ .A2(\soc.core.dbg_uart_address[19] ),
+ .B1(\soc.core.VexRiscv.IBusCachedPlugin_cache.lineLoader_address[21] ),
+ .B2(net1634),
+ .ZN(_05768_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__and2_4 _17576_ (.A1(_05767_),
+ .A2(_05768_),
+ .Z(_05769_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_12 _17577_ (.I(_05769_),
+ .ZN(\mgmt_buffers.mprj_adr_o_core[21] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _17578_ (.A1(\soc.core.VexRiscv.dBusWishbone_ADR[20] ),
+ .A2(net1588),
+ .ZN(_05770_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi22_4 _17579_ (.A1(net1826),
+ .A2(\soc.core.dbg_uart_address[20] ),
+ .B1(\soc.core.VexRiscv.IBusCachedPlugin_cache.lineLoader_address[22] ),
+ .B2(net1634),
+ .ZN(_05771_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__and2_4 _17580_ (.A1(_05770_),
+ .A2(_05771_),
+ .Z(_05772_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_12 _17581_ (.I(_05772_),
+ .ZN(\mgmt_buffers.mprj_adr_o_core[22] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi222_4 _17582_ (.A1(net1826),
+ .A2(\soc.core.dbg_uart_address[21] ),
+ .B1(\soc.core.VexRiscv.IBusCachedPlugin_cache.lineLoader_address[23] ),
+ .B2(net1634),
+ .C1(net1588),
+ .C2(\soc.core.VexRiscv.dBusWishbone_ADR[21] ),
+ .ZN(_05773_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_12 _17583_ (.I(net1424),
+ .ZN(\mgmt_buffers.mprj_adr_o_core[23] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _17584_ (.A1(\soc.core.VexRiscv._zz_CsrPlugin_csrMapping_readDataInit[0] ),
+ .A2(\soc.core.VexRiscv.externalInterruptArray_regNext[0] ),
+ .ZN(_05774_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _17585_ (.A1(\soc.core.VexRiscv._zz_CsrPlugin_csrMapping_readDataInit[2] ),
+ .A2(\soc.core.VexRiscv.externalInterruptArray_regNext[2] ),
+ .ZN(_05775_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi22_4 _17586_ (.A1(\soc.core.VexRiscv._zz_CsrPlugin_csrMapping_readDataInit[0] ),
+ .A2(\soc.core.VexRiscv.externalInterruptArray_regNext[0] ),
+ .B1(\soc.core.VexRiscv.externalInterruptArray_regNext[7] ),
+ .B2(\soc.core.VexRiscv._zz_CsrPlugin_csrMapping_readDataInit[7] ),
+ .ZN(_05776_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi22_4 _17587_ (.A1(\soc.core.VexRiscv._zz_CsrPlugin_csrMapping_readDataInit[2] ),
+ .A2(\soc.core.VexRiscv.externalInterruptArray_regNext[2] ),
+ .B1(\soc.core.VexRiscv.externalInterruptArray_regNext[5] ),
+ .B2(\soc.core.VexRiscv._zz_CsrPlugin_csrMapping_readDataInit[5] ),
+ .ZN(_05777_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi22_4 _17588_ (.A1(\soc.core.VexRiscv._zz_CsrPlugin_csrMapping_readDataInit[3] ),
+ .A2(\soc.core.VexRiscv.externalInterruptArray_regNext[3] ),
+ .B1(\soc.core.VexRiscv.externalInterruptArray_regNext[6] ),
+ .B2(\soc.core.VexRiscv._zz_CsrPlugin_csrMapping_readDataInit[6] ),
+ .ZN(_05778_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _17589_ (.A1(_05777_),
+ .A2(_05778_),
+ .ZN(_05779_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi221_4 _17590_ (.A1(\soc.core.VexRiscv._zz_CsrPlugin_csrMapping_readDataInit[1] ),
+ .A2(\soc.core.VexRiscv.externalInterruptArray_regNext[1] ),
+ .B1(\soc.core.VexRiscv.externalInterruptArray_regNext[4] ),
+ .B2(\soc.core.VexRiscv._zz_CsrPlugin_csrMapping_readDataInit[4] ),
+ .C(_05779_),
+ .ZN(_05780_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _17591_ (.A1(_05776_),
+ .A2(_05780_),
+ .ZN(\soc.core.VexRiscv.externalInterrupt ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_4 _17592_ (.A1(_04970_),
+ .A2(\soc.core.VexRiscv.IBusCachedPlugin_cache._zz_when_Fetcher_l398[1] ),
+ .ZN(_05781_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _17593_ (.A1(\soc.core.VexRiscv.IBusCachedPlugin_cache.io_cpu_decode_isValid ),
+ .A2(\soc.core.VexRiscv.IBusCachedPlugin_cache.decodeStage_hit_valid ),
+ .ZN(_05782_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_4 _17594_ (.A1(_05781_),
+ .A2(_05782_),
+ .ZN(_05783_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_4 _17595_ (.A1(\soc.core.VexRiscv.IBusCachedPlugin_cache.io_cpu_decode_isValid ),
+ .A2(\soc.core.VexRiscv.IBusCachedPlugin_cache.io_cpu_fetch_isValid ),
+ .ZN(_05784_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_4 _17596_ (.A1(\soc.core.VexRiscv.memory_arbitration_isValid ),
+ .A2(\soc.core.VexRiscv.lastStageIsFiring ),
+ .ZN(_05785_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _17597_ (.A1(_04996_),
+ .A2(_05255_),
+ .ZN(_05786_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _17598_ (.A1(_05783_),
+ .A2(net1791),
+ .ZN(_05787_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand3_4 _17599_ (.A1(_05784_),
+ .A2(_05785_),
+ .A3(_05787_),
+ .ZN(_00129_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_4 _17600_ (.A1(net1659),
+ .A2(_05240_),
+ .ZN(_05788_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_4 _17601_ (.A1(net1773),
+ .A2(\soc.core.VexRiscv.CsrPlugin_selfException_payload_badAddr[12] ),
+ .ZN(_05789_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _17602_ (.A1(net1774),
+ .A2(\soc.core.VexRiscv.CsrPlugin_selfException_payload_badAddr[12] ),
+ .ZN(_05790_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__xor2_2 _17603_ (.A1(net1774),
+ .A2(_05240_),
+ .Z(_05791_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_4 _17604_ (.A1(_05217_),
+ .A2(net1765),
+ .ZN(_05792_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_4 _17605_ (.A1(_05218_),
+ .A2(net1766),
+ .ZN(_05793_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand3_4 _17606_ (.A1(_05218_),
+ .A2(\soc.core.VexRiscv.CsrPlugin_selfException_payload_badAddr[20] ),
+ .A3(net1766),
+ .ZN(_05794_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_4 _17607_ (.A1(net1766),
+ .A2(net1765),
+ .ZN(_05795_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__or2_4 _17608_ (.A1(net1766),
+ .A2(net1765),
+ .Z(_05796_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _17609_ (.A1(net1758),
+ .A2(net1624),
+ .ZN(_05797_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_4 _17610_ (.A1(_05218_),
+ .A2(net1766),
+ .ZN(_05798_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_4 _17611_ (.A1(_05217_),
+ .A2(net1765),
+ .ZN(_05799_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand3_4 _17612_ (.A1(_05217_),
+ .A2(net1765),
+ .A3(\soc.core.VexRiscv.CsrPlugin_selfException_payload_badAddr[7] ),
+ .ZN(_05800_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__and3_4 _17613_ (.A1(_05794_),
+ .A2(_05797_),
+ .A3(_05800_),
+ .Z(_05801_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _17614_ (.A1(_05219_),
+ .A2(_05793_),
+ .B(_05797_),
+ .C(_05800_),
+ .ZN(_05802_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__and2_4 _17615_ (.A1(\soc.core.VexRiscv._zz_execute_SRC1_CTRL[1] ),
+ .A2(\soc.core.VexRiscv._zz_execute_SRC1_CTRL[0] ),
+ .Z(_05803_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _17616_ (.A1(\soc.core.VexRiscv.CsrPlugin_selfException_payload_badAddr[15] ),
+ .A2(_05803_),
+ .ZN(_05804_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_4 _17617_ (.A1(\soc.core.VexRiscv._zz_execute_SRC1_CTRL[1] ),
+ .A2(\soc.core.VexRiscv._zz_execute_SRC1_CTRL[0] ),
+ .ZN(_05805_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_4 _17618_ (.A1(_05241_),
+ .A2(_05242_),
+ .ZN(_05806_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _17619_ (.A1(\soc.core.VexRiscv.decode_to_execute_RS1[0] ),
+ .A2(net1622),
+ .ZN(_05807_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__and2_4 _17620_ (.A1(_05804_),
+ .A2(_05807_),
+ .Z(_05808_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_4 _17621_ (.A1(_05804_),
+ .A2(_05807_),
+ .ZN(_05809_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_4 _17622_ (.A1(_05801_),
+ .A2(_05808_),
+ .ZN(_05810_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__xor2_2 _17623_ (.A1(_05802_),
+ .A2(_05809_),
+ .Z(_05811_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _17624_ (.I0(_05811_),
+ .I1(_05809_),
+ .S(net1750),
+ .Z(_05812_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _17625_ (.A1(\soc.core.VexRiscv.CsrPlugin_selfException_payload_badAddr[16] ),
+ .A2(_05803_),
+ .ZN(_05813_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _17626_ (.A1(\soc.core.VexRiscv.decode_to_execute_RS1[1] ),
+ .A2(net1622),
+ .ZN(_05814_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi22_4 _17627_ (.A1(\soc.core.VexRiscv.CsrPlugin_selfException_payload_badAddr[16] ),
+ .A2(_05803_),
+ .B1(net1622),
+ .B2(\soc.core.VexRiscv.decode_to_execute_RS1[1] ),
+ .ZN(_05815_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_4 _17628_ (.A1(_05813_),
+ .A2(_05814_),
+ .ZN(_05816_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _17629_ (.A1(net1658),
+ .A2(_05802_),
+ .ZN(_05817_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _17630_ (.I0(net1769),
+ .I1(_05809_),
+ .S(_05802_),
+ .Z(_05818_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand3_4 _17631_ (.A1(_05218_),
+ .A2(\soc.core.VexRiscv.CsrPlugin_selfException_payload_badAddr[21] ),
+ .A3(net1766),
+ .ZN(_05819_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand3_4 _17632_ (.A1(_05217_),
+ .A2(_05218_),
+ .A3(\soc.core.VexRiscv._zz_dBus_cmd_payload_data[1] ),
+ .ZN(_05820_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand3_4 _17633_ (.A1(_05217_),
+ .A2(\soc.core.VexRiscv._zz_execute_SRC2_CTRL[1] ),
+ .A3(\soc.core.VexRiscv.CsrPlugin_selfException_payload_badAddr[8] ),
+ .ZN(_05821_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__and3_4 _17634_ (.A1(_05819_),
+ .A2(_05820_),
+ .A3(_05821_),
+ .Z(_05822_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _17635_ (.A1(_05246_),
+ .A2(_05793_),
+ .B(_05820_),
+ .C(_05821_),
+ .ZN(_05823_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_4 _17636_ (.A1(net1769),
+ .A2(_05822_),
+ .ZN(_05824_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _17637_ (.A1(net1658),
+ .A2(_05823_),
+ .ZN(_05825_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _17638_ (.A1(_05816_),
+ .A2(net1750),
+ .ZN(_05826_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _17639_ (.A1(_05824_),
+ .A2(_05825_),
+ .B(_05816_),
+ .ZN(_05827_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _17640_ (.A1(net1658),
+ .A2(_05823_),
+ .B(_05815_),
+ .ZN(_05828_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__or2_4 _17641_ (.A1(_05828_),
+ .A2(_05824_),
+ .Z(_05829_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai22_4 _17642_ (.A1(_05810_),
+ .A2(_05817_),
+ .B1(_05828_),
+ .B2(_05824_),
+ .ZN(_05830_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__and3_4 _17643_ (.A1(_05818_),
+ .A2(_05827_),
+ .A3(_05829_),
+ .Z(_05831_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi21_4 _17644_ (.A1(_05827_),
+ .A2(_05829_),
+ .B(_05818_),
+ .ZN(_05832_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai31_4 _17645_ (.A1(net1750),
+ .A2(_05831_),
+ .A3(_05832_),
+ .B(_05826_),
+ .ZN(_05833_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi21_4 _17646_ (.A1(net1773),
+ .A2(net941),
+ .B(_05812_),
+ .ZN(_05834_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _17647_ (.A1(_05834_),
+ .A2(_05791_),
+ .ZN(_05835_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _17648_ (.A1(net1790),
+ .A2(\soc.core.VexRiscv.decode_to_execute_MEMORY_ENABLE ),
+ .ZN(_05836_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _17649_ (.I(_05836_),
+ .ZN(_05837_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _17650_ (.A1(_05835_),
+ .A2(_05836_),
+ .ZN(_05838_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _17651_ (.A1(_05834_),
+ .A2(_05791_),
+ .B(net1785),
+ .C(_05837_),
+ .ZN(_05839_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__and2_4 _17652_ (.A1(net1766),
+ .A2(net1765),
+ .Z(_05840_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_4 _17653_ (.A1(net1766),
+ .A2(net1765),
+ .ZN(_05841_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_4 _17654_ (.A1(net1620),
+ .A2(\soc.core.VexRiscv._zz_execute_SRC2[2] ),
+ .ZN(_05842_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _17655_ (.A1(\soc.core.VexRiscv._zz_execute_SRC2_CTRL[0] ),
+ .A2(\soc.core.VexRiscv.CsrPlugin_selfException_payload_badAddr[9] ),
+ .B(net1765),
+ .ZN(_05843_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _17656_ (.I(_05843_),
+ .ZN(_05844_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand3_4 _17657_ (.A1(_05217_),
+ .A2(_05218_),
+ .A3(\soc.core.VexRiscv._zz_dBus_cmd_payload_data[2] ),
+ .ZN(_05845_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand3_4 _17658_ (.A1(_05218_),
+ .A2(\soc.core.VexRiscv.CsrPlugin_selfException_payload_badAddr[22] ),
+ .A3(net1766),
+ .ZN(_05846_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _17659_ (.A1(_05845_),
+ .A2(_05846_),
+ .ZN(_05847_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__and3_4 _17660_ (.A1(_05843_),
+ .A2(_05845_),
+ .A3(_05846_),
+ .Z(_05848_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__or2_4 _17661_ (.A1(_05842_),
+ .A2(_05848_),
+ .Z(_05849_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_2 _17662_ (.I(_05849_),
+ .ZN(_05850_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _17663_ (.I0(_05850_),
+ .I1(\soc.core.VexRiscv.execute_LightShifterPlugin_amplitudeReg[2] ),
+ .S(net1759),
+ .Z(_05851_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi21_4 _17664_ (.A1(_05217_),
+ .A2(_05253_),
+ .B(_05218_),
+ .ZN(_05852_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__and3_4 _17665_ (.A1(_05217_),
+ .A2(_05218_),
+ .A3(net1757),
+ .Z(_05853_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__and3_4 _17666_ (.A1(_05218_),
+ .A2(\soc.core.VexRiscv.CsrPlugin_selfException_payload_badAddr[23] ),
+ .A3(\soc.core.VexRiscv._zz_execute_SRC2_CTRL[0] ),
+ .Z(_05854_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai33_4 _17667_ (.A1(_05852_),
+ .A2(_05853_),
+ .A3(_05854_),
+ .B1(\soc.core.VexRiscv._zz_execute_SRC2[3] ),
+ .B2(_05218_),
+ .B3(_05217_),
+ .ZN(_05855_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _17668_ (.A1(_04967_),
+ .A2(\soc.core.VexRiscv.execute_LightShifterPlugin_amplitudeReg[3] ),
+ .ZN(_05856_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi21_4 _17669_ (.A1(_04967_),
+ .A2(net1423),
+ .B(_05856_),
+ .ZN(_05857_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _17670_ (.A1(_05851_),
+ .A2(_05857_),
+ .ZN(_05858_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_4 _17671_ (.A1(net1621),
+ .A2(_05248_),
+ .ZN(_05859_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__and3_4 _17672_ (.A1(_05218_),
+ .A2(\soc.core.VexRiscv.CsrPlugin_selfException_payload_badAddr[24] ),
+ .A3(\soc.core.VexRiscv._zz_execute_SRC2_CTRL[0] ),
+ .Z(_05860_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _17673_ (.A1(\soc.core.VexRiscv._zz_execute_SRC2_CTRL[0] ),
+ .A2(\soc.core.VexRiscv.CsrPlugin_selfException_payload_badAddr[11] ),
+ .B(\soc.core.VexRiscv._zz_execute_SRC2_CTRL[1] ),
+ .ZN(_05861_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai31_4 _17674_ (.A1(\soc.core.VexRiscv._zz_execute_SRC2_CTRL[0] ),
+ .A2(\soc.core.VexRiscv._zz_execute_SRC2_CTRL[1] ),
+ .A3(_05249_),
+ .B(_05861_),
+ .ZN(_05862_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _17675_ (.A1(_05862_),
+ .A2(_05860_),
+ .B(_05859_),
+ .ZN(_05863_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _17676_ (.I(_05863_),
+ .ZN(_05864_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _17677_ (.I0(_05864_),
+ .I1(\soc.core.VexRiscv.execute_LightShifterPlugin_amplitudeReg[4] ),
+ .S(net1759),
+ .Z(_05865_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _17678_ (.I0(_05823_),
+ .I1(\soc.core.VexRiscv.execute_LightShifterPlugin_amplitudeReg[1] ),
+ .S(net1759),
+ .Z(_05866_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_2 _17679_ (.I(_05866_),
+ .ZN(_05867_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _17680_ (.A1(_05865_),
+ .A2(_05866_),
+ .ZN(_05868_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _17681_ (.A1(_05858_),
+ .A2(_05867_),
+ .ZN(_05869_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_4 _17682_ (.A1(_05858_),
+ .A2(_05868_),
+ .ZN(_05870_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__and3_4 _17683_ (.A1(_05863_),
+ .A2(_05822_),
+ .A3(_05801_),
+ .Z(_05871_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _17684_ (.A1(_05842_),
+ .A2(_05848_),
+ .B(_05871_),
+ .C(net1422),
+ .ZN(_05872_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _17685_ (.A1(\soc.core.VexRiscv._zz_execute_SHIFT_CTRL[1] ),
+ .A2(\soc.core.VexRiscv._zz_execute_SHIFT_CTRL[0] ),
+ .ZN(_05873_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _17686_ (.A1(_05872_),
+ .A2(net1791),
+ .ZN(_05874_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_4 _17687_ (.A1(_05874_),
+ .A2(_05873_),
+ .ZN(_05875_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _17688_ (.A1(\soc.core.VexRiscv._zz_execute_SHIFT_CTRL[1] ),
+ .A2(\soc.core.VexRiscv._zz_execute_SHIFT_CTRL[0] ),
+ .B(_05872_),
+ .C(net1791),
+ .ZN(_05876_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__and2_4 _17689_ (.A1(net1790),
+ .A2(\soc.core.VexRiscv.decode_to_execute_IS_CSR ),
+ .Z(_05877_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_4 _17690_ (.A1(net1790),
+ .A2(\soc.core.VexRiscv.decode_to_execute_IS_CSR ),
+ .ZN(_05878_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi22_4 _17691_ (.A1(_05870_),
+ .A2(net939),
+ .B1(net1619),
+ .B2(_05786_),
+ .ZN(_05879_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__and2_4 _17692_ (.A1(net1791),
+ .A2(\soc.core.VexRiscv.decode_to_execute_DO_EBREAK ),
+ .Z(_05880_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_4 _17693_ (.A1(net1791),
+ .A2(\soc.core.VexRiscv.decode_to_execute_DO_EBREAK ),
+ .ZN(_05881_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _17694_ (.A1(_04971_),
+ .A2(\soc.core.VexRiscv.dBusWishbone_WE ),
+ .ZN(_05882_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _17695_ (.A1(\soc.core.count[10] ),
+ .A2(\soc.core.count[9] ),
+ .ZN(_05883_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand3_4 _17696_ (.A1(_05883_),
+ .A2(_05013_),
+ .A3(_05012_),
+ .ZN(_05884_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _17697_ (.A1(_05884_),
+ .A2(\soc.core.count[11] ),
+ .ZN(_05885_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _17698_ (.A1(\soc.core.count[2] ),
+ .A2(\soc.core.count[1] ),
+ .ZN(_05886_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _17699_ (.A1(\soc.core.count[4] ),
+ .A2(\soc.core.count[3] ),
+ .ZN(_05887_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _17700_ (.A1(_05887_),
+ .A2(_05014_),
+ .ZN(_05888_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _17701_ (.A1(\soc.core.count[6] ),
+ .A2(\soc.core.count[0] ),
+ .ZN(_05889_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _17702_ (.A1(_05886_),
+ .A2(_05889_),
+ .ZN(_05890_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _17703_ (.A1(_05888_),
+ .A2(_05890_),
+ .ZN(_05891_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__or2_4 _17704_ (.A1(_05888_),
+ .A2(_05890_),
+ .Z(_05892_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _17705_ (.A1(\soc.core.count[13] ),
+ .A2(\soc.core.count[12] ),
+ .ZN(_05893_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _17706_ (.A1(\soc.core.count[9] ),
+ .A2(\soc.core.count[8] ),
+ .ZN(_05894_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _17707_ (.A1(_05892_),
+ .A2(\soc.core.count[7] ),
+ .ZN(_05895_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__and3_4 _17708_ (.A1(_05895_),
+ .A2(_05011_),
+ .A3(_05894_),
+ .Z(_05896_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _17709_ (.A1(\soc.core.count[12] ),
+ .A2(\soc.core.count[11] ),
+ .ZN(_05897_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__and3_4 _17710_ (.A1(_05885_),
+ .A2(_05891_),
+ .A3(_05893_),
+ .Z(_05898_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__and2_4 _17711_ (.A1(_05898_),
+ .A2(_05010_),
+ .Z(_05899_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__and3_4 _17712_ (.A1(_05898_),
+ .A2(_05010_),
+ .A3(_05009_),
+ .Z(_05900_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_4 _17713_ (.A1(_05900_),
+ .A2(_05008_),
+ .ZN(_05901_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _17714_ (.A1(\soc.core.count[19] ),
+ .A2(\soc.core.count[18] ),
+ .ZN(_05902_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_2 _17715_ (.I(_05902_),
+ .ZN(_05903_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_4 _17716_ (.A1(_05903_),
+ .A2(\soc.core.count[17] ),
+ .ZN(_05904_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_4 _17717_ (.A1(_05901_),
+ .A2(\soc.core.count[17] ),
+ .ZN(_05905_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_4 _17718_ (.A1(_05905_),
+ .A2(_05007_),
+ .ZN(_05906_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_4 _17719_ (.A1(_05906_),
+ .A2(\soc.core.count[19] ),
+ .ZN(_05907_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand3_4 _17720_ (.A1(_05900_),
+ .A2(_05904_),
+ .A3(_05008_),
+ .ZN(_05908_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_4 _17721_ (.A1(\soc.core.litespiphy_state[1] ),
+ .A2(\soc.core.litespiphy_state[0] ),
+ .ZN(_05909_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_4 _17722_ (.A1(_05909_),
+ .A2(net1831),
+ .ZN(_05910_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _17723_ (.A1(\soc.core.litespi_state[1] ),
+ .A2(\soc.core.litespi_state[0] ),
+ .ZN(_05911_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _17724_ (.A1(\soc.core.litespi_state[2] ),
+ .A2(\soc.core.litespi_state[1] ),
+ .ZN(_05912_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _17725_ (.I(_05912_),
+ .ZN(_05913_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _17726_ (.A1(_05913_),
+ .A2(\soc.core.litespi_state[0] ),
+ .ZN(_05914_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__and3_4 _17727_ (.A1(\soc.core.litespi_state[3] ),
+ .A2(_05911_),
+ .A3(_05023_),
+ .Z(_05915_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__and3_4 _17728_ (.A1(\soc.core.litespi_state[3] ),
+ .A2(_05910_),
+ .A3(_05914_),
+ .Z(_05916_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_4 _17729_ (.A1(_05910_),
+ .A2(_05915_),
+ .ZN(_05917_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _17730_ (.A1(\soc.core.mgmtsoc_vexriscv_debug_bus_ack ),
+ .A2(\soc.core.state ),
+ .ZN(_05918_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _17731_ (.A1(_05236_),
+ .A2(\mgmt_buffers.mprj_ack_i_core_bar ),
+ .ZN(_05919_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _17732_ (.A1(_05919_),
+ .A2(net1714),
+ .ZN(_05920_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__and3_4 _17733_ (.A1(net1419),
+ .A2(_05918_),
+ .A3(_05920_),
+ .Z(_05921_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_4 _17734_ (.A1(net979),
+ .A2(_05921_),
+ .ZN(_05922_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_1 _17735_ (.I(_05922_),
+ .ZN(_05923_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi21_4 _17736_ (.A1(net978),
+ .A2(_05921_),
+ .B(net1585),
+ .ZN(_05924_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_4 _17737_ (.A1(_05922_),
+ .A2(net1587),
+ .ZN(_05925_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _17738_ (.A1(\soc.core.VexRiscv.memory_arbitration_isValid ),
+ .A2(\soc.core.VexRiscv.execute_to_memory_MEMORY_ENABLE ),
+ .ZN(_05926_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _17739_ (.A1(_05926_),
+ .A2(\soc.core.VexRiscv.execute_to_memory_INSTRUCTION[5] ),
+ .ZN(_05927_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi211_4 _17740_ (.A1(_05882_),
+ .A2(_05924_),
+ .B(_05926_),
+ .C(\soc.core.VexRiscv.execute_to_memory_INSTRUCTION[5] ),
+ .ZN(_05928_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai31_4 _17741_ (.A1(_04971_),
+ .A2(_05925_),
+ .A3(\soc.core.VexRiscv.dBusWishbone_WE ),
+ .B(_05927_),
+ .ZN(_05929_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_4 _17742_ (.A1(net1617),
+ .A2(net883),
+ .ZN(_05930_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _17743_ (.A1(net1616),
+ .A2(_05929_),
+ .ZN(_05931_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__and3_4 _17744_ (.A1(_05839_),
+ .A2(_05879_),
+ .A3(_05930_),
+ .Z(_05932_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand3_4 _17745_ (.A1(_05839_),
+ .A2(_05879_),
+ .A3(_05930_),
+ .ZN(_05933_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_4 _17746_ (.A1(\soc.core.VexRiscv.DebugPlugin_stepIt ),
+ .A2(\soc.core.VexRiscv.DebugPlugin_haltIt ),
+ .ZN(_05934_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__and3_4 _17747_ (.A1(_05783_),
+ .A2(_05934_),
+ .A3(\soc.core.VexRiscv.CsrPlugin_interrupt_valid ),
+ .Z(_05935_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _17748_ (.A1(\soc.core.VexRiscv.lastStageIsFiring ),
+ .A2(\soc.core.VexRiscv._zz_writeBack_ENV_CTRL[0] ),
+ .ZN(_05936_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_4 _17749_ (.A1(_05936_),
+ .A2(\soc.core.VexRiscv._zz_writeBack_ENV_CTRL[1] ),
+ .ZN(_05937_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_2 _17750_ (.I(_05937_),
+ .ZN(_05938_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _17751_ (.A1(_04996_),
+ .A2(\soc.core.VexRiscv._zz_memory_ENV_CTRL[1] ),
+ .ZN(_05939_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _17752_ (.A1(_04995_),
+ .A2(\soc.core.VexRiscv._zz_execute_ENV_CTRL[1] ),
+ .ZN(_05940_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi221_4 _17753_ (.A1(\soc.core.VexRiscv._zz_memory_ENV_CTRL[0] ),
+ .A2(_05939_),
+ .B1(_05940_),
+ .B2(\soc.core.VexRiscv._zz_execute_ENV_CTRL[0] ),
+ .C(_05935_),
+ .ZN(_05941_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _17754_ (.A1(\soc.core.VexRiscv.IBusCachedPlugin_cache._zz_when_Fetcher_l398[0] ),
+ .A2(_05781_),
+ .B(_05941_),
+ .C(_05938_),
+ .ZN(_05942_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_4 _17755_ (.A1(\soc.core.VexRiscv.IBusCachedPlugin_cache.io_cpu_decode_data[3] ),
+ .A2(\soc.core.VexRiscv.IBusCachedPlugin_cache.io_cpu_decode_data[4] ),
+ .ZN(_05943_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _17756_ (.A1(_05260_),
+ .A2(_05261_),
+ .ZN(_05944_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_4 _17757_ (.A1(\soc.core.VexRiscv.IBusCachedPlugin_cache.io_cpu_decode_data[12] ),
+ .A2(net1808),
+ .ZN(_05945_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_1 _17758_ (.I(_05945_),
+ .ZN(_05946_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _17759_ (.A1(net1809),
+ .A2(_05945_),
+ .ZN(_05947_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _17760_ (.A1(\soc.core.VexRiscv.IBusCachedPlugin_cache.io_cpu_decode_data[14] ),
+ .A2(net1809),
+ .ZN(_05948_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__and3_4 _17761_ (.A1(_05256_),
+ .A2(_05947_),
+ .A3(_05948_),
+ .Z(_05949_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__xor2_1 _17762_ (.A1(\soc.core.VexRiscv.IBusCachedPlugin_cache.io_cpu_decode_data[15] ),
+ .A2(\soc.core.VexRiscv.execute_to_memory_INSTRUCTION[7] ),
+ .Z(_05950_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi21_4 _17763_ (.A1(_05266_),
+ .A2(\soc.core.VexRiscv.execute_to_memory_INSTRUCTION[8] ),
+ .B(_05950_),
+ .ZN(_05951_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai22_4 _17764_ (.A1(_05266_),
+ .A2(\soc.core.VexRiscv.execute_to_memory_INSTRUCTION[8] ),
+ .B1(_05269_),
+ .B2(\soc.core.VexRiscv.execute_to_memory_INSTRUCTION[10] ),
+ .ZN(_05952_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi221_4 _17765_ (.A1(_05268_),
+ .A2(\soc.core.VexRiscv.execute_to_memory_INSTRUCTION[9] ),
+ .B1(\soc.core.VexRiscv.execute_to_memory_INSTRUCTION[10] ),
+ .B2(_05269_),
+ .C(_05952_),
+ .ZN(_05953_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__xor2_1 _17766_ (.A1(\soc.core.VexRiscv.IBusCachedPlugin_cache.io_cpu_decode_data[19] ),
+ .A2(\soc.core.VexRiscv.execute_to_memory_INSTRUCTION[11] ),
+ .Z(_05954_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _17767_ (.A1(_05268_),
+ .A2(\soc.core.VexRiscv.execute_to_memory_INSTRUCTION[9] ),
+ .B(\soc.core.VexRiscv.execute_to_memory_REGFILE_WRITE_VALID ),
+ .C(\soc.core.VexRiscv.memory_arbitration_isValid ),
+ .ZN(_05955_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _17768_ (.A1(_05954_),
+ .A2(_05955_),
+ .ZN(_05956_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand3_4 _17769_ (.A1(_05951_),
+ .A2(_05953_),
+ .A3(_05956_),
+ .ZN(_05957_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__xor2_1 _17770_ (.A1(\soc.core.VexRiscv.HazardSimplePlugin_writeBackBuffer_payload_address[3] ),
+ .A2(_05269_),
+ .Z(_05958_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__xnor2_1 _17771_ (.A1(\soc.core.VexRiscv.HazardSimplePlugin_writeBackBuffer_payload_address[4] ),
+ .A2(\soc.core.VexRiscv.IBusCachedPlugin_cache.io_cpu_decode_data[19] ),
+ .ZN(_05959_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _17772_ (.A1(\soc.core.VexRiscv.HazardSimplePlugin_writeBackBuffer_payload_address[0] ),
+ .A2(_05264_),
+ .B(_05959_),
+ .C(\soc.core.VexRiscv.HazardSimplePlugin_writeBackBuffer_valid ),
+ .ZN(_05960_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai222_4 _17773_ (.A1(_05263_),
+ .A2(\soc.core.VexRiscv.IBusCachedPlugin_cache.io_cpu_decode_data[15] ),
+ .B1(_05265_),
+ .B2(\soc.core.VexRiscv.IBusCachedPlugin_cache.io_cpu_decode_data[16] ),
+ .C1(\soc.core.VexRiscv.HazardSimplePlugin_writeBackBuffer_payload_address[2] ),
+ .C2(_05268_),
+ .ZN(_05961_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _17774_ (.A1(\soc.core.VexRiscv.HazardSimplePlugin_writeBackBuffer_payload_address[1] ),
+ .A2(_05266_),
+ .B1(_05267_),
+ .B2(\soc.core.VexRiscv.IBusCachedPlugin_cache.io_cpu_decode_data[17] ),
+ .C(_05958_),
+ .ZN(_05962_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai31_4 _17775_ (.A1(_05960_),
+ .A2(_05961_),
+ .A3(_05962_),
+ .B(_05957_),
+ .ZN(_05963_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__xor2_1 _17776_ (.A1(\soc.core.VexRiscv.IBusCachedPlugin_cache.io_cpu_decode_data[18] ),
+ .A2(\soc.core.VexRiscv.HazardSimplePlugin_writeBackWrites_payload_address[3] ),
+ .Z(_05964_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_4 _17777_ (.A1(\soc.core.VexRiscv.lastStageIsFiring ),
+ .A2(\soc.core.VexRiscv._zz_lastStageRegFileWrite_valid ),
+ .ZN(_05965_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__xnor2_1 _17778_ (.A1(\soc.core.VexRiscv.IBusCachedPlugin_cache.io_cpu_decode_data[19] ),
+ .A2(\soc.core.VexRiscv.HazardSimplePlugin_writeBackWrites_payload_address[4] ),
+ .ZN(_05966_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__xor2_1 _17779_ (.A1(\soc.core.VexRiscv.IBusCachedPlugin_cache.io_cpu_decode_data[16] ),
+ .A2(\soc.core.VexRiscv.HazardSimplePlugin_writeBackWrites_payload_address[1] ),
+ .Z(_05967_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _17780_ (.A1(_05964_),
+ .A2(_05967_),
+ .ZN(_05968_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__xor2_1 _17781_ (.A1(\soc.core.VexRiscv.IBusCachedPlugin_cache.io_cpu_decode_data[15] ),
+ .A2(\soc.core.VexRiscv.HazardSimplePlugin_writeBackWrites_payload_address[0] ),
+ .Z(_05969_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _17782_ (.A1(_05271_),
+ .A2(\soc.core.VexRiscv.IBusCachedPlugin_cache.io_cpu_decode_data[17] ),
+ .B(\soc.core.VexRiscv.lastStageIsFiring ),
+ .C(\soc.core.VexRiscv._zz_lastStageRegFileWrite_valid ),
+ .ZN(_05970_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi211_4 _17783_ (.A1(\soc.core.VexRiscv.IBusCachedPlugin_cache.io_cpu_decode_data[17] ),
+ .A2(_05271_),
+ .B(_05969_),
+ .C(_05970_),
+ .ZN(_05971_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__and3_4 _17784_ (.A1(_05971_),
+ .A2(_05966_),
+ .A3(_05968_),
+ .Z(_05972_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__xnor2_1 _17785_ (.A1(\soc.core.VexRiscv.CsrPlugin_selfException_payload_badAddr[11] ),
+ .A2(\soc.core.VexRiscv.IBusCachedPlugin_cache.io_cpu_decode_data[19] ),
+ .ZN(_05973_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__xor2_1 _17786_ (.A1(\soc.core.VexRiscv.CsrPlugin_selfException_payload_badAddr[7] ),
+ .A2(\soc.core.VexRiscv.IBusCachedPlugin_cache.io_cpu_decode_data[15] ),
+ .Z(_05974_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi221_4 _17787_ (.A1(_05245_),
+ .A2(\soc.core.VexRiscv.IBusCachedPlugin_cache.io_cpu_decode_data[16] ),
+ .B1(\soc.core.VexRiscv.IBusCachedPlugin_cache.io_cpu_decode_data[18] ),
+ .B2(_05253_),
+ .C(_05974_),
+ .ZN(_05975_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai222_4 _17788_ (.A1(_05245_),
+ .A2(\soc.core.VexRiscv.IBusCachedPlugin_cache.io_cpu_decode_data[16] ),
+ .B1(\soc.core.VexRiscv.IBusCachedPlugin_cache.io_cpu_decode_data[17] ),
+ .B2(_05251_),
+ .C1(\soc.core.VexRiscv.IBusCachedPlugin_cache.io_cpu_decode_data[18] ),
+ .C2(_05253_),
+ .ZN(_05976_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _17789_ (.A1(_05268_),
+ .A2(\soc.core.VexRiscv.CsrPlugin_selfException_payload_badAddr[9] ),
+ .B(net1791),
+ .C(\soc.core.VexRiscv.decode_to_execute_REGFILE_WRITE_VALID ),
+ .ZN(_05977_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _17790_ (.A1(_05976_),
+ .A2(_05977_),
+ .ZN(_05978_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__and3_4 _17791_ (.A1(_05975_),
+ .A2(_05978_),
+ .A3(_05973_),
+ .Z(_05979_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai32_4 _17792_ (.A1(_05963_),
+ .A2(_05972_),
+ .A3(_05979_),
+ .B1(_05949_),
+ .B2(_05943_),
+ .ZN(_05980_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__xor2_1 _17793_ (.A1(\soc.core.VexRiscv.HazardSimplePlugin_writeBackBuffer_payload_address[3] ),
+ .A2(\soc.core.VexRiscv.IBusCachedPlugin_cache.io_cpu_decode_data[23] ),
+ .Z(_05981_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi221_4 _17794_ (.A1(_05263_),
+ .A2(\soc.core.VexRiscv.IBusCachedPlugin_cache.io_cpu_decode_data[20] ),
+ .B1(\soc.core.VexRiscv.IBusCachedPlugin_cache.io_cpu_decode_data[21] ),
+ .B2(_05265_),
+ .C(_05981_),
+ .ZN(_05982_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi222_4 _17795_ (.A1(\soc.core.VexRiscv.HazardSimplePlugin_writeBackBuffer_payload_address[0] ),
+ .A2(_05275_),
+ .B1(\soc.core.VexRiscv.IBusCachedPlugin_cache.io_cpu_decode_data[22] ),
+ .B2(_05267_),
+ .C1(_05276_),
+ .C2(\soc.core.VexRiscv.HazardSimplePlugin_writeBackBuffer_payload_address[1] ),
+ .ZN(_05983_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__xnor2_1 _17796_ (.A1(\soc.core.VexRiscv.HazardSimplePlugin_writeBackBuffer_payload_address[4] ),
+ .A2(\soc.core.VexRiscv.IBusCachedPlugin_cache.io_cpu_decode_data[24] ),
+ .ZN(_05984_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__and3_4 _17797_ (.A1(_05982_),
+ .A2(_05983_),
+ .A3(_05984_),
+ .Z(_05985_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _17798_ (.A1(_05267_),
+ .A2(\soc.core.VexRiscv.IBusCachedPlugin_cache.io_cpu_decode_data[22] ),
+ .B(_05985_),
+ .C(\soc.core.VexRiscv.HazardSimplePlugin_writeBackBuffer_valid ),
+ .ZN(_05986_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi222_4 _17799_ (.A1(\soc.core.VexRiscv.execute_to_memory_INSTRUCTION[7] ),
+ .A2(_05275_),
+ .B1(_05277_),
+ .B2(\soc.core.VexRiscv.execute_to_memory_INSTRUCTION[9] ),
+ .C1(_05278_),
+ .C2(\soc.core.VexRiscv.execute_to_memory_INSTRUCTION[10] ),
+ .ZN(_05987_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__xor2_1 _17800_ (.A1(\soc.core.VexRiscv.execute_to_memory_INSTRUCTION[8] ),
+ .A2(\soc.core.VexRiscv.IBusCachedPlugin_cache.io_cpu_decode_data[21] ),
+ .Z(_05988_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai22_4 _17801_ (.A1(\soc.core.VexRiscv.execute_to_memory_INSTRUCTION[7] ),
+ .A2(_05275_),
+ .B1(_05278_),
+ .B2(\soc.core.VexRiscv.execute_to_memory_INSTRUCTION[10] ),
+ .ZN(_05989_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _17802_ (.A1(_05988_),
+ .A2(_05989_),
+ .ZN(_05990_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _17803_ (.A1(_05273_),
+ .A2(\soc.core.VexRiscv.IBusCachedPlugin_cache.io_cpu_decode_data[24] ),
+ .B(\soc.core.VexRiscv.memory_arbitration_isValid ),
+ .C(\soc.core.VexRiscv.execute_to_memory_REGFILE_WRITE_VALID ),
+ .ZN(_05991_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi221_4 _17804_ (.A1(_05272_),
+ .A2(\soc.core.VexRiscv.IBusCachedPlugin_cache.io_cpu_decode_data[22] ),
+ .B1(\soc.core.VexRiscv.IBusCachedPlugin_cache.io_cpu_decode_data[24] ),
+ .B2(_05273_),
+ .C(_05991_),
+ .ZN(_05992_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand3_4 _17805_ (.A1(_05987_),
+ .A2(_05990_),
+ .A3(_05992_),
+ .ZN(_05993_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__xor2_1 _17806_ (.A1(\soc.core.VexRiscv.HazardSimplePlugin_writeBackWrites_payload_address[1] ),
+ .A2(_05276_),
+ .Z(_05994_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__xnor2_1 _17807_ (.A1(\soc.core.VexRiscv.HazardSimplePlugin_writeBackWrites_payload_address[4] ),
+ .A2(\soc.core.VexRiscv.IBusCachedPlugin_cache.io_cpu_decode_data[24] ),
+ .ZN(_05995_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__xor2_1 _17808_ (.A1(\soc.core.VexRiscv.HazardSimplePlugin_writeBackWrites_payload_address[3] ),
+ .A2(_05278_),
+ .Z(_05996_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__and3_4 _17809_ (.A1(_05994_),
+ .A2(_05996_),
+ .A3(_05995_),
+ .Z(_05997_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__xor2_1 _17810_ (.A1(\soc.core.VexRiscv.HazardSimplePlugin_writeBackWrites_payload_address[0] ),
+ .A2(\soc.core.VexRiscv.IBusCachedPlugin_cache.io_cpu_decode_data[20] ),
+ .Z(_05998_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _17811_ (.A1(_05271_),
+ .A2(\soc.core.VexRiscv.IBusCachedPlugin_cache.io_cpu_decode_data[22] ),
+ .B(\soc.core.VexRiscv.lastStageIsFiring ),
+ .C(\soc.core.VexRiscv._zz_lastStageRegFileWrite_valid ),
+ .ZN(_05999_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi211_4 _17812_ (.A1(_05271_),
+ .A2(\soc.core.VexRiscv.IBusCachedPlugin_cache.io_cpu_decode_data[22] ),
+ .B(_05998_),
+ .C(_05999_),
+ .ZN(_06000_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__xor2_1 _17813_ (.A1(\soc.core.VexRiscv.CsrPlugin_selfException_payload_badAddr[7] ),
+ .A2(\soc.core.VexRiscv.IBusCachedPlugin_cache.io_cpu_decode_data[20] ),
+ .Z(_06001_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__xor2_1 _17814_ (.A1(\soc.core.VexRiscv.CsrPlugin_selfException_payload_badAddr[8] ),
+ .A2(\soc.core.VexRiscv.IBusCachedPlugin_cache.io_cpu_decode_data[21] ),
+ .Z(_06002_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi221_4 _17815_ (.A1(_05251_),
+ .A2(\soc.core.VexRiscv.IBusCachedPlugin_cache.io_cpu_decode_data[22] ),
+ .B1(\soc.core.VexRiscv.IBusCachedPlugin_cache.io_cpu_decode_data[23] ),
+ .B2(_05253_),
+ .C(_06002_),
+ .ZN(_06003_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__xnor2_1 _17816_ (.A1(\soc.core.VexRiscv.CsrPlugin_selfException_payload_badAddr[11] ),
+ .A2(\soc.core.VexRiscv.IBusCachedPlugin_cache.io_cpu_decode_data[24] ),
+ .ZN(_06004_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _17817_ (.A1(_05251_),
+ .A2(\soc.core.VexRiscv.IBusCachedPlugin_cache.io_cpu_decode_data[22] ),
+ .B(\soc.core.VexRiscv.decode_to_execute_REGFILE_WRITE_VALID ),
+ .C(net1791),
+ .ZN(_06005_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi211_4 _17818_ (.A1(\soc.core.VexRiscv.CsrPlugin_selfException_payload_badAddr[10] ),
+ .A2(_05278_),
+ .B(_06001_),
+ .C(_06005_),
+ .ZN(_06006_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__and3_4 _17819_ (.A1(_06003_),
+ .A2(_06006_),
+ .A3(_06004_),
+ .Z(_06007_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi21_4 _17820_ (.A1(_05997_),
+ .A2(_06000_),
+ .B(_06007_),
+ .ZN(_06008_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__and3_4 _17821_ (.A1(_05986_),
+ .A2(_06008_),
+ .A3(_05993_),
+ .Z(_06009_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_4 _17822_ (.A1(_05256_),
+ .A2(net1810),
+ .ZN(_06010_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_4 _17823_ (.A1(_05261_),
+ .A2(_05262_),
+ .ZN(_06011_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_4 _17824_ (.A1(\soc.core.VexRiscv.IBusCachedPlugin_cache.io_cpu_decode_data[4] ),
+ .A2(net1809),
+ .ZN(_06012_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai31_4 _17825_ (.A1(_06009_),
+ .A2(_06010_),
+ .A3(_06011_),
+ .B(_05980_),
+ .ZN(_06013_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi21_4 _17826_ (.A1(_05783_),
+ .A2(_06013_),
+ .B(_05942_),
+ .ZN(_06014_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_4 _17827_ (.A1(net819),
+ .A2(_06014_),
+ .ZN(_06015_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _17828_ (.I0(\soc.core.VexRiscv.IBusCachedPlugin_cache._zz_banks_0_port1[17] ),
+ .I1(\soc.core.VexRiscv.IBusCachedPlugin_cache.io_cpu_decode_data[17] ),
+ .S(net782),
+ .Z(_06016_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _17829_ (.I0(\soc.core.VexRiscv.IBusCachedPlugin_cache._zz_banks_0_port1[15] ),
+ .I1(\soc.core.VexRiscv.IBusCachedPlugin_cache.io_cpu_decode_data[15] ),
+ .S(net782),
+ .Z(_06017_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _17830_ (.I0(_05330_),
+ .I1(_05264_),
+ .S(net782),
+ .Z(_06018_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _17831_ (.I0(_05331_),
+ .I1(_05266_),
+ .S(net782),
+ .Z(_06019_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _17832_ (.I0(\soc.core.VexRiscv.IBusCachedPlugin_cache._zz_banks_0_port1[16] ),
+ .I1(\soc.core.VexRiscv.IBusCachedPlugin_cache.io_cpu_decode_data[16] ),
+ .S(net782),
+ .Z(_06020_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _17833_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[20][0] ),
+ .A2(net723),
+ .ZN(_06021_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _17834_ (.A1(net702),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[21][0] ),
+ .B(net678),
+ .ZN(_06022_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _17835_ (.A1(net702),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[23][0] ),
+ .ZN(_06023_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _17836_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[22][0] ),
+ .A2(net723),
+ .B(net667),
+ .ZN(_06024_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _17837_ (.A1(_06024_),
+ .A2(_06023_),
+ .B1(_06022_),
+ .B2(_06021_),
+ .C(net740),
+ .ZN(_06025_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _17838_ (.I0(_05332_),
+ .I1(_05269_),
+ .S(net782),
+ .Z(_06026_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _17839_ (.I0(\soc.core.VexRiscv.IBusCachedPlugin_cache._zz_banks_0_port1[18] ),
+ .I1(\soc.core.VexRiscv.IBusCachedPlugin_cache.io_cpu_decode_data[18] ),
+ .S(net782),
+ .Z(_06027_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _17840_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[17][0] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[16][0] ),
+ .S(net702),
+ .Z(_06028_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _17841_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[19][0] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[18][0] ),
+ .S(net702),
+ .Z(_06029_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _17842_ (.I0(_06028_),
+ .I1(_06029_),
+ .S(net667),
+ .Z(_06030_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _17843_ (.A1(_06030_),
+ .A2(net740),
+ .B(_06025_),
+ .C(net652),
+ .ZN(_06031_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _17844_ (.I0(\soc.core.VexRiscv.IBusCachedPlugin_cache._zz_banks_0_port1[19] ),
+ .I1(\soc.core.VexRiscv.IBusCachedPlugin_cache.io_cpu_decode_data[19] ),
+ .S(net782),
+ .Z(_06032_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _17845_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[25][0] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[24][0] ),
+ .S(net702),
+ .Z(_06033_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _17846_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[27][0] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[26][0] ),
+ .S(net702),
+ .Z(_06034_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _17847_ (.I0(_06033_),
+ .I1(_06034_),
+ .S(net667),
+ .Z(_06035_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _17848_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[28][0] ),
+ .A2(net723),
+ .ZN(_06036_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _17849_ (.A1(net702),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[29][0] ),
+ .B(net678),
+ .ZN(_06037_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _17850_ (.A1(net702),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[31][0] ),
+ .ZN(_06038_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _17851_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[30][0] ),
+ .A2(net723),
+ .B(net667),
+ .ZN(_06039_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _17852_ (.A1(_06039_),
+ .A2(_06038_),
+ .B1(_06037_),
+ .B2(_06036_),
+ .C(net740),
+ .ZN(_06040_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _17853_ (.A1(_06035_),
+ .A2(net740),
+ .B(net647),
+ .C(_06040_),
+ .ZN(_06041_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _17854_ (.A1(_06031_),
+ .A2(_06041_),
+ .ZN(_06042_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _17855_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[4][0] ),
+ .A2(net723),
+ .ZN(_06043_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _17856_ (.A1(net702),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[5][0] ),
+ .B(net678),
+ .ZN(_06044_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _17857_ (.A1(net702),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[7][0] ),
+ .ZN(_06045_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _17858_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[6][0] ),
+ .A2(net723),
+ .B(net667),
+ .ZN(_06046_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _17859_ (.A1(_06046_),
+ .A2(_06045_),
+ .B1(_06044_),
+ .B2(_06043_),
+ .C(net740),
+ .ZN(_06047_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _17860_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[1][0] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[0][0] ),
+ .S(net702),
+ .Z(_06048_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _17861_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[3][0] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[2][0] ),
+ .S(net702),
+ .Z(_06049_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _17862_ (.I0(_06048_),
+ .I1(_06049_),
+ .S(net667),
+ .Z(_06050_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _17863_ (.A1(_06050_),
+ .A2(net740),
+ .B(net652),
+ .C(_06047_),
+ .ZN(_06051_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _17864_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[12][0] ),
+ .A2(net723),
+ .ZN(_06052_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _17865_ (.A1(net702),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[13][0] ),
+ .B(net678),
+ .ZN(_06053_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _17866_ (.A1(net702),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[15][0] ),
+ .ZN(_06054_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _17867_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[14][0] ),
+ .A2(net723),
+ .B(net667),
+ .ZN(_06055_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _17868_ (.A1(_06055_),
+ .A2(_06054_),
+ .B1(_06053_),
+ .B2(_06052_),
+ .C(net740),
+ .ZN(_06056_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _17869_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[9][0] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[8][0] ),
+ .S(net702),
+ .Z(_06057_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _17870_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[11][0] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[10][0] ),
+ .S(net702),
+ .Z(_06058_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _17871_ (.I0(_06057_),
+ .I1(_06058_),
+ .S(net667),
+ .Z(_06059_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _17872_ (.A1(_06059_),
+ .A2(net740),
+ .B(net647),
+ .C(_06056_),
+ .ZN(_06060_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _17873_ (.A1(_06051_),
+ .A2(_06060_),
+ .ZN(_06061_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _17874_ (.I0(_06061_),
+ .I1(_06042_),
+ .S(net642),
+ .Z(_00032_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _17875_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[20][1] ),
+ .A2(net721),
+ .ZN(_06062_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _17876_ (.A1(net699),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[21][1] ),
+ .B(net678),
+ .ZN(_06063_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _17877_ (.A1(net699),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[23][1] ),
+ .ZN(_06064_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _17878_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[22][1] ),
+ .A2(net721),
+ .B(net665),
+ .ZN(_06065_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _17879_ (.A1(_06065_),
+ .A2(_06064_),
+ .B1(_06063_),
+ .B2(_06062_),
+ .C(net738),
+ .ZN(_06066_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _17880_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[17][1] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[16][1] ),
+ .S(net701),
+ .Z(_06067_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _17881_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[19][1] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[18][1] ),
+ .S(net701),
+ .Z(_06068_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _17882_ (.I0(_06067_),
+ .I1(_06068_),
+ .S(net666),
+ .Z(_06069_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _17883_ (.A1(_06069_),
+ .A2(net739),
+ .B(net652),
+ .C(_06066_),
+ .ZN(_06070_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _17884_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[25][1] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[24][1] ),
+ .S(net702),
+ .Z(_06071_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _17885_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[27][1] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[26][1] ),
+ .S(net702),
+ .Z(_06072_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _17886_ (.I0(_06071_),
+ .I1(_06072_),
+ .S(net667),
+ .Z(_06073_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _17887_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[28][1] ),
+ .A2(net722),
+ .ZN(_06074_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _17888_ (.A1(net701),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[29][1] ),
+ .B(net681),
+ .ZN(_06075_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _17889_ (.A1(net703),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[31][1] ),
+ .ZN(_06076_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _17890_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[30][1] ),
+ .A2(net723),
+ .B(net667),
+ .ZN(_06077_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _17891_ (.A1(_06077_),
+ .A2(_06076_),
+ .B1(_06075_),
+ .B2(_06074_),
+ .C(net740),
+ .ZN(_06078_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _17892_ (.A1(_06073_),
+ .A2(net740),
+ .B(net649),
+ .C(_06078_),
+ .ZN(_06079_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _17893_ (.A1(_06070_),
+ .A2(_06079_),
+ .ZN(_06080_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _17894_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[4][1] ),
+ .A2(net722),
+ .ZN(_06081_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _17895_ (.A1(net701),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[5][1] ),
+ .B(net678),
+ .ZN(_06082_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _17896_ (.A1(net703),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[7][1] ),
+ .ZN(_06083_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _17897_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[6][1] ),
+ .A2(net722),
+ .B(net666),
+ .ZN(_06084_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _17898_ (.A1(_06084_),
+ .A2(_06083_),
+ .B1(_06082_),
+ .B2(_06081_),
+ .C(net739),
+ .ZN(_06085_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _17899_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[1][1] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[0][1] ),
+ .S(net701),
+ .Z(_06086_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _17900_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[3][1] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[2][1] ),
+ .S(net701),
+ .Z(_06087_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _17901_ (.I0(_06086_),
+ .I1(_06087_),
+ .S(net666),
+ .Z(_06088_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _17902_ (.A1(_06088_),
+ .A2(net738),
+ .B(net652),
+ .C(_06085_),
+ .ZN(_06089_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _17903_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[12][1] ),
+ .A2(net721),
+ .ZN(_06090_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _17904_ (.A1(net701),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[13][1] ),
+ .B(net678),
+ .ZN(_06091_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _17905_ (.A1(net700),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[15][1] ),
+ .ZN(_06092_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _17906_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[14][1] ),
+ .A2(net722),
+ .B(net666),
+ .ZN(_06093_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _17907_ (.A1(_06093_),
+ .A2(_06092_),
+ .B1(_06091_),
+ .B2(_06090_),
+ .C(net738),
+ .ZN(_06094_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _17908_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[9][1] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[8][1] ),
+ .S(net700),
+ .Z(_06095_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _17909_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[11][1] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[10][1] ),
+ .S(net701),
+ .Z(_06096_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _17910_ (.I0(_06095_),
+ .I1(_06096_),
+ .S(net665),
+ .Z(_06097_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _17911_ (.A1(_06097_),
+ .A2(net738),
+ .B(net649),
+ .C(_06094_),
+ .ZN(_06098_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _17912_ (.A1(_06089_),
+ .A2(_06098_),
+ .ZN(_06099_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _17913_ (.I0(_06099_),
+ .I1(_06080_),
+ .S(net642),
+ .Z(_00043_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _17914_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[20][2] ),
+ .A2(net722),
+ .ZN(_06100_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _17915_ (.A1(net700),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[21][2] ),
+ .B(net678),
+ .ZN(_06101_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _17916_ (.A1(net700),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[23][2] ),
+ .ZN(_06102_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _17917_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[22][2] ),
+ .A2(net722),
+ .B(net666),
+ .ZN(_06103_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _17918_ (.A1(_06103_),
+ .A2(_06102_),
+ .B1(_06101_),
+ .B2(_06100_),
+ .C(net738),
+ .ZN(_06104_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _17919_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[17][2] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[16][2] ),
+ .S(net700),
+ .Z(_06105_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _17920_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[19][2] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[18][2] ),
+ .S(net700),
+ .Z(_06106_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _17921_ (.I0(_06105_),
+ .I1(_06106_),
+ .S(net666),
+ .Z(_06107_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _17922_ (.A1(_06107_),
+ .A2(net738),
+ .B(net652),
+ .C(_06104_),
+ .ZN(_06108_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _17923_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[25][2] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[24][2] ),
+ .S(net689),
+ .Z(_06109_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _17924_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[27][2] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[26][2] ),
+ .S(net689),
+ .Z(_06110_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _17925_ (.I0(_06109_),
+ .I1(_06110_),
+ .S(net660),
+ .Z(_06111_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _17926_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[28][2] ),
+ .A2(net716),
+ .ZN(_06112_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _17927_ (.A1(net689),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[29][2] ),
+ .B(net675),
+ .ZN(_06113_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _17928_ (.A1(net700),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[31][2] ),
+ .ZN(_06114_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _17929_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[30][2] ),
+ .A2(net716),
+ .B(net660),
+ .ZN(_06115_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _17930_ (.A1(_06115_),
+ .A2(_06114_),
+ .B1(_06113_),
+ .B2(_06112_),
+ .C(net733),
+ .ZN(_06116_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _17931_ (.A1(_06111_),
+ .A2(net733),
+ .B(net645),
+ .C(_06116_),
+ .ZN(_06117_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _17932_ (.A1(_06108_),
+ .A2(_06117_),
+ .ZN(_06118_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _17933_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[4][2] ),
+ .A2(net716),
+ .ZN(_06119_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _17934_ (.A1(net688),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[5][2] ),
+ .B(net675),
+ .ZN(_06120_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _17935_ (.A1(net688),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[7][2] ),
+ .ZN(_06121_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _17936_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[6][2] ),
+ .A2(net716),
+ .B(net660),
+ .ZN(_06122_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _17937_ (.A1(_06122_),
+ .A2(_06121_),
+ .B1(_06120_),
+ .B2(_06119_),
+ .C(net733),
+ .ZN(_06123_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _17938_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[1][2] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[0][2] ),
+ .S(net688),
+ .Z(_06124_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _17939_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[3][2] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[2][2] ),
+ .S(net688),
+ .Z(_06125_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _17940_ (.I0(_06124_),
+ .I1(_06125_),
+ .S(net660),
+ .Z(_06126_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _17941_ (.A1(_06126_),
+ .A2(net733),
+ .B(net651),
+ .C(_06123_),
+ .ZN(_06127_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _17942_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[12][2] ),
+ .A2(net715),
+ .ZN(_06128_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _17943_ (.A1(net687),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[13][2] ),
+ .B(net675),
+ .ZN(_06129_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _17944_ (.A1(net687),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[15][2] ),
+ .ZN(_06130_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _17945_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[14][2] ),
+ .A2(net715),
+ .B(net659),
+ .ZN(_06131_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _17946_ (.A1(_06131_),
+ .A2(_06130_),
+ .B1(_06129_),
+ .B2(_06128_),
+ .C(net732),
+ .ZN(_06132_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _17947_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[9][2] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[8][2] ),
+ .S(net686),
+ .Z(_06133_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _17948_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[11][2] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[10][2] ),
+ .S(net686),
+ .Z(_06134_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _17949_ (.I0(_06133_),
+ .I1(_06134_),
+ .S(net659),
+ .Z(_06135_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _17950_ (.A1(_06135_),
+ .A2(net732),
+ .B(net645),
+ .C(_06132_),
+ .ZN(_06136_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _17951_ (.A1(_06127_),
+ .A2(_06136_),
+ .ZN(_06137_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _17952_ (.I0(_06137_),
+ .I1(_06118_),
+ .S(net642),
+ .Z(_00054_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _17953_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[20][3] ),
+ .A2(net715),
+ .ZN(_06138_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _17954_ (.A1(net686),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[21][3] ),
+ .B(net674),
+ .ZN(_06139_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _17955_ (.A1(net687),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[23][3] ),
+ .ZN(_06140_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _17956_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[22][3] ),
+ .A2(net715),
+ .B(net659),
+ .ZN(_06141_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _17957_ (.A1(_06141_),
+ .A2(_06140_),
+ .B1(_06139_),
+ .B2(_06138_),
+ .C(net732),
+ .ZN(_06142_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _17958_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[17][3] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[16][3] ),
+ .S(net686),
+ .Z(_06143_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _17959_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[19][3] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[18][3] ),
+ .S(net686),
+ .Z(_06144_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _17960_ (.I0(_06143_),
+ .I1(_06144_),
+ .S(net659),
+ .Z(_06145_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _17961_ (.A1(_06145_),
+ .A2(net732),
+ .B(net651),
+ .C(_06142_),
+ .ZN(_06146_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _17962_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[25][3] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[24][3] ),
+ .S(net688),
+ .Z(_06147_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _17963_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[27][3] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[26][3] ),
+ .S(net688),
+ .Z(_06148_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _17964_ (.I0(_06147_),
+ .I1(_06148_),
+ .S(net660),
+ .Z(_06149_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _17965_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[28][3] ),
+ .A2(net715),
+ .ZN(_06150_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _17966_ (.A1(net686),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[29][3] ),
+ .B(net675),
+ .ZN(_06151_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _17967_ (.A1(net686),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[31][3] ),
+ .ZN(_06152_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _17968_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[30][3] ),
+ .A2(net715),
+ .B(net659),
+ .ZN(_06153_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _17969_ (.A1(_06153_),
+ .A2(_06152_),
+ .B1(_06151_),
+ .B2(_06150_),
+ .C(net732),
+ .ZN(_06154_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _17970_ (.A1(_06149_),
+ .A2(net732),
+ .B(net645),
+ .C(_06154_),
+ .ZN(_06155_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _17971_ (.A1(_06146_),
+ .A2(_06155_),
+ .ZN(_06156_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _17972_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[4][3] ),
+ .A2(net715),
+ .ZN(_06157_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _17973_ (.A1(net686),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[5][3] ),
+ .B(net675),
+ .ZN(_06158_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _17974_ (.A1(net687),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[7][3] ),
+ .ZN(_06159_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _17975_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[6][3] ),
+ .A2(net715),
+ .B(net659),
+ .ZN(_06160_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _17976_ (.A1(_06160_),
+ .A2(_06159_),
+ .B1(_06158_),
+ .B2(_06157_),
+ .C(net732),
+ .ZN(_06161_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _17977_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[1][3] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[0][3] ),
+ .S(net687),
+ .Z(_06162_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _17978_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[3][3] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[2][3] ),
+ .S(net687),
+ .Z(_06163_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _17979_ (.I0(_06162_),
+ .I1(_06163_),
+ .S(net659),
+ .Z(_06164_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _17980_ (.A1(_06164_),
+ .A2(net732),
+ .B(net651),
+ .C(_06161_),
+ .ZN(_06165_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _17981_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[12][3] ),
+ .A2(net715),
+ .ZN(_06166_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _17982_ (.A1(net686),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[13][3] ),
+ .B(net675),
+ .ZN(_06167_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _17983_ (.A1(net686),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[15][3] ),
+ .ZN(_06168_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _17984_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[14][3] ),
+ .A2(net715),
+ .B(net659),
+ .ZN(_06169_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _17985_ (.A1(_06169_),
+ .A2(_06168_),
+ .B1(_06167_),
+ .B2(_06166_),
+ .C(net732),
+ .ZN(_06170_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _17986_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[9][3] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[8][3] ),
+ .S(net686),
+ .Z(_06171_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _17987_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[11][3] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[10][3] ),
+ .S(net686),
+ .Z(_06172_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _17988_ (.I0(_06171_),
+ .I1(_06172_),
+ .S(net659),
+ .Z(_06173_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _17989_ (.A1(_06173_),
+ .A2(net732),
+ .B(net645),
+ .C(_06170_),
+ .ZN(_06174_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _17990_ (.A1(_06165_),
+ .A2(_06174_),
+ .ZN(_06175_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _17991_ (.I0(_06175_),
+ .I1(_06156_),
+ .S(net642),
+ .Z(_00057_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _17992_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[20][4] ),
+ .A2(net713),
+ .ZN(_06176_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _17993_ (.A1(net683),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[21][4] ),
+ .B(net674),
+ .ZN(_06177_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _17994_ (.A1(net686),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[23][4] ),
+ .ZN(_06178_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _17995_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[22][4] ),
+ .A2(net713),
+ .B(net657),
+ .ZN(_06179_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _17996_ (.A1(_06179_),
+ .A2(_06178_),
+ .B1(_06177_),
+ .B2(_06176_),
+ .C(net730),
+ .ZN(_06180_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _17997_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[17][4] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[16][4] ),
+ .S(net683),
+ .Z(_06181_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _17998_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[19][4] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[18][4] ),
+ .S(net683),
+ .Z(_06182_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _17999_ (.I0(_06181_),
+ .I1(_06182_),
+ .S(net657),
+ .Z(_06183_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _18000_ (.A1(_06183_),
+ .A2(net730),
+ .B(net651),
+ .C(_06180_),
+ .ZN(_06184_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18001_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[25][4] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[24][4] ),
+ .S(net686),
+ .Z(_06185_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18002_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[27][4] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[26][4] ),
+ .S(net686),
+ .Z(_06186_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18003_ (.I0(_06185_),
+ .I1(_06186_),
+ .S(net659),
+ .Z(_06187_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _18004_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[28][4] ),
+ .A2(net713),
+ .ZN(_06188_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _18005_ (.A1(net683),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[29][4] ),
+ .B(net674),
+ .ZN(_06189_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _18006_ (.A1(net688),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[31][4] ),
+ .ZN(_06190_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _18007_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[30][4] ),
+ .A2(net715),
+ .B(net660),
+ .ZN(_06191_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _18008_ (.A1(_06191_),
+ .A2(_06190_),
+ .B1(_06189_),
+ .B2(_06188_),
+ .C(net730),
+ .ZN(_06192_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _18009_ (.A1(_06187_),
+ .A2(net730),
+ .B(net645),
+ .C(_06192_),
+ .ZN(_06193_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _18010_ (.A1(_06184_),
+ .A2(_06193_),
+ .ZN(_06194_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _18011_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[4][4] ),
+ .A2(net715),
+ .ZN(_06195_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _18012_ (.A1(net686),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[5][4] ),
+ .B(net675),
+ .ZN(_06196_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _18013_ (.A1(net686),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[7][4] ),
+ .ZN(_06197_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _18014_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[6][4] ),
+ .A2(net715),
+ .B(net659),
+ .ZN(_06198_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _18015_ (.A1(_06198_),
+ .A2(_06197_),
+ .B1(_06196_),
+ .B2(_06195_),
+ .C(net732),
+ .ZN(_06199_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18016_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[1][4] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[0][4] ),
+ .S(net686),
+ .Z(_06200_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18017_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[3][4] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[2][4] ),
+ .S(net686),
+ .Z(_06201_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18018_ (.I0(_06200_),
+ .I1(_06201_),
+ .S(net659),
+ .Z(_06202_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _18019_ (.A1(_06202_),
+ .A2(net732),
+ .B(net651),
+ .C(_06199_),
+ .ZN(_06203_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _18020_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[12][4] ),
+ .A2(net713),
+ .ZN(_06204_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _18021_ (.A1(net683),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[13][4] ),
+ .B(net674),
+ .ZN(_06205_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _18022_ (.A1(net686),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[15][4] ),
+ .ZN(_06206_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _18023_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[14][4] ),
+ .A2(net715),
+ .B(net659),
+ .ZN(_06207_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _18024_ (.A1(_06207_),
+ .A2(_06206_),
+ .B1(_06205_),
+ .B2(_06204_),
+ .C(net730),
+ .ZN(_06208_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18025_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[9][4] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[8][4] ),
+ .S(net686),
+ .Z(_06209_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18026_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[11][4] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[10][4] ),
+ .S(net686),
+ .Z(_06210_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18027_ (.I0(_06209_),
+ .I1(_06210_),
+ .S(net659),
+ .Z(_06211_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _18028_ (.A1(_06211_),
+ .A2(net732),
+ .B(net645),
+ .C(_06208_),
+ .ZN(_06212_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _18029_ (.A1(_06203_),
+ .A2(_06212_),
+ .ZN(_06213_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18030_ (.I0(_06213_),
+ .I1(_06194_),
+ .S(net642),
+ .Z(_00058_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _18031_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[20][5] ),
+ .A2(net721),
+ .ZN(_06214_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _18032_ (.A1(net698),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[21][5] ),
+ .B(net678),
+ .ZN(_06215_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _18033_ (.A1(net698),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[23][5] ),
+ .ZN(_06216_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _18034_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[22][5] ),
+ .A2(net721),
+ .B(net665),
+ .ZN(_06217_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _18035_ (.A1(_06217_),
+ .A2(_06216_),
+ .B1(_06215_),
+ .B2(_06214_),
+ .C(net738),
+ .ZN(_06218_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18036_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[17][5] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[16][5] ),
+ .S(net698),
+ .Z(_06219_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18037_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[19][5] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[18][5] ),
+ .S(net698),
+ .Z(_06220_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18038_ (.I0(_06219_),
+ .I1(_06220_),
+ .S(net665),
+ .Z(_06221_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _18039_ (.A1(_06221_),
+ .A2(net738),
+ .B(net652),
+ .C(_06218_),
+ .ZN(_06222_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18040_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[25][5] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[24][5] ),
+ .S(net700),
+ .Z(_06223_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18041_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[27][5] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[26][5] ),
+ .S(net700),
+ .Z(_06224_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18042_ (.I0(_06223_),
+ .I1(_06224_),
+ .S(net665),
+ .Z(_06225_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _18043_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[28][5] ),
+ .A2(net721),
+ .ZN(_06226_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _18044_ (.A1(net698),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[29][5] ),
+ .B(net678),
+ .ZN(_06227_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _18045_ (.A1(net698),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[31][5] ),
+ .ZN(_06228_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _18046_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[30][5] ),
+ .A2(net721),
+ .B(net665),
+ .ZN(_06229_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _18047_ (.A1(_06229_),
+ .A2(_06228_),
+ .B1(_06227_),
+ .B2(_06226_),
+ .C(net738),
+ .ZN(_06230_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _18048_ (.A1(_06225_),
+ .A2(net738),
+ .B(net647),
+ .C(_06230_),
+ .ZN(_06231_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _18049_ (.A1(_06222_),
+ .A2(_06231_),
+ .ZN(_06232_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _18050_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[4][5] ),
+ .A2(net721),
+ .ZN(_06233_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _18051_ (.A1(net698),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[5][5] ),
+ .B(net678),
+ .ZN(_06234_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _18052_ (.A1(net698),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[7][5] ),
+ .ZN(_06235_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _18053_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[6][5] ),
+ .A2(net721),
+ .B(net665),
+ .ZN(_06236_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _18054_ (.A1(_06236_),
+ .A2(_06235_),
+ .B1(_06234_),
+ .B2(_06233_),
+ .C(net738),
+ .ZN(_06237_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18055_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[1][5] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[0][5] ),
+ .S(net698),
+ .Z(_06238_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18056_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[3][5] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[2][5] ),
+ .S(net698),
+ .Z(_06239_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18057_ (.I0(_06238_),
+ .I1(_06239_),
+ .S(net665),
+ .Z(_06240_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _18058_ (.A1(_06240_),
+ .A2(net738),
+ .B(net652),
+ .C(_06237_),
+ .ZN(_06241_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _18059_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[12][5] ),
+ .A2(net721),
+ .ZN(_06242_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _18060_ (.A1(net698),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[13][5] ),
+ .B(net678),
+ .ZN(_06243_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _18061_ (.A1(net698),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[15][5] ),
+ .ZN(_06244_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _18062_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[14][5] ),
+ .A2(net721),
+ .B(net665),
+ .ZN(_06245_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _18063_ (.A1(_06245_),
+ .A2(_06244_),
+ .B1(_06243_),
+ .B2(_06242_),
+ .C(net738),
+ .ZN(_06246_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18064_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[9][5] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[8][5] ),
+ .S(net698),
+ .Z(_06247_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18065_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[11][5] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[10][5] ),
+ .S(net698),
+ .Z(_06248_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18066_ (.I0(_06247_),
+ .I1(_06248_),
+ .S(net665),
+ .Z(_06249_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _18067_ (.A1(_06249_),
+ .A2(net738),
+ .B(net647),
+ .C(_06246_),
+ .ZN(_06250_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _18068_ (.A1(_06241_),
+ .A2(_06250_),
+ .ZN(_06251_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18069_ (.I0(_06251_),
+ .I1(_06232_),
+ .S(_06032_),
+ .Z(_00059_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _18070_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[20][6] ),
+ .A2(net713),
+ .ZN(_06252_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _18071_ (.A1(net682),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[21][6] ),
+ .B(net674),
+ .ZN(_06253_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _18072_ (.A1(net682),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[23][6] ),
+ .ZN(_06254_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _18073_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[22][6] ),
+ .A2(net713),
+ .B(net657),
+ .ZN(_06255_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _18074_ (.A1(_06255_),
+ .A2(_06254_),
+ .B1(_06253_),
+ .B2(_06252_),
+ .C(net730),
+ .ZN(_06256_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18075_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[17][6] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[16][6] ),
+ .S(net682),
+ .Z(_06257_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18076_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[19][6] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[18][6] ),
+ .S(net682),
+ .Z(_06258_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18077_ (.I0(_06257_),
+ .I1(_06258_),
+ .S(net657),
+ .Z(_06259_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _18078_ (.A1(_06259_),
+ .A2(net730),
+ .B(net651),
+ .C(_06256_),
+ .ZN(_06260_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18079_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[25][6] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[24][6] ),
+ .S(net683),
+ .Z(_06261_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18080_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[27][6] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[26][6] ),
+ .S(net682),
+ .Z(_06262_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18081_ (.I0(_06261_),
+ .I1(_06262_),
+ .S(net657),
+ .Z(_06263_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _18082_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[28][6] ),
+ .A2(net713),
+ .ZN(_06264_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _18083_ (.A1(net682),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[29][6] ),
+ .B(net674),
+ .ZN(_06265_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _18084_ (.A1(net682),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[31][6] ),
+ .ZN(_06266_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _18085_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[30][6] ),
+ .A2(net713),
+ .B(net657),
+ .ZN(_06267_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _18086_ (.A1(_06267_),
+ .A2(_06266_),
+ .B1(_06265_),
+ .B2(_06264_),
+ .C(net730),
+ .ZN(_06268_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _18087_ (.A1(_06263_),
+ .A2(net730),
+ .B(net645),
+ .C(_06268_),
+ .ZN(_06269_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _18088_ (.A1(_06260_),
+ .A2(_06269_),
+ .ZN(_06270_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _18089_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[4][6] ),
+ .A2(net713),
+ .ZN(_06271_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _18090_ (.A1(net682),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[5][6] ),
+ .B(net674),
+ .ZN(_06272_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _18091_ (.A1(net683),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[7][6] ),
+ .ZN(_06273_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _18092_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[6][6] ),
+ .A2(net713),
+ .B(net657),
+ .ZN(_06274_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _18093_ (.A1(_06274_),
+ .A2(_06273_),
+ .B1(_06272_),
+ .B2(_06271_),
+ .C(net730),
+ .ZN(_06275_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18094_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[1][6] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[0][6] ),
+ .S(net683),
+ .Z(_06276_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18095_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[3][6] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[2][6] ),
+ .S(net683),
+ .Z(_06277_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18096_ (.I0(_06276_),
+ .I1(_06277_),
+ .S(net657),
+ .Z(_06278_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _18097_ (.A1(_06278_),
+ .A2(net730),
+ .B(net651),
+ .C(_06275_),
+ .ZN(_06279_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _18098_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[12][6] ),
+ .A2(net713),
+ .ZN(_06280_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _18099_ (.A1(net682),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[13][6] ),
+ .B(net674),
+ .ZN(_06281_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _18100_ (.A1(net682),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[15][6] ),
+ .ZN(_06282_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _18101_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[14][6] ),
+ .A2(net713),
+ .B(net657),
+ .ZN(_06283_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _18102_ (.A1(_06283_),
+ .A2(_06282_),
+ .B1(_06281_),
+ .B2(_06280_),
+ .C(net730),
+ .ZN(_06284_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18103_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[9][6] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[8][6] ),
+ .S(net682),
+ .Z(_06285_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18104_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[11][6] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[10][6] ),
+ .S(net682),
+ .Z(_06286_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18105_ (.I0(_06285_),
+ .I1(_06286_),
+ .S(net657),
+ .Z(_06287_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _18106_ (.A1(_06287_),
+ .A2(net730),
+ .B(net645),
+ .C(_06284_),
+ .ZN(_06288_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _18107_ (.A1(_06279_),
+ .A2(_06288_),
+ .ZN(_06289_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18108_ (.I0(_06289_),
+ .I1(_06270_),
+ .S(net642),
+ .Z(_00060_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _18109_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[20][7] ),
+ .A2(net715),
+ .ZN(_06290_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _18110_ (.A1(net687),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[21][7] ),
+ .B(net675),
+ .ZN(_06291_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _18111_ (.A1(net698),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[23][7] ),
+ .ZN(_06292_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _18112_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[22][7] ),
+ .A2(net721),
+ .B(net665),
+ .ZN(_06293_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _18113_ (.A1(_06293_),
+ .A2(_06292_),
+ .B1(_06291_),
+ .B2(_06290_),
+ .C(net732),
+ .ZN(_06294_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18114_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[17][7] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[16][7] ),
+ .S(net698),
+ .Z(_06295_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18115_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[19][7] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[18][7] ),
+ .S(net687),
+ .Z(_06296_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18116_ (.I0(_06295_),
+ .I1(_06296_),
+ .S(net659),
+ .Z(_06297_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _18117_ (.A1(_06297_),
+ .A2(net732),
+ .B(net652),
+ .C(_06294_),
+ .ZN(_06298_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18118_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[25][7] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[24][7] ),
+ .S(net698),
+ .Z(_06299_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18119_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[27][7] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[26][7] ),
+ .S(net698),
+ .Z(_06300_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18120_ (.I0(_06299_),
+ .I1(_06300_),
+ .S(net659),
+ .Z(_06301_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _18121_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[28][7] ),
+ .A2(net715),
+ .ZN(_06302_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _18122_ (.A1(net687),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[29][7] ),
+ .B(net675),
+ .ZN(_06303_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _18123_ (.A1(net687),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[31][7] ),
+ .ZN(_06304_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _18124_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[30][7] ),
+ .A2(net715),
+ .B(net659),
+ .ZN(_06305_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _18125_ (.A1(_06305_),
+ .A2(_06304_),
+ .B1(_06303_),
+ .B2(_06302_),
+ .C(net732),
+ .ZN(_06306_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _18126_ (.A1(_06301_),
+ .A2(net732),
+ .B(net645),
+ .C(_06306_),
+ .ZN(_06307_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _18127_ (.A1(_06298_),
+ .A2(_06307_),
+ .ZN(_06308_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _18128_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[4][7] ),
+ .A2(net715),
+ .ZN(_06309_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _18129_ (.A1(net687),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[5][7] ),
+ .B(net675),
+ .ZN(_06310_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _18130_ (.A1(net698),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[7][7] ),
+ .ZN(_06311_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _18131_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[6][7] ),
+ .A2(net721),
+ .B(net665),
+ .ZN(_06312_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _18132_ (.A1(_06312_),
+ .A2(_06311_),
+ .B1(_06310_),
+ .B2(_06309_),
+ .C(net732),
+ .ZN(_06313_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18133_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[1][7] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[0][7] ),
+ .S(net698),
+ .Z(_06314_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18134_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[3][7] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[2][7] ),
+ .S(net687),
+ .Z(_06315_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18135_ (.I0(_06314_),
+ .I1(_06315_),
+ .S(net659),
+ .Z(_06316_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _18136_ (.A1(_06316_),
+ .A2(net732),
+ .B(net652),
+ .C(_06313_),
+ .ZN(_06317_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _18137_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[12][7] ),
+ .A2(net715),
+ .ZN(_06318_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _18138_ (.A1(net687),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[13][7] ),
+ .B(net675),
+ .ZN(_06319_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _18139_ (.A1(net687),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[15][7] ),
+ .ZN(_06320_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _18140_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[14][7] ),
+ .A2(net715),
+ .B(net659),
+ .ZN(_06321_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _18141_ (.A1(_06321_),
+ .A2(_06320_),
+ .B1(_06319_),
+ .B2(_06318_),
+ .C(net732),
+ .ZN(_06322_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18142_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[9][7] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[8][7] ),
+ .S(net687),
+ .Z(_06323_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18143_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[11][7] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[10][7] ),
+ .S(net687),
+ .Z(_06324_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18144_ (.I0(_06323_),
+ .I1(_06324_),
+ .S(net659),
+ .Z(_06325_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _18145_ (.A1(_06325_),
+ .A2(net732),
+ .B(net645),
+ .C(_06322_),
+ .ZN(_06326_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _18146_ (.A1(_06317_),
+ .A2(_06326_),
+ .ZN(_06327_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18147_ (.I0(_06327_),
+ .I1(_06308_),
+ .S(net642),
+ .Z(_00061_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _18148_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[20][8] ),
+ .A2(net717),
+ .ZN(_06328_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _18149_ (.A1(net690),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[21][8] ),
+ .B(net676),
+ .ZN(_06329_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _18150_ (.A1(net690),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[23][8] ),
+ .ZN(_06330_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _18151_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[22][8] ),
+ .A2(net717),
+ .B(net661),
+ .ZN(_06331_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _18152_ (.A1(_06331_),
+ .A2(_06330_),
+ .B1(_06329_),
+ .B2(_06328_),
+ .C(net734),
+ .ZN(_06332_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18153_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[17][8] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[16][8] ),
+ .S(net690),
+ .Z(_06333_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18154_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[19][8] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[18][8] ),
+ .S(net690),
+ .Z(_06334_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18155_ (.I0(_06333_),
+ .I1(_06334_),
+ .S(net661),
+ .Z(_06335_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _18156_ (.A1(_06335_),
+ .A2(net734),
+ .B(net651),
+ .C(_06332_),
+ .ZN(_06336_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18157_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[25][8] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[24][8] ),
+ .S(net690),
+ .Z(_06337_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18158_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[27][8] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[26][8] ),
+ .S(net690),
+ .Z(_06338_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18159_ (.I0(_06337_),
+ .I1(_06338_),
+ .S(net661),
+ .Z(_06339_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _18160_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[28][8] ),
+ .A2(net717),
+ .ZN(_06340_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _18161_ (.A1(net690),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[29][8] ),
+ .B(net676),
+ .ZN(_06341_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _18162_ (.A1(net690),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[31][8] ),
+ .ZN(_06342_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _18163_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[30][8] ),
+ .A2(net717),
+ .B(net661),
+ .ZN(_06343_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _18164_ (.A1(_06343_),
+ .A2(_06342_),
+ .B1(_06341_),
+ .B2(_06340_),
+ .C(net734),
+ .ZN(_06344_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _18165_ (.A1(_06339_),
+ .A2(net734),
+ .B(net646),
+ .C(_06344_),
+ .ZN(_06345_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _18166_ (.A1(_06336_),
+ .A2(_06345_),
+ .ZN(_06346_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18167_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[1][8] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[0][8] ),
+ .S(net691),
+ .Z(_06347_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18168_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[3][8] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[2][8] ),
+ .S(net691),
+ .Z(_06348_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18169_ (.I0(_06347_),
+ .I1(_06348_),
+ .S(net661),
+ .Z(_06349_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _18170_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[4][8] ),
+ .A2(net717),
+ .ZN(_06350_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _18171_ (.A1(net691),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[5][8] ),
+ .B(net676),
+ .ZN(_06351_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _18172_ (.A1(net691),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[7][8] ),
+ .ZN(_06352_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _18173_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[6][8] ),
+ .A2(net717),
+ .B(net661),
+ .ZN(_06353_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _18174_ (.A1(_06353_),
+ .A2(_06352_),
+ .B1(_06351_),
+ .B2(_06350_),
+ .C(net734),
+ .ZN(_06354_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _18175_ (.A1(_06349_),
+ .A2(net734),
+ .B(net651),
+ .C(_06354_),
+ .ZN(_06355_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _18176_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[12][8] ),
+ .A2(net717),
+ .ZN(_06356_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _18177_ (.A1(net690),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[13][8] ),
+ .B(net676),
+ .ZN(_06357_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _18178_ (.A1(net691),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[15][8] ),
+ .ZN(_06358_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _18179_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[14][8] ),
+ .A2(net717),
+ .B(net661),
+ .ZN(_06359_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _18180_ (.A1(_06359_),
+ .A2(_06358_),
+ .B1(_06357_),
+ .B2(_06356_),
+ .C(net734),
+ .ZN(_06360_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18181_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[9][8] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[8][8] ),
+ .S(net691),
+ .Z(_06361_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18182_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[11][8] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[10][8] ),
+ .S(net690),
+ .Z(_06362_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18183_ (.I0(_06361_),
+ .I1(_06362_),
+ .S(net661),
+ .Z(_06363_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _18184_ (.A1(_06363_),
+ .A2(net734),
+ .B(net646),
+ .C(_06360_),
+ .ZN(_06364_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _18185_ (.A1(_06355_),
+ .A2(_06364_),
+ .ZN(_06365_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18186_ (.I0(_06365_),
+ .I1(_06346_),
+ .S(net643),
+ .Z(_00062_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _18187_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[20][9] ),
+ .A2(net713),
+ .ZN(_06366_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _18188_ (.A1(net684),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[21][9] ),
+ .B(net674),
+ .ZN(_06367_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _18189_ (.A1(net684),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[23][9] ),
+ .ZN(_06368_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _18190_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[22][9] ),
+ .A2(net714),
+ .B(net657),
+ .ZN(_06369_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _18191_ (.A1(_06369_),
+ .A2(_06368_),
+ .B1(_06367_),
+ .B2(_06366_),
+ .C(net731),
+ .ZN(_06370_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18192_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[17][9] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[16][9] ),
+ .S(net684),
+ .Z(_06371_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18193_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[19][9] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[18][9] ),
+ .S(net684),
+ .Z(_06372_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18194_ (.I0(_06371_),
+ .I1(_06372_),
+ .S(net657),
+ .Z(_06373_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _18195_ (.A1(_06373_),
+ .A2(net731),
+ .B(net651),
+ .C(_06370_),
+ .ZN(_06374_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18196_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[25][9] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[24][9] ),
+ .S(net684),
+ .Z(_06375_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18197_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[27][9] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[26][9] ),
+ .S(net684),
+ .Z(_06376_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18198_ (.I0(_06375_),
+ .I1(_06376_),
+ .S(net657),
+ .Z(_06377_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _18199_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[28][9] ),
+ .A2(net714),
+ .ZN(_06378_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _18200_ (.A1(net684),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[29][9] ),
+ .B(net674),
+ .ZN(_06379_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _18201_ (.A1(net684),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[31][9] ),
+ .ZN(_06380_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _18202_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[30][9] ),
+ .A2(net714),
+ .B(net658),
+ .ZN(_06381_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _18203_ (.A1(_06381_),
+ .A2(_06380_),
+ .B1(_06379_),
+ .B2(_06378_),
+ .C(net731),
+ .ZN(_06382_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _18204_ (.A1(_06377_),
+ .A2(net731),
+ .B(net645),
+ .C(_06382_),
+ .ZN(_06383_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _18205_ (.A1(_06374_),
+ .A2(_06383_),
+ .ZN(_06384_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _18206_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[4][9] ),
+ .A2(net714),
+ .ZN(_06385_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _18207_ (.A1(net685),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[5][9] ),
+ .B(net674),
+ .ZN(_06386_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _18208_ (.A1(net685),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[7][9] ),
+ .ZN(_06387_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _18209_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[6][9] ),
+ .A2(net714),
+ .B(net658),
+ .ZN(_06388_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _18210_ (.A1(_06388_),
+ .A2(_06387_),
+ .B1(_06386_),
+ .B2(_06385_),
+ .C(net731),
+ .ZN(_06389_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18211_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[1][9] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[0][9] ),
+ .S(net685),
+ .Z(_06390_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18212_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[3][9] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[2][9] ),
+ .S(net685),
+ .Z(_06391_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18213_ (.I0(_06390_),
+ .I1(_06391_),
+ .S(net658),
+ .Z(_06392_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _18214_ (.A1(_06392_),
+ .A2(net731),
+ .B(net651),
+ .C(_06389_),
+ .ZN(_06393_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _18215_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[12][9] ),
+ .A2(net714),
+ .ZN(_06394_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _18216_ (.A1(net684),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[13][9] ),
+ .B(net674),
+ .ZN(_06395_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _18217_ (.A1(net684),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[15][9] ),
+ .ZN(_06396_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _18218_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[14][9] ),
+ .A2(net714),
+ .B(net658),
+ .ZN(_06397_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _18219_ (.A1(_06397_),
+ .A2(_06396_),
+ .B1(_06395_),
+ .B2(_06394_),
+ .C(net731),
+ .ZN(_06398_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18220_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[9][9] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[8][9] ),
+ .S(net684),
+ .Z(_06399_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18221_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[11][9] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[10][9] ),
+ .S(net684),
+ .Z(_06400_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18222_ (.I0(_06399_),
+ .I1(_06400_),
+ .S(net658),
+ .Z(_06401_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _18223_ (.A1(_06401_),
+ .A2(net730),
+ .B(net645),
+ .C(_06398_),
+ .ZN(_06402_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _18224_ (.A1(_06393_),
+ .A2(_06402_),
+ .ZN(_06403_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18225_ (.I0(_06403_),
+ .I1(_06384_),
+ .S(net643),
+ .Z(_00063_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _18226_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[20][10] ),
+ .A2(net715),
+ .ZN(_06404_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _18227_ (.A1(net688),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[21][10] ),
+ .B(net674),
+ .ZN(_06405_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _18228_ (.A1(net688),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[23][10] ),
+ .ZN(_06406_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _18229_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[22][10] ),
+ .A2(net715),
+ .B(net659),
+ .ZN(_06407_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _18230_ (.A1(_06407_),
+ .A2(_06406_),
+ .B1(_06405_),
+ .B2(_06404_),
+ .C(net732),
+ .ZN(_06408_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18231_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[17][10] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[16][10] ),
+ .S(net688),
+ .Z(_06409_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18232_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[19][10] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[18][10] ),
+ .S(net688),
+ .Z(_06410_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18233_ (.I0(_06409_),
+ .I1(_06410_),
+ .S(net659),
+ .Z(_06411_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _18234_ (.A1(_06411_),
+ .A2(net733),
+ .B(net651),
+ .C(_06408_),
+ .ZN(_06412_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18235_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[25][10] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[24][10] ),
+ .S(net688),
+ .Z(_06413_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18236_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[27][10] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[26][10] ),
+ .S(net688),
+ .Z(_06414_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18237_ (.I0(_06413_),
+ .I1(_06414_),
+ .S(net660),
+ .Z(_06415_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _18238_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[28][10] ),
+ .A2(net716),
+ .ZN(_06416_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _18239_ (.A1(net688),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[29][10] ),
+ .B(net674),
+ .ZN(_06417_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _18240_ (.A1(net688),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[31][10] ),
+ .ZN(_06418_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _18241_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[30][10] ),
+ .A2(net716),
+ .B(net660),
+ .ZN(_06419_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _18242_ (.A1(_06419_),
+ .A2(_06418_),
+ .B1(_06417_),
+ .B2(_06416_),
+ .C(net733),
+ .ZN(_06420_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _18243_ (.A1(_06415_),
+ .A2(net733),
+ .B(net645),
+ .C(_06420_),
+ .ZN(_06421_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _18244_ (.A1(_06412_),
+ .A2(_06421_),
+ .ZN(_06422_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _18245_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[4][10] ),
+ .A2(net716),
+ .ZN(_06423_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _18246_ (.A1(net688),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[5][10] ),
+ .B(net675),
+ .ZN(_06424_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _18247_ (.A1(net689),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[7][10] ),
+ .ZN(_06425_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _18248_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[6][10] ),
+ .A2(net716),
+ .B(net660),
+ .ZN(_06426_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _18249_ (.A1(_06426_),
+ .A2(_06425_),
+ .B1(_06424_),
+ .B2(_06423_),
+ .C(net733),
+ .ZN(_06427_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18250_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[1][10] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[0][10] ),
+ .S(net689),
+ .Z(_06428_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18251_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[3][10] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[2][10] ),
+ .S(net688),
+ .Z(_06429_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18252_ (.I0(_06428_),
+ .I1(_06429_),
+ .S(net660),
+ .Z(_06430_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _18253_ (.A1(_06430_),
+ .A2(net733),
+ .B(net651),
+ .C(_06427_),
+ .ZN(_06431_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _18254_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[12][10] ),
+ .A2(net716),
+ .ZN(_06432_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _18255_ (.A1(net688),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[13][10] ),
+ .B(net675),
+ .ZN(_06433_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _18256_ (.A1(net688),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[15][10] ),
+ .ZN(_06434_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _18257_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[14][10] ),
+ .A2(net716),
+ .B(net660),
+ .ZN(_06435_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _18258_ (.A1(_06435_),
+ .A2(_06434_),
+ .B1(_06433_),
+ .B2(_06432_),
+ .C(net733),
+ .ZN(_06436_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18259_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[9][10] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[8][10] ),
+ .S(net688),
+ .Z(_06437_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18260_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[11][10] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[10][10] ),
+ .S(net688),
+ .Z(_06438_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18261_ (.I0(_06437_),
+ .I1(_06438_),
+ .S(net660),
+ .Z(_06439_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _18262_ (.A1(_06439_),
+ .A2(net733),
+ .B(net645),
+ .C(_06436_),
+ .ZN(_06440_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _18263_ (.A1(_06431_),
+ .A2(_06440_),
+ .ZN(_06441_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18264_ (.I0(_06441_),
+ .I1(_06422_),
+ .S(net644),
+ .Z(_00033_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _18265_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[20][11] ),
+ .A2(net721),
+ .ZN(_06442_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _18266_ (.A1(net699),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[21][11] ),
+ .B(net678),
+ .ZN(_06443_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _18267_ (.A1(net699),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[23][11] ),
+ .ZN(_06444_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _18268_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[22][11] ),
+ .A2(net721),
+ .B(net665),
+ .ZN(_06445_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _18269_ (.A1(_06445_),
+ .A2(_06444_),
+ .B1(_06443_),
+ .B2(_06442_),
+ .C(net738),
+ .ZN(_06446_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18270_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[17][11] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[16][11] ),
+ .S(net699),
+ .Z(_06447_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18271_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[19][11] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[18][11] ),
+ .S(net699),
+ .Z(_06448_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18272_ (.I0(_06447_),
+ .I1(_06448_),
+ .S(net665),
+ .Z(_06449_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _18273_ (.A1(_06449_),
+ .A2(net738),
+ .B(net652),
+ .C(_06446_),
+ .ZN(_06450_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18274_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[25][11] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[24][11] ),
+ .S(net699),
+ .Z(_06451_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18275_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[27][11] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[26][11] ),
+ .S(net699),
+ .Z(_06452_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18276_ (.I0(_06451_),
+ .I1(_06452_),
+ .S(net665),
+ .Z(_06453_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _18277_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[28][11] ),
+ .A2(net721),
+ .ZN(_06454_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _18278_ (.A1(net699),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[29][11] ),
+ .B(net678),
+ .ZN(_06455_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _18279_ (.A1(net699),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[31][11] ),
+ .ZN(_06456_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _18280_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[30][11] ),
+ .A2(net721),
+ .B(net665),
+ .ZN(_06457_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _18281_ (.A1(_06457_),
+ .A2(_06456_),
+ .B1(_06455_),
+ .B2(_06454_),
+ .C(net738),
+ .ZN(_06458_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _18282_ (.A1(_06453_),
+ .A2(net738),
+ .B(net647),
+ .C(_06458_),
+ .ZN(_06459_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _18283_ (.A1(_06450_),
+ .A2(_06459_),
+ .ZN(_06460_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _18284_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[4][11] ),
+ .A2(net721),
+ .ZN(_06461_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _18285_ (.A1(net698),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[5][11] ),
+ .B(net678),
+ .ZN(_06462_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _18286_ (.A1(net699),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[7][11] ),
+ .ZN(_06463_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _18287_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[6][11] ),
+ .A2(net721),
+ .B(net665),
+ .ZN(_06464_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _18288_ (.A1(_06464_),
+ .A2(_06463_),
+ .B1(_06462_),
+ .B2(_06461_),
+ .C(net738),
+ .ZN(_06465_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18289_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[1][11] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[0][11] ),
+ .S(net698),
+ .Z(_06466_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18290_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[3][11] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[2][11] ),
+ .S(net699),
+ .Z(_06467_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18291_ (.I0(_06466_),
+ .I1(_06467_),
+ .S(net665),
+ .Z(_06468_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _18292_ (.A1(_06468_),
+ .A2(net738),
+ .B(net652),
+ .C(_06465_),
+ .ZN(_06469_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _18293_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[12][11] ),
+ .A2(net721),
+ .ZN(_06470_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _18294_ (.A1(net699),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[13][11] ),
+ .B(net678),
+ .ZN(_06471_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _18295_ (.A1(net699),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[15][11] ),
+ .ZN(_06472_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _18296_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[14][11] ),
+ .A2(net721),
+ .B(net665),
+ .ZN(_06473_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _18297_ (.A1(_06473_),
+ .A2(_06472_),
+ .B1(_06471_),
+ .B2(_06470_),
+ .C(net738),
+ .ZN(_06474_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18298_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[9][11] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[8][11] ),
+ .S(net699),
+ .Z(_06475_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18299_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[11][11] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[10][11] ),
+ .S(net699),
+ .Z(_06476_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18300_ (.I0(_06475_),
+ .I1(_06476_),
+ .S(net665),
+ .Z(_06477_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _18301_ (.A1(_06477_),
+ .A2(net738),
+ .B(net647),
+ .C(_06474_),
+ .ZN(_06478_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _18302_ (.A1(_06469_),
+ .A2(_06478_),
+ .ZN(_06479_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18303_ (.I0(_06479_),
+ .I1(_06460_),
+ .S(_06032_),
+ .Z(_00034_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _18304_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[20][12] ),
+ .A2(net717),
+ .ZN(_06480_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _18305_ (.A1(net690),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[21][12] ),
+ .B(net676),
+ .ZN(_06481_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _18306_ (.A1(net690),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[23][12] ),
+ .ZN(_06482_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _18307_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[22][12] ),
+ .A2(net717),
+ .B(net661),
+ .ZN(_06483_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _18308_ (.A1(_06483_),
+ .A2(_06482_),
+ .B1(_06481_),
+ .B2(_06480_),
+ .C(net734),
+ .ZN(_06484_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18309_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[17][12] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[16][12] ),
+ .S(net690),
+ .Z(_06485_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18310_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[19][12] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[18][12] ),
+ .S(net690),
+ .Z(_06486_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18311_ (.I0(_06485_),
+ .I1(_06486_),
+ .S(net661),
+ .Z(_06487_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _18312_ (.A1(_06487_),
+ .A2(net734),
+ .B(net651),
+ .C(_06484_),
+ .ZN(_06488_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18313_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[25][12] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[24][12] ),
+ .S(net690),
+ .Z(_06489_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18314_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[27][12] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[26][12] ),
+ .S(net690),
+ .Z(_06490_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18315_ (.I0(_06489_),
+ .I1(_06490_),
+ .S(net661),
+ .Z(_06491_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _18316_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[28][12] ),
+ .A2(net717),
+ .ZN(_06492_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _18317_ (.A1(net690),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[29][12] ),
+ .B(net676),
+ .ZN(_06493_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _18318_ (.A1(net690),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[31][12] ),
+ .ZN(_06494_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _18319_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[30][12] ),
+ .A2(net717),
+ .B(net661),
+ .ZN(_06495_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _18320_ (.A1(_06495_),
+ .A2(_06494_),
+ .B1(_06493_),
+ .B2(_06492_),
+ .C(net734),
+ .ZN(_06496_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _18321_ (.A1(_06491_),
+ .A2(net734),
+ .B(net646),
+ .C(_06496_),
+ .ZN(_06497_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _18322_ (.A1(_06488_),
+ .A2(_06497_),
+ .ZN(_06498_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _18323_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[4][12] ),
+ .A2(net717),
+ .ZN(_06499_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _18324_ (.A1(net691),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[5][12] ),
+ .B(net676),
+ .ZN(_06500_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _18325_ (.A1(net690),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[7][12] ),
+ .ZN(_06501_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _18326_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[6][12] ),
+ .A2(net717),
+ .B(net661),
+ .ZN(_06502_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _18327_ (.A1(_06502_),
+ .A2(_06501_),
+ .B1(_06500_),
+ .B2(_06499_),
+ .C(net734),
+ .ZN(_06503_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18328_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[1][12] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[0][12] ),
+ .S(net690),
+ .Z(_06504_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18329_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[3][12] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[2][12] ),
+ .S(net691),
+ .Z(_06505_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18330_ (.I0(_06504_),
+ .I1(_06505_),
+ .S(net661),
+ .Z(_06506_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _18331_ (.A1(_06506_),
+ .A2(net734),
+ .B(net651),
+ .C(_06503_),
+ .ZN(_06507_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _18332_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[12][12] ),
+ .A2(net717),
+ .ZN(_06508_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _18333_ (.A1(net690),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[13][12] ),
+ .B(net676),
+ .ZN(_06509_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _18334_ (.A1(net691),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[15][12] ),
+ .ZN(_06510_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _18335_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[14][12] ),
+ .A2(net717),
+ .B(net661),
+ .ZN(_06511_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _18336_ (.A1(_06511_),
+ .A2(_06510_),
+ .B1(_06509_),
+ .B2(_06508_),
+ .C(net734),
+ .ZN(_06512_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18337_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[9][12] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[8][12] ),
+ .S(net691),
+ .Z(_06513_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18338_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[11][12] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[10][12] ),
+ .S(net690),
+ .Z(_06514_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18339_ (.I0(_06513_),
+ .I1(_06514_),
+ .S(net661),
+ .Z(_06515_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _18340_ (.A1(_06515_),
+ .A2(net734),
+ .B(net646),
+ .C(_06512_),
+ .ZN(_06516_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _18341_ (.A1(_06507_),
+ .A2(_06516_),
+ .ZN(_06517_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18342_ (.I0(_06517_),
+ .I1(_06498_),
+ .S(net643),
+ .Z(_00035_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _18343_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[20][13] ),
+ .A2(net714),
+ .ZN(_06518_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _18344_ (.A1(net684),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[21][13] ),
+ .B(net674),
+ .ZN(_06519_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _18345_ (.A1(net684),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[23][13] ),
+ .ZN(_06520_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _18346_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[22][13] ),
+ .A2(net714),
+ .B(net658),
+ .ZN(_06521_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _18347_ (.A1(_06521_),
+ .A2(_06520_),
+ .B1(_06519_),
+ .B2(_06518_),
+ .C(net731),
+ .ZN(_06522_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18348_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[17][13] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[16][13] ),
+ .S(net684),
+ .Z(_06523_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18349_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[19][13] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[18][13] ),
+ .S(net684),
+ .Z(_06524_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18350_ (.I0(_06523_),
+ .I1(_06524_),
+ .S(net658),
+ .Z(_06525_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _18351_ (.A1(_06525_),
+ .A2(net731),
+ .B(net651),
+ .C(_06522_),
+ .ZN(_06526_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18352_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[25][13] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[24][13] ),
+ .S(net684),
+ .Z(_06527_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18353_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[27][13] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[26][13] ),
+ .S(net684),
+ .Z(_06528_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18354_ (.I0(_06527_),
+ .I1(_06528_),
+ .S(net658),
+ .Z(_06529_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _18355_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[28][13] ),
+ .A2(net714),
+ .ZN(_06530_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _18356_ (.A1(net684),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[29][13] ),
+ .B(net674),
+ .ZN(_06531_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _18357_ (.A1(net684),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[31][13] ),
+ .ZN(_06532_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _18358_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[30][13] ),
+ .A2(net714),
+ .B(net658),
+ .ZN(_06533_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _18359_ (.A1(_06533_),
+ .A2(_06532_),
+ .B1(_06531_),
+ .B2(_06530_),
+ .C(net731),
+ .ZN(_06534_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _18360_ (.A1(_06529_),
+ .A2(net731),
+ .B(net645),
+ .C(_06534_),
+ .ZN(_06535_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _18361_ (.A1(_06526_),
+ .A2(_06535_),
+ .ZN(_06536_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _18362_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[4][13] ),
+ .A2(net714),
+ .ZN(_06537_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _18363_ (.A1(net685),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[5][13] ),
+ .B(net674),
+ .ZN(_06538_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _18364_ (.A1(net685),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[7][13] ),
+ .ZN(_06539_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _18365_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[6][13] ),
+ .A2(net714),
+ .B(net658),
+ .ZN(_06540_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _18366_ (.A1(_06540_),
+ .A2(_06539_),
+ .B1(_06538_),
+ .B2(_06537_),
+ .C(net731),
+ .ZN(_06541_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18367_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[1][13] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[0][13] ),
+ .S(net685),
+ .Z(_06542_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18368_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[3][13] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[2][13] ),
+ .S(net685),
+ .Z(_06543_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18369_ (.I0(_06542_),
+ .I1(_06543_),
+ .S(net658),
+ .Z(_06544_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _18370_ (.A1(_06544_),
+ .A2(net731),
+ .B(net651),
+ .C(_06541_),
+ .ZN(_06545_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _18371_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[12][13] ),
+ .A2(net714),
+ .ZN(_06546_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _18372_ (.A1(net684),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[13][13] ),
+ .B(net674),
+ .ZN(_06547_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _18373_ (.A1(net685),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[15][13] ),
+ .ZN(_06548_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _18374_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[14][13] ),
+ .A2(net713),
+ .B(net657),
+ .ZN(_06549_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _18375_ (.A1(_06549_),
+ .A2(_06548_),
+ .B1(_06547_),
+ .B2(_06546_),
+ .C(net731),
+ .ZN(_06550_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18376_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[9][13] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[8][13] ),
+ .S(net685),
+ .Z(_06551_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18377_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[11][13] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[10][13] ),
+ .S(net685),
+ .Z(_06552_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18378_ (.I0(_06551_),
+ .I1(_06552_),
+ .S(net658),
+ .Z(_06553_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _18379_ (.A1(_06553_),
+ .A2(net731),
+ .B(net645),
+ .C(_06550_),
+ .ZN(_06554_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _18380_ (.A1(_06545_),
+ .A2(_06554_),
+ .ZN(_06555_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18381_ (.I0(_06555_),
+ .I1(_06536_),
+ .S(net643),
+ .Z(_00036_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _18382_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[20][14] ),
+ .A2(net713),
+ .ZN(_06556_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _18383_ (.A1(net682),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[21][14] ),
+ .B(net674),
+ .ZN(_06557_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _18384_ (.A1(net682),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[23][14] ),
+ .ZN(_06558_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _18385_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[22][14] ),
+ .A2(net713),
+ .B(net657),
+ .ZN(_06559_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _18386_ (.A1(_06559_),
+ .A2(_06558_),
+ .B1(_06557_),
+ .B2(_06556_),
+ .C(net730),
+ .ZN(_06560_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18387_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[17][14] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[16][14] ),
+ .S(net682),
+ .Z(_06561_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18388_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[19][14] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[18][14] ),
+ .S(net682),
+ .Z(_06562_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18389_ (.I0(_06561_),
+ .I1(_06562_),
+ .S(net657),
+ .Z(_06563_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _18390_ (.A1(_06563_),
+ .A2(net730),
+ .B(net651),
+ .C(_06560_),
+ .ZN(_06564_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18391_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[25][14] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[24][14] ),
+ .S(net682),
+ .Z(_06565_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18392_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[27][14] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[26][14] ),
+ .S(net684),
+ .Z(_06566_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18393_ (.I0(_06565_),
+ .I1(_06566_),
+ .S(net657),
+ .Z(_06567_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _18394_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[28][14] ),
+ .A2(net713),
+ .ZN(_06568_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _18395_ (.A1(net682),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[29][14] ),
+ .B(net674),
+ .ZN(_06569_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _18396_ (.A1(net682),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[31][14] ),
+ .ZN(_06570_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _18397_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[30][14] ),
+ .A2(net713),
+ .B(net657),
+ .ZN(_06571_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _18398_ (.A1(_06571_),
+ .A2(_06570_),
+ .B1(_06569_),
+ .B2(_06568_),
+ .C(net730),
+ .ZN(_06572_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _18399_ (.A1(_06567_),
+ .A2(net730),
+ .B(net645),
+ .C(_06572_),
+ .ZN(_06573_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _18400_ (.A1(_06564_),
+ .A2(_06573_),
+ .ZN(_06574_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _18401_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[4][14] ),
+ .A2(net713),
+ .ZN(_06575_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _18402_ (.A1(net683),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[5][14] ),
+ .B(net674),
+ .ZN(_06576_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _18403_ (.A1(net683),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[7][14] ),
+ .ZN(_06577_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _18404_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[6][14] ),
+ .A2(net713),
+ .B(net657),
+ .ZN(_06578_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _18405_ (.A1(_06578_),
+ .A2(_06577_),
+ .B1(_06576_),
+ .B2(_06575_),
+ .C(net730),
+ .ZN(_06579_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18406_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[1][14] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[0][14] ),
+ .S(net683),
+ .Z(_06580_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18407_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[3][14] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[2][14] ),
+ .S(net683),
+ .Z(_06581_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18408_ (.I0(_06580_),
+ .I1(_06581_),
+ .S(net657),
+ .Z(_06582_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _18409_ (.A1(_06582_),
+ .A2(net730),
+ .B(net651),
+ .C(_06579_),
+ .ZN(_06583_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _18410_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[12][14] ),
+ .A2(net713),
+ .ZN(_06584_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _18411_ (.A1(net682),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[13][14] ),
+ .B(net674),
+ .ZN(_06585_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _18412_ (.A1(net683),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[15][14] ),
+ .ZN(_06586_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _18413_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[14][14] ),
+ .A2(net713),
+ .B(net657),
+ .ZN(_06587_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _18414_ (.A1(_06587_),
+ .A2(_06586_),
+ .B1(_06585_),
+ .B2(_06584_),
+ .C(net730),
+ .ZN(_06588_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18415_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[9][14] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[8][14] ),
+ .S(net682),
+ .Z(_06589_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18416_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[11][14] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[10][14] ),
+ .S(net682),
+ .Z(_06590_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18417_ (.I0(_06589_),
+ .I1(_06590_),
+ .S(net657),
+ .Z(_06591_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _18418_ (.A1(_06591_),
+ .A2(net730),
+ .B(net645),
+ .C(_06588_),
+ .ZN(_06592_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _18419_ (.A1(_06583_),
+ .A2(_06592_),
+ .ZN(_06593_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18420_ (.I0(_06593_),
+ .I1(_06574_),
+ .S(net642),
+ .Z(_00037_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _18421_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[20][15] ),
+ .A2(net718),
+ .ZN(_06594_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _18422_ (.A1(net692),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[21][15] ),
+ .B(net676),
+ .ZN(_06595_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _18423_ (.A1(net692),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[23][15] ),
+ .ZN(_06596_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _18424_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[22][15] ),
+ .A2(net718),
+ .B(net662),
+ .ZN(_06597_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _18425_ (.A1(_06597_),
+ .A2(_06596_),
+ .B1(_06595_),
+ .B2(_06594_),
+ .C(net734),
+ .ZN(_06598_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18426_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[17][15] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[16][15] ),
+ .S(net692),
+ .Z(_06599_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18427_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[19][15] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[18][15] ),
+ .S(net692),
+ .Z(_06600_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18428_ (.I0(_06599_),
+ .I1(_06600_),
+ .S(net662),
+ .Z(_06601_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _18429_ (.A1(_06601_),
+ .A2(net734),
+ .B(net651),
+ .C(_06598_),
+ .ZN(_06602_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18430_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[25][15] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[24][15] ),
+ .S(net692),
+ .Z(_06603_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18431_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[27][15] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[26][15] ),
+ .S(net692),
+ .Z(_06604_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18432_ (.I0(_06603_),
+ .I1(_06604_),
+ .S(net662),
+ .Z(_06605_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _18433_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[28][15] ),
+ .A2(net718),
+ .ZN(_06606_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _18434_ (.A1(net692),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[29][15] ),
+ .B(net676),
+ .ZN(_06607_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _18435_ (.A1(net692),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[31][15] ),
+ .ZN(_06608_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _18436_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[30][15] ),
+ .A2(net718),
+ .B(net662),
+ .ZN(_06609_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _18437_ (.A1(_06609_),
+ .A2(_06608_),
+ .B1(_06607_),
+ .B2(_06606_),
+ .C(net734),
+ .ZN(_06610_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _18438_ (.A1(_06605_),
+ .A2(net735),
+ .B(net646),
+ .C(_06610_),
+ .ZN(_06611_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _18439_ (.A1(_06602_),
+ .A2(_06611_),
+ .ZN(_06612_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18440_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[1][15] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[0][15] ),
+ .S(net693),
+ .Z(_06613_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18441_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[3][15] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[2][15] ),
+ .S(net693),
+ .Z(_06614_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18442_ (.I0(_06613_),
+ .I1(_06614_),
+ .S(net662),
+ .Z(_06615_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _18443_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[4][15] ),
+ .A2(net717),
+ .ZN(_06616_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _18444_ (.A1(net693),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[5][15] ),
+ .B(net676),
+ .ZN(_06617_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _18445_ (.A1(net693),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[7][15] ),
+ .ZN(_06618_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _18446_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[6][15] ),
+ .A2(net717),
+ .B(net662),
+ .ZN(_06619_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _18447_ (.A1(_06619_),
+ .A2(_06618_),
+ .B1(_06617_),
+ .B2(_06616_),
+ .C(net735),
+ .ZN(_06620_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _18448_ (.A1(_06615_),
+ .A2(net735),
+ .B(net651),
+ .C(_06620_),
+ .ZN(_06621_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _18449_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[12][15] ),
+ .A2(net718),
+ .ZN(_06622_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _18450_ (.A1(net692),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[13][15] ),
+ .B(net676),
+ .ZN(_06623_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _18451_ (.A1(net693),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[15][15] ),
+ .ZN(_06624_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _18452_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[14][15] ),
+ .A2(net718),
+ .B(net662),
+ .ZN(_06625_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _18453_ (.A1(_06625_),
+ .A2(_06624_),
+ .B1(_06623_),
+ .B2(_06622_),
+ .C(net735),
+ .ZN(_06626_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18454_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[9][15] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[8][15] ),
+ .S(net693),
+ .Z(_06627_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18455_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[11][15] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[10][15] ),
+ .S(net693),
+ .Z(_06628_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18456_ (.I0(_06627_),
+ .I1(_06628_),
+ .S(net662),
+ .Z(_06629_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _18457_ (.A1(_06629_),
+ .A2(net735),
+ .B(net646),
+ .C(_06626_),
+ .ZN(_06630_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _18458_ (.A1(_06621_),
+ .A2(_06630_),
+ .ZN(_06631_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18459_ (.I0(_06631_),
+ .I1(_06612_),
+ .S(net643),
+ .Z(_00038_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _18460_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[20][16] ),
+ .A2(net719),
+ .ZN(_06632_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _18461_ (.A1(net695),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[21][16] ),
+ .B(net677),
+ .ZN(_06633_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _18462_ (.A1(net696),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[23][16] ),
+ .ZN(_06634_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _18463_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[22][16] ),
+ .A2(net719),
+ .B(net663),
+ .ZN(_06635_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _18464_ (.A1(_06635_),
+ .A2(_06634_),
+ .B1(_06633_),
+ .B2(_06632_),
+ .C(net736),
+ .ZN(_06636_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18465_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[17][16] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[16][16] ),
+ .S(net696),
+ .Z(_06637_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18466_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[19][16] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[18][16] ),
+ .S(net696),
+ .Z(_06638_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18467_ (.I0(_06637_),
+ .I1(_06638_),
+ .S(net663),
+ .Z(_06639_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _18468_ (.A1(_06639_),
+ .A2(net737),
+ .B(net654),
+ .C(_06636_),
+ .ZN(_06640_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18469_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[25][16] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[24][16] ),
+ .S(net696),
+ .Z(_06641_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18470_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[27][16] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[26][16] ),
+ .S(net696),
+ .Z(_06642_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18471_ (.I0(_06641_),
+ .I1(_06642_),
+ .S(net663),
+ .Z(_06643_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _18472_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[28][16] ),
+ .A2(net719),
+ .ZN(_06644_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _18473_ (.A1(net696),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[29][16] ),
+ .B(net677),
+ .ZN(_06645_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _18474_ (.A1(net696),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[31][16] ),
+ .ZN(_06646_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _18475_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[30][16] ),
+ .A2(net719),
+ .B(net664),
+ .ZN(_06647_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _18476_ (.A1(_06647_),
+ .A2(_06646_),
+ .B1(_06645_),
+ .B2(_06644_),
+ .C(net736),
+ .ZN(_06648_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _18477_ (.A1(_06643_),
+ .A2(net737),
+ .B(net645),
+ .C(_06648_),
+ .ZN(_06649_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _18478_ (.A1(_06640_),
+ .A2(_06649_),
+ .ZN(_06650_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _18479_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[4][16] ),
+ .A2(net719),
+ .ZN(_06651_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _18480_ (.A1(net696),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[5][16] ),
+ .B(net677),
+ .ZN(_06652_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _18481_ (.A1(net695),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[7][16] ),
+ .ZN(_06653_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _18482_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[6][16] ),
+ .A2(net719),
+ .B(net664),
+ .ZN(_06654_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _18483_ (.A1(_06654_),
+ .A2(_06653_),
+ .B1(_06652_),
+ .B2(_06651_),
+ .C(net737),
+ .ZN(_06655_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18484_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[1][16] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[0][16] ),
+ .S(net696),
+ .Z(_06656_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18485_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[3][16] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[2][16] ),
+ .S(net696),
+ .Z(_06657_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18486_ (.I0(_06656_),
+ .I1(_06657_),
+ .S(net664),
+ .Z(_06658_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _18487_ (.A1(_06658_),
+ .A2(net737),
+ .B(net654),
+ .C(_06655_),
+ .ZN(_06659_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _18488_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[12][16] ),
+ .A2(net719),
+ .ZN(_06660_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _18489_ (.A1(net695),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[13][16] ),
+ .B(net677),
+ .ZN(_06661_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _18490_ (.A1(net695),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[15][16] ),
+ .ZN(_06662_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _18491_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[14][16] ),
+ .A2(net719),
+ .B(net664),
+ .ZN(_06663_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _18492_ (.A1(_06663_),
+ .A2(_06662_),
+ .B1(_06661_),
+ .B2(_06660_),
+ .C(net737),
+ .ZN(_06664_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18493_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[9][16] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[8][16] ),
+ .S(net695),
+ .Z(_06665_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18494_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[11][16] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[10][16] ),
+ .S(net695),
+ .Z(_06666_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18495_ (.I0(_06665_),
+ .I1(_06666_),
+ .S(net664),
+ .Z(_06667_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _18496_ (.A1(_06667_),
+ .A2(net737),
+ .B(net645),
+ .C(_06664_),
+ .ZN(_06668_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _18497_ (.A1(_06659_),
+ .A2(_06668_),
+ .ZN(_06669_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18498_ (.I0(_06669_),
+ .I1(_06650_),
+ .S(net644),
+ .Z(_00039_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _18499_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[20][17] ),
+ .A2(net718),
+ .ZN(_06670_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _18500_ (.A1(net693),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[21][17] ),
+ .B(net676),
+ .ZN(_06671_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _18501_ (.A1(net695),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[23][17] ),
+ .ZN(_06672_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _18502_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[22][17] ),
+ .A2(net719),
+ .B(net664),
+ .ZN(_06673_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _18503_ (.A1(_06673_),
+ .A2(_06672_),
+ .B1(_06671_),
+ .B2(_06670_),
+ .C(net735),
+ .ZN(_06674_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18504_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[17][17] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[16][17] ),
+ .S(net695),
+ .Z(_06675_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18505_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[19][17] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[18][17] ),
+ .S(net693),
+ .Z(_06676_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18506_ (.I0(_06675_),
+ .I1(_06676_),
+ .S(net661),
+ .Z(_06677_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _18507_ (.A1(_06677_),
+ .A2(net735),
+ .B(net654),
+ .C(_06674_),
+ .ZN(_06678_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18508_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[25][17] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[24][17] ),
+ .S(net693),
+ .Z(_06679_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18509_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[27][17] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[26][17] ),
+ .S(net693),
+ .Z(_06680_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18510_ (.I0(_06679_),
+ .I1(_06680_),
+ .S(net661),
+ .Z(_06681_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _18511_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[28][17] ),
+ .A2(net717),
+ .ZN(_06682_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _18512_ (.A1(net692),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[29][17] ),
+ .B(net676),
+ .ZN(_06683_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _18513_ (.A1(net693),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[31][17] ),
+ .ZN(_06684_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _18514_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[30][17] ),
+ .A2(net718),
+ .B(net661),
+ .ZN(_06685_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _18515_ (.A1(_06685_),
+ .A2(_06684_),
+ .B1(_06683_),
+ .B2(_06682_),
+ .C(net734),
+ .ZN(_06686_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _18516_ (.A1(_06681_),
+ .A2(net734),
+ .B(net646),
+ .C(_06686_),
+ .ZN(_06687_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _18517_ (.A1(_06678_),
+ .A2(_06687_),
+ .ZN(_06688_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _18518_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[4][17] ),
+ .A2(net719),
+ .ZN(_06689_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _18519_ (.A1(net695),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[5][17] ),
+ .B(net677),
+ .ZN(_06690_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _18520_ (.A1(net695),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[7][17] ),
+ .ZN(_06691_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _18521_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[6][17] ),
+ .A2(net719),
+ .B(net664),
+ .ZN(_06692_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _18522_ (.A1(_06692_),
+ .A2(_06691_),
+ .B1(_06690_),
+ .B2(_06689_),
+ .C(net737),
+ .ZN(_06693_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18523_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[1][17] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[0][17] ),
+ .S(net695),
+ .Z(_06694_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18524_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[3][17] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[2][17] ),
+ .S(net695),
+ .Z(_06695_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18525_ (.I0(_06694_),
+ .I1(_06695_),
+ .S(net664),
+ .Z(_06696_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _18526_ (.A1(_06696_),
+ .A2(net737),
+ .B(net651),
+ .C(_06693_),
+ .ZN(_06697_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _18527_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[12][17] ),
+ .A2(net719),
+ .ZN(_06698_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _18528_ (.A1(net695),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[13][17] ),
+ .B(net677),
+ .ZN(_06699_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _18529_ (.A1(net695),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[15][17] ),
+ .ZN(_06700_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _18530_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[14][17] ),
+ .A2(net719),
+ .B(net664),
+ .ZN(_06701_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _18531_ (.A1(_06701_),
+ .A2(_06700_),
+ .B1(_06699_),
+ .B2(_06698_),
+ .C(net737),
+ .ZN(_06702_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18532_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[9][17] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[8][17] ),
+ .S(net695),
+ .Z(_06703_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18533_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[11][17] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[10][17] ),
+ .S(net695),
+ .Z(_06704_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18534_ (.I0(_06703_),
+ .I1(_06704_),
+ .S(net664),
+ .Z(_06705_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _18535_ (.A1(_06705_),
+ .A2(net737),
+ .B(net646),
+ .C(_06702_),
+ .ZN(_06706_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _18536_ (.A1(_06697_),
+ .A2(_06706_),
+ .ZN(_06707_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18537_ (.I0(_06707_),
+ .I1(_06688_),
+ .S(net644),
+ .Z(_00040_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _18538_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[20][18] ),
+ .A2(net719),
+ .ZN(_06708_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _18539_ (.A1(net696),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[21][18] ),
+ .B(net679),
+ .ZN(_06709_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _18540_ (.A1(net706),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[23][18] ),
+ .ZN(_06710_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _18541_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[22][18] ),
+ .A2(net727),
+ .B(net668),
+ .ZN(_06711_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _18542_ (.A1(_06711_),
+ .A2(_06710_),
+ .B1(_06709_),
+ .B2(_06708_),
+ .C(net744),
+ .ZN(_06712_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18543_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[17][18] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[16][18] ),
+ .S(net706),
+ .Z(_06713_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18544_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[19][18] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[18][18] ),
+ .S(net696),
+ .Z(_06714_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18545_ (.I0(_06713_),
+ .I1(_06714_),
+ .S(net664),
+ .Z(_06715_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _18546_ (.A1(_06715_),
+ .A2(net736),
+ .B(net654),
+ .C(_06712_),
+ .ZN(_06716_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18547_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[25][18] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[24][18] ),
+ .S(net706),
+ .Z(_06717_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18548_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[27][18] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[26][18] ),
+ .S(net706),
+ .Z(_06718_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18549_ (.I0(_06717_),
+ .I1(_06718_),
+ .S(net663),
+ .Z(_06719_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _18550_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[28][18] ),
+ .A2(net720),
+ .ZN(_06720_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _18551_ (.A1(net696),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[29][18] ),
+ .B(net677),
+ .ZN(_06721_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _18552_ (.A1(net696),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[31][18] ),
+ .ZN(_06722_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _18553_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[30][18] ),
+ .A2(net719),
+ .B(net664),
+ .ZN(_06723_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _18554_ (.A1(_06723_),
+ .A2(_06722_),
+ .B1(_06721_),
+ .B2(_06720_),
+ .C(net737),
+ .ZN(_06724_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _18555_ (.A1(_06719_),
+ .A2(net736),
+ .B(net646),
+ .C(_06724_),
+ .ZN(_06725_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _18556_ (.A1(_06716_),
+ .A2(_06725_),
+ .ZN(_06726_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _18557_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[4][18] ),
+ .A2(net727),
+ .ZN(_06727_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _18558_ (.A1(net706),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[5][18] ),
+ .B(net679),
+ .ZN(_06728_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _18559_ (.A1(net706),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[7][18] ),
+ .ZN(_06729_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _18560_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[6][18] ),
+ .A2(net727),
+ .B(net669),
+ .ZN(_06730_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _18561_ (.A1(_06730_),
+ .A2(_06729_),
+ .B1(_06728_),
+ .B2(_06727_),
+ .C(net741),
+ .ZN(_06731_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18562_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[1][18] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[0][18] ),
+ .S(net706),
+ .Z(_06732_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18563_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[3][18] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[2][18] ),
+ .S(net706),
+ .Z(_06733_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18564_ (.I0(_06732_),
+ .I1(_06733_),
+ .S(net668),
+ .Z(_06734_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _18565_ (.A1(_06734_),
+ .A2(net741),
+ .B(net652),
+ .C(_06731_),
+ .ZN(_06735_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _18566_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[12][18] ),
+ .A2(net727),
+ .ZN(_06736_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _18567_ (.A1(net706),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[13][18] ),
+ .B(net679),
+ .ZN(_06737_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _18568_ (.A1(net706),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[15][18] ),
+ .ZN(_06738_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _18569_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[14][18] ),
+ .A2(net724),
+ .B(net669),
+ .ZN(_06739_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _18570_ (.A1(_06739_),
+ .A2(_06738_),
+ .B1(_06737_),
+ .B2(_06736_),
+ .C(net741),
+ .ZN(_06740_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18571_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[9][18] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[8][18] ),
+ .S(net706),
+ .Z(_06741_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18572_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[11][18] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[10][18] ),
+ .S(net706),
+ .Z(_06742_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18573_ (.I0(_06741_),
+ .I1(_06742_),
+ .S(net669),
+ .Z(_06743_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _18574_ (.A1(_06743_),
+ .A2(net741),
+ .B(net648),
+ .C(_06740_),
+ .ZN(_06744_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _18575_ (.A1(_06735_),
+ .A2(_06744_),
+ .ZN(_06745_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18576_ (.I0(_06745_),
+ .I1(_06726_),
+ .S(net644),
+ .Z(_00041_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _18577_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[20][19] ),
+ .A2(net725),
+ .ZN(_06746_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _18578_ (.A1(net711),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[21][19] ),
+ .B(net679),
+ .ZN(_06747_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _18579_ (.A1(net711),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[23][19] ),
+ .ZN(_06748_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _18580_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[22][19] ),
+ .A2(net725),
+ .B(net670),
+ .ZN(_06749_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _18581_ (.A1(_06749_),
+ .A2(_06748_),
+ .B1(_06747_),
+ .B2(_06746_),
+ .C(net742),
+ .ZN(_06750_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18582_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[17][19] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[16][19] ),
+ .S(net711),
+ .Z(_06751_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18583_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[19][19] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[18][19] ),
+ .S(net711),
+ .Z(_06752_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18584_ (.I0(_06751_),
+ .I1(_06752_),
+ .S(net670),
+ .Z(_06753_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _18585_ (.A1(_06753_),
+ .A2(net742),
+ .B(net652),
+ .C(_06750_),
+ .ZN(_06754_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18586_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[25][19] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[24][19] ),
+ .S(net710),
+ .Z(_06755_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18587_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[27][19] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[26][19] ),
+ .S(net710),
+ .Z(_06756_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18588_ (.I0(_06755_),
+ .I1(_06756_),
+ .S(net670),
+ .Z(_06757_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _18589_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[28][19] ),
+ .A2(net726),
+ .ZN(_06758_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _18590_ (.A1(net710),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[29][19] ),
+ .B(net679),
+ .ZN(_06759_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _18591_ (.A1(net710),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[31][19] ),
+ .ZN(_06760_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _18592_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[30][19] ),
+ .A2(net725),
+ .B(net670),
+ .ZN(_06761_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _18593_ (.A1(_06761_),
+ .A2(_06760_),
+ .B1(_06759_),
+ .B2(_06758_),
+ .C(net742),
+ .ZN(_06762_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _18594_ (.A1(_06757_),
+ .A2(net742),
+ .B(net648),
+ .C(_06762_),
+ .ZN(_06763_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _18595_ (.A1(_06754_),
+ .A2(_06763_),
+ .ZN(_06764_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _18596_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[4][19] ),
+ .A2(net725),
+ .ZN(_06765_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _18597_ (.A1(net709),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[5][19] ),
+ .B(net679),
+ .ZN(_06766_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _18598_ (.A1(net709),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[7][19] ),
+ .ZN(_06767_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _18599_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[6][19] ),
+ .A2(net725),
+ .B(net670),
+ .ZN(_06768_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _18600_ (.A1(_06768_),
+ .A2(_06767_),
+ .B1(_06766_),
+ .B2(_06765_),
+ .C(net742),
+ .ZN(_06769_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18601_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[1][19] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[0][19] ),
+ .S(net708),
+ .Z(_06770_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18602_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[3][19] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[2][19] ),
+ .S(net708),
+ .Z(_06771_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18603_ (.I0(_06770_),
+ .I1(_06771_),
+ .S(net670),
+ .Z(_06772_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _18604_ (.A1(_06772_),
+ .A2(net742),
+ .B(net652),
+ .C(_06769_),
+ .ZN(_06773_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _18605_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[12][19] ),
+ .A2(net726),
+ .ZN(_06774_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _18606_ (.A1(net709),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[13][19] ),
+ .B(net680),
+ .ZN(_06775_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _18607_ (.A1(net709),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[15][19] ),
+ .ZN(_06776_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _18608_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[14][19] ),
+ .A2(net726),
+ .B(net670),
+ .ZN(_06777_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _18609_ (.A1(_06777_),
+ .A2(_06776_),
+ .B1(_06775_),
+ .B2(_06774_),
+ .C(net743),
+ .ZN(_06778_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18610_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[9][19] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[8][19] ),
+ .S(net708),
+ .Z(_06779_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18611_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[11][19] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[10][19] ),
+ .S(net708),
+ .Z(_06780_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18612_ (.I0(_06779_),
+ .I1(_06780_),
+ .S(net670),
+ .Z(_06781_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _18613_ (.A1(_06781_),
+ .A2(net742),
+ .B(net648),
+ .C(_06778_),
+ .ZN(_06782_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _18614_ (.A1(_06773_),
+ .A2(_06782_),
+ .ZN(_06783_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18615_ (.I0(_06783_),
+ .I1(_06764_),
+ .S(net641),
+ .Z(_00042_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _18616_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[20][20] ),
+ .A2(net718),
+ .ZN(_06784_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _18617_ (.A1(net692),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[21][20] ),
+ .B(net676),
+ .ZN(_06785_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _18618_ (.A1(net692),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[23][20] ),
+ .ZN(_06786_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _18619_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[22][20] ),
+ .A2(net717),
+ .B(net662),
+ .ZN(_06787_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _18620_ (.A1(_06787_),
+ .A2(_06786_),
+ .B1(_06785_),
+ .B2(_06784_),
+ .C(net735),
+ .ZN(_06788_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18621_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[17][20] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[16][20] ),
+ .S(net692),
+ .Z(_06789_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18622_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[19][20] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[18][20] ),
+ .S(net692),
+ .Z(_06790_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18623_ (.I0(_06789_),
+ .I1(_06790_),
+ .S(net662),
+ .Z(_06791_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _18624_ (.A1(_06791_),
+ .A2(net735),
+ .B(net655),
+ .C(_06788_),
+ .ZN(_06792_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18625_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[25][20] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[24][20] ),
+ .S(net692),
+ .Z(_06793_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18626_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[27][20] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[26][20] ),
+ .S(net692),
+ .Z(_06794_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18627_ (.I0(_06793_),
+ .I1(_06794_),
+ .S(net662),
+ .Z(_06795_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _18628_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[28][20] ),
+ .A2(net718),
+ .ZN(_06796_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _18629_ (.A1(net692),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[29][20] ),
+ .B(net676),
+ .ZN(_06797_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _18630_ (.A1(net692),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[31][20] ),
+ .ZN(_06798_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _18631_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[30][20] ),
+ .A2(net718),
+ .B(net662),
+ .ZN(_06799_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _18632_ (.A1(_06799_),
+ .A2(_06798_),
+ .B1(_06797_),
+ .B2(_06796_),
+ .C(net735),
+ .ZN(_06800_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _18633_ (.A1(_06795_),
+ .A2(net735),
+ .B(net646),
+ .C(_06800_),
+ .ZN(_06801_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _18634_ (.A1(_06792_),
+ .A2(_06801_),
+ .ZN(_06802_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _18635_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[4][20] ),
+ .A2(net717),
+ .ZN(_06803_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _18636_ (.A1(net693),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[5][20] ),
+ .B(net676),
+ .ZN(_06804_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _18637_ (.A1(net692),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[7][20] ),
+ .ZN(_06805_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _18638_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[6][20] ),
+ .A2(net718),
+ .B(net662),
+ .ZN(_06806_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _18639_ (.A1(_06806_),
+ .A2(_06805_),
+ .B1(_06804_),
+ .B2(_06803_),
+ .C(net735),
+ .ZN(_06807_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18640_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[1][20] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[0][20] ),
+ .S(net692),
+ .Z(_06808_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18641_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[3][20] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[2][20] ),
+ .S(net693),
+ .Z(_06809_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18642_ (.I0(_06808_),
+ .I1(_06809_),
+ .S(net661),
+ .Z(_06810_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _18643_ (.A1(_06810_),
+ .A2(net734),
+ .B(net655),
+ .C(_06807_),
+ .ZN(_06811_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _18644_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[12][20] ),
+ .A2(net717),
+ .ZN(_06812_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _18645_ (.A1(net692),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[13][20] ),
+ .B(net676),
+ .ZN(_06813_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _18646_ (.A1(net693),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[15][20] ),
+ .ZN(_06814_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _18647_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[14][20] ),
+ .A2(net718),
+ .B(net662),
+ .ZN(_06815_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _18648_ (.A1(_06815_),
+ .A2(_06814_),
+ .B1(_06813_),
+ .B2(_06812_),
+ .C(net735),
+ .ZN(_06816_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18649_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[9][20] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[8][20] ),
+ .S(net693),
+ .Z(_06817_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18650_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[11][20] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[10][20] ),
+ .S(net692),
+ .Z(_06818_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18651_ (.I0(_06817_),
+ .I1(_06818_),
+ .S(net662),
+ .Z(_06819_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _18652_ (.A1(_06819_),
+ .A2(net735),
+ .B(net646),
+ .C(_06816_),
+ .ZN(_06820_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _18653_ (.A1(_06811_),
+ .A2(_06820_),
+ .ZN(_06821_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18654_ (.I0(_06821_),
+ .I1(_06802_),
+ .S(net643),
+ .Z(_00044_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _18655_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[20][21] ),
+ .A2(net723),
+ .ZN(_06822_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _18656_ (.A1(net702),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[21][21] ),
+ .B(net678),
+ .ZN(_06823_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _18657_ (.A1(net702),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[23][21] ),
+ .ZN(_06824_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _18658_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[22][21] ),
+ .A2(net723),
+ .B(net667),
+ .ZN(_06825_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _18659_ (.A1(_06825_),
+ .A2(_06824_),
+ .B1(_06823_),
+ .B2(_06822_),
+ .C(net740),
+ .ZN(_06826_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18660_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[17][21] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[16][21] ),
+ .S(net702),
+ .Z(_06827_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18661_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[19][21] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[18][21] ),
+ .S(net702),
+ .Z(_06828_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18662_ (.I0(_06827_),
+ .I1(_06828_),
+ .S(net667),
+ .Z(_06829_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _18663_ (.A1(_06829_),
+ .A2(net740),
+ .B(net652),
+ .C(_06826_),
+ .ZN(_06830_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18664_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[25][21] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[24][21] ),
+ .S(net703),
+ .Z(_06831_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18665_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[27][21] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[26][21] ),
+ .S(net708),
+ .Z(_06832_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18666_ (.I0(_06831_),
+ .I1(_06832_),
+ .S(net667),
+ .Z(_06833_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _18667_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[28][21] ),
+ .A2(net725),
+ .ZN(_06834_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _18668_ (.A1(net708),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[29][21] ),
+ .B(net680),
+ .ZN(_06835_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _18669_ (.A1(net708),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[31][21] ),
+ .ZN(_06836_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _18670_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[30][21] ),
+ .A2(net725),
+ .B(net670),
+ .ZN(_06837_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _18671_ (.A1(_06837_),
+ .A2(_06836_),
+ .B1(_06835_),
+ .B2(_06834_),
+ .C(net742),
+ .ZN(_06838_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _18672_ (.A1(_06833_),
+ .A2(net742),
+ .B(net649),
+ .C(_06838_),
+ .ZN(_06839_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _18673_ (.A1(_06830_),
+ .A2(_06839_),
+ .ZN(_06840_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _18674_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[4][21] ),
+ .A2(net725),
+ .ZN(_06841_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _18675_ (.A1(net708),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[5][21] ),
+ .B(net680),
+ .ZN(_06842_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _18676_ (.A1(net703),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[7][21] ),
+ .ZN(_06843_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _18677_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[6][21] ),
+ .A2(net725),
+ .B(net670),
+ .ZN(_06844_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _18678_ (.A1(_06844_),
+ .A2(_06843_),
+ .B1(_06842_),
+ .B2(_06841_),
+ .C(net742),
+ .ZN(_06845_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18679_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[1][21] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[0][21] ),
+ .S(net703),
+ .Z(_06846_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18680_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[3][21] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[2][21] ),
+ .S(net703),
+ .Z(_06847_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18681_ (.I0(_06846_),
+ .I1(_06847_),
+ .S(net667),
+ .Z(_06848_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _18682_ (.A1(_06848_),
+ .A2(net740),
+ .B(net656),
+ .C(_06845_),
+ .ZN(_06849_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _18683_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[12][21] ),
+ .A2(net722),
+ .ZN(_06850_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _18684_ (.A1(net701),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[13][21] ),
+ .B(net678),
+ .ZN(_06851_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _18685_ (.A1(net701),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[15][21] ),
+ .ZN(_06852_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _18686_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[14][21] ),
+ .A2(net722),
+ .B(net665),
+ .ZN(_06853_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _18687_ (.A1(_06853_),
+ .A2(_06852_),
+ .B1(_06851_),
+ .B2(_06850_),
+ .C(net739),
+ .ZN(_06854_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18688_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[9][21] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[8][21] ),
+ .S(net705),
+ .Z(_06855_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18689_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[11][21] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[10][21] ),
+ .S(net705),
+ .Z(_06856_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18690_ (.I0(_06855_),
+ .I1(_06856_),
+ .S(net668),
+ .Z(_06857_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _18691_ (.A1(_06857_),
+ .A2(net739),
+ .B(net649),
+ .C(_06854_),
+ .ZN(_06858_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _18692_ (.A1(_06849_),
+ .A2(_06858_),
+ .ZN(_06859_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18693_ (.I0(_06859_),
+ .I1(_06840_),
+ .S(_06032_),
+ .Z(_00045_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _18694_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[20][22] ),
+ .A2(net725),
+ .ZN(_06860_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _18695_ (.A1(net708),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[21][22] ),
+ .B(net679),
+ .ZN(_06861_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _18696_ (.A1(net708),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[23][22] ),
+ .ZN(_06862_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _18697_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[22][22] ),
+ .A2(net725),
+ .B(net670),
+ .ZN(_06863_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _18698_ (.A1(_06863_),
+ .A2(_06862_),
+ .B1(_06861_),
+ .B2(_06860_),
+ .C(net742),
+ .ZN(_06864_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18699_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[17][22] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[16][22] ),
+ .S(net708),
+ .Z(_06865_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18700_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[19][22] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[18][22] ),
+ .S(net708),
+ .Z(_06866_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18701_ (.I0(_06865_),
+ .I1(_06866_),
+ .S(net670),
+ .Z(_06867_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _18702_ (.A1(_06867_),
+ .A2(net742),
+ .B(net652),
+ .C(_06864_),
+ .ZN(_06868_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18703_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[25][22] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[24][22] ),
+ .S(net708),
+ .Z(_06869_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18704_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[27][22] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[26][22] ),
+ .S(net711),
+ .Z(_06870_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18705_ (.I0(_06869_),
+ .I1(_06870_),
+ .S(net670),
+ .Z(_06871_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _18706_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[28][22] ),
+ .A2(net725),
+ .ZN(_06872_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _18707_ (.A1(net708),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[29][22] ),
+ .B(net679),
+ .ZN(_06873_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _18708_ (.A1(net708),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[31][22] ),
+ .ZN(_06874_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _18709_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[30][22] ),
+ .A2(net725),
+ .B(net670),
+ .ZN(_06875_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _18710_ (.A1(_06875_),
+ .A2(_06874_),
+ .B1(_06873_),
+ .B2(_06872_),
+ .C(net742),
+ .ZN(_06876_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _18711_ (.A1(_06871_),
+ .A2(net742),
+ .B(net648),
+ .C(_06876_),
+ .ZN(_06877_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _18712_ (.A1(_06868_),
+ .A2(_06877_),
+ .ZN(_06878_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18713_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[1][22] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[0][22] ),
+ .S(net708),
+ .Z(_06879_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18714_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[3][22] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[2][22] ),
+ .S(net708),
+ .Z(_06880_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18715_ (.I0(_06879_),
+ .I1(_06880_),
+ .S(net670),
+ .Z(_06881_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _18716_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[4][22] ),
+ .A2(net725),
+ .ZN(_06882_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _18717_ (.A1(net708),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[5][22] ),
+ .B(net679),
+ .ZN(_06883_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _18718_ (.A1(net708),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[7][22] ),
+ .ZN(_06884_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _18719_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[6][22] ),
+ .A2(net725),
+ .B(net670),
+ .ZN(_06885_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _18720_ (.A1(_06885_),
+ .A2(_06884_),
+ .B1(_06883_),
+ .B2(_06882_),
+ .C(net742),
+ .ZN(_06886_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _18721_ (.A1(_06881_),
+ .A2(net742),
+ .B(net652),
+ .C(_06886_),
+ .ZN(_06887_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _18722_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[12][22] ),
+ .A2(net725),
+ .ZN(_06888_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _18723_ (.A1(net705),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[13][22] ),
+ .B(net679),
+ .ZN(_06889_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _18724_ (.A1(net708),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[15][22] ),
+ .ZN(_06890_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _18725_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[14][22] ),
+ .A2(net725),
+ .B(net670),
+ .ZN(_06891_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _18726_ (.A1(_06891_),
+ .A2(_06890_),
+ .B1(_06889_),
+ .B2(_06888_),
+ .C(net742),
+ .ZN(_06892_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18727_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[9][22] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[8][22] ),
+ .S(net708),
+ .Z(_06893_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18728_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[11][22] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[10][22] ),
+ .S(net708),
+ .Z(_06894_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18729_ (.I0(_06893_),
+ .I1(_06894_),
+ .S(net668),
+ .Z(_06895_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _18730_ (.A1(_06895_),
+ .A2(net742),
+ .B(net648),
+ .C(_06892_),
+ .ZN(_06896_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _18731_ (.A1(_06887_),
+ .A2(_06896_),
+ .ZN(_06897_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18732_ (.I0(_06897_),
+ .I1(_06878_),
+ .S(_06032_),
+ .Z(_00046_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _18733_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[20][23] ),
+ .A2(net719),
+ .ZN(_06898_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _18734_ (.A1(net695),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[21][23] ),
+ .B(net676),
+ .ZN(_06899_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _18735_ (.A1(net695),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[23][23] ),
+ .ZN(_06900_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _18736_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[22][23] ),
+ .A2(net719),
+ .B(net664),
+ .ZN(_06901_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _18737_ (.A1(_06901_),
+ .A2(_06900_),
+ .B1(_06899_),
+ .B2(_06898_),
+ .C(net737),
+ .ZN(_06902_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18738_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[17][23] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[16][23] ),
+ .S(net694),
+ .Z(_06903_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18739_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[19][23] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[18][23] ),
+ .S(net694),
+ .Z(_06904_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18740_ (.I0(_06903_),
+ .I1(_06904_),
+ .S(net663),
+ .Z(_06905_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _18741_ (.A1(_06905_),
+ .A2(net736),
+ .B(net655),
+ .C(_06902_),
+ .ZN(_06906_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18742_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[25][23] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[24][23] ),
+ .S(net696),
+ .Z(_06907_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18743_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[27][23] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[26][23] ),
+ .S(net697),
+ .Z(_06908_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18744_ (.I0(_06907_),
+ .I1(_06908_),
+ .S(net663),
+ .Z(_06909_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _18745_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[28][23] ),
+ .A2(net719),
+ .ZN(_06910_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _18746_ (.A1(net695),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[29][23] ),
+ .B(net677),
+ .ZN(_06911_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _18747_ (.A1(net696),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[31][23] ),
+ .ZN(_06912_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _18748_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[30][23] ),
+ .A2(net719),
+ .B(net663),
+ .ZN(_06913_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _18749_ (.A1(_06913_),
+ .A2(_06912_),
+ .B1(_06911_),
+ .B2(_06910_),
+ .C(net737),
+ .ZN(_06914_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _18750_ (.A1(_06909_),
+ .A2(net737),
+ .B(net646),
+ .C(_06914_),
+ .ZN(_06915_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _18751_ (.A1(_06906_),
+ .A2(_06915_),
+ .ZN(_06916_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _18752_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[4][23] ),
+ .A2(net720),
+ .ZN(_06917_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _18753_ (.A1(net694),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[5][23] ),
+ .B(net677),
+ .ZN(_06918_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _18754_ (.A1(net706),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[7][23] ),
+ .ZN(_06919_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _18755_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[6][23] ),
+ .A2(net719),
+ .B(net663),
+ .ZN(_06920_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _18756_ (.A1(_06920_),
+ .A2(_06919_),
+ .B1(_06918_),
+ .B2(_06917_),
+ .C(net736),
+ .ZN(_06921_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18757_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[1][23] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[0][23] ),
+ .S(net695),
+ .Z(_06922_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18758_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[3][23] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[2][23] ),
+ .S(net695),
+ .Z(_06923_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18759_ (.I0(_06922_),
+ .I1(_06923_),
+ .S(net663),
+ .Z(_06924_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _18760_ (.A1(_06924_),
+ .A2(net736),
+ .B(net654),
+ .C(_06921_),
+ .ZN(_06925_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _18761_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[12][23] ),
+ .A2(net720),
+ .ZN(_06926_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _18762_ (.A1(net694),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[13][23] ),
+ .B(net677),
+ .ZN(_06927_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _18763_ (.A1(net697),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[15][23] ),
+ .ZN(_06928_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _18764_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[14][23] ),
+ .A2(net720),
+ .B(net663),
+ .ZN(_06929_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _18765_ (.A1(_06929_),
+ .A2(_06928_),
+ .B1(_06927_),
+ .B2(_06926_),
+ .C(net736),
+ .ZN(_06930_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18766_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[9][23] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[8][23] ),
+ .S(net696),
+ .Z(_06931_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18767_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[11][23] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[10][23] ),
+ .S(net697),
+ .Z(_06932_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18768_ (.I0(_06931_),
+ .I1(_06932_),
+ .S(net663),
+ .Z(_06933_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _18769_ (.A1(_06933_),
+ .A2(net736),
+ .B(net646),
+ .C(_06930_),
+ .ZN(_06934_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _18770_ (.A1(_06925_),
+ .A2(_06934_),
+ .ZN(_06935_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18771_ (.I0(_06935_),
+ .I1(_06916_),
+ .S(net644),
+ .Z(_00047_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _18772_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[20][24] ),
+ .A2(net724),
+ .ZN(_06936_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _18773_ (.A1(net704),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[21][24] ),
+ .B(net679),
+ .ZN(_06937_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _18774_ (.A1(net704),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[23][24] ),
+ .ZN(_06938_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _18775_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[22][24] ),
+ .A2(net724),
+ .B(net668),
+ .ZN(_06939_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _18776_ (.A1(_06939_),
+ .A2(_06938_),
+ .B1(_06937_),
+ .B2(_06936_),
+ .C(net741),
+ .ZN(_06940_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18777_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[17][24] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[16][24] ),
+ .S(net704),
+ .Z(_06941_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18778_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[19][24] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[18][24] ),
+ .S(net704),
+ .Z(_06942_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18779_ (.I0(_06941_),
+ .I1(_06942_),
+ .S(net668),
+ .Z(_06943_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _18780_ (.A1(_06943_),
+ .A2(net741),
+ .B(net654),
+ .C(_06940_),
+ .ZN(_06944_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18781_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[25][24] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[24][24] ),
+ .S(net704),
+ .Z(_06945_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18782_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[27][24] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[26][24] ),
+ .S(net704),
+ .Z(_06946_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18783_ (.I0(_06945_),
+ .I1(_06946_),
+ .S(net668),
+ .Z(_06947_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _18784_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[28][24] ),
+ .A2(net724),
+ .ZN(_06948_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _18785_ (.A1(net704),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[29][24] ),
+ .B(net679),
+ .ZN(_06949_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _18786_ (.A1(net704),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[31][24] ),
+ .ZN(_06950_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _18787_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[30][24] ),
+ .A2(net724),
+ .B(net668),
+ .ZN(_06951_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _18788_ (.A1(_06951_),
+ .A2(_06950_),
+ .B1(_06949_),
+ .B2(_06948_),
+ .C(net741),
+ .ZN(_06952_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _18789_ (.A1(_06947_),
+ .A2(net741),
+ .B(net649),
+ .C(_06952_),
+ .ZN(_06953_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _18790_ (.A1(_06944_),
+ .A2(_06953_),
+ .ZN(_06954_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _18791_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[4][24] ),
+ .A2(net724),
+ .ZN(_06955_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _18792_ (.A1(net704),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[5][24] ),
+ .B(net679),
+ .ZN(_06956_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _18793_ (.A1(net704),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[7][24] ),
+ .ZN(_06957_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _18794_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[6][24] ),
+ .A2(net724),
+ .B(net668),
+ .ZN(_06958_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _18795_ (.A1(_06958_),
+ .A2(_06957_),
+ .B1(_06956_),
+ .B2(_06955_),
+ .C(net741),
+ .ZN(_06959_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18796_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[1][24] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[0][24] ),
+ .S(net704),
+ .Z(_06960_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18797_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[3][24] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[2][24] ),
+ .S(net704),
+ .Z(_06961_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18798_ (.I0(_06960_),
+ .I1(_06961_),
+ .S(net668),
+ .Z(_06962_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _18799_ (.A1(_06962_),
+ .A2(net741),
+ .B(net654),
+ .C(_06959_),
+ .ZN(_06963_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _18800_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[12][24] ),
+ .A2(net720),
+ .ZN(_06964_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _18801_ (.A1(net697),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[13][24] ),
+ .B(net676),
+ .ZN(_06965_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _18802_ (.A1(net704),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[15][24] ),
+ .ZN(_06966_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _18803_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[14][24] ),
+ .A2(net720),
+ .B(net663),
+ .ZN(_06967_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _18804_ (.A1(_06967_),
+ .A2(_06966_),
+ .B1(_06965_),
+ .B2(_06964_),
+ .C(net736),
+ .ZN(_06968_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18805_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[9][24] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[8][24] ),
+ .S(net704),
+ .Z(_06969_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18806_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[11][24] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[10][24] ),
+ .S(net704),
+ .Z(_06970_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18807_ (.I0(_06969_),
+ .I1(_06970_),
+ .S(net663),
+ .Z(_06971_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _18808_ (.A1(_06971_),
+ .A2(net741),
+ .B(net649),
+ .C(_06968_),
+ .ZN(_06972_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _18809_ (.A1(_06963_),
+ .A2(_06972_),
+ .ZN(_06973_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18810_ (.I0(_06973_),
+ .I1(_06954_),
+ .S(_06032_),
+ .Z(_00048_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _18811_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[20][25] ),
+ .A2(net724),
+ .ZN(_06974_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _18812_ (.A1(net705),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[21][25] ),
+ .B(net679),
+ .ZN(_06975_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _18813_ (.A1(net705),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[23][25] ),
+ .ZN(_06976_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _18814_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[22][25] ),
+ .A2(net724),
+ .B(net668),
+ .ZN(_06977_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _18815_ (.A1(_06977_),
+ .A2(_06976_),
+ .B1(_06975_),
+ .B2(_06974_),
+ .C(net741),
+ .ZN(_06978_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18816_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[17][25] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[16][25] ),
+ .S(net705),
+ .Z(_06979_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18817_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[19][25] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[18][25] ),
+ .S(net705),
+ .Z(_06980_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18818_ (.I0(_06979_),
+ .I1(_06980_),
+ .S(net668),
+ .Z(_06981_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _18819_ (.A1(_06981_),
+ .A2(net741),
+ .B(net656),
+ .C(_06978_),
+ .ZN(_06982_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18820_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[25][25] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[24][25] ),
+ .S(net705),
+ .Z(_06983_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18821_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[27][25] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[26][25] ),
+ .S(net705),
+ .Z(_06984_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18822_ (.I0(_06983_),
+ .I1(_06984_),
+ .S(net668),
+ .Z(_06985_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _18823_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[28][25] ),
+ .A2(net724),
+ .ZN(_06986_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _18824_ (.A1(net705),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[29][25] ),
+ .B(net679),
+ .ZN(_06987_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _18825_ (.A1(net705),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[31][25] ),
+ .ZN(_06988_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _18826_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[30][25] ),
+ .A2(net724),
+ .B(net668),
+ .ZN(_06989_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _18827_ (.A1(_06989_),
+ .A2(_06988_),
+ .B1(_06987_),
+ .B2(_06986_),
+ .C(net741),
+ .ZN(_06990_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _18828_ (.A1(_06985_),
+ .A2(net741),
+ .B(net650),
+ .C(_06990_),
+ .ZN(_06991_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _18829_ (.A1(_06982_),
+ .A2(_06991_),
+ .ZN(_06992_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _18830_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[4][25] ),
+ .A2(net724),
+ .ZN(_06993_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _18831_ (.A1(net704),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[5][25] ),
+ .B(net679),
+ .ZN(_06994_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _18832_ (.A1(net704),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[7][25] ),
+ .ZN(_06995_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _18833_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[6][25] ),
+ .A2(net724),
+ .B(net668),
+ .ZN(_06996_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _18834_ (.A1(_06996_),
+ .A2(_06995_),
+ .B1(_06994_),
+ .B2(_06993_),
+ .C(net741),
+ .ZN(_06997_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18835_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[1][25] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[0][25] ),
+ .S(net705),
+ .Z(_06998_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18836_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[3][25] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[2][25] ),
+ .S(net705),
+ .Z(_06999_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18837_ (.I0(_06998_),
+ .I1(_06999_),
+ .S(net668),
+ .Z(_07000_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _18838_ (.A1(_07000_),
+ .A2(net741),
+ .B(net654),
+ .C(_06997_),
+ .ZN(_07001_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _18839_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[12][25] ),
+ .A2(net724),
+ .ZN(_07002_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _18840_ (.A1(net706),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[13][25] ),
+ .B(net679),
+ .ZN(_07003_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _18841_ (.A1(net707),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[15][25] ),
+ .ZN(_07004_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _18842_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[14][25] ),
+ .A2(net724),
+ .B(net668),
+ .ZN(_07005_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _18843_ (.A1(_07005_),
+ .A2(_07004_),
+ .B1(_07003_),
+ .B2(_07002_),
+ .C(net744),
+ .ZN(_07006_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18844_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[9][25] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[8][25] ),
+ .S(net704),
+ .Z(_07007_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18845_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[11][25] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[10][25] ),
+ .S(net704),
+ .Z(_07008_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18846_ (.I0(_07007_),
+ .I1(_07008_),
+ .S(net668),
+ .Z(_07009_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _18847_ (.A1(_07009_),
+ .A2(net741),
+ .B(net650),
+ .C(_07006_),
+ .ZN(_07010_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _18848_ (.A1(_07001_),
+ .A2(_07010_),
+ .ZN(_07011_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18849_ (.I0(_07011_),
+ .I1(_06992_),
+ .S(_06032_),
+ .Z(_00049_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _18850_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[20][26] ),
+ .A2(net725),
+ .ZN(_07012_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _18851_ (.A1(net709),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[21][26] ),
+ .B(net680),
+ .ZN(_07013_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _18852_ (.A1(net710),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[23][26] ),
+ .ZN(_07014_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _18853_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[22][26] ),
+ .A2(net725),
+ .B(net671),
+ .ZN(_07015_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _18854_ (.A1(_07015_),
+ .A2(_07014_),
+ .B1(_07013_),
+ .B2(_07012_),
+ .C(net743),
+ .ZN(_07016_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18855_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[17][26] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[16][26] ),
+ .S(net710),
+ .Z(_07017_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18856_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[19][26] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[18][26] ),
+ .S(net710),
+ .Z(_07018_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18857_ (.I0(_07017_),
+ .I1(_07018_),
+ .S(net671),
+ .Z(_07019_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _18858_ (.A1(_07019_),
+ .A2(net743),
+ .B(net656),
+ .C(_07016_),
+ .ZN(_07020_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18859_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[25][26] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[24][26] ),
+ .S(net709),
+ .Z(_07021_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18860_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[27][26] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[26][26] ),
+ .S(net709),
+ .Z(_07022_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18861_ (.I0(_07021_),
+ .I1(_07022_),
+ .S(net671),
+ .Z(_07023_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _18862_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[28][26] ),
+ .A2(net725),
+ .ZN(_07024_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _18863_ (.A1(net709),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[29][26] ),
+ .B(net680),
+ .ZN(_07025_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _18864_ (.A1(net709),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[31][26] ),
+ .ZN(_07026_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _18865_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[30][26] ),
+ .A2(net725),
+ .B(net671),
+ .ZN(_07027_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _18866_ (.A1(_07027_),
+ .A2(_07026_),
+ .B1(_07025_),
+ .B2(_07024_),
+ .C(net743),
+ .ZN(_07028_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _18867_ (.A1(_07023_),
+ .A2(net743),
+ .B(net650),
+ .C(_07028_),
+ .ZN(_07029_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _18868_ (.A1(_07020_),
+ .A2(_07029_),
+ .ZN(_07030_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _18869_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[4][26] ),
+ .A2(net727),
+ .ZN(_07031_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _18870_ (.A1(net706),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[5][26] ),
+ .B(net680),
+ .ZN(_07032_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _18871_ (.A1(net709),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[7][26] ),
+ .ZN(_07033_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _18872_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[6][26] ),
+ .A2(net726),
+ .B(net671),
+ .ZN(_07034_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _18873_ (.A1(_07034_),
+ .A2(_07033_),
+ .B1(_07032_),
+ .B2(_07031_),
+ .C(net743),
+ .ZN(_07035_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18874_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[1][26] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[0][26] ),
+ .S(net709),
+ .Z(_07036_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18875_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[3][26] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[2][26] ),
+ .S(net707),
+ .Z(_07037_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18876_ (.I0(_07036_),
+ .I1(_07037_),
+ .S(net669),
+ .Z(_07038_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _18877_ (.A1(_07038_),
+ .A2(net743),
+ .B(net656),
+ .C(_07035_),
+ .ZN(_07039_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _18878_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[12][26] ),
+ .A2(net724),
+ .ZN(_07040_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _18879_ (.A1(net707),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[13][26] ),
+ .B(net680),
+ .ZN(_07041_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _18880_ (.A1(net709),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[15][26] ),
+ .ZN(_07042_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _18881_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[14][26] ),
+ .A2(net726),
+ .B(net671),
+ .ZN(_07043_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _18882_ (.A1(_07043_),
+ .A2(_07042_),
+ .B1(_07041_),
+ .B2(_07040_),
+ .C(net743),
+ .ZN(_07044_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18883_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[9][26] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[8][26] ),
+ .S(net709),
+ .Z(_07045_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18884_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[11][26] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[10][26] ),
+ .S(net707),
+ .Z(_07046_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18885_ (.I0(_07045_),
+ .I1(_07046_),
+ .S(net668),
+ .Z(_07047_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _18886_ (.A1(_07047_),
+ .A2(net743),
+ .B(net650),
+ .C(_07044_),
+ .ZN(_07048_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _18887_ (.A1(_07039_),
+ .A2(_07048_),
+ .ZN(_07049_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18888_ (.I0(_07049_),
+ .I1(_07030_),
+ .S(_06032_),
+ .Z(_00050_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _18889_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[20][27] ),
+ .A2(net726),
+ .ZN(_07050_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _18890_ (.A1(net709),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[21][27] ),
+ .B(net680),
+ .ZN(_07051_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _18891_ (.A1(net710),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[23][27] ),
+ .ZN(_07052_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _18892_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[22][27] ),
+ .A2(net726),
+ .B(net670),
+ .ZN(_07053_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _18893_ (.A1(_07053_),
+ .A2(_07052_),
+ .B1(_07051_),
+ .B2(_07050_),
+ .C(net742),
+ .ZN(_07054_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18894_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[17][27] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[16][27] ),
+ .S(net710),
+ .Z(_07055_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18895_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[19][27] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[18][27] ),
+ .S(net710),
+ .Z(_07056_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18896_ (.I0(_07055_),
+ .I1(_07056_),
+ .S(net670),
+ .Z(_07057_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _18897_ (.A1(_07057_),
+ .A2(net742),
+ .B(net656),
+ .C(_07054_),
+ .ZN(_07058_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18898_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[25][27] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[24][27] ),
+ .S(net710),
+ .Z(_07059_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18899_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[27][27] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[26][27] ),
+ .S(net710),
+ .Z(_07060_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18900_ (.I0(_07059_),
+ .I1(_07060_),
+ .S(net670),
+ .Z(_07061_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _18901_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[28][27] ),
+ .A2(net726),
+ .ZN(_07062_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _18902_ (.A1(net710),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[29][27] ),
+ .B(net680),
+ .ZN(_07063_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _18903_ (.A1(net710),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[31][27] ),
+ .ZN(_07064_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _18904_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[30][27] ),
+ .A2(net725),
+ .B(net670),
+ .ZN(_07065_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _18905_ (.A1(_07065_),
+ .A2(_07064_),
+ .B1(_07063_),
+ .B2(_07062_),
+ .C(net742),
+ .ZN(_07066_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _18906_ (.A1(_07061_),
+ .A2(net742),
+ .B(net650),
+ .C(_07066_),
+ .ZN(_07067_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _18907_ (.A1(_07058_),
+ .A2(_07067_),
+ .ZN(_07068_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _18908_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[4][27] ),
+ .A2(net726),
+ .ZN(_07069_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _18909_ (.A1(net709),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[5][27] ),
+ .B(net680),
+ .ZN(_07070_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _18910_ (.A1(net709),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[7][27] ),
+ .ZN(_07071_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _18911_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[6][27] ),
+ .A2(net726),
+ .B(net671),
+ .ZN(_07072_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _18912_ (.A1(_07072_),
+ .A2(_07071_),
+ .B1(_07070_),
+ .B2(_07069_),
+ .C(net743),
+ .ZN(_07073_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18913_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[1][27] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[0][27] ),
+ .S(net709),
+ .Z(_07074_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18914_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[3][27] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[2][27] ),
+ .S(net709),
+ .Z(_07075_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18915_ (.I0(_07074_),
+ .I1(_07075_),
+ .S(net670),
+ .Z(_07076_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _18916_ (.A1(_07076_),
+ .A2(net743),
+ .B(net652),
+ .C(_07073_),
+ .ZN(_07077_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _18917_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[12][27] ),
+ .A2(net726),
+ .ZN(_07078_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _18918_ (.A1(net709),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[13][27] ),
+ .B(net680),
+ .ZN(_07079_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _18919_ (.A1(net709),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[15][27] ),
+ .ZN(_07080_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _18920_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[14][27] ),
+ .A2(net726),
+ .B(net671),
+ .ZN(_07081_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _18921_ (.A1(_07081_),
+ .A2(_07080_),
+ .B1(_07079_),
+ .B2(_07078_),
+ .C(net743),
+ .ZN(_07082_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18922_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[9][27] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[8][27] ),
+ .S(net709),
+ .Z(_07083_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18923_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[11][27] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[10][27] ),
+ .S(net709),
+ .Z(_07084_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18924_ (.I0(_07083_),
+ .I1(_07084_),
+ .S(net671),
+ .Z(_07085_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _18925_ (.A1(_07085_),
+ .A2(net743),
+ .B(net648),
+ .C(_07082_),
+ .ZN(_07086_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _18926_ (.A1(_07077_),
+ .A2(_07086_),
+ .ZN(_07087_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18927_ (.I0(_07087_),
+ .I1(_07068_),
+ .S(_06032_),
+ .Z(_00051_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _18928_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[20][28] ),
+ .A2(net724),
+ .ZN(_07088_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _18929_ (.A1(net706),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[21][28] ),
+ .B(net679),
+ .ZN(_07089_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _18930_ (.A1(net707),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[23][28] ),
+ .ZN(_07090_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _18931_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[22][28] ),
+ .A2(net724),
+ .B(net668),
+ .ZN(_07091_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _18932_ (.A1(_07091_),
+ .A2(_07090_),
+ .B1(_07089_),
+ .B2(_07088_),
+ .C(net741),
+ .ZN(_07092_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18933_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[17][28] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[16][28] ),
+ .S(net707),
+ .Z(_07093_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18934_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[19][28] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[18][28] ),
+ .S(net706),
+ .Z(_07094_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18935_ (.I0(_07093_),
+ .I1(_07094_),
+ .S(net669),
+ .Z(_07095_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _18936_ (.A1(_07095_),
+ .A2(net741),
+ .B(net652),
+ .C(_07092_),
+ .ZN(_07096_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18937_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[25][28] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[24][28] ),
+ .S(net707),
+ .Z(_07097_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18938_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[27][28] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[26][28] ),
+ .S(net706),
+ .Z(_07098_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18939_ (.I0(_07097_),
+ .I1(_07098_),
+ .S(net669),
+ .Z(_07099_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _18940_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[28][28] ),
+ .A2(net724),
+ .ZN(_07100_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _18941_ (.A1(net707),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[29][28] ),
+ .B(net679),
+ .ZN(_07101_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _18942_ (.A1(net707),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[31][28] ),
+ .ZN(_07102_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _18943_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[30][28] ),
+ .A2(net724),
+ .B(net669),
+ .ZN(_07103_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _18944_ (.A1(_07103_),
+ .A2(_07102_),
+ .B1(_07101_),
+ .B2(_07100_),
+ .C(net744),
+ .ZN(_07104_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _18945_ (.A1(_07099_),
+ .A2(net744),
+ .B(net648),
+ .C(_07104_),
+ .ZN(_07105_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _18946_ (.A1(_07096_),
+ .A2(_07105_),
+ .ZN(_07106_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _18947_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[4][28] ),
+ .A2(net727),
+ .ZN(_07107_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _18948_ (.A1(net707),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[5][28] ),
+ .B(net679),
+ .ZN(_07108_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _18949_ (.A1(net707),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[7][28] ),
+ .ZN(_07109_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _18950_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[6][28] ),
+ .A2(net727),
+ .B(net669),
+ .ZN(_07110_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _18951_ (.A1(_07110_),
+ .A2(_07109_),
+ .B1(_07108_),
+ .B2(_07107_),
+ .C(net744),
+ .ZN(_07111_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18952_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[1][28] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[0][28] ),
+ .S(net707),
+ .Z(_07112_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18953_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[3][28] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[2][28] ),
+ .S(net707),
+ .Z(_07113_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18954_ (.I0(_07112_),
+ .I1(_07113_),
+ .S(net669),
+ .Z(_07114_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _18955_ (.A1(_07114_),
+ .A2(net744),
+ .B(net652),
+ .C(_07111_),
+ .ZN(_07115_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _18956_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[12][28] ),
+ .A2(net727),
+ .ZN(_07116_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _18957_ (.A1(net706),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[13][28] ),
+ .B(net679),
+ .ZN(_07117_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _18958_ (.A1(net706),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[15][28] ),
+ .ZN(_07118_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _18959_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[14][28] ),
+ .A2(net727),
+ .B(net669),
+ .ZN(_07119_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _18960_ (.A1(_07119_),
+ .A2(_07118_),
+ .B1(_07117_),
+ .B2(_07116_),
+ .C(net744),
+ .ZN(_07120_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18961_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[9][28] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[8][28] ),
+ .S(net706),
+ .Z(_07121_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18962_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[11][28] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[10][28] ),
+ .S(net706),
+ .Z(_07122_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18963_ (.I0(_07121_),
+ .I1(_07122_),
+ .S(net669),
+ .Z(_07123_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _18964_ (.A1(_07123_),
+ .A2(net744),
+ .B(net648),
+ .C(_07120_),
+ .ZN(_07124_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _18965_ (.A1(_07115_),
+ .A2(_07124_),
+ .ZN(_07125_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18966_ (.I0(_07125_),
+ .I1(_07106_),
+ .S(_06032_),
+ .Z(_00052_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _18967_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[20][29] ),
+ .A2(net720),
+ .ZN(_07126_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _18968_ (.A1(net694),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[21][29] ),
+ .B(net677),
+ .ZN(_07127_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _18969_ (.A1(net694),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[23][29] ),
+ .ZN(_07128_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _18970_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[22][29] ),
+ .A2(net720),
+ .B(net663),
+ .ZN(_07129_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _18971_ (.A1(_07129_),
+ .A2(_07128_),
+ .B1(_07127_),
+ .B2(_07126_),
+ .C(net736),
+ .ZN(_07130_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18972_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[17][29] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[16][29] ),
+ .S(net694),
+ .Z(_07131_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18973_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[19][29] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[18][29] ),
+ .S(net694),
+ .Z(_07132_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18974_ (.I0(_07131_),
+ .I1(_07132_),
+ .S(net661),
+ .Z(_07133_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _18975_ (.A1(_07133_),
+ .A2(net736),
+ .B(net655),
+ .C(_07130_),
+ .ZN(_07134_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18976_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[25][29] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[24][29] ),
+ .S(net694),
+ .Z(_07135_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18977_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[27][29] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[26][29] ),
+ .S(net691),
+ .Z(_07136_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18978_ (.I0(_07135_),
+ .I1(_07136_),
+ .S(net661),
+ .Z(_07137_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _18979_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[28][29] ),
+ .A2(net719),
+ .ZN(_07138_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _18980_ (.A1(net695),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[29][29] ),
+ .B(net677),
+ .ZN(_07139_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _18981_ (.A1(net694),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[31][29] ),
+ .ZN(_07140_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _18982_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[30][29] ),
+ .A2(net719),
+ .B(net663),
+ .ZN(_07141_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _18983_ (.A1(_07141_),
+ .A2(_07140_),
+ .B1(_07139_),
+ .B2(_07138_),
+ .C(net736),
+ .ZN(_07142_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _18984_ (.A1(_07137_),
+ .A2(net736),
+ .B(net646),
+ .C(_07142_),
+ .ZN(_07143_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _18985_ (.A1(_07134_),
+ .A2(_07143_),
+ .ZN(_07144_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18986_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[1][29] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[0][29] ),
+ .S(net697),
+ .Z(_07145_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18987_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[3][29] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[2][29] ),
+ .S(net694),
+ .Z(_07146_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _18988_ (.I0(_07145_),
+ .I1(_07146_),
+ .S(net663),
+ .Z(_07147_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _18989_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[4][29] ),
+ .A2(net720),
+ .ZN(_07148_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _18990_ (.A1(net697),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[5][29] ),
+ .B(net677),
+ .ZN(_07149_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _18991_ (.A1(net694),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[7][29] ),
+ .ZN(_07150_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _18992_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[6][29] ),
+ .A2(net720),
+ .B(net663),
+ .ZN(_07151_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _18993_ (.A1(_07151_),
+ .A2(_07150_),
+ .B1(_07149_),
+ .B2(_07148_),
+ .C(net736),
+ .ZN(_07152_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _18994_ (.A1(_07147_),
+ .A2(net736),
+ .B(net655),
+ .C(_07152_),
+ .ZN(_07153_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _18995_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[12][29] ),
+ .A2(net720),
+ .ZN(_07154_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _18996_ (.A1(net694),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[13][29] ),
+ .B(net677),
+ .ZN(_07155_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _18997_ (.A1(net694),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[15][29] ),
+ .ZN(_07156_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _18998_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[14][29] ),
+ .A2(net720),
+ .B(net663),
+ .ZN(_07157_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _18999_ (.A1(_07157_),
+ .A2(_07156_),
+ .B1(_07155_),
+ .B2(_07154_),
+ .C(net736),
+ .ZN(_07158_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19000_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[9][29] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[8][29] ),
+ .S(net694),
+ .Z(_07159_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19001_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[11][29] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[10][29] ),
+ .S(net694),
+ .Z(_07160_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19002_ (.I0(_07159_),
+ .I1(_07160_),
+ .S(net663),
+ .Z(_07161_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _19003_ (.A1(_07161_),
+ .A2(net736),
+ .B(net646),
+ .C(_07158_),
+ .ZN(_07162_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _19004_ (.A1(_07153_),
+ .A2(_07162_),
+ .ZN(_07163_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19005_ (.I0(_07163_),
+ .I1(_07144_),
+ .S(net643),
+ .Z(_00053_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _19006_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[20][30] ),
+ .A2(net720),
+ .ZN(_07164_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _19007_ (.A1(net694),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[21][30] ),
+ .B(net676),
+ .ZN(_07165_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _19008_ (.A1(net694),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[23][30] ),
+ .ZN(_07166_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _19009_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[22][30] ),
+ .A2(net720),
+ .B(net663),
+ .ZN(_07167_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _19010_ (.A1(_07167_),
+ .A2(_07166_),
+ .B1(_07165_),
+ .B2(_07164_),
+ .C(net736),
+ .ZN(_07168_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19011_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[17][30] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[16][30] ),
+ .S(net689),
+ .Z(_07169_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19012_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[19][30] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[18][30] ),
+ .S(net689),
+ .Z(_07170_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19013_ (.I0(_07169_),
+ .I1(_07170_),
+ .S(net660),
+ .Z(_07171_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _19014_ (.A1(_07171_),
+ .A2(net736),
+ .B(net655),
+ .C(_07168_),
+ .ZN(_07172_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19015_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[25][30] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[24][30] ),
+ .S(net694),
+ .Z(_07173_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19016_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[27][30] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[26][30] ),
+ .S(net694),
+ .Z(_07174_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19017_ (.I0(_07173_),
+ .I1(_07174_),
+ .S(net663),
+ .Z(_07175_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _19018_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[28][30] ),
+ .A2(net720),
+ .ZN(_07176_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _19019_ (.A1(net694),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[29][30] ),
+ .B(net676),
+ .ZN(_07177_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _19020_ (.A1(net694),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[31][30] ),
+ .ZN(_07178_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _19021_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[30][30] ),
+ .A2(net720),
+ .B(net663),
+ .ZN(_07179_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _19022_ (.A1(_07179_),
+ .A2(_07178_),
+ .B1(_07177_),
+ .B2(_07176_),
+ .C(net736),
+ .ZN(_07180_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _19023_ (.A1(_07175_),
+ .A2(net736),
+ .B(net645),
+ .C(_07180_),
+ .ZN(_07181_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _19024_ (.A1(_07172_),
+ .A2(_07181_),
+ .ZN(_07182_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _19025_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[4][30] ),
+ .A2(net716),
+ .ZN(_07183_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _19026_ (.A1(net689),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[5][30] ),
+ .B(net678),
+ .ZN(_07184_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _19027_ (.A1(net700),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[7][30] ),
+ .ZN(_07185_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _19028_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[6][30] ),
+ .A2(net721),
+ .B(net665),
+ .ZN(_07186_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _19029_ (.A1(_07186_),
+ .A2(_07185_),
+ .B1(_07184_),
+ .B2(_07183_),
+ .C(net739),
+ .ZN(_07187_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19030_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[1][30] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[0][30] ),
+ .S(net700),
+ .Z(_07188_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19031_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[3][30] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[2][30] ),
+ .S(net700),
+ .Z(_07189_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19032_ (.I0(_07188_),
+ .I1(_07189_),
+ .S(net660),
+ .Z(_07190_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _19033_ (.A1(_07190_),
+ .A2(net733),
+ .B(net652),
+ .C(_07187_),
+ .ZN(_07191_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _19034_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[12][30] ),
+ .A2(net716),
+ .ZN(_07192_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _19035_ (.A1(net689),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[13][30] ),
+ .B(net675),
+ .ZN(_07193_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _19036_ (.A1(net689),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[15][30] ),
+ .ZN(_07194_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _19037_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[14][30] ),
+ .A2(net716),
+ .B(net660),
+ .ZN(_07195_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _19038_ (.A1(_07195_),
+ .A2(_07194_),
+ .B1(_07193_),
+ .B2(_07192_),
+ .C(net733),
+ .ZN(_07196_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19039_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[9][30] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[8][30] ),
+ .S(net688),
+ .Z(_07197_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19040_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[11][30] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[10][30] ),
+ .S(net689),
+ .Z(_07198_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19041_ (.I0(_07197_),
+ .I1(_07198_),
+ .S(net660),
+ .Z(_07199_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _19042_ (.A1(_07199_),
+ .A2(net733),
+ .B(net645),
+ .C(_07196_),
+ .ZN(_07200_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _19043_ (.A1(_07191_),
+ .A2(_07200_),
+ .ZN(_07201_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19044_ (.I0(_07201_),
+ .I1(_07182_),
+ .S(net644),
+ .Z(_00055_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _19045_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[20][31] ),
+ .A2(net722),
+ .ZN(_07202_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _19046_ (.A1(net701),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[21][31] ),
+ .B(net678),
+ .ZN(_07203_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _19047_ (.A1(net700),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[23][31] ),
+ .ZN(_07204_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _19048_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[22][31] ),
+ .A2(net722),
+ .B(net666),
+ .ZN(_07205_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _19049_ (.A1(_07205_),
+ .A2(_07204_),
+ .B1(_07203_),
+ .B2(_07202_),
+ .C(net739),
+ .ZN(_07206_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19050_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[17][31] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[16][31] ),
+ .S(net701),
+ .Z(_07207_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19051_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[19][31] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[18][31] ),
+ .S(net701),
+ .Z(_07208_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19052_ (.I0(_07207_),
+ .I1(_07208_),
+ .S(net666),
+ .Z(_07209_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _19053_ (.A1(_07209_),
+ .A2(net739),
+ .B(net655),
+ .C(_07206_),
+ .ZN(_07210_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19054_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[25][31] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[24][31] ),
+ .S(net700),
+ .Z(_07211_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19055_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[27][31] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[26][31] ),
+ .S(net704),
+ .Z(_07212_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19056_ (.I0(_07211_),
+ .I1(_07212_),
+ .S(net668),
+ .Z(_07213_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _19057_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[28][31] ),
+ .A2(net724),
+ .ZN(_07214_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _19058_ (.A1(net704),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[29][31] ),
+ .B(net679),
+ .ZN(_07215_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _19059_ (.A1(net704),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[31][31] ),
+ .ZN(_07216_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _19060_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[30][31] ),
+ .A2(net724),
+ .B(net668),
+ .ZN(_07217_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _19061_ (.A1(_07217_),
+ .A2(_07216_),
+ .B1(_07215_),
+ .B2(_07214_),
+ .C(net741),
+ .ZN(_07218_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _19062_ (.A1(_07213_),
+ .A2(net741),
+ .B(net649),
+ .C(_07218_),
+ .ZN(_07219_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _19063_ (.A1(_07210_),
+ .A2(_07219_),
+ .ZN(_07220_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _19064_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[4][31] ),
+ .A2(net722),
+ .ZN(_07221_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _19065_ (.A1(net700),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[5][31] ),
+ .B(net678),
+ .ZN(_07222_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _19066_ (.A1(net700),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[7][31] ),
+ .ZN(_07223_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _19067_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[6][31] ),
+ .A2(net722),
+ .B(net666),
+ .ZN(_07224_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _19068_ (.A1(_07224_),
+ .A2(_07223_),
+ .B1(_07222_),
+ .B2(_07221_),
+ .C(net739),
+ .ZN(_07225_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19069_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[1][31] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[0][31] ),
+ .S(net700),
+ .Z(_07226_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19070_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[3][31] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[2][31] ),
+ .S(net700),
+ .Z(_07227_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19071_ (.I0(_07226_),
+ .I1(_07227_),
+ .S(net666),
+ .Z(_07228_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _19072_ (.A1(_07228_),
+ .A2(net739),
+ .B(net652),
+ .C(_07225_),
+ .ZN(_07229_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _19073_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[12][31] ),
+ .A2(net722),
+ .ZN(_07230_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _19074_ (.A1(net700),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[13][31] ),
+ .B(net678),
+ .ZN(_07231_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _19075_ (.A1(net700),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[15][31] ),
+ .ZN(_07232_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _19076_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[14][31] ),
+ .A2(net722),
+ .B(net666),
+ .ZN(_07233_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _19077_ (.A1(_07233_),
+ .A2(_07232_),
+ .B1(_07231_),
+ .B2(_07230_),
+ .C(net739),
+ .ZN(_07234_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19078_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[9][31] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[8][31] ),
+ .S(net700),
+ .Z(_07235_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19079_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[11][31] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[10][31] ),
+ .S(net700),
+ .Z(_07236_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19080_ (.I0(_07235_),
+ .I1(_07236_),
+ .S(net666),
+ .Z(_07237_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _19081_ (.A1(_07237_),
+ .A2(net739),
+ .B(net649),
+ .C(_07234_),
+ .ZN(_07238_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _19082_ (.A1(_07229_),
+ .A2(_07238_),
+ .ZN(_07239_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19083_ (.I0(_07239_),
+ .I1(_07220_),
+ .S(_06032_),
+ .Z(_00056_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19084_ (.I0(\soc.core.VexRiscv.IBusCachedPlugin_cache._zz_banks_0_port1[22] ),
+ .I1(\soc.core.VexRiscv.IBusCachedPlugin_cache.io_cpu_decode_data[22] ),
+ .S(net782),
+ .Z(_07240_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19085_ (.I0(\soc.core.VexRiscv.IBusCachedPlugin_cache._zz_banks_0_port1[20] ),
+ .I1(\soc.core.VexRiscv.IBusCachedPlugin_cache.io_cpu_decode_data[20] ),
+ .S(net782),
+ .Z(_07241_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19086_ (.I0(_05333_),
+ .I1(_05275_),
+ .S(net782),
+ .Z(_07242_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19087_ (.I0(_05334_),
+ .I1(_05276_),
+ .S(net782),
+ .Z(_07243_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19088_ (.I0(\soc.core.VexRiscv.IBusCachedPlugin_cache._zz_banks_0_port1[21] ),
+ .I1(\soc.core.VexRiscv.IBusCachedPlugin_cache.io_cpu_decode_data[21] ),
+ .S(net782),
+ .Z(_07244_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _19089_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[20][0] ),
+ .A2(net619),
+ .ZN(_07245_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _19090_ (.A1(net598),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[21][0] ),
+ .B(net574),
+ .ZN(_07246_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _19091_ (.A1(net598),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[23][0] ),
+ .ZN(_07247_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _19092_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[22][0] ),
+ .A2(net619),
+ .B(net564),
+ .ZN(_07248_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _19093_ (.A1(_07248_),
+ .A2(_07247_),
+ .B1(_07246_),
+ .B2(_07245_),
+ .C(net635),
+ .ZN(_07249_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19094_ (.I0(_05335_),
+ .I1(_05278_),
+ .S(net782),
+ .Z(_07250_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19095_ (.I0(\soc.core.VexRiscv.IBusCachedPlugin_cache._zz_banks_0_port1[23] ),
+ .I1(\soc.core.VexRiscv.IBusCachedPlugin_cache.io_cpu_decode_data[23] ),
+ .S(net782),
+ .Z(_07251_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19096_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[17][0] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[16][0] ),
+ .S(net598),
+ .Z(_07252_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19097_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[19][0] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[18][0] ),
+ .S(net598),
+ .Z(_07253_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19098_ (.I0(_07252_),
+ .I1(_07253_),
+ .S(net564),
+ .Z(_07254_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _19099_ (.A1(_07254_),
+ .A2(net635),
+ .B(_07249_),
+ .C(net550),
+ .ZN(_07255_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19100_ (.I0(\soc.core.VexRiscv.IBusCachedPlugin_cache._zz_banks_0_port1[24] ),
+ .I1(\soc.core.VexRiscv.IBusCachedPlugin_cache.io_cpu_decode_data[24] ),
+ .S(net782),
+ .Z(_07256_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19101_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[25][0] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[24][0] ),
+ .S(net598),
+ .Z(_07257_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19102_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[27][0] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[26][0] ),
+ .S(net598),
+ .Z(_07258_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19103_ (.I0(_07257_),
+ .I1(_07258_),
+ .S(net564),
+ .Z(_07259_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _19104_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[28][0] ),
+ .A2(net619),
+ .ZN(_07260_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _19105_ (.A1(net598),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[29][0] ),
+ .B(net574),
+ .ZN(_07261_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _19106_ (.A1(net598),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[31][0] ),
+ .ZN(_07262_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _19107_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[30][0] ),
+ .A2(net619),
+ .B(net564),
+ .ZN(_07263_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _19108_ (.A1(_07263_),
+ .A2(_07262_),
+ .B1(_07261_),
+ .B2(_07260_),
+ .C(net635),
+ .ZN(_07264_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _19109_ (.A1(_07259_),
+ .A2(net635),
+ .B(net547),
+ .C(_07264_),
+ .ZN(_07265_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _19110_ (.A1(_07255_),
+ .A2(_07265_),
+ .ZN(_07266_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _19111_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[4][0] ),
+ .A2(net619),
+ .ZN(_07267_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _19112_ (.A1(net598),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[5][0] ),
+ .B(net574),
+ .ZN(_07268_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _19113_ (.A1(net598),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[7][0] ),
+ .ZN(_07269_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _19114_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[6][0] ),
+ .A2(net619),
+ .B(net564),
+ .ZN(_07270_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _19115_ (.A1(_07270_),
+ .A2(_07269_),
+ .B1(_07268_),
+ .B2(_07267_),
+ .C(net635),
+ .ZN(_07271_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19116_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[1][0] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[0][0] ),
+ .S(net598),
+ .Z(_07272_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19117_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[3][0] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[2][0] ),
+ .S(net598),
+ .Z(_07273_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19118_ (.I0(_07272_),
+ .I1(_07273_),
+ .S(net564),
+ .Z(_07274_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _19119_ (.A1(_07274_),
+ .A2(net635),
+ .B(net550),
+ .C(_07271_),
+ .ZN(_07275_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _19120_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[12][0] ),
+ .A2(net619),
+ .ZN(_07276_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _19121_ (.A1(net595),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[13][0] ),
+ .B(net574),
+ .ZN(_07277_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _19122_ (.A1(net598),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[15][0] ),
+ .ZN(_07278_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _19123_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[14][0] ),
+ .A2(net619),
+ .B(net564),
+ .ZN(_07279_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _19124_ (.A1(_07279_),
+ .A2(_07278_),
+ .B1(_07277_),
+ .B2(_07276_),
+ .C(net635),
+ .ZN(_07280_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19125_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[9][0] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[8][0] ),
+ .S(net598),
+ .Z(_07281_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19126_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[11][0] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[10][0] ),
+ .S(net598),
+ .Z(_07282_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19127_ (.I0(_07281_),
+ .I1(_07282_),
+ .S(net564),
+ .Z(_07283_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _19128_ (.A1(_07283_),
+ .A2(net635),
+ .B(net547),
+ .C(_07280_),
+ .ZN(_07284_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _19129_ (.A1(_07275_),
+ .A2(_07284_),
+ .ZN(_07285_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19130_ (.I0(_07285_),
+ .I1(_07266_),
+ .S(_07256_),
+ .Z(_00000_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _19131_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[20][1] ),
+ .A2(net617),
+ .ZN(_07286_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _19132_ (.A1(net595),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[21][1] ),
+ .B(net574),
+ .ZN(_07287_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _19133_ (.A1(net595),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[23][1] ),
+ .ZN(_07288_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _19134_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[22][1] ),
+ .A2(net617),
+ .B(net562),
+ .ZN(_07289_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _19135_ (.A1(_07289_),
+ .A2(_07288_),
+ .B1(_07287_),
+ .B2(_07286_),
+ .C(net633),
+ .ZN(_07290_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19136_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[17][1] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[16][1] ),
+ .S(net597),
+ .Z(_07291_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19137_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[19][1] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[18][1] ),
+ .S(net597),
+ .Z(_07292_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19138_ (.I0(_07291_),
+ .I1(_07292_),
+ .S(net563),
+ .Z(_07293_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _19139_ (.A1(_07293_),
+ .A2(net634),
+ .B(net550),
+ .C(_07290_),
+ .ZN(_07294_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19140_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[25][1] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[24][1] ),
+ .S(net598),
+ .Z(_07295_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19141_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[27][1] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[26][1] ),
+ .S(net598),
+ .Z(_07296_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19142_ (.I0(_07295_),
+ .I1(_07296_),
+ .S(net564),
+ .Z(_07297_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _19143_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[28][1] ),
+ .A2(net618),
+ .ZN(_07298_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _19144_ (.A1(net597),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[29][1] ),
+ .B(_07243_),
+ .ZN(_07299_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _19145_ (.A1(net598),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[31][1] ),
+ .ZN(_07300_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _19146_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[30][1] ),
+ .A2(net619),
+ .B(net564),
+ .ZN(_07301_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _19147_ (.A1(_07301_),
+ .A2(_07300_),
+ .B1(_07299_),
+ .B2(_07298_),
+ .C(net635),
+ .ZN(_07302_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _19148_ (.A1(_07297_),
+ .A2(net635),
+ .B(net547),
+ .C(_07302_),
+ .ZN(_07303_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _19149_ (.A1(_07294_),
+ .A2(_07303_),
+ .ZN(_07304_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _19150_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[4][1] ),
+ .A2(net618),
+ .ZN(_07305_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _19151_ (.A1(net597),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[5][1] ),
+ .B(net574),
+ .ZN(_07306_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _19152_ (.A1(net596),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[7][1] ),
+ .ZN(_07307_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _19153_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[6][1] ),
+ .A2(net618),
+ .B(net563),
+ .ZN(_07308_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _19154_ (.A1(_07308_),
+ .A2(_07307_),
+ .B1(_07306_),
+ .B2(_07305_),
+ .C(net634),
+ .ZN(_07309_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19155_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[1][1] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[0][1] ),
+ .S(net597),
+ .Z(_07310_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19156_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[3][1] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[2][1] ),
+ .S(net597),
+ .Z(_07311_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19157_ (.I0(_07310_),
+ .I1(_07311_),
+ .S(net563),
+ .Z(_07312_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _19158_ (.A1(_07312_),
+ .A2(net634),
+ .B(net550),
+ .C(_07309_),
+ .ZN(_07313_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _19159_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[12][1] ),
+ .A2(net617),
+ .ZN(_07314_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _19160_ (.A1(net597),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[13][1] ),
+ .B(net574),
+ .ZN(_07315_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _19161_ (.A1(net596),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[15][1] ),
+ .ZN(_07316_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _19162_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[14][1] ),
+ .A2(net618),
+ .B(net563),
+ .ZN(_07317_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _19163_ (.A1(_07317_),
+ .A2(_07316_),
+ .B1(_07315_),
+ .B2(_07314_),
+ .C(net633),
+ .ZN(_07318_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19164_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[9][1] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[8][1] ),
+ .S(net597),
+ .Z(_07319_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19165_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[11][1] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[10][1] ),
+ .S(net597),
+ .Z(_07320_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19166_ (.I0(_07319_),
+ .I1(_07320_),
+ .S(net562),
+ .Z(_07321_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _19167_ (.A1(_07321_),
+ .A2(net634),
+ .B(net547),
+ .C(_07318_),
+ .ZN(_07322_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _19168_ (.A1(_07313_),
+ .A2(_07322_),
+ .ZN(_07323_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19169_ (.I0(_07323_),
+ .I1(_07304_),
+ .S(_07256_),
+ .Z(_00011_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _19170_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[20][2] ),
+ .A2(net618),
+ .ZN(_07324_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _19171_ (.A1(net596),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[21][2] ),
+ .B(net574),
+ .ZN(_07325_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _19172_ (.A1(net596),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[23][2] ),
+ .ZN(_07326_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _19173_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[22][2] ),
+ .A2(net618),
+ .B(net563),
+ .ZN(_07327_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _19174_ (.A1(_07327_),
+ .A2(_07326_),
+ .B1(_07325_),
+ .B2(_07324_),
+ .C(net633),
+ .ZN(_07328_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19175_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[17][2] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[16][2] ),
+ .S(net596),
+ .Z(_07329_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19176_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[19][2] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[18][2] ),
+ .S(net596),
+ .Z(_07330_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19177_ (.I0(_07329_),
+ .I1(_07330_),
+ .S(net563),
+ .Z(_07331_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _19178_ (.A1(_07331_),
+ .A2(net634),
+ .B(net550),
+ .C(_07328_),
+ .ZN(_07332_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19179_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[25][2] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[24][2] ),
+ .S(net585),
+ .Z(_07333_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19180_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[27][2] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[26][2] ),
+ .S(net585),
+ .Z(_07334_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19181_ (.I0(_07333_),
+ .I1(_07334_),
+ .S(net557),
+ .Z(_07335_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _19182_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[28][2] ),
+ .A2(net612),
+ .ZN(_07336_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _19183_ (.A1(net585),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[29][2] ),
+ .B(net571),
+ .ZN(_07337_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _19184_ (.A1(net596),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[31][2] ),
+ .ZN(_07338_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _19185_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[30][2] ),
+ .A2(net612),
+ .B(net557),
+ .ZN(_07339_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _19186_ (.A1(_07339_),
+ .A2(_07338_),
+ .B1(_07337_),
+ .B2(_07336_),
+ .C(net628),
+ .ZN(_07340_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _19187_ (.A1(_07335_),
+ .A2(net628),
+ .B(net545),
+ .C(_07340_),
+ .ZN(_07341_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _19188_ (.A1(_07332_),
+ .A2(_07341_),
+ .ZN(_07342_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _19189_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[4][2] ),
+ .A2(net612),
+ .ZN(_07343_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _19190_ (.A1(net584),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[5][2] ),
+ .B(net571),
+ .ZN(_07344_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _19191_ (.A1(net584),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[7][2] ),
+ .ZN(_07345_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _19192_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[6][2] ),
+ .A2(net612),
+ .B(net557),
+ .ZN(_07346_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _19193_ (.A1(_07346_),
+ .A2(_07345_),
+ .B1(_07344_),
+ .B2(_07343_),
+ .C(net628),
+ .ZN(_07347_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19194_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[1][2] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[0][2] ),
+ .S(net584),
+ .Z(_07348_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19195_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[3][2] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[2][2] ),
+ .S(net584),
+ .Z(_07349_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19196_ (.I0(_07348_),
+ .I1(_07349_),
+ .S(net557),
+ .Z(_07350_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _19197_ (.A1(_07350_),
+ .A2(net628),
+ .B(net549),
+ .C(_07347_),
+ .ZN(_07351_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _19198_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[12][2] ),
+ .A2(net611),
+ .ZN(_07352_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _19199_ (.A1(net583),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[13][2] ),
+ .B(net571),
+ .ZN(_07353_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _19200_ (.A1(net583),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[15][2] ),
+ .ZN(_07354_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _19201_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[14][2] ),
+ .A2(net611),
+ .B(net556),
+ .ZN(_07355_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _19202_ (.A1(_07355_),
+ .A2(_07354_),
+ .B1(_07353_),
+ .B2(_07352_),
+ .C(net627),
+ .ZN(_07356_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19203_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[9][2] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[8][2] ),
+ .S(net582),
+ .Z(_07357_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19204_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[11][2] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[10][2] ),
+ .S(net582),
+ .Z(_07358_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19205_ (.I0(_07357_),
+ .I1(_07358_),
+ .S(net556),
+ .Z(_07359_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _19206_ (.A1(_07359_),
+ .A2(net627),
+ .B(net545),
+ .C(_07356_),
+ .ZN(_07360_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _19207_ (.A1(_07351_),
+ .A2(_07360_),
+ .ZN(_07361_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19208_ (.I0(_07361_),
+ .I1(_07342_),
+ .S(net542),
+ .Z(_00022_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _19209_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[20][3] ),
+ .A2(net611),
+ .ZN(_07362_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _19210_ (.A1(net582),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[21][3] ),
+ .B(net570),
+ .ZN(_07363_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _19211_ (.A1(net583),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[23][3] ),
+ .ZN(_07364_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _19212_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[22][3] ),
+ .A2(net611),
+ .B(net556),
+ .ZN(_07365_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _19213_ (.A1(_07365_),
+ .A2(_07364_),
+ .B1(_07363_),
+ .B2(_07362_),
+ .C(net627),
+ .ZN(_07366_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19214_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[17][3] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[16][3] ),
+ .S(net582),
+ .Z(_07367_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19215_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[19][3] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[18][3] ),
+ .S(net582),
+ .Z(_07368_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19216_ (.I0(_07367_),
+ .I1(_07368_),
+ .S(net556),
+ .Z(_07369_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _19217_ (.A1(_07369_),
+ .A2(net627),
+ .B(net549),
+ .C(_07366_),
+ .ZN(_07370_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19218_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[25][3] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[24][3] ),
+ .S(net584),
+ .Z(_07371_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19219_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[27][3] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[26][3] ),
+ .S(net584),
+ .Z(_07372_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19220_ (.I0(_07371_),
+ .I1(_07372_),
+ .S(net557),
+ .Z(_07373_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _19221_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[28][3] ),
+ .A2(net611),
+ .ZN(_07374_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _19222_ (.A1(net582),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[29][3] ),
+ .B(net571),
+ .ZN(_07375_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _19223_ (.A1(net582),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[31][3] ),
+ .ZN(_07376_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _19224_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[30][3] ),
+ .A2(net611),
+ .B(net556),
+ .ZN(_07377_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _19225_ (.A1(_07377_),
+ .A2(_07376_),
+ .B1(_07375_),
+ .B2(_07374_),
+ .C(net627),
+ .ZN(_07378_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _19226_ (.A1(_07373_),
+ .A2(net627),
+ .B(net545),
+ .C(_07378_),
+ .ZN(_07379_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _19227_ (.A1(_07370_),
+ .A2(_07379_),
+ .ZN(_07380_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _19228_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[4][3] ),
+ .A2(net611),
+ .ZN(_07381_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _19229_ (.A1(net582),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[5][3] ),
+ .B(net571),
+ .ZN(_07382_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _19230_ (.A1(net583),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[7][3] ),
+ .ZN(_07383_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _19231_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[6][3] ),
+ .A2(net611),
+ .B(net556),
+ .ZN(_07384_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _19232_ (.A1(_07384_),
+ .A2(_07383_),
+ .B1(_07382_),
+ .B2(_07381_),
+ .C(net627),
+ .ZN(_07385_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19233_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[1][3] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[0][3] ),
+ .S(net583),
+ .Z(_07386_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19234_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[3][3] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[2][3] ),
+ .S(net583),
+ .Z(_07387_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19235_ (.I0(_07386_),
+ .I1(_07387_),
+ .S(net556),
+ .Z(_07388_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _19236_ (.A1(_07388_),
+ .A2(net627),
+ .B(net549),
+ .C(_07385_),
+ .ZN(_07389_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _19237_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[12][3] ),
+ .A2(net611),
+ .ZN(_07390_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _19238_ (.A1(net582),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[13][3] ),
+ .B(net571),
+ .ZN(_07391_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _19239_ (.A1(net582),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[15][3] ),
+ .ZN(_07392_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _19240_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[14][3] ),
+ .A2(net611),
+ .B(net556),
+ .ZN(_07393_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _19241_ (.A1(_07393_),
+ .A2(_07392_),
+ .B1(_07391_),
+ .B2(_07390_),
+ .C(net627),
+ .ZN(_07394_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19242_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[9][3] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[8][3] ),
+ .S(net582),
+ .Z(_07395_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19243_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[11][3] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[10][3] ),
+ .S(net582),
+ .Z(_07396_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19244_ (.I0(_07395_),
+ .I1(_07396_),
+ .S(net556),
+ .Z(_07397_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _19245_ (.A1(_07397_),
+ .A2(net627),
+ .B(net545),
+ .C(_07394_),
+ .ZN(_07398_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _19246_ (.A1(_07389_),
+ .A2(_07398_),
+ .ZN(_07399_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19247_ (.I0(_07399_),
+ .I1(_07380_),
+ .S(net539),
+ .Z(_00025_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _19248_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[20][4] ),
+ .A2(net609),
+ .ZN(_07400_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _19249_ (.A1(net579),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[21][4] ),
+ .B(net570),
+ .ZN(_07401_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _19250_ (.A1(net582),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[23][4] ),
+ .ZN(_07402_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _19251_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[22][4] ),
+ .A2(net609),
+ .B(net554),
+ .ZN(_07403_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _19252_ (.A1(_07403_),
+ .A2(_07402_),
+ .B1(_07401_),
+ .B2(_07400_),
+ .C(net625),
+ .ZN(_07404_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19253_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[17][4] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[16][4] ),
+ .S(net579),
+ .Z(_07405_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19254_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[19][4] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[18][4] ),
+ .S(net579),
+ .Z(_07406_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19255_ (.I0(_07405_),
+ .I1(_07406_),
+ .S(net554),
+ .Z(_07407_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _19256_ (.A1(_07407_),
+ .A2(net625),
+ .B(net549),
+ .C(_07404_),
+ .ZN(_07408_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19257_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[25][4] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[24][4] ),
+ .S(net582),
+ .Z(_07409_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19258_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[27][4] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[26][4] ),
+ .S(net582),
+ .Z(_07410_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19259_ (.I0(_07409_),
+ .I1(_07410_),
+ .S(net556),
+ .Z(_07411_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _19260_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[28][4] ),
+ .A2(net609),
+ .ZN(_07412_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _19261_ (.A1(net579),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[29][4] ),
+ .B(net570),
+ .ZN(_07413_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _19262_ (.A1(net584),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[31][4] ),
+ .ZN(_07414_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _19263_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[30][4] ),
+ .A2(net611),
+ .B(net557),
+ .ZN(_07415_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _19264_ (.A1(_07415_),
+ .A2(_07414_),
+ .B1(_07413_),
+ .B2(_07412_),
+ .C(net625),
+ .ZN(_07416_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _19265_ (.A1(_07411_),
+ .A2(net625),
+ .B(net545),
+ .C(_07416_),
+ .ZN(_07417_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _19266_ (.A1(_07408_),
+ .A2(_07417_),
+ .ZN(_07418_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _19267_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[4][4] ),
+ .A2(net611),
+ .ZN(_07419_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _19268_ (.A1(net582),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[5][4] ),
+ .B(net571),
+ .ZN(_07420_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _19269_ (.A1(net582),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[7][4] ),
+ .ZN(_07421_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _19270_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[6][4] ),
+ .A2(net611),
+ .B(net556),
+ .ZN(_07422_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _19271_ (.A1(_07422_),
+ .A2(_07421_),
+ .B1(_07420_),
+ .B2(_07419_),
+ .C(net627),
+ .ZN(_07423_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19272_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[1][4] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[0][4] ),
+ .S(net582),
+ .Z(_07424_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19273_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[3][4] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[2][4] ),
+ .S(net582),
+ .Z(_07425_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19274_ (.I0(_07424_),
+ .I1(_07425_),
+ .S(net556),
+ .Z(_07426_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _19275_ (.A1(_07426_),
+ .A2(net627),
+ .B(net549),
+ .C(_07423_),
+ .ZN(_07427_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _19276_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[12][4] ),
+ .A2(net609),
+ .ZN(_07428_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _19277_ (.A1(net579),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[13][4] ),
+ .B(net570),
+ .ZN(_07429_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _19278_ (.A1(net582),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[15][4] ),
+ .ZN(_07430_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _19279_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[14][4] ),
+ .A2(net611),
+ .B(net556),
+ .ZN(_07431_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _19280_ (.A1(_07431_),
+ .A2(_07430_),
+ .B1(_07429_),
+ .B2(_07428_),
+ .C(net625),
+ .ZN(_07432_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19281_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[9][4] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[8][4] ),
+ .S(net582),
+ .Z(_07433_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19282_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[11][4] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[10][4] ),
+ .S(net582),
+ .Z(_07434_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19283_ (.I0(_07433_),
+ .I1(_07434_),
+ .S(net556),
+ .Z(_07435_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _19284_ (.A1(_07435_),
+ .A2(net627),
+ .B(net545),
+ .C(_07432_),
+ .ZN(_07436_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _19285_ (.A1(_07427_),
+ .A2(_07436_),
+ .ZN(_07437_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19286_ (.I0(_07437_),
+ .I1(_07418_),
+ .S(net540),
+ .Z(_00026_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _19287_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[20][5] ),
+ .A2(net617),
+ .ZN(_07438_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _19288_ (.A1(net594),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[21][5] ),
+ .B(net574),
+ .ZN(_07439_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _19289_ (.A1(net594),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[23][5] ),
+ .ZN(_07440_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _19290_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[22][5] ),
+ .A2(net617),
+ .B(net562),
+ .ZN(_07441_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _19291_ (.A1(_07441_),
+ .A2(_07440_),
+ .B1(_07439_),
+ .B2(_07438_),
+ .C(net633),
+ .ZN(_07442_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19292_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[17][5] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[16][5] ),
+ .S(net594),
+ .Z(_07443_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19293_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[19][5] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[18][5] ),
+ .S(net594),
+ .Z(_07444_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19294_ (.I0(_07443_),
+ .I1(_07444_),
+ .S(net562),
+ .Z(_07445_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _19295_ (.A1(_07445_),
+ .A2(net633),
+ .B(net550),
+ .C(_07442_),
+ .ZN(_07446_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19296_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[25][5] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[24][5] ),
+ .S(net596),
+ .Z(_07447_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19297_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[27][5] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[26][5] ),
+ .S(net596),
+ .Z(_07448_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19298_ (.I0(_07447_),
+ .I1(_07448_),
+ .S(net562),
+ .Z(_07449_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _19299_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[28][5] ),
+ .A2(net617),
+ .ZN(_07450_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _19300_ (.A1(net594),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[29][5] ),
+ .B(net574),
+ .ZN(_07451_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _19301_ (.A1(net594),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[31][5] ),
+ .ZN(_07452_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _19302_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[30][5] ),
+ .A2(net617),
+ .B(net562),
+ .ZN(_07453_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _19303_ (.A1(_07453_),
+ .A2(_07452_),
+ .B1(_07451_),
+ .B2(_07450_),
+ .C(net633),
+ .ZN(_07454_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _19304_ (.A1(_07449_),
+ .A2(net633),
+ .B(net547),
+ .C(_07454_),
+ .ZN(_07455_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _19305_ (.A1(_07446_),
+ .A2(_07455_),
+ .ZN(_07456_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _19306_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[4][5] ),
+ .A2(net617),
+ .ZN(_07457_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _19307_ (.A1(net594),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[5][5] ),
+ .B(net574),
+ .ZN(_07458_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _19308_ (.A1(net594),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[7][5] ),
+ .ZN(_07459_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _19309_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[6][5] ),
+ .A2(net617),
+ .B(net562),
+ .ZN(_07460_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _19310_ (.A1(_07460_),
+ .A2(_07459_),
+ .B1(_07458_),
+ .B2(_07457_),
+ .C(net633),
+ .ZN(_07461_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19311_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[1][5] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[0][5] ),
+ .S(net594),
+ .Z(_07462_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19312_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[3][5] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[2][5] ),
+ .S(net594),
+ .Z(_07463_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19313_ (.I0(_07462_),
+ .I1(_07463_),
+ .S(net562),
+ .Z(_07464_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _19314_ (.A1(_07464_),
+ .A2(net633),
+ .B(net550),
+ .C(_07461_),
+ .ZN(_07465_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _19315_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[12][5] ),
+ .A2(net617),
+ .ZN(_07466_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _19316_ (.A1(net594),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[13][5] ),
+ .B(net574),
+ .ZN(_07467_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _19317_ (.A1(net594),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[15][5] ),
+ .ZN(_07468_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _19318_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[14][5] ),
+ .A2(net617),
+ .B(net562),
+ .ZN(_07469_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _19319_ (.A1(_07469_),
+ .A2(_07468_),
+ .B1(_07467_),
+ .B2(_07466_),
+ .C(net633),
+ .ZN(_07470_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19320_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[9][5] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[8][5] ),
+ .S(net594),
+ .Z(_07471_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19321_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[11][5] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[10][5] ),
+ .S(net594),
+ .Z(_07472_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19322_ (.I0(_07471_),
+ .I1(_07472_),
+ .S(net562),
+ .Z(_07473_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _19323_ (.A1(_07473_),
+ .A2(net633),
+ .B(net547),
+ .C(_07470_),
+ .ZN(_07474_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _19324_ (.A1(_07465_),
+ .A2(_07474_),
+ .ZN(_07475_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19325_ (.I0(_07475_),
+ .I1(_07456_),
+ .S(_07256_),
+ .Z(_00027_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _19326_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[20][6] ),
+ .A2(net609),
+ .ZN(_07476_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _19327_ (.A1(net578),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[21][6] ),
+ .B(net570),
+ .ZN(_07477_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _19328_ (.A1(net578),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[23][6] ),
+ .ZN(_07478_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _19329_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[22][6] ),
+ .A2(net609),
+ .B(net554),
+ .ZN(_07479_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _19330_ (.A1(_07479_),
+ .A2(_07478_),
+ .B1(_07477_),
+ .B2(_07476_),
+ .C(net625),
+ .ZN(_07480_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19331_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[17][6] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[16][6] ),
+ .S(net578),
+ .Z(_07481_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19332_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[19][6] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[18][6] ),
+ .S(net578),
+ .Z(_07482_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19333_ (.I0(_07481_),
+ .I1(_07482_),
+ .S(net554),
+ .Z(_07483_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _19334_ (.A1(_07483_),
+ .A2(net625),
+ .B(net549),
+ .C(_07480_),
+ .ZN(_07484_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19335_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[25][6] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[24][6] ),
+ .S(net579),
+ .Z(_07485_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19336_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[27][6] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[26][6] ),
+ .S(net578),
+ .Z(_07486_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19337_ (.I0(_07485_),
+ .I1(_07486_),
+ .S(net554),
+ .Z(_07487_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _19338_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[28][6] ),
+ .A2(net609),
+ .ZN(_07488_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _19339_ (.A1(net578),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[29][6] ),
+ .B(net570),
+ .ZN(_07489_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _19340_ (.A1(net578),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[31][6] ),
+ .ZN(_07490_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _19341_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[30][6] ),
+ .A2(net609),
+ .B(net554),
+ .ZN(_07491_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _19342_ (.A1(_07491_),
+ .A2(_07490_),
+ .B1(_07489_),
+ .B2(_07488_),
+ .C(net625),
+ .ZN(_07492_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _19343_ (.A1(_07487_),
+ .A2(net625),
+ .B(net545),
+ .C(_07492_),
+ .ZN(_07493_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _19344_ (.A1(_07484_),
+ .A2(_07493_),
+ .ZN(_07494_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _19345_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[4][6] ),
+ .A2(net609),
+ .ZN(_07495_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _19346_ (.A1(net578),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[5][6] ),
+ .B(net570),
+ .ZN(_07496_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _19347_ (.A1(net579),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[7][6] ),
+ .ZN(_07497_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _19348_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[6][6] ),
+ .A2(net609),
+ .B(net554),
+ .ZN(_07498_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _19349_ (.A1(_07498_),
+ .A2(_07497_),
+ .B1(_07496_),
+ .B2(_07495_),
+ .C(net625),
+ .ZN(_07499_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19350_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[1][6] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[0][6] ),
+ .S(net579),
+ .Z(_07500_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19351_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[3][6] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[2][6] ),
+ .S(net579),
+ .Z(_07501_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19352_ (.I0(_07500_),
+ .I1(_07501_),
+ .S(net554),
+ .Z(_07502_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _19353_ (.A1(_07502_),
+ .A2(net625),
+ .B(net549),
+ .C(_07499_),
+ .ZN(_07503_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _19354_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[12][6] ),
+ .A2(net609),
+ .ZN(_07504_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _19355_ (.A1(net578),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[13][6] ),
+ .B(net570),
+ .ZN(_07505_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _19356_ (.A1(net578),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[15][6] ),
+ .ZN(_07506_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _19357_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[14][6] ),
+ .A2(net609),
+ .B(net554),
+ .ZN(_07507_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _19358_ (.A1(_07507_),
+ .A2(_07506_),
+ .B1(_07505_),
+ .B2(_07504_),
+ .C(net625),
+ .ZN(_07508_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19359_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[9][6] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[8][6] ),
+ .S(net578),
+ .Z(_07509_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19360_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[11][6] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[10][6] ),
+ .S(net578),
+ .Z(_07510_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19361_ (.I0(_07509_),
+ .I1(_07510_),
+ .S(net554),
+ .Z(_07511_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _19362_ (.A1(_07511_),
+ .A2(net625),
+ .B(net545),
+ .C(_07508_),
+ .ZN(_07512_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _19363_ (.A1(_07503_),
+ .A2(_07512_),
+ .ZN(_07513_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19364_ (.I0(_07513_),
+ .I1(_07494_),
+ .S(net540),
+ .Z(_00028_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _19365_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[20][7] ),
+ .A2(net611),
+ .ZN(_07514_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _19366_ (.A1(net583),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[21][7] ),
+ .B(net571),
+ .ZN(_07515_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _19367_ (.A1(net594),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[23][7] ),
+ .ZN(_07516_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _19368_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[22][7] ),
+ .A2(net617),
+ .B(net562),
+ .ZN(_07517_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _19369_ (.A1(_07517_),
+ .A2(_07516_),
+ .B1(_07515_),
+ .B2(_07514_),
+ .C(net633),
+ .ZN(_07518_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19370_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[17][7] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[16][7] ),
+ .S(net594),
+ .Z(_07519_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19371_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[19][7] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[18][7] ),
+ .S(net583),
+ .Z(_07520_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19372_ (.I0(_07519_),
+ .I1(_07520_),
+ .S(net556),
+ .Z(_07521_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _19373_ (.A1(_07521_),
+ .A2(net627),
+ .B(net550),
+ .C(_07518_),
+ .ZN(_07522_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19374_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[25][7] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[24][7] ),
+ .S(net594),
+ .Z(_07523_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19375_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[27][7] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[26][7] ),
+ .S(net594),
+ .Z(_07524_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19376_ (.I0(_07523_),
+ .I1(_07524_),
+ .S(net556),
+ .Z(_07525_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _19377_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[28][7] ),
+ .A2(net611),
+ .ZN(_07526_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _19378_ (.A1(net583),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[29][7] ),
+ .B(net571),
+ .ZN(_07527_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _19379_ (.A1(net583),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[31][7] ),
+ .ZN(_07528_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _19380_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[30][7] ),
+ .A2(net611),
+ .B(net556),
+ .ZN(_07529_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _19381_ (.A1(_07529_),
+ .A2(_07528_),
+ .B1(_07527_),
+ .B2(_07526_),
+ .C(net627),
+ .ZN(_07530_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _19382_ (.A1(_07525_),
+ .A2(net627),
+ .B(net545),
+ .C(_07530_),
+ .ZN(_07531_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _19383_ (.A1(_07522_),
+ .A2(_07531_),
+ .ZN(_07532_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _19384_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[4][7] ),
+ .A2(net611),
+ .ZN(_07533_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _19385_ (.A1(net583),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[5][7] ),
+ .B(net571),
+ .ZN(_07534_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _19386_ (.A1(net594),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[7][7] ),
+ .ZN(_07535_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _19387_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[6][7] ),
+ .A2(net617),
+ .B(net562),
+ .ZN(_07536_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _19388_ (.A1(_07536_),
+ .A2(_07535_),
+ .B1(_07534_),
+ .B2(_07533_),
+ .C(net627),
+ .ZN(_07537_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19389_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[1][7] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[0][7] ),
+ .S(net594),
+ .Z(_07538_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19390_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[3][7] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[2][7] ),
+ .S(net583),
+ .Z(_07539_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19391_ (.I0(_07538_),
+ .I1(_07539_),
+ .S(net556),
+ .Z(_07540_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _19392_ (.A1(_07540_),
+ .A2(net627),
+ .B(net550),
+ .C(_07537_),
+ .ZN(_07541_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _19393_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[12][7] ),
+ .A2(net611),
+ .ZN(_07542_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _19394_ (.A1(net583),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[13][7] ),
+ .B(net571),
+ .ZN(_07543_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _19395_ (.A1(net583),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[15][7] ),
+ .ZN(_07544_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _19396_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[14][7] ),
+ .A2(net611),
+ .B(net556),
+ .ZN(_07545_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _19397_ (.A1(_07545_),
+ .A2(_07544_),
+ .B1(_07543_),
+ .B2(_07542_),
+ .C(net627),
+ .ZN(_07546_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19398_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[9][7] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[8][7] ),
+ .S(net583),
+ .Z(_07547_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19399_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[11][7] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[10][7] ),
+ .S(net583),
+ .Z(_07548_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19400_ (.I0(_07547_),
+ .I1(_07548_),
+ .S(net556),
+ .Z(_07549_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _19401_ (.A1(_07549_),
+ .A2(net627),
+ .B(net545),
+ .C(_07546_),
+ .ZN(_07550_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _19402_ (.A1(_07541_),
+ .A2(_07550_),
+ .ZN(_07551_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19403_ (.I0(_07551_),
+ .I1(_07532_),
+ .S(net539),
+ .Z(_00029_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _19404_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[20][8] ),
+ .A2(net613),
+ .ZN(_07552_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _19405_ (.A1(net586),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[21][8] ),
+ .B(net572),
+ .ZN(_07553_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _19406_ (.A1(net586),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[23][8] ),
+ .ZN(_07554_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _19407_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[22][8] ),
+ .A2(net613),
+ .B(net558),
+ .ZN(_07555_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _19408_ (.A1(_07555_),
+ .A2(_07554_),
+ .B1(_07553_),
+ .B2(_07552_),
+ .C(net629),
+ .ZN(_07556_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19409_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[17][8] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[16][8] ),
+ .S(net586),
+ .Z(_07557_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19410_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[19][8] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[18][8] ),
+ .S(net586),
+ .Z(_07558_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19411_ (.I0(_07557_),
+ .I1(_07558_),
+ .S(net558),
+ .Z(_07559_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _19412_ (.A1(_07559_),
+ .A2(net629),
+ .B(net549),
+ .C(_07556_),
+ .ZN(_07560_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19413_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[25][8] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[24][8] ),
+ .S(net586),
+ .Z(_07561_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19414_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[27][8] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[26][8] ),
+ .S(net586),
+ .Z(_07562_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19415_ (.I0(_07561_),
+ .I1(_07562_),
+ .S(net558),
+ .Z(_07563_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _19416_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[28][8] ),
+ .A2(net613),
+ .ZN(_07564_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _19417_ (.A1(net586),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[29][8] ),
+ .B(net572),
+ .ZN(_07565_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _19418_ (.A1(net586),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[31][8] ),
+ .ZN(_07566_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _19419_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[30][8] ),
+ .A2(net613),
+ .B(net558),
+ .ZN(_07567_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _19420_ (.A1(_07567_),
+ .A2(_07566_),
+ .B1(_07565_),
+ .B2(_07564_),
+ .C(net629),
+ .ZN(_07568_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _19421_ (.A1(_07563_),
+ .A2(net629),
+ .B(net546),
+ .C(_07568_),
+ .ZN(_07569_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _19422_ (.A1(_07560_),
+ .A2(_07569_),
+ .ZN(_07570_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _19423_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[4][8] ),
+ .A2(net613),
+ .ZN(_07571_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _19424_ (.A1(net587),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[5][8] ),
+ .B(net572),
+ .ZN(_07572_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _19425_ (.A1(net587),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[7][8] ),
+ .ZN(_07573_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _19426_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[6][8] ),
+ .A2(net613),
+ .B(net558),
+ .ZN(_07574_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _19427_ (.A1(_07574_),
+ .A2(_07573_),
+ .B1(_07572_),
+ .B2(_07571_),
+ .C(net629),
+ .ZN(_07575_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19428_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[1][8] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[0][8] ),
+ .S(net587),
+ .Z(_07576_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19429_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[3][8] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[2][8] ),
+ .S(net587),
+ .Z(_07577_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19430_ (.I0(_07576_),
+ .I1(_07577_),
+ .S(net558),
+ .Z(_07578_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _19431_ (.A1(_07578_),
+ .A2(net629),
+ .B(net549),
+ .C(_07575_),
+ .ZN(_07579_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _19432_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[12][8] ),
+ .A2(net613),
+ .ZN(_07580_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _19433_ (.A1(net586),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[13][8] ),
+ .B(net572),
+ .ZN(_07581_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _19434_ (.A1(net587),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[15][8] ),
+ .ZN(_07582_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _19435_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[14][8] ),
+ .A2(net613),
+ .B(net558),
+ .ZN(_07583_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _19436_ (.A1(_07583_),
+ .A2(_07582_),
+ .B1(_07581_),
+ .B2(_07580_),
+ .C(net629),
+ .ZN(_07584_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19437_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[9][8] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[8][8] ),
+ .S(net587),
+ .Z(_07585_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19438_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[11][8] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[10][8] ),
+ .S(net586),
+ .Z(_07586_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19439_ (.I0(_07585_),
+ .I1(_07586_),
+ .S(net558),
+ .Z(_07587_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _19440_ (.A1(_07587_),
+ .A2(net629),
+ .B(net546),
+ .C(_07584_),
+ .ZN(_07588_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _19441_ (.A1(_07579_),
+ .A2(_07588_),
+ .ZN(_07589_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19442_ (.I0(_07589_),
+ .I1(_07570_),
+ .S(net540),
+ .Z(_00030_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _19443_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[20][9] ),
+ .A2(net609),
+ .ZN(_07590_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _19444_ (.A1(net580),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[21][9] ),
+ .B(net570),
+ .ZN(_07591_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _19445_ (.A1(net580),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[23][9] ),
+ .ZN(_07592_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _19446_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[22][9] ),
+ .A2(net610),
+ .B(net554),
+ .ZN(_07593_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _19447_ (.A1(_07593_),
+ .A2(_07592_),
+ .B1(_07591_),
+ .B2(_07590_),
+ .C(net626),
+ .ZN(_07594_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19448_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[17][9] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[16][9] ),
+ .S(net580),
+ .Z(_07595_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19449_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[19][9] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[18][9] ),
+ .S(net580),
+ .Z(_07596_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19450_ (.I0(_07595_),
+ .I1(_07596_),
+ .S(net554),
+ .Z(_07597_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _19451_ (.A1(_07597_),
+ .A2(net626),
+ .B(net549),
+ .C(_07594_),
+ .ZN(_07598_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19452_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[25][9] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[24][9] ),
+ .S(net580),
+ .Z(_07599_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19453_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[27][9] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[26][9] ),
+ .S(net580),
+ .Z(_07600_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19454_ (.I0(_07599_),
+ .I1(_07600_),
+ .S(net554),
+ .Z(_07601_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _19455_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[28][9] ),
+ .A2(net610),
+ .ZN(_07602_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _19456_ (.A1(net580),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[29][9] ),
+ .B(net570),
+ .ZN(_07603_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _19457_ (.A1(net580),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[31][9] ),
+ .ZN(_07604_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _19458_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[30][9] ),
+ .A2(net610),
+ .B(net555),
+ .ZN(_07605_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _19459_ (.A1(_07605_),
+ .A2(_07604_),
+ .B1(_07603_),
+ .B2(_07602_),
+ .C(net626),
+ .ZN(_07606_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _19460_ (.A1(_07601_),
+ .A2(net626),
+ .B(net545),
+ .C(_07606_),
+ .ZN(_07607_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _19461_ (.A1(_07598_),
+ .A2(_07607_),
+ .ZN(_07608_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19462_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[1][9] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[0][9] ),
+ .S(net581),
+ .Z(_07609_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19463_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[3][9] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[2][9] ),
+ .S(net581),
+ .Z(_07610_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19464_ (.I0(_07609_),
+ .I1(_07610_),
+ .S(net555),
+ .Z(_07611_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _19465_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[4][9] ),
+ .A2(net610),
+ .ZN(_07612_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _19466_ (.A1(net581),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[5][9] ),
+ .B(net570),
+ .ZN(_07613_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _19467_ (.A1(net581),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[7][9] ),
+ .ZN(_07614_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _19468_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[6][9] ),
+ .A2(net610),
+ .B(net555),
+ .ZN(_07615_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _19469_ (.A1(_07615_),
+ .A2(_07614_),
+ .B1(_07613_),
+ .B2(_07612_),
+ .C(net626),
+ .ZN(_07616_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _19470_ (.A1(_07611_),
+ .A2(net626),
+ .B(net549),
+ .C(_07616_),
+ .ZN(_07617_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _19471_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[12][9] ),
+ .A2(net610),
+ .ZN(_07618_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _19472_ (.A1(net580),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[13][9] ),
+ .B(net570),
+ .ZN(_07619_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _19473_ (.A1(net580),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[15][9] ),
+ .ZN(_07620_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _19474_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[14][9] ),
+ .A2(net610),
+ .B(net555),
+ .ZN(_07621_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _19475_ (.A1(_07621_),
+ .A2(_07620_),
+ .B1(_07619_),
+ .B2(_07618_),
+ .C(net626),
+ .ZN(_07622_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19476_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[9][9] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[8][9] ),
+ .S(net580),
+ .Z(_07623_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19477_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[11][9] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[10][9] ),
+ .S(net580),
+ .Z(_07624_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19478_ (.I0(_07623_),
+ .I1(_07624_),
+ .S(net555),
+ .Z(_07625_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _19479_ (.A1(_07625_),
+ .A2(net625),
+ .B(net545),
+ .C(_07622_),
+ .ZN(_07626_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _19480_ (.A1(_07617_),
+ .A2(_07626_),
+ .ZN(_07627_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19481_ (.I0(_07627_),
+ .I1(_07608_),
+ .S(net540),
+ .Z(_00031_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _19482_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[20][10] ),
+ .A2(net611),
+ .ZN(_07628_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _19483_ (.A1(net584),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[21][10] ),
+ .B(net570),
+ .ZN(_07629_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _19484_ (.A1(net584),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[23][10] ),
+ .ZN(_07630_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _19485_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[22][10] ),
+ .A2(net611),
+ .B(net556),
+ .ZN(_07631_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _19486_ (.A1(_07631_),
+ .A2(_07630_),
+ .B1(_07629_),
+ .B2(_07628_),
+ .C(net627),
+ .ZN(_07632_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19487_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[17][10] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[16][10] ),
+ .S(net584),
+ .Z(_07633_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19488_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[19][10] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[18][10] ),
+ .S(net584),
+ .Z(_07634_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19489_ (.I0(_07633_),
+ .I1(_07634_),
+ .S(net556),
+ .Z(_07635_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _19490_ (.A1(_07635_),
+ .A2(net627),
+ .B(net549),
+ .C(_07632_),
+ .ZN(_07636_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19491_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[25][10] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[24][10] ),
+ .S(net584),
+ .Z(_07637_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19492_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[27][10] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[26][10] ),
+ .S(net584),
+ .Z(_07638_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19493_ (.I0(_07637_),
+ .I1(_07638_),
+ .S(net557),
+ .Z(_07639_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _19494_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[28][10] ),
+ .A2(net612),
+ .ZN(_07640_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _19495_ (.A1(net584),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[29][10] ),
+ .B(net570),
+ .ZN(_07641_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _19496_ (.A1(net584),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[31][10] ),
+ .ZN(_07642_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _19497_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[30][10] ),
+ .A2(net612),
+ .B(net557),
+ .ZN(_07643_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _19498_ (.A1(_07643_),
+ .A2(_07642_),
+ .B1(_07641_),
+ .B2(_07640_),
+ .C(net628),
+ .ZN(_07644_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _19499_ (.A1(_07639_),
+ .A2(net628),
+ .B(net545),
+ .C(_07644_),
+ .ZN(_07645_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _19500_ (.A1(_07636_),
+ .A2(_07645_),
+ .ZN(_07646_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _19501_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[4][10] ),
+ .A2(net612),
+ .ZN(_07647_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _19502_ (.A1(net584),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[5][10] ),
+ .B(net571),
+ .ZN(_07648_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _19503_ (.A1(net585),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[7][10] ),
+ .ZN(_07649_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _19504_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[6][10] ),
+ .A2(net612),
+ .B(net557),
+ .ZN(_07650_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _19505_ (.A1(_07650_),
+ .A2(_07649_),
+ .B1(_07648_),
+ .B2(_07647_),
+ .C(net628),
+ .ZN(_07651_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19506_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[1][10] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[0][10] ),
+ .S(net585),
+ .Z(_07652_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19507_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[3][10] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[2][10] ),
+ .S(net584),
+ .Z(_07653_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19508_ (.I0(_07652_),
+ .I1(_07653_),
+ .S(net557),
+ .Z(_07654_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _19509_ (.A1(_07654_),
+ .A2(net628),
+ .B(net549),
+ .C(_07651_),
+ .ZN(_07655_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _19510_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[12][10] ),
+ .A2(net612),
+ .ZN(_07656_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _19511_ (.A1(net584),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[13][10] ),
+ .B(net571),
+ .ZN(_07657_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _19512_ (.A1(net584),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[15][10] ),
+ .ZN(_07658_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _19513_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[14][10] ),
+ .A2(net612),
+ .B(net557),
+ .ZN(_07659_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _19514_ (.A1(_07659_),
+ .A2(_07658_),
+ .B1(_07657_),
+ .B2(_07656_),
+ .C(net628),
+ .ZN(_07660_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19515_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[9][10] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[8][10] ),
+ .S(net584),
+ .Z(_07661_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19516_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[11][10] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[10][10] ),
+ .S(net584),
+ .Z(_07662_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19517_ (.I0(_07661_),
+ .I1(_07662_),
+ .S(net557),
+ .Z(_07663_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _19518_ (.A1(_07663_),
+ .A2(net628),
+ .B(net545),
+ .C(_07660_),
+ .ZN(_07664_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _19519_ (.A1(_07655_),
+ .A2(_07664_),
+ .ZN(_07665_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19520_ (.I0(_07665_),
+ .I1(_07646_),
+ .S(net539),
+ .Z(_00001_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _19521_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[20][11] ),
+ .A2(net617),
+ .ZN(_07666_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _19522_ (.A1(net595),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[21][11] ),
+ .B(net574),
+ .ZN(_07667_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _19523_ (.A1(net595),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[23][11] ),
+ .ZN(_07668_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _19524_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[22][11] ),
+ .A2(net617),
+ .B(net562),
+ .ZN(_07669_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _19525_ (.A1(_07669_),
+ .A2(_07668_),
+ .B1(_07667_),
+ .B2(_07666_),
+ .C(net633),
+ .ZN(_07670_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19526_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[17][11] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[16][11] ),
+ .S(net595),
+ .Z(_07671_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19527_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[19][11] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[18][11] ),
+ .S(net595),
+ .Z(_07672_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19528_ (.I0(_07671_),
+ .I1(_07672_),
+ .S(net562),
+ .Z(_07673_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _19529_ (.A1(_07673_),
+ .A2(net633),
+ .B(net550),
+ .C(_07670_),
+ .ZN(_07674_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19530_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[25][11] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[24][11] ),
+ .S(net595),
+ .Z(_07675_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19531_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[27][11] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[26][11] ),
+ .S(net595),
+ .Z(_07676_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19532_ (.I0(_07675_),
+ .I1(_07676_),
+ .S(net562),
+ .Z(_07677_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _19533_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[28][11] ),
+ .A2(net617),
+ .ZN(_07678_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _19534_ (.A1(net595),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[29][11] ),
+ .B(net574),
+ .ZN(_07679_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _19535_ (.A1(net595),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[31][11] ),
+ .ZN(_07680_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _19536_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[30][11] ),
+ .A2(net617),
+ .B(net562),
+ .ZN(_07681_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _19537_ (.A1(_07681_),
+ .A2(_07680_),
+ .B1(_07679_),
+ .B2(_07678_),
+ .C(net633),
+ .ZN(_07682_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _19538_ (.A1(_07677_),
+ .A2(net633),
+ .B(net547),
+ .C(_07682_),
+ .ZN(_07683_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _19539_ (.A1(_07674_),
+ .A2(_07683_),
+ .ZN(_07684_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _19540_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[4][11] ),
+ .A2(net617),
+ .ZN(_07685_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _19541_ (.A1(net594),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[5][11] ),
+ .B(net574),
+ .ZN(_07686_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _19542_ (.A1(net595),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[7][11] ),
+ .ZN(_07687_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _19543_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[6][11] ),
+ .A2(net617),
+ .B(net562),
+ .ZN(_07688_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _19544_ (.A1(_07688_),
+ .A2(_07687_),
+ .B1(_07686_),
+ .B2(_07685_),
+ .C(net633),
+ .ZN(_07689_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19545_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[1][11] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[0][11] ),
+ .S(net594),
+ .Z(_07690_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19546_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[3][11] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[2][11] ),
+ .S(net595),
+ .Z(_07691_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19547_ (.I0(_07690_),
+ .I1(_07691_),
+ .S(net562),
+ .Z(_07692_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _19548_ (.A1(_07692_),
+ .A2(net633),
+ .B(net550),
+ .C(_07689_),
+ .ZN(_07693_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _19549_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[12][11] ),
+ .A2(net617),
+ .ZN(_07694_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _19550_ (.A1(net595),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[13][11] ),
+ .B(net574),
+ .ZN(_07695_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _19551_ (.A1(net595),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[15][11] ),
+ .ZN(_07696_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _19552_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[14][11] ),
+ .A2(net617),
+ .B(net562),
+ .ZN(_07697_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _19553_ (.A1(_07697_),
+ .A2(_07696_),
+ .B1(_07695_),
+ .B2(_07694_),
+ .C(net633),
+ .ZN(_07698_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19554_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[9][11] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[8][11] ),
+ .S(net595),
+ .Z(_07699_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19555_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[11][11] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[10][11] ),
+ .S(net595),
+ .Z(_07700_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19556_ (.I0(_07699_),
+ .I1(_07700_),
+ .S(net562),
+ .Z(_07701_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _19557_ (.A1(_07701_),
+ .A2(net633),
+ .B(net547),
+ .C(_07698_),
+ .ZN(_07702_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _19558_ (.A1(_07693_),
+ .A2(_07702_),
+ .ZN(_07703_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19559_ (.I0(_07703_),
+ .I1(_07684_),
+ .S(_07256_),
+ .Z(_00002_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _19560_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[20][12] ),
+ .A2(net613),
+ .ZN(_07704_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _19561_ (.A1(net586),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[21][12] ),
+ .B(net572),
+ .ZN(_07705_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _19562_ (.A1(net586),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[23][12] ),
+ .ZN(_07706_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _19563_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[22][12] ),
+ .A2(net613),
+ .B(net558),
+ .ZN(_07707_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _19564_ (.A1(_07707_),
+ .A2(_07706_),
+ .B1(_07705_),
+ .B2(_07704_),
+ .C(net629),
+ .ZN(_07708_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19565_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[17][12] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[16][12] ),
+ .S(net586),
+ .Z(_07709_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19566_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[19][12] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[18][12] ),
+ .S(net586),
+ .Z(_07710_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19567_ (.I0(_07709_),
+ .I1(_07710_),
+ .S(net558),
+ .Z(_07711_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _19568_ (.A1(_07711_),
+ .A2(net629),
+ .B(net549),
+ .C(_07708_),
+ .ZN(_07712_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19569_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[25][12] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[24][12] ),
+ .S(net586),
+ .Z(_07713_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19570_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[27][12] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[26][12] ),
+ .S(net586),
+ .Z(_07714_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19571_ (.I0(_07713_),
+ .I1(_07714_),
+ .S(net558),
+ .Z(_07715_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _19572_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[28][12] ),
+ .A2(net613),
+ .ZN(_07716_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _19573_ (.A1(net586),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[29][12] ),
+ .B(net572),
+ .ZN(_07717_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _19574_ (.A1(net586),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[31][12] ),
+ .ZN(_07718_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _19575_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[30][12] ),
+ .A2(net613),
+ .B(net558),
+ .ZN(_07719_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _19576_ (.A1(_07719_),
+ .A2(_07718_),
+ .B1(_07717_),
+ .B2(_07716_),
+ .C(net629),
+ .ZN(_07720_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _19577_ (.A1(_07715_),
+ .A2(net629),
+ .B(net546),
+ .C(_07720_),
+ .ZN(_07721_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _19578_ (.A1(_07712_),
+ .A2(_07721_),
+ .ZN(_07722_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _19579_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[4][12] ),
+ .A2(net613),
+ .ZN(_07723_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _19580_ (.A1(net587),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[5][12] ),
+ .B(net572),
+ .ZN(_07724_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _19581_ (.A1(net586),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[7][12] ),
+ .ZN(_07725_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _19582_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[6][12] ),
+ .A2(net613),
+ .B(net558),
+ .ZN(_07726_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _19583_ (.A1(_07726_),
+ .A2(_07725_),
+ .B1(_07724_),
+ .B2(_07723_),
+ .C(net629),
+ .ZN(_07727_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19584_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[1][12] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[0][12] ),
+ .S(net586),
+ .Z(_07728_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19585_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[3][12] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[2][12] ),
+ .S(net587),
+ .Z(_07729_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19586_ (.I0(_07728_),
+ .I1(_07729_),
+ .S(net558),
+ .Z(_07730_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _19587_ (.A1(_07730_),
+ .A2(net629),
+ .B(net549),
+ .C(_07727_),
+ .ZN(_07731_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _19588_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[12][12] ),
+ .A2(net613),
+ .ZN(_07732_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _19589_ (.A1(net586),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[13][12] ),
+ .B(net572),
+ .ZN(_07733_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _19590_ (.A1(net587),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[15][12] ),
+ .ZN(_07734_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _19591_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[14][12] ),
+ .A2(net613),
+ .B(net558),
+ .ZN(_07735_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _19592_ (.A1(_07735_),
+ .A2(_07734_),
+ .B1(_07733_),
+ .B2(_07732_),
+ .C(net629),
+ .ZN(_07736_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19593_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[9][12] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[8][12] ),
+ .S(net587),
+ .Z(_07737_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19594_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[11][12] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[10][12] ),
+ .S(net586),
+ .Z(_07738_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19595_ (.I0(_07737_),
+ .I1(_07738_),
+ .S(net558),
+ .Z(_07739_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _19596_ (.A1(_07739_),
+ .A2(net629),
+ .B(net546),
+ .C(_07736_),
+ .ZN(_07740_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _19597_ (.A1(_07731_),
+ .A2(_07740_),
+ .ZN(_07741_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19598_ (.I0(_07741_),
+ .I1(_07722_),
+ .S(net540),
+ .Z(_00003_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _19599_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[20][13] ),
+ .A2(net610),
+ .ZN(_07742_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _19600_ (.A1(net580),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[21][13] ),
+ .B(net570),
+ .ZN(_07743_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _19601_ (.A1(net580),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[23][13] ),
+ .ZN(_07744_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _19602_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[22][13] ),
+ .A2(net610),
+ .B(net555),
+ .ZN(_07745_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _19603_ (.A1(_07745_),
+ .A2(_07744_),
+ .B1(_07743_),
+ .B2(_07742_),
+ .C(net626),
+ .ZN(_07746_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19604_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[17][13] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[16][13] ),
+ .S(net580),
+ .Z(_07747_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19605_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[19][13] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[18][13] ),
+ .S(net580),
+ .Z(_07748_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19606_ (.I0(_07747_),
+ .I1(_07748_),
+ .S(net555),
+ .Z(_07749_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _19607_ (.A1(_07749_),
+ .A2(net626),
+ .B(net549),
+ .C(_07746_),
+ .ZN(_07750_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19608_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[25][13] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[24][13] ),
+ .S(net580),
+ .Z(_07751_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19609_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[27][13] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[26][13] ),
+ .S(net580),
+ .Z(_07752_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19610_ (.I0(_07751_),
+ .I1(_07752_),
+ .S(net555),
+ .Z(_07753_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _19611_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[28][13] ),
+ .A2(net610),
+ .ZN(_07754_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _19612_ (.A1(net580),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[29][13] ),
+ .B(net570),
+ .ZN(_07755_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _19613_ (.A1(net580),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[31][13] ),
+ .ZN(_07756_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _19614_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[30][13] ),
+ .A2(net610),
+ .B(net555),
+ .ZN(_07757_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _19615_ (.A1(_07757_),
+ .A2(_07756_),
+ .B1(_07755_),
+ .B2(_07754_),
+ .C(net626),
+ .ZN(_07758_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _19616_ (.A1(_07753_),
+ .A2(net626),
+ .B(net545),
+ .C(_07758_),
+ .ZN(_07759_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _19617_ (.A1(_07750_),
+ .A2(_07759_),
+ .ZN(_07760_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _19618_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[4][13] ),
+ .A2(net610),
+ .ZN(_07761_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _19619_ (.A1(net581),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[5][13] ),
+ .B(net570),
+ .ZN(_07762_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _19620_ (.A1(net581),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[7][13] ),
+ .ZN(_07763_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _19621_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[6][13] ),
+ .A2(net610),
+ .B(net555),
+ .ZN(_07764_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _19622_ (.A1(_07764_),
+ .A2(_07763_),
+ .B1(_07762_),
+ .B2(_07761_),
+ .C(net626),
+ .ZN(_07765_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19623_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[1][13] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[0][13] ),
+ .S(net581),
+ .Z(_07766_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19624_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[3][13] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[2][13] ),
+ .S(net581),
+ .Z(_07767_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19625_ (.I0(_07766_),
+ .I1(_07767_),
+ .S(net555),
+ .Z(_07768_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _19626_ (.A1(_07768_),
+ .A2(net626),
+ .B(net549),
+ .C(_07765_),
+ .ZN(_07769_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _19627_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[12][13] ),
+ .A2(net610),
+ .ZN(_07770_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _19628_ (.A1(net580),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[13][13] ),
+ .B(net570),
+ .ZN(_07771_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _19629_ (.A1(net581),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[15][13] ),
+ .ZN(_07772_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _19630_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[14][13] ),
+ .A2(net609),
+ .B(net554),
+ .ZN(_07773_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _19631_ (.A1(_07773_),
+ .A2(_07772_),
+ .B1(_07771_),
+ .B2(_07770_),
+ .C(net626),
+ .ZN(_07774_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19632_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[9][13] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[8][13] ),
+ .S(net581),
+ .Z(_07775_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19633_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[11][13] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[10][13] ),
+ .S(net581),
+ .Z(_07776_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19634_ (.I0(_07775_),
+ .I1(_07776_),
+ .S(net555),
+ .Z(_07777_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _19635_ (.A1(_07777_),
+ .A2(net626),
+ .B(net545),
+ .C(_07774_),
+ .ZN(_07778_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _19636_ (.A1(_07769_),
+ .A2(_07778_),
+ .ZN(_07779_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19637_ (.I0(_07779_),
+ .I1(_07760_),
+ .S(net540),
+ .Z(_00004_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _19638_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[20][14] ),
+ .A2(net609),
+ .ZN(_07780_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _19639_ (.A1(net578),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[21][14] ),
+ .B(net570),
+ .ZN(_07781_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _19640_ (.A1(net578),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[23][14] ),
+ .ZN(_07782_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _19641_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[22][14] ),
+ .A2(net609),
+ .B(net554),
+ .ZN(_07783_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _19642_ (.A1(_07783_),
+ .A2(_07782_),
+ .B1(_07781_),
+ .B2(_07780_),
+ .C(net625),
+ .ZN(_07784_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19643_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[17][14] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[16][14] ),
+ .S(net578),
+ .Z(_07785_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19644_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[19][14] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[18][14] ),
+ .S(net578),
+ .Z(_07786_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19645_ (.I0(_07785_),
+ .I1(_07786_),
+ .S(net554),
+ .Z(_07787_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _19646_ (.A1(_07787_),
+ .A2(net625),
+ .B(net549),
+ .C(_07784_),
+ .ZN(_07788_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19647_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[25][14] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[24][14] ),
+ .S(net578),
+ .Z(_07789_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19648_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[27][14] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[26][14] ),
+ .S(net580),
+ .Z(_07790_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19649_ (.I0(_07789_),
+ .I1(_07790_),
+ .S(net554),
+ .Z(_07791_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _19650_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[28][14] ),
+ .A2(net609),
+ .ZN(_07792_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _19651_ (.A1(net578),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[29][14] ),
+ .B(net570),
+ .ZN(_07793_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _19652_ (.A1(net578),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[31][14] ),
+ .ZN(_07794_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _19653_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[30][14] ),
+ .A2(net609),
+ .B(net554),
+ .ZN(_07795_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _19654_ (.A1(_07795_),
+ .A2(_07794_),
+ .B1(_07793_),
+ .B2(_07792_),
+ .C(net625),
+ .ZN(_07796_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _19655_ (.A1(_07791_),
+ .A2(net625),
+ .B(net545),
+ .C(_07796_),
+ .ZN(_07797_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _19656_ (.A1(_07788_),
+ .A2(_07797_),
+ .ZN(_07798_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _19657_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[4][14] ),
+ .A2(net609),
+ .ZN(_07799_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _19658_ (.A1(net579),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[5][14] ),
+ .B(net570),
+ .ZN(_07800_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _19659_ (.A1(net579),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[7][14] ),
+ .ZN(_07801_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _19660_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[6][14] ),
+ .A2(net609),
+ .B(net554),
+ .ZN(_07802_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _19661_ (.A1(_07802_),
+ .A2(_07801_),
+ .B1(_07800_),
+ .B2(_07799_),
+ .C(net625),
+ .ZN(_07803_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19662_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[1][14] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[0][14] ),
+ .S(net579),
+ .Z(_07804_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19663_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[3][14] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[2][14] ),
+ .S(net579),
+ .Z(_07805_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19664_ (.I0(_07804_),
+ .I1(_07805_),
+ .S(net554),
+ .Z(_07806_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _19665_ (.A1(_07806_),
+ .A2(net625),
+ .B(net549),
+ .C(_07803_),
+ .ZN(_07807_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _19666_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[12][14] ),
+ .A2(net609),
+ .ZN(_07808_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _19667_ (.A1(net578),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[13][14] ),
+ .B(net570),
+ .ZN(_07809_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _19668_ (.A1(net579),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[15][14] ),
+ .ZN(_07810_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _19669_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[14][14] ),
+ .A2(net609),
+ .B(net554),
+ .ZN(_07811_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _19670_ (.A1(_07811_),
+ .A2(_07810_),
+ .B1(_07809_),
+ .B2(_07808_),
+ .C(net625),
+ .ZN(_07812_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19671_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[9][14] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[8][14] ),
+ .S(net578),
+ .Z(_07813_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19672_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[11][14] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[10][14] ),
+ .S(net578),
+ .Z(_07814_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19673_ (.I0(_07813_),
+ .I1(_07814_),
+ .S(net554),
+ .Z(_07815_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _19674_ (.A1(_07815_),
+ .A2(net625),
+ .B(net545),
+ .C(_07812_),
+ .ZN(_07816_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _19675_ (.A1(_07807_),
+ .A2(_07816_),
+ .ZN(_07817_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19676_ (.I0(_07817_),
+ .I1(_07798_),
+ .S(net540),
+ .Z(_00005_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _19677_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[20][15] ),
+ .A2(net614),
+ .ZN(_07818_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _19678_ (.A1(net588),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[21][15] ),
+ .B(net572),
+ .ZN(_07819_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _19679_ (.A1(net588),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[23][15] ),
+ .ZN(_07820_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _19680_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[22][15] ),
+ .A2(net614),
+ .B(net559),
+ .ZN(_07821_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _19681_ (.A1(_07821_),
+ .A2(_07820_),
+ .B1(_07819_),
+ .B2(_07818_),
+ .C(net629),
+ .ZN(_07822_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19682_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[17][15] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[16][15] ),
+ .S(net588),
+ .Z(_07823_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19683_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[19][15] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[18][15] ),
+ .S(net588),
+ .Z(_07824_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19684_ (.I0(_07823_),
+ .I1(_07824_),
+ .S(net559),
+ .Z(_07825_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _19685_ (.A1(_07825_),
+ .A2(net629),
+ .B(net549),
+ .C(_07822_),
+ .ZN(_07826_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19686_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[25][15] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[24][15] ),
+ .S(net588),
+ .Z(_07827_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19687_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[27][15] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[26][15] ),
+ .S(net588),
+ .Z(_07828_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19688_ (.I0(_07827_),
+ .I1(_07828_),
+ .S(net559),
+ .Z(_07829_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _19689_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[28][15] ),
+ .A2(net614),
+ .ZN(_07830_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _19690_ (.A1(net588),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[29][15] ),
+ .B(net572),
+ .ZN(_07831_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _19691_ (.A1(net588),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[31][15] ),
+ .ZN(_07832_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _19692_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[30][15] ),
+ .A2(net614),
+ .B(net559),
+ .ZN(_07833_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _19693_ (.A1(_07833_),
+ .A2(_07832_),
+ .B1(_07831_),
+ .B2(_07830_),
+ .C(net629),
+ .ZN(_07834_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _19694_ (.A1(_07829_),
+ .A2(net630),
+ .B(net546),
+ .C(_07834_),
+ .ZN(_07835_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _19695_ (.A1(_07826_),
+ .A2(_07835_),
+ .ZN(_07836_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _19696_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[4][15] ),
+ .A2(net613),
+ .ZN(_07837_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _19697_ (.A1(net589),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[5][15] ),
+ .B(net572),
+ .ZN(_07838_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _19698_ (.A1(net589),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[7][15] ),
+ .ZN(_07839_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _19699_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[6][15] ),
+ .A2(net613),
+ .B(net559),
+ .ZN(_07840_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _19700_ (.A1(_07840_),
+ .A2(_07839_),
+ .B1(_07838_),
+ .B2(_07837_),
+ .C(net630),
+ .ZN(_07841_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19701_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[1][15] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[0][15] ),
+ .S(net589),
+ .Z(_07842_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19702_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[3][15] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[2][15] ),
+ .S(net589),
+ .Z(_07843_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19703_ (.I0(_07842_),
+ .I1(_07843_),
+ .S(net559),
+ .Z(_07844_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _19704_ (.A1(_07844_),
+ .A2(net630),
+ .B(net549),
+ .C(_07841_),
+ .ZN(_07845_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _19705_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[12][15] ),
+ .A2(net614),
+ .ZN(_07846_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _19706_ (.A1(net588),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[13][15] ),
+ .B(net572),
+ .ZN(_07847_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _19707_ (.A1(net589),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[15][15] ),
+ .ZN(_07848_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _19708_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[14][15] ),
+ .A2(net614),
+ .B(net559),
+ .ZN(_07849_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _19709_ (.A1(_07849_),
+ .A2(_07848_),
+ .B1(_07847_),
+ .B2(_07846_),
+ .C(net630),
+ .ZN(_07850_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19710_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[9][15] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[8][15] ),
+ .S(net589),
+ .Z(_07851_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19711_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[11][15] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[10][15] ),
+ .S(net589),
+ .Z(_07852_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19712_ (.I0(_07851_),
+ .I1(_07852_),
+ .S(net559),
+ .Z(_07853_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _19713_ (.A1(_07853_),
+ .A2(net630),
+ .B(net546),
+ .C(_07850_),
+ .ZN(_07854_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _19714_ (.A1(_07845_),
+ .A2(_07854_),
+ .ZN(_07855_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19715_ (.I0(_07855_),
+ .I1(_07836_),
+ .S(net541),
+ .Z(_00006_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _19716_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[20][16] ),
+ .A2(net615),
+ .ZN(_07856_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _19717_ (.A1(net591),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[21][16] ),
+ .B(net573),
+ .ZN(_07857_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _19718_ (.A1(net592),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[23][16] ),
+ .ZN(_07858_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _19719_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[22][16] ),
+ .A2(net615),
+ .B(net560),
+ .ZN(_07859_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _19720_ (.A1(_07859_),
+ .A2(_07858_),
+ .B1(_07857_),
+ .B2(_07856_),
+ .C(net631),
+ .ZN(_07860_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19721_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[17][16] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[16][16] ),
+ .S(net592),
+ .Z(_07861_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19722_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[19][16] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[18][16] ),
+ .S(net592),
+ .Z(_07862_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19723_ (.I0(_07861_),
+ .I1(_07862_),
+ .S(net560),
+ .Z(_07863_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _19724_ (.A1(_07863_),
+ .A2(net632),
+ .B(net552),
+ .C(_07860_),
+ .ZN(_07864_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19725_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[25][16] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[24][16] ),
+ .S(net592),
+ .Z(_07865_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19726_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[27][16] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[26][16] ),
+ .S(net592),
+ .Z(_07866_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19727_ (.I0(_07865_),
+ .I1(_07866_),
+ .S(net560),
+ .Z(_07867_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _19728_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[28][16] ),
+ .A2(net615),
+ .ZN(_07868_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _19729_ (.A1(net592),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[29][16] ),
+ .B(net573),
+ .ZN(_07869_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _19730_ (.A1(net592),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[31][16] ),
+ .ZN(_07870_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _19731_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[30][16] ),
+ .A2(net615),
+ .B(net561),
+ .ZN(_07871_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _19732_ (.A1(_07871_),
+ .A2(_07870_),
+ .B1(_07869_),
+ .B2(_07868_),
+ .C(net631),
+ .ZN(_07872_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _19733_ (.A1(_07867_),
+ .A2(net632),
+ .B(net545),
+ .C(_07872_),
+ .ZN(_07873_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _19734_ (.A1(_07864_),
+ .A2(_07873_),
+ .ZN(_07874_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19735_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[1][16] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[0][16] ),
+ .S(net591),
+ .Z(_07875_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19736_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[3][16] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[2][16] ),
+ .S(net592),
+ .Z(_07876_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19737_ (.I0(_07875_),
+ .I1(_07876_),
+ .S(net561),
+ .Z(_07877_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _19738_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[4][16] ),
+ .A2(net615),
+ .ZN(_07878_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _19739_ (.A1(net592),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[5][16] ),
+ .B(net573),
+ .ZN(_07879_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _19740_ (.A1(net591),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[7][16] ),
+ .ZN(_07880_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _19741_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[6][16] ),
+ .A2(net615),
+ .B(net561),
+ .ZN(_07881_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _19742_ (.A1(_07881_),
+ .A2(_07880_),
+ .B1(_07879_),
+ .B2(_07878_),
+ .C(net632),
+ .ZN(_07882_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _19743_ (.A1(_07877_),
+ .A2(net632),
+ .B(net552),
+ .C(_07882_),
+ .ZN(_07883_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _19744_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[12][16] ),
+ .A2(net615),
+ .ZN(_07884_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _19745_ (.A1(net591),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[13][16] ),
+ .B(net573),
+ .ZN(_07885_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _19746_ (.A1(net591),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[15][16] ),
+ .ZN(_07886_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _19747_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[14][16] ),
+ .A2(net615),
+ .B(net561),
+ .ZN(_07887_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _19748_ (.A1(_07887_),
+ .A2(_07886_),
+ .B1(_07885_),
+ .B2(_07884_),
+ .C(net632),
+ .ZN(_07888_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19749_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[9][16] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[8][16] ),
+ .S(net591),
+ .Z(_07889_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19750_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[11][16] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[10][16] ),
+ .S(net591),
+ .Z(_07890_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19751_ (.I0(_07889_),
+ .I1(_07890_),
+ .S(net561),
+ .Z(_07891_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _19752_ (.A1(_07891_),
+ .A2(net632),
+ .B(net545),
+ .C(_07888_),
+ .ZN(_07892_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _19753_ (.A1(_07883_),
+ .A2(_07892_),
+ .ZN(_07893_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19754_ (.I0(_07893_),
+ .I1(_07874_),
+ .S(net541),
+ .Z(_00007_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _19755_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[20][17] ),
+ .A2(net614),
+ .ZN(_07894_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _19756_ (.A1(net589),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[21][17] ),
+ .B(net572),
+ .ZN(_07895_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _19757_ (.A1(net591),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[23][17] ),
+ .ZN(_07896_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _19758_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[22][17] ),
+ .A2(net615),
+ .B(net561),
+ .ZN(_07897_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _19759_ (.A1(_07897_),
+ .A2(_07896_),
+ .B1(_07895_),
+ .B2(_07894_),
+ .C(net630),
+ .ZN(_07898_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19760_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[17][17] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[16][17] ),
+ .S(net589),
+ .Z(_07899_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19761_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[19][17] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[18][17] ),
+ .S(net589),
+ .Z(_07900_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19762_ (.I0(_07899_),
+ .I1(_07900_),
+ .S(net558),
+ .Z(_07901_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _19763_ (.A1(_07901_),
+ .A2(net630),
+ .B(net552),
+ .C(_07898_),
+ .ZN(_07902_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19764_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[25][17] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[24][17] ),
+ .S(net589),
+ .Z(_07903_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19765_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[27][17] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[26][17] ),
+ .S(net589),
+ .Z(_07904_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19766_ (.I0(_07903_),
+ .I1(_07904_),
+ .S(net558),
+ .Z(_07905_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _19767_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[28][17] ),
+ .A2(net613),
+ .ZN(_07906_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _19768_ (.A1(net588),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[29][17] ),
+ .B(net572),
+ .ZN(_07907_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _19769_ (.A1(net589),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[31][17] ),
+ .ZN(_07908_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _19770_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[30][17] ),
+ .A2(net614),
+ .B(net558),
+ .ZN(_07909_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _19771_ (.A1(_07909_),
+ .A2(_07908_),
+ .B1(_07907_),
+ .B2(_07906_),
+ .C(net629),
+ .ZN(_07910_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _19772_ (.A1(_07905_),
+ .A2(net629),
+ .B(net546),
+ .C(_07910_),
+ .ZN(_07911_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _19773_ (.A1(_07902_),
+ .A2(_07911_),
+ .ZN(_07912_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _19774_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[4][17] ),
+ .A2(net615),
+ .ZN(_07913_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _19775_ (.A1(net591),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[5][17] ),
+ .B(net573),
+ .ZN(_07914_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _19776_ (.A1(net591),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[7][17] ),
+ .ZN(_07915_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _19777_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[6][17] ),
+ .A2(net615),
+ .B(net561),
+ .ZN(_07916_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _19778_ (.A1(_07916_),
+ .A2(_07915_),
+ .B1(_07914_),
+ .B2(_07913_),
+ .C(net632),
+ .ZN(_07917_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19779_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[1][17] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[0][17] ),
+ .S(net591),
+ .Z(_07918_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19780_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[3][17] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[2][17] ),
+ .S(net591),
+ .Z(_07919_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19781_ (.I0(_07918_),
+ .I1(_07919_),
+ .S(net561),
+ .Z(_07920_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _19782_ (.A1(_07920_),
+ .A2(net632),
+ .B(net549),
+ .C(_07917_),
+ .ZN(_07921_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _19783_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[12][17] ),
+ .A2(net615),
+ .ZN(_07922_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _19784_ (.A1(net591),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[13][17] ),
+ .B(net573),
+ .ZN(_07923_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _19785_ (.A1(net591),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[15][17] ),
+ .ZN(_07924_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _19786_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[14][17] ),
+ .A2(net615),
+ .B(net561),
+ .ZN(_07925_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _19787_ (.A1(_07925_),
+ .A2(_07924_),
+ .B1(_07923_),
+ .B2(_07922_),
+ .C(net632),
+ .ZN(_07926_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19788_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[9][17] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[8][17] ),
+ .S(net591),
+ .Z(_07927_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19789_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[11][17] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[10][17] ),
+ .S(net591),
+ .Z(_07928_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19790_ (.I0(_07927_),
+ .I1(_07928_),
+ .S(net561),
+ .Z(_07929_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _19791_ (.A1(_07929_),
+ .A2(net632),
+ .B(net546),
+ .C(_07926_),
+ .ZN(_07930_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _19792_ (.A1(_07921_),
+ .A2(_07930_),
+ .ZN(_07931_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19793_ (.I0(_07931_),
+ .I1(_07912_),
+ .S(net541),
+ .Z(_00008_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _19794_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[20][18] ),
+ .A2(net615),
+ .ZN(_07932_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _19795_ (.A1(net592),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[21][18] ),
+ .B(net575),
+ .ZN(_07933_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _19796_ (.A1(net601),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[23][18] ),
+ .ZN(_07934_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _19797_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[22][18] ),
+ .A2(net622),
+ .B(net565),
+ .ZN(_07935_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _19798_ (.A1(_07935_),
+ .A2(_07934_),
+ .B1(_07933_),
+ .B2(_07932_),
+ .C(net638),
+ .ZN(_07936_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19799_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[17][18] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[16][18] ),
+ .S(net601),
+ .Z(_07937_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19800_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[19][18] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[18][18] ),
+ .S(net592),
+ .Z(_07938_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19801_ (.I0(_07937_),
+ .I1(_07938_),
+ .S(net561),
+ .Z(_07939_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _19802_ (.A1(_07939_),
+ .A2(net631),
+ .B(net552),
+ .C(_07936_),
+ .ZN(_07940_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19803_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[25][18] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[24][18] ),
+ .S(net601),
+ .Z(_07941_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19804_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[27][18] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[26][18] ),
+ .S(net601),
+ .Z(_07942_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19805_ (.I0(_07941_),
+ .I1(_07942_),
+ .S(net560),
+ .Z(_07943_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _19806_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[28][18] ),
+ .A2(net616),
+ .ZN(_07944_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _19807_ (.A1(net592),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[29][18] ),
+ .B(net573),
+ .ZN(_07945_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _19808_ (.A1(net592),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[31][18] ),
+ .ZN(_07946_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _19809_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[30][18] ),
+ .A2(net615),
+ .B(net561),
+ .ZN(_07947_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _19810_ (.A1(_07947_),
+ .A2(_07946_),
+ .B1(_07945_),
+ .B2(_07944_),
+ .C(net632),
+ .ZN(_07948_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _19811_ (.A1(_07943_),
+ .A2(net631),
+ .B(net546),
+ .C(_07948_),
+ .ZN(_07949_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _19812_ (.A1(_07940_),
+ .A2(_07949_),
+ .ZN(_07950_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _19813_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[4][18] ),
+ .A2(net622),
+ .ZN(_07951_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _19814_ (.A1(net601),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[5][18] ),
+ .B(net575),
+ .ZN(_07952_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _19815_ (.A1(net601),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[7][18] ),
+ .ZN(_07953_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _19816_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[6][18] ),
+ .A2(net622),
+ .B(net567),
+ .ZN(_07954_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _19817_ (.A1(_07954_),
+ .A2(_07953_),
+ .B1(_07952_),
+ .B2(_07951_),
+ .C(net638),
+ .ZN(_07955_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19818_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[1][18] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[0][18] ),
+ .S(net601),
+ .Z(_07956_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19819_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[3][18] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[2][18] ),
+ .S(net601),
+ .Z(_07957_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19820_ (.I0(_07956_),
+ .I1(_07957_),
+ .S(net565),
+ .Z(_07958_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _19821_ (.A1(_07958_),
+ .A2(net638),
+ .B(net550),
+ .C(_07955_),
+ .ZN(_07959_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _19822_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[12][18] ),
+ .A2(net622),
+ .ZN(_07960_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _19823_ (.A1(net601),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[13][18] ),
+ .B(net575),
+ .ZN(_07961_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _19824_ (.A1(net601),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[15][18] ),
+ .ZN(_07962_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _19825_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[14][18] ),
+ .A2(net620),
+ .B(net567),
+ .ZN(_07963_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _19826_ (.A1(_07963_),
+ .A2(_07962_),
+ .B1(_07961_),
+ .B2(_07960_),
+ .C(net636),
+ .ZN(_07964_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19827_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[9][18] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[8][18] ),
+ .S(net601),
+ .Z(_07965_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19828_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[11][18] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[10][18] ),
+ .S(net601),
+ .Z(_07966_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19829_ (.I0(_07965_),
+ .I1(_07966_),
+ .S(net565),
+ .Z(_07967_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _19830_ (.A1(_07967_),
+ .A2(net638),
+ .B(net547),
+ .C(_07964_),
+ .ZN(_07968_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _19831_ (.A1(_07959_),
+ .A2(_07968_),
+ .ZN(_07969_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19832_ (.I0(_07969_),
+ .I1(_07950_),
+ .S(net543),
+ .Z(_00009_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _19833_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[20][19] ),
+ .A2(net621),
+ .ZN(_07970_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _19834_ (.A1(net606),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[21][19] ),
+ .B(net575),
+ .ZN(_07971_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _19835_ (.A1(net606),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[23][19] ),
+ .ZN(_07972_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _19836_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[22][19] ),
+ .A2(net621),
+ .B(net566),
+ .ZN(_07973_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _19837_ (.A1(_07973_),
+ .A2(_07972_),
+ .B1(_07971_),
+ .B2(_07970_),
+ .C(net637),
+ .ZN(_07974_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19838_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[17][19] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[16][19] ),
+ .S(net606),
+ .Z(_07975_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19839_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[19][19] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[18][19] ),
+ .S(net606),
+ .Z(_07976_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19840_ (.I0(_07975_),
+ .I1(_07976_),
+ .S(net566),
+ .Z(_07977_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _19841_ (.A1(_07977_),
+ .A2(net637),
+ .B(net550),
+ .C(_07974_),
+ .ZN(_07978_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19842_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[25][19] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[24][19] ),
+ .S(net605),
+ .Z(_07979_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19843_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[27][19] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[26][19] ),
+ .S(net605),
+ .Z(_07980_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19844_ (.I0(_07979_),
+ .I1(_07980_),
+ .S(net566),
+ .Z(_07981_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _19845_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[28][19] ),
+ .A2(net621),
+ .ZN(_07982_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _19846_ (.A1(net605),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[29][19] ),
+ .B(net575),
+ .ZN(_07983_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _19847_ (.A1(net605),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[31][19] ),
+ .ZN(_07984_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _19848_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[30][19] ),
+ .A2(net622),
+ .B(net566),
+ .ZN(_07985_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _19849_ (.A1(_07985_),
+ .A2(_07984_),
+ .B1(_07983_),
+ .B2(_07982_),
+ .C(net637),
+ .ZN(_07986_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _19850_ (.A1(_07981_),
+ .A2(net637),
+ .B(net547),
+ .C(_07986_),
+ .ZN(_07987_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _19851_ (.A1(_07978_),
+ .A2(_07987_),
+ .ZN(_07988_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _19852_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[4][19] ),
+ .A2(net621),
+ .ZN(_07989_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _19853_ (.A1(net604),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[5][19] ),
+ .B(net575),
+ .ZN(_07990_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _19854_ (.A1(net604),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[7][19] ),
+ .ZN(_07991_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _19855_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[6][19] ),
+ .A2(net621),
+ .B(net566),
+ .ZN(_07992_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _19856_ (.A1(_07992_),
+ .A2(_07991_),
+ .B1(_07990_),
+ .B2(_07989_),
+ .C(net637),
+ .ZN(_07993_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19857_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[1][19] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[0][19] ),
+ .S(net603),
+ .Z(_07994_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19858_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[3][19] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[2][19] ),
+ .S(net603),
+ .Z(_07995_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19859_ (.I0(_07994_),
+ .I1(_07995_),
+ .S(net566),
+ .Z(_07996_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _19860_ (.A1(_07996_),
+ .A2(net637),
+ .B(net550),
+ .C(_07993_),
+ .ZN(_07997_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _19861_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[12][19] ),
+ .A2(net622),
+ .ZN(_07998_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _19862_ (.A1(net604),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[13][19] ),
+ .B(net576),
+ .ZN(_07999_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _19863_ (.A1(net604),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[15][19] ),
+ .ZN(_08000_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _19864_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[14][19] ),
+ .A2(net622),
+ .B(net566),
+ .ZN(_08001_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _19865_ (.A1(_08001_),
+ .A2(_08000_),
+ .B1(_07999_),
+ .B2(_07998_),
+ .C(net637),
+ .ZN(_08002_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19866_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[9][19] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[8][19] ),
+ .S(net603),
+ .Z(_08003_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19867_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[11][19] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[10][19] ),
+ .S(net603),
+ .Z(_08004_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19868_ (.I0(_08003_),
+ .I1(_08004_),
+ .S(net566),
+ .Z(_08005_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _19869_ (.A1(_08005_),
+ .A2(net637),
+ .B(net547),
+ .C(_08002_),
+ .ZN(_08006_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _19870_ (.A1(_07997_),
+ .A2(_08006_),
+ .ZN(_08007_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19871_ (.I0(_08007_),
+ .I1(_07988_),
+ .S(net542),
+ .Z(_00010_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _19872_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[20][20] ),
+ .A2(net614),
+ .ZN(_08008_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _19873_ (.A1(net588),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[21][20] ),
+ .B(net572),
+ .ZN(_08009_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _19874_ (.A1(net588),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[23][20] ),
+ .ZN(_08010_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _19875_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[22][20] ),
+ .A2(net613),
+ .B(net559),
+ .ZN(_08011_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _19876_ (.A1(_08011_),
+ .A2(_08010_),
+ .B1(_08009_),
+ .B2(_08008_),
+ .C(net630),
+ .ZN(_08012_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19877_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[17][20] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[16][20] ),
+ .S(net588),
+ .Z(_08013_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19878_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[19][20] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[18][20] ),
+ .S(net588),
+ .Z(_08014_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19879_ (.I0(_08013_),
+ .I1(_08014_),
+ .S(net559),
+ .Z(_08015_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _19880_ (.A1(_08015_),
+ .A2(net630),
+ .B(net552),
+ .C(_08012_),
+ .ZN(_08016_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19881_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[25][20] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[24][20] ),
+ .S(net588),
+ .Z(_08017_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19882_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[27][20] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[26][20] ),
+ .S(net588),
+ .Z(_08018_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19883_ (.I0(_08017_),
+ .I1(_08018_),
+ .S(net559),
+ .Z(_08019_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _19884_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[28][20] ),
+ .A2(net614),
+ .ZN(_08020_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _19885_ (.A1(net588),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[29][20] ),
+ .B(net572),
+ .ZN(_08021_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _19886_ (.A1(net588),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[31][20] ),
+ .ZN(_08022_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _19887_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[30][20] ),
+ .A2(net614),
+ .B(net559),
+ .ZN(_08023_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _19888_ (.A1(_08023_),
+ .A2(_08022_),
+ .B1(_08021_),
+ .B2(_08020_),
+ .C(net630),
+ .ZN(_08024_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _19889_ (.A1(_08019_),
+ .A2(net630),
+ .B(net546),
+ .C(_08024_),
+ .ZN(_08025_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _19890_ (.A1(_08016_),
+ .A2(_08025_),
+ .ZN(_08026_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _19891_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[4][20] ),
+ .A2(net613),
+ .ZN(_08027_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _19892_ (.A1(net589),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[5][20] ),
+ .B(net572),
+ .ZN(_08028_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _19893_ (.A1(net588),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[7][20] ),
+ .ZN(_08029_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _19894_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[6][20] ),
+ .A2(net614),
+ .B(net559),
+ .ZN(_08030_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _19895_ (.A1(_08030_),
+ .A2(_08029_),
+ .B1(_08028_),
+ .B2(_08027_),
+ .C(net630),
+ .ZN(_08031_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19896_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[1][20] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[0][20] ),
+ .S(net588),
+ .Z(_08032_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19897_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[3][20] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[2][20] ),
+ .S(net589),
+ .Z(_08033_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19898_ (.I0(_08032_),
+ .I1(_08033_),
+ .S(net558),
+ .Z(_08034_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _19899_ (.A1(_08034_),
+ .A2(net629),
+ .B(net552),
+ .C(_08031_),
+ .ZN(_08035_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _19900_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[12][20] ),
+ .A2(net613),
+ .ZN(_08036_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _19901_ (.A1(net588),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[13][20] ),
+ .B(net572),
+ .ZN(_08037_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _19902_ (.A1(net589),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[15][20] ),
+ .ZN(_08038_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _19903_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[14][20] ),
+ .A2(net614),
+ .B(net559),
+ .ZN(_08039_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _19904_ (.A1(_08039_),
+ .A2(_08038_),
+ .B1(_08037_),
+ .B2(_08036_),
+ .C(net630),
+ .ZN(_08040_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19905_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[9][20] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[8][20] ),
+ .S(net589),
+ .Z(_08041_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19906_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[11][20] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[10][20] ),
+ .S(net588),
+ .Z(_08042_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19907_ (.I0(_08041_),
+ .I1(_08042_),
+ .S(net559),
+ .Z(_08043_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _19908_ (.A1(_08043_),
+ .A2(net630),
+ .B(net546),
+ .C(_08040_),
+ .ZN(_08044_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _19909_ (.A1(_08035_),
+ .A2(_08044_),
+ .ZN(_08045_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19910_ (.I0(_08045_),
+ .I1(_08026_),
+ .S(net540),
+ .Z(_00012_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _19911_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[20][21] ),
+ .A2(net619),
+ .ZN(_08046_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _19912_ (.A1(net598),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[21][21] ),
+ .B(net574),
+ .ZN(_08047_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _19913_ (.A1(net598),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[23][21] ),
+ .ZN(_08048_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _19914_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[22][21] ),
+ .A2(net619),
+ .B(net564),
+ .ZN(_08049_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _19915_ (.A1(_08049_),
+ .A2(_08048_),
+ .B1(_08047_),
+ .B2(_08046_),
+ .C(net635),
+ .ZN(_08050_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19916_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[17][21] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[16][21] ),
+ .S(net598),
+ .Z(_08051_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19917_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[19][21] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[18][21] ),
+ .S(net598),
+ .Z(_08052_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19918_ (.I0(_08051_),
+ .I1(_08052_),
+ .S(net564),
+ .Z(_08053_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _19919_ (.A1(_08053_),
+ .A2(net635),
+ .B(net550),
+ .C(_08050_),
+ .ZN(_08054_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19920_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[25][21] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[24][21] ),
+ .S(net607),
+ .Z(_08055_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19921_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[27][21] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[26][21] ),
+ .S(net607),
+ .Z(_08056_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19922_ (.I0(_08055_),
+ .I1(_08056_),
+ .S(net564),
+ .Z(_08057_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _19923_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[28][21] ),
+ .A2(net619),
+ .ZN(_08058_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _19924_ (.A1(net603),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[29][21] ),
+ .B(net576),
+ .ZN(_08059_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _19925_ (.A1(net603),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[31][21] ),
+ .ZN(_08060_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _19926_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[30][21] ),
+ .A2(net621),
+ .B(net566),
+ .ZN(_08061_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _19927_ (.A1(_08061_),
+ .A2(_08060_),
+ .B1(_08059_),
+ .B2(_08058_),
+ .C(net635),
+ .ZN(_08062_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _19928_ (.A1(_08057_),
+ .A2(net635),
+ .B(net547),
+ .C(_08062_),
+ .ZN(_08063_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _19929_ (.A1(_08054_),
+ .A2(_08063_),
+ .ZN(_08064_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _19930_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[4][21] ),
+ .A2(net619),
+ .ZN(_08065_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _19931_ (.A1(net603),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[5][21] ),
+ .B(net576),
+ .ZN(_08066_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _19932_ (.A1(net607),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[7][21] ),
+ .ZN(_08067_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _19933_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[6][21] ),
+ .A2(net621),
+ .B(net566),
+ .ZN(_08068_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _19934_ (.A1(_08068_),
+ .A2(_08067_),
+ .B1(_08066_),
+ .B2(_08065_),
+ .C(net635),
+ .ZN(_08069_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19935_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[1][21] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[0][21] ),
+ .S(net607),
+ .Z(_08070_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19936_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[3][21] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[2][21] ),
+ .S(net607),
+ .Z(_08071_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19937_ (.I0(_08070_),
+ .I1(_08071_),
+ .S(net564),
+ .Z(_08072_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _19938_ (.A1(_08072_),
+ .A2(net635),
+ .B(net550),
+ .C(_08069_),
+ .ZN(_08073_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _19939_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[12][21] ),
+ .A2(net618),
+ .ZN(_08074_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _19940_ (.A1(net597),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[13][21] ),
+ .B(net574),
+ .ZN(_08075_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _19941_ (.A1(net597),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[15][21] ),
+ .ZN(_08076_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _19942_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[14][21] ),
+ .A2(net618),
+ .B(net563),
+ .ZN(_08077_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _19943_ (.A1(_08077_),
+ .A2(_08076_),
+ .B1(_08075_),
+ .B2(_08074_),
+ .C(net633),
+ .ZN(_08078_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19944_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[9][21] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[8][21] ),
+ .S(net600),
+ .Z(_08079_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19945_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[11][21] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[10][21] ),
+ .S(net600),
+ .Z(_08080_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19946_ (.I0(_08079_),
+ .I1(_08080_),
+ .S(net562),
+ .Z(_08081_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _19947_ (.A1(_08081_),
+ .A2(net634),
+ .B(net547),
+ .C(_08078_),
+ .ZN(_08082_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _19948_ (.A1(_08073_),
+ .A2(_08082_),
+ .ZN(_08083_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19949_ (.I0(_08083_),
+ .I1(_08064_),
+ .S(net544),
+ .Z(_00013_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _19950_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[20][22] ),
+ .A2(net621),
+ .ZN(_08084_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _19951_ (.A1(net603),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[21][22] ),
+ .B(net576),
+ .ZN(_08085_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _19952_ (.A1(net603),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[23][22] ),
+ .ZN(_08086_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _19953_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[22][22] ),
+ .A2(net621),
+ .B(net566),
+ .ZN(_08087_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _19954_ (.A1(_08087_),
+ .A2(_08086_),
+ .B1(_08085_),
+ .B2(_08084_),
+ .C(net637),
+ .ZN(_08088_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19955_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[17][22] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[16][22] ),
+ .S(net603),
+ .Z(_08089_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19956_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[19][22] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[18][22] ),
+ .S(net603),
+ .Z(_08090_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19957_ (.I0(_08089_),
+ .I1(_08090_),
+ .S(net566),
+ .Z(_08091_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _19958_ (.A1(_08091_),
+ .A2(net637),
+ .B(net550),
+ .C(_08088_),
+ .ZN(_08092_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19959_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[25][22] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[24][22] ),
+ .S(net603),
+ .Z(_08093_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19960_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[27][22] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[26][22] ),
+ .S(net603),
+ .Z(_08094_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19961_ (.I0(_08093_),
+ .I1(_08094_),
+ .S(net566),
+ .Z(_08095_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _19962_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[28][22] ),
+ .A2(net621),
+ .ZN(_08096_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _19963_ (.A1(net603),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[29][22] ),
+ .B(net575),
+ .ZN(_08097_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _19964_ (.A1(net603),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[31][22] ),
+ .ZN(_08098_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _19965_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[30][22] ),
+ .A2(net621),
+ .B(net566),
+ .ZN(_08099_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _19966_ (.A1(_08099_),
+ .A2(_08098_),
+ .B1(_08097_),
+ .B2(_08096_),
+ .C(net637),
+ .ZN(_08100_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _19967_ (.A1(_08095_),
+ .A2(net637),
+ .B(net547),
+ .C(_08100_),
+ .ZN(_08101_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _19968_ (.A1(_08092_),
+ .A2(_08101_),
+ .ZN(_08102_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _19969_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[4][22] ),
+ .A2(net621),
+ .ZN(_08103_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _19970_ (.A1(net603),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[5][22] ),
+ .B(net575),
+ .ZN(_08104_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _19971_ (.A1(net603),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[7][22] ),
+ .ZN(_08105_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _19972_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[6][22] ),
+ .A2(net621),
+ .B(net566),
+ .ZN(_08106_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _19973_ (.A1(_08106_),
+ .A2(_08105_),
+ .B1(_08104_),
+ .B2(_08103_),
+ .C(net637),
+ .ZN(_08107_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19974_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[1][22] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[0][22] ),
+ .S(net603),
+ .Z(_08108_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19975_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[3][22] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[2][22] ),
+ .S(net603),
+ .Z(_08109_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19976_ (.I0(_08108_),
+ .I1(_08109_),
+ .S(net566),
+ .Z(_08110_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _19977_ (.A1(_08110_),
+ .A2(net637),
+ .B(net550),
+ .C(_08107_),
+ .ZN(_08111_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _19978_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[12][22] ),
+ .A2(net620),
+ .ZN(_08112_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _19979_ (.A1(net600),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[13][22] ),
+ .B(net575),
+ .ZN(_08113_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _19980_ (.A1(net603),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[15][22] ),
+ .ZN(_08114_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _19981_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[14][22] ),
+ .A2(net621),
+ .B(net566),
+ .ZN(_08115_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _19982_ (.A1(_08115_),
+ .A2(_08114_),
+ .B1(_08113_),
+ .B2(_08112_),
+ .C(net637),
+ .ZN(_08116_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19983_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[9][22] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[8][22] ),
+ .S(net603),
+ .Z(_08117_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19984_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[11][22] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[10][22] ),
+ .S(net603),
+ .Z(_08118_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19985_ (.I0(_08117_),
+ .I1(_08118_),
+ .S(net565),
+ .Z(_08119_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _19986_ (.A1(_08119_),
+ .A2(net637),
+ .B(net547),
+ .C(_08116_),
+ .ZN(_08120_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _19987_ (.A1(_08111_),
+ .A2(_08120_),
+ .ZN(_08121_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19988_ (.I0(_08121_),
+ .I1(_08102_),
+ .S(net544),
+ .Z(_00014_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _19989_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[20][23] ),
+ .A2(net615),
+ .ZN(_08122_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _19990_ (.A1(net591),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[21][23] ),
+ .B(net572),
+ .ZN(_08123_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _19991_ (.A1(net591),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[23][23] ),
+ .ZN(_08124_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _19992_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[22][23] ),
+ .A2(net615),
+ .B(net561),
+ .ZN(_08125_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _19993_ (.A1(_08125_),
+ .A2(_08124_),
+ .B1(_08123_),
+ .B2(_08122_),
+ .C(net632),
+ .ZN(_08126_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19994_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[17][23] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[16][23] ),
+ .S(net590),
+ .Z(_08127_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19995_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[19][23] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[18][23] ),
+ .S(net590),
+ .Z(_08128_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19996_ (.I0(_08127_),
+ .I1(_08128_),
+ .S(net560),
+ .Z(_08129_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _19997_ (.A1(_08129_),
+ .A2(net631),
+ .B(net553),
+ .C(_08126_),
+ .ZN(_08130_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19998_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[25][23] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[24][23] ),
+ .S(net592),
+ .Z(_08131_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _19999_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[27][23] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[26][23] ),
+ .S(net593),
+ .Z(_08132_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _20000_ (.I0(_08131_),
+ .I1(_08132_),
+ .S(net560),
+ .Z(_08133_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _20001_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[28][23] ),
+ .A2(net615),
+ .ZN(_08134_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _20002_ (.A1(net591),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[29][23] ),
+ .B(net573),
+ .ZN(_08135_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _20003_ (.A1(net592),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[31][23] ),
+ .ZN(_08136_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _20004_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[30][23] ),
+ .A2(net615),
+ .B(net560),
+ .ZN(_08137_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _20005_ (.A1(_08137_),
+ .A2(_08136_),
+ .B1(_08135_),
+ .B2(_08134_),
+ .C(net632),
+ .ZN(_08138_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _20006_ (.A1(_08133_),
+ .A2(net632),
+ .B(net546),
+ .C(_08138_),
+ .ZN(_08139_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _20007_ (.A1(_08130_),
+ .A2(_08139_),
+ .ZN(_08140_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _20008_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[1][23] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[0][23] ),
+ .S(net591),
+ .Z(_08141_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _20009_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[3][23] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[2][23] ),
+ .S(net591),
+ .Z(_08142_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _20010_ (.I0(_08141_),
+ .I1(_08142_),
+ .S(net560),
+ .Z(_08143_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _20011_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[4][23] ),
+ .A2(net616),
+ .ZN(_08144_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _20012_ (.A1(net593),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[5][23] ),
+ .B(net573),
+ .ZN(_08145_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _20013_ (.A1(net601),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[7][23] ),
+ .ZN(_08146_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _20014_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[6][23] ),
+ .A2(net615),
+ .B(net560),
+ .ZN(_08147_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _20015_ (.A1(_08147_),
+ .A2(_08146_),
+ .B1(_08145_),
+ .B2(_08144_),
+ .C(net631),
+ .ZN(_08148_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _20016_ (.A1(_08143_),
+ .A2(net631),
+ .B(net552),
+ .C(_08148_),
+ .ZN(_08149_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _20017_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[12][23] ),
+ .A2(net616),
+ .ZN(_08150_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _20018_ (.A1(net590),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[13][23] ),
+ .B(net573),
+ .ZN(_08151_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _20019_ (.A1(net593),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[15][23] ),
+ .ZN(_08152_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _20020_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[14][23] ),
+ .A2(net616),
+ .B(net560),
+ .ZN(_08153_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _20021_ (.A1(_08153_),
+ .A2(_08152_),
+ .B1(_08151_),
+ .B2(_08150_),
+ .C(net631),
+ .ZN(_08154_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _20022_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[9][23] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[8][23] ),
+ .S(net592),
+ .Z(_08155_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _20023_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[11][23] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[10][23] ),
+ .S(net593),
+ .Z(_08156_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _20024_ (.I0(_08155_),
+ .I1(_08156_),
+ .S(net560),
+ .Z(_08157_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _20025_ (.A1(_08157_),
+ .A2(net631),
+ .B(net546),
+ .C(_08154_),
+ .ZN(_08158_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _20026_ (.A1(_08149_),
+ .A2(_08158_),
+ .ZN(_08159_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _20027_ (.I0(_08159_),
+ .I1(_08140_),
+ .S(net541),
+ .Z(_00015_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _20028_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[20][24] ),
+ .A2(net620),
+ .ZN(_08160_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _20029_ (.A1(net599),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[21][24] ),
+ .B(net575),
+ .ZN(_08161_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _20030_ (.A1(net599),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[23][24] ),
+ .ZN(_08162_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _20031_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[22][24] ),
+ .A2(net620),
+ .B(net565),
+ .ZN(_08163_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _20032_ (.A1(_08163_),
+ .A2(_08162_),
+ .B1(_08161_),
+ .B2(_08160_),
+ .C(net636),
+ .ZN(_08164_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _20033_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[17][24] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[16][24] ),
+ .S(net599),
+ .Z(_08165_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _20034_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[19][24] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[18][24] ),
+ .S(net599),
+ .Z(_08166_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _20035_ (.I0(_08165_),
+ .I1(_08166_),
+ .S(net565),
+ .Z(_08167_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _20036_ (.A1(_08167_),
+ .A2(net636),
+ .B(net553),
+ .C(_08164_),
+ .ZN(_08168_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _20037_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[25][24] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[24][24] ),
+ .S(net599),
+ .Z(_08169_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _20038_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[27][24] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[26][24] ),
+ .S(net599),
+ .Z(_08170_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _20039_ (.I0(_08169_),
+ .I1(_08170_),
+ .S(net565),
+ .Z(_08171_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _20040_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[28][24] ),
+ .A2(net620),
+ .ZN(_08172_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _20041_ (.A1(net599),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[29][24] ),
+ .B(net575),
+ .ZN(_08173_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _20042_ (.A1(net599),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[31][24] ),
+ .ZN(_08174_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _20043_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[30][24] ),
+ .A2(net620),
+ .B(net565),
+ .ZN(_08175_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _20044_ (.A1(_08175_),
+ .A2(_08174_),
+ .B1(_08173_),
+ .B2(_08172_),
+ .C(net636),
+ .ZN(_08176_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _20045_ (.A1(_08171_),
+ .A2(net636),
+ .B(net547),
+ .C(_08176_),
+ .ZN(_08177_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _20046_ (.A1(_08168_),
+ .A2(_08177_),
+ .ZN(_08178_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _20047_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[4][24] ),
+ .A2(net620),
+ .ZN(_08179_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _20048_ (.A1(net599),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[5][24] ),
+ .B(net575),
+ .ZN(_08180_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _20049_ (.A1(net599),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[7][24] ),
+ .ZN(_08181_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _20050_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[6][24] ),
+ .A2(net620),
+ .B(net565),
+ .ZN(_08182_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _20051_ (.A1(_08182_),
+ .A2(_08181_),
+ .B1(_08180_),
+ .B2(_08179_),
+ .C(net636),
+ .ZN(_08183_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _20052_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[1][24] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[0][24] ),
+ .S(net599),
+ .Z(_08184_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _20053_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[3][24] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[2][24] ),
+ .S(net599),
+ .Z(_08185_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _20054_ (.I0(_08184_),
+ .I1(_08185_),
+ .S(net565),
+ .Z(_08186_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _20055_ (.A1(_08186_),
+ .A2(net636),
+ .B(net550),
+ .C(_08183_),
+ .ZN(_08187_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _20056_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[12][24] ),
+ .A2(net616),
+ .ZN(_08188_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _20057_ (.A1(net593),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[13][24] ),
+ .B(net572),
+ .ZN(_08189_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _20058_ (.A1(net599),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[15][24] ),
+ .ZN(_08190_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _20059_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[14][24] ),
+ .A2(net616),
+ .B(net560),
+ .ZN(_08191_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _20060_ (.A1(_08191_),
+ .A2(_08190_),
+ .B1(_08189_),
+ .B2(_08188_),
+ .C(net631),
+ .ZN(_08192_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _20061_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[9][24] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[8][24] ),
+ .S(net599),
+ .Z(_08193_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _20062_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[11][24] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[10][24] ),
+ .S(net599),
+ .Z(_08194_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _20063_ (.I0(_08193_),
+ .I1(_08194_),
+ .S(net560),
+ .Z(_08195_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _20064_ (.A1(_08195_),
+ .A2(net636),
+ .B(net547),
+ .C(_08192_),
+ .ZN(_08196_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _20065_ (.A1(_08187_),
+ .A2(_08196_),
+ .ZN(_08197_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _20066_ (.I0(_08197_),
+ .I1(_08178_),
+ .S(net542),
+ .Z(_00016_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _20067_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[20][25] ),
+ .A2(net620),
+ .ZN(_08198_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _20068_ (.A1(net600),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[21][25] ),
+ .B(net575),
+ .ZN(_08199_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _20069_ (.A1(net600),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[23][25] ),
+ .ZN(_08200_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _20070_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[22][25] ),
+ .A2(net620),
+ .B(net565),
+ .ZN(_08201_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _20071_ (.A1(_08201_),
+ .A2(_08200_),
+ .B1(_08199_),
+ .B2(_08198_),
+ .C(net636),
+ .ZN(_08202_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _20072_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[17][25] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[16][25] ),
+ .S(net600),
+ .Z(_08203_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _20073_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[19][25] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[18][25] ),
+ .S(net600),
+ .Z(_08204_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _20074_ (.I0(_08203_),
+ .I1(_08204_),
+ .S(net565),
+ .Z(_08205_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _20075_ (.A1(_08205_),
+ .A2(net636),
+ .B(net551),
+ .C(_08202_),
+ .ZN(_08206_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _20076_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[25][25] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[24][25] ),
+ .S(net600),
+ .Z(_08207_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _20077_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[27][25] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[26][25] ),
+ .S(net600),
+ .Z(_08208_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _20078_ (.I0(_08207_),
+ .I1(_08208_),
+ .S(net565),
+ .Z(_08209_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _20079_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[28][25] ),
+ .A2(net620),
+ .ZN(_08210_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _20080_ (.A1(net600),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[29][25] ),
+ .B(net575),
+ .ZN(_08211_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _20081_ (.A1(net600),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[31][25] ),
+ .ZN(_08212_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _20082_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[30][25] ),
+ .A2(net620),
+ .B(net565),
+ .ZN(_08213_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _20083_ (.A1(_08213_),
+ .A2(_08212_),
+ .B1(_08211_),
+ .B2(_08210_),
+ .C(net636),
+ .ZN(_08214_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _20084_ (.A1(_08209_),
+ .A2(net636),
+ .B(net548),
+ .C(_08214_),
+ .ZN(_08215_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _20085_ (.A1(_08206_),
+ .A2(_08215_),
+ .ZN(_08216_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _20086_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[4][25] ),
+ .A2(net620),
+ .ZN(_08217_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _20087_ (.A1(net599),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[5][25] ),
+ .B(net575),
+ .ZN(_08218_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _20088_ (.A1(net599),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[7][25] ),
+ .ZN(_08219_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _20089_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[6][25] ),
+ .A2(net620),
+ .B(net565),
+ .ZN(_08220_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _20090_ (.A1(_08220_),
+ .A2(_08219_),
+ .B1(_08218_),
+ .B2(_08217_),
+ .C(net636),
+ .ZN(_08221_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _20091_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[1][25] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[0][25] ),
+ .S(net600),
+ .Z(_08222_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _20092_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[3][25] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[2][25] ),
+ .S(net600),
+ .Z(_08223_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _20093_ (.I0(_08222_),
+ .I1(_08223_),
+ .S(net565),
+ .Z(_08224_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _20094_ (.A1(_08224_),
+ .A2(net636),
+ .B(net553),
+ .C(_08221_),
+ .ZN(_08225_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _20095_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[12][25] ),
+ .A2(net622),
+ .ZN(_08226_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _20096_ (.A1(net601),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[13][25] ),
+ .B(net575),
+ .ZN(_08227_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _20097_ (.A1(net602),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[15][25] ),
+ .ZN(_08228_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _20098_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[14][25] ),
+ .A2(net622),
+ .B(net565),
+ .ZN(_08229_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _20099_ (.A1(_08229_),
+ .A2(_08228_),
+ .B1(_08227_),
+ .B2(_08226_),
+ .C(net638),
+ .ZN(_08230_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _20100_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[9][25] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[8][25] ),
+ .S(net599),
+ .Z(_08231_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _20101_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[11][25] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[10][25] ),
+ .S(net599),
+ .Z(_08232_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _20102_ (.I0(_08231_),
+ .I1(_08232_),
+ .S(net565),
+ .Z(_08233_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _20103_ (.A1(_08233_),
+ .A2(net636),
+ .B(net548),
+ .C(_08230_),
+ .ZN(_08234_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _20104_ (.A1(_08225_),
+ .A2(_08234_),
+ .ZN(_08235_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _20105_ (.I0(_08235_),
+ .I1(_08216_),
+ .S(net542),
+ .Z(_00017_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _20106_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[20][26] ),
+ .A2(net621),
+ .ZN(_08236_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _20107_ (.A1(net604),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[21][26] ),
+ .B(net576),
+ .ZN(_08237_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _20108_ (.A1(net605),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[23][26] ),
+ .ZN(_08238_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _20109_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[22][26] ),
+ .A2(net621),
+ .B(net567),
+ .ZN(_08239_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _20110_ (.A1(_08239_),
+ .A2(_08238_),
+ .B1(_08237_),
+ .B2(_08236_),
+ .C(net638),
+ .ZN(_08240_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _20111_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[17][26] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[16][26] ),
+ .S(net605),
+ .Z(_08241_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _20112_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[19][26] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[18][26] ),
+ .S(net605),
+ .Z(_08242_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _20113_ (.I0(_08241_),
+ .I1(_08242_),
+ .S(net567),
+ .Z(_08243_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _20114_ (.A1(_08243_),
+ .A2(net638),
+ .B(net551),
+ .C(_08240_),
+ .ZN(_08244_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _20115_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[25][26] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[24][26] ),
+ .S(net604),
+ .Z(_08245_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _20116_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[27][26] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[26][26] ),
+ .S(net604),
+ .Z(_08246_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _20117_ (.I0(_08245_),
+ .I1(_08246_),
+ .S(net567),
+ .Z(_08247_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _20118_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[28][26] ),
+ .A2(net621),
+ .ZN(_08248_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _20119_ (.A1(net604),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[29][26] ),
+ .B(net576),
+ .ZN(_08249_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _20120_ (.A1(net604),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[31][26] ),
+ .ZN(_08250_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _20121_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[30][26] ),
+ .A2(net621),
+ .B(net567),
+ .ZN(_08251_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _20122_ (.A1(_08251_),
+ .A2(_08250_),
+ .B1(_08249_),
+ .B2(_08248_),
+ .C(net638),
+ .ZN(_08252_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _20123_ (.A1(_08247_),
+ .A2(net638),
+ .B(net548),
+ .C(_08252_),
+ .ZN(_08253_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _20124_ (.A1(_08244_),
+ .A2(_08253_),
+ .ZN(_08254_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _20125_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[4][26] ),
+ .A2(net622),
+ .ZN(_08255_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _20126_ (.A1(net601),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[5][26] ),
+ .B(net576),
+ .ZN(_08256_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _20127_ (.A1(net604),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[7][26] ),
+ .ZN(_08257_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _20128_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[6][26] ),
+ .A2(net621),
+ .B(net567),
+ .ZN(_08258_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _20129_ (.A1(_08258_),
+ .A2(_08257_),
+ .B1(_08256_),
+ .B2(_08255_),
+ .C(net638),
+ .ZN(_08259_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _20130_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[1][26] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[0][26] ),
+ .S(net604),
+ .Z(_08260_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _20131_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[3][26] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[2][26] ),
+ .S(net602),
+ .Z(_08261_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _20132_ (.I0(_08260_),
+ .I1(_08261_),
+ .S(net567),
+ .Z(_08262_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _20133_ (.A1(_08262_),
+ .A2(net638),
+ .B(net551),
+ .C(_08259_),
+ .ZN(_08263_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _20134_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[12][26] ),
+ .A2(net620),
+ .ZN(_08264_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _20135_ (.A1(net602),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[13][26] ),
+ .B(net575),
+ .ZN(_08265_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _20136_ (.A1(net604),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[15][26] ),
+ .ZN(_08266_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _20137_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[14][26] ),
+ .A2(net622),
+ .B(net567),
+ .ZN(_08267_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _20138_ (.A1(_08267_),
+ .A2(_08266_),
+ .B1(_08265_),
+ .B2(_08264_),
+ .C(net638),
+ .ZN(_08268_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _20139_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[9][26] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[8][26] ),
+ .S(net604),
+ .Z(_08269_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _20140_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[11][26] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[10][26] ),
+ .S(net602),
+ .Z(_08270_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _20141_ (.I0(_08269_),
+ .I1(_08270_),
+ .S(net565),
+ .Z(_08271_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _20142_ (.A1(_08271_),
+ .A2(net638),
+ .B(net548),
+ .C(_08268_),
+ .ZN(_08272_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _20143_ (.A1(_08263_),
+ .A2(_08272_),
+ .ZN(_08273_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _20144_ (.I0(_08273_),
+ .I1(_08254_),
+ .S(net542),
+ .Z(_00018_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _20145_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[20][27] ),
+ .A2(net622),
+ .ZN(_08274_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _20146_ (.A1(net604),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[21][27] ),
+ .B(net576),
+ .ZN(_08275_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _20147_ (.A1(net605),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[23][27] ),
+ .ZN(_08276_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _20148_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[22][27] ),
+ .A2(net621),
+ .B(net566),
+ .ZN(_08277_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _20149_ (.A1(_08277_),
+ .A2(_08276_),
+ .B1(_08275_),
+ .B2(_08274_),
+ .C(net637),
+ .ZN(_08278_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _20150_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[17][27] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[16][27] ),
+ .S(net605),
+ .Z(_08279_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _20151_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[19][27] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[18][27] ),
+ .S(net605),
+ .Z(_08280_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _20152_ (.I0(_08279_),
+ .I1(_08280_),
+ .S(net566),
+ .Z(_08281_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _20153_ (.A1(_08281_),
+ .A2(net637),
+ .B(net551),
+ .C(_08278_),
+ .ZN(_08282_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _20154_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[25][27] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[24][27] ),
+ .S(net605),
+ .Z(_08283_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _20155_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[27][27] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[26][27] ),
+ .S(net605),
+ .Z(_08284_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _20156_ (.I0(_08283_),
+ .I1(_08284_),
+ .S(net566),
+ .Z(_08285_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _20157_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[28][27] ),
+ .A2(net621),
+ .ZN(_08286_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _20158_ (.A1(net605),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[29][27] ),
+ .B(net576),
+ .ZN(_08287_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _20159_ (.A1(net605),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[31][27] ),
+ .ZN(_08288_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _20160_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[30][27] ),
+ .A2(net621),
+ .B(net566),
+ .ZN(_08289_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _20161_ (.A1(_08289_),
+ .A2(_08288_),
+ .B1(_08287_),
+ .B2(_08286_),
+ .C(net637),
+ .ZN(_08290_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _20162_ (.A1(_08285_),
+ .A2(net637),
+ .B(net548),
+ .C(_08290_),
+ .ZN(_08291_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _20163_ (.A1(_08282_),
+ .A2(_08291_),
+ .ZN(_08292_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _20164_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[4][27] ),
+ .A2(net622),
+ .ZN(_08293_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _20165_ (.A1(net604),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[5][27] ),
+ .B(net576),
+ .ZN(_08294_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _20166_ (.A1(net604),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[7][27] ),
+ .ZN(_08295_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _20167_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[6][27] ),
+ .A2(net622),
+ .B(net567),
+ .ZN(_08296_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _20168_ (.A1(_08296_),
+ .A2(_08295_),
+ .B1(_08294_),
+ .B2(_08293_),
+ .C(net637),
+ .ZN(_08297_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _20169_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[1][27] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[0][27] ),
+ .S(net604),
+ .Z(_08298_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _20170_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[3][27] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[2][27] ),
+ .S(net604),
+ .Z(_08299_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _20171_ (.I0(_08298_),
+ .I1(_08299_),
+ .S(net566),
+ .Z(_08300_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _20172_ (.A1(_08300_),
+ .A2(net637),
+ .B(net551),
+ .C(_08297_),
+ .ZN(_08301_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _20173_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[12][27] ),
+ .A2(net622),
+ .ZN(_08302_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _20174_ (.A1(net604),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[13][27] ),
+ .B(net576),
+ .ZN(_08303_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _20175_ (.A1(net604),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[15][27] ),
+ .ZN(_08304_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _20176_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[14][27] ),
+ .A2(net622),
+ .B(net567),
+ .ZN(_08305_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _20177_ (.A1(_08305_),
+ .A2(_08304_),
+ .B1(_08303_),
+ .B2(_08302_),
+ .C(net638),
+ .ZN(_08306_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _20178_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[9][27] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[8][27] ),
+ .S(net604),
+ .Z(_08307_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _20179_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[11][27] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[10][27] ),
+ .S(net604),
+ .Z(_08308_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _20180_ (.I0(_08307_),
+ .I1(_08308_),
+ .S(net567),
+ .Z(_08309_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _20181_ (.A1(_08309_),
+ .A2(net638),
+ .B(net547),
+ .C(_08306_),
+ .ZN(_08310_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _20182_ (.A1(_08301_),
+ .A2(_08310_),
+ .ZN(_08311_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _20183_ (.I0(_08311_),
+ .I1(_08292_),
+ .S(net544),
+ .Z(_00019_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _20184_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[20][28] ),
+ .A2(net620),
+ .ZN(_08312_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _20185_ (.A1(net601),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[21][28] ),
+ .B(net575),
+ .ZN(_08313_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _20186_ (.A1(net602),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[23][28] ),
+ .ZN(_08314_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _20187_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[22][28] ),
+ .A2(net620),
+ .B(net565),
+ .ZN(_08315_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _20188_ (.A1(_08315_),
+ .A2(_08314_),
+ .B1(_08313_),
+ .B2(_08312_),
+ .C(net636),
+ .ZN(_08316_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _20189_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[17][28] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[16][28] ),
+ .S(net602),
+ .Z(_08317_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _20190_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[19][28] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[18][28] ),
+ .S(net601),
+ .Z(_08318_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _20191_ (.I0(_08317_),
+ .I1(_08318_),
+ .S(net567),
+ .Z(_08319_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _20192_ (.A1(_08319_),
+ .A2(net636),
+ .B(net552),
+ .C(_08316_),
+ .ZN(_08320_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _20193_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[25][28] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[24][28] ),
+ .S(net602),
+ .Z(_08321_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _20194_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[27][28] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[26][28] ),
+ .S(net601),
+ .Z(_08322_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _20195_ (.I0(_08321_),
+ .I1(_08322_),
+ .S(net567),
+ .Z(_08323_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _20196_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[28][28] ),
+ .A2(net620),
+ .ZN(_08324_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _20197_ (.A1(net602),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[29][28] ),
+ .B(net575),
+ .ZN(_08325_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _20198_ (.A1(net602),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[31][28] ),
+ .ZN(_08326_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _20199_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[30][28] ),
+ .A2(net620),
+ .B(net567),
+ .ZN(_08327_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _20200_ (.A1(_08327_),
+ .A2(_08326_),
+ .B1(_08325_),
+ .B2(_08324_),
+ .C(net636),
+ .ZN(_08328_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _20201_ (.A1(_08323_),
+ .A2(net636),
+ .B(net547),
+ .C(_08328_),
+ .ZN(_08329_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _20202_ (.A1(_08320_),
+ .A2(_08329_),
+ .ZN(_08330_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _20203_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[4][28] ),
+ .A2(net620),
+ .ZN(_08331_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _20204_ (.A1(net602),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[5][28] ),
+ .B(net575),
+ .ZN(_08332_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _20205_ (.A1(net602),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[7][28] ),
+ .ZN(_08333_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _20206_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[6][28] ),
+ .A2(net622),
+ .B(net567),
+ .ZN(_08334_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _20207_ (.A1(_08334_),
+ .A2(_08333_),
+ .B1(_08332_),
+ .B2(_08331_),
+ .C(net636),
+ .ZN(_08335_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _20208_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[1][28] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[0][28] ),
+ .S(net602),
+ .Z(_08336_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _20209_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[3][28] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[2][28] ),
+ .S(net602),
+ .Z(_08337_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _20210_ (.I0(_08336_),
+ .I1(_08337_),
+ .S(net567),
+ .Z(_08338_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _20211_ (.A1(_08338_),
+ .A2(net638),
+ .B(net551),
+ .C(_08335_),
+ .ZN(_08339_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _20212_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[12][28] ),
+ .A2(net622),
+ .ZN(_08340_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _20213_ (.A1(net601),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[13][28] ),
+ .B(net575),
+ .ZN(_08341_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _20214_ (.A1(net601),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[15][28] ),
+ .ZN(_08342_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _20215_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[14][28] ),
+ .A2(net622),
+ .B(net567),
+ .ZN(_08343_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _20216_ (.A1(_08343_),
+ .A2(_08342_),
+ .B1(_08341_),
+ .B2(_08340_),
+ .C(net638),
+ .ZN(_08344_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _20217_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[9][28] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[8][28] ),
+ .S(net601),
+ .Z(_08345_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _20218_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[11][28] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[10][28] ),
+ .S(net601),
+ .Z(_08346_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _20219_ (.I0(_08345_),
+ .I1(_08346_),
+ .S(net567),
+ .Z(_08347_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _20220_ (.A1(_08347_),
+ .A2(net638),
+ .B(net547),
+ .C(_08344_),
+ .ZN(_08348_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _20221_ (.A1(_08339_),
+ .A2(_08348_),
+ .ZN(_08349_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _20222_ (.I0(_08349_),
+ .I1(_08330_),
+ .S(net543),
+ .Z(_00020_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _20223_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[20][29] ),
+ .A2(net616),
+ .ZN(_08350_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _20224_ (.A1(net590),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[21][29] ),
+ .B(net573),
+ .ZN(_08351_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _20225_ (.A1(net590),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[23][29] ),
+ .ZN(_08352_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _20226_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[22][29] ),
+ .A2(net616),
+ .B(net560),
+ .ZN(_08353_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _20227_ (.A1(_08353_),
+ .A2(_08352_),
+ .B1(_08351_),
+ .B2(_08350_),
+ .C(net631),
+ .ZN(_08354_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _20228_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[17][29] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[16][29] ),
+ .S(net590),
+ .Z(_08355_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _20229_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[19][29] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[18][29] ),
+ .S(net590),
+ .Z(_08356_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _20230_ (.I0(_08355_),
+ .I1(_08356_),
+ .S(net558),
+ .Z(_08357_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _20231_ (.A1(_08357_),
+ .A2(net631),
+ .B(net553),
+ .C(_08354_),
+ .ZN(_08358_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _20232_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[25][29] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[24][29] ),
+ .S(net590),
+ .Z(_08359_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _20233_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[27][29] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[26][29] ),
+ .S(net587),
+ .Z(_08360_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _20234_ (.I0(_08359_),
+ .I1(_08360_),
+ .S(net558),
+ .Z(_08361_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _20235_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[28][29] ),
+ .A2(net615),
+ .ZN(_08362_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _20236_ (.A1(net591),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[29][29] ),
+ .B(net573),
+ .ZN(_08363_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _20237_ (.A1(net590),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[31][29] ),
+ .ZN(_08364_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _20238_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[30][29] ),
+ .A2(net615),
+ .B(net560),
+ .ZN(_08365_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _20239_ (.A1(_08365_),
+ .A2(_08364_),
+ .B1(_08363_),
+ .B2(_08362_),
+ .C(net631),
+ .ZN(_08366_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _20240_ (.A1(_08361_),
+ .A2(net631),
+ .B(net546),
+ .C(_08366_),
+ .ZN(_08367_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _20241_ (.A1(_08358_),
+ .A2(_08367_),
+ .ZN(_08368_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _20242_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[4][29] ),
+ .A2(net616),
+ .ZN(_08369_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _20243_ (.A1(net593),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[5][29] ),
+ .B(net573),
+ .ZN(_08370_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _20244_ (.A1(net590),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[7][29] ),
+ .ZN(_08371_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _20245_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[6][29] ),
+ .A2(net616),
+ .B(net560),
+ .ZN(_08372_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _20246_ (.A1(_08372_),
+ .A2(_08371_),
+ .B1(_08370_),
+ .B2(_08369_),
+ .C(net631),
+ .ZN(_08373_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _20247_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[1][29] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[0][29] ),
+ .S(net590),
+ .Z(_08374_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _20248_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[3][29] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[2][29] ),
+ .S(net590),
+ .Z(_08375_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _20249_ (.I0(_08374_),
+ .I1(_08375_),
+ .S(net560),
+ .Z(_08376_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _20250_ (.A1(_08376_),
+ .A2(net631),
+ .B(net553),
+ .C(_08373_),
+ .ZN(_08377_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _20251_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[12][29] ),
+ .A2(net616),
+ .ZN(_08378_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _20252_ (.A1(net590),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[13][29] ),
+ .B(net573),
+ .ZN(_08379_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _20253_ (.A1(net590),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[15][29] ),
+ .ZN(_08380_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _20254_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[14][29] ),
+ .A2(net616),
+ .B(net560),
+ .ZN(_08381_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _20255_ (.A1(_08381_),
+ .A2(_08380_),
+ .B1(_08379_),
+ .B2(_08378_),
+ .C(net631),
+ .ZN(_08382_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _20256_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[9][29] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[8][29] ),
+ .S(net590),
+ .Z(_08383_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _20257_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[11][29] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[10][29] ),
+ .S(net590),
+ .Z(_08384_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _20258_ (.I0(_08383_),
+ .I1(_08384_),
+ .S(net560),
+ .Z(_08385_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _20259_ (.A1(_08385_),
+ .A2(net631),
+ .B(net546),
+ .C(_08382_),
+ .ZN(_08386_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _20260_ (.A1(_08377_),
+ .A2(_08386_),
+ .ZN(_08387_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _20261_ (.I0(_08387_),
+ .I1(_08368_),
+ .S(net541),
+ .Z(_00021_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _20262_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[20][30] ),
+ .A2(net616),
+ .ZN(_08388_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _20263_ (.A1(net590),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[21][30] ),
+ .B(net572),
+ .ZN(_08389_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _20264_ (.A1(net590),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[23][30] ),
+ .ZN(_08390_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _20265_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[22][30] ),
+ .A2(net616),
+ .B(net560),
+ .ZN(_08391_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _20266_ (.A1(_08391_),
+ .A2(_08390_),
+ .B1(_08389_),
+ .B2(_08388_),
+ .C(net631),
+ .ZN(_08392_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _20267_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[17][30] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[16][30] ),
+ .S(net585),
+ .Z(_08393_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _20268_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[19][30] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[18][30] ),
+ .S(net585),
+ .Z(_08394_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _20269_ (.I0(_08393_),
+ .I1(_08394_),
+ .S(net557),
+ .Z(_08395_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _20270_ (.A1(_08395_),
+ .A2(net631),
+ .B(net553),
+ .C(_08392_),
+ .ZN(_08396_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _20271_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[25][30] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[24][30] ),
+ .S(net590),
+ .Z(_08397_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _20272_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[27][30] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[26][30] ),
+ .S(net590),
+ .Z(_08398_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _20273_ (.I0(_08397_),
+ .I1(_08398_),
+ .S(net560),
+ .Z(_08399_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _20274_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[28][30] ),
+ .A2(net616),
+ .ZN(_08400_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _20275_ (.A1(net590),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[29][30] ),
+ .B(net572),
+ .ZN(_08401_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _20276_ (.A1(net590),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[31][30] ),
+ .ZN(_08402_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _20277_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[30][30] ),
+ .A2(net616),
+ .B(net560),
+ .ZN(_08403_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _20278_ (.A1(_08403_),
+ .A2(_08402_),
+ .B1(_08401_),
+ .B2(_08400_),
+ .C(net631),
+ .ZN(_08404_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _20279_ (.A1(_08399_),
+ .A2(net631),
+ .B(net545),
+ .C(_08404_),
+ .ZN(_08405_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _20280_ (.A1(_08396_),
+ .A2(_08405_),
+ .ZN(_08406_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _20281_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[1][30] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[0][30] ),
+ .S(net596),
+ .Z(_08407_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _20282_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[3][30] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[2][30] ),
+ .S(net596),
+ .Z(_08408_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _20283_ (.I0(_08407_),
+ .I1(_08408_),
+ .S(net557),
+ .Z(_08409_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _20284_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[4][30] ),
+ .A2(net612),
+ .ZN(_08410_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _20285_ (.A1(net585),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[5][30] ),
+ .B(net574),
+ .ZN(_08411_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _20286_ (.A1(net596),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[7][30] ),
+ .ZN(_08412_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _20287_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[6][30] ),
+ .A2(net617),
+ .B(net562),
+ .ZN(_08413_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _20288_ (.A1(_08413_),
+ .A2(_08412_),
+ .B1(_08411_),
+ .B2(_08410_),
+ .C(net633),
+ .ZN(_08414_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _20289_ (.A1(_08409_),
+ .A2(net628),
+ .B(net550),
+ .C(_08414_),
+ .ZN(_08415_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _20290_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[12][30] ),
+ .A2(net612),
+ .ZN(_08416_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _20291_ (.A1(net585),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[13][30] ),
+ .B(net571),
+ .ZN(_08417_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _20292_ (.A1(net585),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[15][30] ),
+ .ZN(_08418_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _20293_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[14][30] ),
+ .A2(net612),
+ .B(net557),
+ .ZN(_08419_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _20294_ (.A1(_08419_),
+ .A2(_08418_),
+ .B1(_08417_),
+ .B2(_08416_),
+ .C(net628),
+ .ZN(_08420_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _20295_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[9][30] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[8][30] ),
+ .S(net584),
+ .Z(_08421_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _20296_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[11][30] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[10][30] ),
+ .S(net585),
+ .Z(_08422_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _20297_ (.I0(_08421_),
+ .I1(_08422_),
+ .S(net557),
+ .Z(_08423_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _20298_ (.A1(_08423_),
+ .A2(net628),
+ .B(net545),
+ .C(_08420_),
+ .ZN(_08424_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _20299_ (.A1(_08415_),
+ .A2(_08424_),
+ .ZN(_08425_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _20300_ (.I0(_08425_),
+ .I1(_08406_),
+ .S(net542),
+ .Z(_00023_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _20301_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[20][31] ),
+ .A2(net618),
+ .ZN(_08426_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _20302_ (.A1(net597),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[21][31] ),
+ .B(net574),
+ .ZN(_08427_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _20303_ (.A1(net596),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[23][31] ),
+ .ZN(_08428_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _20304_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[22][31] ),
+ .A2(net618),
+ .B(net563),
+ .ZN(_08429_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _20305_ (.A1(_08429_),
+ .A2(_08428_),
+ .B1(_08427_),
+ .B2(_08426_),
+ .C(net634),
+ .ZN(_08430_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _20306_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[17][31] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[16][31] ),
+ .S(net597),
+ .Z(_08431_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _20307_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[19][31] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[18][31] ),
+ .S(net597),
+ .Z(_08432_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _20308_ (.I0(_08431_),
+ .I1(_08432_),
+ .S(net563),
+ .Z(_08433_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _20309_ (.A1(_08433_),
+ .A2(net634),
+ .B(net550),
+ .C(_08430_),
+ .ZN(_08434_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _20310_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[25][31] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[24][31] ),
+ .S(net596),
+ .Z(_08435_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _20311_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[27][31] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[26][31] ),
+ .S(net599),
+ .Z(_08436_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _20312_ (.I0(_08435_),
+ .I1(_08436_),
+ .S(net565),
+ .Z(_08437_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _20313_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[28][31] ),
+ .A2(net620),
+ .ZN(_08438_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _20314_ (.A1(net599),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[29][31] ),
+ .B(net575),
+ .ZN(_08439_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _20315_ (.A1(net599),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[31][31] ),
+ .ZN(_08440_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _20316_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[30][31] ),
+ .A2(net620),
+ .B(net565),
+ .ZN(_08441_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _20317_ (.A1(_08441_),
+ .A2(_08440_),
+ .B1(_08439_),
+ .B2(_08438_),
+ .C(net636),
+ .ZN(_08442_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _20318_ (.A1(_08437_),
+ .A2(net636),
+ .B(net547),
+ .C(_08442_),
+ .ZN(_08443_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _20319_ (.A1(_08434_),
+ .A2(_08443_),
+ .ZN(_08444_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _20320_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[4][31] ),
+ .A2(net618),
+ .ZN(_08445_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _20321_ (.A1(net596),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[5][31] ),
+ .B(net574),
+ .ZN(_08446_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _20322_ (.A1(net596),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[7][31] ),
+ .ZN(_08447_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _20323_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[6][31] ),
+ .A2(net618),
+ .B(net563),
+ .ZN(_08448_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _20324_ (.A1(_08448_),
+ .A2(_08447_),
+ .B1(_08446_),
+ .B2(_08445_),
+ .C(net634),
+ .ZN(_08449_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _20325_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[1][31] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[0][31] ),
+ .S(net596),
+ .Z(_08450_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _20326_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[3][31] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[2][31] ),
+ .S(net596),
+ .Z(_08451_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _20327_ (.I0(_08450_),
+ .I1(_08451_),
+ .S(net563),
+ .Z(_08452_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _20328_ (.A1(_08452_),
+ .A2(net634),
+ .B(net550),
+ .C(_08449_),
+ .ZN(_08453_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _20329_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[12][31] ),
+ .A2(net618),
+ .ZN(_08454_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _20330_ (.A1(net596),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[13][31] ),
+ .B(net574),
+ .ZN(_08455_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _20331_ (.A1(net596),
+ .A2(\soc.core.VexRiscv.RegFilePlugin_regFile[15][31] ),
+ .ZN(_08456_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _20332_ (.A1(\soc.core.VexRiscv.RegFilePlugin_regFile[14][31] ),
+ .A2(net618),
+ .B(net563),
+ .ZN(_08457_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _20333_ (.A1(_08457_),
+ .A2(_08456_),
+ .B1(_08455_),
+ .B2(_08454_),
+ .C(net634),
+ .ZN(_08458_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _20334_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[9][31] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[8][31] ),
+ .S(net596),
+ .Z(_08459_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _20335_ (.I0(\soc.core.VexRiscv.RegFilePlugin_regFile[11][31] ),
+ .I1(\soc.core.VexRiscv.RegFilePlugin_regFile[10][31] ),
+ .S(net596),
+ .Z(_08460_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _20336_ (.I0(_08459_),
+ .I1(_08460_),
+ .S(net563),
+ .Z(_08461_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _20337_ (.A1(_08461_),
+ .A2(net634),
+ .B(net547),
+ .C(_08458_),
+ .ZN(_08462_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _20338_ (.A1(_08453_),
+ .A2(_08462_),
+ .ZN(_08463_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _20339_ (.I0(_08463_),
+ .I1(_08444_),
+ .S(net543),
+ .Z(_00024_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__and2_4 _20340_ (.A1(\soc.core.mgmtsoc_master_tx_fifo_source_payload_width[1] ),
+ .A2(net1831),
+ .Z(_08464_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _20341_ (.A1(\soc.core.mgmtsoc_master_tx_fifo_source_payload_width[1] ),
+ .A2(net1831),
+ .ZN(_08465_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_4 _20342_ (.A1(_05025_),
+ .A2(\soc.core.litespi_state[3] ),
+ .ZN(_08466_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_4 _20343_ (.A1(_05022_),
+ .A2(\soc.core.litespi_state[0] ),
+ .ZN(_08467_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_4 _20344_ (.A1(_08467_),
+ .A2(net1832),
+ .ZN(_08468_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi21_4 _20345_ (.A1(\soc.core.mgmtsoc_master_tx_fifo_source_payload_width[0] ),
+ .A2(net1831),
+ .B(_08468_),
+ .ZN(_08469_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _20346_ (.I0(_08466_),
+ .I1(\soc.core.mgmtsoc_master_tx_fifo_source_payload_width[0] ),
+ .S(net1831),
+ .Z(_08470_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_4 _20347_ (.A1(\soc.core.mgmtsoc_master_tx_fifo_source_payload_width[2] ),
+ .A2(net1832),
+ .ZN(_08471_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _20348_ (.A1(_08471_),
+ .A2(\soc.core.mgmtsoc_master_tx_fifo_source_payload_width[3] ),
+ .ZN(_08472_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__and3_4 _20349_ (.A1(_08469_),
+ .A2(_08472_),
+ .A3(_08465_),
+ .Z(_08473_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_4 _20350_ (.A1(\soc.core.mgmtsoc_master_tx_fifo_source_payload_width[3] ),
+ .A2(net1832),
+ .ZN(_08474_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _20351_ (.A1(_08464_),
+ .A2(_08474_),
+ .ZN(_08475_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi211_4 _20352_ (.A1(\soc.core.mgmtsoc_master_tx_fifo_source_payload_width[0] ),
+ .A2(net1831),
+ .B(_08475_),
+ .C(\soc.core.mgmtsoc_master_tx_fifo_source_payload_width[2] ),
+ .ZN(_08476_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _20353_ (.A1(_08474_),
+ .A2(\soc.core.mgmtsoc_master_tx_fifo_source_payload_width[2] ),
+ .ZN(_08477_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__and3_4 _20354_ (.A1(_08469_),
+ .A2(_08477_),
+ .A3(_08465_),
+ .Z(_08478_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _20355_ (.A1(net1418),
+ .A2(_08478_),
+ .ZN(_08479_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _20356_ (.I(_08479_),
+ .ZN(_08480_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_4 _20357_ (.A1(_08480_),
+ .A2(_08473_),
+ .ZN(_08481_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai31_4 _20358_ (.A1(\soc.core.mgmtsoc_master_tx_fifo_source_payload_width[3] ),
+ .A2(\soc.core.mgmtsoc_master_tx_fifo_source_payload_width[2] ),
+ .A3(\soc.core.mgmtsoc_master_tx_fifo_source_payload_width[1] ),
+ .B(net1832),
+ .ZN(_08482_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__and2_4 _20359_ (.A1(_08470_),
+ .A2(_08482_),
+ .Z(_08483_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_4 _20360_ (.A1(_08470_),
+ .A2(_08482_),
+ .ZN(_08484_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _20361_ (.A1(_05026_),
+ .A2(\soc.core.litespiphy_state[0] ),
+ .ZN(_08485_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_2 _20362_ (.I(_08485_),
+ .ZN(_08486_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai22_4 _20363_ (.A1(\soc.core.mgmtsoc_litespisdrphycore_storage[5] ),
+ .A2(_05298_),
+ .B1(_05299_),
+ .B2(\soc.core.mgmtsoc_litespisdrphycore_storage[4] ),
+ .ZN(_08487_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _20364_ (.A1(_05298_),
+ .A2(\soc.core.mgmtsoc_litespisdrphycore_storage[5] ),
+ .ZN(_08488_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi22_4 _20365_ (.A1(\soc.core.mgmtsoc_litespisdrphycore_storage[3] ),
+ .A2(_05294_),
+ .B1(_05299_),
+ .B2(\soc.core.mgmtsoc_litespisdrphycore_storage[4] ),
+ .ZN(_08489_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _20366_ (.A1(_08489_),
+ .A2(_08488_),
+ .ZN(_08490_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _20367_ (.A1(_08487_),
+ .A2(_08490_),
+ .ZN(_08491_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai22_4 _20368_ (.A1(_05166_),
+ .A2(\soc.core.mgmtsoc_litespisdrphycore_cnt[1] ),
+ .B1(_05167_),
+ .B2(\soc.core.mgmtsoc_litespisdrphycore_cnt[0] ),
+ .ZN(_08492_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi221_4 _20369_ (.A1(_05164_),
+ .A2(\soc.core.mgmtsoc_litespisdrphycore_cnt[3] ),
+ .B1(_05295_),
+ .B2(\soc.core.mgmtsoc_litespisdrphycore_storage[2] ),
+ .C(_08492_),
+ .ZN(_08493_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai222_4 _20370_ (.A1(_05162_),
+ .A2(\soc.core.mgmtsoc_litespisdrphycore_cnt[7] ),
+ .B1(_05297_),
+ .B2(\soc.core.mgmtsoc_litespisdrphycore_storage[6] ),
+ .C1(\soc.core.mgmtsoc_litespisdrphycore_storage[1] ),
+ .C2(_05293_),
+ .ZN(_08494_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi22_4 _20371_ (.A1(_05162_),
+ .A2(\soc.core.mgmtsoc_litespisdrphycore_cnt[7] ),
+ .B1(_05167_),
+ .B2(\soc.core.mgmtsoc_litespisdrphycore_cnt[0] ),
+ .ZN(_08495_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _20372_ (.A1(\soc.core.mgmtsoc_litespisdrphycore_storage[2] ),
+ .A2(_05295_),
+ .B1(\soc.core.mgmtsoc_litespisdrphycore_cnt[6] ),
+ .B2(_05163_),
+ .C(_08495_),
+ .ZN(_08496_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _20373_ (.A1(_08494_),
+ .A2(_08496_),
+ .ZN(_08497_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__and3_4 _20374_ (.A1(_08491_),
+ .A2(_08493_),
+ .A3(_08497_),
+ .Z(_08498_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__and3_4 _20375_ (.A1(\soc.core.mgmtsoc_litespisdrphycore_clk ),
+ .A2(_08486_),
+ .A3(_08498_),
+ .Z(_08499_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand3_4 _20376_ (.A1(\soc.core.mgmtsoc_litespisdrphycore_clk ),
+ .A2(_08486_),
+ .A3(_08498_),
+ .ZN(_08500_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi21_4 _20377_ (.A1(_08481_),
+ .A2(_08484_),
+ .B(_08500_),
+ .ZN(_08501_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _20378_ (.I0(_08466_),
+ .I1(\soc.core.mgmtsoc_master_tx_fifo_source_valid ),
+ .S(net1831),
+ .Z(_08502_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _20379_ (.A1(_05586_),
+ .A2(_08502_),
+ .ZN(_08503_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_2 _20380_ (.I(_08503_),
+ .ZN(_08504_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_4 _20381_ (.A1(\soc.core.litespiphy_state[1] ),
+ .A2(\soc.core.litespiphy_state[0] ),
+ .ZN(_08505_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_4 _20382_ (.A1(_05026_),
+ .A2(_05027_),
+ .ZN(_08506_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_4 _20383_ (.A1(_08504_),
+ .A2(_08505_),
+ .ZN(_08507_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_4 _20384_ (.A1(_08467_),
+ .A2(\soc.core.litespi_state[1] ),
+ .ZN(_08508_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__and3_4 _20385_ (.A1(\soc.core.litespi_state[2] ),
+ .A2(_08466_),
+ .A3(_05024_),
+ .Z(_08509_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_4 _20386_ (.A1(net1831),
+ .A2(_08509_),
+ .ZN(_08510_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__or2_4 _20387_ (.A1(net1832),
+ .A2(_08509_),
+ .Z(_08511_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _20388_ (.I0(\soc.core.mgmtsoc_litespimmap_storage[0] ),
+ .I1(\soc.core.mgmtsoc_master_tx_fifo_source_payload_len[0] ),
+ .S(net1832),
+ .Z(_08512_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__and2_4 _20389_ (.A1(_08511_),
+ .A2(_08512_),
+ .Z(_08513_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_4 _20390_ (.A1(_08511_),
+ .A2(_08512_),
+ .ZN(_08514_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _20391_ (.I0(\soc.core.mgmtsoc_litespimmap_storage[1] ),
+ .I1(\soc.core.mgmtsoc_master_tx_fifo_source_payload_len[1] ),
+ .S(net1831),
+ .Z(_08515_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_4 _20392_ (.A1(_08511_),
+ .A2(_08515_),
+ .ZN(_08516_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _20393_ (.A1(net1120),
+ .A2(_08516_),
+ .ZN(_08517_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _20394_ (.I0(\soc.core.mgmtsoc_litespimmap_storage[2] ),
+ .I1(\soc.core.mgmtsoc_master_tx_fifo_source_payload_len[2] ),
+ .S(net1831),
+ .Z(_08518_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _20395_ (.A1(_08511_),
+ .A2(_08518_),
+ .ZN(_08519_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_3 _20396_ (.I(_08519_),
+ .ZN(_08520_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__or2_4 _20397_ (.A1(_08517_),
+ .A2(_08520_),
+ .Z(_08521_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _20398_ (.I(_08521_),
+ .ZN(_08522_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_4 _20399_ (.A1(_08467_),
+ .A2(\soc.core.litespi_state[2] ),
+ .ZN(_08523_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_4 _20400_ (.A1(_08508_),
+ .A2(_08523_),
+ .ZN(_08524_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi21_4 _20401_ (.A1(\soc.core.litespi_state[2] ),
+ .A2(\soc.core.litespi_state[1] ),
+ .B(_08467_),
+ .ZN(_08525_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _20402_ (.A1(net1832),
+ .A2(_08524_),
+ .ZN(_08526_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _20403_ (.A1(_05155_),
+ .A2(\soc.core.litespi_state[2] ),
+ .ZN(_08527_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _20404_ (.A1(_08526_),
+ .A2(_08527_),
+ .ZN(_08528_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _20405_ (.A1(\soc.core.mgmtsoc_master_tx_fifo_source_payload_len[3] ),
+ .A2(net1831),
+ .ZN(_08529_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_4 _20406_ (.A1(_08528_),
+ .A2(_08529_),
+ .ZN(_08530_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _20407_ (.A1(_08521_),
+ .A2(_08530_),
+ .ZN(_08531_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__and3_4 _20408_ (.A1(_08466_),
+ .A2(_05023_),
+ .A3(\soc.core.litespi_state[1] ),
+ .Z(_08532_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_4 _20409_ (.A1(\soc.core.litespi_state[1] ),
+ .A2(_08523_),
+ .ZN(_08533_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_4 _20410_ (.A1(_08533_),
+ .A2(net1833),
+ .ZN(_08534_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _20411_ (.A1(\soc.core.mgmtsoc_litespimmap_storage[4] ),
+ .A2(_08509_),
+ .ZN(_08535_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _20412_ (.A1(_08533_),
+ .A2(_08535_),
+ .ZN(_08536_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _20413_ (.I0(_08536_),
+ .I1(\soc.core.mgmtsoc_master_tx_fifo_source_payload_len[4] ),
+ .S(net1832),
+ .Z(_08537_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_2 _20414_ (.I(_08537_),
+ .ZN(_08538_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _20415_ (.A1(_08531_),
+ .A2(_08538_),
+ .ZN(_08539_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _20416_ (.A1(\soc.core.mgmtsoc_master_tx_fifo_source_payload_len[5] ),
+ .A2(net1831),
+ .ZN(_08540_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_4 _20417_ (.A1(\soc.core.litespi_state[1] ),
+ .A2(\soc.core.litespi_state[0] ),
+ .ZN(_08541_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _20418_ (.A1(_05023_),
+ .A2(\soc.core.litespi_state[3] ),
+ .ZN(_08542_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_4 _20419_ (.A1(_08541_),
+ .A2(\soc.core.litespi_state[3] ),
+ .ZN(_08543_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _20420_ (.A1(\soc.core.mgmtsoc_litespimmap_storage[5] ),
+ .A2(_08543_),
+ .B(_08468_),
+ .C(\soc.core.litespi_state[2] ),
+ .ZN(_08544_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_4 _20421_ (.A1(_08540_),
+ .A2(_08544_),
+ .ZN(_08545_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi21_4 _20422_ (.A1(_08539_),
+ .A2(_08545_),
+ .B(net878),
+ .ZN(_08546_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _20423_ (.A1(_08539_),
+ .A2(_08545_),
+ .B(_08546_),
+ .ZN(_08547_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_4 _20424_ (.I(net780),
+ .ZN(_08548_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__xor2_4 _20425_ (.A1(_08531_),
+ .A2(_08538_),
+ .Z(_08549_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__xor2_4 _20426_ (.A1(_08531_),
+ .A2(_08537_),
+ .Z(_08550_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_4 _20427_ (.A1(net781),
+ .A2(_08549_),
+ .ZN(_08551_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _20428_ (.I0(_08508_),
+ .I1(\soc.core.mgmtsoc_master_tx_fifo_source_payload_data[0] ),
+ .S(net1831),
+ .Z(_08552_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _20429_ (.A1(_08522_),
+ .A2(_08552_),
+ .ZN(_08553_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _20430_ (.A1(_08530_),
+ .A2(_08553_),
+ .ZN(_08554_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi22_4 _20431_ (.A1(_08551_),
+ .A2(_08554_),
+ .B1(\soc.core.mgmtsoc_litespisdrphycore_sr_out[0] ),
+ .B2(net878),
+ .ZN(_08555_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _20432_ (.A1(net848),
+ .A2(_08555_),
+ .ZN(_00065_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__xor2_4 _20433_ (.A1(_08521_),
+ .A2(_08530_),
+ .Z(_08556_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__xor2_4 _20434_ (.A1(_08522_),
+ .A2(_08530_),
+ .Z(_08557_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__xor2_4 _20435_ (.A1(net1120),
+ .A2(_08516_),
+ .Z(_08558_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__xor2_4 _20436_ (.A1(_08513_),
+ .A2(_08516_),
+ .Z(_08559_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _20437_ (.A1(_05913_),
+ .A2(_08467_),
+ .ZN(_08560_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _20438_ (.I0(_08560_),
+ .I1(\soc.core.mgmtsoc_master_tx_fifo_source_payload_data[1] ),
+ .S(net1831),
+ .Z(_08561_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _20439_ (.I0(_08552_),
+ .I1(_08561_),
+ .S(net1120),
+ .Z(_08562_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _20440_ (.A1(_08559_),
+ .A2(_08562_),
+ .ZN(_08563_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__xor2_4 _20441_ (.A1(_08517_),
+ .A2(_08520_),
+ .Z(_08564_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__xor2_4 _20442_ (.A1(_08517_),
+ .A2(_08519_),
+ .Z(_08565_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _20443_ (.A1(_08563_),
+ .A2(_08564_),
+ .ZN(_08566_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _20444_ (.A1(_08557_),
+ .A2(_08566_),
+ .ZN(_08567_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_1 _20445_ (.I(_08567_),
+ .ZN(_08568_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi22_4 _20446_ (.A1(_08551_),
+ .A2(_08568_),
+ .B1(\soc.core.mgmtsoc_litespisdrphycore_sr_out[1] ),
+ .B2(net878),
+ .ZN(_08569_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai32_4 _20447_ (.A1(_05364_),
+ .A2(_08484_),
+ .A3(_08500_),
+ .B1(net848),
+ .B2(_08569_),
+ .ZN(_00076_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _20448_ (.A1(net1159),
+ .A2(_08532_),
+ .ZN(_08570_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi22_4 _20449_ (.A1(_08510_),
+ .A2(_08570_),
+ .B1(_05154_),
+ .B2(net1831),
+ .ZN(_08571_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _20450_ (.I0(_08561_),
+ .I1(_08571_),
+ .S(net1120),
+ .Z(_08572_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_1 _20451_ (.I(_08572_),
+ .ZN(_08573_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _20452_ (.A1(net977),
+ .A2(_08552_),
+ .ZN(_08574_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai22_4 _20453_ (.A1(_08574_),
+ .A2(_08513_),
+ .B1(net977),
+ .B2(_08573_),
+ .ZN(_08575_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _20454_ (.A1(net938),
+ .A2(_08575_),
+ .ZN(_08576_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _20455_ (.A1(_08576_),
+ .A2(net877),
+ .ZN(_08577_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi221_4 _20456_ (.A1(_08551_),
+ .A2(_08577_),
+ .B1(\soc.core.mgmtsoc_litespisdrphycore_sr_out[2] ),
+ .B2(net878),
+ .C(net848),
+ .ZN(_08578_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi22_4 _20457_ (.A1(\soc.core.mgmtsoc_litespisdrphycore_sr_out[0] ),
+ .A2(net1417),
+ .B1(net1300),
+ .B2(\soc.core.mgmtsoc_litespisdrphycore_sr_out[1] ),
+ .ZN(_08579_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi21_4 _20458_ (.A1(net848),
+ .A2(_08579_),
+ .B(_08578_),
+ .ZN(_00087_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _20459_ (.A1(net1160),
+ .A2(_08532_),
+ .ZN(_08580_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _20460_ (.A1(_05237_),
+ .A2(\soc.core.mgmtsoc_master_tx_fifo_source_payload_data[3] ),
+ .ZN(_08581_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi21_4 _20461_ (.A1(_08580_),
+ .A2(_08510_),
+ .B(_08581_),
+ .ZN(_08582_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _20462_ (.I0(_08571_),
+ .I1(_08582_),
+ .S(net1120),
+ .Z(_08583_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _20463_ (.I(_08583_),
+ .ZN(_08584_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _20464_ (.I0(_08583_),
+ .I1(_08562_),
+ .S(net977),
+ .Z(_08585_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _20465_ (.A1(_08585_),
+ .A2(net938),
+ .ZN(_08586_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _20466_ (.I(_08586_),
+ .ZN(_08587_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_4 _20467_ (.A1(_08586_),
+ .A2(net877),
+ .ZN(_08588_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi221_4 _20468_ (.A1(net538),
+ .A2(_08588_),
+ .B1(\soc.core.mgmtsoc_litespisdrphycore_sr_out[3] ),
+ .B2(net878),
+ .C(net848),
+ .ZN(_08589_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi22_4 _20469_ (.A1(\soc.core.mgmtsoc_litespisdrphycore_sr_out[1] ),
+ .A2(net1417),
+ .B1(net1300),
+ .B2(\soc.core.mgmtsoc_litespisdrphycore_sr_out[2] ),
+ .ZN(_08590_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi21_4 _20470_ (.A1(net848),
+ .A2(_08590_),
+ .B(_08589_),
+ .ZN(_00090_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi22_4 _20471_ (.A1(_08534_),
+ .A2(\mgmt_buffers.mprj_adr_o_core[4] ),
+ .B1(net1833),
+ .B2(\soc.core.mgmtsoc_master_tx_fifo_source_payload_data[4] ),
+ .ZN(_08591_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _20472_ (.I0(_08581_),
+ .I1(_08591_),
+ .S(net1120),
+ .Z(_08592_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _20473_ (.I0(_08592_),
+ .I1(_08573_),
+ .S(net977),
+ .Z(_08593_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _20474_ (.A1(_08520_),
+ .A2(_08552_),
+ .ZN(_08594_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _20475_ (.I0(_08593_),
+ .I1(_08594_),
+ .S(_08564_),
+ .Z(_08595_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _20476_ (.I(_08595_),
+ .ZN(_08596_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _20477_ (.A1(net877),
+ .A2(_08595_),
+ .ZN(_08597_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _20478_ (.I(_08597_),
+ .ZN(_08598_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi221_4 _20479_ (.A1(_08551_),
+ .A2(_08597_),
+ .B1(\soc.core.mgmtsoc_litespisdrphycore_sr_out[4] ),
+ .B2(net878),
+ .C(net848),
+ .ZN(_08599_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi222_4 _20480_ (.A1(net2830),
+ .A2(net1122),
+ .B1(net1417),
+ .B2(\soc.core.mgmtsoc_litespisdrphycore_sr_out[2] ),
+ .C1(net1300),
+ .C2(\soc.core.mgmtsoc_litespisdrphycore_sr_out[3] ),
+ .ZN(_08600_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi21_4 _20481_ (.A1(net848),
+ .A2(net2831),
+ .B(_08599_),
+ .ZN(_00091_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _20482_ (.A1(net1526),
+ .A2(_08533_),
+ .ZN(_08601_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _20483_ (.A1(_05237_),
+ .A2(\soc.core.mgmtsoc_master_tx_fifo_source_payload_data[5] ),
+ .ZN(_08602_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai32_4 _20484_ (.A1(\soc.core.mgmtsoc_master_tx_fifo_source_payload_len[0] ),
+ .A2(\soc.core.mgmtsoc_master_tx_fifo_source_payload_data[5] ),
+ .A3(_05237_),
+ .B1(_08601_),
+ .B2(_08511_),
+ .ZN(_08603_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi21_4 _20485_ (.A1(_08513_),
+ .A2(_08591_),
+ .B(_08603_),
+ .ZN(_08604_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _20486_ (.I(_08604_),
+ .ZN(_08605_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _20487_ (.I0(_08605_),
+ .I1(_08584_),
+ .S(net977),
+ .Z(_08606_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _20488_ (.I0(_08606_),
+ .I1(_08563_),
+ .S(_08564_),
+ .Z(_08607_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_4 _20489_ (.A1(_08607_),
+ .A2(net877),
+ .ZN(_08608_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi221_4 _20490_ (.A1(net538),
+ .A2(_08608_),
+ .B1(\soc.core.mgmtsoc_litespisdrphycore_sr_out[5] ),
+ .B2(net878),
+ .C(net848),
+ .ZN(_08609_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi222_4 _20491_ (.A1(\soc.core.mgmtsoc_litespisdrphycore_sr_out[1] ),
+ .A2(net1122),
+ .B1(net1417),
+ .B2(\soc.core.mgmtsoc_litespisdrphycore_sr_out[3] ),
+ .C1(net1300),
+ .C2(\soc.core.mgmtsoc_litespisdrphycore_sr_out[4] ),
+ .ZN(_08610_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi21_4 _20492_ (.A1(net848),
+ .A2(_08610_),
+ .B(_08609_),
+ .ZN(_00092_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _20493_ (.A1(net938),
+ .A2(_08575_),
+ .ZN(_08611_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi22_4 _20494_ (.A1(net1119),
+ .A2(net1170),
+ .B1(net1833),
+ .B2(\soc.core.mgmtsoc_master_tx_fifo_source_payload_data[6] ),
+ .ZN(_08612_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _20495_ (.I0(_08602_),
+ .I1(_08612_),
+ .S(net1120),
+ .Z(_08613_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _20496_ (.I0(_08613_),
+ .I1(_08592_),
+ .S(net977),
+ .Z(_08614_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi21_4 _20497_ (.A1(net938),
+ .A2(_08614_),
+ .B(_08611_),
+ .ZN(_08615_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _20498_ (.A1(_08615_),
+ .A2(_08557_),
+ .ZN(_08616_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__and3_4 _20499_ (.A1(net538),
+ .A2(_08557_),
+ .A3(_08615_),
+ .Z(_08617_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi211_4 _20500_ (.A1(\soc.core.mgmtsoc_litespisdrphycore_sr_out[6] ),
+ .A2(net878),
+ .B(_08617_),
+ .C(net848),
+ .ZN(_08618_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi222_4 _20501_ (.A1(\soc.core.mgmtsoc_litespisdrphycore_sr_out[2] ),
+ .A2(net1122),
+ .B1(net1417),
+ .B2(\soc.core.mgmtsoc_litespisdrphycore_sr_out[4] ),
+ .C1(net1300),
+ .C2(\soc.core.mgmtsoc_litespisdrphycore_sr_out[5] ),
+ .ZN(_08619_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi21_4 _20502_ (.A1(net848),
+ .A2(_08619_),
+ .B(_08618_),
+ .ZN(_00093_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _20503_ (.A1(net1530),
+ .A2(_08533_),
+ .ZN(_08620_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai22_4 _20504_ (.A1(_08511_),
+ .A2(_08620_),
+ .B1(\soc.core.mgmtsoc_master_tx_fifo_source_payload_data[7] ),
+ .B2(_05237_),
+ .ZN(_08621_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _20505_ (.I0(_08612_),
+ .I1(_08621_),
+ .S(net1120),
+ .Z(_08622_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _20506_ (.A1(_08559_),
+ .A2(_08604_),
+ .ZN(_08623_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi21_4 _20507_ (.A1(_08559_),
+ .A2(_08622_),
+ .B(_08623_),
+ .ZN(_08624_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _20508_ (.I0(_08585_),
+ .I1(_08624_),
+ .S(net938),
+ .Z(_08625_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _20509_ (.A1(_08557_),
+ .A2(_08625_),
+ .ZN(_08626_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_1 _20510_ (.I(_08626_),
+ .ZN(_08627_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi221_4 _20511_ (.A1(net538),
+ .A2(_08627_),
+ .B1(\soc.core.mgmtsoc_litespisdrphycore_sr_out[7] ),
+ .B2(net878),
+ .C(net848),
+ .ZN(_08628_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi222_4 _20512_ (.A1(\soc.core.mgmtsoc_litespisdrphycore_sr_out[3] ),
+ .A2(net1122),
+ .B1(net1417),
+ .B2(\soc.core.mgmtsoc_litespisdrphycore_sr_out[5] ),
+ .C1(net1300),
+ .C2(\soc.core.mgmtsoc_litespisdrphycore_sr_out[6] ),
+ .ZN(_08629_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi21_4 _20513_ (.A1(net848),
+ .A2(_08629_),
+ .B(_08628_),
+ .ZN(_00094_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi22_4 _20514_ (.A1(net1118),
+ .A2(net1329),
+ .B1(net1833),
+ .B2(\soc.core.mgmtsoc_master_tx_fifo_source_payload_data[8] ),
+ .ZN(_08630_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _20515_ (.I0(_08621_),
+ .I1(_08630_),
+ .S(net1120),
+ .Z(_08631_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _20516_ (.I0(_08631_),
+ .I1(_08613_),
+ .S(net977),
+ .Z(_08632_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _20517_ (.I0(_08593_),
+ .I1(_08632_),
+ .S(net938),
+ .Z(_08633_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _20518_ (.I0(_08633_),
+ .I1(_08553_),
+ .S(_08556_),
+ .Z(_08634_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_1 _20519_ (.I(_08634_),
+ .ZN(_08635_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi221_4 _20520_ (.A1(_08635_),
+ .A2(net537),
+ .B1(net878),
+ .B2(\soc.core.mgmtsoc_litespisdrphycore_sr_out[8] ),
+ .C(net848),
+ .ZN(_08636_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _20521_ (.A1(\soc.core.mgmtsoc_litespisdrphycore_sr_out[0] ),
+ .A2(net1121),
+ .ZN(_08637_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi222_4 _20522_ (.A1(\soc.core.mgmtsoc_litespisdrphycore_sr_out[4] ),
+ .A2(net1122),
+ .B1(net1417),
+ .B2(\soc.core.mgmtsoc_litespisdrphycore_sr_out[6] ),
+ .C1(net1300),
+ .C2(\soc.core.mgmtsoc_litespisdrphycore_sr_out[7] ),
+ .ZN(_08638_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__and3_4 _20523_ (.A1(net848),
+ .A2(_08637_),
+ .A3(_08638_),
+ .Z(_08639_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _20524_ (.A1(_08636_),
+ .A2(_08639_),
+ .ZN(_00095_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _20525_ (.A1(net1441),
+ .A2(_08533_),
+ .ZN(_08640_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai22_4 _20526_ (.A1(_08511_),
+ .A2(_08640_),
+ .B1(\soc.core.mgmtsoc_master_tx_fifo_source_payload_data[9] ),
+ .B2(_05237_),
+ .ZN(_08641_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _20527_ (.I0(_08630_),
+ .I1(_08641_),
+ .S(net1120),
+ .Z(_08642_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _20528_ (.I0(_08642_),
+ .I1(_08622_),
+ .S(net977),
+ .Z(_08643_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _20529_ (.I0(_08643_),
+ .I1(_08606_),
+ .S(_08564_),
+ .Z(_08644_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _20530_ (.I(_08644_),
+ .ZN(_08645_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _20531_ (.I0(_08645_),
+ .I1(_08566_),
+ .S(net877),
+ .Z(_08646_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi221_4 _20532_ (.A1(net537),
+ .A2(_08646_),
+ .B1(\soc.core.mgmtsoc_litespisdrphycore_sr_out[9] ),
+ .B2(net878),
+ .C(net848),
+ .ZN(_08647_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _20533_ (.A1(net2898),
+ .A2(net1122),
+ .ZN(_08648_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi222_4 _20534_ (.A1(\soc.core.mgmtsoc_litespisdrphycore_sr_out[7] ),
+ .A2(net1417),
+ .B1(net1300),
+ .B2(\soc.core.mgmtsoc_litespisdrphycore_sr_out[8] ),
+ .C1(net1121),
+ .C2(\soc.core.mgmtsoc_litespisdrphycore_sr_out[1] ),
+ .ZN(_08649_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__and3_4 _20535_ (.A1(net848),
+ .A2(_08648_),
+ .A3(_08649_),
+ .Z(_08650_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _20536_ (.A1(_08647_),
+ .A2(_08650_),
+ .ZN(_00096_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _20537_ (.A1(_08576_),
+ .A2(net877),
+ .ZN(_08651_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _20538_ (.A1(net1437),
+ .A2(_08533_),
+ .ZN(_08652_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai22_4 _20539_ (.A1(_08511_),
+ .A2(_08652_),
+ .B1(\soc.core.mgmtsoc_master_tx_fifo_source_payload_data[10] ),
+ .B2(_05237_),
+ .ZN(_08653_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _20540_ (.I0(_08653_),
+ .I1(_08641_),
+ .S(_08513_),
+ .Z(_08654_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _20541_ (.I0(_08654_),
+ .I1(_08631_),
+ .S(net977),
+ .Z(_08655_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _20542_ (.I0(_08655_),
+ .I1(_08614_),
+ .S(_08564_),
+ .Z(_08656_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _20543_ (.A1(_08557_),
+ .A2(_08656_),
+ .ZN(_08657_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _20544_ (.A1(_08651_),
+ .A2(_08657_),
+ .ZN(_08658_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__and3_4 _20545_ (.A1(_08657_),
+ .A2(net538),
+ .A3(_08651_),
+ .Z(_08659_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi211_4 _20546_ (.A1(\soc.core.mgmtsoc_litespisdrphycore_sr_out[10] ),
+ .A2(net878),
+ .B(_08659_),
+ .C(net848),
+ .ZN(_08660_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _20547_ (.A1(net2953),
+ .A2(net1121),
+ .ZN(_08661_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi222_4 _20548_ (.A1(\soc.core.mgmtsoc_litespisdrphycore_sr_out[6] ),
+ .A2(net1122),
+ .B1(net1417),
+ .B2(\soc.core.mgmtsoc_litespisdrphycore_sr_out[8] ),
+ .C1(net1300),
+ .C2(\soc.core.mgmtsoc_litespisdrphycore_sr_out[9] ),
+ .ZN(_08662_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__and3_4 _20549_ (.A1(net850),
+ .A2(_08661_),
+ .A3(_08662_),
+ .Z(_08663_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _20550_ (.A1(_08660_),
+ .A2(_08663_),
+ .ZN(_00066_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _20551_ (.A1(net1144),
+ .A2(_08532_),
+ .ZN(_08664_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _20552_ (.A1(_08664_),
+ .A2(_08510_),
+ .ZN(_08665_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _20553_ (.A1(_05153_),
+ .A2(net1833),
+ .ZN(_08666_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _20554_ (.A1(_08665_),
+ .A2(_08666_),
+ .ZN(_08667_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _20555_ (.I0(_08667_),
+ .I1(_08653_),
+ .S(_08513_),
+ .Z(_08668_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _20556_ (.A1(_08559_),
+ .A2(_08668_),
+ .ZN(_08669_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _20557_ (.A1(net977),
+ .A2(_08642_),
+ .ZN(_08670_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__and2_4 _20558_ (.A1(_08669_),
+ .A2(_08670_),
+ .Z(_08671_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _20559_ (.I0(_08624_),
+ .I1(_08671_),
+ .S(net938),
+ .Z(_08672_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _20560_ (.I0(_08672_),
+ .I1(_08587_),
+ .S(net877),
+ .Z(_08673_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi221_4 _20561_ (.A1(net537),
+ .A2(_08673_),
+ .B1(\soc.core.mgmtsoc_litespisdrphycore_sr_out[11] ),
+ .B2(net878),
+ .C(net850),
+ .ZN(_08674_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _20562_ (.A1(\soc.core.mgmtsoc_litespisdrphycore_sr_out[7] ),
+ .A2(net1122),
+ .ZN(_08675_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi222_4 _20563_ (.A1(\soc.core.mgmtsoc_litespisdrphycore_sr_out[9] ),
+ .A2(net1417),
+ .B1(net1300),
+ .B2(\soc.core.mgmtsoc_litespisdrphycore_sr_out[10] ),
+ .C1(net1121),
+ .C2(\soc.core.mgmtsoc_litespisdrphycore_sr_out[3] ),
+ .ZN(_08676_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__and3_4 _20564_ (.A1(net850),
+ .A2(_08675_),
+ .A3(_08676_),
+ .Z(_08677_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _20565_ (.A1(_08674_),
+ .A2(_08677_),
+ .ZN(_00067_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _20566_ (.A1(_05731_),
+ .A2(_08533_),
+ .ZN(_08678_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _20567_ (.A1(_05237_),
+ .A2(\soc.core.mgmtsoc_master_tx_fifo_source_payload_data[12] ),
+ .ZN(_08679_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai32_4 _20568_ (.A1(\soc.core.mgmtsoc_master_tx_fifo_source_payload_len[0] ),
+ .A2(\soc.core.mgmtsoc_master_tx_fifo_source_payload_data[12] ),
+ .A3(_05237_),
+ .B1(_08678_),
+ .B2(_08511_),
+ .ZN(_08680_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _20569_ (.I(_08680_),
+ .ZN(_08681_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _20570_ (.A1(net1120),
+ .A2(_08666_),
+ .B(_08681_),
+ .ZN(_08682_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _20571_ (.I0(_08682_),
+ .I1(_08654_),
+ .S(net977),
+ .Z(_08683_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _20572_ (.I0(_08683_),
+ .I1(_08632_),
+ .S(_08564_),
+ .Z(_08684_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _20573_ (.I(_08684_),
+ .ZN(_08685_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _20574_ (.I0(_08685_),
+ .I1(_08596_),
+ .S(net877),
+ .Z(_08686_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi221_4 _20575_ (.A1(net538),
+ .A2(_08686_),
+ .B1(\soc.core.mgmtsoc_litespisdrphycore_sr_out[12] ),
+ .B2(net878),
+ .C(net850),
+ .ZN(_08687_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _20576_ (.A1(\soc.core.mgmtsoc_litespisdrphycore_sr_out[4] ),
+ .A2(net1121),
+ .ZN(_08688_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi222_4 _20577_ (.A1(\soc.core.mgmtsoc_litespisdrphycore_sr_out[8] ),
+ .A2(net1122),
+ .B1(net1417),
+ .B2(\soc.core.mgmtsoc_litespisdrphycore_sr_out[10] ),
+ .C1(net1300),
+ .C2(\soc.core.mgmtsoc_litespisdrphycore_sr_out[11] ),
+ .ZN(_08689_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__and3_4 _20578_ (.A1(net850),
+ .A2(_08688_),
+ .A3(_08689_),
+ .Z(_08690_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _20579_ (.A1(_08687_),
+ .A2(_08690_),
+ .ZN(_00068_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi22_4 _20580_ (.A1(net1119),
+ .A2(net1138),
+ .B1(net1833),
+ .B2(\soc.core.mgmtsoc_master_tx_fifo_source_payload_data[13] ),
+ .ZN(_08691_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _20581_ (.I0(_08679_),
+ .I1(_08691_),
+ .S(net1120),
+ .Z(_08692_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _20582_ (.I0(_08692_),
+ .I1(_08668_),
+ .S(net977),
+ .Z(_08693_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _20583_ (.I0(_08643_),
+ .I1(_08693_),
+ .S(net938),
+ .Z(_08694_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _20584_ (.I0(_08694_),
+ .I1(_08607_),
+ .S(net877),
+ .Z(_08695_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_1 _20585_ (.I(_08695_),
+ .ZN(_08696_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi221_4 _20586_ (.A1(net537),
+ .A2(_08696_),
+ .B1(\soc.core.mgmtsoc_litespisdrphycore_sr_out[13] ),
+ .B2(net878),
+ .C(net850),
+ .ZN(_08697_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _20587_ (.A1(\soc.core.mgmtsoc_litespisdrphycore_sr_out[5] ),
+ .A2(net1121),
+ .ZN(_08698_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi222_4 _20588_ (.A1(\soc.core.mgmtsoc_litespisdrphycore_sr_out[9] ),
+ .A2(net1122),
+ .B1(net1417),
+ .B2(\soc.core.mgmtsoc_litespisdrphycore_sr_out[11] ),
+ .C1(net1300),
+ .C2(\soc.core.mgmtsoc_litespisdrphycore_sr_out[12] ),
+ .ZN(_08699_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__and3_4 _20589_ (.A1(net850),
+ .A2(_08698_),
+ .A3(_08699_),
+ .Z(_08700_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _20590_ (.A1(_08697_),
+ .A2(_08700_),
+ .ZN(_00069_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _20591_ (.A1(_05737_),
+ .A2(_08533_),
+ .ZN(_08701_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai22_4 _20592_ (.A1(_08511_),
+ .A2(_08701_),
+ .B1(\soc.core.mgmtsoc_master_tx_fifo_source_payload_data[14] ),
+ .B2(_05237_),
+ .ZN(_08702_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _20593_ (.I0(_08702_),
+ .I1(_08691_),
+ .S(_08513_),
+ .Z(_08703_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _20594_ (.I0(_08682_),
+ .I1(_08703_),
+ .S(_08559_),
+ .Z(_08704_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _20595_ (.I0(_08704_),
+ .I1(_08655_),
+ .S(_08564_),
+ .Z(_08705_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _20596_ (.I(_08705_),
+ .ZN(_08706_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _20597_ (.I0(_08706_),
+ .I1(_08615_),
+ .S(_08556_),
+ .Z(_08707_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi221_4 _20598_ (.A1(net537),
+ .A2(_08707_),
+ .B1(\soc.core.mgmtsoc_litespisdrphycore_sr_out[14] ),
+ .B2(net878),
+ .C(net850),
+ .ZN(_08708_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _20599_ (.A1(\soc.core.mgmtsoc_litespisdrphycore_sr_out[10] ),
+ .A2(net1122),
+ .ZN(_08709_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi222_4 _20600_ (.A1(\soc.core.mgmtsoc_litespisdrphycore_sr_out[12] ),
+ .A2(net1417),
+ .B1(net1300),
+ .B2(\soc.core.mgmtsoc_litespisdrphycore_sr_out[13] ),
+ .C1(net1121),
+ .C2(\soc.core.mgmtsoc_litespisdrphycore_sr_out[6] ),
+ .ZN(_08710_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__and3_4 _20601_ (.A1(net850),
+ .A2(_08709_),
+ .A3(_08710_),
+ .Z(_08711_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _20602_ (.A1(_08708_),
+ .A2(_08711_),
+ .ZN(_00070_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _20603_ (.A1(_05740_),
+ .A2(_08533_),
+ .ZN(_08712_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai22_4 _20604_ (.A1(_08511_),
+ .A2(_08712_),
+ .B1(\soc.core.mgmtsoc_master_tx_fifo_source_payload_data[15] ),
+ .B2(_05237_),
+ .ZN(_08713_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _20605_ (.I0(_08702_),
+ .I1(_08713_),
+ .S(net1120),
+ .Z(_08714_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _20606_ (.I0(_08714_),
+ .I1(_08692_),
+ .S(net977),
+ .Z(_08715_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _20607_ (.I(_08715_),
+ .ZN(_08716_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _20608_ (.I0(_08716_),
+ .I1(_08671_),
+ .S(_08564_),
+ .Z(_08717_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_1 _20609_ (.I(_08717_),
+ .ZN(_08718_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _20610_ (.I0(_08717_),
+ .I1(_08625_),
+ .S(_08556_),
+ .Z(_08719_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi221_4 _20611_ (.A1(_08719_),
+ .A2(net537),
+ .B1(net878),
+ .B2(\soc.core.mgmtsoc_litespisdrphycore_sr_out[15] ),
+ .C(net849),
+ .ZN(_08720_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _20612_ (.A1(\soc.core.mgmtsoc_litespisdrphycore_sr_out[11] ),
+ .A2(net1122),
+ .ZN(_08721_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi222_4 _20613_ (.A1(\soc.core.mgmtsoc_litespisdrphycore_sr_out[13] ),
+ .A2(net1417),
+ .B1(net1300),
+ .B2(\soc.core.mgmtsoc_litespisdrphycore_sr_out[14] ),
+ .C1(net1121),
+ .C2(\soc.core.mgmtsoc_litespisdrphycore_sr_out[7] ),
+ .ZN(_08722_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__and3_4 _20614_ (.A1(net850),
+ .A2(_08721_),
+ .A3(_08722_),
+ .Z(_08723_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _20615_ (.A1(_08720_),
+ .A2(_08723_),
+ .ZN(_00071_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_4 _20616_ (.A1(_08549_),
+ .A2(_08557_),
+ .ZN(_08724_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _20617_ (.A1(_08554_),
+ .A2(_08537_),
+ .ZN(_08725_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi22_4 _20618_ (.A1(net1119),
+ .A2(net1333),
+ .B1(net1833),
+ .B2(\soc.core.mgmtsoc_master_tx_fifo_source_payload_data[16] ),
+ .ZN(_08726_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _20619_ (.I0(_08713_),
+ .I1(_08726_),
+ .S(net1120),
+ .Z(_08727_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _20620_ (.I0(_08727_),
+ .I1(_08703_),
+ .S(net977),
+ .Z(_08728_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _20621_ (.I0(_08728_),
+ .I1(_08683_),
+ .S(_08564_),
+ .Z(_08729_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_4 _20622_ (.A1(_08549_),
+ .A2(_08556_),
+ .ZN(_08730_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _20623_ (.I0(_08729_),
+ .I1(_08633_),
+ .S(_08556_),
+ .Z(_08731_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _20624_ (.A1(_08731_),
+ .A2(_08549_),
+ .B(_08725_),
+ .ZN(_08732_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi221_4 _20625_ (.A1(_08732_),
+ .A2(_08548_),
+ .B1(net878),
+ .B2(\soc.core.mgmtsoc_litespisdrphycore_sr_out[16] ),
+ .C(net849),
+ .ZN(_08733_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _20626_ (.A1(\soc.core.mgmtsoc_litespisdrphycore_sr_out[12] ),
+ .A2(net1122),
+ .ZN(_08734_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi222_4 _20627_ (.A1(\soc.core.mgmtsoc_litespisdrphycore_sr_out[14] ),
+ .A2(net1417),
+ .B1(net1300),
+ .B2(\soc.core.mgmtsoc_litespisdrphycore_sr_out[15] ),
+ .C1(net1121),
+ .C2(\soc.core.mgmtsoc_litespisdrphycore_sr_out[8] ),
+ .ZN(_08735_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__and3_4 _20628_ (.A1(net850),
+ .A2(_08734_),
+ .A3(_08735_),
+ .Z(_08736_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _20629_ (.A1(_08733_),
+ .A2(_08736_),
+ .ZN(_00072_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _20630_ (.A1(_08644_),
+ .A2(net877),
+ .ZN(_08737_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi22_4 _20631_ (.A1(_08534_),
+ .A2(net1335),
+ .B1(net1833),
+ .B2(\soc.core.mgmtsoc_master_tx_fifo_source_payload_data[17] ),
+ .ZN(_08738_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _20632_ (.I0(_08726_),
+ .I1(_08738_),
+ .S(net1120),
+ .Z(_08739_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _20633_ (.I0(_08739_),
+ .I1(_08714_),
+ .S(net977),
+ .Z(_08740_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _20634_ (.I0(_08740_),
+ .I1(_08693_),
+ .S(_08564_),
+ .Z(_08741_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi221_4 _20635_ (.A1(net809),
+ .A2(_08741_),
+ .B1(_08549_),
+ .B2(_08567_),
+ .C(net781),
+ .ZN(_08742_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi221_4 _20636_ (.A1(_08737_),
+ .A2(_08742_),
+ .B1(\soc.core.mgmtsoc_litespisdrphycore_sr_out[17] ),
+ .B2(net878),
+ .C(net848),
+ .ZN(_08743_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _20637_ (.A1(\soc.core.mgmtsoc_litespisdrphycore_sr_out[9] ),
+ .A2(net1121),
+ .ZN(_08744_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi222_4 _20638_ (.A1(\soc.core.mgmtsoc_litespisdrphycore_sr_out[13] ),
+ .A2(net1122),
+ .B1(net1417),
+ .B2(\soc.core.mgmtsoc_litespisdrphycore_sr_out[15] ),
+ .C1(net1300),
+ .C2(\soc.core.mgmtsoc_litespisdrphycore_sr_out[16] ),
+ .ZN(_08745_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__and3_4 _20639_ (.A1(net850),
+ .A2(_08744_),
+ .A3(_08745_),
+ .Z(_08746_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _20640_ (.A1(_08743_),
+ .A2(_08746_),
+ .ZN(_00073_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi22_4 _20641_ (.A1(_08534_),
+ .A2(net1147),
+ .B1(net1832),
+ .B2(\soc.core.mgmtsoc_master_tx_fifo_source_payload_data[18] ),
+ .ZN(_08747_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _20642_ (.I0(_08738_),
+ .I1(_08747_),
+ .S(net1120),
+ .Z(_08748_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _20643_ (.I0(_08748_),
+ .I1(_08727_),
+ .S(net977),
+ .Z(_08749_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _20644_ (.I0(_08704_),
+ .I1(_08749_),
+ .S(net938),
+ .Z(_08750_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _20645_ (.A1(_08730_),
+ .A2(_08750_),
+ .ZN(_08751_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _20646_ (.A1(_08577_),
+ .A2(_08550_),
+ .ZN(_08752_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi211_4 _20647_ (.A1(net877),
+ .A2(_08656_),
+ .B(_08752_),
+ .C(net781),
+ .ZN(_08753_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi221_4 _20648_ (.A1(_08751_),
+ .A2(_08753_),
+ .B1(\soc.core.mgmtsoc_litespisdrphycore_sr_out[18] ),
+ .B2(net879),
+ .C(net848),
+ .ZN(_08754_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _20649_ (.A1(\soc.core.mgmtsoc_litespisdrphycore_sr_out[10] ),
+ .A2(net1121),
+ .ZN(_08755_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi222_4 _20650_ (.A1(\soc.core.mgmtsoc_litespisdrphycore_sr_out[14] ),
+ .A2(net1122),
+ .B1(net1417),
+ .B2(\soc.core.mgmtsoc_litespisdrphycore_sr_out[16] ),
+ .C1(net1300),
+ .C2(\soc.core.mgmtsoc_litespisdrphycore_sr_out[17] ),
+ .ZN(_08756_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__and3_4 _20651_ (.A1(net850),
+ .A2(_08755_),
+ .A3(_08756_),
+ .Z(_08757_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _20652_ (.A1(_08754_),
+ .A2(_08757_),
+ .ZN(_00074_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai22_4 _20653_ (.A1(_08550_),
+ .A2(_08588_),
+ .B1(_08672_),
+ .B2(_08557_),
+ .ZN(_08758_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi22_4 _20654_ (.A1(_08534_),
+ .A2(net1337),
+ .B1(net1832),
+ .B2(\soc.core.mgmtsoc_master_tx_fifo_source_payload_data[19] ),
+ .ZN(_08759_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _20655_ (.I0(_08747_),
+ .I1(_08759_),
+ .S(net1120),
+ .Z(_08760_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _20656_ (.I0(_08760_),
+ .I1(_08739_),
+ .S(net977),
+ .Z(_08761_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _20657_ (.I0(_08715_),
+ .I1(_08761_),
+ .S(net938),
+ .Z(_08762_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi211_4 _20658_ (.A1(_08730_),
+ .A2(_08762_),
+ .B(_08758_),
+ .C(net780),
+ .ZN(_08763_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi211_4 _20659_ (.A1(\soc.core.mgmtsoc_litespisdrphycore_sr_out[19] ),
+ .A2(net879),
+ .B(_08763_),
+ .C(net849),
+ .ZN(_08764_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _20660_ (.A1(\soc.core.mgmtsoc_litespisdrphycore_sr_out[11] ),
+ .A2(net1121),
+ .ZN(_08765_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi222_4 _20661_ (.A1(\soc.core.mgmtsoc_litespisdrphycore_sr_out[15] ),
+ .A2(net1122),
+ .B1(net1417),
+ .B2(\soc.core.mgmtsoc_litespisdrphycore_sr_out[17] ),
+ .C1(net1300),
+ .C2(\soc.core.mgmtsoc_litespisdrphycore_sr_out[18] ),
+ .ZN(_08766_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__and3_4 _20662_ (.A1(net849),
+ .A2(_08765_),
+ .A3(_08766_),
+ .Z(_08767_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _20663_ (.A1(_08764_),
+ .A2(_08767_),
+ .ZN(_00075_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _20664_ (.A1(_08598_),
+ .A2(_08549_),
+ .ZN(_08768_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi22_4 _20665_ (.A1(net1119),
+ .A2(net1304),
+ .B1(net1833),
+ .B2(\soc.core.mgmtsoc_master_tx_fifo_source_payload_data[20] ),
+ .ZN(_08769_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _20666_ (.I0(_08759_),
+ .I1(_08769_),
+ .S(_08514_),
+ .Z(_08770_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _20667_ (.I0(_08770_),
+ .I1(_08748_),
+ .S(net977),
+ .Z(_08771_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _20668_ (.I0(_08728_),
+ .I1(_08771_),
+ .S(net938),
+ .Z(_08772_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi221_4 _20669_ (.A1(net809),
+ .A2(_08772_),
+ .B1(_08684_),
+ .B2(_08556_),
+ .C(net781),
+ .ZN(_08773_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi221_4 _20670_ (.A1(_08768_),
+ .A2(_08773_),
+ .B1(\soc.core.mgmtsoc_litespisdrphycore_sr_out[20] ),
+ .B2(net878),
+ .C(net848),
+ .ZN(_08774_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _20671_ (.A1(\soc.core.mgmtsoc_litespisdrphycore_sr_out[12] ),
+ .A2(net1121),
+ .ZN(_08775_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi222_4 _20672_ (.A1(\soc.core.mgmtsoc_litespisdrphycore_sr_out[16] ),
+ .A2(net1122),
+ .B1(net1417),
+ .B2(\soc.core.mgmtsoc_litespisdrphycore_sr_out[18] ),
+ .C1(net1300),
+ .C2(\soc.core.mgmtsoc_litespisdrphycore_sr_out[19] ),
+ .ZN(_08776_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__and3_4 _20673_ (.A1(net849),
+ .A2(_08775_),
+ .A3(_08776_),
+ .Z(_08777_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _20674_ (.A1(_08774_),
+ .A2(_08777_),
+ .ZN(_00077_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi21_4 _20675_ (.A1(_08694_),
+ .A2(net877),
+ .B(net781),
+ .ZN(_08778_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi22_4 _20676_ (.A1(net1117),
+ .A2(net1126),
+ .B1(net1833),
+ .B2(\soc.core.mgmtsoc_master_tx_fifo_source_payload_data[21] ),
+ .ZN(_08779_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _20677_ (.I0(_08769_),
+ .I1(_08779_),
+ .S(_08514_),
+ .Z(_08780_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _20678_ (.I0(_08780_),
+ .I1(_08760_),
+ .S(net977),
+ .Z(_08781_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _20679_ (.I0(_08740_),
+ .I1(_08781_),
+ .S(net938),
+ .Z(_08782_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _20680_ (.A1(_08730_),
+ .A2(_08782_),
+ .ZN(_08783_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _20681_ (.A1(_08550_),
+ .A2(_08608_),
+ .B(_08778_),
+ .C(_08783_),
+ .ZN(_08784_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi21_4 _20682_ (.A1(\soc.core.mgmtsoc_litespisdrphycore_sr_out[21] ),
+ .A2(net879),
+ .B(net850),
+ .ZN(_08785_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _20683_ (.A1(\soc.core.mgmtsoc_litespisdrphycore_sr_out[17] ),
+ .A2(net1122),
+ .ZN(_08786_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi222_4 _20684_ (.A1(\soc.core.mgmtsoc_litespisdrphycore_sr_out[19] ),
+ .A2(net1417),
+ .B1(net1300),
+ .B2(\soc.core.mgmtsoc_litespisdrphycore_sr_out[20] ),
+ .C1(net1121),
+ .C2(\soc.core.mgmtsoc_litespisdrphycore_sr_out[13] ),
+ .ZN(_08787_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__and3_4 _20685_ (.A1(net850),
+ .A2(_08786_),
+ .A3(_08787_),
+ .Z(_08788_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi21_4 _20686_ (.A1(_08784_),
+ .A2(_08785_),
+ .B(_08788_),
+ .ZN(_00078_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _20687_ (.A1(_08616_),
+ .A2(_08549_),
+ .ZN(_08789_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi22_4 _20688_ (.A1(net1117),
+ .A2(net1124),
+ .B1(net1833),
+ .B2(\soc.core.mgmtsoc_master_tx_fifo_source_payload_data[22] ),
+ .ZN(_08790_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _20689_ (.I0(_08779_),
+ .I1(_08790_),
+ .S(_08514_),
+ .Z(_08791_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _20690_ (.I0(_08791_),
+ .I1(_08770_),
+ .S(net977),
+ .Z(_08792_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _20691_ (.I0(_08749_),
+ .I1(_08792_),
+ .S(net938),
+ .Z(_08793_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi221_4 _20692_ (.A1(_08730_),
+ .A2(_08793_),
+ .B1(_08705_),
+ .B2(_08556_),
+ .C(net780),
+ .ZN(_08794_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi221_4 _20693_ (.A1(_08789_),
+ .A2(_08794_),
+ .B1(\soc.core.mgmtsoc_litespisdrphycore_sr_out[22] ),
+ .B2(net879),
+ .C(net849),
+ .ZN(_08795_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _20694_ (.A1(\soc.core.mgmtsoc_litespisdrphycore_sr_out[14] ),
+ .A2(net1121),
+ .ZN(_08796_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi222_4 _20695_ (.A1(\soc.core.mgmtsoc_litespisdrphycore_sr_out[18] ),
+ .A2(net1122),
+ .B1(net1417),
+ .B2(\soc.core.mgmtsoc_litespisdrphycore_sr_out[20] ),
+ .C1(net1300),
+ .C2(\soc.core.mgmtsoc_litespisdrphycore_sr_out[21] ),
+ .ZN(_08797_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__and3_4 _20696_ (.A1(net849),
+ .A2(_08796_),
+ .A3(_08797_),
+ .Z(_08798_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _20697_ (.A1(_08795_),
+ .A2(_08798_),
+ .ZN(_00079_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _20698_ (.A1(_08626_),
+ .A2(_08549_),
+ .ZN(_08799_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi22_4 _20699_ (.A1(net1117),
+ .A2(net1302),
+ .B1(net1833),
+ .B2(\soc.core.mgmtsoc_master_tx_fifo_source_payload_data[23] ),
+ .ZN(_08800_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _20700_ (.I0(_08790_),
+ .I1(_08800_),
+ .S(net1120),
+ .Z(_08801_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _20701_ (.I0(_08801_),
+ .I1(_08780_),
+ .S(net977),
+ .Z(_08802_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _20702_ (.I0(_08761_),
+ .I1(_08802_),
+ .S(net938),
+ .Z(_08803_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi221_4 _20703_ (.A1(_08556_),
+ .A2(_08718_),
+ .B1(_08730_),
+ .B2(_08803_),
+ .C(net780),
+ .ZN(_08804_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi221_4 _20704_ (.A1(_08799_),
+ .A2(_08804_),
+ .B1(\soc.core.mgmtsoc_litespisdrphycore_sr_out[23] ),
+ .B2(net879),
+ .C(net849),
+ .ZN(_08805_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _20705_ (.A1(\soc.core.mgmtsoc_litespisdrphycore_sr_out[15] ),
+ .A2(net1121),
+ .ZN(_08806_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi222_4 _20706_ (.A1(\soc.core.mgmtsoc_litespisdrphycore_sr_out[19] ),
+ .A2(net1122),
+ .B1(net1418),
+ .B2(\soc.core.mgmtsoc_litespisdrphycore_sr_out[21] ),
+ .C1(net1300),
+ .C2(\soc.core.mgmtsoc_litespisdrphycore_sr_out[22] ),
+ .ZN(_08807_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__and3_4 _20707_ (.A1(net850),
+ .A2(_08806_),
+ .A3(_08807_),
+ .Z(_08808_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _20708_ (.A1(_08805_),
+ .A2(_08808_),
+ .ZN(_00080_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _20709_ (.A1(_08557_),
+ .A2(_08729_),
+ .ZN(_08809_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi22_4 _20710_ (.A1(net1117),
+ .A2(net1444),
+ .B1(net1833),
+ .B2(\soc.core.mgmtsoc_master_tx_fifo_source_payload_data[24] ),
+ .ZN(_08810_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _20711_ (.I0(_08800_),
+ .I1(_08810_),
+ .S(net1120),
+ .Z(_08811_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _20712_ (.I0(_08811_),
+ .I1(_08791_),
+ .S(net977),
+ .Z(_08812_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _20713_ (.I0(_08771_),
+ .I1(_08812_),
+ .S(net938),
+ .Z(_08813_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_1 _20714_ (.I(_08813_),
+ .ZN(_08814_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi211_4 _20715_ (.A1(_08557_),
+ .A2(_08814_),
+ .B(_08809_),
+ .C(_08549_),
+ .ZN(_08815_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi21_4 _20716_ (.A1(_08549_),
+ .A2(_08634_),
+ .B(_08815_),
+ .ZN(_08816_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi221_4 _20717_ (.A1(_08548_),
+ .A2(_08816_),
+ .B1(\soc.core.mgmtsoc_litespisdrphycore_sr_out[24] ),
+ .B2(net879),
+ .C(net849),
+ .ZN(_08817_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _20718_ (.A1(\soc.core.mgmtsoc_litespisdrphycore_sr_out[20] ),
+ .A2(_08473_),
+ .ZN(_08818_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi222_4 _20719_ (.A1(\soc.core.mgmtsoc_litespisdrphycore_sr_out[22] ),
+ .A2(net1418),
+ .B1(_08483_),
+ .B2(\soc.core.mgmtsoc_litespisdrphycore_sr_out[23] ),
+ .C1(net1121),
+ .C2(\soc.core.mgmtsoc_litespisdrphycore_sr_out[16] ),
+ .ZN(_08819_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__and3_4 _20720_ (.A1(net849),
+ .A2(_08818_),
+ .A3(_08819_),
+ .Z(_08820_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _20721_ (.A1(_08817_),
+ .A2(_08820_),
+ .ZN(_00081_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__or2_4 _20722_ (.A1(_08646_),
+ .A2(_08550_),
+ .Z(_08821_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi22_4 _20723_ (.A1(net1117),
+ .A2(net1338),
+ .B1(net1833),
+ .B2(\soc.core.mgmtsoc_master_tx_fifo_source_payload_data[25] ),
+ .ZN(_08822_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _20724_ (.I0(_08810_),
+ .I1(_08822_),
+ .S(net1120),
+ .Z(_08823_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _20725_ (.I0(_08823_),
+ .I1(_08801_),
+ .S(_08558_),
+ .Z(_08824_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _20726_ (.I0(_08781_),
+ .I1(_08824_),
+ .S(net938),
+ .Z(_08825_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi221_4 _20727_ (.A1(_08724_),
+ .A2(_08741_),
+ .B1(_08825_),
+ .B2(net809),
+ .C(net781),
+ .ZN(_08826_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi221_4 _20728_ (.A1(_08821_),
+ .A2(_08826_),
+ .B1(\soc.core.mgmtsoc_litespisdrphycore_sr_out[25] ),
+ .B2(net879),
+ .C(net849),
+ .ZN(_08827_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _20729_ (.A1(\soc.core.mgmtsoc_litespisdrphycore_sr_out[17] ),
+ .A2(net1121),
+ .ZN(_08828_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi222_4 _20730_ (.A1(\soc.core.mgmtsoc_litespisdrphycore_sr_out[21] ),
+ .A2(_08473_),
+ .B1(net1418),
+ .B2(\soc.core.mgmtsoc_litespisdrphycore_sr_out[23] ),
+ .C1(_08483_),
+ .C2(\soc.core.mgmtsoc_litespisdrphycore_sr_out[24] ),
+ .ZN(_08829_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__and3_4 _20731_ (.A1(net850),
+ .A2(_08828_),
+ .A3(_08829_),
+ .Z(_08830_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _20732_ (.A1(_08827_),
+ .A2(_08830_),
+ .ZN(_00082_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _20733_ (.A1(_08658_),
+ .A2(_08549_),
+ .ZN(_08831_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi22_4 _20734_ (.A1(net1117),
+ .A2(net1149),
+ .B1(net1833),
+ .B2(\soc.core.mgmtsoc_master_tx_fifo_source_payload_data[26] ),
+ .ZN(_08832_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _20735_ (.I0(_08822_),
+ .I1(_08832_),
+ .S(_08514_),
+ .Z(_08833_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _20736_ (.I0(_08833_),
+ .I1(_08811_),
+ .S(_08558_),
+ .Z(_08834_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _20737_ (.I0(_08792_),
+ .I1(_08834_),
+ .S(net938),
+ .Z(_08835_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi221_4 _20738_ (.A1(_08730_),
+ .A2(_08835_),
+ .B1(_08724_),
+ .B2(_08750_),
+ .C(net780),
+ .ZN(_08836_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi221_4 _20739_ (.A1(_08831_),
+ .A2(_08836_),
+ .B1(\soc.core.mgmtsoc_litespisdrphycore_sr_out[26] ),
+ .B2(net878),
+ .C(net849),
+ .ZN(_08837_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _20740_ (.A1(\soc.core.mgmtsoc_litespisdrphycore_sr_out[18] ),
+ .A2(net1121),
+ .ZN(_08838_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi222_4 _20741_ (.A1(\soc.core.mgmtsoc_litespisdrphycore_sr_out[22] ),
+ .A2(_08473_),
+ .B1(net1418),
+ .B2(\soc.core.mgmtsoc_litespisdrphycore_sr_out[24] ),
+ .C1(_08483_),
+ .C2(\soc.core.mgmtsoc_litespisdrphycore_sr_out[25] ),
+ .ZN(_08839_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__and3_4 _20742_ (.A1(net849),
+ .A2(_08838_),
+ .A3(_08839_),
+ .Z(_08840_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _20743_ (.A1(_08837_),
+ .A2(_08840_),
+ .ZN(_00083_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__or2_4 _20744_ (.A1(_08673_),
+ .A2(_08550_),
+ .Z(_08841_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _20745_ (.A1(net938),
+ .A2(_08802_),
+ .ZN(_08842_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi22_4 _20746_ (.A1(net1117),
+ .A2(net1430),
+ .B1(net1833),
+ .B2(\soc.core.mgmtsoc_master_tx_fifo_source_payload_data[27] ),
+ .ZN(_08843_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _20747_ (.I0(_08832_),
+ .I1(_08843_),
+ .S(_08514_),
+ .Z(_08844_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_1 _20748_ (.I(_08844_),
+ .ZN(_08845_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _20749_ (.I0(_08844_),
+ .I1(_08823_),
+ .S(_08558_),
+ .Z(_08846_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_1 _20750_ (.I(_08846_),
+ .ZN(_08847_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi211_4 _20751_ (.A1(net938),
+ .A2(_08847_),
+ .B(_08842_),
+ .C(_08556_),
+ .ZN(_08848_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi221_4 _20752_ (.A1(_08550_),
+ .A2(_08848_),
+ .B1(_08762_),
+ .B2(_08724_),
+ .C(net780),
+ .ZN(_08849_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi221_4 _20753_ (.A1(_08841_),
+ .A2(_08849_),
+ .B1(\soc.core.mgmtsoc_litespisdrphycore_sr_out[27] ),
+ .B2(net879),
+ .C(net849),
+ .ZN(_08850_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _20754_ (.A1(\soc.core.mgmtsoc_litespisdrphycore_sr_out[23] ),
+ .A2(_08473_),
+ .ZN(_08851_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi222_4 _20755_ (.A1(\soc.core.mgmtsoc_litespisdrphycore_sr_out[25] ),
+ .A2(net1418),
+ .B1(_08483_),
+ .B2(\soc.core.mgmtsoc_litespisdrphycore_sr_out[26] ),
+ .C1(net1121),
+ .C2(\soc.core.mgmtsoc_litespisdrphycore_sr_out[19] ),
+ .ZN(_08852_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__and3_4 _20756_ (.A1(net850),
+ .A2(_08851_),
+ .A3(_08852_),
+ .Z(_08853_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _20757_ (.A1(_08850_),
+ .A2(_08853_),
+ .ZN(_00084_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _20758_ (.A1(_08686_),
+ .A2(_08550_),
+ .ZN(_08854_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _20759_ (.A1(net938),
+ .A2(_08812_),
+ .ZN(_08855_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi22_4 _20760_ (.A1(net1118),
+ .A2(net1151),
+ .B1(net1833),
+ .B2(\soc.core.mgmtsoc_master_tx_fifo_source_payload_data[28] ),
+ .ZN(_08856_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _20761_ (.I0(_08843_),
+ .I1(_08856_),
+ .S(_08514_),
+ .Z(_08857_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _20762_ (.A1(_08559_),
+ .A2(_08857_),
+ .ZN(_08858_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _20763_ (.A1(_08558_),
+ .A2(_08833_),
+ .ZN(_08859_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__and3_4 _20764_ (.A1(net938),
+ .A2(_08858_),
+ .A3(_08859_),
+ .Z(_08860_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _20765_ (.A1(_08855_),
+ .A2(_08860_),
+ .ZN(_08861_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi221_4 _20766_ (.A1(_08724_),
+ .A2(_08772_),
+ .B1(_08861_),
+ .B2(net809),
+ .C(_08854_),
+ .ZN(_08862_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi221_4 _20767_ (.A1(_08548_),
+ .A2(_08862_),
+ .B1(\soc.core.mgmtsoc_litespisdrphycore_sr_out[28] ),
+ .B2(net879),
+ .C(net849),
+ .ZN(_08863_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _20768_ (.A1(\soc.core.mgmtsoc_litespisdrphycore_sr_out[20] ),
+ .A2(_08478_),
+ .ZN(_08864_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi222_4 _20769_ (.A1(\soc.core.mgmtsoc_litespisdrphycore_sr_out[24] ),
+ .A2(_08473_),
+ .B1(net1418),
+ .B2(\soc.core.mgmtsoc_litespisdrphycore_sr_out[26] ),
+ .C1(_08483_),
+ .C2(\soc.core.mgmtsoc_litespisdrphycore_sr_out[27] ),
+ .ZN(_08865_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__and3_4 _20770_ (.A1(net849),
+ .A2(_08864_),
+ .A3(_08865_),
+ .Z(_08866_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _20771_ (.A1(_08863_),
+ .A2(_08866_),
+ .ZN(_00085_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi22_4 _20772_ (.A1(net1118),
+ .A2(net1340),
+ .B1(net1833),
+ .B2(\soc.core.mgmtsoc_master_tx_fifo_source_payload_data[29] ),
+ .ZN(_08867_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _20773_ (.I0(_08856_),
+ .I1(_08867_),
+ .S(_08514_),
+ .Z(_08868_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _20774_ (.A1(_08559_),
+ .A2(_08868_),
+ .ZN(_08869_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _20775_ (.A1(_08559_),
+ .A2(_08845_),
+ .B(_08869_),
+ .C(net938),
+ .ZN(_08870_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _20776_ (.A1(_08565_),
+ .A2(_08824_),
+ .B(net809),
+ .C(_08870_),
+ .ZN(_08871_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _20777_ (.I(_08871_),
+ .ZN(_08872_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi221_4 _20778_ (.A1(_08549_),
+ .A2(_08695_),
+ .B1(_08724_),
+ .B2(_08782_),
+ .C(_08872_),
+ .ZN(_08873_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi221_4 _20779_ (.A1(_08548_),
+ .A2(_08873_),
+ .B1(\soc.core.mgmtsoc_litespisdrphycore_sr_out[29] ),
+ .B2(net879),
+ .C(net849),
+ .ZN(_08874_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _20780_ (.A1(\soc.core.mgmtsoc_litespisdrphycore_sr_out[21] ),
+ .A2(net1121),
+ .ZN(_08875_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi222_4 _20781_ (.A1(\soc.core.mgmtsoc_litespisdrphycore_sr_out[25] ),
+ .A2(net1122),
+ .B1(net1418),
+ .B2(\soc.core.mgmtsoc_litespisdrphycore_sr_out[27] ),
+ .C1(_08483_),
+ .C2(\soc.core.mgmtsoc_litespisdrphycore_sr_out[28] ),
+ .ZN(_08876_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__and3_4 _20782_ (.A1(net849),
+ .A2(_08875_),
+ .A3(_08876_),
+ .Z(_08877_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _20783_ (.A1(_08874_),
+ .A2(_08877_),
+ .ZN(_00086_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _20784_ (.A1(\soc.core.mgmtsoc_litespisdrphycore_sr_out[26] ),
+ .A2(net1122),
+ .ZN(_08878_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi222_4 _20785_ (.A1(\soc.core.mgmtsoc_litespisdrphycore_sr_out[28] ),
+ .A2(net1418),
+ .B1(_08483_),
+ .B2(\soc.core.mgmtsoc_litespisdrphycore_sr_out[29] ),
+ .C1(net1121),
+ .C2(\soc.core.mgmtsoc_litespisdrphycore_sr_out[22] ),
+ .ZN(_08879_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__and3_4 _20786_ (.A1(net849),
+ .A2(_08878_),
+ .A3(_08879_),
+ .Z(_08880_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__or2_4 _20787_ (.A1(_08707_),
+ .A2(_08550_),
+ .Z(_08881_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _20788_ (.A1(_08558_),
+ .A2(_08857_),
+ .ZN(_08882_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi22_4 _20789_ (.A1(net1118),
+ .A2(net1153),
+ .B1(net1833),
+ .B2(\soc.core.mgmtsoc_master_tx_fifo_source_payload_data[30] ),
+ .ZN(_08883_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _20790_ (.I0(_08867_),
+ .I1(_08883_),
+ .S(net1120),
+ .Z(_08884_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _20791_ (.A1(_08559_),
+ .A2(_08884_),
+ .ZN(_08885_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__and3_4 _20792_ (.A1(_08565_),
+ .A2(_08882_),
+ .A3(_08885_),
+ .Z(_08886_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _20793_ (.A1(_08565_),
+ .A2(_08834_),
+ .ZN(_08887_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _20794_ (.A1(_08886_),
+ .A2(_08887_),
+ .ZN(_08888_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi221_4 _20795_ (.A1(_08724_),
+ .A2(_08793_),
+ .B1(_08888_),
+ .B2(net809),
+ .C(net780),
+ .ZN(_08889_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi221_4 _20796_ (.A1(_08881_),
+ .A2(_08889_),
+ .B1(\soc.core.mgmtsoc_litespisdrphycore_sr_out[30] ),
+ .B2(net879),
+ .C(net849),
+ .ZN(_08890_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _20797_ (.A1(_08880_),
+ .A2(_08890_),
+ .ZN(_00088_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _20798_ (.A1(_08550_),
+ .A2(_08719_),
+ .ZN(_08891_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi221_4 _20799_ (.A1(\soc.core.mgmtsoc_master_tx_fifo_source_payload_data[31] ),
+ .A2(net1833),
+ .B1(net1155),
+ .B2(net1118),
+ .C(_08513_),
+ .ZN(_08892_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi21_4 _20800_ (.A1(_08513_),
+ .A2(_08883_),
+ .B(_08892_),
+ .ZN(_08893_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _20801_ (.I(_08893_),
+ .ZN(_08894_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _20802_ (.I0(_08894_),
+ .I1(_08868_),
+ .S(_08558_),
+ .Z(_08895_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _20803_ (.I0(_08895_),
+ .I1(_08846_),
+ .S(_08564_),
+ .Z(_08896_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi221_4 _20804_ (.A1(_08724_),
+ .A2(_08803_),
+ .B1(_08896_),
+ .B2(net809),
+ .C(_08891_),
+ .ZN(_08897_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi221_4 _20805_ (.A1(_08548_),
+ .A2(_08897_),
+ .B1(\soc.core.mgmtsoc_litespisdrphycore_sr_out[31] ),
+ .B2(net878),
+ .C(net849),
+ .ZN(_08898_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _20806_ (.A1(\soc.core.mgmtsoc_litespisdrphycore_sr_out[27] ),
+ .A2(_08473_),
+ .ZN(_08899_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi222_4 _20807_ (.A1(\soc.core.mgmtsoc_litespisdrphycore_sr_out[29] ),
+ .A2(net1417),
+ .B1(_08483_),
+ .B2(\soc.core.mgmtsoc_litespisdrphycore_sr_out[30] ),
+ .C1(_08478_),
+ .C2(\soc.core.mgmtsoc_litespisdrphycore_sr_out[23] ),
+ .ZN(_08900_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__and3_4 _20808_ (.A1(net849),
+ .A2(_08899_),
+ .A3(_08900_),
+ .Z(_08901_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _20809_ (.A1(_08898_),
+ .A2(_08901_),
+ .ZN(_00089_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__and2_4 _20810_ (.A1(net1812),
+ .A2(\soc.core.slave_sel_r[5] ),
+ .Z(_08902_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _20811_ (.A1(\soc.core.interface4_bank_bus_dat_r[0] ),
+ .A2(\soc.core.interface5_bank_bus_dat_r[0] ),
+ .ZN(_08903_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _20812_ (.A1(\soc.core.interface6_bank_bus_dat_r[0] ),
+ .A2(\soc.core.interface7_bank_bus_dat_r[0] ),
+ .ZN(_08904_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _20813_ (.A1(_08903_),
+ .A2(_08904_),
+ .ZN(_08905_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _20814_ (.A1(\soc.core.interface2_bank_bus_dat_r[0] ),
+ .A2(\soc.core.interface3_bank_bus_dat_r[0] ),
+ .ZN(_08906_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _20815_ (.A1(\soc.core.interface1_bank_bus_dat_r[0] ),
+ .A2(\soc.core.interface0_bank_bus_dat_r[0] ),
+ .ZN(_08907_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _20816_ (.A1(_08906_),
+ .A2(_08907_),
+ .ZN(_08908_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _20817_ (.A1(_08905_),
+ .A2(_08908_),
+ .ZN(_08909_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _20818_ (.A1(\soc.core.interface16_bank_bus_dat_r[0] ),
+ .A2(\soc.core.interface17_bank_bus_dat_r[0] ),
+ .ZN(_08910_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _20819_ (.A1(\soc.core.interface18_bank_bus_dat_r[0] ),
+ .A2(\soc.core.interface19_bank_bus_dat_r[0] ),
+ .ZN(_08911_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _20820_ (.A1(\soc.core.interface8_bank_bus_dat_r[0] ),
+ .A2(\soc.core.interface9_bank_bus_dat_r[0] ),
+ .ZN(_08912_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _20821_ (.A1(\soc.core.interface10_bank_bus_dat_r[0] ),
+ .A2(\soc.core.interface11_bank_bus_dat_r[0] ),
+ .ZN(_08913_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _20822_ (.A1(\soc.core.interface14_bank_bus_dat_r[0] ),
+ .A2(\soc.core.interface15_bank_bus_dat_r[0] ),
+ .ZN(_08914_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _20823_ (.A1(\soc.core.interface12_bank_bus_dat_r[0] ),
+ .A2(\soc.core.interface13_bank_bus_dat_r[0] ),
+ .ZN(_08915_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__and3_4 _20824_ (.A1(_08912_),
+ .A2(_08913_),
+ .A3(_08915_),
+ .Z(_08916_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__and3_4 _20825_ (.A1(_08909_),
+ .A2(_08914_),
+ .A3(_08916_),
+ .Z(_08917_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand3_4 _20826_ (.A1(_08910_),
+ .A2(_08911_),
+ .A3(_08917_),
+ .ZN(_08918_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi222_4 _20827_ (.A1(\soc.core.mgmtsoc_vexriscv_debug_bus_dat_r[0] ),
+ .A2(net1822),
+ .B1(net1693),
+ .B2(net1819),
+ .C1(net1713),
+ .C2(net1814),
+ .ZN(_08919_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_2 _20828_ (.I(_08919_),
+ .ZN(_08920_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi21_4 _20829_ (.A1(net1818),
+ .A2(_05373_),
+ .B(_08920_),
+ .ZN(_08921_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__and3_4 _20830_ (.A1(_05915_),
+ .A2(_05237_),
+ .A3(\soc.core.slave_sel_r[2] ),
+ .Z(_08922_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi22_4 _20831_ (.A1(_08918_),
+ .A2(net1615),
+ .B1(\soc.core.mgmtsoc_litespisdrphycore_sr_in[24] ),
+ .B2(net1415),
+ .ZN(_08923_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _20832_ (.A1(_05906_),
+ .A2(\soc.core.count[19] ),
+ .B(_08923_),
+ .C(_08921_),
+ .ZN(\soc.core.VexRiscv.dBusWishbone_DAT_MISO[0] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _20833_ (.A1(\soc.core.interface3_bank_bus_dat_r[1] ),
+ .A2(\soc.core.interface0_bank_bus_dat_r[1] ),
+ .ZN(_08924_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _20834_ (.A1(\soc.core.interface4_bank_bus_dat_r[1] ),
+ .A2(\soc.core.interface6_bank_bus_dat_r[1] ),
+ .ZN(_08925_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _20835_ (.A1(\soc.core.interface9_bank_bus_dat_r[1] ),
+ .A2(\soc.core.interface10_bank_bus_dat_r[1] ),
+ .ZN(_08926_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand3_4 _20836_ (.A1(_08924_),
+ .A2(_08925_),
+ .A3(_08926_),
+ .ZN(_08927_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai31_4 _20837_ (.A1(_08927_),
+ .A2(\soc.core.interface19_bank_bus_dat_r[1] ),
+ .A3(\soc.core.interface11_bank_bus_dat_r[1] ),
+ .B(net1615),
+ .ZN(_08928_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi222_4 _20838_ (.A1(net1822),
+ .A2(\soc.core.mgmtsoc_vexriscv_debug_bus_dat_r[1] ),
+ .B1(net1692),
+ .B2(net1819),
+ .C1(net1705),
+ .C2(net1814),
+ .ZN(_08929_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _20839_ (.A1(_08928_),
+ .A2(_08929_),
+ .ZN(_08930_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi221_4 _20840_ (.A1(net1816),
+ .A2(_05374_),
+ .B1(net1414),
+ .B2(\soc.core.mgmtsoc_litespisdrphycore_sr_in[25] ),
+ .C(_08930_),
+ .ZN(_08931_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _20841_ (.A1(net978),
+ .A2(_08931_),
+ .ZN(\soc.core.VexRiscv.dBusWishbone_DAT_MISO[1] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _20842_ (.A1(\soc.core.interface9_bank_bus_dat_r[2] ),
+ .A2(\soc.core.interface10_bank_bus_dat_r[2] ),
+ .ZN(_08932_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _20843_ (.A1(\soc.core.interface11_bank_bus_dat_r[2] ),
+ .A2(\soc.core.interface19_bank_bus_dat_r[2] ),
+ .ZN(_08933_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _20844_ (.A1(\soc.core.interface3_bank_bus_dat_r[2] ),
+ .A2(\soc.core.interface0_bank_bus_dat_r[2] ),
+ .ZN(_08934_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand3_4 _20845_ (.A1(_08932_),
+ .A2(_08933_),
+ .A3(_08934_),
+ .ZN(_08935_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai31_4 _20846_ (.A1(_08935_),
+ .A2(\soc.core.interface6_bank_bus_dat_r[2] ),
+ .A3(\soc.core.interface4_bank_bus_dat_r[2] ),
+ .B(net1615),
+ .ZN(_08936_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi222_4 _20847_ (.A1(_05375_),
+ .A2(net1816),
+ .B1(net1822),
+ .B2(\soc.core.mgmtsoc_vexriscv_debug_bus_dat_r[2] ),
+ .C1(net1700),
+ .C2(net1814),
+ .ZN(_08937_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _20848_ (.A1(_08936_),
+ .A2(_08937_),
+ .ZN(_08938_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi221_4 _20849_ (.A1(net1819),
+ .A2(net1690),
+ .B1(net1414),
+ .B2(\soc.core.mgmtsoc_litespisdrphycore_sr_in[26] ),
+ .C(_08938_),
+ .ZN(_08939_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _20850_ (.A1(net978),
+ .A2(_08939_),
+ .ZN(\soc.core.VexRiscv.dBusWishbone_DAT_MISO[2] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _20851_ (.A1(\soc.core.interface9_bank_bus_dat_r[3] ),
+ .A2(\soc.core.interface10_bank_bus_dat_r[3] ),
+ .ZN(_08940_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _20852_ (.A1(\soc.core.interface3_bank_bus_dat_r[3] ),
+ .A2(\soc.core.interface0_bank_bus_dat_r[3] ),
+ .ZN(_08941_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand3_4 _20853_ (.A1(_08940_),
+ .A2(_08941_),
+ .A3(_05377_),
+ .ZN(_08942_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai31_4 _20854_ (.A1(_08942_),
+ .A2(\soc.core.interface6_bank_bus_dat_r[3] ),
+ .A3(\soc.core.interface4_bank_bus_dat_r[3] ),
+ .B(net1615),
+ .ZN(_08943_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi222_4 _20855_ (.A1(_05376_),
+ .A2(net1816),
+ .B1(net1822),
+ .B2(\soc.core.mgmtsoc_vexriscv_debug_bus_dat_r[3] ),
+ .C1(net1699),
+ .C2(net1814),
+ .ZN(_08944_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _20856_ (.A1(_08943_),
+ .A2(_08944_),
+ .ZN(_08945_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi221_4 _20857_ (.A1(net1819),
+ .A2(net1688),
+ .B1(net1414),
+ .B2(\soc.core.mgmtsoc_litespisdrphycore_sr_in[27] ),
+ .C(_08945_),
+ .ZN(_08946_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _20858_ (.A1(net978),
+ .A2(_08946_),
+ .ZN(\soc.core.VexRiscv.dBusWishbone_DAT_MISO[3] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _20859_ (.A1(\soc.core.interface9_bank_bus_dat_r[4] ),
+ .A2(\soc.core.interface10_bank_bus_dat_r[4] ),
+ .ZN(_08947_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _20860_ (.A1(\soc.core.interface3_bank_bus_dat_r[4] ),
+ .A2(\soc.core.interface0_bank_bus_dat_r[4] ),
+ .ZN(_08948_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand3_4 _20861_ (.A1(_08947_),
+ .A2(_08948_),
+ .A3(_05379_),
+ .ZN(_08949_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai31_4 _20862_ (.A1(_08949_),
+ .A2(\soc.core.interface6_bank_bus_dat_r[4] ),
+ .A3(\soc.core.interface4_bank_bus_dat_r[4] ),
+ .B(net1615),
+ .ZN(_08950_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi222_4 _20863_ (.A1(net1822),
+ .A2(\soc.core.mgmtsoc_vexriscv_debug_bus_dat_r[4] ),
+ .B1(net1686),
+ .B2(net1819),
+ .C1(net1698),
+ .C2(net1814),
+ .ZN(_08951_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _20864_ (.A1(_08950_),
+ .A2(_08951_),
+ .ZN(_08952_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi221_4 _20865_ (.A1(net1816),
+ .A2(_05378_),
+ .B1(net1414),
+ .B2(\soc.core.mgmtsoc_litespisdrphycore_sr_in[28] ),
+ .C(_08952_),
+ .ZN(_08953_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _20866_ (.A1(net978),
+ .A2(_08953_),
+ .ZN(\soc.core.VexRiscv.dBusWishbone_DAT_MISO[4] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _20867_ (.A1(\soc.core.interface9_bank_bus_dat_r[5] ),
+ .A2(\soc.core.interface10_bank_bus_dat_r[5] ),
+ .ZN(_08954_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _20868_ (.A1(\soc.core.interface3_bank_bus_dat_r[5] ),
+ .A2(\soc.core.interface0_bank_bus_dat_r[5] ),
+ .ZN(_08955_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand3_4 _20869_ (.A1(_08954_),
+ .A2(_08955_),
+ .A3(_05381_),
+ .ZN(_08956_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai31_4 _20870_ (.A1(_08956_),
+ .A2(\soc.core.interface6_bank_bus_dat_r[5] ),
+ .A3(\soc.core.interface4_bank_bus_dat_r[5] ),
+ .B(net1615),
+ .ZN(_08957_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi222_4 _20871_ (.A1(_05380_),
+ .A2(net1816),
+ .B1(net1822),
+ .B2(\soc.core.mgmtsoc_vexriscv_debug_bus_dat_r[5] ),
+ .C1(net1697),
+ .C2(net1814),
+ .ZN(_08958_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _20872_ (.A1(_08957_),
+ .A2(_08958_),
+ .ZN(_08959_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi221_4 _20873_ (.A1(net1819),
+ .A2(net1684),
+ .B1(net1414),
+ .B2(\soc.core.mgmtsoc_litespisdrphycore_sr_in[29] ),
+ .C(_08959_),
+ .ZN(_08960_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _20874_ (.A1(net978),
+ .A2(_08960_),
+ .ZN(\soc.core.VexRiscv.dBusWishbone_DAT_MISO[5] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _20875_ (.A1(\soc.core.interface9_bank_bus_dat_r[6] ),
+ .A2(\soc.core.interface10_bank_bus_dat_r[6] ),
+ .ZN(_08961_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _20876_ (.A1(\soc.core.interface3_bank_bus_dat_r[6] ),
+ .A2(\soc.core.interface0_bank_bus_dat_r[6] ),
+ .ZN(_08962_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand3_4 _20877_ (.A1(_08961_),
+ .A2(_08962_),
+ .A3(_05383_),
+ .ZN(_08963_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai31_4 _20878_ (.A1(_08963_),
+ .A2(\soc.core.interface6_bank_bus_dat_r[6] ),
+ .A3(\soc.core.interface4_bank_bus_dat_r[6] ),
+ .B(net1615),
+ .ZN(_08964_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi222_4 _20879_ (.A1(net1822),
+ .A2(\soc.core.mgmtsoc_vexriscv_debug_bus_dat_r[6] ),
+ .B1(net1682),
+ .B2(net1819),
+ .C1(net1696),
+ .C2(net1814),
+ .ZN(_08965_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _20880_ (.A1(_08964_),
+ .A2(_08965_),
+ .ZN(_08966_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi221_4 _20881_ (.A1(net1816),
+ .A2(_05382_),
+ .B1(net1414),
+ .B2(\soc.core.mgmtsoc_litespisdrphycore_sr_in[30] ),
+ .C(_08966_),
+ .ZN(_08967_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _20882_ (.A1(net978),
+ .A2(_08967_),
+ .ZN(\soc.core.VexRiscv.dBusWishbone_DAT_MISO[6] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _20883_ (.A1(\soc.core.interface9_bank_bus_dat_r[7] ),
+ .A2(\soc.core.interface10_bank_bus_dat_r[7] ),
+ .ZN(_08968_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _20884_ (.A1(\soc.core.interface3_bank_bus_dat_r[7] ),
+ .A2(\soc.core.interface0_bank_bus_dat_r[7] ),
+ .ZN(_08969_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand3_4 _20885_ (.A1(_08968_),
+ .A2(_08969_),
+ .A3(_05385_),
+ .ZN(_08970_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai31_4 _20886_ (.A1(_08970_),
+ .A2(\soc.core.interface6_bank_bus_dat_r[7] ),
+ .A3(\soc.core.interface4_bank_bus_dat_r[7] ),
+ .B(net1615),
+ .ZN(_08971_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi222_4 _20887_ (.A1(net1822),
+ .A2(\soc.core.mgmtsoc_vexriscv_debug_bus_dat_r[7] ),
+ .B1(net1680),
+ .B2(net1819),
+ .C1(net1695),
+ .C2(net1814),
+ .ZN(_08972_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _20888_ (.A1(_08971_),
+ .A2(_08972_),
+ .ZN(_08973_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi221_4 _20889_ (.A1(net1817),
+ .A2(_05384_),
+ .B1(net1414),
+ .B2(\soc.core.mgmtsoc_litespisdrphycore_sr_in[31] ),
+ .C(_08973_),
+ .ZN(_08974_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _20890_ (.A1(net978),
+ .A2(_08974_),
+ .ZN(\soc.core.VexRiscv.dBusWishbone_DAT_MISO[7] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _20891_ (.A1(\soc.core.interface3_bank_bus_dat_r[8] ),
+ .A2(\soc.core.interface0_bank_bus_dat_r[8] ),
+ .ZN(_08975_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _20892_ (.A1(\soc.core.interface6_bank_bus_dat_r[8] ),
+ .A2(\soc.core.interface10_bank_bus_dat_r[8] ),
+ .ZN(_08976_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _20893_ (.A1(_08975_),
+ .A2(_08976_),
+ .ZN(_08977_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _20894_ (.A1(_08977_),
+ .A2(\soc.core.interface9_bank_bus_dat_r[8] ),
+ .B(\soc.core.slave_sel_r[5] ),
+ .C(net1813),
+ .ZN(_08978_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi222_4 _20895_ (.A1(_05386_),
+ .A2(net1816),
+ .B1(net1819),
+ .B2(net1679),
+ .C1(net1694),
+ .C2(net1814),
+ .ZN(_08979_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi22_4 _20896_ (.A1(net1824),
+ .A2(\soc.core.mgmtsoc_vexriscv_debug_bus_dat_r[8] ),
+ .B1(net1414),
+ .B2(\soc.core.mgmtsoc_litespisdrphycore_sr_in[16] ),
+ .ZN(_08980_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__and3_4 _20897_ (.A1(_08980_),
+ .A2(_08978_),
+ .A3(_08979_),
+ .Z(_08981_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _20898_ (.A1(net978),
+ .A2(_08981_),
+ .ZN(\soc.core.VexRiscv.dBusWishbone_DAT_MISO[8] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _20899_ (.A1(\soc.core.interface3_bank_bus_dat_r[9] ),
+ .A2(\soc.core.interface0_bank_bus_dat_r[9] ),
+ .ZN(_08982_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _20900_ (.A1(\soc.core.interface6_bank_bus_dat_r[9] ),
+ .A2(\soc.core.interface10_bank_bus_dat_r[9] ),
+ .ZN(_08983_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _20901_ (.A1(_08982_),
+ .A2(_08983_),
+ .ZN(_08984_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _20902_ (.A1(_08984_),
+ .A2(\soc.core.interface9_bank_bus_dat_r[9] ),
+ .B(\soc.core.slave_sel_r[5] ),
+ .C(net1812),
+ .ZN(_08985_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi222_4 _20903_ (.A1(_05387_),
+ .A2(net1816),
+ .B1(net1819),
+ .B2(net1678),
+ .C1(\soc.core.hk_dat_i[9] ),
+ .C2(net1814),
+ .ZN(_08986_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi22_4 _20904_ (.A1(net1822),
+ .A2(\soc.core.mgmtsoc_vexriscv_debug_bus_dat_r[9] ),
+ .B1(net1415),
+ .B2(\soc.core.mgmtsoc_litespisdrphycore_sr_in[17] ),
+ .ZN(_08987_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__and3_4 _20905_ (.A1(_08987_),
+ .A2(_08985_),
+ .A3(_08986_),
+ .Z(_08988_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _20906_ (.A1(net978),
+ .A2(_08988_),
+ .ZN(\soc.core.VexRiscv.dBusWishbone_DAT_MISO[9] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _20907_ (.A1(\soc.core.interface3_bank_bus_dat_r[10] ),
+ .A2(\soc.core.interface0_bank_bus_dat_r[10] ),
+ .ZN(_08989_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _20908_ (.A1(\soc.core.interface6_bank_bus_dat_r[10] ),
+ .A2(\soc.core.interface10_bank_bus_dat_r[10] ),
+ .ZN(_08990_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _20909_ (.A1(_08989_),
+ .A2(_08990_),
+ .ZN(_08991_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _20910_ (.A1(_08991_),
+ .A2(\soc.core.interface9_bank_bus_dat_r[10] ),
+ .B(\soc.core.slave_sel_r[5] ),
+ .C(net1812),
+ .ZN(_08992_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi222_4 _20911_ (.A1(_05388_),
+ .A2(net1816),
+ .B1(net1819),
+ .B2(net1677),
+ .C1(net1712),
+ .C2(net1814),
+ .ZN(_08993_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi22_4 _20912_ (.A1(net1823),
+ .A2(\soc.core.mgmtsoc_vexriscv_debug_bus_dat_r[10] ),
+ .B1(net1414),
+ .B2(\soc.core.mgmtsoc_litespisdrphycore_sr_in[18] ),
+ .ZN(_08994_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__and3_4 _20913_ (.A1(_08994_),
+ .A2(_08992_),
+ .A3(_08993_),
+ .Z(_08995_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _20914_ (.A1(net978),
+ .A2(_08995_),
+ .ZN(\soc.core.VexRiscv.dBusWishbone_DAT_MISO[10] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _20915_ (.A1(\soc.core.mgmtsoc_litespisdrphycore_sr_in[19] ),
+ .A2(net1415),
+ .ZN(_08996_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi22_4 _20916_ (.A1(_05389_),
+ .A2(net1818),
+ .B1(net1821),
+ .B2(\soc.core.bus_dat_r[11] ),
+ .ZN(_08997_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _20917_ (.I(_08997_),
+ .ZN(_08998_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi221_4 _20918_ (.A1(net1822),
+ .A2(\soc.core.mgmtsoc_vexriscv_debug_bus_dat_r[11] ),
+ .B1(net1711),
+ .B2(net1815),
+ .C(_08998_),
+ .ZN(_08999_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _20919_ (.A1(\soc.core.interface3_bank_bus_dat_r[11] ),
+ .A2(\soc.core.interface0_bank_bus_dat_r[11] ),
+ .ZN(_09000_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _20920_ (.A1(\soc.core.interface6_bank_bus_dat_r[11] ),
+ .A2(\soc.core.interface10_bank_bus_dat_r[11] ),
+ .ZN(_09001_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _20921_ (.A1(_09000_),
+ .A2(_09001_),
+ .ZN(_09002_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _20922_ (.A1(_09002_),
+ .A2(\soc.core.interface9_bank_bus_dat_r[11] ),
+ .B(\soc.core.slave_sel_r[5] ),
+ .C(net1812),
+ .ZN(_09003_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__and3_4 _20923_ (.A1(_08996_),
+ .A2(_08999_),
+ .A3(_09003_),
+ .Z(_09004_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _20924_ (.A1(net978),
+ .A2(_09004_),
+ .ZN(\soc.core.VexRiscv.dBusWishbone_DAT_MISO[11] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _20925_ (.A1(\soc.core.interface3_bank_bus_dat_r[12] ),
+ .A2(\soc.core.interface0_bank_bus_dat_r[12] ),
+ .ZN(_09005_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _20926_ (.A1(\soc.core.interface6_bank_bus_dat_r[12] ),
+ .A2(\soc.core.interface10_bank_bus_dat_r[12] ),
+ .ZN(_09006_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _20927_ (.A1(_09005_),
+ .A2(_09006_),
+ .ZN(_09007_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _20928_ (.A1(_09007_),
+ .A2(\soc.core.interface9_bank_bus_dat_r[12] ),
+ .B(\soc.core.slave_sel_r[5] ),
+ .C(net1812),
+ .ZN(_09008_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi222_4 _20929_ (.A1(_05390_),
+ .A2(net1818),
+ .B1(net1824),
+ .B2(\soc.core.mgmtsoc_vexriscv_debug_bus_dat_r[12] ),
+ .C1(net1676),
+ .C2(net1821),
+ .ZN(_09009_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _20930_ (.A1(_09008_),
+ .A2(net1413),
+ .ZN(_09010_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi221_4 _20931_ (.A1(net1815),
+ .A2(\soc.core.hk_dat_i[12] ),
+ .B1(net1415),
+ .B2(\soc.core.mgmtsoc_litespisdrphycore_sr_in[20] ),
+ .C(_09010_),
+ .ZN(_09011_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _20932_ (.A1(net979),
+ .A2(_09011_),
+ .ZN(\soc.core.VexRiscv.dBusWishbone_DAT_MISO[12] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _20933_ (.A1(\soc.core.interface3_bank_bus_dat_r[13] ),
+ .A2(\soc.core.interface0_bank_bus_dat_r[13] ),
+ .ZN(_09012_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _20934_ (.A1(\soc.core.interface6_bank_bus_dat_r[13] ),
+ .A2(\soc.core.interface10_bank_bus_dat_r[13] ),
+ .ZN(_09013_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _20935_ (.A1(_09012_),
+ .A2(_09013_),
+ .ZN(_09014_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _20936_ (.A1(_09014_),
+ .A2(\soc.core.interface9_bank_bus_dat_r[13] ),
+ .B(\soc.core.slave_sel_r[5] ),
+ .C(net1812),
+ .ZN(_09015_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi222_4 _20937_ (.A1(_05391_),
+ .A2(net1818),
+ .B1(net1824),
+ .B2(\soc.core.mgmtsoc_vexriscv_debug_bus_dat_r[13] ),
+ .C1(net1675),
+ .C2(net1821),
+ .ZN(_09016_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _20938_ (.A1(_09015_),
+ .A2(net1412),
+ .ZN(_09017_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi221_4 _20939_ (.A1(net1815),
+ .A2(\soc.core.hk_dat_i[13] ),
+ .B1(net1415),
+ .B2(\soc.core.mgmtsoc_litespisdrphycore_sr_in[21] ),
+ .C(_09017_),
+ .ZN(_09018_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _20940_ (.A1(net979),
+ .A2(_09018_),
+ .ZN(\soc.core.VexRiscv.dBusWishbone_DAT_MISO[13] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _20941_ (.A1(\soc.core.interface3_bank_bus_dat_r[14] ),
+ .A2(\soc.core.interface0_bank_bus_dat_r[14] ),
+ .ZN(_09019_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _20942_ (.A1(\soc.core.interface6_bank_bus_dat_r[14] ),
+ .A2(\soc.core.interface10_bank_bus_dat_r[14] ),
+ .ZN(_09020_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _20943_ (.A1(_09019_),
+ .A2(_09020_),
+ .ZN(_09021_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _20944_ (.A1(_09021_),
+ .A2(\soc.core.interface9_bank_bus_dat_r[14] ),
+ .B(\soc.core.slave_sel_r[5] ),
+ .C(net1812),
+ .ZN(_09022_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi222_4 _20945_ (.A1(_05392_),
+ .A2(net1818),
+ .B1(net1824),
+ .B2(\soc.core.mgmtsoc_vexriscv_debug_bus_dat_r[14] ),
+ .C1(net1674),
+ .C2(net1821),
+ .ZN(_09023_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _20946_ (.A1(_09022_),
+ .A2(net1411),
+ .ZN(_09024_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi221_4 _20947_ (.A1(net1815),
+ .A2(\soc.core.hk_dat_i[14] ),
+ .B1(net1415),
+ .B2(\soc.core.mgmtsoc_litespisdrphycore_sr_in[22] ),
+ .C(_09024_),
+ .ZN(_09025_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _20948_ (.A1(net979),
+ .A2(_09025_),
+ .ZN(\soc.core.VexRiscv.dBusWishbone_DAT_MISO[14] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _20949_ (.A1(\soc.core.interface3_bank_bus_dat_r[15] ),
+ .A2(\soc.core.interface0_bank_bus_dat_r[15] ),
+ .ZN(_09026_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _20950_ (.A1(\soc.core.interface6_bank_bus_dat_r[15] ),
+ .A2(\soc.core.interface10_bank_bus_dat_r[15] ),
+ .ZN(_09027_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _20951_ (.A1(_09026_),
+ .A2(_09027_),
+ .ZN(_09028_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _20952_ (.A1(_09028_),
+ .A2(\soc.core.interface9_bank_bus_dat_r[15] ),
+ .B(\soc.core.slave_sel_r[5] ),
+ .C(net1812),
+ .ZN(_09029_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi222_4 _20953_ (.A1(_05393_),
+ .A2(net1816),
+ .B1(net1819),
+ .B2(net1673),
+ .C1(net1710),
+ .C2(net1814),
+ .ZN(_09030_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _20954_ (.A1(_09029_),
+ .A2(_09030_),
+ .ZN(_09031_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi221_4 _20955_ (.A1(net1822),
+ .A2(\soc.core.mgmtsoc_vexriscv_debug_bus_dat_r[15] ),
+ .B1(net1414),
+ .B2(\soc.core.mgmtsoc_litespisdrphycore_sr_in[23] ),
+ .C(_09031_),
+ .ZN(_09032_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _20956_ (.A1(net978),
+ .A2(_09032_),
+ .ZN(\soc.core.VexRiscv.dBusWishbone_DAT_MISO[15] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _20957_ (.A1(\soc.core.interface3_bank_bus_dat_r[16] ),
+ .A2(\soc.core.interface0_bank_bus_dat_r[16] ),
+ .ZN(_09033_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _20958_ (.A1(\soc.core.interface6_bank_bus_dat_r[16] ),
+ .A2(\soc.core.interface10_bank_bus_dat_r[16] ),
+ .ZN(_09034_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _20959_ (.A1(_09033_),
+ .A2(_09034_),
+ .ZN(_09035_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _20960_ (.A1(_09035_),
+ .A2(\soc.core.interface9_bank_bus_dat_r[16] ),
+ .B(\soc.core.slave_sel_r[5] ),
+ .C(net1812),
+ .ZN(_09036_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi222_4 _20961_ (.A1(_05394_),
+ .A2(net1816),
+ .B1(net1819),
+ .B2(\soc.core.bus_dat_r[16] ),
+ .C1(net1709),
+ .C2(net1814),
+ .ZN(_09037_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi22_4 _20962_ (.A1(net1822),
+ .A2(\soc.core.mgmtsoc_vexriscv_debug_bus_dat_r[16] ),
+ .B1(net1414),
+ .B2(\soc.core.mgmtsoc_litespisdrphycore_sr_in[8] ),
+ .ZN(_09038_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__and3_4 _20963_ (.A1(_09038_),
+ .A2(_09036_),
+ .A3(_09037_),
+ .Z(_09039_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _20964_ (.A1(net978),
+ .A2(_09039_),
+ .ZN(\soc.core.VexRiscv.dBusWishbone_DAT_MISO[16] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _20965_ (.A1(\soc.core.interface0_bank_bus_dat_r[17] ),
+ .A2(\soc.core.interface6_bank_bus_dat_r[17] ),
+ .ZN(_09040_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_2 _20966_ (.I(_09040_),
+ .ZN(_09041_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai31_4 _20967_ (.A1(_09041_),
+ .A2(\soc.core.interface10_bank_bus_dat_r[17] ),
+ .A3(\soc.core.interface3_bank_bus_dat_r[17] ),
+ .B(net1615),
+ .ZN(_09042_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi222_4 _20968_ (.A1(_05395_),
+ .A2(net1816),
+ .B1(net1819),
+ .B2(\soc.core.bus_dat_r[17] ),
+ .C1(net1708),
+ .C2(net1814),
+ .ZN(_09043_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi22_4 _20969_ (.A1(net1822),
+ .A2(\soc.core.mgmtsoc_vexriscv_debug_bus_dat_r[17] ),
+ .B1(net1414),
+ .B2(\soc.core.mgmtsoc_litespisdrphycore_sr_in[9] ),
+ .ZN(_09044_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__and3_4 _20970_ (.A1(_09044_),
+ .A2(_09042_),
+ .A3(_09043_),
+ .Z(_09045_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _20971_ (.A1(net978),
+ .A2(_09045_),
+ .ZN(\soc.core.VexRiscv.dBusWishbone_DAT_MISO[17] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _20972_ (.A1(\soc.core.interface0_bank_bus_dat_r[18] ),
+ .A2(\soc.core.interface6_bank_bus_dat_r[18] ),
+ .ZN(_09046_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_2 _20973_ (.I(_09046_),
+ .ZN(_09047_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai31_4 _20974_ (.A1(_09047_),
+ .A2(\soc.core.interface10_bank_bus_dat_r[18] ),
+ .A3(\soc.core.interface3_bank_bus_dat_r[18] ),
+ .B(net1615),
+ .ZN(_09048_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi222_4 _20975_ (.A1(_05396_),
+ .A2(net1816),
+ .B1(net1819),
+ .B2(\soc.core.bus_dat_r[18] ),
+ .C1(net1707),
+ .C2(net1814),
+ .ZN(_09049_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi22_4 _20976_ (.A1(net1822),
+ .A2(\soc.core.mgmtsoc_vexriscv_debug_bus_dat_r[18] ),
+ .B1(net1414),
+ .B2(\soc.core.mgmtsoc_litespisdrphycore_sr_in[10] ),
+ .ZN(_09050_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__and3_4 _20977_ (.A1(_09050_),
+ .A2(_09048_),
+ .A3(_09049_),
+ .Z(_09051_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _20978_ (.A1(net978),
+ .A2(_09051_),
+ .ZN(\soc.core.VexRiscv.dBusWishbone_DAT_MISO[18] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _20979_ (.A1(\soc.core.interface0_bank_bus_dat_r[19] ),
+ .A2(\soc.core.interface6_bank_bus_dat_r[19] ),
+ .ZN(_09052_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_2 _20980_ (.I(_09052_),
+ .ZN(_09053_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai31_4 _20981_ (.A1(_09053_),
+ .A2(\soc.core.interface10_bank_bus_dat_r[19] ),
+ .A3(\soc.core.interface3_bank_bus_dat_r[19] ),
+ .B(net1615),
+ .ZN(_09054_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi222_4 _20982_ (.A1(_05397_),
+ .A2(net1816),
+ .B1(net1819),
+ .B2(\soc.core.bus_dat_r[19] ),
+ .C1(net1706),
+ .C2(net1814),
+ .ZN(_09055_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi22_4 _20983_ (.A1(net1822),
+ .A2(\soc.core.mgmtsoc_vexriscv_debug_bus_dat_r[19] ),
+ .B1(net1414),
+ .B2(\soc.core.mgmtsoc_litespisdrphycore_sr_in[11] ),
+ .ZN(_09056_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__and3_4 _20984_ (.A1(_09056_),
+ .A2(_09054_),
+ .A3(_09055_),
+ .Z(_09057_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _20985_ (.A1(net978),
+ .A2(_09057_),
+ .ZN(\soc.core.VexRiscv.dBusWishbone_DAT_MISO[19] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _20986_ (.A1(\soc.core.interface0_bank_bus_dat_r[20] ),
+ .A2(\soc.core.interface6_bank_bus_dat_r[20] ),
+ .ZN(_09058_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_2 _20987_ (.I(_09058_),
+ .ZN(_09059_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai31_4 _20988_ (.A1(_09059_),
+ .A2(\soc.core.interface10_bank_bus_dat_r[20] ),
+ .A3(\soc.core.interface3_bank_bus_dat_r[20] ),
+ .B(net1615),
+ .ZN(_09060_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi222_4 _20989_ (.A1(_05398_),
+ .A2(net1816),
+ .B1(net1819),
+ .B2(\soc.core.bus_dat_r[20] ),
+ .C1(net1704),
+ .C2(net1814),
+ .ZN(_09061_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi22_4 _20990_ (.A1(net1822),
+ .A2(\soc.core.mgmtsoc_vexriscv_debug_bus_dat_r[20] ),
+ .B1(net1414),
+ .B2(\soc.core.mgmtsoc_litespisdrphycore_sr_in[12] ),
+ .ZN(_09062_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__and3_4 _20991_ (.A1(_09062_),
+ .A2(_09060_),
+ .A3(_09061_),
+ .Z(_09063_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _20992_ (.A1(net978),
+ .A2(_09063_),
+ .ZN(\soc.core.VexRiscv.dBusWishbone_DAT_MISO[20] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _20993_ (.A1(\soc.core.interface0_bank_bus_dat_r[21] ),
+ .A2(\soc.core.interface6_bank_bus_dat_r[21] ),
+ .ZN(_09064_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_1 _20994_ (.I(_09064_),
+ .ZN(_09065_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai31_4 _20995_ (.A1(_09065_),
+ .A2(\soc.core.interface10_bank_bus_dat_r[21] ),
+ .A3(\soc.core.interface3_bank_bus_dat_r[21] ),
+ .B(net1615),
+ .ZN(_09066_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi222_4 _20996_ (.A1(_05399_),
+ .A2(net1816),
+ .B1(net1819),
+ .B2(\soc.core.bus_dat_r[21] ),
+ .C1(net1703),
+ .C2(net1814),
+ .ZN(_09067_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi22_4 _20997_ (.A1(net1822),
+ .A2(\soc.core.mgmtsoc_vexriscv_debug_bus_dat_r[21] ),
+ .B1(net1414),
+ .B2(\soc.core.mgmtsoc_litespisdrphycore_sr_in[13] ),
+ .ZN(_09068_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__and3_4 _20998_ (.A1(_09068_),
+ .A2(_09066_),
+ .A3(_09067_),
+ .Z(_09069_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _20999_ (.A1(net979),
+ .A2(_09069_),
+ .ZN(\soc.core.VexRiscv.dBusWishbone_DAT_MISO[21] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _21000_ (.A1(\soc.core.interface0_bank_bus_dat_r[22] ),
+ .A2(\soc.core.interface6_bank_bus_dat_r[22] ),
+ .ZN(_09070_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_1 _21001_ (.I(_09070_),
+ .ZN(_09071_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai31_4 _21002_ (.A1(_09071_),
+ .A2(\soc.core.interface10_bank_bus_dat_r[22] ),
+ .A3(\soc.core.interface3_bank_bus_dat_r[22] ),
+ .B(net1615),
+ .ZN(_09072_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi222_4 _21003_ (.A1(_05400_),
+ .A2(net1816),
+ .B1(net1819),
+ .B2(\soc.core.bus_dat_r[22] ),
+ .C1(net1702),
+ .C2(net1814),
+ .ZN(_09073_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi22_4 _21004_ (.A1(net1822),
+ .A2(\soc.core.mgmtsoc_vexriscv_debug_bus_dat_r[22] ),
+ .B1(net1414),
+ .B2(\soc.core.mgmtsoc_litespisdrphycore_sr_in[14] ),
+ .ZN(_09074_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__and3_4 _21005_ (.A1(_09074_),
+ .A2(_09072_),
+ .A3(_09073_),
+ .Z(_09075_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _21006_ (.A1(net979),
+ .A2(_09075_),
+ .ZN(\soc.core.VexRiscv.dBusWishbone_DAT_MISO[22] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _21007_ (.A1(\soc.core.interface0_bank_bus_dat_r[23] ),
+ .A2(\soc.core.interface6_bank_bus_dat_r[23] ),
+ .ZN(_09076_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_1 _21008_ (.I(_09076_),
+ .ZN(_09077_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai31_4 _21009_ (.A1(_09077_),
+ .A2(\soc.core.interface10_bank_bus_dat_r[23] ),
+ .A3(\soc.core.interface3_bank_bus_dat_r[23] ),
+ .B(net1615),
+ .ZN(_09078_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi222_4 _21010_ (.A1(_05401_),
+ .A2(net1816),
+ .B1(net1819),
+ .B2(\soc.core.bus_dat_r[23] ),
+ .C1(net1701),
+ .C2(net1814),
+ .ZN(_09079_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi22_4 _21011_ (.A1(net1822),
+ .A2(\soc.core.mgmtsoc_vexriscv_debug_bus_dat_r[23] ),
+ .B1(net1414),
+ .B2(\soc.core.mgmtsoc_litespisdrphycore_sr_in[15] ),
+ .ZN(_09080_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__and3_4 _21012_ (.A1(_09080_),
+ .A2(_09078_),
+ .A3(_09079_),
+ .Z(_09081_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _21013_ (.A1(net978),
+ .A2(_09081_),
+ .ZN(\soc.core.VexRiscv.dBusWishbone_DAT_MISO[23] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _21014_ (.A1(\soc.core.interface0_bank_bus_dat_r[24] ),
+ .A2(\soc.core.interface6_bank_bus_dat_r[24] ),
+ .ZN(_09082_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_2 _21015_ (.I(_09082_),
+ .ZN(_09083_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai31_4 _21016_ (.A1(_09083_),
+ .A2(\soc.core.interface10_bank_bus_dat_r[24] ),
+ .A3(\soc.core.interface3_bank_bus_dat_r[24] ),
+ .B(net1615),
+ .ZN(_09084_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi222_4 _21017_ (.A1(_05402_),
+ .A2(net1817),
+ .B1(net1822),
+ .B2(\soc.core.mgmtsoc_vexriscv_debug_bus_dat_r[24] ),
+ .C1(\soc.core.bus_dat_r[24] ),
+ .C2(net1821),
+ .ZN(_09085_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi22_4 _21018_ (.A1(net1815),
+ .A2(\soc.core.hk_dat_i[24] ),
+ .B1(net1415),
+ .B2(\soc.core.mgmtsoc_litespisdrphycore_sr_in[0] ),
+ .ZN(_09086_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__and3_4 _21019_ (.A1(_09086_),
+ .A2(_09084_),
+ .A3(_09085_),
+ .Z(_09087_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _21020_ (.A1(net979),
+ .A2(_09087_),
+ .ZN(\soc.core.VexRiscv.dBusWishbone_DAT_MISO[24] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _21021_ (.A1(\soc.core.interface0_bank_bus_dat_r[25] ),
+ .A2(\soc.core.interface6_bank_bus_dat_r[25] ),
+ .ZN(_09088_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_1 _21022_ (.I(_09088_),
+ .ZN(_09089_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai31_4 _21023_ (.A1(_09089_),
+ .A2(\soc.core.interface10_bank_bus_dat_r[25] ),
+ .A3(\soc.core.interface3_bank_bus_dat_r[25] ),
+ .B(net1615),
+ .ZN(_09090_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi222_4 _21024_ (.A1(_05403_),
+ .A2(net1816),
+ .B1(net1820),
+ .B2(\soc.core.bus_dat_r[25] ),
+ .C1(\soc.core.hk_dat_i[25] ),
+ .C2(net1815),
+ .ZN(_09091_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi22_4 _21025_ (.A1(net1822),
+ .A2(\soc.core.mgmtsoc_vexriscv_debug_bus_dat_r[25] ),
+ .B1(net1414),
+ .B2(\soc.core.mgmtsoc_litespisdrphycore_sr_in[1] ),
+ .ZN(_09092_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__and3_4 _21026_ (.A1(_09092_),
+ .A2(_09090_),
+ .A3(_09091_),
+ .Z(_09093_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _21027_ (.A1(net979),
+ .A2(_09093_),
+ .ZN(\soc.core.VexRiscv.dBusWishbone_DAT_MISO[25] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _21028_ (.A1(\soc.core.interface0_bank_bus_dat_r[26] ),
+ .A2(\soc.core.interface6_bank_bus_dat_r[26] ),
+ .ZN(_09094_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_2 _21029_ (.I(_09094_),
+ .ZN(_09095_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai31_4 _21030_ (.A1(_09095_),
+ .A2(\soc.core.interface10_bank_bus_dat_r[26] ),
+ .A3(\soc.core.interface3_bank_bus_dat_r[26] ),
+ .B(net1615),
+ .ZN(_09096_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi222_4 _21031_ (.A1(_05404_),
+ .A2(net1816),
+ .B1(net1820),
+ .B2(\soc.core.bus_dat_r[26] ),
+ .C1(\soc.core.hk_dat_i[26] ),
+ .C2(net1815),
+ .ZN(_09097_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi22_4 _21032_ (.A1(net1824),
+ .A2(\soc.core.mgmtsoc_vexriscv_debug_bus_dat_r[26] ),
+ .B1(net1414),
+ .B2(\soc.core.mgmtsoc_litespisdrphycore_sr_in[2] ),
+ .ZN(_09098_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__and3_4 _21033_ (.A1(_09098_),
+ .A2(_09096_),
+ .A3(_09097_),
+ .Z(_09099_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _21034_ (.A1(net978),
+ .A2(_09099_),
+ .ZN(\soc.core.VexRiscv.dBusWishbone_DAT_MISO[26] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _21035_ (.A1(\soc.core.interface0_bank_bus_dat_r[27] ),
+ .A2(\soc.core.interface6_bank_bus_dat_r[27] ),
+ .ZN(_09100_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_2 _21036_ (.I(_09100_),
+ .ZN(_09101_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai31_4 _21037_ (.A1(_09101_),
+ .A2(\soc.core.interface10_bank_bus_dat_r[27] ),
+ .A3(\soc.core.interface3_bank_bus_dat_r[27] ),
+ .B(net1615),
+ .ZN(_09102_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi222_4 _21038_ (.A1(_05405_),
+ .A2(net1816),
+ .B1(net1819),
+ .B2(\soc.core.bus_dat_r[27] ),
+ .C1(\soc.core.hk_dat_i[27] ),
+ .C2(net1814),
+ .ZN(_09103_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi22_4 _21039_ (.A1(net1824),
+ .A2(\soc.core.mgmtsoc_vexriscv_debug_bus_dat_r[27] ),
+ .B1(net1414),
+ .B2(\soc.core.mgmtsoc_litespisdrphycore_sr_in[3] ),
+ .ZN(_09104_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__and3_4 _21040_ (.A1(_09104_),
+ .A2(_09102_),
+ .A3(_09103_),
+ .Z(_09105_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _21041_ (.A1(net978),
+ .A2(_09105_),
+ .ZN(\soc.core.VexRiscv.dBusWishbone_DAT_MISO[27] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _21042_ (.A1(\soc.core.interface0_bank_bus_dat_r[28] ),
+ .A2(\soc.core.interface6_bank_bus_dat_r[28] ),
+ .ZN(_09106_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_2 _21043_ (.I(_09106_),
+ .ZN(_09107_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai31_4 _21044_ (.A1(_09107_),
+ .A2(\soc.core.interface10_bank_bus_dat_r[28] ),
+ .A3(\soc.core.interface3_bank_bus_dat_r[28] ),
+ .B(net1615),
+ .ZN(_09108_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi222_4 _21045_ (.A1(_05406_),
+ .A2(net1816),
+ .B1(net1819),
+ .B2(\soc.core.bus_dat_r[28] ),
+ .C1(\soc.core.hk_dat_i[28] ),
+ .C2(net1814),
+ .ZN(_09109_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi22_4 _21046_ (.A1(net1824),
+ .A2(\soc.core.mgmtsoc_vexriscv_debug_bus_dat_r[28] ),
+ .B1(net1414),
+ .B2(\soc.core.mgmtsoc_litespisdrphycore_sr_in[4] ),
+ .ZN(_09110_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__and3_4 _21047_ (.A1(_09110_),
+ .A2(_09108_),
+ .A3(_09109_),
+ .Z(_09111_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _21048_ (.A1(net978),
+ .A2(_09111_),
+ .ZN(\soc.core.VexRiscv.dBusWishbone_DAT_MISO[28] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _21049_ (.A1(\soc.core.interface0_bank_bus_dat_r[29] ),
+ .A2(\soc.core.interface6_bank_bus_dat_r[29] ),
+ .ZN(_09112_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_2 _21050_ (.I(_09112_),
+ .ZN(_09113_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai31_4 _21051_ (.A1(_09113_),
+ .A2(\soc.core.interface10_bank_bus_dat_r[29] ),
+ .A3(\soc.core.interface3_bank_bus_dat_r[29] ),
+ .B(net1615),
+ .ZN(_09114_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi222_4 _21052_ (.A1(_05407_),
+ .A2(net1818),
+ .B1(net1824),
+ .B2(\soc.core.mgmtsoc_vexriscv_debug_bus_dat_r[29] ),
+ .C1(\soc.core.bus_dat_r[29] ),
+ .C2(net1821),
+ .ZN(_09115_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi22_4 _21053_ (.A1(net1815),
+ .A2(\soc.core.hk_dat_i[29] ),
+ .B1(net1415),
+ .B2(\soc.core.mgmtsoc_litespisdrphycore_sr_in[5] ),
+ .ZN(_09116_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__and3_4 _21054_ (.A1(_09116_),
+ .A2(_09114_),
+ .A3(_09115_),
+ .Z(_09117_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _21055_ (.A1(net979),
+ .A2(_09117_),
+ .ZN(\soc.core.VexRiscv.dBusWishbone_DAT_MISO[29] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _21056_ (.A1(\soc.core.interface0_bank_bus_dat_r[30] ),
+ .A2(\soc.core.interface6_bank_bus_dat_r[30] ),
+ .ZN(_09118_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_1 _21057_ (.I(_09118_),
+ .ZN(_09119_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai31_4 _21058_ (.A1(_09119_),
+ .A2(\soc.core.interface10_bank_bus_dat_r[30] ),
+ .A3(\soc.core.interface3_bank_bus_dat_r[30] ),
+ .B(net1615),
+ .ZN(_09120_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi222_4 _21059_ (.A1(_05408_),
+ .A2(net1818),
+ .B1(net1824),
+ .B2(\soc.core.mgmtsoc_vexriscv_debug_bus_dat_r[30] ),
+ .C1(\soc.core.bus_dat_r[30] ),
+ .C2(net1821),
+ .ZN(_09121_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi22_4 _21060_ (.A1(net1815),
+ .A2(\soc.core.hk_dat_i[30] ),
+ .B1(net1415),
+ .B2(\soc.core.mgmtsoc_litespisdrphycore_sr_in[6] ),
+ .ZN(_09122_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__and3_4 _21061_ (.A1(_09122_),
+ .A2(_09120_),
+ .A3(_09121_),
+ .Z(_09123_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _21062_ (.A1(net979),
+ .A2(_09123_),
+ .ZN(\soc.core.VexRiscv.dBusWishbone_DAT_MISO[30] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _21063_ (.A1(\soc.core.mgmtsoc_litespisdrphycore_sr_in[7] ),
+ .A2(net1415),
+ .ZN(_09124_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi22_4 _21064_ (.A1(_05409_),
+ .A2(net1818),
+ .B1(net1821),
+ .B2(\soc.core.bus_dat_r[31] ),
+ .ZN(_09125_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _21065_ (.I(_09125_),
+ .ZN(_09126_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi221_4 _21066_ (.A1(net1822),
+ .A2(\soc.core.mgmtsoc_vexriscv_debug_bus_dat_r[31] ),
+ .B1(\soc.core.hk_dat_i[31] ),
+ .B2(net1815),
+ .C(_09126_),
+ .ZN(_09127_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _21067_ (.A1(\soc.core.interface0_bank_bus_dat_r[31] ),
+ .A2(\soc.core.interface6_bank_bus_dat_r[31] ),
+ .ZN(_09128_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_1 _21068_ (.I(_09128_),
+ .ZN(_09129_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai31_4 _21069_ (.A1(_09129_),
+ .A2(\soc.core.interface10_bank_bus_dat_r[31] ),
+ .A3(\soc.core.interface3_bank_bus_dat_r[31] ),
+ .B(_08902_),
+ .ZN(_09130_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__and3_4 _21070_ (.A1(_09124_),
+ .A2(_09127_),
+ .A3(_09130_),
+ .Z(_09131_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _21071_ (.A1(net979),
+ .A2(_09131_),
+ .ZN(\soc.core.VexRiscv.dBusWishbone_DAT_MISO[31] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _21072_ (.I0(\soc.core.sys_uart_tx ),
+ .I1(\soc.core.dbg_uart_dbg_uart_tx ),
+ .S(\soc.core.debug_in ),
+ .Z(\soc.core.serial_tx ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _21073_ (.I0(\soc.core.VexRiscv.DebugPlugin_haltedByBreak ),
+ .I1(\soc.core.VexRiscv.DebugPlugin_busReadDataReg[3] ),
+ .S(\soc.core.VexRiscv._zz_when_DebugPlugin_l244 ),
+ .Z(\soc.core.VexRiscv.debug_bus_rsp_data[3] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _21074_ (.I0(net2811),
+ .I1(\soc.core.VexRiscv.DebugPlugin_busReadDataReg[0] ),
+ .S(\soc.core.VexRiscv._zz_when_DebugPlugin_l244 ),
+ .Z(\soc.core.VexRiscv.debug_bus_rsp_data[0] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _21075_ (.I0(\soc.core.VexRiscv.DebugPlugin_haltIt ),
+ .I1(\soc.core.VexRiscv.DebugPlugin_busReadDataReg[1] ),
+ .S(\soc.core.VexRiscv._zz_when_DebugPlugin_l244 ),
+ .Z(\soc.core.VexRiscv.debug_bus_rsp_data[1] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _21076_ (.I0(\soc.core.VexRiscv.DebugPlugin_isPipBusy ),
+ .I1(\soc.core.VexRiscv.DebugPlugin_busReadDataReg[2] ),
+ .S(\soc.core.VexRiscv._zz_when_DebugPlugin_l244 ),
+ .Z(\soc.core.VexRiscv.debug_bus_rsp_data[2] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _21077_ (.I0(\soc.core.VexRiscv.DebugPlugin_stepIt ),
+ .I1(\soc.core.VexRiscv.DebugPlugin_busReadDataReg[4] ),
+ .S(\soc.core.VexRiscv._zz_when_DebugPlugin_l244 ),
+ .Z(\soc.core.VexRiscv.debug_bus_rsp_data[4] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__and3_4 _21078_ (.A1(net1791),
+ .A2(\soc.core.VexRiscv.decode_to_execute_IS_CSR ),
+ .A3(\soc.core.VexRiscv.decode_to_execute_CSR_WRITE_OPCODE ),
+ .Z(_09132_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__and3_4 _21079_ (.A1(\soc.core.VexRiscv.decode_to_execute_CSR_WRITE_OPCODE ),
+ .A2(net1619),
+ .A3(net819),
+ .Z(_09133_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_4 _21080_ (.A1(net1794),
+ .A2(_09133_),
+ .ZN(_09134_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _21081_ (.A1(\soc.core.VexRiscv.CsrPlugin_exceptionPendings_1 ),
+ .A2(net1745),
+ .ZN(_09135_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__and3_4 _21082_ (.A1(\soc.core.VexRiscv.CsrPlugin_interrupt_valid ),
+ .A2(_09135_),
+ .A3(_05283_),
+ .Z(_09136_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__and2_4 _21083_ (.A1(_04997_),
+ .A2(\soc.core.VexRiscv.CsrPlugin_pipelineLiberator_pcValids_2 ),
+ .Z(_09137_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__and3_4 _21084_ (.A1(_05934_),
+ .A2(_09136_),
+ .A3(_09137_),
+ .Z(_09138_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand3_4 _21085_ (.A1(_05934_),
+ .A2(_09136_),
+ .A3(_09137_),
+ .ZN(_09139_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_4 _21086_ (.A1(net1761),
+ .A2(_09138_),
+ .ZN(_09140_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_4 _21087_ (.A1(_04997_),
+ .A2(_09139_),
+ .ZN(_09141_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _21088_ (.A1(\soc.core.VexRiscv.CsrPlugin_mepc[0] ),
+ .A2(net1298),
+ .ZN(_09142_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand3_4 _21089_ (.A1(net1794),
+ .A2(net819),
+ .A3(_09132_),
+ .ZN(_09143_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _21090_ (.A1(\soc.core.VexRiscv._zz_CsrPlugin_csrMapping_readDataInit[0] ),
+ .A2(net1796),
+ .ZN(_09144_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi222_4 _21091_ (.A1(net1794),
+ .A2(\soc.core.VexRiscv.CsrPlugin_mepc[0] ),
+ .B1(\soc.core.VexRiscv.execute_CsrPlugin_csr_834 ),
+ .B2(\soc.core.VexRiscv.CsrPlugin_mcause_exceptionCode[0] ),
+ .C1(net1802),
+ .C2(\soc.core.VexRiscv.CsrPlugin_mtval[0] ),
+ .ZN(_09145_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _21092_ (.A1(_05455_),
+ .A2(_05774_),
+ .B(_09145_),
+ .C(_09144_),
+ .ZN(_09146_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__and3_4 _21093_ (.A1(net1773),
+ .A2(_05808_),
+ .A3(_09146_),
+ .Z(_09147_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi21_4 _21094_ (.A1(net1628),
+ .A2(_05809_),
+ .B(_09147_),
+ .ZN(_09148_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _21095_ (.I0(_09148_),
+ .I1(_09142_),
+ .S(_09134_),
+ .Z(_09149_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _21096_ (.I(_09149_),
+ .ZN(_00097_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _21097_ (.A1(\soc.core.VexRiscv.CsrPlugin_mepc[1] ),
+ .A2(net1298),
+ .ZN(_09150_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _21098_ (.I(_09150_),
+ .ZN(_09151_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi21_4 _21099_ (.A1(\soc.core.VexRiscv.externalInterruptArray_regNext[1] ),
+ .A2(\soc.core.VexRiscv.execute_CsrPlugin_csr_4032 ),
+ .B(net1796),
+ .ZN(_09152_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_4 _21100_ (.A1(_09152_),
+ .A2(_04968_),
+ .ZN(_09153_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi222_4 _21101_ (.A1(net1794),
+ .A2(\soc.core.VexRiscv.CsrPlugin_mepc[1] ),
+ .B1(\soc.core.VexRiscv.CsrPlugin_mcause_exceptionCode[1] ),
+ .B2(\soc.core.VexRiscv.execute_CsrPlugin_csr_834 ),
+ .C1(\soc.core.VexRiscv.CsrPlugin_mtval[1] ),
+ .C2(net1802),
+ .ZN(_09154_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_2 _21102_ (.I(_09154_),
+ .ZN(_09155_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _21103_ (.A1(_09153_),
+ .A2(_09155_),
+ .ZN(_09156_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _21104_ (.A1(_09153_),
+ .A2(_09155_),
+ .B(net1773),
+ .C(_05815_),
+ .ZN(_09157_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _21105_ (.A1(net1628),
+ .A2(_05816_),
+ .ZN(_09158_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _21106_ (.A1(_09157_),
+ .A2(_09158_),
+ .ZN(_09159_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _21107_ (.I0(_09159_),
+ .I1(_09151_),
+ .S(_09134_),
+ .Z(_00108_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _21108_ (.I0(\soc.core.VexRiscv.CsrPlugin_mepc[2] ),
+ .I1(\soc.core.VexRiscv.lastStagePc[2] ),
+ .S(net1296),
+ .Z(_09160_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _21109_ (.A1(\soc.core.VexRiscv._zz_execute_SRC1_CTRL[1] ),
+ .A2(\soc.core.VexRiscv.decode_to_execute_RS1[2] ),
+ .ZN(_09161_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_4 _21110_ (.A1(_05242_),
+ .A2(\soc.core.VexRiscv._zz_execute_SRC1_CTRL[1] ),
+ .ZN(_09162_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_4 _21111_ (.A1(_05241_),
+ .A2(\soc.core.VexRiscv._zz_execute_SRC1_CTRL[0] ),
+ .ZN(_09163_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi211_4 _21112_ (.A1(_05423_),
+ .A2(\soc.core.VexRiscv._zz_execute_SRC1_CTRL[0] ),
+ .B(_09162_),
+ .C(_09161_),
+ .ZN(_09164_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _21113_ (.A1(\soc.core.VexRiscv._zz_CsrPlugin_csrMapping_readDataInit[2] ),
+ .A2(net1796),
+ .ZN(_09165_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi222_4 _21114_ (.A1(\soc.core.VexRiscv.CsrPlugin_mepc[2] ),
+ .A2(net1794),
+ .B1(\soc.core.VexRiscv.execute_CsrPlugin_csr_834 ),
+ .B2(\soc.core.VexRiscv.CsrPlugin_mcause_exceptionCode[2] ),
+ .C1(\soc.core.VexRiscv.CsrPlugin_mtval[2] ),
+ .C2(net1802),
+ .ZN(_09166_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _21115_ (.A1(_05455_),
+ .A2(_05775_),
+ .B(_09166_),
+ .C(_09165_),
+ .ZN(_09167_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _21116_ (.A1(_09167_),
+ .A2(net1773),
+ .ZN(_09168_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _21117_ (.I(_09168_),
+ .ZN(_09169_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _21118_ (.I0(_09169_),
+ .I1(net1628),
+ .S(net1410),
+ .Z(_09170_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_1 _21119_ (.I(_09170_),
+ .ZN(_09171_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _21120_ (.I0(_09170_),
+ .I1(_09160_),
+ .S(net776),
+ .Z(_00119_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _21121_ (.I0(\soc.core.VexRiscv.CsrPlugin_mepc[3] ),
+ .I1(\soc.core.VexRiscv.lastStagePc[3] ),
+ .S(net1294),
+ .Z(_09172_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi222_4 _21122_ (.A1(\soc.core.VexRiscv.CsrPlugin_mie_MSIE ),
+ .A2(\soc.core.VexRiscv.execute_CsrPlugin_csr_772 ),
+ .B1(\soc.core.VexRiscv.execute_CsrPlugin_csr_834 ),
+ .B2(\soc.core.VexRiscv.CsrPlugin_mcause_exceptionCode[3] ),
+ .C1(\soc.core.VexRiscv.CsrPlugin_mip_MSIP ),
+ .C2(\soc.core.VexRiscv.execute_CsrPlugin_csr_836 ),
+ .ZN(_09173_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__and3_4 _21123_ (.A1(\soc.core.VexRiscv._zz_CsrPlugin_csrMapping_readDataInit[3] ),
+ .A2(\soc.core.VexRiscv.externalInterruptArray_regNext[3] ),
+ .A3(\soc.core.VexRiscv.execute_CsrPlugin_csr_4032 ),
+ .Z(_09174_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi222_4 _21124_ (.A1(\soc.core.VexRiscv._zz_CsrPlugin_csrMapping_readDataInit[3] ),
+ .A2(net1796),
+ .B1(\soc.core.VexRiscv.CsrPlugin_mstatus_MIE ),
+ .B2(\soc.core.VexRiscv.execute_CsrPlugin_csr_768 ),
+ .C1(\soc.core.VexRiscv.CsrPlugin_mtval[3] ),
+ .C2(net1802),
+ .ZN(_09175_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi21_4 _21125_ (.A1(\soc.core.VexRiscv.CsrPlugin_mepc[3] ),
+ .A2(net1794),
+ .B(_09174_),
+ .ZN(_09176_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__and3_4 _21126_ (.A1(_09173_),
+ .A2(_09175_),
+ .A3(_09176_),
+ .Z(_09177_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _21127_ (.I(_09177_),
+ .ZN(_09178_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _21128_ (.A1(\soc.core.VexRiscv.CsrPlugin_selfException_payload_badAddr[18] ),
+ .A2(_05803_),
+ .ZN(_09179_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_4 _21129_ (.A1(\soc.core.VexRiscv.decode_to_execute_RS1[3] ),
+ .A2(net1622),
+ .ZN(_09180_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__and2_4 _21130_ (.A1(_09179_),
+ .A2(_09180_),
+ .Z(_09181_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_4 _21131_ (.A1(_09179_),
+ .A2(_09180_),
+ .ZN(_09182_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _21132_ (.A1(net1628),
+ .A2(_09182_),
+ .ZN(_09183_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai31_4 _21133_ (.A1(_09177_),
+ .A2(_09182_),
+ .A3(net1659),
+ .B(_09183_),
+ .ZN(_09184_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_2 _21134_ (.I(_09184_),
+ .ZN(_09185_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _21135_ (.I0(_09184_),
+ .I1(_09172_),
+ .S(net776),
+ .Z(_00122_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _21136_ (.I0(\soc.core.VexRiscv.CsrPlugin_mepc[4] ),
+ .I1(\soc.core.VexRiscv.lastStagePc[4] ),
+ .S(net1294),
+ .Z(_09186_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand3_4 _21137_ (.A1(\soc.core.VexRiscv._zz_CsrPlugin_csrMapping_readDataInit[4] ),
+ .A2(\soc.core.VexRiscv.externalInterruptArray_regNext[4] ),
+ .A3(\soc.core.VexRiscv.execute_CsrPlugin_csr_4032 ),
+ .ZN(_09187_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi222_4 _21138_ (.A1(\soc.core.VexRiscv._zz_CsrPlugin_csrMapping_readDataInit[4] ),
+ .A2(net1796),
+ .B1(\soc.core.VexRiscv.CsrPlugin_mepc[4] ),
+ .B2(net1794),
+ .C1(net1802),
+ .C2(\soc.core.VexRiscv.CsrPlugin_mtval[4] ),
+ .ZN(_09188_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _21139_ (.A1(_09188_),
+ .A2(_09187_),
+ .ZN(_09189_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _21140_ (.A1(\soc.core.VexRiscv.CsrPlugin_selfException_payload_badAddr[19] ),
+ .A2(_05803_),
+ .ZN(_09190_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _21141_ (.A1(\soc.core.VexRiscv.decode_to_execute_RS1[4] ),
+ .A2(net1622),
+ .ZN(_09191_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__and2_4 _21142_ (.A1(_09190_),
+ .A2(_09191_),
+ .Z(_09192_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_4 _21143_ (.A1(_09190_),
+ .A2(_09191_),
+ .ZN(_09193_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand3_4 _21144_ (.A1(net1773),
+ .A2(_09192_),
+ .A3(_09189_),
+ .ZN(_09194_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _21145_ (.A1(net1628),
+ .A2(_09193_),
+ .ZN(_09195_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _21146_ (.A1(_09194_),
+ .A2(_09195_),
+ .ZN(_09196_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_1 _21147_ (.I(_09196_),
+ .ZN(_09197_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _21148_ (.I0(_09196_),
+ .I1(_09186_),
+ .S(net778),
+ .Z(_00123_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _21149_ (.I0(\soc.core.VexRiscv.CsrPlugin_mepc[5] ),
+ .I1(\soc.core.VexRiscv.lastStagePc[5] ),
+ .S(net1296),
+ .Z(_09198_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand3_4 _21150_ (.A1(\soc.core.VexRiscv._zz_CsrPlugin_csrMapping_readDataInit[5] ),
+ .A2(\soc.core.VexRiscv.externalInterruptArray_regNext[5] ),
+ .A3(\soc.core.VexRiscv.execute_CsrPlugin_csr_4032 ),
+ .ZN(_09199_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi222_4 _21151_ (.A1(\soc.core.VexRiscv._zz_CsrPlugin_csrMapping_readDataInit[5] ),
+ .A2(net1796),
+ .B1(\soc.core.VexRiscv.CsrPlugin_mepc[5] ),
+ .B2(net1794),
+ .C1(net1802),
+ .C2(\soc.core.VexRiscv.CsrPlugin_mtval[5] ),
+ .ZN(_09200_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _21152_ (.A1(_09200_),
+ .A2(_09199_),
+ .ZN(_09201_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__and3_4 _21153_ (.A1(_05241_),
+ .A2(_05242_),
+ .A3(\soc.core.VexRiscv.decode_to_execute_RS1[5] ),
+ .Z(_09202_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _21154_ (.A1(\soc.core.VexRiscv.decode_to_execute_RS1[5] ),
+ .A2(net1622),
+ .ZN(_09203_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _21155_ (.A1(_09201_),
+ .A2(net1773),
+ .ZN(_09204_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _21156_ (.I(_09204_),
+ .ZN(_09205_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _21157_ (.I0(_09205_),
+ .I1(net1628),
+ .S(_09202_),
+ .Z(_09206_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_1 _21158_ (.I(_09206_),
+ .ZN(_09207_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _21159_ (.I0(_09206_),
+ .I1(_09198_),
+ .S(net776),
+ .Z(_00124_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _21160_ (.I0(\soc.core.VexRiscv.CsrPlugin_mepc[6] ),
+ .I1(\soc.core.VexRiscv.lastStagePc[6] ),
+ .S(net1296),
+ .Z(_09208_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand3_4 _21161_ (.A1(\soc.core.VexRiscv._zz_CsrPlugin_csrMapping_readDataInit[6] ),
+ .A2(\soc.core.VexRiscv.externalInterruptArray_regNext[6] ),
+ .A3(\soc.core.VexRiscv.execute_CsrPlugin_csr_4032 ),
+ .ZN(_09209_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi222_4 _21162_ (.A1(\soc.core.VexRiscv._zz_CsrPlugin_csrMapping_readDataInit[6] ),
+ .A2(net1796),
+ .B1(net1794),
+ .B2(\soc.core.VexRiscv.CsrPlugin_mepc[6] ),
+ .C1(\soc.core.VexRiscv.CsrPlugin_mtval[6] ),
+ .C2(net1802),
+ .ZN(_09210_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _21163_ (.A1(_09210_),
+ .A2(_09209_),
+ .ZN(_09211_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__and3_4 _21164_ (.A1(_05241_),
+ .A2(_05242_),
+ .A3(\soc.core.VexRiscv.decode_to_execute_RS1[6] ),
+ .Z(_09212_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_4 _21165_ (.A1(\soc.core.VexRiscv.decode_to_execute_RS1[6] ),
+ .A2(net1622),
+ .ZN(_09213_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _21166_ (.A1(_09211_),
+ .A2(_09213_),
+ .ZN(_09214_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai22_4 _21167_ (.A1(net1659),
+ .A2(_09214_),
+ .B1(_09213_),
+ .B2(_05788_),
+ .ZN(_09215_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_1 _21168_ (.I(_09215_),
+ .ZN(_09216_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _21169_ (.I0(_09215_),
+ .I1(_09208_),
+ .S(net776),
+ .Z(_00125_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _21170_ (.I0(\soc.core.VexRiscv.CsrPlugin_mepc[7] ),
+ .I1(\soc.core.VexRiscv.lastStagePc[7] ),
+ .S(net1294),
+ .Z(_09217_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__and3_4 _21171_ (.A1(\soc.core.VexRiscv._zz_CsrPlugin_csrMapping_readDataInit[7] ),
+ .A2(\soc.core.VexRiscv.externalInterruptArray_regNext[7] ),
+ .A3(\soc.core.VexRiscv.execute_CsrPlugin_csr_4032 ),
+ .Z(_09218_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi222_4 _21172_ (.A1(\soc.core.VexRiscv.CsrPlugin_mie_MTIE ),
+ .A2(\soc.core.VexRiscv.execute_CsrPlugin_csr_772 ),
+ .B1(\soc.core.VexRiscv.execute_CsrPlugin_csr_768 ),
+ .B2(\soc.core.VexRiscv.CsrPlugin_mstatus_MPIE ),
+ .C1(\soc.core.VexRiscv.CsrPlugin_mepc[7] ),
+ .C2(net1794),
+ .ZN(_09219_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi221_4 _21173_ (.A1(\soc.core.VexRiscv._zz_CsrPlugin_csrMapping_readDataInit[7] ),
+ .A2(net1796),
+ .B1(net1802),
+ .B2(\soc.core.VexRiscv.CsrPlugin_mtval[7] ),
+ .C(_09218_),
+ .ZN(_09220_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _21174_ (.A1(_09219_),
+ .A2(_09220_),
+ .ZN(_09221_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__and3_4 _21175_ (.A1(_05241_),
+ .A2(_05242_),
+ .A3(\soc.core.VexRiscv.decode_to_execute_RS1[7] ),
+ .Z(_09222_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _21176_ (.A1(\soc.core.VexRiscv.decode_to_execute_RS1[7] ),
+ .A2(net1622),
+ .ZN(_09223_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__and3_4 _21177_ (.A1(_09221_),
+ .A2(_09223_),
+ .A3(net1773),
+ .Z(_09224_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi21_4 _21178_ (.A1(net1628),
+ .A2(_09222_),
+ .B(_09224_),
+ .ZN(_09225_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _21179_ (.I(_09225_),
+ .ZN(_09226_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _21180_ (.I0(_09226_),
+ .I1(_09217_),
+ .S(_09134_),
+ .Z(_00126_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _21181_ (.I0(\soc.core.VexRiscv.CsrPlugin_mepc[8] ),
+ .I1(\soc.core.VexRiscv.lastStagePc[8] ),
+ .S(net1297),
+ .Z(_09227_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi222_4 _21182_ (.A1(\soc.core.VexRiscv._zz_CsrPlugin_csrMapping_readDataInit[8] ),
+ .A2(net1797),
+ .B1(net1795),
+ .B2(\soc.core.VexRiscv.CsrPlugin_mepc[8] ),
+ .C1(\soc.core.VexRiscv.CsrPlugin_mtval[8] ),
+ .C2(net1801),
+ .ZN(_09228_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _21183_ (.I(_09228_),
+ .ZN(_09229_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__and3_4 _21184_ (.A1(_05241_),
+ .A2(_05242_),
+ .A3(\soc.core.VexRiscv.decode_to_execute_RS1[8] ),
+ .Z(_09230_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_4 _21185_ (.A1(\soc.core.VexRiscv.decode_to_execute_RS1[8] ),
+ .A2(net1623),
+ .ZN(_09231_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _21186_ (.A1(_09231_),
+ .A2(net1776),
+ .ZN(_09232_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai22_4 _21187_ (.A1(_09232_),
+ .A2(_09228_),
+ .B1(net1578),
+ .B2(_09231_),
+ .ZN(_09233_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_1 _21188_ (.I(_09233_),
+ .ZN(_09234_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _21189_ (.I0(_09233_),
+ .I1(_09227_),
+ .S(net779),
+ .Z(_00127_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _21190_ (.I0(\soc.core.VexRiscv.CsrPlugin_mepc[9] ),
+ .I1(\soc.core.VexRiscv.lastStagePc[9] ),
+ .S(net1297),
+ .Z(_09235_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi222_4 _21191_ (.A1(\soc.core.VexRiscv._zz_CsrPlugin_csrMapping_readDataInit[9] ),
+ .A2(net1799),
+ .B1(net1795),
+ .B2(\soc.core.VexRiscv.CsrPlugin_mepc[9] ),
+ .C1(\soc.core.VexRiscv.CsrPlugin_mtval[9] ),
+ .C2(net1803),
+ .ZN(_09236_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _21192_ (.I(_09236_),
+ .ZN(_09237_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__and3_4 _21193_ (.A1(_05241_),
+ .A2(_05242_),
+ .A3(\soc.core.VexRiscv.decode_to_execute_RS1[9] ),
+ .Z(_09238_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_4 _21194_ (.A1(\soc.core.VexRiscv.decode_to_execute_RS1[9] ),
+ .A2(net1622),
+ .ZN(_09239_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _21195_ (.A1(_09239_),
+ .A2(net1776),
+ .ZN(_09240_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai22_4 _21196_ (.A1(_09240_),
+ .A2(_09236_),
+ .B1(net1578),
+ .B2(_09239_),
+ .ZN(_09241_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_1 _21197_ (.I(_09241_),
+ .ZN(_09242_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _21198_ (.I0(_09241_),
+ .I1(_09235_),
+ .S(net779),
+ .Z(_00128_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _21199_ (.I0(\soc.core.VexRiscv.CsrPlugin_mepc[10] ),
+ .I1(\soc.core.VexRiscv.lastStagePc[10] ),
+ .S(net1296),
+ .Z(_09243_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi222_4 _21200_ (.A1(\soc.core.VexRiscv._zz_CsrPlugin_csrMapping_readDataInit[10] ),
+ .A2(net1799),
+ .B1(net1794),
+ .B2(\soc.core.VexRiscv.CsrPlugin_mepc[10] ),
+ .C1(\soc.core.VexRiscv.CsrPlugin_mtval[10] ),
+ .C2(net1802),
+ .ZN(_09244_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _21201_ (.I(_09244_),
+ .ZN(_09245_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__and3_4 _21202_ (.A1(_05241_),
+ .A2(_05242_),
+ .A3(\soc.core.VexRiscv.decode_to_execute_RS1[10] ),
+ .Z(_09246_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_4 _21203_ (.A1(\soc.core.VexRiscv.decode_to_execute_RS1[10] ),
+ .A2(net1622),
+ .ZN(_09247_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _21204_ (.A1(_09247_),
+ .A2(net1774),
+ .ZN(_09248_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai22_4 _21205_ (.A1(_09248_),
+ .A2(_09244_),
+ .B1(net1578),
+ .B2(_09247_),
+ .ZN(_09249_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_1 _21206_ (.I(_09249_),
+ .ZN(_09250_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _21207_ (.I0(_09249_),
+ .I1(_09243_),
+ .S(net776),
+ .Z(_00098_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _21208_ (.I0(\soc.core.VexRiscv.CsrPlugin_mepc[11] ),
+ .I1(\soc.core.VexRiscv.lastStagePc[11] ),
+ .S(net1296),
+ .Z(_09251_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi222_4 _21209_ (.A1(\soc.core.VexRiscv.execute_CsrPlugin_csr_836 ),
+ .A2(\soc.core.VexRiscv.CsrPlugin_mip_MEIP ),
+ .B1(\soc.core.VexRiscv.execute_CsrPlugin_csr_768 ),
+ .B2(\soc.core.VexRiscv.CsrPlugin_mstatus_MPP[0] ),
+ .C1(\soc.core.VexRiscv.CsrPlugin_mtval[11] ),
+ .C2(net1802),
+ .ZN(_09252_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi222_4 _21210_ (.A1(\soc.core.VexRiscv._zz_CsrPlugin_csrMapping_readDataInit[11] ),
+ .A2(net1796),
+ .B1(net1794),
+ .B2(\soc.core.VexRiscv.CsrPlugin_mepc[11] ),
+ .C1(\soc.core.VexRiscv.execute_CsrPlugin_csr_772 ),
+ .C2(\soc.core.VexRiscv.CsrPlugin_mie_MEIE ),
+ .ZN(_09253_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__and2_4 _21211_ (.A1(_09252_),
+ .A2(_09253_),
+ .Z(_09254_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_4 _21212_ (.A1(_05435_),
+ .A2(_05806_),
+ .ZN(_09255_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_4 _21213_ (.A1(\soc.core.VexRiscv.decode_to_execute_RS1[11] ),
+ .A2(net1622),
+ .ZN(_09256_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _21214_ (.A1(_09256_),
+ .A2(net1773),
+ .ZN(_09257_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _21215_ (.A1(_09254_),
+ .A2(_09257_),
+ .ZN(_09258_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi21_4 _21216_ (.A1(net1628),
+ .A2(_09255_),
+ .B(_09258_),
+ .ZN(_09259_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai22_4 _21217_ (.A1(_09257_),
+ .A2(_09254_),
+ .B1(net1578),
+ .B2(_09256_),
+ .ZN(_09260_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _21218_ (.I0(_09260_),
+ .I1(_09251_),
+ .S(_09134_),
+ .Z(_00099_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _21219_ (.A1(\soc.core.VexRiscv.CsrPlugin_selfException_payload_badAddr[12] ),
+ .A2(_09162_),
+ .ZN(_09261_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _21220_ (.A1(\soc.core.VexRiscv.decode_to_execute_RS1[12] ),
+ .A2(net1622),
+ .ZN(_09262_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__and2_4 _21221_ (.A1(_09261_),
+ .A2(_09262_),
+ .Z(_09263_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_4 _21222_ (.A1(_09261_),
+ .A2(_09262_),
+ .ZN(_09264_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _21223_ (.A1(\soc.core.VexRiscv.execute_CsrPlugin_csr_768 ),
+ .A2(\soc.core.VexRiscv.CsrPlugin_mstatus_MPP[1] ),
+ .ZN(_09265_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi222_4 _21224_ (.A1(\soc.core.VexRiscv._zz_CsrPlugin_csrMapping_readDataInit[12] ),
+ .A2(net1796),
+ .B1(net1794),
+ .B2(\soc.core.VexRiscv.CsrPlugin_mepc[12] ),
+ .C1(\soc.core.VexRiscv.CsrPlugin_mtval[12] ),
+ .C2(net1802),
+ .ZN(_09266_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _21225_ (.A1(_09266_),
+ .A2(_09265_),
+ .ZN(_09267_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _21226_ (.A1(_09267_),
+ .A2(net1773),
+ .ZN(_09268_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _21227_ (.I(_09268_),
+ .ZN(_09269_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _21228_ (.I0(_09268_),
+ .I1(net1578),
+ .S(_09264_),
+ .Z(_09270_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _21229_ (.I0(_09269_),
+ .I1(net1628),
+ .S(_09264_),
+ .Z(_09271_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _21230_ (.I0(\soc.core.VexRiscv.CsrPlugin_mepc[12] ),
+ .I1(\soc.core.VexRiscv.lastStagePc[12] ),
+ .S(net1296),
+ .Z(_09272_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _21231_ (.I0(_09271_),
+ .I1(_09272_),
+ .S(_09134_),
+ .Z(_00100_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _21232_ (.I0(\soc.core.VexRiscv.CsrPlugin_mepc[13] ),
+ .I1(\soc.core.VexRiscv.lastStagePc[13] ),
+ .S(net1295),
+ .Z(_09273_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _21233_ (.A1(\soc.core.VexRiscv.decode_to_execute_RS1[13] ),
+ .A2(net1622),
+ .ZN(_09274_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _21234_ (.A1(net1773),
+ .A2(net1577),
+ .ZN(_09275_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__and2_4 _21235_ (.A1(_09274_),
+ .A2(_09275_),
+ .Z(_09276_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_4 _21236_ (.A1(_09274_),
+ .A2(_09275_),
+ .ZN(_09277_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi222_4 _21237_ (.A1(\soc.core.VexRiscv._zz_CsrPlugin_csrMapping_readDataInit[13] ),
+ .A2(net1797),
+ .B1(net1794),
+ .B2(\soc.core.VexRiscv.CsrPlugin_mepc[13] ),
+ .C1(\soc.core.VexRiscv.CsrPlugin_mtval[13] ),
+ .C2(net1801),
+ .ZN(_09278_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _21238_ (.A1(_09278_),
+ .A2(_05239_),
+ .ZN(_09279_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _21239_ (.I0(_09279_),
+ .I1(net1629),
+ .S(_09277_),
+ .Z(_09280_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_1 _21240_ (.I(_09280_),
+ .ZN(_09281_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _21241_ (.I0(_09280_),
+ .I1(_09273_),
+ .S(net777),
+ .Z(_00101_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _21242_ (.I0(\soc.core.VexRiscv.CsrPlugin_mepc[14] ),
+ .I1(\soc.core.VexRiscv.lastStagePc[14] ),
+ .S(net1295),
+ .Z(_09282_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi22_4 _21243_ (.A1(\soc.core.VexRiscv.decode_to_execute_RS1[14] ),
+ .A2(net1622),
+ .B1(_09162_),
+ .B2(\soc.core.VexRiscv.CsrPlugin_selfException_payload_badAddr[14] ),
+ .ZN(_09283_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai22_4 _21244_ (.A1(_05429_),
+ .A2(_05806_),
+ .B1(_09163_),
+ .B2(_05428_),
+ .ZN(_09284_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi222_4 _21245_ (.A1(\soc.core.VexRiscv._zz_CsrPlugin_csrMapping_readDataInit[14] ),
+ .A2(net1797),
+ .B1(net1793),
+ .B2(\soc.core.VexRiscv.CsrPlugin_mepc[14] ),
+ .C1(\soc.core.VexRiscv.CsrPlugin_mtval[14] ),
+ .C2(net1801),
+ .ZN(_09285_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _21246_ (.I(_09285_),
+ .ZN(_09286_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _21247_ (.A1(_09285_),
+ .A2(_05239_),
+ .ZN(_09287_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _21248_ (.I0(_09287_),
+ .I1(net1629),
+ .S(_09284_),
+ .Z(_09288_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_1 _21249_ (.I(_09288_),
+ .ZN(_09289_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _21250_ (.I0(_09288_),
+ .I1(_09282_),
+ .S(net777),
+ .Z(_00102_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _21251_ (.I0(\soc.core.VexRiscv.CsrPlugin_mepc[15] ),
+ .I1(\soc.core.VexRiscv.lastStagePc[15] ),
+ .S(net1295),
+ .Z(_09290_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _21252_ (.A1(\soc.core.VexRiscv.decode_to_execute_RS1[15] ),
+ .A2(net1622),
+ .ZN(_09291_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _21253_ (.A1(\soc.core.VexRiscv.CsrPlugin_selfException_payload_badAddr[15] ),
+ .A2(net1577),
+ .ZN(_09292_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__and2_4 _21254_ (.A1(_09291_),
+ .A2(_09292_),
+ .Z(_09293_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_4 _21255_ (.A1(_09291_),
+ .A2(_09292_),
+ .ZN(_09294_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _21256_ (.A1(net1801),
+ .A2(\soc.core.VexRiscv.CsrPlugin_mtval[15] ),
+ .ZN(_09295_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi22_4 _21257_ (.A1(\soc.core.VexRiscv._zz_CsrPlugin_csrMapping_readDataInit[15] ),
+ .A2(net1797),
+ .B1(net1793),
+ .B2(\soc.core.VexRiscv.CsrPlugin_mepc[15] ),
+ .ZN(_09296_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _21258_ (.A1(_09296_),
+ .A2(_09295_),
+ .ZN(_09297_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _21259_ (.A1(_09297_),
+ .A2(net1776),
+ .ZN(_09298_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _21260_ (.I(_09298_),
+ .ZN(_09299_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _21261_ (.I0(_09299_),
+ .I1(net1629),
+ .S(_09294_),
+ .Z(_09300_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_1 _21262_ (.I(_09300_),
+ .ZN(_09301_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _21263_ (.I0(_09300_),
+ .I1(_09290_),
+ .S(net777),
+ .Z(_00103_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _21264_ (.I0(\soc.core.VexRiscv.CsrPlugin_mepc[16] ),
+ .I1(\soc.core.VexRiscv.lastStagePc[16] ),
+ .S(net1295),
+ .Z(_09302_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _21265_ (.A1(\soc.core.VexRiscv.decode_to_execute_RS1[16] ),
+ .A2(net1622),
+ .ZN(_09303_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _21266_ (.A1(\soc.core.VexRiscv.CsrPlugin_selfException_payload_badAddr[16] ),
+ .A2(net1576),
+ .ZN(_09304_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__and2_4 _21267_ (.A1(_09303_),
+ .A2(_09304_),
+ .Z(_09305_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _21268_ (.A1(_09303_),
+ .A2(_09304_),
+ .ZN(_09306_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _21269_ (.A1(net1801),
+ .A2(\soc.core.VexRiscv.CsrPlugin_mtval[16] ),
+ .ZN(_09307_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi22_4 _21270_ (.A1(\soc.core.VexRiscv._zz_CsrPlugin_csrMapping_readDataInit[16] ),
+ .A2(net1797),
+ .B1(net1793),
+ .B2(\soc.core.VexRiscv.CsrPlugin_mepc[16] ),
+ .ZN(_09308_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _21271_ (.A1(_09308_),
+ .A2(_09307_),
+ .ZN(_09309_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _21272_ (.A1(_09309_),
+ .A2(net1775),
+ .ZN(_09310_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _21273_ (.I(_09310_),
+ .ZN(_09311_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _21274_ (.I0(_09311_),
+ .I1(net1629),
+ .S(_09306_),
+ .Z(_09312_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_1 _21275_ (.I(_09312_),
+ .ZN(_09313_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _21276_ (.I0(_09312_),
+ .I1(_09302_),
+ .S(net777),
+ .Z(_00104_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _21277_ (.I0(\soc.core.VexRiscv.CsrPlugin_mepc[17] ),
+ .I1(\soc.core.VexRiscv.lastStagePc[17] ),
+ .S(net1295),
+ .Z(_09314_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _21278_ (.A1(\soc.core.VexRiscv._zz_execute_SRC1_CTRL[0] ),
+ .A2(\soc.core.VexRiscv.decode_to_execute_RS1[17] ),
+ .ZN(_09315_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi211_4 _21279_ (.A1(\soc.core.VexRiscv._zz_execute_SRC1_CTRL[0] ),
+ .A2(_05423_),
+ .B(_09315_),
+ .C(\soc.core.VexRiscv._zz_execute_SRC1_CTRL[1] ),
+ .ZN(_09316_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi222_4 _21280_ (.A1(\soc.core.VexRiscv._zz_CsrPlugin_csrMapping_readDataInit[17] ),
+ .A2(net1797),
+ .B1(net1793),
+ .B2(\soc.core.VexRiscv.CsrPlugin_mepc[17] ),
+ .C1(\soc.core.VexRiscv.CsrPlugin_mtval[17] ),
+ .C2(net1801),
+ .ZN(_09317_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _21281_ (.I(_09317_),
+ .ZN(_09318_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _21282_ (.A1(_09317_),
+ .A2(net1659),
+ .ZN(_09319_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _21283_ (.I0(_09319_),
+ .I1(net1629),
+ .S(_09316_),
+ .Z(_09320_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_1 _21284_ (.I(_09320_),
+ .ZN(_09321_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _21285_ (.I0(_09320_),
+ .I1(_09314_),
+ .S(net777),
+ .Z(_00105_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _21286_ (.I0(\soc.core.VexRiscv.CsrPlugin_mepc[18] ),
+ .I1(\soc.core.VexRiscv.lastStagePc[18] ),
+ .S(net1296),
+ .Z(_09322_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi22_4 _21287_ (.A1(\soc.core.VexRiscv.decode_to_execute_RS1[18] ),
+ .A2(net1622),
+ .B1(net1576),
+ .B2(\soc.core.VexRiscv.CsrPlugin_selfException_payload_badAddr[18] ),
+ .ZN(_09323_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _21288_ (.I(net1409),
+ .ZN(_09324_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi222_4 _21289_ (.A1(\soc.core.VexRiscv._zz_CsrPlugin_csrMapping_readDataInit[18] ),
+ .A2(net1798),
+ .B1(net1793),
+ .B2(\soc.core.VexRiscv.CsrPlugin_mepc[18] ),
+ .C1(\soc.core.VexRiscv.CsrPlugin_mtval[18] ),
+ .C2(net1800),
+ .ZN(_09325_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _21290_ (.A1(_09325_),
+ .A2(net1659),
+ .ZN(_09326_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _21291_ (.I0(net1628),
+ .I1(_09326_),
+ .S(_09323_),
+ .Z(_09327_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_1 _21292_ (.I(_09327_),
+ .ZN(_09328_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _21293_ (.I0(_09327_),
+ .I1(_09322_),
+ .S(net778),
+ .Z(_00106_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _21294_ (.I0(\soc.core.VexRiscv.CsrPlugin_mepc[19] ),
+ .I1(\soc.core.VexRiscv.lastStagePc[19] ),
+ .S(net1295),
+ .Z(_09329_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_4 _21295_ (.A1(\soc.core.VexRiscv.decode_to_execute_RS1[19] ),
+ .A2(net1622),
+ .ZN(_09330_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_4 _21296_ (.A1(\soc.core.VexRiscv.CsrPlugin_selfException_payload_badAddr[19] ),
+ .A2(net1576),
+ .ZN(_09331_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__and2_4 _21297_ (.A1(_09330_),
+ .A2(_09331_),
+ .Z(_09332_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_4 _21298_ (.A1(_09330_),
+ .A2(_09331_),
+ .ZN(_09333_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _21299_ (.A1(net1801),
+ .A2(\soc.core.VexRiscv.CsrPlugin_mtval[19] ),
+ .ZN(_09334_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi22_4 _21300_ (.A1(\soc.core.VexRiscv._zz_CsrPlugin_csrMapping_readDataInit[19] ),
+ .A2(net1797),
+ .B1(net1793),
+ .B2(\soc.core.VexRiscv.CsrPlugin_mepc[19] ),
+ .ZN(_09335_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _21301_ (.A1(_09335_),
+ .A2(_09334_),
+ .ZN(_09336_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _21302_ (.A1(_09336_),
+ .A2(net1776),
+ .ZN(_09337_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _21303_ (.I(_09337_),
+ .ZN(_09338_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _21304_ (.I0(_09338_),
+ .I1(net1629),
+ .S(_09333_),
+ .Z(_09339_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_1 _21305_ (.I(_09339_),
+ .ZN(_09340_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _21306_ (.I0(_09339_),
+ .I1(_09329_),
+ .S(net777),
+ .Z(_00107_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _21307_ (.I0(\soc.core.VexRiscv.CsrPlugin_mepc[20] ),
+ .I1(\soc.core.VexRiscv.lastStagePc[20] ),
+ .S(net1295),
+ .Z(_09341_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _21308_ (.A1(\soc.core.VexRiscv.decode_to_execute_RS1[20] ),
+ .A2(net1622),
+ .ZN(_09342_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _21309_ (.A1(\soc.core.VexRiscv.CsrPlugin_selfException_payload_badAddr[20] ),
+ .A2(_09162_),
+ .ZN(_09343_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__and2_4 _21310_ (.A1(_09342_),
+ .A2(_09343_),
+ .Z(_09344_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_4 _21311_ (.A1(_09342_),
+ .A2(_09343_),
+ .ZN(_09345_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _21312_ (.A1(net1801),
+ .A2(\soc.core.VexRiscv.CsrPlugin_mtval[20] ),
+ .ZN(_09346_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi22_4 _21313_ (.A1(\soc.core.VexRiscv._zz_CsrPlugin_csrMapping_readDataInit[20] ),
+ .A2(net1799),
+ .B1(net1793),
+ .B2(\soc.core.VexRiscv.CsrPlugin_mepc[20] ),
+ .ZN(_09347_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _21314_ (.A1(_09347_),
+ .A2(_09346_),
+ .ZN(_09348_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _21315_ (.A1(_09348_),
+ .A2(net1776),
+ .ZN(_09349_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _21316_ (.I(_09349_),
+ .ZN(_09350_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _21317_ (.I0(_09350_),
+ .I1(net1629),
+ .S(_09345_),
+ .Z(_09351_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_1 _21318_ (.I(_09351_),
+ .ZN(_09352_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _21319_ (.I0(_09351_),
+ .I1(_09341_),
+ .S(net777),
+ .Z(_00109_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _21320_ (.I0(\soc.core.VexRiscv.CsrPlugin_mepc[21] ),
+ .I1(\soc.core.VexRiscv.lastStagePc[21] ),
+ .S(net1297),
+ .Z(_09353_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _21321_ (.A1(\soc.core.VexRiscv.decode_to_execute_RS1[21] ),
+ .A2(net1622),
+ .ZN(_09354_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _21322_ (.A1(\soc.core.VexRiscv.CsrPlugin_selfException_payload_badAddr[21] ),
+ .A2(_09162_),
+ .ZN(_09355_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__and2_4 _21323_ (.A1(_09354_),
+ .A2(_09355_),
+ .Z(_09356_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_4 _21324_ (.A1(_09354_),
+ .A2(_09355_),
+ .ZN(_09357_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _21325_ (.A1(net1801),
+ .A2(\soc.core.VexRiscv.CsrPlugin_mtval[21] ),
+ .ZN(_09358_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi22_4 _21326_ (.A1(\soc.core.VexRiscv._zz_CsrPlugin_csrMapping_readDataInit[21] ),
+ .A2(net1799),
+ .B1(net1795),
+ .B2(\soc.core.VexRiscv.CsrPlugin_mepc[21] ),
+ .ZN(_09359_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _21327_ (.A1(_09359_),
+ .A2(_09358_),
+ .ZN(_09360_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _21328_ (.A1(_09360_),
+ .A2(net1776),
+ .ZN(_09361_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _21329_ (.I(_09361_),
+ .ZN(_09362_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _21330_ (.I0(_09362_),
+ .I1(net1629),
+ .S(_09357_),
+ .Z(_09363_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_1 _21331_ (.I(_09363_),
+ .ZN(_09364_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _21332_ (.I0(_09363_),
+ .I1(_09353_),
+ .S(net777),
+ .Z(_00110_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _21333_ (.I0(\soc.core.VexRiscv.CsrPlugin_mepc[22] ),
+ .I1(\soc.core.VexRiscv.lastStagePc[22] ),
+ .S(net1297),
+ .Z(_09365_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_4 _21334_ (.A1(\soc.core.VexRiscv.decode_to_execute_RS1[22] ),
+ .A2(net1623),
+ .ZN(_09366_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_4 _21335_ (.A1(\soc.core.VexRiscv.CsrPlugin_selfException_payload_badAddr[22] ),
+ .A2(net1576),
+ .ZN(_09367_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__and2_4 _21336_ (.A1(_09366_),
+ .A2(_09367_),
+ .Z(_09368_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_4 _21337_ (.A1(_09366_),
+ .A2(_09367_),
+ .ZN(_09369_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi222_4 _21338_ (.A1(\soc.core.VexRiscv._zz_CsrPlugin_csrMapping_readDataInit[22] ),
+ .A2(net1799),
+ .B1(net1795),
+ .B2(\soc.core.VexRiscv.CsrPlugin_mepc[22] ),
+ .C1(\soc.core.VexRiscv.CsrPlugin_mtval[22] ),
+ .C2(net1803),
+ .ZN(_09370_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _21339_ (.A1(_09370_),
+ .A2(_05239_),
+ .ZN(_09371_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _21340_ (.I0(_09371_),
+ .I1(net1629),
+ .S(_09369_),
+ .Z(_09372_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_1 _21341_ (.I(_09372_),
+ .ZN(_09373_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _21342_ (.I0(_09372_),
+ .I1(_09365_),
+ .S(net777),
+ .Z(_00111_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _21343_ (.I0(\soc.core.VexRiscv.CsrPlugin_mepc[23] ),
+ .I1(\soc.core.VexRiscv.lastStagePc[23] ),
+ .S(net1297),
+ .Z(_09374_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi22_4 _21344_ (.A1(\soc.core.VexRiscv.decode_to_execute_RS1[23] ),
+ .A2(_05805_),
+ .B1(net1576),
+ .B2(\soc.core.VexRiscv.CsrPlugin_selfException_payload_badAddr[23] ),
+ .ZN(_09375_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai22_4 _21345_ (.A1(_05420_),
+ .A2(_05806_),
+ .B1(_09163_),
+ .B2(_05254_),
+ .ZN(_09376_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi222_4 _21346_ (.A1(\soc.core.VexRiscv._zz_CsrPlugin_csrMapping_readDataInit[23] ),
+ .A2(net1799),
+ .B1(net1795),
+ .B2(\soc.core.VexRiscv.CsrPlugin_mepc[23] ),
+ .C1(\soc.core.VexRiscv.CsrPlugin_mtval[23] ),
+ .C2(net1803),
+ .ZN(_09377_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _21347_ (.A1(_09377_),
+ .A2(_05239_),
+ .ZN(_09378_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _21348_ (.I0(_09378_),
+ .I1(net1629),
+ .S(_09376_),
+ .Z(_09379_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_1 _21349_ (.I(_09379_),
+ .ZN(_09380_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _21350_ (.I0(_09379_),
+ .I1(_09374_),
+ .S(net777),
+ .Z(_00112_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _21351_ (.I0(\soc.core.VexRiscv.CsrPlugin_mepc[24] ),
+ .I1(\soc.core.VexRiscv.lastStagePc[24] ),
+ .S(net1297),
+ .Z(_09381_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _21352_ (.A1(\soc.core.VexRiscv.decode_to_execute_RS1[24] ),
+ .A2(net1622),
+ .ZN(_09382_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _21353_ (.A1(\soc.core.VexRiscv.CsrPlugin_selfException_payload_badAddr[24] ),
+ .A2(net1577),
+ .ZN(_09383_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__and2_4 _21354_ (.A1(_09382_),
+ .A2(_09383_),
+ .Z(_09384_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_4 _21355_ (.A1(_09382_),
+ .A2(_09383_),
+ .ZN(_09385_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi222_4 _21356_ (.A1(\soc.core.VexRiscv._zz_CsrPlugin_csrMapping_readDataInit[24] ),
+ .A2(net1799),
+ .B1(net1795),
+ .B2(\soc.core.VexRiscv.CsrPlugin_mepc[24] ),
+ .C1(\soc.core.VexRiscv.CsrPlugin_mtval[24] ),
+ .C2(net1803),
+ .ZN(_09386_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _21357_ (.A1(_09386_),
+ .A2(_05239_),
+ .ZN(_09387_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _21358_ (.I0(_09387_),
+ .I1(net1629),
+ .S(_09385_),
+ .Z(_09388_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_1 _21359_ (.I(_09388_),
+ .ZN(_09389_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _21360_ (.I0(_09388_),
+ .I1(_09381_),
+ .S(net777),
+ .Z(_00113_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _21361_ (.I0(\soc.core.VexRiscv.CsrPlugin_mepc[25] ),
+ .I1(\soc.core.VexRiscv.lastStagePc[25] ),
+ .S(net1297),
+ .Z(_09390_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _21362_ (.A1(\soc.core.VexRiscv.decode_to_execute_RS1[25] ),
+ .A2(net1623),
+ .ZN(_09391_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _21363_ (.A1(\soc.core.VexRiscv.CsrPlugin_selfException_payload_badAddr[25] ),
+ .A2(net1577),
+ .ZN(_09392_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__and2_4 _21364_ (.A1(_09391_),
+ .A2(_09392_),
+ .Z(_09393_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _21365_ (.A1(_09391_),
+ .A2(_09392_),
+ .ZN(_09394_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi222_4 _21366_ (.A1(\soc.core.VexRiscv._zz_CsrPlugin_csrMapping_readDataInit[25] ),
+ .A2(net1799),
+ .B1(net1795),
+ .B2(\soc.core.VexRiscv.CsrPlugin_mepc[25] ),
+ .C1(\soc.core.VexRiscv.CsrPlugin_mtval[25] ),
+ .C2(net1803),
+ .ZN(_09395_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _21367_ (.I(_09395_),
+ .ZN(_09396_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _21368_ (.A1(_09395_),
+ .A2(_05239_),
+ .ZN(_09397_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _21369_ (.I0(_09397_),
+ .I1(_05789_),
+ .S(_09394_),
+ .Z(_09398_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_1 _21370_ (.I(_09398_),
+ .ZN(_09399_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _21371_ (.I0(_09398_),
+ .I1(_09390_),
+ .S(net777),
+ .Z(_00114_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _21372_ (.I0(\soc.core.VexRiscv.CsrPlugin_mepc[26] ),
+ .I1(\soc.core.VexRiscv.lastStagePc[26] ),
+ .S(net1297),
+ .Z(_09400_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _21373_ (.A1(\soc.core.VexRiscv.decode_to_execute_RS1[26] ),
+ .A2(net1623),
+ .ZN(_09401_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _21374_ (.A1(\soc.core.VexRiscv.CsrPlugin_selfException_payload_badAddr[26] ),
+ .A2(net1577),
+ .ZN(_09402_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__and2_4 _21375_ (.A1(_09401_),
+ .A2(_09402_),
+ .Z(_09403_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_4 _21376_ (.A1(_09401_),
+ .A2(_09402_),
+ .ZN(_09404_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi222_4 _21377_ (.A1(\soc.core.VexRiscv._zz_CsrPlugin_csrMapping_readDataInit[26] ),
+ .A2(net1799),
+ .B1(net1795),
+ .B2(\soc.core.VexRiscv.CsrPlugin_mepc[26] ),
+ .C1(\soc.core.VexRiscv.CsrPlugin_mtval[26] ),
+ .C2(net1803),
+ .ZN(_09405_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _21378_ (.A1(_09405_),
+ .A2(_05239_),
+ .ZN(_09406_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _21379_ (.I0(_09406_),
+ .I1(_05789_),
+ .S(_09404_),
+ .Z(_09407_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_1 _21380_ (.I(_09407_),
+ .ZN(_09408_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _21381_ (.I0(_09407_),
+ .I1(_09400_),
+ .S(net779),
+ .Z(_00115_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _21382_ (.I0(\soc.core.VexRiscv.CsrPlugin_mepc[27] ),
+ .I1(\soc.core.VexRiscv.lastStagePc[27] ),
+ .S(net1297),
+ .Z(_09409_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _21383_ (.A1(\soc.core.VexRiscv.decode_to_execute_RS1[27] ),
+ .A2(net1623),
+ .ZN(_09410_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _21384_ (.A1(\soc.core.VexRiscv.CsrPlugin_selfException_payload_badAddr[27] ),
+ .A2(net1577),
+ .ZN(_09411_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__and2_4 _21385_ (.A1(_09410_),
+ .A2(_09411_),
+ .Z(_09412_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _21386_ (.A1(_09410_),
+ .A2(_09411_),
+ .ZN(_09413_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _21387_ (.A1(net1803),
+ .A2(\soc.core.VexRiscv.CsrPlugin_mtval[27] ),
+ .ZN(_09414_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi22_4 _21388_ (.A1(\soc.core.VexRiscv._zz_CsrPlugin_csrMapping_readDataInit[27] ),
+ .A2(net1799),
+ .B1(net1795),
+ .B2(\soc.core.VexRiscv.CsrPlugin_mepc[27] ),
+ .ZN(_09415_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _21389_ (.A1(_09415_),
+ .A2(_09414_),
+ .ZN(_09416_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _21390_ (.A1(_09416_),
+ .A2(net1776),
+ .ZN(_09417_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _21391_ (.I(_09417_),
+ .ZN(_09418_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _21392_ (.I0(_09418_),
+ .I1(_05789_),
+ .S(_09413_),
+ .Z(_09419_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_1 _21393_ (.I(_09419_),
+ .ZN(_09420_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _21394_ (.I0(_09419_),
+ .I1(_09409_),
+ .S(net779),
+ .Z(_00116_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _21395_ (.I0(\soc.core.VexRiscv.CsrPlugin_mepc[28] ),
+ .I1(\soc.core.VexRiscv.lastStagePc[28] ),
+ .S(net1297),
+ .Z(_09421_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _21396_ (.A1(\soc.core.VexRiscv.decode_to_execute_RS1[28] ),
+ .A2(net1623),
+ .ZN(_09422_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _21397_ (.A1(\soc.core.VexRiscv.CsrPlugin_selfException_payload_badAddr[28] ),
+ .A2(net1577),
+ .ZN(_09423_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__and2_4 _21398_ (.A1(_09422_),
+ .A2(_09423_),
+ .Z(_09424_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _21399_ (.A1(_09422_),
+ .A2(_09423_),
+ .ZN(_09425_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi222_4 _21400_ (.A1(\soc.core.VexRiscv._zz_CsrPlugin_csrMapping_readDataInit[28] ),
+ .A2(net1799),
+ .B1(net1795),
+ .B2(\soc.core.VexRiscv.CsrPlugin_mepc[28] ),
+ .C1(\soc.core.VexRiscv.CsrPlugin_mtval[28] ),
+ .C2(net1803),
+ .ZN(_09426_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _21401_ (.A1(_09426_),
+ .A2(_05239_),
+ .ZN(_09427_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _21402_ (.I0(_09427_),
+ .I1(_05789_),
+ .S(_09425_),
+ .Z(_09428_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_1 _21403_ (.I(_09428_),
+ .ZN(_09429_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _21404_ (.I0(_09428_),
+ .I1(_09421_),
+ .S(net779),
+ .Z(_00117_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _21405_ (.I0(\soc.core.VexRiscv.CsrPlugin_mepc[29] ),
+ .I1(\soc.core.VexRiscv.lastStagePc[29] ),
+ .S(net1297),
+ .Z(_09430_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai22_4 _21406_ (.A1(_05417_),
+ .A2(_05806_),
+ .B1(_09163_),
+ .B2(_05416_),
+ .ZN(_09431_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _21407_ (.A1(net1803),
+ .A2(\soc.core.VexRiscv.CsrPlugin_mtval[29] ),
+ .ZN(_09432_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi22_4 _21408_ (.A1(\soc.core.VexRiscv._zz_CsrPlugin_csrMapping_readDataInit[29] ),
+ .A2(net1799),
+ .B1(net1795),
+ .B2(\soc.core.VexRiscv.CsrPlugin_mepc[29] ),
+ .ZN(_09433_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _21409_ (.A1(_09433_),
+ .A2(_09432_),
+ .ZN(_09434_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _21410_ (.A1(_09434_),
+ .A2(net1776),
+ .ZN(_09435_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _21411_ (.I(_09435_),
+ .ZN(_09436_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _21412_ (.I0(_09436_),
+ .I1(_05789_),
+ .S(_09431_),
+ .Z(_09437_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_1 _21413_ (.I(_09437_),
+ .ZN(_09438_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _21414_ (.I0(_09437_),
+ .I1(_09430_),
+ .S(net777),
+ .Z(_00118_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _21415_ (.I0(\soc.core.VexRiscv.CsrPlugin_mepc[30] ),
+ .I1(\soc.core.VexRiscv.lastStagePc[30] ),
+ .S(net1297),
+ .Z(_09439_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai22_4 _21416_ (.A1(_05415_),
+ .A2(_05806_),
+ .B1(_09163_),
+ .B2(_05414_),
+ .ZN(_09440_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi222_4 _21417_ (.A1(\soc.core.VexRiscv._zz_CsrPlugin_csrMapping_readDataInit[30] ),
+ .A2(net1797),
+ .B1(net1795),
+ .B2(\soc.core.VexRiscv.CsrPlugin_mepc[30] ),
+ .C1(\soc.core.VexRiscv.CsrPlugin_mtval[30] ),
+ .C2(net1803),
+ .ZN(_09441_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _21418_ (.I(_09441_),
+ .ZN(_09442_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _21419_ (.A1(_09441_),
+ .A2(_05239_),
+ .ZN(_09443_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _21420_ (.I0(_09443_),
+ .I1(_05789_),
+ .S(_09440_),
+ .Z(_09444_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_1 _21421_ (.I(_09444_),
+ .ZN(_09445_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _21422_ (.I0(_09444_),
+ .I1(_09439_),
+ .S(net777),
+ .Z(_00120_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _21423_ (.I0(\soc.core.VexRiscv.CsrPlugin_mepc[31] ),
+ .I1(\soc.core.VexRiscv.lastStagePc[31] ),
+ .S(net1297),
+ .Z(_09446_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi22_4 _21424_ (.A1(\soc.core.VexRiscv.decode_to_execute_RS1[31] ),
+ .A2(net1623),
+ .B1(net1577),
+ .B2(net1770),
+ .ZN(_09447_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _21425_ (.A1(\soc.core.VexRiscv.execute_CsrPlugin_csr_834 ),
+ .A2(\soc.core.VexRiscv.CsrPlugin_mcause_interrupt ),
+ .ZN(_09448_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi222_4 _21426_ (.A1(\soc.core.VexRiscv._zz_CsrPlugin_csrMapping_readDataInit[31] ),
+ .A2(net1797),
+ .B1(net1795),
+ .B2(\soc.core.VexRiscv.CsrPlugin_mepc[31] ),
+ .C1(\soc.core.VexRiscv.CsrPlugin_mtval[31] ),
+ .C2(net1803),
+ .ZN(_09449_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _21427_ (.A1(_09449_),
+ .A2(_09448_),
+ .ZN(_09450_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _21428_ (.A1(_09450_),
+ .A2(net1776),
+ .ZN(_09451_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _21429_ (.I(_09451_),
+ .ZN(_09452_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _21430_ (.I0(net1629),
+ .I1(_09452_),
+ .S(_09447_),
+ .Z(_09453_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_1 _21431_ (.I(_09453_),
+ .ZN(_09454_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _21432_ (.I0(_09453_),
+ .I1(_09446_),
+ .S(net777),
+ .Z(_00121_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _21433_ (.A1(\clock_ctrl.divider2.even_0.N[2] ),
+ .A2(\clock_ctrl.divider2.even_0.N[1] ),
+ .ZN(_09455_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_4 _21434_ (.A1(_05223_),
+ .A2(_05224_),
+ .ZN(_09456_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_4 _21435_ (.A1(_09455_),
+ .A2(_05225_),
+ .ZN(_09457_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_4 _21436_ (.A1(_09456_),
+ .A2(\clock_ctrl.divider2.even_0.N[0] ),
+ .ZN(_09458_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__xnor2_1 _21437_ (.A1(\clock_ctrl.divider2.odd_0.out_counter ),
+ .A2(\clock_ctrl.divider2.odd_0.out_counter2 ),
+ .ZN(_09459_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _21438_ (.A1(\clock_ctrl.divider2.even_0.out_counter ),
+ .A2(_09455_),
+ .ZN(_09460_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _21439_ (.A1(_09456_),
+ .A2(net1913),
+ .ZN(_09461_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai32_4 _21440_ (.A1(\clock_ctrl.divider2.even_0.N[0] ),
+ .A2(_09460_),
+ .A3(_09461_),
+ .B1(_09458_),
+ .B2(_09459_),
+ .ZN(\clock_ctrl.divider2.out ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _21441_ (.A1(_05479_),
+ .A2(\clock_ctrl.use_pll_first ),
+ .ZN(_09462_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _21442_ (.A1(net2129),
+ .A2(\clock_ctrl.use_pll_first ),
+ .B(_05480_),
+ .C(_09462_),
+ .ZN(_09463_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _21443_ (.A1(\clock_ctrl.divider2.out ),
+ .A2(\clock_ctrl.use_pll_second ),
+ .ZN(_09464_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_4 _21444_ (.A1(_09463_),
+ .A2(_09464_),
+ .ZN(\clock_ctrl.user_clk ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _21445_ (.A1(\clock_ctrl.divider.even_0.N[2] ),
+ .A2(\clock_ctrl.divider.even_0.N[1] ),
+ .ZN(_09465_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _21446_ (.A1(_05220_),
+ .A2(_05221_),
+ .ZN(_09466_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _21447_ (.A1(\clock_ctrl.divider.even_0.out_counter ),
+ .A2(_09465_),
+ .ZN(_09467_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _21448_ (.A1(_09466_),
+ .A2(net1912),
+ .ZN(_09468_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_4 _21449_ (.A1(_09465_),
+ .A2(_05222_),
+ .ZN(_09469_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_4 _21450_ (.A1(_09466_),
+ .A2(\clock_ctrl.divider.even_0.N[0] ),
+ .ZN(_09470_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__xnor2_1 _21451_ (.A1(\clock_ctrl.divider.odd_0.out_counter ),
+ .A2(\clock_ctrl.divider.odd_0.out_counter2 ),
+ .ZN(_09471_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai32_4 _21452_ (.A1(\clock_ctrl.divider.even_0.N[0] ),
+ .A2(_09467_),
+ .A3(_09468_),
+ .B1(_09470_),
+ .B2(_09471_),
+ .ZN(\clock_ctrl.divider.out ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _21453_ (.A1(\clock_ctrl.divider.out ),
+ .A2(\clock_ctrl.use_pll_second ),
+ .ZN(_09472_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _21454_ (.A1(_09463_),
+ .A2(_09472_),
+ .ZN(\clock_ctrl.core_clk ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _21455_ (.I0(_05683_),
+ .I1(\pll.ext_trim[0] ),
+ .S(net2195),
+ .Z(\pll.itrim[0] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _21456_ (.A1(net2195),
+ .A2(\pll.ext_trim[1] ),
+ .ZN(_09473_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _21457_ (.A1(_05213_),
+ .A2(\pll.pll_control.tint[3] ),
+ .ZN(_09474_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_4 _21458_ (.A1(_05212_),
+ .A2(\pll.pll_control.tint[2] ),
+ .ZN(_09475_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_4 _21459_ (.A1(_05214_),
+ .A2(_05215_),
+ .ZN(_09476_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_4 _21460_ (.A1(\pll.pll_control.tint[1] ),
+ .A2(\pll.pll_control.tint[0] ),
+ .ZN(_09477_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi22_4 _21461_ (.A1(_05621_),
+ .A2(_09474_),
+ .B1(_09476_),
+ .B2(_05619_),
+ .ZN(_09478_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _21462_ (.A1(\pll.pll_control.tint[4] ),
+ .A2(_09478_),
+ .ZN(_09479_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _21463_ (.A1(_05681_),
+ .A2(_09477_),
+ .ZN(_09480_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_4 _21464_ (.A1(_05215_),
+ .A2(\pll.pll_control.tint[1] ),
+ .ZN(_09481_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _21465_ (.A1(_05481_),
+ .A2(_09480_),
+ .ZN(_09482_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _21466_ (.A1(_09482_),
+ .A2(_09479_),
+ .ZN(_09483_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _21467_ (.A1(\pll.pll_control.tint[4] ),
+ .A2(_09478_),
+ .B(_09480_),
+ .C(_05481_),
+ .ZN(_09484_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_4 _21468_ (.A1(_09475_),
+ .A2(\pll.pll_control.tint[4] ),
+ .ZN(_09485_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__and3_4 _21469_ (.A1(_09485_),
+ .A2(_09477_),
+ .A3(_05622_),
+ .Z(_09486_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_4 _21470_ (.A1(_09484_),
+ .A2(_09486_),
+ .ZN(_09487_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_4 _21471_ (.A1(_05213_),
+ .A2(\pll.pll_control.tint[3] ),
+ .ZN(_09488_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_4 _21472_ (.A1(_09488_),
+ .A2(\pll.pll_control.tint[4] ),
+ .ZN(_09489_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__or2_4 _21473_ (.A1(_09488_),
+ .A2(\pll.pll_control.tint[4] ),
+ .Z(_09490_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_4 _21474_ (.A1(_09476_),
+ .A2(_09485_),
+ .ZN(_09491_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _21475_ (.A1(_09490_),
+ .A2(_09491_),
+ .ZN(_09492_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _21476_ (.I(_09492_),
+ .ZN(_09493_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _21477_ (.A1(_09481_),
+ .A2(_09485_),
+ .ZN(_09494_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_4 _21478_ (.A1(_09483_),
+ .A2(_09494_),
+ .ZN(_09495_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _21479_ (.A1(_09487_),
+ .A2(_09493_),
+ .ZN(_09496_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _21480_ (.A1(_09473_),
+ .A2(_09496_),
+ .ZN(\pll.itrim[1] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi21_4 _21481_ (.A1(_05622_),
+ .A2(_09485_),
+ .B(_09484_),
+ .ZN(_09497_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi21_4 _21482_ (.A1(net2195),
+ .A2(\pll.ext_trim[2] ),
+ .B(_09497_),
+ .ZN(_09498_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _21483_ (.I(_09498_),
+ .ZN(\pll.itrim[2] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _21484_ (.I0(_05682_),
+ .I1(\pll.ext_trim[3] ),
+ .S(net2194),
+ .Z(\pll.itrim[3] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _21485_ (.A1(net2195),
+ .A2(\pll.ext_trim[4] ),
+ .ZN(_09499_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _21486_ (.A1(_09490_),
+ .A2(\pll.pll_control.tint[1] ),
+ .ZN(_09500_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _21487_ (.A1(\pll.pll_control.tint[1] ),
+ .A2(_09490_),
+ .B(_09487_),
+ .C(_09491_),
+ .ZN(_09501_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _21488_ (.A1(_09499_),
+ .A2(_09501_),
+ .ZN(\pll.itrim[4] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi21_4 _21489_ (.A1(net2194),
+ .A2(\pll.ext_trim[5] ),
+ .B(_09487_),
+ .ZN(_09502_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _21490_ (.I(_09502_),
+ .ZN(\pll.itrim[5] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _21491_ (.A1(\pll.pll_control.tint[1] ),
+ .A2(net2194),
+ .ZN(_09503_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi22_4 _21492_ (.A1(_05681_),
+ .A2(_09503_),
+ .B1(net2194),
+ .B2(_05482_),
+ .ZN(\pll.itrim[6] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _21493_ (.A1(net2194),
+ .A2(\pll.ext_trim[7] ),
+ .ZN(_09504_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_4 _21494_ (.A1(_05673_),
+ .A2(\pll.pll_control.tint[4] ),
+ .ZN(_09505_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_4 _21495_ (.I(_09505_),
+ .ZN(_09506_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _21496_ (.A1(_09489_),
+ .A2(_09477_),
+ .ZN(_09507_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _21497_ (.A1(_05622_),
+ .A2(_09506_),
+ .B1(_09475_),
+ .B2(\pll.pll_control.tint[4] ),
+ .C(_09490_),
+ .ZN(_09508_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai31_4 _21498_ (.A1(_09508_),
+ .A2(_05681_),
+ .A3(net2194),
+ .B(_09504_),
+ .ZN(\pll.itrim[7] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _21499_ (.A1(\pll.dco ),
+ .A2(\pll.ext_trim[8] ),
+ .ZN(_09509_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _21500_ (.A1(_09484_),
+ .A2(_09509_),
+ .ZN(\pll.itrim[8] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _21501_ (.A1(\pll.dco ),
+ .A2(\pll.ext_trim[9] ),
+ .ZN(_09510_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _21502_ (.A1(_05622_),
+ .A2(_09490_),
+ .B(_09487_),
+ .C(_09491_),
+ .ZN(_09511_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _21503_ (.A1(_09510_),
+ .A2(_09511_),
+ .ZN(\pll.itrim[9] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _21504_ (.I0(_09480_),
+ .I1(\pll.ext_trim[10] ),
+ .S(net2194),
+ .Z(\pll.itrim[10] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi22_4 _21505_ (.A1(_09497_),
+ .A2(_09507_),
+ .B1(net2195),
+ .B2(\pll.ext_trim[11] ),
+ .ZN(_09512_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _21506_ (.I(_09512_),
+ .ZN(\pll.itrim[11] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _21507_ (.A1(net2194),
+ .A2(\pll.ext_trim[12] ),
+ .ZN(_09513_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _21508_ (.A1(_09495_),
+ .A2(_09513_),
+ .ZN(\pll.itrim[12] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _21509_ (.A1(net2195),
+ .A2(\pll.ext_trim[13] ),
+ .ZN(_09514_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _21510_ (.A1(\pll.pll_control.tint[1] ),
+ .A2(_09506_),
+ .B(_09497_),
+ .C(_09490_),
+ .ZN(_09515_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _21511_ (.A1(_09514_),
+ .A2(_09515_),
+ .ZN(\pll.itrim[13] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_4 _21512_ (.A1(_05211_),
+ .A2(_05620_),
+ .ZN(_09516_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_4 _21513_ (.A1(\pll.pll_control.tint[4] ),
+ .A2(_05619_),
+ .ZN(_09517_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi22_4 _21514_ (.A1(_09476_),
+ .A2(_09505_),
+ .B1(_09516_),
+ .B2(_05621_),
+ .ZN(_09518_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai22_4 _21515_ (.A1(_09477_),
+ .A2(_09506_),
+ .B1(_09517_),
+ .B2(_05622_),
+ .ZN(_09519_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_4 _21516_ (.A1(_09505_),
+ .A2(_09477_),
+ .ZN(_09520_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi21_4 _21517_ (.A1(_05621_),
+ .A2(_09516_),
+ .B(_09505_),
+ .ZN(_09521_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__inv_1 _21518_ (.I(_09521_),
+ .ZN(_09522_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _21519_ (.A1(_09487_),
+ .A2(_09521_),
+ .ZN(_09523_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _21520_ (.A1(_05211_),
+ .A2(_09475_),
+ .ZN(_09524_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _21521_ (.A1(\pll.pll_control.tint[4] ),
+ .A2(_09474_),
+ .ZN(_09525_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_4 _21522_ (.A1(_05622_),
+ .A2(_09488_),
+ .B1(_09517_),
+ .B2(_05214_),
+ .C(_09525_),
+ .ZN(_09526_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _21523_ (.A1(_09481_),
+ .A2(_09516_),
+ .ZN(_09527_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _21524_ (.A1(_09475_),
+ .A2(_09477_),
+ .B(_09490_),
+ .C(_09527_),
+ .ZN(_09528_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _21525_ (.I0(_09525_),
+ .I1(_09517_),
+ .S(\pll.pll_control.tint[1] ),
+ .Z(_09529_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_4 _21526_ (.A1(_05672_),
+ .A2(_09475_),
+ .ZN(_09530_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai32_4 _21527_ (.A1(_09523_),
+ .A2(_09526_),
+ .A3(_09528_),
+ .B1(_05483_),
+ .B2(_05481_),
+ .ZN(\pll.itrim[14] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai32_4 _21528_ (.A1(_05621_),
+ .A2(_09476_),
+ .A3(_09517_),
+ .B1(_09478_),
+ .B2(_05211_),
+ .ZN(_09531_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai32_4 _21529_ (.A1(_09492_),
+ .A2(_09523_),
+ .A3(_09531_),
+ .B1(_05484_),
+ .B2(_05481_),
+ .ZN(\pll.itrim[15] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _21530_ (.A1(\pll.pll_control.tint[4] ),
+ .A2(_09488_),
+ .B(_09497_),
+ .C(_09520_),
+ .ZN(_09532_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai22_4 _21531_ (.A1(_05481_),
+ .A2(_05485_),
+ .B1(_09519_),
+ .B2(_09532_),
+ .ZN(\pll.itrim[16] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_4 _21532_ (.A1(_09485_),
+ .A2(_09516_),
+ .B(\pll.pll_control.tint[1] ),
+ .ZN(_09533_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi221_4 _21533_ (.A1(_09481_),
+ .A2(_09516_),
+ .B1(_09524_),
+ .B2(_09477_),
+ .C(_09489_),
+ .ZN(_09534_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _21534_ (.A1(_09533_),
+ .A2(_09534_),
+ .ZN(_09535_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai32_4 _21535_ (.A1(_09495_),
+ .A2(_09522_),
+ .A3(_09535_),
+ .B1(_05486_),
+ .B2(_05481_),
+ .ZN(\pll.itrim[17] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _21536_ (.A1(_09518_),
+ .A2(_09527_),
+ .ZN(_09536_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _21537_ (.A1(\pll.pll_control.tint[4] ),
+ .A2(_09488_),
+ .B(_09533_),
+ .C(_09520_),
+ .ZN(_09537_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai32_4 _21538_ (.A1(_09495_),
+ .A2(_09536_),
+ .A3(_09537_),
+ .B1(_05487_),
+ .B2(_05481_),
+ .ZN(\pll.itrim[18] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _21539_ (.A1(net2194),
+ .A2(\pll.ext_trim[19] ),
+ .ZN(_09538_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _21540_ (.A1(_09532_),
+ .A2(_09538_),
+ .ZN(\pll.itrim[19] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__and3_4 _21541_ (.A1(_09518_),
+ .A2(_09529_),
+ .A3(_09527_),
+ .Z(_09539_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai31_4 _21542_ (.A1(_05211_),
+ .A2(\pll.pll_control.tint[1] ),
+ .A3(_09488_),
+ .B(_09539_),
+ .ZN(_09540_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai32_4 _21543_ (.A1(_09532_),
+ .A2(_09540_),
+ .A3(_09530_),
+ .B1(_05488_),
+ .B2(_05481_),
+ .ZN(\pll.itrim[20] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__and2_4 _21544_ (.A1(net2194),
+ .A2(\pll.ext_trim[21] ),
+ .Z(_09541_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi211_4 _21545_ (.A1(_09505_),
+ .A2(_09477_),
+ .B(_09496_),
+ .C(_09536_),
+ .ZN(_09542_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__or2_4 _21546_ (.A1(_09541_),
+ .A2(_09542_),
+ .Z(\pll.itrim[21] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi22_4 _21547_ (.A1(net2194),
+ .A2(\pll.ext_trim[22] ),
+ .B1(_09529_),
+ .B2(_09542_),
+ .ZN(_09543_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _21548_ (.I(_09543_),
+ .ZN(\pll.itrim[22] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _21549_ (.I0(\pll.pll_control.tint[4] ),
+ .I1(\pll.ext_trim[23] ),
+ .S(net2194),
+ .Z(\pll.itrim[23] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi211_4 _21550_ (.A1(_09485_),
+ .A2(_05622_),
+ .B(_09530_),
+ .C(_09489_),
+ .ZN(_09544_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__and3_4 _21551_ (.A1(_09483_),
+ .A2(_09539_),
+ .A3(_09544_),
+ .Z(_09545_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi22_4 _21552_ (.A1(_09545_),
+ .A2(_09520_),
+ .B1(\pll.ext_trim[24] ),
+ .B2(net2194),
+ .ZN(_09546_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _21553_ (.I(_09546_),
+ .ZN(\pll.itrim[24] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__aoi221_4 _21554_ (.A1(_05622_),
+ .A2(_09485_),
+ .B1(_09489_),
+ .B2(\pll.pll_control.tint[1] ),
+ .C(_09519_),
+ .ZN(_09547_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _21555_ (.A1(_09505_),
+ .A2(_09516_),
+ .B(_05622_),
+ .C(_09477_),
+ .ZN(_09548_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _21556_ (.A1(_05622_),
+ .A2(_09506_),
+ .B(_09547_),
+ .C(_09548_),
+ .ZN(_09549_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__oai32_4 _21557_ (.A1(_09484_),
+ .A2(_09549_),
+ .A3(_09500_),
+ .B1(_05481_),
+ .B2(_05489_),
+ .ZN(\pll.itrim[25] ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _21558_ (.I0(net2183),
+ .I1(\mgmt_io_out_hk[0] ),
+ .S(\gpio_control_bidir_1[0].mgmt_ena ),
+ .Z(\gpio_control_bidir_1[0].pad_gpio_out ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _21559_ (.I0(net2193),
+ .I1(\gpio_control_bidir_1[0].mgmt_gpio_oeb ),
+ .S(\gpio_control_bidir_1[0].mgmt_ena ),
+ .Z(_09550_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _21560_ (.I(_09550_),
+ .ZN(_09551_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _21561_ (.I0(_09551_),
+ .I1(\gpio_control_bidir_1[0].gpio_outen ),
+ .S(\gpio_control_bidir_1[0].gpio_oe_override ),
+ .Z(\gpio_control_bidir_1[0].pad_gpio_outen ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _21562_ (.I0(net2182),
+ .I1(\mgmt_io_out_hk[1] ),
+ .S(\gpio_control_bidir_1[1].mgmt_ena ),
+ .Z(\gpio_control_bidir_1[1].pad_gpio_out ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _21563_ (.I0(net2192),
+ .I1(\gpio_control_bidir_1[1].mgmt_gpio_oeb ),
+ .S(\gpio_control_bidir_1[1].mgmt_ena ),
+ .Z(_09552_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _21564_ (.I(_09552_),
+ .ZN(_09553_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _21565_ (.I0(_09553_),
+ .I1(\gpio_control_bidir_1[1].gpio_outen ),
+ .S(\gpio_control_bidir_1[1].gpio_oe_override ),
+ .Z(\gpio_control_bidir_1[1].pad_gpio_outen ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _21566_ (.I0(net2181),
+ .I1(\mgmt_io_out_hk[2] ),
+ .S(\gpio_control_in_1a[0].mgmt_ena ),
+ .Z(\gpio_control_in_1a[0].pad_gpio_out ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _21567_ (.I0(net2191),
+ .I1(net2318),
+ .S(\gpio_control_in_1a[0].mgmt_ena ),
+ .Z(_09554_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _21568_ (.I(_09554_),
+ .ZN(_09555_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _21569_ (.I0(_09555_),
+ .I1(\gpio_control_in_1a[0].gpio_outen ),
+ .S(\gpio_control_in_1a[0].gpio_oe_override ),
+ .Z(\gpio_control_in_1a[0].pad_gpio_outen ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _21570_ (.I0(net2176),
+ .I1(\mgmt_io_out_hk[3] ),
+ .S(\gpio_control_in_1a[1].mgmt_ena ),
+ .Z(\gpio_control_in_1a[1].pad_gpio_out ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _21571_ (.I0(net2187),
+ .I1(net2319),
+ .S(\gpio_control_in_1a[1].mgmt_ena ),
+ .Z(_09556_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _21572_ (.I(_09556_),
+ .ZN(_09557_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _21573_ (.I0(_09557_),
+ .I1(\gpio_control_in_1a[1].gpio_outen ),
+ .S(\gpio_control_in_1a[1].gpio_oe_override ),
+ .Z(\gpio_control_in_1a[1].pad_gpio_outen ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _21574_ (.I0(net2175),
+ .I1(\mgmt_io_out_hk[4] ),
+ .S(\gpio_control_in_1a[2].mgmt_ena ),
+ .Z(\gpio_control_in_1a[2].pad_gpio_out ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _21575_ (.I0(net2186),
+ .I1(net2320),
+ .S(\gpio_control_in_1a[2].mgmt_ena ),
+ .Z(_09558_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _21576_ (.I(_09558_),
+ .ZN(_09559_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _21577_ (.I0(_09559_),
+ .I1(\gpio_control_in_1a[2].gpio_outen ),
+ .S(\gpio_control_in_1a[2].gpio_oe_override ),
+ .Z(\gpio_control_in_1a[2].pad_gpio_outen ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _21578_ (.I0(net2174),
+ .I1(\mgmt_io_out_hk[5] ),
+ .S(\gpio_control_in_1a[3].mgmt_ena ),
+ .Z(\gpio_control_in_1a[3].pad_gpio_out ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _21579_ (.I0(net2185),
+ .I1(net2321),
+ .S(\gpio_control_in_1a[3].mgmt_ena ),
+ .Z(_09560_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _21580_ (.I(_09560_),
+ .ZN(_09561_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _21581_ (.I0(_09561_),
+ .I1(\gpio_control_in_1a[3].gpio_outen ),
+ .S(\gpio_control_in_1a[3].gpio_oe_override ),
+ .Z(\gpio_control_in_1a[3].pad_gpio_outen ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _21582_ (.I0(net2173),
+ .I1(net1171),
+ .S(\gpio_control_in_1a[4].mgmt_ena ),
+ .Z(\gpio_control_in_1a[4].pad_gpio_out ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _21583_ (.I0(net2184),
+ .I1(net2322),
+ .S(\gpio_control_in_1a[4].mgmt_ena ),
+ .Z(_09562_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _21584_ (.I(_09562_),
+ .ZN(_09563_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _21585_ (.I0(_09563_),
+ .I1(\gpio_control_in_1a[4].gpio_outen ),
+ .S(\gpio_control_in_1a[4].gpio_oe_override ),
+ .Z(\gpio_control_in_1a[4].pad_gpio_outen ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _21586_ (.I0(\user_io_out[7] ),
+ .I1(net2199),
+ .S(\gpio_control_in_1a[5].mgmt_ena ),
+ .Z(\gpio_control_in_1a[5].pad_gpio_out ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _21587_ (.I0(\user_io_oeb[7] ),
+ .I1(net2323),
+ .S(\gpio_control_in_1a[5].mgmt_ena ),
+ .Z(_09564_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _21588_ (.I(_09564_),
+ .ZN(_09565_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _21589_ (.I0(_09565_),
+ .I1(\gpio_control_in_1a[5].gpio_outen ),
+ .S(\gpio_control_in_1a[5].gpio_oe_override ),
+ .Z(\gpio_control_in_1a[5].pad_gpio_outen ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _21590_ (.I0(\user_io_out[8] ),
+ .I1(net1920),
+ .S(\gpio_control_in_1[0].mgmt_ena ),
+ .Z(\gpio_control_in_1[0].pad_gpio_out ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _21591_ (.I0(\user_io_oeb[8] ),
+ .I1(net2307),
+ .S(\gpio_control_in_1[0].mgmt_ena ),
+ .Z(_09566_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _21592_ (.I(_09566_),
+ .ZN(_09567_),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _21593_ (.I0(_09567_),
+ .I1(\gpio_control_in_1[0].gpio_outen ),
+ .S(\gpio_control_in_1[0].gpio_oe_override ),
+ .Z(\gpio_control_in_1[0].pad_gpio_outen ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _21594_ (.I0(\user_io_out[9] ),
+ .I1(net2196),
+ .S(\gpio_control_in_1[1].mgmt_ena ),
+ .Z(\gpio_control_in_1[1].pad_gpio_out ),
+ .VDD(VDD),
+ .VNW(VDD),
+ .VPW(VSS),
+ .VSS(VSS));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_4 _21595_ (.I0(\user_io_oeb[9] ),
+ .I1(net2309),
