| 2022-12-05 17:51:19 - [INFO] - {{Project Git Info}} Repository: https://github.com/egorxe/ophelia_fpga_openmpw.git | Branch: main | Commit: 4b407974710e71322cb6270d812c2b44b3e13cbb |
| 2022-12-05 17:51:19 - [INFO] - {{EXTRACTING FILES}} Extracting compressed files in: ophelia_efpga |
| 2022-12-05 17:51:20 - [INFO] - {{Project Type Info}} digital |
| 2022-12-05 17:51:20 - [INFO] - {{Project GDS Info}} user_project_wrapper: a5b78e1dee205485a829ba28cdd3753d8636ecf7 |
| 2022-12-05 17:51:21 - [INFO] - {{Tools Info}} KLayout: v0.27.12 | Magic: v8.3.340 |
| 2022-12-05 17:51:21 - [INFO] - {{PDKs Info}} GF180MCUC: a897aa30369d3bcec87d9d50ce9b01f320f854ef | Open PDKs: 120b0bd69c745825a0b8b76f364043a1cd08bb6a |
| 2022-12-05 17:51:21 - [INFO] - {{START}} Precheck Started, the full log 'precheck.log' will be located in 'ophelia_efpga/jobs/mpw_precheck/e91b7603-4cb2-40d3-9c9d-39f7dcd32d80/logs' |
| 2022-12-05 17:51:21 - [INFO] - {{PRECHECK SEQUENCE}} Precheck will run the following checks: [License, GPIO-Defines, XOR, Klayout FEOL, Klayout BEOL, Klayout Offgrid, Klayout Metal Minimum Clear Area Density] |
| 2022-12-05 17:51:21 - [INFO] - {{STEP UPDATE}} Executing Check 1 of 7: License |
| 2022-12-05 17:51:22 - [INFO] - An approved LICENSE (Apache-2.0) was found in ophelia_efpga. |
| 2022-12-05 17:51:22 - [INFO] - {{MAIN LICENSE CHECK PASSED}} An approved LICENSE was found in project root. |
| 2022-12-05 17:51:22 - [INFO] - An approved LICENSE (Apache-2.0) was found in ophelia_efpga. |
| 2022-12-05 17:51:22 - [INFO] - {{SUBMODULES LICENSE CHECK PASSED}} No prohibited LICENSE file(s) was found in project submodules |
| 2022-12-05 17:51:23 - [WARNING] - {{SPDX COMPLIANCE CHECK FAILED}} Found 16 non-compliant file(s) with the SPDX Standard. |
| 2022-12-05 17:51:23 - [INFO] - SPDX COMPLIANCE: NON-COMPLIANT FILE(S) PREVIEW: ['ophelia_efpga/openlane/config.tcl', 'ophelia_efpga/openlane/user_project_wrapper.sdc', 'ophelia_efpga/openlane/efuse_ctrl/config.tcl', 'ophelia_efpga/openlane/fpga_struct_block/config.tcl', 'ophelia_efpga/openlane/fpga_struct_block/fpga_struct_block.sdc', 'ophelia_efpga/sdf/efuse_ctrl.sdf', 'ophelia_efpga/sdf/fpga_struct_block.sdf', 'ophelia_efpga/sdf/user_project_wrapper.sdf', 'ophelia_efpga/verilog/includes/includes.gl+sdf.caravel_user_project', 'ophelia_efpga/verilog/includes/includes.gl.caravel_user_project', 'ophelia_efpga/verilog/includes/includes.rtl.caravel_user_project', 'ophelia_efpga/verilog/rtl/ariel_fpga_top_fromvhdl.v', 'ophelia_efpga/verilog/rtl/fpga_tech.v', 'ophelia_efpga/verilog/rtl/efuse_ctrl/efuse_array_fromvhdl.v', 'ophelia_efpga/verilog/rtl/fpga_struct_block/fpga_struct_block_fromvhdl.v'] |
| 2022-12-05 17:51:23 - [INFO] - For the full SPDX compliance report check: ophelia_efpga/jobs/mpw_precheck/e91b7603-4cb2-40d3-9c9d-39f7dcd32d80/logs/spdx_compliance_report.log |
| 2022-12-05 17:51:23 - [INFO] - {{STEP UPDATE}} Executing Check 2 of 7: GPIO-Defines |
| 2022-12-05 17:51:23 - [INFO] - GPIO-DEFINES: Checking verilog/rtl/user_defines.v, parsing files: ['/opt/checks/gpio_defines_check/verilog_assets/gpio_modes_base.v', 'ophelia_efpga/verilog/rtl/user_defines.v', '/opt/checks/gpio_defines_check/verilog_assets/gpio_modes_observe.v'] |
| 2022-12-05 17:51:24 - [INFO] - GPIO-DEFINES report path: ophelia_efpga/jobs/mpw_precheck/e91b7603-4cb2-40d3-9c9d-39f7dcd32d80/outputs/reports/gpio_defines.report |
| 2022-12-05 17:51:24 - [INFO] - {{GPIO-DEFINES CHECK PASSED}} The user verilog/rtl/user_defines.v is valid. |
| 2022-12-05 17:51:24 - [INFO] - {{STEP UPDATE}} Executing Check 3 of 7: XOR |
| 2022-12-05 17:52:11 - [INFO] - {{XOR CHECK UPDATE}} Total XOR differences: 0, for more details view ophelia_efpga/jobs/mpw_precheck/e91b7603-4cb2-40d3-9c9d-39f7dcd32d80/outputs/user_project_wrapper.xor.gds |
| 2022-12-05 17:52:11 - [INFO] - {{XOR CHECK PASSED}} The GDS file has no XOR violations. |
| 2022-12-05 17:52:11 - [INFO] - {{STEP UPDATE}} Executing Check 4 of 7: Klayout FEOL |
| 2022-12-05 17:52:11 - [INFO] - in CUSTOM klayout_gds_drc_check |
| 2022-12-05 17:52:11 - [INFO] - run: klayout -b -r /opt/checks/tech-files/gf180mcuC_mr.drc -rd input=ophelia_efpga/gds/user_project_wrapper.gds -rd topcell=user_project_wrapper -rd report=ophelia_efpga/jobs/mpw_precheck/e91b7603-4cb2-40d3-9c9d-39f7dcd32d80/outputs/reports/klayout_feol_check.xml -rd feol=true -rd metal_top=9K -rd mim_option=B -rd metal_level=5LM -rd conn_drc=true >& ophelia_efpga/jobs/mpw_precheck/e91b7603-4cb2-40d3-9c9d-39f7dcd32d80/logs/klayout_feol_check.log |
| 2022-12-05 18:58:03 - [ERROR] - ERROR klayout_feol FAILED, stat=-9, see ophelia_efpga/jobs/mpw_precheck/e91b7603-4cb2-40d3-9c9d-39f7dcd32d80/logs/klayout_feol_check.log |
| 2022-12-05 18:58:03 - [WARNING] - {{Klayout FEOL CHECK FAILED}} The GDS file, user_project_wrapper.gds, has DRC violations. |
| 2022-12-05 18:58:03 - [INFO] - {{STEP UPDATE}} Executing Check 5 of 7: Klayout BEOL |
| 2022-12-05 18:58:03 - [INFO] - in CUSTOM klayout_gds_drc_check |
| 2022-12-05 18:58:03 - [INFO] - run: klayout -b -r /opt/checks/tech-files/gf180mcuC_mr.drc -rd input=ophelia_efpga/gds/user_project_wrapper.gds -rd topcell=user_project_wrapper -rd report=ophelia_efpga/jobs/mpw_precheck/e91b7603-4cb2-40d3-9c9d-39f7dcd32d80/outputs/reports/klayout_beol_check.xml -rd beol=true -rd metal_top=9K -rd mim_option=B -rd metal_level=5LM -rd conn_drc=true >& ophelia_efpga/jobs/mpw_precheck/e91b7603-4cb2-40d3-9c9d-39f7dcd32d80/logs/klayout_beol_check.log |
| 2022-12-05 23:10:11 - [INFO] - No DRC Violations found |
| 2022-12-05 23:10:11 - [INFO] - {{Klayout BEOL CHECK PASSED}} The GDS file, user_project_wrapper.gds, has no DRC violations. |
| 2022-12-05 23:10:11 - [INFO] - {{STEP UPDATE}} Executing Check 6 of 7: Klayout Offgrid |
| 2022-12-05 23:10:11 - [INFO] - in CUSTOM klayout_gds_drc_check |
| 2022-12-05 23:10:11 - [INFO] - run: klayout -b -r /opt/checks/tech-files/gf180mcuC_mr.drc -rd input=ophelia_efpga/gds/user_project_wrapper.gds -rd topcell=user_project_wrapper -rd report=ophelia_efpga/jobs/mpw_precheck/e91b7603-4cb2-40d3-9c9d-39f7dcd32d80/outputs/reports/klayout_offgrid_check.xml -rd offgrid=true -rd metal_top=9K -rd mim_option=B -rd metal_level=5LM -rd conn_drc=true >& ophelia_efpga/jobs/mpw_precheck/e91b7603-4cb2-40d3-9c9d-39f7dcd32d80/logs/klayout_offgrid_check.log |
| 2022-12-06 03:09:42 - [INFO] - No DRC Violations found |
| 2022-12-06 03:09:42 - [INFO] - {{Klayout Offgrid CHECK PASSED}} The GDS file, user_project_wrapper.gds, has no DRC violations. |
| 2022-12-06 03:09:42 - [INFO] - {{STEP UPDATE}} Executing Check 7 of 7: Klayout Metal Minimum Clear Area Density |
| 2022-12-06 03:09:42 - [INFO] - in CUSTOM klayout_gds_drc_check |
| 2022-12-06 03:09:42 - [INFO] - run: klayout -b -r /opt/checks/drc_checks/klayout/gf180mcu_density.lydrc -rd input=ophelia_efpga/gds/user_project_wrapper.gds -rd topcell=user_project_wrapper -rd report=ophelia_efpga/jobs/mpw_precheck/e91b7603-4cb2-40d3-9c9d-39f7dcd32d80/outputs/reports/klayout_met_min_ca_density_check.xml >& ophelia_efpga/jobs/mpw_precheck/e91b7603-4cb2-40d3-9c9d-39f7dcd32d80/logs/klayout_met_min_ca_density_check.log |
| 2022-12-06 03:09:46 - [INFO] - No DRC Violations found |
| 2022-12-06 03:09:46 - [INFO] - {{Klayout Metal Minimum Clear Area Density CHECK PASSED}} The GDS file, user_project_wrapper.gds, has no DRC violations. |
| 2022-12-06 03:09:46 - [INFO] - {{FINISH}} Executing Finished, the full log 'precheck.log' can be found in 'ophelia_efpga/jobs/mpw_precheck/e91b7603-4cb2-40d3-9c9d-39f7dcd32d80/logs' |
| 2022-12-06 03:09:46 - [CRITICAL] - {{FAILURE}} 1 Check(s) Failed: ['Klayout FEOL'] !!! |
