| commit | 4b407974710e71322cb6270d812c2b44b3e13cbb | [log] [tgz] |
|---|---|---|
| author | egorxe <13577050+egorxe@users.noreply.github.com> | Mon Dec 05 23:36:06 2022 +0600 |
| committer | egorxe <13577050+egorxe@users.noreply.github.com> | Mon Dec 05 23:36:06 2022 +0600 |
| tree | cff576e861ed47f64397dee9377f52935757a05d | |
| parent | 4959273cd86fa77017ad71832a5989283bb63808 [diff] |
Fixed errors found during gatelevel simulation. Updated GDS.
Ophelia is a test project implementing open-source Uranus eFPGA fabric for OpenMPW-GF0 using open source GF180 PDK and OpenLane flow. FPGA contains 112 4-input LUTs and uses Wishbone bus from Caravel test harness for bitstream loading. Project also contains eFuse array for nonvolatile FPGA config storage.
Project is implemented for Skywater 130nm ASIC technology using OpenLane open source flow. Synthesis is done in two steps: first Yosys+GHDL are used for VHDL to Verilog translation, and then resulting Verilog source is synthesized by Yosys inside OpenLane flow.
Uranus FPGA uses opensource flow for FPGA bitstream generation. Yosys (with optional GHDL frontend for VHDL) is used for synthesis and VPR for place and route. Flow glue and bitstream generation is done by custom Python scripts.
This repository contains mainly implementation products (GDS/netlists/etc) needed for OpenMPW and test Caravel programs. VHDL sources of Uranus FPGA fabric, FPGA flow, tests and simulation scripts are stored in main Uranus repository.
Documentation is avaliable in main Uranus repository.