First commit for precheck
diff --git a/Makefile b/Makefile
new file mode 100644
index 0000000..06e4255
--- /dev/null
+++ b/Makefile
@@ -0,0 +1,325 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+MAKEFLAGS+=--warn-undefined-variables
+
+export CARAVEL_ROOT?=$(PWD)/caravel
+PRECHECK_ROOT?=${HOME}/mpw_precheck
+export MCW_ROOT?=$(PWD)/mgmt_core_wrapper
+SIM?=RTL
+
+# Install lite version of caravel, (1): caravel-lite, (0): caravel
+CARAVEL_LITE?=1
+
+# PDK switch varient
+export PDK?=gf180mcuC
+#export PDK?=gf180mcuC
+export PDKPATH?=$(PDK_ROOT)/$(PDK)
+
+
+
+ifeq ($(PDK),sky130A)
+ SKYWATER_COMMIT=f70d8ca46961ff92719d8870a18a076370b85f6c
+ export OPEN_PDKS_COMMIT?=0059588eebfc704681dc2368bd1d33d96281d10f
+ export OPENLANE_TAG?=2022.11.19
+ MPW_TAG ?= mpw-8a
+
+ifeq ($(CARAVEL_LITE),1)
+ CARAVEL_NAME := caravel-lite
+ CARAVEL_REPO := https://github.com/efabless/caravel-lite
+ CARAVEL_TAG := $(MPW_TAG)
+else
+ CARAVEL_NAME := caravel
+ CARAVEL_REPO := https://github.com/efabless/caravel
+ CARAVEL_TAG := $(MPW_TAG)
+endif
+
+endif
+
+ifeq ($(PDK),sky130B)
+ SKYWATER_COMMIT=f70d8ca46961ff92719d8870a18a076370b85f6c
+ export OPEN_PDKS_COMMIT?=0059588eebfc704681dc2368bd1d33d96281d10f
+ export OPENLANE_TAG?=2022.11.19
+ MPW_TAG ?= mpw-8a
+
+ifeq ($(CARAVEL_LITE),1)
+ CARAVEL_NAME := caravel-lite
+ CARAVEL_REPO := https://github.com/efabless/caravel-lite
+ CARAVEL_TAG := $(MPW_TAG)
+else
+ CARAVEL_NAME := caravel
+ CARAVEL_REPO := https://github.com/efabless/caravel
+ CARAVEL_TAG := $(MPW_TAG)
+endif
+
+endif
+
+ifeq ($(PDK),gf180mcuC)
+
+ MPW_TAG ?= gfmpw-0d
+ CARAVEL_NAME := caravel
+ CARAVEL_REPO := https://github.com/efabless/caravel-gf180mcu
+ CARAVEL_TAG := $(MPW_TAG)
+ #OPENLANE_TAG=ddfeab57e3e8769ea3d40dda12be0460e09bb6d9
+ #export OPEN_PDKS_COMMIT?=0059588eebfc704681dc2368bd1d33d96281d10f
+ export OPEN_PDKS_COMMIT?=35c7265f51749ad8d9fdbb575af22c7c8fab974e
+ export OPENLANE_TAG?=2022.11.29
+
+endif
+
+# Include Caravel Makefile Targets
+.PHONY: % : check-caravel
+%:
+ export CARAVEL_ROOT=$(CARAVEL_ROOT) && $(MAKE) -f $(CARAVEL_ROOT)/Makefile $@
+
+.PHONY: install
+install:
+ if [ -d "$(CARAVEL_ROOT)" ]; then\
+ echo "Deleting exisiting $(CARAVEL_ROOT)" && \
+ rm -rf $(CARAVEL_ROOT) && sleep 2;\
+ fi
+ echo "Installing $(CARAVEL_NAME).."
+ git clone -b $(CARAVEL_TAG) $(CARAVEL_REPO) $(CARAVEL_ROOT) --depth=1
+
+# Install DV setup
+.PHONY: simenv
+simenv:
+ docker pull efabless/dv:latest
+
+.PHONY: setup
+setup: install check-env install_mcw openlane pdk-with-volare setup-timing-scripts
+
+# Openlane
+blocks=$(shell cd openlane && find * -maxdepth 0 -type d)
+.PHONY: $(blocks)
+$(blocks): % :
+ $(MAKE) -C openlane $*
+
+dv_patterns=$(shell cd verilog/dv && find * -maxdepth 0 -type d)
+dv-targets-rtl=$(dv_patterns:%=verify-%-rtl)
+dv-targets-gl=$(dv_patterns:%=verify-%-gl)
+dv-targets-gl-sdf=$(dv_patterns:%=verify-%-gl-sdf)
+
+TARGET_PATH=$(shell pwd)
+verify_command="source ~/.bashrc && cd ${TARGET_PATH}/verilog/dv/$* && export SIM=${SIM} && make"
+dv_base_dependencies=simenv
+docker_run_verify=\
+ docker run -v ${TARGET_PATH}:${TARGET_PATH} -v ${PDK_ROOT}:${PDK_ROOT} \
+ -v ${CARAVEL_ROOT}:${CARAVEL_ROOT} \
+ -e TARGET_PATH=${TARGET_PATH} -e PDK_ROOT=${PDK_ROOT} \
+ -e CARAVEL_ROOT=${CARAVEL_ROOT} \
+ -e TOOLS=/foss/tools/riscv-gnu-toolchain-rv32i/217e7f3debe424d61374d31e33a091a630535937 \
+ -e DESIGNS=$(TARGET_PATH) \
+ -e USER_PROJECT_VERILOG=$(TARGET_PATH)/verilog \
+ -e PDK=$(PDK) \
+ -e CORE_VERILOG_PATH=$(TARGET_PATH)/mgmt_core_wrapper/verilog \
+ -e CARAVEL_VERILOG_PATH=$(TARGET_PATH)/caravel/verilog \
+ -e MCW_ROOT=$(MCW_ROOT) \
+ -u $$(id -u $$USER):$$(id -g $$USER) efabless/dv:latest \
+ sh -c $(verify_command)
+
+.PHONY: harden
+harden: $(blocks)
+
+.PHONY: verify
+verify: $(dv-targets-rtl)
+
+.PHONY: verify-all-rtl
+verify-all-rtl: $(dv-targets-rtl)
+
+.PHONY: verify-all-gl
+verify-all-gl: $(dv-targets-gl)
+
+.PHONY: verify-all-gl-sdf
+verify-all-gl-sdf: $(dv-targets-gl-sdf)
+
+$(dv-targets-rtl): SIM=RTL
+$(dv-targets-rtl): verify-%-rtl: $(dv_base_dependencies)
+ $(docker_run_verify)
+
+$(dv-targets-gl): SIM=GL
+$(dv-targets-gl): verify-%-gl: $(dv_base_dependencies)
+ $(docker_run_verify)
+
+$(dv-targets-gl-sdf): SIM=GL_SDF
+$(dv-targets-gl-sdf): verify-%-gl-sdf: $(dv_base_dependencies)
+ $(docker_run_verify)
+
+clean-targets=$(blocks:%=clean-%)
+.PHONY: $(clean-targets)
+$(clean-targets): clean-% :
+ rm -f ./verilog/gl/$*.v
+ rm -f ./spef/$*.spef
+ rm -f ./sdc/$*.sdc
+ rm -f ./sdf/$*.sdf
+ rm -f ./gds/$*.gds
+ rm -f ./mag/$*.mag
+ rm -f ./lef/$*.lef
+ rm -f ./maglef/*.maglef
+
+make_what=setup $(blocks) $(dv-targets-rtl) $(dv-targets-gl) $(dv-targets-gl-sdf) $(clean-targets)
+.PHONY: what
+what:
+ # $(make_what)
+
+# Install Openlane
+.PHONY: openlane
+openlane:
+ @if [ "$$(realpath $${OPENLANE_ROOT})" = "$$(realpath $$(pwd)/openlane)" ]; then\
+ echo "OPENLANE_ROOT is set to '$$(pwd)/openlane' which contains openlane config files"; \
+ echo "Please set it to a different directory"; \
+ exit 1; \
+ fi
+ cd openlane && $(MAKE) openlane
+
+#### Not sure if the targets following are of any use
+
+# Create symbolic links to caravel's main files
+.PHONY: simlink
+simlink: check-caravel
+### Symbolic links relative path to $CARAVEL_ROOT
+ $(eval MAKEFILE_PATH := $(shell realpath --relative-to=openlane $(CARAVEL_ROOT)/openlane/Makefile))
+ $(eval PIN_CFG_PATH := $(shell realpath --relative-to=openlane/user_project_wrapper $(CARAVEL_ROOT)/openlane/user_project_wrapper_empty/pin_order.cfg))
+ mkdir -p openlane
+ mkdir -p openlane/user_project_wrapper
+ cd openlane &&\
+ ln -sf $(MAKEFILE_PATH) Makefile
+ cd openlane/user_project_wrapper &&\
+ ln -sf $(PIN_CFG_PATH) pin_order.cfg
+
+# Update Caravel
+.PHONY: update_caravel
+update_caravel: check-caravel
+ cd $(CARAVEL_ROOT)/ && git checkout $(CARAVEL_TAG) && git pull
+
+# Uninstall Caravel
+.PHONY: uninstall
+uninstall:
+ rm -rf $(CARAVEL_ROOT)
+
+
+# Install Pre-check
+# Default installs to the user home directory, override by "export PRECHECK_ROOT=<precheck-installation-path>"
+.PHONY: precheck
+precheck:
+ @git clone --depth=1 --branch $(MPW_TAG) https://github.com/efabless/mpw_precheck.git $(PRECHECK_ROOT)
+ @docker pull efabless/mpw_precheck:latest
+
+.PHONY: run-precheck
+run-precheck: check-pdk check-precheck
+ $(eval INPUT_DIRECTORY := $(shell pwd))
+ cd $(PRECHECK_ROOT) && \
+ docker run -v $(PRECHECK_ROOT):$(PRECHECK_ROOT) \
+ -v $(INPUT_DIRECTORY):$(INPUT_DIRECTORY) \
+ -v $(PDK_ROOT):$(PDK_ROOT) \
+ -e INPUT_DIRECTORY=$(INPUT_DIRECTORY) \
+ -e PDK_PATH=$(PDK_ROOT)/$(PDK) \
+ -e PDK_ROOT=$(PDK_ROOT) \
+ -e PDKPATH=$(PDKPATH) \
+ -u $(shell id -u $(USER)):$(shell id -g $(USER)) \
+ efabless/mpw_precheck:latest bash -c "cd $(PRECHECK_ROOT) ; python3 mpw_precheck.py --input_directory $(INPUT_DIRECTORY) --pdk_path $(PDK_ROOT)/$(PDK)"
+
+
+
+.PHONY: clean
+clean:
+ cd ./verilog/dv/ && \
+ $(MAKE) -j$(THREADS) clean
+
+check-caravel:
+ @if [ ! -d "$(CARAVEL_ROOT)" ]; then \
+ echo "Caravel Root: "$(CARAVEL_ROOT)" doesn't exists, please export the correct path before running make. "; \
+ exit 1; \
+ fi
+
+check-precheck:
+ @if [ ! -d "$(PRECHECK_ROOT)" ]; then \
+ echo "Pre-check Root: "$(PRECHECK_ROOT)" doesn't exists, please export the correct path before running make. "; \
+ exit 1; \
+ fi
+
+check-pdk:
+ @if [ ! -d "$(PDK_ROOT)" ]; then \
+ echo "PDK Root: "$(PDK_ROOT)" doesn't exists, please export the correct path before running make. "; \
+ exit 1; \
+ fi
+
+.PHONY: help
+help:
+ cd $(CARAVEL_ROOT) && $(MAKE) help
+ @$(MAKE) -pRrq -f $(lastword $(MAKEFILE_LIST)) : 2>/dev/null | awk -v RS= -F: '/^# File/,/^# Finished Make data base/ {if ($$1 !~ "^[#.]") {print $$1}}' | sort | egrep -v -e '^[^[:alnum:]]' -e '^$@$$'
+
+
+export CUP_ROOT=$(shell pwd)
+export TIMING_ROOT?=$(shell pwd)/deps/timing-scripts
+export PROJECT_ROOT=$(CUP_ROOT)
+timing-scripts-repo=https://github.com/efabless/timing-scripts.git
+
+$(TIMING_ROOT):
+ @mkdir -p $(CUP_ROOT)/deps
+ @git clone $(timing-scripts-repo) $(TIMING_ROOT)
+
+.PHONY: setup-timing-scripts
+setup-timing-scripts: $(TIMING_ROOT)
+ @( cd $(TIMING_ROOT) && git pull )
+ @#( cd $(TIMING_ROOT) && git fetch && git checkout $(MPW_TAG); )
+ @python3 -m venv ./venv
+ . ./venv/bin/activate && \
+ python3 -m pip install --upgrade pip && \
+ python3 -m pip install -r $(TIMING_ROOT)/requirements.txt && \
+ deactivate
+
+./verilog/gl/user_project_wrapper.v:
+ $(error you don't have $@)
+
+./env/spef-mapping.tcl:
+ @echo "run the following:"
+ @echo "make extract-parasitics"
+ @echo "make create-spef-mapping"
+ exit 1
+
+.PHONY: create-spef-mapping
+create-spef-mapping: ./verilog/gl/user_project_wrapper.v
+ @. ./venv/bin/activate && \
+ python3 $(TIMING_ROOT)/scripts/generate_spef_mapping.py \
+ -i ./verilog/gl/user_project_wrapper.v \
+ -o ./env/spef-mapping.tcl \
+ --pdk-path $(PDK_ROOT)/$(PDK) \
+ --macro-parent mprj \
+ --project-root "$(CUP_ROOT)" && \
+ deactivate
+
+.PHONY: extract-parasitics
+extract-parasitics: ./verilog/gl/user_project_wrapper.v
+ @. ./venv/bin/activate && \
+ python3 $(TIMING_ROOT)/scripts/get_macros.py \
+ -i ./verilog/gl/user_project_wrapper.v \
+ -o ./tmp-macros-list \
+ --project-root "$(CUP_ROOT)" \
+ --pdk-path $(PDK_ROOT)/$(PDK) && \
+ deactivate
+ @cat ./tmp-macros-list | cut -d " " -f2 \
+ | xargs -I % bash -c "$(MAKE) -C $(TIMING_ROOT) \
+ -f $(TIMING_ROOT)/timing.mk rcx-% || echo 'Cannot extract %. Probably no def for this macro'"
+ @$(MAKE) -C $(TIMING_ROOT) -f $(TIMING_ROOT)/timing.mk rcx-user_project_wrapper
+ @cat ./tmp-macros-list
+ @rm ./tmp-macros-list
+
+.PHONY: caravel-sta
+caravel-sta: ./env/spef-mapping.tcl
+ @$(MAKE) -C $(TIMING_ROOT) -f $(TIMING_ROOT)/timing.mk caravel-timing-typ
+ @$(MAKE) -C $(TIMING_ROOT) -f $(TIMING_ROOT)/timing.mk caravel-timing-fast
+ @$(MAKE) -C $(TIMING_ROOT) -f $(TIMING_ROOT)/timing.mk caravel-timing-slow
+ @echo "You can find results for all corners in $(CUP_ROOT)/signoff/caravel/openlane-signoff/timing/"
diff --git a/README.md b/README.md
new file mode 100644
index 0000000..126e29a
--- /dev/null
+++ b/README.md
@@ -0,0 +1,23 @@
+# Ophelia eFPGA
+
+[](https://opensource.org/licenses/Apache-2.0)
+
+## General description
+
+Ophelia is a test project implementing open-source Uranus eFPGA fabric for OpenMPW-GF0 using open source GF180 PDK and OpenLane flow. FPGA contains 112 4-input LUTs and uses Wishbone bus from Caravel test harness for bitstream loading. Project also contains eFuse array for nonvolatile FPGA config storage.
+
+## Project implementation
+
+Project is implemented for Skywater 130nm ASIC technology using OpenLane open source flow. Synthesis is done in two steps: first Yosys+GHDL are used for VHDL to Verilog translation, and then resulting Verilog source is synthesized by Yosys inside OpenLane flow.
+
+## FPGA flow
+
+Uranus FPGA uses opensource flow for FPGA bitstream generation. Yosys (with optional GHDL frontend for VHDL) is used for synthesis and VPR for place and route. Flow glue and bitstream generation is done by custom Python scripts.
+
+## Sources
+
+This repository contains mainly implementation products (GDS/netlists/etc) needed for OpenMPW and test Caravel programs. VHDL sources of Uranus FPGA fabric, FPGA flow, tests and simulation scripts are stored in [main Uranus repository](https://github.com/egorxe/uranus_fpga).
+
+## Documentation
+
+Documentation is avaliable in [main Uranus repository](https://github.com/egorxe/uranus_fpga/blob/main/docs/index.rst).
diff --git a/def/efuse_ctrl.def.gz b/def/efuse_ctrl.def.gz
new file mode 100644
index 0000000..a414355
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diff --git a/def/user_project_wrapper.def.gz b/def/user_project_wrapper.def.gz
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diff --git a/docs/Makefile b/docs/Makefile
new file mode 100644
index 0000000..c715218
--- /dev/null
+++ b/docs/Makefile
@@ -0,0 +1,37 @@
+
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+# Minimal makefile for Sphinx documentation
+#
+
+# You can set these variables from the command line, and also
+# from the environment for the first two.
+SPHINXOPTS ?=
+SPHINXBUILD ?= sphinx-build
+SOURCEDIR = source
+BUILDDIR = build
+
+# Put it first so that "make" without argument is like "make help".
+help:
+ @$(SPHINXBUILD) -M help "$(SOURCEDIR)" "$(BUILDDIR)" $(SPHINXOPTS) $(O)
+
+.PHONY: help Makefile
+
+# Catch-all target: route all unknown targets to Sphinx using the new
+# "make mode" option. $(O) is meant as a shortcut for $(SPHINXOPTS).
+%: Makefile
+ @$(SPHINXBUILD) -M $@ "$(SOURCEDIR)" "$(BUILDDIR)" $(SPHINXOPTS) $(O)
+
diff --git a/docs/environment.yml b/docs/environment.yml
new file mode 100644
index 0000000..2bddf94
--- /dev/null
+++ b/docs/environment.yml
@@ -0,0 +1,23 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+name: caravel-docs
+channels:
+- defaults
+dependencies:
+- python>=3.8
+- pip:
+ - -r file:requirements.txt
diff --git a/docs/requirements.txt b/docs/requirements.txt
new file mode 100644
index 0000000..f5c5383
--- /dev/null
+++ b/docs/requirements.txt
@@ -0,0 +1,6 @@
+git+https://github.com/SymbiFlow/sphinx_materialdesign_theme.git#egg=sphinx-symbiflow-theme
+
+docutils
+sphinx
+sphinx-autobuild
+sphinxcontrib-wavedrom
diff --git a/docs/source/_static/counter_32.png b/docs/source/_static/counter_32.png
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diff --git a/docs/source/conf.py b/docs/source/conf.py
new file mode 100644
index 0000000..f960f13
--- /dev/null
+++ b/docs/source/conf.py
@@ -0,0 +1,89 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+# Configuration file for the Sphinx documentation builder.
+#
+# This file only contains a selection of the most common options. For a full
+# list see the documentation:
+# https://www.sphinx-doc.org/en/master/usage/configuration.html
+
+# -- Path setup --------------------------------------------------------------
+
+# If extensions (or modules to document with autodoc) are in another directory,
+# add these directories to sys.path here. If the directory is relative to the
+# documentation root, use os.path.abspath to make it absolute, like shown here.
+#
+# import os
+# import sys
+# sys.path.insert(0, os.path.abspath('.'))
+
+
+# -- Project information -----------------------------------------------------
+
+project = 'CIIC Harness'
+copyright = '2020, efabless'
+author = 'efabless'
+
+
+# -- General configuration ---------------------------------------------------
+
+# Add any Sphinx extension module names here, as strings. They can be
+# extensions coming with Sphinx (named 'sphinx.ext.*') or your custom
+# ones.
+extensions = [
+ 'sphinxcontrib.wavedrom',
+ 'sphinx.ext.mathjax',
+ 'sphinx.ext.todo'
+]
+
+# Add any paths that contain templates here, relative to this directory.
+templates_path = ['_templates']
+
+# List of patterns, relative to source directory, that match files and
+# directories to ignore when looking for source files.
+# This pattern also affects html_static_path and html_extra_path.
+exclude_patterns = [
+ 'build',
+ 'Thumbs.db',
+ # Files included in other rst files.
+ 'introduction.rst',
+]
+
+
+# -- Options for HTML output -------------------------------------------------
+"""
+html_theme_options = {
+ 'header_links' : [
+ ("Home", 'index', False, 'home'),
+ ("GitHub", "https://github.com/efabless/caravel", True, 'code'),
+ ],
+ 'hide_symbiflow_links': True,
+ 'license_url' : 'https://www.apache.org/licenses/LICENSE-2.0',
+}
+"""
+# The theme to use for HTML and HTML Help pages. See the documentation for
+# a list of builtin themes.
+#
+html_theme = 'sphinx_rtd_theme'
+
+# Add any paths that contain custom static files (such as style sheets) here,
+# relative to this directory. They are copied after the builtin static files,
+# so a file named "default.css" will overwrite the builtin "default.css".
+html_static_path = ['_static']
+
+todo_include_todos = False
+
+numfig = True
diff --git a/docs/source/index.rst b/docs/source/index.rst
new file mode 100644
index 0000000..e736ac6
--- /dev/null
+++ b/docs/source/index.rst
@@ -0,0 +1,597 @@
+.. raw:: html
+
+ <!---
+ # SPDX-FileCopyrightText: 2020 Efabless Corporation
+ #
+ # Licensed under the Apache License, Version 2.0 (the "License");
+ # you may not use this file except in compliance with the License.
+ # You may obtain a copy of the License at
+ #
+ # http://www.apache.org/licenses/LICENSE-2.0
+ #
+ # Unless required by applicable law or agreed to in writing, software
+ # distributed under the License is distributed on an "AS IS" BASIS,
+ # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ # See the License for the specific language governing permissions and
+ # limitations under the License.
+ #
+ # SPDX-License-Identifier: Apache-2.0
+ -->
+
+Caravel User Project
+====================
+
+|License| |User CI| |Caravel Build|
+
+Table of contents
+=================
+
+- `Overview <#overview>`__
+- `Quickstart <#quickstart>`__
+- `Caravel Integration <#caravel-integration>`__
+
+ - `Repo Integration <#repo-integration>`__
+ - `Verilog Integration <#verilog-integration>`__
+ - `GPIO Configuration <#gpio-configuration>`__
+ - `Layout Integration <#layout-integration>`__
+
+- `Running Full Chip Simulation <#running-full-chip-simulation>`__
+- `User Project Wrapper Requirements <#user-project-wrapper-requirements>`__
+- `Hardening the User Project using
+ Openlane <#hardening-the-user-project-using-openlane>`__
+- `Running Timing Analysis on Existing Projects <#running-timing-analysis-on-existing-projects>`__
+- `Checklist for Open-MPW
+ Submission <#checklist-for-open-mpw-submission>`__
+
+Overview
+========
+
+This repo contains a sample user project that utilizes the
+`caravel <https://github.com/efabless/caravel.git>`__ chip user space.
+The user project is a simple counter that showcases how to make use of
+`caravel's <https://github.com/efabless/caravel.git>`__ user space
+utilities like IO pads, logic analyzer probes, and wishbone port. The
+repo also demonstrates the recommended structure for the open-mpw
+shuttle projects.
+
+Prerequisites
+=============
+
+- Docker: `Linux <https://hub.docker.com/search?q=&type=edition&offering=community&operating_system=linux&utm_source=docker&utm_medium=webreferral&utm_campaign=dd-smartbutton&utm_location=header>`_ || `Windows <https://desktop.docker.com/win/main/amd64/Docker%20Desktop%20Installer.exe?utm_source=docker&utm_medium=webreferral&utm_campaign=dd-smartbutton&utm_location=header>`_ || `Mac with Intel Chip <https://desktop.docker.com/mac/main/amd64/Docker.dmg?utm_source=docker&utm_medium=webreferral&utm_campaign=dd-smartbutton&utm_location=header>`_ || `Mac with M1 Chip <https://desktop.docker.com/mac/main/arm64/Docker.dmg?utm_source=docker&utm_medium=webreferral&utm_campaign=dd-smartbutton&utm_location=header>`_
+
+- Python 3.6+ with PIP
+
+
+Quickstart
+===========
+
+---------------------
+Starting your project
+---------------------
+
+#. To start the project you first need to create a new repository based on the `caravel_user_project <https://github.com/efabless/caravel_user_project/>`_ and make sure your repo is public and includes a README.
+
+# NOTE: You cannoty use the create from template feature as this points to main branch based on SKY130.
+
+ * Create a blank repo for your project on github. Copy the URL for the new project from github.
+
+ * Clone the reposity using the following command:
+
+ .. code:: bash
+
+ git clone -b gfmpw-0b https://github.com/efabless/caravel_user_project.git <my_project>
+
+ cd <my_project>
+
+ git remote add MYREPO <repo URL for your project>
+
+ git push MYREPO
+
+#. To setup your local environment run:
+
+ .. code:: bash
+
+ mkdir dependencies
+
+ export OPENLANE_ROOT=$(pwd)/dependencies/openlane_src # you need to export this whenever you start a new shell
+
+ export PDK_ROOT=$(pwd)/dependencies/pdks # you need to export this whenever you start a new shell
+
+ export PDK=gf180mcuC
+
+ make setup
+
+* This command will setup your environment by installing the following
+
+ - caravel_lite (a lite version of caravel)
+ - management core for simulation
+ - openlane to harden your design
+ - pdk
+
+
+#. Now you can start hardening your design
+
+ * To start hardening you project you need
+ - RTL verilog model for your design for OpenLane to harden
+ - A subdirectory for each macro in your project under ``openlane/`` directory, each subdirectory should include openlane configuration files for the macro
+
+ .. code:: bash
+
+ make <module_name>
+ ..
+
+ For an example of hardening a project please refer to `Hardening the User Project using OpenLane`_. .
+
+#. Integrate modules into the user_project_wrapper
+
+ * Change the environment variables ``VERILOG_FILES_BLACKBOX``, ``EXTRA_LEFS`` and ``EXTRA_GDS_FILES`` in ``openlane/user_project_wrapper/config.tcl`` to point to your module
+ * Instantiate your module(s) in ``verilog/rtl/user_project_wrapper.v``
+ * Harden the user_project_wrapper including your module(s), using this command:
+
+ .. code:: bash
+
+ make user_project_wrapper
+
+#. Run simulation on your design
+
+ * You need to include your rtl/gl/gl+sdf files in ``verilog/includes/includes.<rtl/gl/gl+sdf>.caravel_user_project``
+
+ **NOTE:** You shouldn't include the files inside the verilog code
+
+ .. code:: bash
+
+ # you can then run RTL simulations using
+ make verify-<testbench-name>-rtl
+
+ # OR GL simulation using
+ make verify-<testbench-name>-gl
+
+ # OR for GL+SDF simulation using
+ # sdf annotated simulation is slow
+ make verify-<testbench-name>-gl-sdf
+
+ # for example
+ make verify-io_ports-rtl
+
+#. Run opensta on your design
+
+ * Extract spefs for ``user_project_wrapper`` and macros inside it:
+
+ .. code:: bash
+
+ make extract-parasitics
+
+ * Create spef mapping file that maps instance names to spef files:
+
+ .. code:: bash
+
+ make create-spef-mapping
+
+ * Run opensta:
+
+ .. code:: bash
+
+ make caravel-sta
+
+ **NOTE:** To update timing scripts run ``make setup-timing-scripts``
+
+#. Run the precheck locally
+
+ .. code:: bash
+
+ make precheck
+ make run-precheck
+
+#. You are done! now go to https://efabless.com/open_shuttle_program/ to submit your project!
+
+
+Caravel Integration
+===================
+
+----------------
+Repo Integration
+----------------
+
+Caravel files are kept separate from the user project by having caravel
+as submodule. The submodule commit should point to the latest of
+caravel/caravel-lite master/main branch. The following files should have a symbolic
+link to `caravel's <https://github.com/efabless/caravel.git>`__
+corresponding files:
+
+- `Openlane Makefile <../../openlane/Makefile>`__: This provides an easier
+ way for running openlane to harden your macros. Refer to `Hardening
+ the User Project Macro using
+ Openlane <#hardening-the-user-project-using-openlane>`__. Also,
+ the makefile retains the openlane summary reports under the signoff
+ directory.
+
+- `Pin order <../../openlane/user_project_wrapper/pin_order.cfg>`__ file for
+ the user wrapper: The hardened user project wrapper macro must have
+ the same pin order specified in caravel's repo. Failing to adhere to
+ the same order will fail the gds integration of the macro with
+ caravel's back-end.
+
+The symbolic links are automatically set when you run ``make install``.
+
+-------------------
+Verilog Integration
+-------------------
+
+You need to create a wrapper around your macro that adheres to the
+template at
+`user\_project\_wrapper <https://github.com/efabless/caravel/blob/master/verilog/rtl/__user_project_wrapper.v>`__.
+The wrapper top module must be named ``user_project_wrapper`` and must
+have the same input and output ports as the golden wrapper `template <https://github.com/efabless/caravel/blob/master/verilog/rtl/__user_project_wrapper.v>`__. The wrapper gives access to the
+user space utilities provided by caravel like IO ports, logic analyzer
+probes, and wishbone bus connection to the management SoC.
+
+For this sample project, the user macro makes use of:
+
+- The IO ports for displaying the count register values on the IO pads.
+
+- The LA probes for supplying an optional reset and clock signals and
+ for setting an initial value for the count register.
+
+- The wishbone port for reading/writing the count value through the
+ management SoC.
+
+Refer to `user\_project\_wrapper <../../verilog/rtl/user_project_wrapper.v>`__
+for more information.
+
+.. raw:: html
+
+ <p align="center">
+ <img src="./_static/counter_32.png" width="50%" height="50%">
+ </p>
+
+.. raw:: html
+
+ </p>
+
+-------------------
+GPIO Configuration
+-------------------
+
+You are required to specify the power-on default configuration for each GPIO in Caravel. The default configuration provide the state the GPIO will come up on power up. The configuration can be changed by the management SoC during firmware execution.
+
+Configuration settings define whether the GPIO is configured to connect to the user project area or the managment SoC. They also determine whether IOs are inputs or outputs, digital or analog, as well as whether pull-up or pull-down resistors are configured for inputs.
+
+GPIOs are configured by assigning predefined values for each IO in the file `verilog/rtl/user_defines.v <https://github.com/efabless/caravel_user_project/blob/main/verilog/rtl/user_defines.v>`_ in your project.
+
+You need to assigned configuration values for GPIO[5] thru GPIO[37].
+
+GPIO[0] thru GPIO[4] are preset and cannot be changed.
+
+The following values are redefined for assigning to GPIOs.
+
+
+- GPIO_MODE_MGMT_STD_INPUT_NOPULL
+- GPIO_MODE_MGMT_STD_INPUT_PULLDOWN
+- GPIO_MODE_MGMT_STD_INPUT_PULLUP
+- GPIO_MODE_MGMT_STD_OUTPUT
+- GPIO_MODE_MGMT_STD_BIDIRECTIONAL
+- GPIO_MODE_MGMT_STD_ANALOG
+
+- GPIO_MODE_USER_STD_INPUT_NOPULL
+- GPIO_MODE_USER_STD_INPUT_PULLDOWN
+- GPIO_MODE_USER_STD_INPUT_PULLUP
+- GPIO_MODE_USER_STD_OUTPUT
+- GPIO_MODE_USER_STD_BIDIRECTIONAL
+- GPIO_MODE_USER_STD_OUT_MONITORED
+- GPIO_MODE_USER_STD_ANALOG
+
+
+MPW_Prececk includes a check to confirm each GPIO is assigned a valid value.
+
+-------------------
+Layout Integration
+-------------------
+
+The caravel layout is pre-designed with an empty golden wrapper in the user space. You only need to provide us with a valid ``user_project_wrapper`` GDS file. And, as part of the tapeout process, your hardened ``user_project_wrapper`` will be inserted into a vanilla caravel layout to get the final layout shipped for fabrication.
+
+.. raw:: html
+
+ <p align="center">
+ <img src="./_static/layout.png" width="80%" height="80%">
+ </p>
+
+To make sure that this integration process goes smoothly without having any DRC or LVS issues, your hardened ``user_project_wrapper`` must adhere to a number of requirements listed at `User Project Wrapper Requirements <#user-project-wrapper-requirements>`__ .
+
+
+Running Full Chip Simulation
+============================
+
+First, you will need to install the simulation environment, by
+
+.. code:: bash
+
+ make simenv
+
+This will pull a docker image with the needed tools installed.
+
+Then, run the RTL simulation by
+
+.. code:: bash
+
+ export PDK_ROOT=<pdk-installation-path>
+ make verify-<testbench-name>-rtl
+
+ # For example
+ make verify-io_ports-rtl
+
+Once you have the physical implementation done and you have the gate-level netlists ready, it is crucial to run full gate-level simulations to make sure that your design works as intended after running the physical implementation.
+
+Run the gate-level simulation by:
+
+.. code:: bash
+
+ export PDK_ROOT=<pdk-installation-path>
+ make verify-<testbench-name>-gl
+
+ # For example
+ make verify-io_ports-gl
+
+To make sure that your design is timing clean, one way is running sdf annotated gate-level simulation
+Run the sdf annotated gate-level simulation by:
+
+.. code:: bash
+
+ export PDK_ROOT=<pdk-installation-path>
+ make verify-<testbench-name>-gl-sdf
+
+ # For example
+ make verify-io_ports-gl-sdf
+
+This sample project comes with four example testbenches to test the IO port connection, wishbone interface, and logic analyzer. The test-benches are under the
+`verilog/dv <https://github.com/efabless/caravel_user_project/tree/main/verilog/dv>`__ directory. For more information on setting up the
+simulation environment and the available testbenches for this sample
+project, refer to `README <https://github.com/efabless/caravel_user_project/blob/main/verilog/dv/README.md>`__.
+
+
+User Project Wrapper Requirements
+=================================
+
+Your hardened ``user_project_wrapper`` must match the `golden user_project_wrapper <https://github.com/efabless/caravel/blob/master/gds/user_project_wrapper_empty.gds.gz>`__ in the following:
+
+- Area ``(2.920um x 3.520um)``
+- Top module name ``"user_project_wrapper"``
+- Pin Placement
+- Pin Sizes
+- Core Rings Width and Offset
+- PDN Vertical and Horizontal Straps Width
+
+
+.. raw:: html
+
+ <p align="center">
+ <img src="./_static/empty.png" width="40%" height="40%">
+ </p>
+
+You are allowed to change the following if you need to:
+
+- PDN Vertical and Horizontal Pitch & Offset
+
+.. raw:: html
+
+ <p align="center">
+ <img src="./_static/pitch.png" width="30%" height="30%">
+ </p>
+
+To make sure that you adhere to these requirements, we run an exclusive-or (XOR) check between your hardened ``user_project_wrapper`` GDS and the golden wrapper GDS after processing both layouts to include only the boundary (pins and core rings). This check is done as part of the `mpw-precheck <https://github.com/efabless/mpw_precheck>`__ tool.
+
+
+Hardening the User Project using OpenLane
+==========================================
+
+---------------------
+OpenLane Installation
+---------------------
+
+You will need to install openlane by running the following
+
+.. code:: bash
+
+ export OPENLANE_ROOT=<openlane-installation-path>
+
+ # you can optionally specify the openlane tag to use
+ # by running: export OPENLANE_TAG=<openlane-tag>
+ # if you do not set the tag, it defaults to the last verfied tag tested for this project
+
+ make openlane
+
+For detailed instructions on the openlane and the pdk installation refer
+to
+`README <https://github.com/The-OpenROAD-Project/OpenLane#setting-up-openlane>`__.
+
+-----------------
+Hardening Options
+-----------------
+
+There are three options for hardening the user project macro using
+openlane:
+
++--------------------------------------------------------------+--------------------------------------------+--------------------------------------------+
+| Option 1 | Option 2 | Option 3 |
++--------------------------------------------------------------+--------------------------------------------+--------------------------------------------+
+| Hardening the user macro(s) first, then inserting it in the | Flattening the user macro(s) with the | Placing multiple macros in the wrapper |
+| user project wrapper with no standard cells on the top level | user_project_wrapper | along with standard cells on the top level |
++==============================================================+============================================+============================================+
+| |pic1| | |pic2| | |pic3| |
+| | | |
++--------------------------------------------------------------+--------------------------------------------+--------------------------------------------+
+| ex: |link1| | | ex: |link2| |
++--------------------------------------------------------------+--------------------------------------------+--------------------------------------------+
+
+.. |link1| replace:: `caravel_user_project <https://github.com/efabless/caravel_user_project>`__
+
+.. |link2| replace:: `caravel_ibex <https://github.com/efabless/caravel_ibex>`__
+
+
+.. |pic1| image:: ./_static/option1.png
+ :width: 48%
+
+.. |pic2| image:: ./_static/option2.png
+ :width: 140%
+
+.. |pic3| image:: ./_static/option3.png
+ :width: 72%
+
+For more details on hardening macros using openlane, refer to `README <https://github.com/The-OpenROAD-Project/OpenLane/blob/master/docs/source/hardening_macros.md>`__.
+
+-----------------
+Running OpenLane
+-----------------
+
+For this sample project, we went for the first option where the user
+macro is hardened first, then it is inserted in the user project
+wrapper without having any standard cells on the top level.
+
+.. raw:: html
+
+ <p align="center">
+ <img src="./_static/wrapper.png" width="30%" height="30%">
+ </p>
+
+.. raw:: html
+
+ </p>
+
+To reproduce hardening this project, run the following:
+
+.. code:: bash
+
+ # DO NOT cd into openlane
+
+ # Run openlane to harden user_proj_example
+ make user_proj_example
+ # Run openlane to harden user_project_wrapper
+ make user_project_wrapper
+
+
+For more information on the openlane flow, check `README <https://github.com/The-OpenROAD-Project/OpenLane#readme>`__.
+
+Running MPW Precheck Locally
+=================================
+
+You can install the `mpw-precheck <https://github.com/efabless/mpw_precheck>`__ by running
+
+.. code:: bash
+
+ # By default, this install the precheck in your home directory
+ # To change the installtion path, run "export PRECHECK_ROOT=<precheck installation path>"
+ make precheck
+
+This will clone the precheck repo and pull the latest precheck docker image.
+
+
+Then, you can run the precheck by running
+
+.. code:: bash
+
+ make run-precheck
+
+This will run all the precheck checks on your project and will produce the logs under the ``checks`` directory.
+
+Running Timing Analysis on Existing Projects
+========================================================
+
+Start by updating the Makefile for your project. Starting in the project root...
+
+.. code:: bash
+
+ curl -k https://raw.githubusercontent.com/efabless/caravel_user_project/main/Makefile > Makefile
+
+ make setup-timing-scripts
+
+ make install
+
+ make install_mcw
+
+
+This will update Caravel design files and install the scripts for running timing.
+
+
+Then, you can run then run timing by the following...
+
+.. code:: bash
+
+ make extract-parasitics
+
+ make create-spef-mapping
+
+ make caravel-sta
+
+
+A summary of timing results is provided at the end of the flow.
+
+
+Other Miscellaneous Targets
+============================
+
+The makefile provides a number of useful that targets that can run LVS, DRC, and XOR checks on your hardened design outside of openlane's flow.
+
+Run ``make help`` to display available targets.
+
+Run lvs on the mag view,
+
+.. code:: bash
+
+ make lvs-<macro_name>
+
+Run lvs on the gds,
+
+.. code:: bash
+
+ make lvs-gds-<macro_name>
+
+Run lvs on the maglef,
+
+.. code:: bash
+
+ make lvs-maglef-<macro_name>
+
+Run drc using magic,
+
+.. code:: bash
+
+ make drc-<macro_name>
+
+Run antenna check using magic,
+
+.. code:: bash
+
+ make antenna-<macro_name>
+
+Run XOR check,
+
+.. code:: bash
+
+ make xor-wrapper
+
+
+
+
+Checklist for Open-MPW Submission
+=================================
+
+- ✔️ The project repo adheres to the same directory structure in this
+ repo.
+- ✔️ The project repo contain info.yaml at the project root.
+- ✔️ Top level macro is named ``user_project_wrapper``.
+- ✔️ Full Chip Simulation passes for RTL and GL (gate-level)
+- ✔️ The hardened Macros are LVS and DRC clean
+- ✔️ The project contains a gate-level netlist for ``user_project_wrapper`` at verilog/gl/user_project_wrapper.v
+- ✔️ The hardened ``user_project_wrapper`` adheres to the same pin
+ order specified at
+ `pin\_order <https://github.com/efabless/caravel/blob/master/openlane/user_project_wrapper_empty/pin_order.cfg>`__
+- ✔️ The hardened ``user_project_wrapper`` adheres to the fixed wrapper configuration specified at `fixed_wrapper_cfgs <https://github.com/efabless/caravel/blob/master/openlane/user_project_wrapper_empty/fixed_wrapper_cfgs.tcl>`__
+- ✔️ XOR check passes with zero total difference.
+- ✔️ Openlane summary reports are retained under ./signoff/
+- ✔️ The design passes the `mpw-precheck <https://github.com/efabless/mpw_precheck>`__
+
+.. |License| image:: https://img.shields.io/badge/License-Apache%202.0-blue.svg
+ :target: https://opensource.org/licenses/Apache-2.0
+.. |User CI| image:: https://github.com/efabless/caravel_project_example/actions/workflows/user_project_ci.yml/badge.svg
+ :target: https://github.com/efabless/caravel_project_example/actions/workflows/user_project_ci.yml
+.. |Caravel Build| image:: https://github.com/efabless/caravel_project_example/actions/workflows/caravel_build.yml/badge.svg
+ :target: https://github.com/efabless/caravel_project_example/actions/workflows/caravel_build.yml
diff --git a/gds/efuse_ctrl.gds.gz b/gds/efuse_ctrl.gds.gz
new file mode 100644
index 0000000..f0d894c
--- /dev/null
+++ b/gds/efuse_ctrl.gds.gz
Binary files differ
diff --git a/gds/fpga_struct_block.gds.gz b/gds/fpga_struct_block.gds.gz
new file mode 100644
index 0000000..d6e26ef
--- /dev/null
+++ b/gds/fpga_struct_block.gds.gz
Binary files differ
diff --git a/gds/user_project_wrapper.gds.gz b/gds/user_project_wrapper.gds.gz
new file mode 100644
index 0000000..b8ae994
--- /dev/null
+++ b/gds/user_project_wrapper.gds.gz
Binary files differ
diff --git a/lef/efuse_ctrl.lef b/lef/efuse_ctrl.lef
new file mode 100644
index 0000000..70de3cb
--- /dev/null
+++ b/lef/efuse_ctrl.lef
@@ -0,0 +1,1617 @@
+VERSION 5.7 ;
+ NOWIREEXTENSIONATPIN ON ;
+ DIVIDERCHAR "/" ;
+ BUSBITCHARS "[]" ;
+MACRO efuse_ctrl
+ CLASS BLOCK ;
+ FOREIGN efuse_ctrl ;
+ ORIGIN 0.000 0.000 ;
+ SIZE 2175.000 BY 2350.000 ;
+ PIN VDD
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER Metal4 ;
+ RECT 25.920 15.380 27.520 2332.700 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 215.920 15.380 217.520 29.720 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 215.920 768.115 217.520 789.720 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 215.920 1528.115 217.520 1549.720 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 215.920 2288.115 217.520 2332.700 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 405.920 15.380 407.520 32.245 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 405.920 767.505 407.520 792.245 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 405.920 1527.505 407.520 1552.245 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 405.920 2287.505 407.520 2332.700 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 595.920 15.380 597.520 32.270 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 595.920 767.505 597.520 792.270 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 595.920 1527.505 597.520 1552.270 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 595.920 2287.505 597.520 2332.700 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 785.920 15.380 787.520 32.270 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 785.920 767.530 787.520 792.270 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 785.920 1527.530 787.520 1552.270 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 785.920 2287.530 787.520 2332.700 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 975.920 15.380 977.520 32.245 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 975.920 767.505 977.520 792.245 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 975.920 1527.505 977.520 1552.245 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 975.920 2287.505 977.520 2332.700 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 1165.920 15.380 1167.520 2332.700 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 1355.920 15.380 1357.520 2332.700 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 1545.920 15.380 1547.520 29.720 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 1545.920 767.530 1547.520 789.720 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 1545.920 1527.530 1547.520 1549.720 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 1545.920 2287.530 1547.520 2332.700 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 1735.920 15.380 1737.520 32.270 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 1735.920 767.505 1737.520 792.270 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 1735.920 1527.505 1737.520 1552.270 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 1735.920 2287.505 1737.520 2332.700 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 1925.920 15.380 1927.520 32.270 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 1925.920 767.505 1927.520 792.270 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 1925.920 1527.505 1927.520 1552.270 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 1925.920 2287.505 1927.520 2332.700 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 2115.920 15.380 2117.520 32.245 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 2115.920 767.530 2117.520 792.245 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 2115.920 1527.530 2117.520 1552.245 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 2115.920 2287.530 2117.520 2332.700 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 110.360 23.220 111.960 772.540 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 198.280 783.700 199.880 1533.020 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 286.200 1544.180 287.800 2293.500 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 110.360 783.700 111.960 1533.020 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 198.280 23.220 199.880 772.540 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 374.120 1544.180 375.720 2293.500 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 110.360 1544.180 111.960 2293.500 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 286.200 23.220 287.800 772.540 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 374.120 783.700 375.720 1533.020 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 198.280 1544.180 199.880 2293.500 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 286.200 783.700 287.800 1533.020 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 374.120 23.220 375.720 772.540 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 462.040 23.220 463.640 772.540 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 549.960 783.700 551.560 1533.020 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 638.440 1544.180 640.040 2293.500 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 462.040 783.700 463.640 1533.020 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 549.960 23.220 551.560 772.540 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 726.360 1544.180 727.960 2293.500 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 462.040 1544.180 463.640 2293.500 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 638.440 23.220 640.040 772.540 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 726.360 783.700 727.960 1533.020 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 549.960 1544.180 551.560 2293.500 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 638.440 783.700 640.040 1533.020 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 726.360 23.220 727.960 772.540 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 814.280 23.220 815.880 772.540 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 902.200 783.700 903.800 1533.020 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 990.120 1544.180 991.720 2293.500 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 814.280 783.700 815.880 1533.020 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 902.200 23.220 903.800 772.540 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 1078.040 1544.180 1079.640 2293.500 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 814.280 1544.180 815.880 2293.500 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 990.120 23.220 991.720 772.540 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 1078.040 783.700 1079.640 1533.020 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 902.200 1544.180 903.800 2293.500 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 990.120 783.700 991.720 1533.020 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 1078.040 23.220 1079.640 772.540 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 1254.440 23.220 1256.040 772.540 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 1430.280 1544.180 1431.880 2293.500 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 1254.440 783.700 1256.040 1533.020 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 1518.200 1544.180 1519.800 2293.500 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 1254.440 1544.180 1256.040 2293.500 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 1430.280 23.220 1431.880 772.540 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 1518.200 783.700 1519.800 1533.020 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 1430.280 783.700 1431.880 1533.020 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 1518.200 23.220 1519.800 772.540 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 1606.120 23.220 1607.720 772.540 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 1694.040 783.700 1695.640 1533.020 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 1781.960 1544.180 1783.560 2293.500 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 1606.120 783.700 1607.720 1533.020 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 1694.040 23.220 1695.640 772.540 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 1870.440 1544.180 1872.040 2293.500 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 1606.120 1544.180 1607.720 2293.500 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 1781.960 23.220 1783.560 772.540 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 1870.440 783.700 1872.040 1533.020 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 1694.040 1544.180 1695.640 2293.500 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 1781.960 783.700 1783.560 1533.020 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 1870.440 23.220 1872.040 772.540 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 1958.360 23.220 1959.960 772.540 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 2046.280 783.700 2047.880 1533.020 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 2143.720 1544.180 2145.320 2293.500 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 1958.360 783.700 1959.960 1533.020 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 2046.280 23.220 2047.880 772.540 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 1958.360 1544.180 1959.960 2293.500 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 2143.720 23.220 2145.320 772.540 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 2046.280 1544.180 2047.880 2293.500 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 2143.720 783.700 2145.320 1533.020 ;
+ END
+ END VDD
+ PIN VSS
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER Metal4 ;
+ RECT 35.520 15.380 37.120 2332.700 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 225.520 15.380 227.120 29.720 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 225.520 767.530 227.120 789.720 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 225.520 1527.530 227.120 1549.720 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 225.520 2287.530 227.120 2332.700 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 415.520 15.380 417.120 32.270 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 415.520 767.505 417.120 792.270 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 415.520 1527.505 417.120 1552.270 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 415.520 2287.505 417.120 2332.700 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 605.520 15.380 607.120 32.270 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 605.520 767.505 607.120 792.270 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 605.520 1527.505 607.120 1552.270 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 605.520 2287.505 607.120 2332.700 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 795.520 15.380 797.120 32.270 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 795.520 767.530 797.120 792.270 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 795.520 1527.530 797.120 1552.270 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 795.520 2287.530 797.120 2332.700 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 985.520 15.380 987.120 2332.700 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 1175.520 15.380 1177.120 2332.700 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 1365.520 15.380 1367.120 29.720 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 1365.520 767.530 1367.120 789.720 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 1365.520 1527.530 1367.120 1549.720 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 1365.520 2287.530 1367.120 2332.700 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 1555.520 15.380 1557.120 32.270 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 1555.520 767.505 1557.120 792.270 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 1555.520 1527.505 1557.120 1552.270 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 1555.520 2287.505 1557.120 2332.700 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 1745.520 15.380 1747.120 32.270 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 1745.520 767.505 1747.120 792.270 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 1745.520 1527.505 1747.120 1552.270 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 1745.520 2287.505 1747.120 2332.700 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 1935.520 15.380 1937.120 32.270 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 1935.520 767.530 1937.120 792.270 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 1935.520 1527.530 1937.120 1552.270 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 1935.520 2287.530 1937.120 2332.700 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 2125.520 15.380 2127.120 30.510 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 2125.520 768.115 2127.120 790.510 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 2125.520 1528.115 2127.120 1550.510 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 2125.520 2288.115 2127.120 2332.700 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 120.440 23.220 122.040 772.540 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 208.360 783.700 209.960 1533.020 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 296.280 1544.180 297.880 2293.500 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 120.440 783.700 122.040 1533.020 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 208.360 23.220 209.960 772.540 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 384.200 1544.180 385.800 2293.500 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 120.440 1544.180 122.040 2293.500 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 296.280 23.220 297.880 772.540 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 384.200 783.700 385.800 1533.020 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 208.360 1544.180 209.960 2293.500 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 296.280 783.700 297.880 1533.020 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 384.200 23.220 385.800 772.540 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 472.120 23.220 473.720 772.540 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 560.040 783.700 561.640 1533.020 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 648.520 1544.180 650.120 2293.500 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 472.120 783.700 473.720 1533.020 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 560.040 23.220 561.640 772.540 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 736.440 1544.180 738.040 2293.500 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 472.120 1544.180 473.720 2293.500 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 648.520 23.220 650.120 772.540 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 736.440 783.700 738.040 1533.020 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 560.040 1544.180 561.640 2293.500 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 648.520 783.700 650.120 1533.020 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 736.440 23.220 738.040 772.540 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 824.360 23.220 825.960 772.540 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 912.280 783.700 913.880 1533.020 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 1000.200 1544.180 1001.800 2293.500 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 824.360 783.700 825.960 1533.020 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 912.280 23.220 913.880 772.540 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 1088.120 1544.180 1089.720 2293.500 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 824.360 1544.180 825.960 2293.500 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 1000.200 23.220 1001.800 772.540 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 1088.120 783.700 1089.720 1533.020 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 912.280 1544.180 913.880 2293.500 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 1000.200 783.700 1001.800 1533.020 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 1088.120 23.220 1089.720 772.540 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 1264.520 23.220 1266.120 772.540 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 1347.400 783.700 1349.000 1529.100 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 1440.360 1544.180 1441.960 2293.500 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 1264.520 783.700 1266.120 1533.020 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 1347.400 23.220 1349.000 768.620 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 1528.280 1544.180 1529.880 2293.500 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 1264.520 1544.180 1266.120 2293.500 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 1440.360 23.220 1441.960 772.540 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 1528.280 783.700 1529.880 1533.020 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 1347.400 1544.180 1349.000 2289.580 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 1440.360 783.700 1441.960 1533.020 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 1528.280 23.220 1529.880 772.540 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 1616.200 23.220 1617.800 772.540 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 1704.120 783.700 1705.720 1533.020 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 1792.040 1544.180 1793.640 2293.500 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 1616.200 783.700 1617.800 1533.020 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 1704.120 23.220 1705.720 772.540 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 1880.520 1544.180 1882.120 2293.500 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 1616.200 1544.180 1617.800 2293.500 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 1792.040 23.220 1793.640 772.540 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 1880.520 783.700 1882.120 1533.020 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 1704.120 1544.180 1705.720 2293.500 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 1792.040 783.700 1793.640 1533.020 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 1880.520 23.220 1882.120 772.540 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 1968.440 23.220 1970.040 772.540 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 2056.360 783.700 2057.960 1533.020 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 2153.800 1544.180 2155.400 2293.500 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 1968.440 783.700 1970.040 1533.020 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 2056.360 23.220 2057.960 772.540 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 1968.440 1544.180 1970.040 2293.500 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 2153.800 23.220 2155.400 772.540 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 2056.360 1544.180 2057.960 2293.500 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 2153.800 783.700 2155.400 1533.020 ;
+ END
+ END VSS
+ PIN wb_ack_o
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT 1.000 547.680 4.000 548.240 ;
+ END
+ END wb_ack_o
+ PIN wb_adr_i[0]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 2039.520 2346.000 2040.080 2349.000 ;
+ END
+ END wb_adr_i[0]
+ PIN wb_adr_i[1]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 1095.360 1.000 1095.920 4.000 ;
+ END
+ END wb_adr_i[1]
+ PIN wb_adr_i[2]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 665.280 2346.000 665.840 2349.000 ;
+ END
+ END wb_adr_i[2]
+ PIN wb_adr_i[3]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT 1.000 823.200 4.000 823.760 ;
+ END
+ END wb_adr_i[3]
+ PIN wb_adr_i[4]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT 2171.000 840.000 2174.000 840.560 ;
+ END
+ END wb_adr_i[4]
+ PIN wb_adr_i[5]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 1216.320 2346.000 1216.880 2349.000 ;
+ END
+ END wb_adr_i[5]
+ PIN wb_adr_i[6]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT 2171.000 16.800 2174.000 17.360 ;
+ END
+ END wb_adr_i[6]
+ PIN wb_adr_i[7]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT 2171.000 1391.040 2174.000 1391.600 ;
+ END
+ END wb_adr_i[7]
+ PIN wb_adr_i[8]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 1918.560 1.000 1919.120 4.000 ;
+ END
+ END wb_adr_i[8]
+ PIN wb_adr_i[9]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT 2171.000 1663.200 2174.000 1663.760 ;
+ END
+ END wb_adr_i[9]
+ PIN wb_clk_i
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT 1.000 272.160 4.000 272.720 ;
+ END
+ END wb_clk_i
+ PIN wb_cyc_i
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 0.000 1.000 0.560 4.000 ;
+ END
+ END wb_cyc_i
+ PIN wb_dat_i[0]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 1488.480 2346.000 1489.040 2349.000 ;
+ END
+ END wb_dat_i[0]
+ PIN wb_dat_i[1]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 1764.000 2346.000 1764.560 2349.000 ;
+ END
+ END wb_dat_i[1]
+ PIN wb_dat_i[2]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT 1.000 1646.400 4.000 1646.960 ;
+ END
+ END wb_dat_i[2]
+ PIN wb_dat_i[3]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 389.760 2346.000 390.320 2349.000 ;
+ END
+ END wb_dat_i[3]
+ PIN wb_dat_i[4]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 1646.400 1.000 1646.960 4.000 ;
+ END
+ END wb_dat_i[4]
+ PIN wb_dat_i[5]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT 1.000 1918.560 4.000 1919.120 ;
+ END
+ END wb_dat_i[5]
+ PIN wb_dat_i[6]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT 2171.000 292.320 2174.000 292.880 ;
+ END
+ END wb_dat_i[6]
+ PIN wb_dat_i[7]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 272.160 1.000 272.720 4.000 ;
+ END
+ END wb_dat_i[7]
+ PIN wb_dat_o[0]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 547.680 1.000 548.240 4.000 ;
+ END
+ END wb_dat_o[0]
+ PIN wb_dat_o[1]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 117.600 2346.000 118.160 2349.000 ;
+ END
+ END wb_dat_o[1]
+ PIN wb_dat_o[2]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT 2171.000 564.480 2174.000 565.040 ;
+ END
+ END wb_dat_o[2]
+ PIN wb_dat_o[3]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 823.200 1.000 823.760 4.000 ;
+ END
+ END wb_dat_o[3]
+ PIN wb_dat_o[4]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT 2171.000 1938.720 2174.000 1939.280 ;
+ END
+ END wb_dat_o[4]
+ PIN wb_dat_o[5]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT 2171.000 2214.240 2174.000 2214.800 ;
+ END
+ END wb_dat_o[5]
+ PIN wb_dat_o[6]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT 1.000 1370.880 4.000 1371.440 ;
+ END
+ END wb_dat_o[6]
+ PIN wb_dat_o[7]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 940.800 2346.000 941.360 2349.000 ;
+ END
+ END wb_dat_o[7]
+ PIN wb_rst_i
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 1370.880 1.000 1371.440 4.000 ;
+ END
+ END wb_rst_i
+ PIN wb_sel_i
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT 1.000 1095.360 4.000 1095.920 ;
+ END
+ END wb_sel_i
+ PIN wb_stb_i
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT 1.000 2194.080 4.000 2194.640 ;
+ END
+ END wb_stb_i
+ PIN wb_we_i
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT 2171.000 1115.520 2174.000 1116.080 ;
+ END
+ END wb_we_i
+ OBS
+ LAYER Metal1 ;
+ RECT 6.720 15.380 2167.760 2332.700 ;
+ LAYER Metal2 ;
+ RECT 8.540 2345.700 117.300 2346.000 ;
+ RECT 118.460 2345.700 389.460 2346.000 ;
+ RECT 390.620 2345.700 664.980 2346.000 ;
+ RECT 666.140 2345.700 940.500 2346.000 ;
+ RECT 941.660 2345.700 1216.020 2346.000 ;
+ RECT 1217.180 2345.700 1488.180 2346.000 ;
+ RECT 1489.340 2345.700 1763.700 2346.000 ;
+ RECT 1764.860 2345.700 2039.220 2346.000 ;
+ RECT 2040.380 2345.700 2165.380 2346.000 ;
+ RECT 8.540 4.300 2165.380 2345.700 ;
+ RECT 8.540 1.770 271.860 4.300 ;
+ RECT 273.020 1.770 547.380 4.300 ;
+ RECT 548.540 1.770 822.900 4.300 ;
+ RECT 824.060 1.770 1095.060 4.300 ;
+ RECT 1096.220 1.770 1370.580 4.300 ;
+ RECT 1371.740 1.770 1646.100 4.300 ;
+ RECT 1647.260 1.770 1918.260 4.300 ;
+ RECT 1919.420 1.770 2165.380 4.300 ;
+ LAYER Metal3 ;
+ RECT 4.000 2215.100 2171.000 2332.540 ;
+ RECT 4.000 2213.940 2170.700 2215.100 ;
+ RECT 4.000 2194.940 2171.000 2213.940 ;
+ RECT 4.300 2193.780 2171.000 2194.940 ;
+ RECT 4.000 1939.580 2171.000 2193.780 ;
+ RECT 4.000 1938.420 2170.700 1939.580 ;
+ RECT 4.000 1919.420 2171.000 1938.420 ;
+ RECT 4.300 1918.260 2171.000 1919.420 ;
+ RECT 4.000 1664.060 2171.000 1918.260 ;
+ RECT 4.000 1662.900 2170.700 1664.060 ;
+ RECT 4.000 1647.260 2171.000 1662.900 ;
+ RECT 4.300 1646.100 2171.000 1647.260 ;
+ RECT 4.000 1391.900 2171.000 1646.100 ;
+ RECT 4.000 1390.740 2170.700 1391.900 ;
+ RECT 4.000 1371.740 2171.000 1390.740 ;
+ RECT 4.300 1370.580 2171.000 1371.740 ;
+ RECT 4.000 1116.380 2171.000 1370.580 ;
+ RECT 4.000 1115.220 2170.700 1116.380 ;
+ RECT 4.000 1096.220 2171.000 1115.220 ;
+ RECT 4.300 1095.060 2171.000 1096.220 ;
+ RECT 4.000 840.860 2171.000 1095.060 ;
+ RECT 4.000 839.700 2170.700 840.860 ;
+ RECT 4.000 824.060 2171.000 839.700 ;
+ RECT 4.300 822.900 2171.000 824.060 ;
+ RECT 4.000 565.340 2171.000 822.900 ;
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+ RECT 4.000 548.540 2171.000 564.180 ;
+ RECT 4.300 547.380 2171.000 548.540 ;
+ RECT 4.000 293.180 2171.000 547.380 ;
+ RECT 4.000 292.020 2170.700 293.180 ;
+ RECT 4.000 273.020 2171.000 292.020 ;
+ RECT 4.300 271.860 2171.000 273.020 ;
+ RECT 4.000 17.660 2171.000 271.860 ;
+ RECT 4.000 16.500 2170.700 17.660 ;
+ RECT 4.000 1.260 2171.000 16.500 ;
+ LAYER Metal4 ;
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+ RECT 37.420 2293.800 215.620 2330.070 ;
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+ RECT 1783.860 1543.880 1791.740 2293.800 ;
+ RECT 1793.940 1543.880 1870.140 2293.800 ;
+ RECT 1872.340 1543.880 1880.220 2293.800 ;
+ RECT 1882.420 2287.205 1925.620 2293.800 ;
+ RECT 1927.820 2287.230 1935.220 2330.070 ;
+ RECT 1937.420 2293.800 2115.620 2330.070 ;
+ RECT 1937.420 2287.230 1958.060 2293.800 ;
+ RECT 1927.820 2287.205 1958.060 2287.230 ;
+ RECT 1882.420 1552.570 1958.060 2287.205 ;
+ RECT 1882.420 1543.880 1925.620 1552.570 ;
+ RECT 1747.420 1533.320 1925.620 1543.880 ;
+ RECT 1747.420 1527.205 1781.660 1533.320 ;
+ RECT 1706.020 792.570 1781.660 1527.205 ;
+ RECT 1706.020 783.400 1735.620 792.570 ;
+ RECT 1557.420 772.840 1735.620 783.400 ;
+ RECT 1557.420 767.205 1605.820 772.840 ;
+ RECT 1530.180 32.570 1605.820 767.205 ;
+ RECT 1530.180 30.020 1555.220 32.570 ;
+ RECT 1530.180 22.920 1545.620 30.020 ;
+ RECT 1367.420 15.080 1545.620 22.920 ;
+ RECT 1547.820 15.080 1555.220 30.020 ;
+ RECT 1557.420 22.920 1605.820 32.570 ;
+ RECT 1608.020 22.920 1615.900 772.840 ;
+ RECT 1618.100 22.920 1693.740 772.840 ;
+ RECT 1695.940 22.920 1703.820 772.840 ;
+ RECT 1706.020 767.205 1735.620 772.840 ;
+ RECT 1737.820 767.205 1745.220 792.570 ;
+ RECT 1747.420 783.400 1781.660 792.570 ;
+ RECT 1783.860 783.400 1791.740 1533.320 ;
+ RECT 1793.940 783.400 1870.140 1533.320 ;
+ RECT 1872.340 783.400 1880.220 1533.320 ;
+ RECT 1882.420 1527.205 1925.620 1533.320 ;
+ RECT 1927.820 1527.230 1935.220 1552.570 ;
+ RECT 1937.420 1543.880 1958.060 1552.570 ;
+ RECT 1960.260 1543.880 1968.140 2293.800 ;
+ RECT 1970.340 1543.880 2045.980 2293.800 ;
+ RECT 2048.180 1543.880 2056.060 2293.800 ;
+ RECT 2058.260 2287.230 2115.620 2293.800 ;
+ RECT 2117.820 2287.815 2125.220 2330.070 ;
+ RECT 2127.420 2293.800 2147.460 2330.070 ;
+ RECT 2127.420 2287.815 2143.420 2293.800 ;
+ RECT 2117.820 2287.230 2143.420 2287.815 ;
+ RECT 2058.260 1552.545 2143.420 2287.230 ;
+ RECT 2058.260 1543.880 2115.620 1552.545 ;
+ RECT 1937.420 1533.320 2115.620 1543.880 ;
+ RECT 1937.420 1527.230 1958.060 1533.320 ;
+ RECT 1927.820 1527.205 1958.060 1527.230 ;
+ RECT 1882.420 792.570 1958.060 1527.205 ;
+ RECT 1882.420 783.400 1925.620 792.570 ;
+ RECT 1747.420 772.840 1925.620 783.400 ;
+ RECT 1747.420 767.205 1781.660 772.840 ;
+ RECT 1706.020 32.570 1781.660 767.205 ;
+ RECT 1706.020 22.920 1735.620 32.570 ;
+ RECT 1557.420 15.080 1735.620 22.920 ;
+ RECT 1737.820 15.080 1745.220 32.570 ;
+ RECT 1747.420 22.920 1781.660 32.570 ;
+ RECT 1783.860 22.920 1791.740 772.840 ;
+ RECT 1793.940 22.920 1870.140 772.840 ;
+ RECT 1872.340 22.920 1880.220 772.840 ;
+ RECT 1882.420 767.205 1925.620 772.840 ;
+ RECT 1927.820 767.230 1935.220 792.570 ;
+ RECT 1937.420 783.400 1958.060 792.570 ;
+ RECT 1960.260 783.400 1968.140 1533.320 ;
+ RECT 1970.340 783.400 2045.980 1533.320 ;
+ RECT 2048.180 783.400 2056.060 1533.320 ;
+ RECT 2058.260 1527.230 2115.620 1533.320 ;
+ RECT 2117.820 1550.810 2143.420 1552.545 ;
+ RECT 2117.820 1527.815 2125.220 1550.810 ;
+ RECT 2127.420 1543.880 2143.420 1550.810 ;
+ RECT 2145.620 1543.880 2147.460 2293.800 ;
+ RECT 2127.420 1533.320 2147.460 1543.880 ;
+ RECT 2127.420 1527.815 2143.420 1533.320 ;
+ RECT 2117.820 1527.230 2143.420 1527.815 ;
+ RECT 2058.260 792.545 2143.420 1527.230 ;
+ RECT 2058.260 783.400 2115.620 792.545 ;
+ RECT 1937.420 772.840 2115.620 783.400 ;
+ RECT 1937.420 767.230 1958.060 772.840 ;
+ RECT 1927.820 767.205 1958.060 767.230 ;
+ RECT 1882.420 32.570 1958.060 767.205 ;
+ RECT 1882.420 22.920 1925.620 32.570 ;
+ RECT 1747.420 15.080 1925.620 22.920 ;
+ RECT 1927.820 15.080 1935.220 32.570 ;
+ RECT 1937.420 22.920 1958.060 32.570 ;
+ RECT 1960.260 22.920 1968.140 772.840 ;
+ RECT 1970.340 22.920 2045.980 772.840 ;
+ RECT 2048.180 22.920 2056.060 772.840 ;
+ RECT 2058.260 767.230 2115.620 772.840 ;
+ RECT 2117.820 790.810 2143.420 792.545 ;
+ RECT 2117.820 767.815 2125.220 790.810 ;
+ RECT 2127.420 783.400 2143.420 790.810 ;
+ RECT 2145.620 783.400 2147.460 1533.320 ;
+ RECT 2127.420 772.840 2147.460 783.400 ;
+ RECT 2127.420 767.815 2143.420 772.840 ;
+ RECT 2117.820 767.230 2143.420 767.815 ;
+ RECT 2058.260 32.545 2143.420 767.230 ;
+ RECT 2058.260 22.920 2115.620 32.545 ;
+ RECT 1937.420 15.080 2115.620 22.920 ;
+ RECT 2117.820 30.810 2143.420 32.545 ;
+ RECT 2117.820 15.080 2125.220 30.810 ;
+ RECT 2127.420 22.920 2143.420 30.810 ;
+ RECT 2145.620 22.920 2147.460 772.840 ;
+ RECT 2127.420 15.080 2147.460 22.920 ;
+ RECT 16.940 1.210 2147.460 15.080 ;
+ LAYER Metal5 ;
+ RECT 10 0 2165 34.5 ;
+ RECT 10 49.5 2165 79.5 ;
+ RECT 10 94.5 2165 124.5 ;
+ RECT 10 139.5 2165 169.5 ;
+ RECT 10 184.5 2165 214.5 ;
+ RECT 10 229.5 2165 259.5 ;
+ RECT 10 274.5 2165 304.5 ;
+ RECT 10 319.5 2165 349.5 ;
+ RECT 10 364.5 2165 394.5 ;
+ RECT 10 409.5 2165 439.5 ;
+ RECT 10 454.5 2165 484.5 ;
+ RECT 10 499.5 2165 529.5 ;
+ RECT 10 544.5 2165 574.5 ;
+ RECT 10 589.5 2165 619.5 ;
+ RECT 10 634.5 2165 664.5 ;
+ RECT 10 679.5 2165 709.5 ;
+ RECT 10 724.5 2165 754.5 ;
+ RECT 10 769.5 2165 799.5 ;
+ RECT 10 814.5 2165 844.5 ;
+ RECT 10 859.5 2165 889.5 ;
+ RECT 10 904.5 2165 934.5 ;
+ RECT 10 949.5 2165 979.5 ;
+ RECT 10 994.5 2165 1024.5 ;
+ RECT 10 1039.5 2165 1069.5 ;
+ RECT 10 1084.5 2165 1114.5 ;
+ RECT 10 1129.5 2165 1159.5 ;
+ RECT 10 1174.5 2165 1204.5 ;
+ RECT 10 1219.5 2165 1249.5 ;
+ RECT 10 1264.5 2165 1294.5 ;
+ RECT 10 1309.5 2165 1339.5 ;
+ RECT 10 1354.5 2165 1384.5 ;
+ RECT 10 1399.5 2165 1429.5 ;
+ RECT 10 1444.5 2165 1474.5 ;
+ RECT 10 1489.5 2165 1519.5 ;
+ RECT 10 1534.5 2165 1564.5 ;
+ RECT 10 1579.5 2165 1609.5 ;
+ RECT 10 1624.5 2165 1654.5 ;
+ RECT 10 1669.5 2165 1699.5 ;
+ RECT 10 1714.5 2165 1744.5 ;
+ RECT 10 1759.5 2165 1789.5 ;
+ RECT 10 1804.5 2165 1834.5 ;
+ RECT 10 1849.5 2165 1879.5 ;
+ RECT 10 1894.5 2165 1924.5 ;
+ RECT 10 1939.5 2165 1969.5 ;
+ RECT 10 1984.5 2165 2014.5 ;
+ RECT 10 2029.5 2165 2059.5 ;
+ RECT 10 2074.5 2165 2104.5 ;
+ RECT 10 2119.5 2165 2149.5 ;
+ RECT 10 2164.5 2165 2194.5 ;
+ RECT 10 2209.5 2165 2239.5 ;
+ RECT 10 2254.5 2165 2284.5 ;
+ RECT 10 2299.5 2165 2329.5 ;
+ END
+END efuse_ctrl
+END LIBRARY
+
diff --git a/lef/fpga_struct_block.lef b/lef/fpga_struct_block.lef
new file mode 100644
index 0000000..4148b33
--- /dev/null
+++ b/lef/fpga_struct_block.lef
@@ -0,0 +1,1434 @@
+VERSION 5.7 ;
+ NOWIREEXTENSIONATPIN ON ;
+ DIVIDERCHAR "/" ;
+ BUSBITCHARS "[]" ;
+MACRO fpga_struct_block
+ CLASS BLOCK ;
+ FOREIGN fpga_struct_block ;
+ ORIGIN 0.000 0.000 ;
+ SIZE 288.390 BY 301.830 ;
+ PIN VDD
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER Metal4 ;
+ RECT 16.640 7.540 18.240 290.380 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 66.640 7.540 68.240 290.380 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 116.640 7.540 118.240 290.380 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 166.640 7.540 168.240 290.380 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 216.640 7.540 218.240 290.380 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 266.640 7.540 268.240 290.380 ;
+ END
+ END VDD
+ PIN VSS
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER Metal4 ;
+ RECT 41.640 7.540 43.240 290.380 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 91.640 7.540 93.240 290.380 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 141.640 7.540 143.240 290.380 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 191.640 7.540 193.240 290.380 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 241.640 7.540 243.240 290.380 ;
+ END
+ END VSS
+ PIN clk_i
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT 284.390 7.840 288.390 8.400 ;
+ END
+ END clk_i
+ PIN config_clk_i
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 8.960 297.830 9.520 301.830 ;
+ END
+ END config_clk_i
+ PIN config_ena_i
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 16.240 297.830 16.800 301.830 ;
+ END
+ END config_ena_i
+ PIN config_shift_i
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 23.520 297.830 24.080 301.830 ;
+ END
+ END config_shift_i
+ PIN config_shift_o
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 10.640 0.000 11.200 4.000 ;
+ END
+ END config_shift_o
+ PIN glb_rstn_i
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 30.800 297.830 31.360 301.830 ;
+ END
+ END glb_rstn_i
+ PIN inputs_down_i[0]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 34.160 0.000 34.720 4.000 ;
+ END
+ END inputs_down_i[0]
+ PIN inputs_down_i[10]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 112.560 0.000 113.120 4.000 ;
+ END
+ END inputs_down_i[10]
+ PIN inputs_down_i[11]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 120.400 0.000 120.960 4.000 ;
+ END
+ END inputs_down_i[11]
+ PIN inputs_down_i[12]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 128.240 0.000 128.800 4.000 ;
+ END
+ END inputs_down_i[12]
+ PIN inputs_down_i[13]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 136.080 0.000 136.640 4.000 ;
+ END
+ END inputs_down_i[13]
+ PIN inputs_down_i[14]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 143.920 0.000 144.480 4.000 ;
+ END
+ END inputs_down_i[14]
+ PIN inputs_down_i[15]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 151.760 0.000 152.320 4.000 ;
+ END
+ END inputs_down_i[15]
+ PIN inputs_down_i[16]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 159.600 0.000 160.160 4.000 ;
+ END
+ END inputs_down_i[16]
+ PIN inputs_down_i[17]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 167.440 0.000 168.000 4.000 ;
+ END
+ END inputs_down_i[17]
+ PIN inputs_down_i[18]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 175.280 0.000 175.840 4.000 ;
+ END
+ END inputs_down_i[18]
+ PIN inputs_down_i[19]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 183.120 0.000 183.680 4.000 ;
+ END
+ END inputs_down_i[19]
+ PIN inputs_down_i[1]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 42.000 0.000 42.560 4.000 ;
+ END
+ END inputs_down_i[1]
+ PIN inputs_down_i[20]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 190.960 0.000 191.520 4.000 ;
+ END
+ END inputs_down_i[20]
+ PIN inputs_down_i[21]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 198.800 0.000 199.360 4.000 ;
+ END
+ END inputs_down_i[21]
+ PIN inputs_down_i[22]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 206.640 0.000 207.200 4.000 ;
+ END
+ END inputs_down_i[22]
+ PIN inputs_down_i[23]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 214.480 0.000 215.040 4.000 ;
+ END
+ END inputs_down_i[23]
+ PIN inputs_down_i[24]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 222.320 0.000 222.880 4.000 ;
+ END
+ END inputs_down_i[24]
+ PIN inputs_down_i[25]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 230.160 0.000 230.720 4.000 ;
+ END
+ END inputs_down_i[25]
+ PIN inputs_down_i[26]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 238.000 0.000 238.560 4.000 ;
+ END
+ END inputs_down_i[26]
+ PIN inputs_down_i[27]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 245.840 0.000 246.400 4.000 ;
+ END
+ END inputs_down_i[27]
+ PIN inputs_down_i[28]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 253.680 0.000 254.240 4.000 ;
+ END
+ END inputs_down_i[28]
+ PIN inputs_down_i[29]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 261.520 0.000 262.080 4.000 ;
+ END
+ END inputs_down_i[29]
+ PIN inputs_down_i[2]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 49.840 0.000 50.400 4.000 ;
+ END
+ END inputs_down_i[2]
+ PIN inputs_down_i[30]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 269.360 0.000 269.920 4.000 ;
+ END
+ END inputs_down_i[30]
+ PIN inputs_down_i[31]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 277.200 0.000 277.760 4.000 ;
+ END
+ END inputs_down_i[31]
+ PIN inputs_down_i[3]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 57.680 0.000 58.240 4.000 ;
+ END
+ END inputs_down_i[3]
+ PIN inputs_down_i[4]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 65.520 0.000 66.080 4.000 ;
+ END
+ END inputs_down_i[4]
+ PIN inputs_down_i[5]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 73.360 0.000 73.920 4.000 ;
+ END
+ END inputs_down_i[5]
+ PIN inputs_down_i[6]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 81.200 0.000 81.760 4.000 ;
+ END
+ END inputs_down_i[6]
+ PIN inputs_down_i[7]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 89.040 0.000 89.600 4.000 ;
+ END
+ END inputs_down_i[7]
+ PIN inputs_down_i[8]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 96.880 0.000 97.440 4.000 ;
+ END
+ END inputs_down_i[8]
+ PIN inputs_down_i[9]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 104.720 0.000 105.280 4.000 ;
+ END
+ END inputs_down_i[9]
+ PIN inputs_left_i[0]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT 0.000 28.560 4.000 29.120 ;
+ END
+ END inputs_left_i[0]
+ PIN inputs_left_i[10]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT 0.000 112.560 4.000 113.120 ;
+ END
+ END inputs_left_i[10]
+ PIN inputs_left_i[11]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT 0.000 120.960 4.000 121.520 ;
+ END
+ END inputs_left_i[11]
+ PIN inputs_left_i[12]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT 0.000 129.360 4.000 129.920 ;
+ END
+ END inputs_left_i[12]
+ PIN inputs_left_i[13]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT 0.000 137.760 4.000 138.320 ;
+ END
+ END inputs_left_i[13]
+ PIN inputs_left_i[14]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT 0.000 146.160 4.000 146.720 ;
+ END
+ END inputs_left_i[14]
+ PIN inputs_left_i[15]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT 0.000 154.560 4.000 155.120 ;
+ END
+ END inputs_left_i[15]
+ PIN inputs_left_i[16]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT 0.000 162.960 4.000 163.520 ;
+ END
+ END inputs_left_i[16]
+ PIN inputs_left_i[17]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT 0.000 171.360 4.000 171.920 ;
+ END
+ END inputs_left_i[17]
+ PIN inputs_left_i[18]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT 0.000 179.760 4.000 180.320 ;
+ END
+ END inputs_left_i[18]
+ PIN inputs_left_i[19]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT 0.000 188.160 4.000 188.720 ;
+ END
+ END inputs_left_i[19]
+ PIN inputs_left_i[1]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT 0.000 36.960 4.000 37.520 ;
+ END
+ END inputs_left_i[1]
+ PIN inputs_left_i[20]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT 0.000 196.560 4.000 197.120 ;
+ END
+ END inputs_left_i[20]
+ PIN inputs_left_i[21]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT 0.000 204.960 4.000 205.520 ;
+ END
+ END inputs_left_i[21]
+ PIN inputs_left_i[22]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT 0.000 213.360 4.000 213.920 ;
+ END
+ END inputs_left_i[22]
+ PIN inputs_left_i[23]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT 0.000 221.760 4.000 222.320 ;
+ END
+ END inputs_left_i[23]
+ PIN inputs_left_i[24]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT 0.000 230.160 4.000 230.720 ;
+ END
+ END inputs_left_i[24]
+ PIN inputs_left_i[25]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT 0.000 238.560 4.000 239.120 ;
+ END
+ END inputs_left_i[25]
+ PIN inputs_left_i[26]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT 0.000 246.960 4.000 247.520 ;
+ END
+ END inputs_left_i[26]
+ PIN inputs_left_i[27]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT 0.000 255.360 4.000 255.920 ;
+ END
+ END inputs_left_i[27]
+ PIN inputs_left_i[28]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT 0.000 263.760 4.000 264.320 ;
+ END
+ END inputs_left_i[28]
+ PIN inputs_left_i[29]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT 0.000 272.160 4.000 272.720 ;
+ END
+ END inputs_left_i[29]
+ PIN inputs_left_i[2]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT 0.000 45.360 4.000 45.920 ;
+ END
+ END inputs_left_i[2]
+ PIN inputs_left_i[30]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT 0.000 280.560 4.000 281.120 ;
+ END
+ END inputs_left_i[30]
+ PIN inputs_left_i[31]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT 0.000 288.960 4.000 289.520 ;
+ END
+ END inputs_left_i[31]
+ PIN inputs_left_i[3]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT 0.000 53.760 4.000 54.320 ;
+ END
+ END inputs_left_i[3]
+ PIN inputs_left_i[4]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT 0.000 62.160 4.000 62.720 ;
+ END
+ END inputs_left_i[4]
+ PIN inputs_left_i[5]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT 0.000 70.560 4.000 71.120 ;
+ END
+ END inputs_left_i[5]
+ PIN inputs_left_i[6]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT 0.000 78.960 4.000 79.520 ;
+ END
+ END inputs_left_i[6]
+ PIN inputs_left_i[7]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT 0.000 87.360 4.000 87.920 ;
+ END
+ END inputs_left_i[7]
+ PIN inputs_left_i[8]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT 0.000 95.760 4.000 96.320 ;
+ END
+ END inputs_left_i[8]
+ PIN inputs_left_i[9]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT 0.000 104.160 4.000 104.720 ;
+ END
+ END inputs_left_i[9]
+ PIN inputs_right_i[0]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT 284.390 33.040 288.390 33.600 ;
+ END
+ END inputs_right_i[0]
+ PIN inputs_right_i[10]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT 284.390 117.040 288.390 117.600 ;
+ END
+ END inputs_right_i[10]
+ PIN inputs_right_i[11]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT 284.390 125.440 288.390 126.000 ;
+ END
+ END inputs_right_i[11]
+ PIN inputs_right_i[12]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT 284.390 133.840 288.390 134.400 ;
+ END
+ END inputs_right_i[12]
+ PIN inputs_right_i[13]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT 284.390 142.240 288.390 142.800 ;
+ END
+ END inputs_right_i[13]
+ PIN inputs_right_i[14]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT 284.390 150.640 288.390 151.200 ;
+ END
+ END inputs_right_i[14]
+ PIN inputs_right_i[15]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT 284.390 159.040 288.390 159.600 ;
+ END
+ END inputs_right_i[15]
+ PIN inputs_right_i[16]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT 284.390 167.440 288.390 168.000 ;
+ END
+ END inputs_right_i[16]
+ PIN inputs_right_i[17]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT 284.390 175.840 288.390 176.400 ;
+ END
+ END inputs_right_i[17]
+ PIN inputs_right_i[18]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT 284.390 184.240 288.390 184.800 ;
+ END
+ END inputs_right_i[18]
+ PIN inputs_right_i[19]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT 284.390 192.640 288.390 193.200 ;
+ END
+ END inputs_right_i[19]
+ PIN inputs_right_i[1]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT 284.390 41.440 288.390 42.000 ;
+ END
+ END inputs_right_i[1]
+ PIN inputs_right_i[20]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT 284.390 201.040 288.390 201.600 ;
+ END
+ END inputs_right_i[20]
+ PIN inputs_right_i[21]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT 284.390 209.440 288.390 210.000 ;
+ END
+ END inputs_right_i[21]
+ PIN inputs_right_i[22]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT 284.390 217.840 288.390 218.400 ;
+ END
+ END inputs_right_i[22]
+ PIN inputs_right_i[23]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT 284.390 226.240 288.390 226.800 ;
+ END
+ END inputs_right_i[23]
+ PIN inputs_right_i[24]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT 284.390 234.640 288.390 235.200 ;
+ END
+ END inputs_right_i[24]
+ PIN inputs_right_i[25]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT 284.390 243.040 288.390 243.600 ;
+ END
+ END inputs_right_i[25]
+ PIN inputs_right_i[26]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT 284.390 251.440 288.390 252.000 ;
+ END
+ END inputs_right_i[26]
+ PIN inputs_right_i[27]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT 284.390 259.840 288.390 260.400 ;
+ END
+ END inputs_right_i[27]
+ PIN inputs_right_i[28]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT 284.390 268.240 288.390 268.800 ;
+ END
+ END inputs_right_i[28]
+ PIN inputs_right_i[29]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT 284.390 276.640 288.390 277.200 ;
+ END
+ END inputs_right_i[29]
+ PIN inputs_right_i[2]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT 284.390 49.840 288.390 50.400 ;
+ END
+ END inputs_right_i[2]
+ PIN inputs_right_i[30]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT 284.390 285.040 288.390 285.600 ;
+ END
+ END inputs_right_i[30]
+ PIN inputs_right_i[31]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT 284.390 293.440 288.390 294.000 ;
+ END
+ END inputs_right_i[31]
+ PIN inputs_right_i[3]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT 284.390 58.240 288.390 58.800 ;
+ END
+ END inputs_right_i[3]
+ PIN inputs_right_i[4]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT 284.390 66.640 288.390 67.200 ;
+ END
+ END inputs_right_i[4]
+ PIN inputs_right_i[5]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT 284.390 75.040 288.390 75.600 ;
+ END
+ END inputs_right_i[5]
+ PIN inputs_right_i[6]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT 284.390 83.440 288.390 84.000 ;
+ END
+ END inputs_right_i[6]
+ PIN inputs_right_i[7]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT 284.390 91.840 288.390 92.400 ;
+ END
+ END inputs_right_i[7]
+ PIN inputs_right_i[8]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT 284.390 100.240 288.390 100.800 ;
+ END
+ END inputs_right_i[8]
+ PIN inputs_right_i[9]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT 284.390 108.640 288.390 109.200 ;
+ END
+ END inputs_right_i[9]
+ PIN inputs_up_i[0]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 52.640 297.830 53.200 301.830 ;
+ END
+ END inputs_up_i[0]
+ PIN inputs_up_i[10]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 125.440 297.830 126.000 301.830 ;
+ END
+ END inputs_up_i[10]
+ PIN inputs_up_i[11]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 132.720 297.830 133.280 301.830 ;
+ END
+ END inputs_up_i[11]
+ PIN inputs_up_i[12]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 140.000 297.830 140.560 301.830 ;
+ END
+ END inputs_up_i[12]
+ PIN inputs_up_i[13]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 147.280 297.830 147.840 301.830 ;
+ END
+ END inputs_up_i[13]
+ PIN inputs_up_i[14]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 154.560 297.830 155.120 301.830 ;
+ END
+ END inputs_up_i[14]
+ PIN inputs_up_i[15]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 161.840 297.830 162.400 301.830 ;
+ END
+ END inputs_up_i[15]
+ PIN inputs_up_i[16]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 169.120 297.830 169.680 301.830 ;
+ END
+ END inputs_up_i[16]
+ PIN inputs_up_i[17]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 176.400 297.830 176.960 301.830 ;
+ END
+ END inputs_up_i[17]
+ PIN inputs_up_i[18]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 183.680 297.830 184.240 301.830 ;
+ END
+ END inputs_up_i[18]
+ PIN inputs_up_i[19]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 190.960 297.830 191.520 301.830 ;
+ END
+ END inputs_up_i[19]
+ PIN inputs_up_i[1]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 59.920 297.830 60.480 301.830 ;
+ END
+ END inputs_up_i[1]
+ PIN inputs_up_i[20]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 198.240 297.830 198.800 301.830 ;
+ END
+ END inputs_up_i[20]
+ PIN inputs_up_i[21]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 205.520 297.830 206.080 301.830 ;
+ END
+ END inputs_up_i[21]
+ PIN inputs_up_i[22]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 212.800 297.830 213.360 301.830 ;
+ END
+ END inputs_up_i[22]
+ PIN inputs_up_i[23]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 220.080 297.830 220.640 301.830 ;
+ END
+ END inputs_up_i[23]
+ PIN inputs_up_i[24]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 227.360 297.830 227.920 301.830 ;
+ END
+ END inputs_up_i[24]
+ PIN inputs_up_i[25]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 234.640 297.830 235.200 301.830 ;
+ END
+ END inputs_up_i[25]
+ PIN inputs_up_i[26]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 241.920 297.830 242.480 301.830 ;
+ END
+ END inputs_up_i[26]
+ PIN inputs_up_i[27]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 249.200 297.830 249.760 301.830 ;
+ END
+ END inputs_up_i[27]
+ PIN inputs_up_i[28]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 256.480 297.830 257.040 301.830 ;
+ END
+ END inputs_up_i[28]
+ PIN inputs_up_i[29]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 263.760 297.830 264.320 301.830 ;
+ END
+ END inputs_up_i[29]
+ PIN inputs_up_i[2]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 67.200 297.830 67.760 301.830 ;
+ END
+ END inputs_up_i[2]
+ PIN inputs_up_i[30]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 271.040 297.830 271.600 301.830 ;
+ END
+ END inputs_up_i[30]
+ PIN inputs_up_i[31]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 278.320 297.830 278.880 301.830 ;
+ END
+ END inputs_up_i[31]
+ PIN inputs_up_i[3]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 74.480 297.830 75.040 301.830 ;
+ END
+ END inputs_up_i[3]
+ PIN inputs_up_i[4]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 81.760 297.830 82.320 301.830 ;
+ END
+ END inputs_up_i[4]
+ PIN inputs_up_i[5]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 89.040 297.830 89.600 301.830 ;
+ END
+ END inputs_up_i[5]
+ PIN inputs_up_i[6]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 96.320 297.830 96.880 301.830 ;
+ END
+ END inputs_up_i[6]
+ PIN inputs_up_i[7]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 103.600 297.830 104.160 301.830 ;
+ END
+ END inputs_up_i[7]
+ PIN inputs_up_i[8]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 110.880 297.830 111.440 301.830 ;
+ END
+ END inputs_up_i[8]
+ PIN inputs_up_i[9]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 118.160 297.830 118.720 301.830 ;
+ END
+ END inputs_up_i[9]
+ PIN outputs_o[0]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 38.080 297.830 38.640 301.830 ;
+ END
+ END outputs_o[0]
+ PIN outputs_o[1]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT 284.390 16.240 288.390 16.800 ;
+ END
+ END outputs_o[1]
+ PIN outputs_o[2]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 18.480 0.000 19.040 4.000 ;
+ END
+ END outputs_o[2]
+ PIN outputs_o[3]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT 0.000 11.760 4.000 12.320 ;
+ END
+ END outputs_o[3]
+ PIN outputs_o[4]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 45.360 297.830 45.920 301.830 ;
+ END
+ END outputs_o[4]
+ PIN outputs_o[5]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT 284.390 24.640 288.390 25.200 ;
+ END
+ END outputs_o[5]
+ PIN outputs_o[6]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 26.320 0.000 26.880 4.000 ;
+ END
+ END outputs_o[6]
+ PIN outputs_o[7]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT 0.000 20.160 4.000 20.720 ;
+ END
+ END outputs_o[7]
+ OBS
+ LAYER Metal1 ;
+ RECT 1.120 7.540 286.720 293.290 ;
+ LAYER Metal2 ;
+ RECT 0.700 297.530 8.660 298.340 ;
+ RECT 9.820 297.530 15.940 298.340 ;
+ RECT 17.100 297.530 23.220 298.340 ;
+ RECT 24.380 297.530 30.500 298.340 ;
+ RECT 31.660 297.530 37.780 298.340 ;
+ RECT 38.940 297.530 45.060 298.340 ;
+ RECT 46.220 297.530 52.340 298.340 ;
+ RECT 53.500 297.530 59.620 298.340 ;
+ RECT 60.780 297.530 66.900 298.340 ;
+ RECT 68.060 297.530 74.180 298.340 ;
+ RECT 75.340 297.530 81.460 298.340 ;
+ RECT 82.620 297.530 88.740 298.340 ;
+ RECT 89.900 297.530 96.020 298.340 ;
+ RECT 97.180 297.530 103.300 298.340 ;
+ RECT 104.460 297.530 110.580 298.340 ;
+ RECT 111.740 297.530 117.860 298.340 ;
+ RECT 119.020 297.530 125.140 298.340 ;
+ RECT 126.300 297.530 132.420 298.340 ;
+ RECT 133.580 297.530 139.700 298.340 ;
+ RECT 140.860 297.530 146.980 298.340 ;
+ RECT 148.140 297.530 154.260 298.340 ;
+ RECT 155.420 297.530 161.540 298.340 ;
+ RECT 162.700 297.530 168.820 298.340 ;
+ RECT 169.980 297.530 176.100 298.340 ;
+ RECT 177.260 297.530 183.380 298.340 ;
+ RECT 184.540 297.530 190.660 298.340 ;
+ RECT 191.820 297.530 197.940 298.340 ;
+ RECT 199.100 297.530 205.220 298.340 ;
+ RECT 206.380 297.530 212.500 298.340 ;
+ RECT 213.660 297.530 219.780 298.340 ;
+ RECT 220.940 297.530 227.060 298.340 ;
+ RECT 228.220 297.530 234.340 298.340 ;
+ RECT 235.500 297.530 241.620 298.340 ;
+ RECT 242.780 297.530 248.900 298.340 ;
+ RECT 250.060 297.530 256.180 298.340 ;
+ RECT 257.340 297.530 263.460 298.340 ;
+ RECT 264.620 297.530 270.740 298.340 ;
+ RECT 271.900 297.530 278.020 298.340 ;
+ RECT 279.180 297.530 288.260 298.340 ;
+ RECT 0.700 4.300 288.260 297.530 ;
+ RECT 0.700 0.090 10.340 4.300 ;
+ RECT 11.500 0.090 18.180 4.300 ;
+ RECT 19.340 0.090 26.020 4.300 ;
+ RECT 27.180 0.090 33.860 4.300 ;
+ RECT 35.020 0.090 41.700 4.300 ;
+ RECT 42.860 0.090 49.540 4.300 ;
+ RECT 50.700 0.090 57.380 4.300 ;
+ RECT 58.540 0.090 65.220 4.300 ;
+ RECT 66.380 0.090 73.060 4.300 ;
+ RECT 74.220 0.090 80.900 4.300 ;
+ RECT 82.060 0.090 88.740 4.300 ;
+ RECT 89.900 0.090 96.580 4.300 ;
+ RECT 97.740 0.090 104.420 4.300 ;
+ RECT 105.580 0.090 112.260 4.300 ;
+ RECT 113.420 0.090 120.100 4.300 ;
+ RECT 121.260 0.090 127.940 4.300 ;
+ RECT 129.100 0.090 135.780 4.300 ;
+ RECT 136.940 0.090 143.620 4.300 ;
+ RECT 144.780 0.090 151.460 4.300 ;
+ RECT 152.620 0.090 159.300 4.300 ;
+ RECT 160.460 0.090 167.140 4.300 ;
+ RECT 168.300 0.090 174.980 4.300 ;
+ RECT 176.140 0.090 182.820 4.300 ;
+ RECT 183.980 0.090 190.660 4.300 ;
+ RECT 191.820 0.090 198.500 4.300 ;
+ RECT 199.660 0.090 206.340 4.300 ;
+ RECT 207.500 0.090 214.180 4.300 ;
+ RECT 215.340 0.090 222.020 4.300 ;
+ RECT 223.180 0.090 229.860 4.300 ;
+ RECT 231.020 0.090 237.700 4.300 ;
+ RECT 238.860 0.090 245.540 4.300 ;
+ RECT 246.700 0.090 253.380 4.300 ;
+ RECT 254.540 0.090 261.220 4.300 ;
+ RECT 262.380 0.090 269.060 4.300 ;
+ RECT 270.220 0.090 276.900 4.300 ;
+ RECT 278.060 0.090 288.260 4.300 ;
+ LAYER Metal3 ;
+ RECT 0.650 294.300 288.310 296.100 ;
+ RECT 0.650 293.140 284.090 294.300 ;
+ RECT 0.650 289.820 288.310 293.140 ;
+ RECT 4.300 288.660 288.310 289.820 ;
+ RECT 0.650 285.900 288.310 288.660 ;
+ RECT 0.650 284.740 284.090 285.900 ;
+ RECT 0.650 281.420 288.310 284.740 ;
+ RECT 4.300 280.260 288.310 281.420 ;
+ RECT 0.650 277.500 288.310 280.260 ;
+ RECT 0.650 276.340 284.090 277.500 ;
+ RECT 0.650 273.020 288.310 276.340 ;
+ RECT 4.300 271.860 288.310 273.020 ;
+ RECT 0.650 269.100 288.310 271.860 ;
+ RECT 0.650 267.940 284.090 269.100 ;
+ RECT 0.650 264.620 288.310 267.940 ;
+ RECT 4.300 263.460 288.310 264.620 ;
+ RECT 0.650 260.700 288.310 263.460 ;
+ RECT 0.650 259.540 284.090 260.700 ;
+ RECT 0.650 256.220 288.310 259.540 ;
+ RECT 4.300 255.060 288.310 256.220 ;
+ RECT 0.650 252.300 288.310 255.060 ;
+ RECT 0.650 251.140 284.090 252.300 ;
+ RECT 0.650 247.820 288.310 251.140 ;
+ RECT 4.300 246.660 288.310 247.820 ;
+ RECT 0.650 243.900 288.310 246.660 ;
+ RECT 0.650 242.740 284.090 243.900 ;
+ RECT 0.650 239.420 288.310 242.740 ;
+ RECT 4.300 238.260 288.310 239.420 ;
+ RECT 0.650 235.500 288.310 238.260 ;
+ RECT 0.650 234.340 284.090 235.500 ;
+ RECT 0.650 231.020 288.310 234.340 ;
+ RECT 4.300 229.860 288.310 231.020 ;
+ RECT 0.650 227.100 288.310 229.860 ;
+ RECT 0.650 225.940 284.090 227.100 ;
+ RECT 0.650 222.620 288.310 225.940 ;
+ RECT 4.300 221.460 288.310 222.620 ;
+ RECT 0.650 218.700 288.310 221.460 ;
+ RECT 0.650 217.540 284.090 218.700 ;
+ RECT 0.650 214.220 288.310 217.540 ;
+ RECT 4.300 213.060 288.310 214.220 ;
+ RECT 0.650 210.300 288.310 213.060 ;
+ RECT 0.650 209.140 284.090 210.300 ;
+ RECT 0.650 205.820 288.310 209.140 ;
+ RECT 4.300 204.660 288.310 205.820 ;
+ RECT 0.650 201.900 288.310 204.660 ;
+ RECT 0.650 200.740 284.090 201.900 ;
+ RECT 0.650 197.420 288.310 200.740 ;
+ RECT 4.300 196.260 288.310 197.420 ;
+ RECT 0.650 193.500 288.310 196.260 ;
+ RECT 0.650 192.340 284.090 193.500 ;
+ RECT 0.650 189.020 288.310 192.340 ;
+ RECT 4.300 187.860 288.310 189.020 ;
+ RECT 0.650 185.100 288.310 187.860 ;
+ RECT 0.650 183.940 284.090 185.100 ;
+ RECT 0.650 180.620 288.310 183.940 ;
+ RECT 4.300 179.460 288.310 180.620 ;
+ RECT 0.650 176.700 288.310 179.460 ;
+ RECT 0.650 175.540 284.090 176.700 ;
+ RECT 0.650 172.220 288.310 175.540 ;
+ RECT 4.300 171.060 288.310 172.220 ;
+ RECT 0.650 168.300 288.310 171.060 ;
+ RECT 0.650 167.140 284.090 168.300 ;
+ RECT 0.650 163.820 288.310 167.140 ;
+ RECT 4.300 162.660 288.310 163.820 ;
+ RECT 0.650 159.900 288.310 162.660 ;
+ RECT 0.650 158.740 284.090 159.900 ;
+ RECT 0.650 155.420 288.310 158.740 ;
+ RECT 4.300 154.260 288.310 155.420 ;
+ RECT 0.650 151.500 288.310 154.260 ;
+ RECT 0.650 150.340 284.090 151.500 ;
+ RECT 0.650 147.020 288.310 150.340 ;
+ RECT 4.300 145.860 288.310 147.020 ;
+ RECT 0.650 143.100 288.310 145.860 ;
+ RECT 0.650 141.940 284.090 143.100 ;
+ RECT 0.650 138.620 288.310 141.940 ;
+ RECT 4.300 137.460 288.310 138.620 ;
+ RECT 0.650 134.700 288.310 137.460 ;
+ RECT 0.650 133.540 284.090 134.700 ;
+ RECT 0.650 130.220 288.310 133.540 ;
+ RECT 4.300 129.060 288.310 130.220 ;
+ RECT 0.650 126.300 288.310 129.060 ;
+ RECT 0.650 125.140 284.090 126.300 ;
+ RECT 0.650 121.820 288.310 125.140 ;
+ RECT 4.300 120.660 288.310 121.820 ;
+ RECT 0.650 117.900 288.310 120.660 ;
+ RECT 0.650 116.740 284.090 117.900 ;
+ RECT 0.650 113.420 288.310 116.740 ;
+ RECT 4.300 112.260 288.310 113.420 ;
+ RECT 0.650 109.500 288.310 112.260 ;
+ RECT 0.650 108.340 284.090 109.500 ;
+ RECT 0.650 105.020 288.310 108.340 ;
+ RECT 4.300 103.860 288.310 105.020 ;
+ RECT 0.650 101.100 288.310 103.860 ;
+ RECT 0.650 99.940 284.090 101.100 ;
+ RECT 0.650 96.620 288.310 99.940 ;
+ RECT 4.300 95.460 288.310 96.620 ;
+ RECT 0.650 92.700 288.310 95.460 ;
+ RECT 0.650 91.540 284.090 92.700 ;
+ RECT 0.650 88.220 288.310 91.540 ;
+ RECT 4.300 87.060 288.310 88.220 ;
+ RECT 0.650 84.300 288.310 87.060 ;
+ RECT 0.650 83.140 284.090 84.300 ;
+ RECT 0.650 79.820 288.310 83.140 ;
+ RECT 4.300 78.660 288.310 79.820 ;
+ RECT 0.650 75.900 288.310 78.660 ;
+ RECT 0.650 74.740 284.090 75.900 ;
+ RECT 0.650 71.420 288.310 74.740 ;
+ RECT 4.300 70.260 288.310 71.420 ;
+ RECT 0.650 67.500 288.310 70.260 ;
+ RECT 0.650 66.340 284.090 67.500 ;
+ RECT 0.650 63.020 288.310 66.340 ;
+ RECT 4.300 61.860 288.310 63.020 ;
+ RECT 0.650 59.100 288.310 61.860 ;
+ RECT 0.650 57.940 284.090 59.100 ;
+ RECT 0.650 54.620 288.310 57.940 ;
+ RECT 4.300 53.460 288.310 54.620 ;
+ RECT 0.650 50.700 288.310 53.460 ;
+ RECT 0.650 49.540 284.090 50.700 ;
+ RECT 0.650 46.220 288.310 49.540 ;
+ RECT 4.300 45.060 288.310 46.220 ;
+ RECT 0.650 42.300 288.310 45.060 ;
+ RECT 0.650 41.140 284.090 42.300 ;
+ RECT 0.650 37.820 288.310 41.140 ;
+ RECT 4.300 36.660 288.310 37.820 ;
+ RECT 0.650 33.900 288.310 36.660 ;
+ RECT 0.650 32.740 284.090 33.900 ;
+ RECT 0.650 29.420 288.310 32.740 ;
+ RECT 4.300 28.260 288.310 29.420 ;
+ RECT 0.650 25.500 288.310 28.260 ;
+ RECT 0.650 24.340 284.090 25.500 ;
+ RECT 0.650 21.020 288.310 24.340 ;
+ RECT 4.300 19.860 288.310 21.020 ;
+ RECT 0.650 17.100 288.310 19.860 ;
+ RECT 0.650 15.940 284.090 17.100 ;
+ RECT 0.650 12.620 288.310 15.940 ;
+ RECT 4.300 11.460 288.310 12.620 ;
+ RECT 0.650 8.700 288.310 11.460 ;
+ RECT 0.650 7.540 284.090 8.700 ;
+ RECT 0.650 0.140 288.310 7.540 ;
+ LAYER Metal4 ;
+ RECT 5.180 8.490 16.340 288.310 ;
+ RECT 18.540 8.490 41.340 288.310 ;
+ RECT 43.540 8.490 66.340 288.310 ;
+ RECT 68.540 8.490 91.340 288.310 ;
+ RECT 93.540 8.490 116.340 288.310 ;
+ RECT 118.540 8.490 141.340 288.310 ;
+ RECT 143.540 8.490 166.340 288.310 ;
+ RECT 168.540 8.490 191.340 288.310 ;
+ RECT 193.540 8.490 216.340 288.310 ;
+ RECT 218.540 8.490 241.340 288.310 ;
+ RECT 243.540 8.490 266.340 288.310 ;
+ RECT 268.540 8.490 284.340 288.310 ;
+ END
+END fpga_struct_block
+END LIBRARY
+
diff --git a/lef/user_project_wrapper.lef b/lef/user_project_wrapper.lef
new file mode 100644
index 0000000..1d15bec
--- /dev/null
+++ b/lef/user_project_wrapper.lef
@@ -0,0 +1,5397 @@
+VERSION 5.7 ;
+ NOWIREEXTENSIONATPIN ON ;
+ DIVIDERCHAR "/" ;
+ BUSBITCHARS "[]" ;
+MACRO user_project_wrapper
+ CLASS BLOCK ;
+ FOREIGN user_project_wrapper ;
+ ORIGIN 0.000 0.000 ;
+ SIZE 2980.200 BY 2980.200 ;
+ PIN io_in[0]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT 2977.800 35.560 2985.000 36.680 ;
+ END
+ END io_in[0]
+ PIN io_in[10]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT 2977.800 2017.960 2985.000 2019.080 ;
+ END
+ END io_in[10]
+ PIN io_in[11]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT 2977.800 2216.200 2985.000 2217.320 ;
+ END
+ END io_in[11]
+ PIN io_in[12]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT 2977.800 2414.440 2985.000 2415.560 ;
+ END
+ END io_in[12]
+ PIN io_in[13]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT 2977.800 2612.680 2985.000 2613.800 ;
+ END
+ END io_in[13]
+ PIN io_in[14]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT 2977.800 2810.920 2985.000 2812.040 ;
+ END
+ END io_in[14]
+ PIN io_in[15]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 2923.480 2977.800 2924.600 2985.000 ;
+ END
+ END io_in[15]
+ PIN io_in[16]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 2592.520 2977.800 2593.640 2985.000 ;
+ END
+ END io_in[16]
+ PIN io_in[17]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 2261.560 2977.800 2262.680 2985.000 ;
+ END
+ END io_in[17]
+ PIN io_in[18]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 1930.600 2977.800 1931.720 2985.000 ;
+ END
+ END io_in[18]
+ PIN io_in[19]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 1599.640 2977.800 1600.760 2985.000 ;
+ END
+ END io_in[19]
+ PIN io_in[1]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT 2977.800 233.800 2985.000 234.920 ;
+ END
+ END io_in[1]
+ PIN io_in[20]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 1268.680 2977.800 1269.800 2985.000 ;
+ END
+ END io_in[20]
+ PIN io_in[21]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 937.720 2977.800 938.840 2985.000 ;
+ END
+ END io_in[21]
+ PIN io_in[22]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 606.760 2977.800 607.880 2985.000 ;
+ END
+ END io_in[22]
+ PIN io_in[23]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 275.800 2977.800 276.920 2985.000 ;
+ END
+ END io_in[23]
+ PIN io_in[24]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT -4.800 2935.800 2.400 2936.920 ;
+ END
+ END io_in[24]
+ PIN io_in[25]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT -4.800 2724.120 2.400 2725.240 ;
+ END
+ END io_in[25]
+ PIN io_in[26]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT -4.800 2512.440 2.400 2513.560 ;
+ END
+ END io_in[26]
+ PIN io_in[27]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT -4.800 2300.760 2.400 2301.880 ;
+ END
+ END io_in[27]
+ PIN io_in[28]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT -4.800 2089.080 2.400 2090.200 ;
+ END
+ END io_in[28]
+ PIN io_in[29]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT -4.800 1877.400 2.400 1878.520 ;
+ END
+ END io_in[29]
+ PIN io_in[2]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT 2977.800 432.040 2985.000 433.160 ;
+ END
+ END io_in[2]
+ PIN io_in[30]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT -4.800 1665.720 2.400 1666.840 ;
+ END
+ END io_in[30]
+ PIN io_in[31]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT -4.800 1454.040 2.400 1455.160 ;
+ END
+ END io_in[31]
+ PIN io_in[32]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT -4.800 1242.360 2.400 1243.480 ;
+ END
+ END io_in[32]
+ PIN io_in[33]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT -4.800 1030.680 2.400 1031.800 ;
+ END
+ END io_in[33]
+ PIN io_in[34]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT -4.800 819.000 2.400 820.120 ;
+ END
+ END io_in[34]
+ PIN io_in[35]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT -4.800 607.320 2.400 608.440 ;
+ END
+ END io_in[35]
+ PIN io_in[36]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT -4.800 395.640 2.400 396.760 ;
+ END
+ END io_in[36]
+ PIN io_in[37]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT -4.800 183.960 2.400 185.080 ;
+ END
+ END io_in[37]
+ PIN io_in[3]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT 2977.800 630.280 2985.000 631.400 ;
+ END
+ END io_in[3]
+ PIN io_in[4]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT 2977.800 828.520 2985.000 829.640 ;
+ END
+ END io_in[4]
+ PIN io_in[5]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT 2977.800 1026.760 2985.000 1027.880 ;
+ END
+ END io_in[5]
+ PIN io_in[6]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT 2977.800 1225.000 2985.000 1226.120 ;
+ END
+ END io_in[6]
+ PIN io_in[7]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT 2977.800 1423.240 2985.000 1424.360 ;
+ END
+ END io_in[7]
+ PIN io_in[8]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT 2977.800 1621.480 2985.000 1622.600 ;
+ END
+ END io_in[8]
+ PIN io_in[9]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT 2977.800 1819.720 2985.000 1820.840 ;
+ END
+ END io_in[9]
+ PIN io_oeb[0]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT 2977.800 167.720 2985.000 168.840 ;
+ END
+ END io_oeb[0]
+ PIN io_oeb[10]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT 2977.800 2150.120 2985.000 2151.240 ;
+ END
+ END io_oeb[10]
+ PIN io_oeb[11]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT 2977.800 2348.360 2985.000 2349.480 ;
+ END
+ END io_oeb[11]
+ PIN io_oeb[12]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT 2977.800 2546.600 2985.000 2547.720 ;
+ END
+ END io_oeb[12]
+ PIN io_oeb[13]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT 2977.800 2744.840 2985.000 2745.960 ;
+ END
+ END io_oeb[13]
+ PIN io_oeb[14]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT 2977.800 2943.080 2985.000 2944.200 ;
+ END
+ END io_oeb[14]
+ PIN io_oeb[15]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 2702.840 2977.800 2703.960 2985.000 ;
+ END
+ END io_oeb[15]
+ PIN io_oeb[16]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 2371.880 2977.800 2373.000 2985.000 ;
+ END
+ END io_oeb[16]
+ PIN io_oeb[17]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 2040.920 2977.800 2042.040 2985.000 ;
+ END
+ END io_oeb[17]
+ PIN io_oeb[18]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 1709.960 2977.800 1711.080 2985.000 ;
+ END
+ END io_oeb[18]
+ PIN io_oeb[19]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 1379.000 2977.800 1380.120 2985.000 ;
+ END
+ END io_oeb[19]
+ PIN io_oeb[1]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT 2977.800 365.960 2985.000 367.080 ;
+ END
+ END io_oeb[1]
+ PIN io_oeb[20]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 1048.040 2977.800 1049.160 2985.000 ;
+ END
+ END io_oeb[20]
+ PIN io_oeb[21]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 717.080 2977.800 718.200 2985.000 ;
+ END
+ END io_oeb[21]
+ PIN io_oeb[22]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 386.120 2977.800 387.240 2985.000 ;
+ END
+ END io_oeb[22]
+ PIN io_oeb[23]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 55.160 2977.800 56.280 2985.000 ;
+ END
+ END io_oeb[23]
+ PIN io_oeb[24]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT -4.800 2794.680 2.400 2795.800 ;
+ END
+ END io_oeb[24]
+ PIN io_oeb[25]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT -4.800 2583.000 2.400 2584.120 ;
+ END
+ END io_oeb[25]
+ PIN io_oeb[26]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT -4.800 2371.320 2.400 2372.440 ;
+ END
+ END io_oeb[26]
+ PIN io_oeb[27]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT -4.800 2159.640 2.400 2160.760 ;
+ END
+ END io_oeb[27]
+ PIN io_oeb[28]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT -4.800 1947.960 2.400 1949.080 ;
+ END
+ END io_oeb[28]
+ PIN io_oeb[29]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT -4.800 1736.280 2.400 1737.400 ;
+ END
+ END io_oeb[29]
+ PIN io_oeb[2]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT 2977.800 564.200 2985.000 565.320 ;
+ END
+ END io_oeb[2]
+ PIN io_oeb[30]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT -4.800 1524.600 2.400 1525.720 ;
+ END
+ END io_oeb[30]
+ PIN io_oeb[31]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT -4.800 1312.920 2.400 1314.040 ;
+ END
+ END io_oeb[31]
+ PIN io_oeb[32]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT -4.800 1101.240 2.400 1102.360 ;
+ END
+ END io_oeb[32]
+ PIN io_oeb[33]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT -4.800 889.560 2.400 890.680 ;
+ END
+ END io_oeb[33]
+ PIN io_oeb[34]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT -4.800 677.880 2.400 679.000 ;
+ END
+ END io_oeb[34]
+ PIN io_oeb[35]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT -4.800 466.200 2.400 467.320 ;
+ END
+ END io_oeb[35]
+ PIN io_oeb[36]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT -4.800 254.520 2.400 255.640 ;
+ END
+ END io_oeb[36]
+ PIN io_oeb[37]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT -4.800 42.840 2.400 43.960 ;
+ END
+ END io_oeb[37]
+ PIN io_oeb[3]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT 2977.800 762.440 2985.000 763.560 ;
+ END
+ END io_oeb[3]
+ PIN io_oeb[4]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT 2977.800 960.680 2985.000 961.800 ;
+ END
+ END io_oeb[4]
+ PIN io_oeb[5]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT 2977.800 1158.920 2985.000 1160.040 ;
+ END
+ END io_oeb[5]
+ PIN io_oeb[6]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT 2977.800 1357.160 2985.000 1358.280 ;
+ END
+ END io_oeb[6]
+ PIN io_oeb[7]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT 2977.800 1555.400 2985.000 1556.520 ;
+ END
+ END io_oeb[7]
+ PIN io_oeb[8]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT 2977.800 1753.640 2985.000 1754.760 ;
+ END
+ END io_oeb[8]
+ PIN io_oeb[9]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT 2977.800 1951.880 2985.000 1953.000 ;
+ END
+ END io_oeb[9]
+ PIN io_out[0]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT 2977.800 101.640 2985.000 102.760 ;
+ END
+ END io_out[0]
+ PIN io_out[10]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT 2977.800 2084.040 2985.000 2085.160 ;
+ END
+ END io_out[10]
+ PIN io_out[11]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT 2977.800 2282.280 2985.000 2283.400 ;
+ END
+ END io_out[11]
+ PIN io_out[12]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT 2977.800 2480.520 2985.000 2481.640 ;
+ END
+ END io_out[12]
+ PIN io_out[13]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT 2977.800 2678.760 2985.000 2679.880 ;
+ END
+ END io_out[13]
+ PIN io_out[14]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT 2977.800 2877.000 2985.000 2878.120 ;
+ END
+ END io_out[14]
+ PIN io_out[15]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 2813.160 2977.800 2814.280 2985.000 ;
+ END
+ END io_out[15]
+ PIN io_out[16]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 2482.200 2977.800 2483.320 2985.000 ;
+ END
+ END io_out[16]
+ PIN io_out[17]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 2151.240 2977.800 2152.360 2985.000 ;
+ END
+ END io_out[17]
+ PIN io_out[18]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 1820.280 2977.800 1821.400 2985.000 ;
+ END
+ END io_out[18]
+ PIN io_out[19]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 1489.320 2977.800 1490.440 2985.000 ;
+ END
+ END io_out[19]
+ PIN io_out[1]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT 2977.800 299.880 2985.000 301.000 ;
+ END
+ END io_out[1]
+ PIN io_out[20]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 1158.360 2977.800 1159.480 2985.000 ;
+ END
+ END io_out[20]
+ PIN io_out[21]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 827.400 2977.800 828.520 2985.000 ;
+ END
+ END io_out[21]
+ PIN io_out[22]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 496.440 2977.800 497.560 2985.000 ;
+ END
+ END io_out[22]
+ PIN io_out[23]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 165.480 2977.800 166.600 2985.000 ;
+ END
+ END io_out[23]
+ PIN io_out[24]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT -4.800 2865.240 2.400 2866.360 ;
+ END
+ END io_out[24]
+ PIN io_out[25]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT -4.800 2653.560 2.400 2654.680 ;
+ END
+ END io_out[25]
+ PIN io_out[26]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT -4.800 2441.880 2.400 2443.000 ;
+ END
+ END io_out[26]
+ PIN io_out[27]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT -4.800 2230.200 2.400 2231.320 ;
+ END
+ END io_out[27]
+ PIN io_out[28]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT -4.800 2018.520 2.400 2019.640 ;
+ END
+ END io_out[28]
+ PIN io_out[29]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT -4.800 1806.840 2.400 1807.960 ;
+ END
+ END io_out[29]
+ PIN io_out[2]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT 2977.800 498.120 2985.000 499.240 ;
+ END
+ END io_out[2]
+ PIN io_out[30]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT -4.800 1595.160 2.400 1596.280 ;
+ END
+ END io_out[30]
+ PIN io_out[31]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT -4.800 1383.480 2.400 1384.600 ;
+ END
+ END io_out[31]
+ PIN io_out[32]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT -4.800 1171.800 2.400 1172.920 ;
+ END
+ END io_out[32]
+ PIN io_out[33]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT -4.800 960.120 2.400 961.240 ;
+ END
+ END io_out[33]
+ PIN io_out[34]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT -4.800 748.440 2.400 749.560 ;
+ END
+ END io_out[34]
+ PIN io_out[35]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT -4.800 536.760 2.400 537.880 ;
+ END
+ END io_out[35]
+ PIN io_out[36]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT -4.800 325.080 2.400 326.200 ;
+ END
+ END io_out[36]
+ PIN io_out[37]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT -4.800 113.400 2.400 114.520 ;
+ END
+ END io_out[37]
+ PIN io_out[3]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT 2977.800 696.360 2985.000 697.480 ;
+ END
+ END io_out[3]
+ PIN io_out[4]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT 2977.800 894.600 2985.000 895.720 ;
+ END
+ END io_out[4]
+ PIN io_out[5]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT 2977.800 1092.840 2985.000 1093.960 ;
+ END
+ END io_out[5]
+ PIN io_out[6]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT 2977.800 1291.080 2985.000 1292.200 ;
+ END
+ END io_out[6]
+ PIN io_out[7]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT 2977.800 1489.320 2985.000 1490.440 ;
+ END
+ END io_out[7]
+ PIN io_out[8]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT 2977.800 1687.560 2985.000 1688.680 ;
+ END
+ END io_out[8]
+ PIN io_out[9]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT 2977.800 1885.800 2985.000 1886.920 ;
+ END
+ END io_out[9]
+ PIN la_data_in[0]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 1065.960 -4.800 1067.080 2.400 ;
+ END
+ END la_data_in[0]
+ PIN la_data_in[10]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 1351.560 -4.800 1352.680 2.400 ;
+ END
+ END la_data_in[10]
+ PIN la_data_in[11]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 1380.120 -4.800 1381.240 2.400 ;
+ END
+ END la_data_in[11]
+ PIN la_data_in[12]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 1408.680 -4.800 1409.800 2.400 ;
+ END
+ END la_data_in[12]
+ PIN la_data_in[13]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 1437.240 -4.800 1438.360 2.400 ;
+ END
+ END la_data_in[13]
+ PIN la_data_in[14]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 1465.800 -4.800 1466.920 2.400 ;
+ END
+ END la_data_in[14]
+ PIN la_data_in[15]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 1494.360 -4.800 1495.480 2.400 ;
+ END
+ END la_data_in[15]
+ PIN la_data_in[16]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 1522.920 -4.800 1524.040 2.400 ;
+ END
+ END la_data_in[16]
+ PIN la_data_in[17]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 1551.480 -4.800 1552.600 2.400 ;
+ END
+ END la_data_in[17]
+ PIN la_data_in[18]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 1580.040 -4.800 1581.160 2.400 ;
+ END
+ END la_data_in[18]
+ PIN la_data_in[19]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 1608.600 -4.800 1609.720 2.400 ;
+ END
+ END la_data_in[19]
+ PIN la_data_in[1]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 1094.520 -4.800 1095.640 2.400 ;
+ END
+ END la_data_in[1]
+ PIN la_data_in[20]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 1637.160 -4.800 1638.280 2.400 ;
+ END
+ END la_data_in[20]
+ PIN la_data_in[21]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 1665.720 -4.800 1666.840 2.400 ;
+ END
+ END la_data_in[21]
+ PIN la_data_in[22]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 1694.280 -4.800 1695.400 2.400 ;
+ END
+ END la_data_in[22]
+ PIN la_data_in[23]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 1722.840 -4.800 1723.960 2.400 ;
+ END
+ END la_data_in[23]
+ PIN la_data_in[24]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 1751.400 -4.800 1752.520 2.400 ;
+ END
+ END la_data_in[24]
+ PIN la_data_in[25]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 1779.960 -4.800 1781.080 2.400 ;
+ END
+ END la_data_in[25]
+ PIN la_data_in[26]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 1808.520 -4.800 1809.640 2.400 ;
+ END
+ END la_data_in[26]
+ PIN la_data_in[27]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 1837.080 -4.800 1838.200 2.400 ;
+ END
+ END la_data_in[27]
+ PIN la_data_in[28]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 1865.640 -4.800 1866.760 2.400 ;
+ END
+ END la_data_in[28]
+ PIN la_data_in[29]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 1894.200 -4.800 1895.320 2.400 ;
+ END
+ END la_data_in[29]
+ PIN la_data_in[2]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 1123.080 -4.800 1124.200 2.400 ;
+ END
+ END la_data_in[2]
+ PIN la_data_in[30]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 1922.760 -4.800 1923.880 2.400 ;
+ END
+ END la_data_in[30]
+ PIN la_data_in[31]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 1951.320 -4.800 1952.440 2.400 ;
+ END
+ END la_data_in[31]
+ PIN la_data_in[32]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 1979.880 -4.800 1981.000 2.400 ;
+ END
+ END la_data_in[32]
+ PIN la_data_in[33]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 2008.440 -4.800 2009.560 2.400 ;
+ END
+ END la_data_in[33]
+ PIN la_data_in[34]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 2037.000 -4.800 2038.120 2.400 ;
+ END
+ END la_data_in[34]
+ PIN la_data_in[35]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 2065.560 -4.800 2066.680 2.400 ;
+ END
+ END la_data_in[35]
+ PIN la_data_in[36]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 2094.120 -4.800 2095.240 2.400 ;
+ END
+ END la_data_in[36]
+ PIN la_data_in[37]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 2122.680 -4.800 2123.800 2.400 ;
+ END
+ END la_data_in[37]
+ PIN la_data_in[38]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 2151.240 -4.800 2152.360 2.400 ;
+ END
+ END la_data_in[38]
+ PIN la_data_in[39]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 2179.800 -4.800 2180.920 2.400 ;
+ END
+ END la_data_in[39]
+ PIN la_data_in[3]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 1151.640 -4.800 1152.760 2.400 ;
+ END
+ END la_data_in[3]
+ PIN la_data_in[40]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 2208.360 -4.800 2209.480 2.400 ;
+ END
+ END la_data_in[40]
+ PIN la_data_in[41]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 2236.920 -4.800 2238.040 2.400 ;
+ END
+ END la_data_in[41]
+ PIN la_data_in[42]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 2265.480 -4.800 2266.600 2.400 ;
+ END
+ END la_data_in[42]
+ PIN la_data_in[43]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 2294.040 -4.800 2295.160 2.400 ;
+ END
+ END la_data_in[43]
+ PIN la_data_in[44]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 2322.600 -4.800 2323.720 2.400 ;
+ END
+ END la_data_in[44]
+ PIN la_data_in[45]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 2351.160 -4.800 2352.280 2.400 ;
+ END
+ END la_data_in[45]
+ PIN la_data_in[46]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 2379.720 -4.800 2380.840 2.400 ;
+ END
+ END la_data_in[46]
+ PIN la_data_in[47]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 2408.280 -4.800 2409.400 2.400 ;
+ END
+ END la_data_in[47]
+ PIN la_data_in[48]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 2436.840 -4.800 2437.960 2.400 ;
+ END
+ END la_data_in[48]
+ PIN la_data_in[49]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 2465.400 -4.800 2466.520 2.400 ;
+ END
+ END la_data_in[49]
+ PIN la_data_in[4]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 1180.200 -4.800 1181.320 2.400 ;
+ END
+ END la_data_in[4]
+ PIN la_data_in[50]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 2493.960 -4.800 2495.080 2.400 ;
+ END
+ END la_data_in[50]
+ PIN la_data_in[51]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 2522.520 -4.800 2523.640 2.400 ;
+ END
+ END la_data_in[51]
+ PIN la_data_in[52]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 2551.080 -4.800 2552.200 2.400 ;
+ END
+ END la_data_in[52]
+ PIN la_data_in[53]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 2579.640 -4.800 2580.760 2.400 ;
+ END
+ END la_data_in[53]
+ PIN la_data_in[54]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 2608.200 -4.800 2609.320 2.400 ;
+ END
+ END la_data_in[54]
+ PIN la_data_in[55]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 2636.760 -4.800 2637.880 2.400 ;
+ END
+ END la_data_in[55]
+ PIN la_data_in[56]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 2665.320 -4.800 2666.440 2.400 ;
+ END
+ END la_data_in[56]
+ PIN la_data_in[57]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 2693.880 -4.800 2695.000 2.400 ;
+ END
+ END la_data_in[57]
+ PIN la_data_in[58]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 2722.440 -4.800 2723.560 2.400 ;
+ END
+ END la_data_in[58]
+ PIN la_data_in[59]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 2751.000 -4.800 2752.120 2.400 ;
+ END
+ END la_data_in[59]
+ PIN la_data_in[5]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 1208.760 -4.800 1209.880 2.400 ;
+ END
+ END la_data_in[5]
+ PIN la_data_in[60]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 2779.560 -4.800 2780.680 2.400 ;
+ END
+ END la_data_in[60]
+ PIN la_data_in[61]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 2808.120 -4.800 2809.240 2.400 ;
+ END
+ END la_data_in[61]
+ PIN la_data_in[62]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 2836.680 -4.800 2837.800 2.400 ;
+ END
+ END la_data_in[62]
+ PIN la_data_in[63]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 2865.240 -4.800 2866.360 2.400 ;
+ END
+ END la_data_in[63]
+ PIN la_data_in[6]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 1237.320 -4.800 1238.440 2.400 ;
+ END
+ END la_data_in[6]
+ PIN la_data_in[7]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 1265.880 -4.800 1267.000 2.400 ;
+ END
+ END la_data_in[7]
+ PIN la_data_in[8]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 1294.440 -4.800 1295.560 2.400 ;
+ END
+ END la_data_in[8]
+ PIN la_data_in[9]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 1323.000 -4.800 1324.120 2.400 ;
+ END
+ END la_data_in[9]
+ PIN la_data_out[0]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 1075.480 -4.800 1076.600 2.400 ;
+ END
+ END la_data_out[0]
+ PIN la_data_out[10]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 1361.080 -4.800 1362.200 2.400 ;
+ END
+ END la_data_out[10]
+ PIN la_data_out[11]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 1389.640 -4.800 1390.760 2.400 ;
+ END
+ END la_data_out[11]
+ PIN la_data_out[12]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 1418.200 -4.800 1419.320 2.400 ;
+ END
+ END la_data_out[12]
+ PIN la_data_out[13]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 1446.760 -4.800 1447.880 2.400 ;
+ END
+ END la_data_out[13]
+ PIN la_data_out[14]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 1475.320 -4.800 1476.440 2.400 ;
+ END
+ END la_data_out[14]
+ PIN la_data_out[15]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 1503.880 -4.800 1505.000 2.400 ;
+ END
+ END la_data_out[15]
+ PIN la_data_out[16]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 1532.440 -4.800 1533.560 2.400 ;
+ END
+ END la_data_out[16]
+ PIN la_data_out[17]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 1561.000 -4.800 1562.120 2.400 ;
+ END
+ END la_data_out[17]
+ PIN la_data_out[18]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 1589.560 -4.800 1590.680 2.400 ;
+ END
+ END la_data_out[18]
+ PIN la_data_out[19]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 1618.120 -4.800 1619.240 2.400 ;
+ END
+ END la_data_out[19]
+ PIN la_data_out[1]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 1104.040 -4.800 1105.160 2.400 ;
+ END
+ END la_data_out[1]
+ PIN la_data_out[20]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 1646.680 -4.800 1647.800 2.400 ;
+ END
+ END la_data_out[20]
+ PIN la_data_out[21]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 1675.240 -4.800 1676.360 2.400 ;
+ END
+ END la_data_out[21]
+ PIN la_data_out[22]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 1703.800 -4.800 1704.920 2.400 ;
+ END
+ END la_data_out[22]
+ PIN la_data_out[23]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 1732.360 -4.800 1733.480 2.400 ;
+ END
+ END la_data_out[23]
+ PIN la_data_out[24]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 1760.920 -4.800 1762.040 2.400 ;
+ END
+ END la_data_out[24]
+ PIN la_data_out[25]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 1789.480 -4.800 1790.600 2.400 ;
+ END
+ END la_data_out[25]
+ PIN la_data_out[26]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 1818.040 -4.800 1819.160 2.400 ;
+ END
+ END la_data_out[26]
+ PIN la_data_out[27]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 1846.600 -4.800 1847.720 2.400 ;
+ END
+ END la_data_out[27]
+ PIN la_data_out[28]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 1875.160 -4.800 1876.280 2.400 ;
+ END
+ END la_data_out[28]
+ PIN la_data_out[29]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 1903.720 -4.800 1904.840 2.400 ;
+ END
+ END la_data_out[29]
+ PIN la_data_out[2]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 1132.600 -4.800 1133.720 2.400 ;
+ END
+ END la_data_out[2]
+ PIN la_data_out[30]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 1932.280 -4.800 1933.400 2.400 ;
+ END
+ END la_data_out[30]
+ PIN la_data_out[31]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 1960.840 -4.800 1961.960 2.400 ;
+ END
+ END la_data_out[31]
+ PIN la_data_out[32]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 1989.400 -4.800 1990.520 2.400 ;
+ END
+ END la_data_out[32]
+ PIN la_data_out[33]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 2017.960 -4.800 2019.080 2.400 ;
+ END
+ END la_data_out[33]
+ PIN la_data_out[34]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 2046.520 -4.800 2047.640 2.400 ;
+ END
+ END la_data_out[34]
+ PIN la_data_out[35]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 2075.080 -4.800 2076.200 2.400 ;
+ END
+ END la_data_out[35]
+ PIN la_data_out[36]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 2103.640 -4.800 2104.760 2.400 ;
+ END
+ END la_data_out[36]
+ PIN la_data_out[37]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 2132.200 -4.800 2133.320 2.400 ;
+ END
+ END la_data_out[37]
+ PIN la_data_out[38]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 2160.760 -4.800 2161.880 2.400 ;
+ END
+ END la_data_out[38]
+ PIN la_data_out[39]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 2189.320 -4.800 2190.440 2.400 ;
+ END
+ END la_data_out[39]
+ PIN la_data_out[3]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 1161.160 -4.800 1162.280 2.400 ;
+ END
+ END la_data_out[3]
+ PIN la_data_out[40]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 2217.880 -4.800 2219.000 2.400 ;
+ END
+ END la_data_out[40]
+ PIN la_data_out[41]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 2246.440 -4.800 2247.560 2.400 ;
+ END
+ END la_data_out[41]
+ PIN la_data_out[42]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 2275.000 -4.800 2276.120 2.400 ;
+ END
+ END la_data_out[42]
+ PIN la_data_out[43]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 2303.560 -4.800 2304.680 2.400 ;
+ END
+ END la_data_out[43]
+ PIN la_data_out[44]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 2332.120 -4.800 2333.240 2.400 ;
+ END
+ END la_data_out[44]
+ PIN la_data_out[45]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 2360.680 -4.800 2361.800 2.400 ;
+ END
+ END la_data_out[45]
+ PIN la_data_out[46]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 2389.240 -4.800 2390.360 2.400 ;
+ END
+ END la_data_out[46]
+ PIN la_data_out[47]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 2417.800 -4.800 2418.920 2.400 ;
+ END
+ END la_data_out[47]
+ PIN la_data_out[48]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 2446.360 -4.800 2447.480 2.400 ;
+ END
+ END la_data_out[48]
+ PIN la_data_out[49]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 2474.920 -4.800 2476.040 2.400 ;
+ END
+ END la_data_out[49]
+ PIN la_data_out[4]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 1189.720 -4.800 1190.840 2.400 ;
+ END
+ END la_data_out[4]
+ PIN la_data_out[50]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 2503.480 -4.800 2504.600 2.400 ;
+ END
+ END la_data_out[50]
+ PIN la_data_out[51]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 2532.040 -4.800 2533.160 2.400 ;
+ END
+ END la_data_out[51]
+ PIN la_data_out[52]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 2560.600 -4.800 2561.720 2.400 ;
+ END
+ END la_data_out[52]
+ PIN la_data_out[53]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 2589.160 -4.800 2590.280 2.400 ;
+ END
+ END la_data_out[53]
+ PIN la_data_out[54]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 2617.720 -4.800 2618.840 2.400 ;
+ END
+ END la_data_out[54]
+ PIN la_data_out[55]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 2646.280 -4.800 2647.400 2.400 ;
+ END
+ END la_data_out[55]
+ PIN la_data_out[56]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 2674.840 -4.800 2675.960 2.400 ;
+ END
+ END la_data_out[56]
+ PIN la_data_out[57]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 2703.400 -4.800 2704.520 2.400 ;
+ END
+ END la_data_out[57]
+ PIN la_data_out[58]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 2731.960 -4.800 2733.080 2.400 ;
+ END
+ END la_data_out[58]
+ PIN la_data_out[59]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 2760.520 -4.800 2761.640 2.400 ;
+ END
+ END la_data_out[59]
+ PIN la_data_out[5]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 1218.280 -4.800 1219.400 2.400 ;
+ END
+ END la_data_out[5]
+ PIN la_data_out[60]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 2789.080 -4.800 2790.200 2.400 ;
+ END
+ END la_data_out[60]
+ PIN la_data_out[61]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 2817.640 -4.800 2818.760 2.400 ;
+ END
+ END la_data_out[61]
+ PIN la_data_out[62]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 2846.200 -4.800 2847.320 2.400 ;
+ END
+ END la_data_out[62]
+ PIN la_data_out[63]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 2874.760 -4.800 2875.880 2.400 ;
+ END
+ END la_data_out[63]
+ PIN la_data_out[6]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 1246.840 -4.800 1247.960 2.400 ;
+ END
+ END la_data_out[6]
+ PIN la_data_out[7]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 1275.400 -4.800 1276.520 2.400 ;
+ END
+ END la_data_out[7]
+ PIN la_data_out[8]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 1303.960 -4.800 1305.080 2.400 ;
+ END
+ END la_data_out[8]
+ PIN la_data_out[9]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 1332.520 -4.800 1333.640 2.400 ;
+ END
+ END la_data_out[9]
+ PIN la_oenb[0]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 1085.000 -4.800 1086.120 2.400 ;
+ END
+ END la_oenb[0]
+ PIN la_oenb[10]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 1370.600 -4.800 1371.720 2.400 ;
+ END
+ END la_oenb[10]
+ PIN la_oenb[11]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 1399.160 -4.800 1400.280 2.400 ;
+ END
+ END la_oenb[11]
+ PIN la_oenb[12]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 1427.720 -4.800 1428.840 2.400 ;
+ END
+ END la_oenb[12]
+ PIN la_oenb[13]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 1456.280 -4.800 1457.400 2.400 ;
+ END
+ END la_oenb[13]
+ PIN la_oenb[14]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 1484.840 -4.800 1485.960 2.400 ;
+ END
+ END la_oenb[14]
+ PIN la_oenb[15]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 1513.400 -4.800 1514.520 2.400 ;
+ END
+ END la_oenb[15]
+ PIN la_oenb[16]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 1541.960 -4.800 1543.080 2.400 ;
+ END
+ END la_oenb[16]
+ PIN la_oenb[17]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 1570.520 -4.800 1571.640 2.400 ;
+ END
+ END la_oenb[17]
+ PIN la_oenb[18]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 1599.080 -4.800 1600.200 2.400 ;
+ END
+ END la_oenb[18]
+ PIN la_oenb[19]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 1627.640 -4.800 1628.760 2.400 ;
+ END
+ END la_oenb[19]
+ PIN la_oenb[1]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 1113.560 -4.800 1114.680 2.400 ;
+ END
+ END la_oenb[1]
+ PIN la_oenb[20]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 1656.200 -4.800 1657.320 2.400 ;
+ END
+ END la_oenb[20]
+ PIN la_oenb[21]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 1684.760 -4.800 1685.880 2.400 ;
+ END
+ END la_oenb[21]
+ PIN la_oenb[22]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 1713.320 -4.800 1714.440 2.400 ;
+ END
+ END la_oenb[22]
+ PIN la_oenb[23]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 1741.880 -4.800 1743.000 2.400 ;
+ END
+ END la_oenb[23]
+ PIN la_oenb[24]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 1770.440 -4.800 1771.560 2.400 ;
+ END
+ END la_oenb[24]
+ PIN la_oenb[25]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 1799.000 -4.800 1800.120 2.400 ;
+ END
+ END la_oenb[25]
+ PIN la_oenb[26]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 1827.560 -4.800 1828.680 2.400 ;
+ END
+ END la_oenb[26]
+ PIN la_oenb[27]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 1856.120 -4.800 1857.240 2.400 ;
+ END
+ END la_oenb[27]
+ PIN la_oenb[28]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 1884.680 -4.800 1885.800 2.400 ;
+ END
+ END la_oenb[28]
+ PIN la_oenb[29]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 1913.240 -4.800 1914.360 2.400 ;
+ END
+ END la_oenb[29]
+ PIN la_oenb[2]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 1142.120 -4.800 1143.240 2.400 ;
+ END
+ END la_oenb[2]
+ PIN la_oenb[30]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 1941.800 -4.800 1942.920 2.400 ;
+ END
+ END la_oenb[30]
+ PIN la_oenb[31]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 1970.360 -4.800 1971.480 2.400 ;
+ END
+ END la_oenb[31]
+ PIN la_oenb[32]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 1998.920 -4.800 2000.040 2.400 ;
+ END
+ END la_oenb[32]
+ PIN la_oenb[33]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 2027.480 -4.800 2028.600 2.400 ;
+ END
+ END la_oenb[33]
+ PIN la_oenb[34]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 2056.040 -4.800 2057.160 2.400 ;
+ END
+ END la_oenb[34]
+ PIN la_oenb[35]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 2084.600 -4.800 2085.720 2.400 ;
+ END
+ END la_oenb[35]
+ PIN la_oenb[36]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 2113.160 -4.800 2114.280 2.400 ;
+ END
+ END la_oenb[36]
+ PIN la_oenb[37]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 2141.720 -4.800 2142.840 2.400 ;
+ END
+ END la_oenb[37]
+ PIN la_oenb[38]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 2170.280 -4.800 2171.400 2.400 ;
+ END
+ END la_oenb[38]
+ PIN la_oenb[39]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 2198.840 -4.800 2199.960 2.400 ;
+ END
+ END la_oenb[39]
+ PIN la_oenb[3]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 1170.680 -4.800 1171.800 2.400 ;
+ END
+ END la_oenb[3]
+ PIN la_oenb[40]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 2227.400 -4.800 2228.520 2.400 ;
+ END
+ END la_oenb[40]
+ PIN la_oenb[41]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 2255.960 -4.800 2257.080 2.400 ;
+ END
+ END la_oenb[41]
+ PIN la_oenb[42]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 2284.520 -4.800 2285.640 2.400 ;
+ END
+ END la_oenb[42]
+ PIN la_oenb[43]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 2313.080 -4.800 2314.200 2.400 ;
+ END
+ END la_oenb[43]
+ PIN la_oenb[44]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 2341.640 -4.800 2342.760 2.400 ;
+ END
+ END la_oenb[44]
+ PIN la_oenb[45]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 2370.200 -4.800 2371.320 2.400 ;
+ END
+ END la_oenb[45]
+ PIN la_oenb[46]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 2398.760 -4.800 2399.880 2.400 ;
+ END
+ END la_oenb[46]
+ PIN la_oenb[47]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 2427.320 -4.800 2428.440 2.400 ;
+ END
+ END la_oenb[47]
+ PIN la_oenb[48]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 2455.880 -4.800 2457.000 2.400 ;
+ END
+ END la_oenb[48]
+ PIN la_oenb[49]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 2484.440 -4.800 2485.560 2.400 ;
+ END
+ END la_oenb[49]
+ PIN la_oenb[4]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 1199.240 -4.800 1200.360 2.400 ;
+ END
+ END la_oenb[4]
+ PIN la_oenb[50]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 2513.000 -4.800 2514.120 2.400 ;
+ END
+ END la_oenb[50]
+ PIN la_oenb[51]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 2541.560 -4.800 2542.680 2.400 ;
+ END
+ END la_oenb[51]
+ PIN la_oenb[52]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 2570.120 -4.800 2571.240 2.400 ;
+ END
+ END la_oenb[52]
+ PIN la_oenb[53]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 2598.680 -4.800 2599.800 2.400 ;
+ END
+ END la_oenb[53]
+ PIN la_oenb[54]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 2627.240 -4.800 2628.360 2.400 ;
+ END
+ END la_oenb[54]
+ PIN la_oenb[55]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 2655.800 -4.800 2656.920 2.400 ;
+ END
+ END la_oenb[55]
+ PIN la_oenb[56]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 2684.360 -4.800 2685.480 2.400 ;
+ END
+ END la_oenb[56]
+ PIN la_oenb[57]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 2712.920 -4.800 2714.040 2.400 ;
+ END
+ END la_oenb[57]
+ PIN la_oenb[58]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 2741.480 -4.800 2742.600 2.400 ;
+ END
+ END la_oenb[58]
+ PIN la_oenb[59]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 2770.040 -4.800 2771.160 2.400 ;
+ END
+ END la_oenb[59]
+ PIN la_oenb[5]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 1227.800 -4.800 1228.920 2.400 ;
+ END
+ END la_oenb[5]
+ PIN la_oenb[60]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 2798.600 -4.800 2799.720 2.400 ;
+ END
+ END la_oenb[60]
+ PIN la_oenb[61]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 2827.160 -4.800 2828.280 2.400 ;
+ END
+ END la_oenb[61]
+ PIN la_oenb[62]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 2855.720 -4.800 2856.840 2.400 ;
+ END
+ END la_oenb[62]
+ PIN la_oenb[63]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 2884.280 -4.800 2885.400 2.400 ;
+ END
+ END la_oenb[63]
+ PIN la_oenb[6]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 1256.360 -4.800 1257.480 2.400 ;
+ END
+ END la_oenb[6]
+ PIN la_oenb[7]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 1284.920 -4.800 1286.040 2.400 ;
+ END
+ END la_oenb[7]
+ PIN la_oenb[8]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 1313.480 -4.800 1314.600 2.400 ;
+ END
+ END la_oenb[8]
+ PIN la_oenb[9]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 1342.040 -4.800 1343.160 2.400 ;
+ END
+ END la_oenb[9]
+ PIN user_clock2
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 2893.800 -4.800 2894.920 2.400 ;
+ END
+ END user_clock2
+ PIN user_irq[0]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 2903.320 -4.800 2904.440 2.400 ;
+ END
+ END user_irq[0]
+ PIN user_irq[1]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 2912.840 -4.800 2913.960 2.400 ;
+ END
+ END user_irq[1]
+ PIN user_irq[2]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 2922.360 -4.800 2923.480 2.400 ;
+ END
+ END user_irq[2]
+ PIN vdd
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER Metal4 ;
+ RECT -4.780 -3.420 -1.680 2986.540 ;
+ END
+ PORT
+ LAYER Metal5 ;
+ RECT -4.780 -3.420 2985.100 -0.320 ;
+ END
+ PORT
+ LAYER Metal5 ;
+ RECT -4.780 2983.440 2985.100 2986.540 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 2982.000 -3.420 2985.100 2986.540 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 15.770 -8.220 18.870 2991.340 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 105.770 -8.220 108.870 103.210 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 105.770 393.590 108.870 517.210 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 105.770 807.590 108.870 931.210 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 105.770 1221.590 108.870 1345.210 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 105.770 1635.590 108.870 1759.210 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 105.770 2049.590 108.870 2173.210 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 105.770 2463.590 108.870 2587.210 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 105.770 2877.590 108.870 2991.340 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 195.770 -8.220 198.870 103.210 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 195.770 393.590 198.870 517.210 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 195.770 807.590 198.870 931.210 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 195.770 1221.590 198.870 1345.210 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 195.770 1635.590 198.870 1759.210 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 195.770 2049.590 198.870 2173.210 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 195.770 2463.590 198.870 2587.210 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 195.770 2877.590 198.870 2991.340 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 285.770 -8.220 288.870 103.210 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 285.770 393.590 288.870 517.210 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 285.770 807.590 288.870 931.210 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 285.770 1221.590 288.870 1345.210 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 285.770 1635.590 288.870 1759.210 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 285.770 2049.590 288.870 2173.210 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 285.770 2463.590 288.870 2587.210 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 285.770 2877.590 288.870 2991.340 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 375.770 -8.220 378.870 103.210 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 375.770 393.590 378.870 517.210 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 375.770 807.590 378.870 931.210 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 375.770 1221.590 378.870 1345.210 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 375.770 1635.590 378.870 1759.210 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 375.770 2049.590 378.870 2173.210 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 375.770 2463.590 378.870 2587.210 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 375.770 2877.590 378.870 2991.340 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 465.770 -8.220 468.870 103.210 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 465.770 393.590 468.870 517.210 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 465.770 807.590 468.870 931.210 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 465.770 1221.590 468.870 1345.210 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 465.770 1635.590 468.870 1759.210 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 465.770 2049.590 468.870 2173.210 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 465.770 2463.590 468.870 2587.210 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 465.770 2877.590 468.870 2991.340 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 555.770 -8.220 558.870 103.210 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 555.770 393.590 558.870 517.210 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 555.770 807.590 558.870 931.210 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 555.770 1221.590 558.870 1345.210 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 555.770 1635.590 558.870 1759.210 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 555.770 2049.590 558.870 2173.210 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 555.770 2463.590 558.870 2587.210 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 555.770 2877.590 558.870 2991.340 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 645.770 -8.220 648.870 103.210 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 645.770 393.590 648.870 517.210 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 645.770 807.590 648.870 931.210 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 645.770 1221.590 648.870 1345.210 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 645.770 1635.590 648.870 1759.210 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 645.770 2049.590 648.870 2173.210 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 645.770 2463.590 648.870 2587.210 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 645.770 2877.590 648.870 2991.340 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 735.770 -8.220 738.870 2991.340 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 825.770 -8.220 828.870 332.630 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 825.770 2672.050 828.870 2991.340 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 915.770 -8.220 918.870 332.630 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 915.770 2672.050 918.870 2991.340 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 1005.770 -8.220 1008.870 332.630 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 1005.770 2672.050 1008.870 2991.340 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 1095.770 -8.220 1098.870 332.630 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 1095.770 2672.050 1098.870 2991.340 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 1185.770 -8.220 1188.870 332.630 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 1185.770 2674.680 1188.870 2991.340 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 1275.770 -8.220 1278.870 332.630 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 1275.770 2672.050 1278.870 2991.340 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 1365.770 -8.220 1368.870 332.630 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 1365.770 2674.680 1368.870 2991.340 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 1455.770 -8.220 1458.870 332.630 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 1455.770 2672.050 1458.870 2991.340 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 1545.770 -8.220 1548.870 332.630 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 1545.770 2672.050 1548.870 2991.340 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 1635.770 -8.220 1638.870 332.630 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 1635.770 2672.050 1638.870 2991.340 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 1725.770 -8.220 1728.870 332.630 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 1725.770 2672.050 1728.870 2991.340 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 1815.770 -8.220 1818.870 332.630 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 1815.770 2672.050 1818.870 2991.340 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 1905.770 -8.220 1908.870 332.630 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 1905.770 2672.050 1908.870 2991.340 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 1995.770 -8.220 1998.870 332.630 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 1995.770 2672.050 1998.870 2991.340 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 2085.770 -8.220 2088.870 332.630 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 2085.770 2672.050 2088.870 2991.340 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 2175.770 -8.220 2178.870 332.630 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 2175.770 2672.050 2178.870 2991.340 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 2265.770 -8.220 2268.870 332.630 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 2265.770 2672.050 2268.870 2991.340 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 2355.770 -8.220 2358.870 332.630 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 2355.770 2672.050 2358.870 2991.340 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 2445.770 -8.220 2448.870 332.630 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 2445.770 2672.050 2448.870 2991.340 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 2535.770 -8.220 2538.870 332.630 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 2535.770 2672.050 2538.870 2991.340 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 2625.770 -8.220 2628.870 332.630 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 2625.770 2672.050 2628.870 2991.340 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 2715.770 -8.220 2718.870 332.630 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 2715.770 2672.050 2718.870 2991.340 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 2805.770 -8.220 2808.870 332.630 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 2805.770 2672.050 2808.870 2991.340 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 2895.770 -8.220 2898.870 332.630 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 2895.770 2674.680 2898.870 2991.340 ;
+ END
+ PORT
+ LAYER Metal5 ;
+ RECT -9.580 17.130 2989.900 20.230 ;
+ END
+ PORT
+ LAYER Metal5 ;
+ RECT -9.580 107.130 2989.900 110.230 ;
+ END
+ PORT
+ LAYER Metal5 ;
+ RECT -9.580 197.130 2989.900 200.230 ;
+ END
+ PORT
+ LAYER Metal5 ;
+ RECT -9.580 287.130 2989.900 290.230 ;
+ END
+ PORT
+ LAYER Metal5 ;
+ RECT -9.580 377.130 2989.900 380.230 ;
+ END
+ PORT
+ LAYER Metal5 ;
+ RECT -9.580 467.130 2989.900 470.230 ;
+ END
+ PORT
+ LAYER Metal5 ;
+ RECT -9.580 557.130 2989.900 560.230 ;
+ END
+ PORT
+ LAYER Metal5 ;
+ RECT -9.580 647.130 2989.900 650.230 ;
+ END
+ PORT
+ LAYER Metal5 ;
+ RECT -9.580 737.130 2989.900 740.230 ;
+ END
+ PORT
+ LAYER Metal5 ;
+ RECT -9.580 827.130 2989.900 830.230 ;
+ END
+ PORT
+ LAYER Metal5 ;
+ RECT -9.580 917.130 2989.900 920.230 ;
+ END
+ PORT
+ LAYER Metal5 ;
+ RECT -9.580 1007.130 2989.900 1010.230 ;
+ END
+ PORT
+ LAYER Metal5 ;
+ RECT -9.580 1097.130 2989.900 1100.230 ;
+ END
+ PORT
+ LAYER Metal5 ;
+ RECT -9.580 1187.130 2989.900 1190.230 ;
+ END
+ PORT
+ LAYER Metal5 ;
+ RECT -9.580 1277.130 2989.900 1280.230 ;
+ END
+ PORT
+ LAYER Metal5 ;
+ RECT -9.580 1367.130 2989.900 1370.230 ;
+ END
+ PORT
+ LAYER Metal5 ;
+ RECT -9.580 1457.130 2989.900 1460.230 ;
+ END
+ PORT
+ LAYER Metal5 ;
+ RECT -9.580 1547.130 2989.900 1550.230 ;
+ END
+ PORT
+ LAYER Metal5 ;
+ RECT -9.580 1637.130 2989.900 1640.230 ;
+ END
+ PORT
+ LAYER Metal5 ;
+ RECT -9.580 1727.130 2989.900 1730.230 ;
+ END
+ PORT
+ LAYER Metal5 ;
+ RECT -9.580 1817.130 2989.900 1820.230 ;
+ END
+ PORT
+ LAYER Metal5 ;
+ RECT -9.580 1907.130 2989.900 1910.230 ;
+ END
+ PORT
+ LAYER Metal5 ;
+ RECT -9.580 1997.130 2989.900 2000.230 ;
+ END
+ PORT
+ LAYER Metal5 ;
+ RECT -9.580 2087.130 2989.900 2090.230 ;
+ END
+ PORT
+ LAYER Metal5 ;
+ RECT -9.580 2177.130 2989.900 2180.230 ;
+ END
+ PORT
+ LAYER Metal5 ;
+ RECT -9.580 2267.130 2989.900 2270.230 ;
+ END
+ PORT
+ LAYER Metal5 ;
+ RECT -9.580 2357.130 2989.900 2360.230 ;
+ END
+ PORT
+ LAYER Metal5 ;
+ RECT -9.580 2447.130 2989.900 2450.230 ;
+ END
+ PORT
+ LAYER Metal5 ;
+ RECT -9.580 2537.130 2989.900 2540.230 ;
+ END
+ PORT
+ LAYER Metal5 ;
+ RECT -9.580 2627.130 2989.900 2630.230 ;
+ END
+ PORT
+ LAYER Metal5 ;
+ RECT -9.580 2717.130 2989.900 2720.230 ;
+ END
+ PORT
+ LAYER Metal5 ;
+ RECT -9.580 2807.130 2989.900 2810.230 ;
+ END
+ PORT
+ LAYER Metal5 ;
+ RECT -9.580 2897.130 2989.900 2900.230 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 410.330 82.020 413.430 419.740 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 410.330 497.540 413.430 827.465 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 410.330 913.060 413.430 1242.940 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 410.330 1328.580 413.430 1658.460 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 410.330 1744.100 413.430 2073.980 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 410.330 2159.620 413.430 2489.500 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 410.330 2567.300 413.430 2897.180 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 2958.890 321.140 2961.990 2701.180 ;
+ END
+ END vdd
+ PIN vss
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER Metal4 ;
+ RECT -9.580 -8.220 -6.480 2991.340 ;
+ END
+ PORT
+ LAYER Metal5 ;
+ RECT -9.580 -8.220 2989.900 -5.120 ;
+ END
+ PORT
+ LAYER Metal5 ;
+ RECT -9.580 2988.240 2989.900 2991.340 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 2986.800 -8.220 2989.900 2991.340 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 60.770 -8.220 63.870 2991.340 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 150.770 -8.220 153.870 103.210 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 150.770 393.590 153.870 517.210 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 150.770 807.590 153.870 931.210 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 150.770 1221.590 153.870 1345.210 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 150.770 1635.590 153.870 1759.210 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 150.770 2049.590 153.870 2173.210 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 150.770 2463.590 153.870 2587.210 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 150.770 2877.590 153.870 2991.340 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 240.770 -8.220 243.870 102.260 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 240.770 395.660 243.870 516.260 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 240.770 809.660 243.870 930.260 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 240.770 1223.660 243.870 1344.260 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 240.770 1637.660 243.870 1758.260 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 240.770 2051.660 243.870 2172.260 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 240.770 2465.660 243.870 2586.260 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 240.770 2879.660 243.870 2991.340 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 330.770 -8.220 333.870 103.210 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 330.770 393.590 333.870 517.210 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 330.770 807.590 333.870 931.210 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 330.770 1221.590 333.870 1345.210 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 330.770 1635.590 333.870 1759.210 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 330.770 2049.590 333.870 2173.210 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 330.770 2463.590 333.870 2587.210 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 330.770 2877.590 333.870 2991.340 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 420.770 -8.220 423.870 2991.340 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 510.770 -8.220 513.870 103.210 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 510.770 393.590 513.870 517.210 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 510.770 807.590 513.870 931.210 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 510.770 1221.590 513.870 1345.210 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 510.770 1635.590 513.870 1759.210 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 510.770 2049.590 513.870 2173.210 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 510.770 2463.590 513.870 2587.210 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 510.770 2877.590 513.870 2991.340 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 600.770 -8.220 603.870 102.260 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 600.770 395.660 603.870 516.260 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 600.770 809.660 603.870 930.260 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 600.770 1223.660 603.870 1344.260 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 600.770 1637.660 603.870 1758.260 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 600.770 2051.660 603.870 2172.260 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 600.770 2465.660 603.870 2586.260 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 600.770 2879.660 603.870 2991.340 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 690.770 -8.220 693.870 103.210 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 690.770 393.590 693.870 517.210 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 690.770 807.590 693.870 931.210 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 690.770 1221.590 693.870 1345.210 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 690.770 1635.590 693.870 1759.210 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 690.770 2049.590 693.870 2173.210 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 690.770 2463.590 693.870 2587.210 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 690.770 2877.590 693.870 2991.340 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 780.770 -8.220 783.870 332.630 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 780.770 2672.050 783.870 2991.340 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 870.770 -8.220 873.870 332.630 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 870.770 2672.050 873.870 2991.340 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 960.770 -8.220 963.870 332.630 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 960.770 2672.050 963.870 2991.340 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 1050.770 -8.220 1053.870 332.630 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 1050.770 2672.050 1053.870 2991.340 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 1140.770 -8.220 1143.870 332.630 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 1140.770 2672.050 1143.870 2991.340 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 1230.770 -8.220 1233.870 332.630 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 1230.770 2672.050 1233.870 2991.340 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 1320.770 -8.220 1323.870 332.630 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 1320.770 2672.050 1323.870 2991.340 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 1410.770 -8.220 1413.870 332.630 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 1410.770 2672.050 1413.870 2991.340 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 1500.770 -8.220 1503.870 332.630 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 1500.770 2672.050 1503.870 2991.340 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 1590.770 -8.220 1593.870 332.630 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 1590.770 2672.050 1593.870 2991.340 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 1680.770 -8.220 1683.870 332.630 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 1680.770 2672.050 1683.870 2991.340 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 1770.770 -8.220 1773.870 332.630 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 1770.770 2672.050 1773.870 2991.340 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 1860.770 -8.220 1863.870 332.630 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 1860.770 2672.050 1863.870 2991.340 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 1950.770 -8.220 1953.870 332.630 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 1950.770 2672.050 1953.870 2991.340 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 2040.770 -8.220 2043.870 332.630 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 2040.770 2672.050 2043.870 2991.340 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 2130.770 -8.220 2133.870 332.630 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 2130.770 2672.050 2133.870 2991.340 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 2220.770 -8.220 2223.870 332.630 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 2220.770 2672.050 2223.870 2991.340 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 2310.770 -8.220 2313.870 332.630 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 2310.770 2672.050 2313.870 2991.340 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 2400.770 -8.220 2403.870 332.630 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 2400.770 2672.050 2403.870 2991.340 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 2490.770 -8.220 2493.870 332.630 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 2490.770 2672.050 2493.870 2991.340 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 2580.770 -8.220 2583.870 332.630 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 2580.770 2672.050 2583.870 2991.340 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 2670.770 -8.220 2673.870 332.630 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 2670.770 2672.050 2673.870 2991.340 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 2760.770 -8.220 2763.870 332.630 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 2760.770 2672.050 2763.870 2991.340 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 2850.770 -8.220 2853.870 332.630 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 2850.770 2672.050 2853.870 2991.340 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 2940.770 -8.220 2943.870 2991.340 ;
+ END
+ PORT
+ LAYER Metal5 ;
+ RECT -9.580 62.130 2989.900 65.230 ;
+ END
+ PORT
+ LAYER Metal5 ;
+ RECT -9.580 152.130 2989.900 155.230 ;
+ END
+ PORT
+ LAYER Metal5 ;
+ RECT -9.580 242.130 2989.900 245.230 ;
+ END
+ PORT
+ LAYER Metal5 ;
+ RECT -9.580 332.130 775.340 335.230 ;
+ END
+ PORT
+ LAYER Metal5 ;
+ RECT -9.580 422.130 2989.900 425.230 ;
+ END
+ PORT
+ LAYER Metal5 ;
+ RECT -9.580 512.130 2989.900 515.230 ;
+ END
+ PORT
+ LAYER Metal5 ;
+ RECT -9.580 602.130 2989.900 605.230 ;
+ END
+ PORT
+ LAYER Metal5 ;
+ RECT -9.580 692.130 2989.900 695.230 ;
+ END
+ PORT
+ LAYER Metal5 ;
+ RECT -9.580 782.130 2989.900 785.230 ;
+ END
+ PORT
+ LAYER Metal5 ;
+ RECT -9.580 872.130 2989.900 875.230 ;
+ END
+ PORT
+ LAYER Metal5 ;
+ RECT -9.580 962.130 2989.900 965.230 ;
+ END
+ PORT
+ LAYER Metal5 ;
+ RECT -9.580 1052.130 2989.900 1055.230 ;
+ END
+ PORT
+ LAYER Metal5 ;
+ RECT -9.580 1142.130 2989.900 1145.230 ;
+ END
+ PORT
+ LAYER Metal5 ;
+ RECT -9.580 1232.130 2989.900 1235.230 ;
+ END
+ PORT
+ LAYER Metal5 ;
+ RECT -9.580 1322.130 2989.900 1325.230 ;
+ END
+ PORT
+ LAYER Metal5 ;
+ RECT -9.580 1412.130 2989.900 1415.230 ;
+ END
+ PORT
+ LAYER Metal5 ;
+ RECT -9.580 1502.130 2989.900 1505.230 ;
+ END
+ PORT
+ LAYER Metal5 ;
+ RECT -9.580 1592.130 2989.900 1595.230 ;
+ END
+ PORT
+ LAYER Metal5 ;
+ RECT -9.580 1682.130 2989.900 1685.230 ;
+ END
+ PORT
+ LAYER Metal5 ;
+ RECT -9.580 1772.130 2989.900 1775.230 ;
+ END
+ PORT
+ LAYER Metal5 ;
+ RECT -9.580 1862.130 2989.900 1865.230 ;
+ END
+ PORT
+ LAYER Metal5 ;
+ RECT -9.580 1952.130 2989.900 1955.230 ;
+ END
+ PORT
+ LAYER Metal5 ;
+ RECT -9.580 2042.130 2989.900 2045.230 ;
+ END
+ PORT
+ LAYER Metal5 ;
+ RECT -9.580 2132.130 2989.900 2135.230 ;
+ END
+ PORT
+ LAYER Metal5 ;
+ RECT -9.580 2222.130 2989.900 2225.230 ;
+ END
+ PORT
+ LAYER Metal5 ;
+ RECT -9.580 2312.130 2989.900 2315.230 ;
+ END
+ PORT
+ LAYER Metal5 ;
+ RECT -9.580 2402.130 2989.900 2405.230 ;
+ END
+ PORT
+ LAYER Metal5 ;
+ RECT -9.580 2492.130 2989.900 2495.230 ;
+ END
+ PORT
+ LAYER Metal5 ;
+ RECT -9.580 2582.130 2989.900 2585.230 ;
+ END
+ PORT
+ LAYER Metal5 ;
+ RECT -9.580 2672.130 2989.900 2675.230 ;
+ END
+ PORT
+ LAYER Metal5 ;
+ RECT -9.580 2762.130 2989.900 2765.230 ;
+ END
+ PORT
+ LAYER Metal5 ;
+ RECT -9.580 2852.130 2989.900 2855.230 ;
+ END
+ PORT
+ LAYER Metal5 ;
+ RECT -9.580 2942.130 2989.900 2945.230 ;
+ END
+ PORT
+ LAYER Metal5 ;
+ RECT 2941.260 332.130 2989.900 335.230 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 745.770 501.460 748.870 831.340 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 745.770 321.140 748.870 415.820 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 745.770 1324.660 748.870 1654.540 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 745.770 916.980 748.870 1246.860 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 745.770 2155.700 748.870 2485.580 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 745.770 1740.180 748.870 2070.060 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 745.770 2571.220 748.870 2697.260 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 2962.810 321.140 2965.910 2701.180 ;
+ END
+ END vss
+ PIN wb_clk_i
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 56.840 -4.800 57.960 2.400 ;
+ END
+ END wb_clk_i
+ PIN wb_rst_i
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 66.360 -4.800 67.480 2.400 ;
+ END
+ END wb_rst_i
+ PIN wbs_ack_o
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 75.880 -4.800 77.000 2.400 ;
+ END
+ END wbs_ack_o
+ PIN wbs_adr_i[0]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 113.960 -4.800 115.080 2.400 ;
+ END
+ END wbs_adr_i[0]
+ PIN wbs_adr_i[10]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 437.640 -4.800 438.760 2.400 ;
+ END
+ END wbs_adr_i[10]
+ PIN wbs_adr_i[11]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 466.200 -4.800 467.320 2.400 ;
+ END
+ END wbs_adr_i[11]
+ PIN wbs_adr_i[12]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 494.760 -4.800 495.880 2.400 ;
+ END
+ END wbs_adr_i[12]
+ PIN wbs_adr_i[13]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 523.320 -4.800 524.440 2.400 ;
+ END
+ END wbs_adr_i[13]
+ PIN wbs_adr_i[14]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 551.880 -4.800 553.000 2.400 ;
+ END
+ END wbs_adr_i[14]
+ PIN wbs_adr_i[15]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 580.440 -4.800 581.560 2.400 ;
+ END
+ END wbs_adr_i[15]
+ PIN wbs_adr_i[16]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 609.000 -4.800 610.120 2.400 ;
+ END
+ END wbs_adr_i[16]
+ PIN wbs_adr_i[17]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 637.560 -4.800 638.680 2.400 ;
+ END
+ END wbs_adr_i[17]
+ PIN wbs_adr_i[18]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 666.120 -4.800 667.240 2.400 ;
+ END
+ END wbs_adr_i[18]
+ PIN wbs_adr_i[19]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 694.680 -4.800 695.800 2.400 ;
+ END
+ END wbs_adr_i[19]
+ PIN wbs_adr_i[1]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 152.040 -4.800 153.160 2.400 ;
+ END
+ END wbs_adr_i[1]
+ PIN wbs_adr_i[20]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 723.240 -4.800 724.360 2.400 ;
+ END
+ END wbs_adr_i[20]
+ PIN wbs_adr_i[21]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 751.800 -4.800 752.920 2.400 ;
+ END
+ END wbs_adr_i[21]
+ PIN wbs_adr_i[22]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 780.360 -4.800 781.480 2.400 ;
+ END
+ END wbs_adr_i[22]
+ PIN wbs_adr_i[23]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 808.920 -4.800 810.040 2.400 ;
+ END
+ END wbs_adr_i[23]
+ PIN wbs_adr_i[24]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 837.480 -4.800 838.600 2.400 ;
+ END
+ END wbs_adr_i[24]
+ PIN wbs_adr_i[25]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 866.040 -4.800 867.160 2.400 ;
+ END
+ END wbs_adr_i[25]
+ PIN wbs_adr_i[26]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 894.600 -4.800 895.720 2.400 ;
+ END
+ END wbs_adr_i[26]
+ PIN wbs_adr_i[27]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 923.160 -4.800 924.280 2.400 ;
+ END
+ END wbs_adr_i[27]
+ PIN wbs_adr_i[28]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 951.720 -4.800 952.840 2.400 ;
+ END
+ END wbs_adr_i[28]
+ PIN wbs_adr_i[29]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 980.280 -4.800 981.400 2.400 ;
+ END
+ END wbs_adr_i[29]
+ PIN wbs_adr_i[2]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 190.120 -4.800 191.240 2.400 ;
+ END
+ END wbs_adr_i[2]
+ PIN wbs_adr_i[30]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 1008.840 -4.800 1009.960 2.400 ;
+ END
+ END wbs_adr_i[30]
+ PIN wbs_adr_i[31]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 1037.400 -4.800 1038.520 2.400 ;
+ END
+ END wbs_adr_i[31]
+ PIN wbs_adr_i[3]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 228.200 -4.800 229.320 2.400 ;
+ END
+ END wbs_adr_i[3]
+ PIN wbs_adr_i[4]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 266.280 -4.800 267.400 2.400 ;
+ END
+ END wbs_adr_i[4]
+ PIN wbs_adr_i[5]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 294.840 -4.800 295.960 2.400 ;
+ END
+ END wbs_adr_i[5]
+ PIN wbs_adr_i[6]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 323.400 -4.800 324.520 2.400 ;
+ END
+ END wbs_adr_i[6]
+ PIN wbs_adr_i[7]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 351.960 -4.800 353.080 2.400 ;
+ END
+ END wbs_adr_i[7]
+ PIN wbs_adr_i[8]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 380.520 -4.800 381.640 2.400 ;
+ END
+ END wbs_adr_i[8]
+ PIN wbs_adr_i[9]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 409.080 -4.800 410.200 2.400 ;
+ END
+ END wbs_adr_i[9]
+ PIN wbs_cyc_i
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 85.400 -4.800 86.520 2.400 ;
+ END
+ END wbs_cyc_i
+ PIN wbs_dat_i[0]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 123.480 -4.800 124.600 2.400 ;
+ END
+ END wbs_dat_i[0]
+ PIN wbs_dat_i[10]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 447.160 -4.800 448.280 2.400 ;
+ END
+ END wbs_dat_i[10]
+ PIN wbs_dat_i[11]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 475.720 -4.800 476.840 2.400 ;
+ END
+ END wbs_dat_i[11]
+ PIN wbs_dat_i[12]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 504.280 -4.800 505.400 2.400 ;
+ END
+ END wbs_dat_i[12]
+ PIN wbs_dat_i[13]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 532.840 -4.800 533.960 2.400 ;
+ END
+ END wbs_dat_i[13]
+ PIN wbs_dat_i[14]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 561.400 -4.800 562.520 2.400 ;
+ END
+ END wbs_dat_i[14]
+ PIN wbs_dat_i[15]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 589.960 -4.800 591.080 2.400 ;
+ END
+ END wbs_dat_i[15]
+ PIN wbs_dat_i[16]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 618.520 -4.800 619.640 2.400 ;
+ END
+ END wbs_dat_i[16]
+ PIN wbs_dat_i[17]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 647.080 -4.800 648.200 2.400 ;
+ END
+ END wbs_dat_i[17]
+ PIN wbs_dat_i[18]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 675.640 -4.800 676.760 2.400 ;
+ END
+ END wbs_dat_i[18]
+ PIN wbs_dat_i[19]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 704.200 -4.800 705.320 2.400 ;
+ END
+ END wbs_dat_i[19]
+ PIN wbs_dat_i[1]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 161.560 -4.800 162.680 2.400 ;
+ END
+ END wbs_dat_i[1]
+ PIN wbs_dat_i[20]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 732.760 -4.800 733.880 2.400 ;
+ END
+ END wbs_dat_i[20]
+ PIN wbs_dat_i[21]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 761.320 -4.800 762.440 2.400 ;
+ END
+ END wbs_dat_i[21]
+ PIN wbs_dat_i[22]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 789.880 -4.800 791.000 2.400 ;
+ END
+ END wbs_dat_i[22]
+ PIN wbs_dat_i[23]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 818.440 -4.800 819.560 2.400 ;
+ END
+ END wbs_dat_i[23]
+ PIN wbs_dat_i[24]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 847.000 -4.800 848.120 2.400 ;
+ END
+ END wbs_dat_i[24]
+ PIN wbs_dat_i[25]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 875.560 -4.800 876.680 2.400 ;
+ END
+ END wbs_dat_i[25]
+ PIN wbs_dat_i[26]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 904.120 -4.800 905.240 2.400 ;
+ END
+ END wbs_dat_i[26]
+ PIN wbs_dat_i[27]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 932.680 -4.800 933.800 2.400 ;
+ END
+ END wbs_dat_i[27]
+ PIN wbs_dat_i[28]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 961.240 -4.800 962.360 2.400 ;
+ END
+ END wbs_dat_i[28]
+ PIN wbs_dat_i[29]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 989.800 -4.800 990.920 2.400 ;
+ END
+ END wbs_dat_i[29]
+ PIN wbs_dat_i[2]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 199.640 -4.800 200.760 2.400 ;
+ END
+ END wbs_dat_i[2]
+ PIN wbs_dat_i[30]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 1018.360 -4.800 1019.480 2.400 ;
+ END
+ END wbs_dat_i[30]
+ PIN wbs_dat_i[31]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 1046.920 -4.800 1048.040 2.400 ;
+ END
+ END wbs_dat_i[31]
+ PIN wbs_dat_i[3]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 237.720 -4.800 238.840 2.400 ;
+ END
+ END wbs_dat_i[3]
+ PIN wbs_dat_i[4]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 275.800 -4.800 276.920 2.400 ;
+ END
+ END wbs_dat_i[4]
+ PIN wbs_dat_i[5]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 304.360 -4.800 305.480 2.400 ;
+ END
+ END wbs_dat_i[5]
+ PIN wbs_dat_i[6]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 332.920 -4.800 334.040 2.400 ;
+ END
+ END wbs_dat_i[6]
+ PIN wbs_dat_i[7]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 361.480 -4.800 362.600 2.400 ;
+ END
+ END wbs_dat_i[7]
+ PIN wbs_dat_i[8]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 390.040 -4.800 391.160 2.400 ;
+ END
+ END wbs_dat_i[8]
+ PIN wbs_dat_i[9]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 418.600 -4.800 419.720 2.400 ;
+ END
+ END wbs_dat_i[9]
+ PIN wbs_dat_o[0]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 133.000 -4.800 134.120 2.400 ;
+ END
+ END wbs_dat_o[0]
+ PIN wbs_dat_o[10]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 456.680 -4.800 457.800 2.400 ;
+ END
+ END wbs_dat_o[10]
+ PIN wbs_dat_o[11]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 485.240 -4.800 486.360 2.400 ;
+ END
+ END wbs_dat_o[11]
+ PIN wbs_dat_o[12]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 513.800 -4.800 514.920 2.400 ;
+ END
+ END wbs_dat_o[12]
+ PIN wbs_dat_o[13]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 542.360 -4.800 543.480 2.400 ;
+ END
+ END wbs_dat_o[13]
+ PIN wbs_dat_o[14]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 570.920 -4.800 572.040 2.400 ;
+ END
+ END wbs_dat_o[14]
+ PIN wbs_dat_o[15]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 599.480 -4.800 600.600 2.400 ;
+ END
+ END wbs_dat_o[15]
+ PIN wbs_dat_o[16]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 628.040 -4.800 629.160 2.400 ;
+ END
+ END wbs_dat_o[16]
+ PIN wbs_dat_o[17]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 656.600 -4.800 657.720 2.400 ;
+ END
+ END wbs_dat_o[17]
+ PIN wbs_dat_o[18]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 685.160 -4.800 686.280 2.400 ;
+ END
+ END wbs_dat_o[18]
+ PIN wbs_dat_o[19]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 713.720 -4.800 714.840 2.400 ;
+ END
+ END wbs_dat_o[19]
+ PIN wbs_dat_o[1]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 171.080 -4.800 172.200 2.400 ;
+ END
+ END wbs_dat_o[1]
+ PIN wbs_dat_o[20]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 742.280 -4.800 743.400 2.400 ;
+ END
+ END wbs_dat_o[20]
+ PIN wbs_dat_o[21]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 770.840 -4.800 771.960 2.400 ;
+ END
+ END wbs_dat_o[21]
+ PIN wbs_dat_o[22]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 799.400 -4.800 800.520 2.400 ;
+ END
+ END wbs_dat_o[22]
+ PIN wbs_dat_o[23]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 827.960 -4.800 829.080 2.400 ;
+ END
+ END wbs_dat_o[23]
+ PIN wbs_dat_o[24]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 856.520 -4.800 857.640 2.400 ;
+ END
+ END wbs_dat_o[24]
+ PIN wbs_dat_o[25]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 885.080 -4.800 886.200 2.400 ;
+ END
+ END wbs_dat_o[25]
+ PIN wbs_dat_o[26]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 913.640 -4.800 914.760 2.400 ;
+ END
+ END wbs_dat_o[26]
+ PIN wbs_dat_o[27]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 942.200 -4.800 943.320 2.400 ;
+ END
+ END wbs_dat_o[27]
+ PIN wbs_dat_o[28]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 970.760 -4.800 971.880 2.400 ;
+ END
+ END wbs_dat_o[28]
+ PIN wbs_dat_o[29]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 999.320 -4.800 1000.440 2.400 ;
+ END
+ END wbs_dat_o[29]
+ PIN wbs_dat_o[2]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 209.160 -4.800 210.280 2.400 ;
+ END
+ END wbs_dat_o[2]
+ PIN wbs_dat_o[30]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 1027.880 -4.800 1029.000 2.400 ;
+ END
+ END wbs_dat_o[30]
+ PIN wbs_dat_o[31]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 1056.440 -4.800 1057.560 2.400 ;
+ END
+ END wbs_dat_o[31]
+ PIN wbs_dat_o[3]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 247.240 -4.800 248.360 2.400 ;
+ END
+ END wbs_dat_o[3]
+ PIN wbs_dat_o[4]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 285.320 -4.800 286.440 2.400 ;
+ END
+ END wbs_dat_o[4]
+ PIN wbs_dat_o[5]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 313.880 -4.800 315.000 2.400 ;
+ END
+ END wbs_dat_o[5]
+ PIN wbs_dat_o[6]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 342.440 -4.800 343.560 2.400 ;
+ END
+ END wbs_dat_o[6]
+ PIN wbs_dat_o[7]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 371.000 -4.800 372.120 2.400 ;
+ END
+ END wbs_dat_o[7]
+ PIN wbs_dat_o[8]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 399.560 -4.800 400.680 2.400 ;
+ END
+ END wbs_dat_o[8]
+ PIN wbs_dat_o[9]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 428.120 -4.800 429.240 2.400 ;
+ END
+ END wbs_dat_o[9]
+ PIN wbs_sel_i[0]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 142.520 -4.800 143.640 2.400 ;
+ END
+ END wbs_sel_i[0]
+ PIN wbs_sel_i[1]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 180.600 -4.800 181.720 2.400 ;
+ END
+ END wbs_sel_i[1]
+ PIN wbs_sel_i[2]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 218.680 -4.800 219.800 2.400 ;
+ END
+ END wbs_sel_i[2]
+ PIN wbs_sel_i[3]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 256.760 -4.800 257.880 2.400 ;
+ END
+ END wbs_sel_i[3]
+ PIN wbs_stb_i
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 94.920 -4.800 96.040 2.400 ;
+ END
+ END wbs_stb_i
+ PIN wbs_we_i
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 104.440 -4.800 105.560 2.400 ;
+ END
+ END wbs_we_i
+ OBS
+ LAYER Metal1 ;
+ RECT 12.320 15.380 2968.000 2968.410 ;
+ LAYER Metal2 ;
+ RECT 14.700 2977.500 54.860 2978.500 ;
+ RECT 56.580 2977.500 165.180 2978.500 ;
+ RECT 166.900 2977.500 275.500 2978.500 ;
+ RECT 277.220 2977.500 385.820 2978.500 ;
+ RECT 387.540 2977.500 496.140 2978.500 ;
+ RECT 497.860 2977.500 606.460 2978.500 ;
+ RECT 608.180 2977.500 716.780 2978.500 ;
+ RECT 718.500 2977.500 827.100 2978.500 ;
+ RECT 828.820 2977.500 937.420 2978.500 ;
+ RECT 939.140 2977.500 1047.740 2978.500 ;
+ RECT 1049.460 2977.500 1158.060 2978.500 ;
+ RECT 1159.780 2977.500 1268.380 2978.500 ;
+ RECT 1270.100 2977.500 1378.700 2978.500 ;
+ RECT 1380.420 2977.500 1489.020 2978.500 ;
+ RECT 1490.740 2977.500 1599.340 2978.500 ;
+ RECT 1601.060 2977.500 1709.660 2978.500 ;
+ RECT 1711.380 2977.500 1819.980 2978.500 ;
+ RECT 1821.700 2977.500 1930.300 2978.500 ;
+ RECT 1932.020 2977.500 2040.620 2978.500 ;
+ RECT 2042.340 2977.500 2150.940 2978.500 ;
+ RECT 2152.660 2977.500 2261.260 2978.500 ;
+ RECT 2262.980 2977.500 2371.580 2978.500 ;
+ RECT 2373.300 2977.500 2481.900 2978.500 ;
+ RECT 2483.620 2977.500 2592.220 2978.500 ;
+ RECT 2593.940 2977.500 2702.540 2978.500 ;
+ RECT 2704.260 2977.500 2812.860 2978.500 ;
+ RECT 2814.580 2977.500 2923.180 2978.500 ;
+ RECT 2924.900 2977.500 2971.220 2978.500 ;
+ RECT 14.700 2.700 2971.220 2977.500 ;
+ RECT 14.700 1.820 56.540 2.700 ;
+ RECT 58.260 1.820 66.060 2.700 ;
+ RECT 67.780 1.820 75.580 2.700 ;
+ RECT 77.300 1.820 85.100 2.700 ;
+ RECT 86.820 1.820 94.620 2.700 ;
+ RECT 96.340 1.820 104.140 2.700 ;
+ RECT 105.860 1.820 113.660 2.700 ;
+ RECT 115.380 1.820 123.180 2.700 ;
+ RECT 124.900 1.820 132.700 2.700 ;
+ RECT 134.420 1.820 142.220 2.700 ;
+ RECT 143.940 1.820 151.740 2.700 ;
+ RECT 153.460 1.820 161.260 2.700 ;
+ RECT 162.980 1.820 170.780 2.700 ;
+ RECT 172.500 1.820 180.300 2.700 ;
+ RECT 182.020 1.820 189.820 2.700 ;
+ RECT 191.540 1.820 199.340 2.700 ;
+ RECT 201.060 1.820 208.860 2.700 ;
+ RECT 210.580 1.820 218.380 2.700 ;
+ RECT 220.100 1.820 227.900 2.700 ;
+ RECT 229.620 1.820 237.420 2.700 ;
+ RECT 239.140 1.820 246.940 2.700 ;
+ RECT 248.660 1.820 256.460 2.700 ;
+ RECT 258.180 1.820 265.980 2.700 ;
+ RECT 267.700 1.820 275.500 2.700 ;
+ RECT 277.220 1.820 285.020 2.700 ;
+ RECT 286.740 1.820 294.540 2.700 ;
+ RECT 296.260 1.820 304.060 2.700 ;
+ RECT 305.780 1.820 313.580 2.700 ;
+ RECT 315.300 1.820 323.100 2.700 ;
+ RECT 324.820 1.820 332.620 2.700 ;
+ RECT 334.340 1.820 342.140 2.700 ;
+ RECT 343.860 1.820 351.660 2.700 ;
+ RECT 353.380 1.820 361.180 2.700 ;
+ RECT 362.900 1.820 370.700 2.700 ;
+ RECT 372.420 1.820 380.220 2.700 ;
+ RECT 381.940 1.820 389.740 2.700 ;
+ RECT 391.460 1.820 399.260 2.700 ;
+ RECT 400.980 1.820 408.780 2.700 ;
+ RECT 410.500 1.820 418.300 2.700 ;
+ RECT 420.020 1.820 427.820 2.700 ;
+ RECT 429.540 1.820 437.340 2.700 ;
+ RECT 439.060 1.820 446.860 2.700 ;
+ RECT 448.580 1.820 456.380 2.700 ;
+ RECT 458.100 1.820 465.900 2.700 ;
+ RECT 467.620 1.820 475.420 2.700 ;
+ RECT 477.140 1.820 484.940 2.700 ;
+ RECT 486.660 1.820 494.460 2.700 ;
+ RECT 496.180 1.820 503.980 2.700 ;
+ RECT 505.700 1.820 513.500 2.700 ;
+ RECT 515.220 1.820 523.020 2.700 ;
+ RECT 524.740 1.820 532.540 2.700 ;
+ RECT 534.260 1.820 542.060 2.700 ;
+ RECT 543.780 1.820 551.580 2.700 ;
+ RECT 553.300 1.820 561.100 2.700 ;
+ RECT 562.820 1.820 570.620 2.700 ;
+ RECT 572.340 1.820 580.140 2.700 ;
+ RECT 581.860 1.820 589.660 2.700 ;
+ RECT 591.380 1.820 599.180 2.700 ;
+ RECT 600.900 1.820 608.700 2.700 ;
+ RECT 610.420 1.820 618.220 2.700 ;
+ RECT 619.940 1.820 627.740 2.700 ;
+ RECT 629.460 1.820 637.260 2.700 ;
+ RECT 638.980 1.820 646.780 2.700 ;
+ RECT 648.500 1.820 656.300 2.700 ;
+ RECT 658.020 1.820 665.820 2.700 ;
+ RECT 667.540 1.820 675.340 2.700 ;
+ RECT 677.060 1.820 684.860 2.700 ;
+ RECT 686.580 1.820 694.380 2.700 ;
+ RECT 696.100 1.820 703.900 2.700 ;
+ RECT 705.620 1.820 713.420 2.700 ;
+ RECT 715.140 1.820 722.940 2.700 ;
+ RECT 724.660 1.820 732.460 2.700 ;
+ RECT 734.180 1.820 741.980 2.700 ;
+ RECT 743.700 1.820 751.500 2.700 ;
+ RECT 753.220 1.820 761.020 2.700 ;
+ RECT 762.740 1.820 770.540 2.700 ;
+ RECT 772.260 1.820 780.060 2.700 ;
+ RECT 781.780 1.820 789.580 2.700 ;
+ RECT 791.300 1.820 799.100 2.700 ;
+ RECT 800.820 1.820 808.620 2.700 ;
+ RECT 810.340 1.820 818.140 2.700 ;
+ RECT 819.860 1.820 827.660 2.700 ;
+ RECT 829.380 1.820 837.180 2.700 ;
+ RECT 838.900 1.820 846.700 2.700 ;
+ RECT 848.420 1.820 856.220 2.700 ;
+ RECT 857.940 1.820 865.740 2.700 ;
+ RECT 867.460 1.820 875.260 2.700 ;
+ RECT 876.980 1.820 884.780 2.700 ;
+ RECT 886.500 1.820 894.300 2.700 ;
+ RECT 896.020 1.820 903.820 2.700 ;
+ RECT 905.540 1.820 913.340 2.700 ;
+ RECT 915.060 1.820 922.860 2.700 ;
+ RECT 924.580 1.820 932.380 2.700 ;
+ RECT 934.100 1.820 941.900 2.700 ;
+ RECT 943.620 1.820 951.420 2.700 ;
+ RECT 953.140 1.820 960.940 2.700 ;
+ RECT 962.660 1.820 970.460 2.700 ;
+ RECT 972.180 1.820 979.980 2.700 ;
+ RECT 981.700 1.820 989.500 2.700 ;
+ RECT 991.220 1.820 999.020 2.700 ;
+ RECT 1000.740 1.820 1008.540 2.700 ;
+ RECT 1010.260 1.820 1018.060 2.700 ;
+ RECT 1019.780 1.820 1027.580 2.700 ;
+ RECT 1029.300 1.820 1037.100 2.700 ;
+ RECT 1038.820 1.820 1046.620 2.700 ;
+ RECT 1048.340 1.820 1056.140 2.700 ;
+ RECT 1057.860 1.820 1065.660 2.700 ;
+ RECT 1067.380 1.820 1075.180 2.700 ;
+ RECT 1076.900 1.820 1084.700 2.700 ;
+ RECT 1086.420 1.820 1094.220 2.700 ;
+ RECT 1095.940 1.820 1103.740 2.700 ;
+ RECT 1105.460 1.820 1113.260 2.700 ;
+ RECT 1114.980 1.820 1122.780 2.700 ;
+ RECT 1124.500 1.820 1132.300 2.700 ;
+ RECT 1134.020 1.820 1141.820 2.700 ;
+ RECT 1143.540 1.820 1151.340 2.700 ;
+ RECT 1153.060 1.820 1160.860 2.700 ;
+ RECT 1162.580 1.820 1170.380 2.700 ;
+ RECT 1172.100 1.820 1179.900 2.700 ;
+ RECT 1181.620 1.820 1189.420 2.700 ;
+ RECT 1191.140 1.820 1198.940 2.700 ;
+ RECT 1200.660 1.820 1208.460 2.700 ;
+ RECT 1210.180 1.820 1217.980 2.700 ;
+ RECT 1219.700 1.820 1227.500 2.700 ;
+ RECT 1229.220 1.820 1237.020 2.700 ;
+ RECT 1238.740 1.820 1246.540 2.700 ;
+ RECT 1248.260 1.820 1256.060 2.700 ;
+ RECT 1257.780 1.820 1265.580 2.700 ;
+ RECT 1267.300 1.820 1275.100 2.700 ;
+ RECT 1276.820 1.820 1284.620 2.700 ;
+ RECT 1286.340 1.820 1294.140 2.700 ;
+ RECT 1295.860 1.820 1303.660 2.700 ;
+ RECT 1305.380 1.820 1313.180 2.700 ;
+ RECT 1314.900 1.820 1322.700 2.700 ;
+ RECT 1324.420 1.820 1332.220 2.700 ;
+ RECT 1333.940 1.820 1341.740 2.700 ;
+ RECT 1343.460 1.820 1351.260 2.700 ;
+ RECT 1352.980 1.820 1360.780 2.700 ;
+ RECT 1362.500 1.820 1370.300 2.700 ;
+ RECT 1372.020 1.820 1379.820 2.700 ;
+ RECT 1381.540 1.820 1389.340 2.700 ;
+ RECT 1391.060 1.820 1398.860 2.700 ;
+ RECT 1400.580 1.820 1408.380 2.700 ;
+ RECT 1410.100 1.820 1417.900 2.700 ;
+ RECT 1419.620 1.820 1427.420 2.700 ;
+ RECT 1429.140 1.820 1436.940 2.700 ;
+ RECT 1438.660 1.820 1446.460 2.700 ;
+ RECT 1448.180 1.820 1455.980 2.700 ;
+ RECT 1457.700 1.820 1465.500 2.700 ;
+ RECT 1467.220 1.820 1475.020 2.700 ;
+ RECT 1476.740 1.820 1484.540 2.700 ;
+ RECT 1486.260 1.820 1494.060 2.700 ;
+ RECT 1495.780 1.820 1503.580 2.700 ;
+ RECT 1505.300 1.820 1513.100 2.700 ;
+ RECT 1514.820 1.820 1522.620 2.700 ;
+ RECT 1524.340 1.820 1532.140 2.700 ;
+ RECT 1533.860 1.820 1541.660 2.700 ;
+ RECT 1543.380 1.820 1551.180 2.700 ;
+ RECT 1552.900 1.820 1560.700 2.700 ;
+ RECT 1562.420 1.820 1570.220 2.700 ;
+ RECT 1571.940 1.820 1579.740 2.700 ;
+ RECT 1581.460 1.820 1589.260 2.700 ;
+ RECT 1590.980 1.820 1598.780 2.700 ;
+ RECT 1600.500 1.820 1608.300 2.700 ;
+ RECT 1610.020 1.820 1617.820 2.700 ;
+ RECT 1619.540 1.820 1627.340 2.700 ;
+ RECT 1629.060 1.820 1636.860 2.700 ;
+ RECT 1638.580 1.820 1646.380 2.700 ;
+ RECT 1648.100 1.820 1655.900 2.700 ;
+ RECT 1657.620 1.820 1665.420 2.700 ;
+ RECT 1667.140 1.820 1674.940 2.700 ;
+ RECT 1676.660 1.820 1684.460 2.700 ;
+ RECT 1686.180 1.820 1693.980 2.700 ;
+ RECT 1695.700 1.820 1703.500 2.700 ;
+ RECT 1705.220 1.820 1713.020 2.700 ;
+ RECT 1714.740 1.820 1722.540 2.700 ;
+ RECT 1724.260 1.820 1732.060 2.700 ;
+ RECT 1733.780 1.820 1741.580 2.700 ;
+ RECT 1743.300 1.820 1751.100 2.700 ;
+ RECT 1752.820 1.820 1760.620 2.700 ;
+ RECT 1762.340 1.820 1770.140 2.700 ;
+ RECT 1771.860 1.820 1779.660 2.700 ;
+ RECT 1781.380 1.820 1789.180 2.700 ;
+ RECT 1790.900 1.820 1798.700 2.700 ;
+ RECT 1800.420 1.820 1808.220 2.700 ;
+ RECT 1809.940 1.820 1817.740 2.700 ;
+ RECT 1819.460 1.820 1827.260 2.700 ;
+ RECT 1828.980 1.820 1836.780 2.700 ;
+ RECT 1838.500 1.820 1846.300 2.700 ;
+ RECT 1848.020 1.820 1855.820 2.700 ;
+ RECT 1857.540 1.820 1865.340 2.700 ;
+ RECT 1867.060 1.820 1874.860 2.700 ;
+ RECT 1876.580 1.820 1884.380 2.700 ;
+ RECT 1886.100 1.820 1893.900 2.700 ;
+ RECT 1895.620 1.820 1903.420 2.700 ;
+ RECT 1905.140 1.820 1912.940 2.700 ;
+ RECT 1914.660 1.820 1922.460 2.700 ;
+ RECT 1924.180 1.820 1931.980 2.700 ;
+ RECT 1933.700 1.820 1941.500 2.700 ;
+ RECT 1943.220 1.820 1951.020 2.700 ;
+ RECT 1952.740 1.820 1960.540 2.700 ;
+ RECT 1962.260 1.820 1970.060 2.700 ;
+ RECT 1971.780 1.820 1979.580 2.700 ;
+ RECT 1981.300 1.820 1989.100 2.700 ;
+ RECT 1990.820 1.820 1998.620 2.700 ;
+ RECT 2000.340 1.820 2008.140 2.700 ;
+ RECT 2009.860 1.820 2017.660 2.700 ;
+ RECT 2019.380 1.820 2027.180 2.700 ;
+ RECT 2028.900 1.820 2036.700 2.700 ;
+ RECT 2038.420 1.820 2046.220 2.700 ;
+ RECT 2047.940 1.820 2055.740 2.700 ;
+ RECT 2057.460 1.820 2065.260 2.700 ;
+ RECT 2066.980 1.820 2074.780 2.700 ;
+ RECT 2076.500 1.820 2084.300 2.700 ;
+ RECT 2086.020 1.820 2093.820 2.700 ;
+ RECT 2095.540 1.820 2103.340 2.700 ;
+ RECT 2105.060 1.820 2112.860 2.700 ;
+ RECT 2114.580 1.820 2122.380 2.700 ;
+ RECT 2124.100 1.820 2131.900 2.700 ;
+ RECT 2133.620 1.820 2141.420 2.700 ;
+ RECT 2143.140 1.820 2150.940 2.700 ;
+ RECT 2152.660 1.820 2160.460 2.700 ;
+ RECT 2162.180 1.820 2169.980 2.700 ;
+ RECT 2171.700 1.820 2179.500 2.700 ;
+ RECT 2181.220 1.820 2189.020 2.700 ;
+ RECT 2190.740 1.820 2198.540 2.700 ;
+ RECT 2200.260 1.820 2208.060 2.700 ;
+ RECT 2209.780 1.820 2217.580 2.700 ;
+ RECT 2219.300 1.820 2227.100 2.700 ;
+ RECT 2228.820 1.820 2236.620 2.700 ;
+ RECT 2238.340 1.820 2246.140 2.700 ;
+ RECT 2247.860 1.820 2255.660 2.700 ;
+ RECT 2257.380 1.820 2265.180 2.700 ;
+ RECT 2266.900 1.820 2274.700 2.700 ;
+ RECT 2276.420 1.820 2284.220 2.700 ;
+ RECT 2285.940 1.820 2293.740 2.700 ;
+ RECT 2295.460 1.820 2303.260 2.700 ;
+ RECT 2304.980 1.820 2312.780 2.700 ;
+ RECT 2314.500 1.820 2322.300 2.700 ;
+ RECT 2324.020 1.820 2331.820 2.700 ;
+ RECT 2333.540 1.820 2341.340 2.700 ;
+ RECT 2343.060 1.820 2350.860 2.700 ;
+ RECT 2352.580 1.820 2360.380 2.700 ;
+ RECT 2362.100 1.820 2369.900 2.700 ;
+ RECT 2371.620 1.820 2379.420 2.700 ;
+ RECT 2381.140 1.820 2388.940 2.700 ;
+ RECT 2390.660 1.820 2398.460 2.700 ;
+ RECT 2400.180 1.820 2407.980 2.700 ;
+ RECT 2409.700 1.820 2417.500 2.700 ;
+ RECT 2419.220 1.820 2427.020 2.700 ;
+ RECT 2428.740 1.820 2436.540 2.700 ;
+ RECT 2438.260 1.820 2446.060 2.700 ;
+ RECT 2447.780 1.820 2455.580 2.700 ;
+ RECT 2457.300 1.820 2465.100 2.700 ;
+ RECT 2466.820 1.820 2474.620 2.700 ;
+ RECT 2476.340 1.820 2484.140 2.700 ;
+ RECT 2485.860 1.820 2493.660 2.700 ;
+ RECT 2495.380 1.820 2503.180 2.700 ;
+ RECT 2504.900 1.820 2512.700 2.700 ;
+ RECT 2514.420 1.820 2522.220 2.700 ;
+ RECT 2523.940 1.820 2531.740 2.700 ;
+ RECT 2533.460 1.820 2541.260 2.700 ;
+ RECT 2542.980 1.820 2550.780 2.700 ;
+ RECT 2552.500 1.820 2560.300 2.700 ;
+ RECT 2562.020 1.820 2569.820 2.700 ;
+ RECT 2571.540 1.820 2579.340 2.700 ;
+ RECT 2581.060 1.820 2588.860 2.700 ;
+ RECT 2590.580 1.820 2598.380 2.700 ;
+ RECT 2600.100 1.820 2607.900 2.700 ;
+ RECT 2609.620 1.820 2617.420 2.700 ;
+ RECT 2619.140 1.820 2626.940 2.700 ;
+ RECT 2628.660 1.820 2636.460 2.700 ;
+ RECT 2638.180 1.820 2645.980 2.700 ;
+ RECT 2647.700 1.820 2655.500 2.700 ;
+ RECT 2657.220 1.820 2665.020 2.700 ;
+ RECT 2666.740 1.820 2674.540 2.700 ;
+ RECT 2676.260 1.820 2684.060 2.700 ;
+ RECT 2685.780 1.820 2693.580 2.700 ;
+ RECT 2695.300 1.820 2703.100 2.700 ;
+ RECT 2704.820 1.820 2712.620 2.700 ;
+ RECT 2714.340 1.820 2722.140 2.700 ;
+ RECT 2723.860 1.820 2731.660 2.700 ;
+ RECT 2733.380 1.820 2741.180 2.700 ;
+ RECT 2742.900 1.820 2750.700 2.700 ;
+ RECT 2752.420 1.820 2760.220 2.700 ;
+ RECT 2761.940 1.820 2769.740 2.700 ;
+ RECT 2771.460 1.820 2779.260 2.700 ;
+ RECT 2780.980 1.820 2788.780 2.700 ;
+ RECT 2790.500 1.820 2798.300 2.700 ;
+ RECT 2800.020 1.820 2807.820 2.700 ;
+ RECT 2809.540 1.820 2817.340 2.700 ;
+ RECT 2819.060 1.820 2826.860 2.700 ;
+ RECT 2828.580 1.820 2836.380 2.700 ;
+ RECT 2838.100 1.820 2845.900 2.700 ;
+ RECT 2847.620 1.820 2855.420 2.700 ;
+ RECT 2857.140 1.820 2864.940 2.700 ;
+ RECT 2866.660 1.820 2874.460 2.700 ;
+ RECT 2876.180 1.820 2883.980 2.700 ;
+ RECT 2885.700 1.820 2893.500 2.700 ;
+ RECT 2895.220 1.820 2903.020 2.700 ;
+ RECT 2904.740 1.820 2912.540 2.700 ;
+ RECT 2914.260 1.820 2922.060 2.700 ;
+ RECT 2923.780 1.820 2971.220 2.700 ;
+ LAYER Metal3 ;
+ RECT 1.960 2944.500 2978.500 2968.420 ;
+ RECT 1.960 2942.780 2977.500 2944.500 ;
+ RECT 1.960 2937.220 2978.500 2942.780 ;
+ RECT 2.700 2935.500 2978.500 2937.220 ;
+ RECT 1.960 2878.420 2978.500 2935.500 ;
+ RECT 1.960 2876.700 2977.500 2878.420 ;
+ RECT 1.960 2866.660 2978.500 2876.700 ;
+ RECT 2.700 2864.940 2978.500 2866.660 ;
+ RECT 1.960 2812.340 2978.500 2864.940 ;
+ RECT 1.960 2810.620 2977.500 2812.340 ;
+ RECT 1.960 2796.100 2978.500 2810.620 ;
+ RECT 2.700 2794.380 2978.500 2796.100 ;
+ RECT 1.960 2746.260 2978.500 2794.380 ;
+ RECT 1.960 2744.540 2977.500 2746.260 ;
+ RECT 1.960 2725.540 2978.500 2744.540 ;
+ RECT 2.700 2723.820 2978.500 2725.540 ;
+ RECT 1.960 2680.180 2978.500 2723.820 ;
+ RECT 1.960 2678.460 2977.500 2680.180 ;
+ RECT 1.960 2654.980 2978.500 2678.460 ;
+ RECT 2.700 2653.260 2978.500 2654.980 ;
+ RECT 1.960 2614.100 2978.500 2653.260 ;
+ RECT 1.960 2612.380 2977.500 2614.100 ;
+ RECT 1.960 2584.420 2978.500 2612.380 ;
+ RECT 2.700 2582.700 2978.500 2584.420 ;
+ RECT 1.960 2548.020 2978.500 2582.700 ;
+ RECT 1.960 2546.300 2977.500 2548.020 ;
+ RECT 1.960 2513.860 2978.500 2546.300 ;
+ RECT 2.700 2512.140 2978.500 2513.860 ;
+ RECT 1.960 2481.940 2978.500 2512.140 ;
+ RECT 1.960 2480.220 2977.500 2481.940 ;
+ RECT 1.960 2443.300 2978.500 2480.220 ;
+ RECT 2.700 2441.580 2978.500 2443.300 ;
+ RECT 1.960 2415.860 2978.500 2441.580 ;
+ RECT 1.960 2414.140 2977.500 2415.860 ;
+ RECT 1.960 2372.740 2978.500 2414.140 ;
+ RECT 2.700 2371.020 2978.500 2372.740 ;
+ RECT 1.960 2349.780 2978.500 2371.020 ;
+ RECT 1.960 2348.060 2977.500 2349.780 ;
+ RECT 1.960 2302.180 2978.500 2348.060 ;
+ RECT 2.700 2300.460 2978.500 2302.180 ;
+ RECT 1.960 2283.700 2978.500 2300.460 ;
+ RECT 1.960 2281.980 2977.500 2283.700 ;
+ RECT 1.960 2231.620 2978.500 2281.980 ;
+ RECT 2.700 2229.900 2978.500 2231.620 ;
+ RECT 1.960 2217.620 2978.500 2229.900 ;
+ RECT 1.960 2215.900 2977.500 2217.620 ;
+ RECT 1.960 2161.060 2978.500 2215.900 ;
+ RECT 2.700 2159.340 2978.500 2161.060 ;
+ RECT 1.960 2151.540 2978.500 2159.340 ;
+ RECT 1.960 2149.820 2977.500 2151.540 ;
+ RECT 1.960 2090.500 2978.500 2149.820 ;
+ RECT 2.700 2088.780 2978.500 2090.500 ;
+ RECT 1.960 2085.460 2978.500 2088.780 ;
+ RECT 1.960 2083.740 2977.500 2085.460 ;
+ RECT 1.960 2019.940 2978.500 2083.740 ;
+ RECT 2.700 2019.380 2978.500 2019.940 ;
+ RECT 2.700 2018.220 2977.500 2019.380 ;
+ RECT 1.960 2017.660 2977.500 2018.220 ;
+ RECT 1.960 1953.300 2978.500 2017.660 ;
+ RECT 1.960 1951.580 2977.500 1953.300 ;
+ RECT 1.960 1949.380 2978.500 1951.580 ;
+ RECT 2.700 1947.660 2978.500 1949.380 ;
+ RECT 1.960 1887.220 2978.500 1947.660 ;
+ RECT 1.960 1885.500 2977.500 1887.220 ;
+ RECT 1.960 1878.820 2978.500 1885.500 ;
+ RECT 2.700 1877.100 2978.500 1878.820 ;
+ RECT 1.960 1821.140 2978.500 1877.100 ;
+ RECT 1.960 1819.420 2977.500 1821.140 ;
+ RECT 1.960 1808.260 2978.500 1819.420 ;
+ RECT 2.700 1806.540 2978.500 1808.260 ;
+ RECT 1.960 1755.060 2978.500 1806.540 ;
+ RECT 1.960 1753.340 2977.500 1755.060 ;
+ RECT 1.960 1737.700 2978.500 1753.340 ;
+ RECT 2.700 1735.980 2978.500 1737.700 ;
+ RECT 1.960 1688.980 2978.500 1735.980 ;
+ RECT 1.960 1687.260 2977.500 1688.980 ;
+ RECT 1.960 1667.140 2978.500 1687.260 ;
+ RECT 2.700 1665.420 2978.500 1667.140 ;
+ RECT 1.960 1622.900 2978.500 1665.420 ;
+ RECT 1.960 1621.180 2977.500 1622.900 ;
+ RECT 1.960 1596.580 2978.500 1621.180 ;
+ RECT 2.700 1594.860 2978.500 1596.580 ;
+ RECT 1.960 1556.820 2978.500 1594.860 ;
+ RECT 1.960 1555.100 2977.500 1556.820 ;
+ RECT 1.960 1526.020 2978.500 1555.100 ;
+ RECT 2.700 1524.300 2978.500 1526.020 ;
+ RECT 1.960 1490.740 2978.500 1524.300 ;
+ RECT 1.960 1489.020 2977.500 1490.740 ;
+ RECT 1.960 1455.460 2978.500 1489.020 ;
+ RECT 2.700 1453.740 2978.500 1455.460 ;
+ RECT 1.960 1424.660 2978.500 1453.740 ;
+ RECT 1.960 1422.940 2977.500 1424.660 ;
+ RECT 1.960 1384.900 2978.500 1422.940 ;
+ RECT 2.700 1383.180 2978.500 1384.900 ;
+ RECT 1.960 1358.580 2978.500 1383.180 ;
+ RECT 1.960 1356.860 2977.500 1358.580 ;
+ RECT 1.960 1314.340 2978.500 1356.860 ;
+ RECT 2.700 1312.620 2978.500 1314.340 ;
+ RECT 1.960 1292.500 2978.500 1312.620 ;
+ RECT 1.960 1290.780 2977.500 1292.500 ;
+ RECT 1.960 1243.780 2978.500 1290.780 ;
+ RECT 2.700 1242.060 2978.500 1243.780 ;
+ RECT 1.960 1226.420 2978.500 1242.060 ;
+ RECT 1.960 1224.700 2977.500 1226.420 ;
+ RECT 1.960 1173.220 2978.500 1224.700 ;
+ RECT 2.700 1171.500 2978.500 1173.220 ;
+ RECT 1.960 1160.340 2978.500 1171.500 ;
+ RECT 1.960 1158.620 2977.500 1160.340 ;
+ RECT 1.960 1102.660 2978.500 1158.620 ;
+ RECT 2.700 1100.940 2978.500 1102.660 ;
+ RECT 1.960 1094.260 2978.500 1100.940 ;
+ RECT 1.960 1092.540 2977.500 1094.260 ;
+ RECT 1.960 1032.100 2978.500 1092.540 ;
+ RECT 2.700 1030.380 2978.500 1032.100 ;
+ RECT 1.960 1028.180 2978.500 1030.380 ;
+ RECT 1.960 1026.460 2977.500 1028.180 ;
+ RECT 1.960 962.100 2978.500 1026.460 ;
+ RECT 1.960 961.540 2977.500 962.100 ;
+ RECT 2.700 960.380 2977.500 961.540 ;
+ RECT 2.700 959.820 2978.500 960.380 ;
+ RECT 1.960 896.020 2978.500 959.820 ;
+ RECT 1.960 894.300 2977.500 896.020 ;
+ RECT 1.960 890.980 2978.500 894.300 ;
+ RECT 2.700 889.260 2978.500 890.980 ;
+ RECT 1.960 829.940 2978.500 889.260 ;
+ RECT 1.960 828.220 2977.500 829.940 ;
+ RECT 1.960 820.420 2978.500 828.220 ;
+ RECT 2.700 818.700 2978.500 820.420 ;
+ RECT 1.960 763.860 2978.500 818.700 ;
+ RECT 1.960 762.140 2977.500 763.860 ;
+ RECT 1.960 749.860 2978.500 762.140 ;
+ RECT 2.700 748.140 2978.500 749.860 ;
+ RECT 1.960 697.780 2978.500 748.140 ;
+ RECT 1.960 696.060 2977.500 697.780 ;
+ RECT 1.960 679.300 2978.500 696.060 ;
+ RECT 2.700 677.580 2978.500 679.300 ;
+ RECT 1.960 631.700 2978.500 677.580 ;
+ RECT 1.960 629.980 2977.500 631.700 ;
+ RECT 1.960 608.740 2978.500 629.980 ;
+ RECT 2.700 607.020 2978.500 608.740 ;
+ RECT 1.960 565.620 2978.500 607.020 ;
+ RECT 1.960 563.900 2977.500 565.620 ;
+ RECT 1.960 538.180 2978.500 563.900 ;
+ RECT 2.700 536.460 2978.500 538.180 ;
+ RECT 1.960 499.540 2978.500 536.460 ;
+ RECT 1.960 497.820 2977.500 499.540 ;
+ RECT 1.960 467.620 2978.500 497.820 ;
+ RECT 2.700 465.900 2978.500 467.620 ;
+ RECT 1.960 433.460 2978.500 465.900 ;
+ RECT 1.960 431.740 2977.500 433.460 ;
+ RECT 1.960 397.060 2978.500 431.740 ;
+ RECT 2.700 395.340 2978.500 397.060 ;
+ RECT 1.960 367.380 2978.500 395.340 ;
+ RECT 1.960 365.660 2977.500 367.380 ;
+ RECT 1.960 326.500 2978.500 365.660 ;
+ RECT 2.700 324.780 2978.500 326.500 ;
+ RECT 1.960 301.300 2978.500 324.780 ;
+ RECT 1.960 299.580 2977.500 301.300 ;
+ RECT 1.960 255.940 2978.500 299.580 ;
+ RECT 2.700 254.220 2978.500 255.940 ;
+ RECT 1.960 235.220 2978.500 254.220 ;
+ RECT 1.960 233.500 2977.500 235.220 ;
+ RECT 1.960 185.380 2978.500 233.500 ;
+ RECT 2.700 183.660 2978.500 185.380 ;
+ RECT 1.960 169.140 2978.500 183.660 ;
+ RECT 1.960 167.420 2977.500 169.140 ;
+ RECT 1.960 114.820 2978.500 167.420 ;
+ RECT 2.700 113.100 2978.500 114.820 ;
+ RECT 1.960 103.060 2978.500 113.100 ;
+ RECT 1.960 101.340 2977.500 103.060 ;
+ RECT 1.960 44.260 2978.500 101.340 ;
+ RECT 2.700 42.540 2978.500 44.260 ;
+ RECT 1.960 36.980 2978.500 42.540 ;
+ RECT 1.960 35.260 2977.500 36.980 ;
+ RECT 1.960 15.540 2978.500 35.260 ;
+ LAYER Metal4 ;
+ RECT 70.700 2587.510 410.030 2874.380 ;
+ RECT 70.700 2463.290 105.470 2587.510 ;
+ RECT 109.170 2463.290 150.470 2587.510 ;
+ RECT 154.170 2463.290 195.470 2587.510 ;
+ RECT 199.170 2586.560 285.470 2587.510 ;
+ RECT 199.170 2465.360 240.470 2586.560 ;
+ RECT 244.170 2465.360 285.470 2586.560 ;
+ RECT 199.170 2463.290 285.470 2465.360 ;
+ RECT 289.170 2463.290 330.470 2587.510 ;
+ RECT 334.170 2463.290 375.470 2587.510 ;
+ RECT 379.170 2567.000 410.030 2587.510 ;
+ RECT 413.730 2567.000 420.470 2874.380 ;
+ RECT 379.170 2489.800 420.470 2567.000 ;
+ RECT 379.170 2463.290 410.030 2489.800 ;
+ RECT 70.700 2173.510 410.030 2463.290 ;
+ RECT 70.700 2049.290 105.470 2173.510 ;
+ RECT 109.170 2049.290 150.470 2173.510 ;
+ RECT 154.170 2049.290 195.470 2173.510 ;
+ RECT 199.170 2172.560 285.470 2173.510 ;
+ RECT 199.170 2051.360 240.470 2172.560 ;
+ RECT 244.170 2051.360 285.470 2172.560 ;
+ RECT 199.170 2049.290 285.470 2051.360 ;
+ RECT 289.170 2049.290 330.470 2173.510 ;
+ RECT 334.170 2049.290 375.470 2173.510 ;
+ RECT 379.170 2159.320 410.030 2173.510 ;
+ RECT 413.730 2159.320 420.470 2489.800 ;
+ RECT 379.170 2074.280 420.470 2159.320 ;
+ RECT 379.170 2049.290 410.030 2074.280 ;
+ RECT 70.700 1759.510 410.030 2049.290 ;
+ RECT 70.700 1635.290 105.470 1759.510 ;
+ RECT 109.170 1635.290 150.470 1759.510 ;
+ RECT 154.170 1635.290 195.470 1759.510 ;
+ RECT 199.170 1758.560 285.470 1759.510 ;
+ RECT 199.170 1637.360 240.470 1758.560 ;
+ RECT 244.170 1637.360 285.470 1758.560 ;
+ RECT 199.170 1635.290 285.470 1637.360 ;
+ RECT 289.170 1635.290 330.470 1759.510 ;
+ RECT 334.170 1635.290 375.470 1759.510 ;
+ RECT 379.170 1743.800 410.030 1759.510 ;
+ RECT 413.730 1743.800 420.470 2074.280 ;
+ RECT 379.170 1658.760 420.470 1743.800 ;
+ RECT 379.170 1635.290 410.030 1658.760 ;
+ RECT 70.700 1345.510 410.030 1635.290 ;
+ RECT 70.700 1221.290 105.470 1345.510 ;
+ RECT 109.170 1221.290 150.470 1345.510 ;
+ RECT 154.170 1221.290 195.470 1345.510 ;
+ RECT 199.170 1344.560 285.470 1345.510 ;
+ RECT 199.170 1223.360 240.470 1344.560 ;
+ RECT 244.170 1223.360 285.470 1344.560 ;
+ RECT 199.170 1221.290 285.470 1223.360 ;
+ RECT 289.170 1221.290 330.470 1345.510 ;
+ RECT 334.170 1221.290 375.470 1345.510 ;
+ RECT 379.170 1328.280 410.030 1345.510 ;
+ RECT 413.730 1328.280 420.470 1658.760 ;
+ RECT 379.170 1243.240 420.470 1328.280 ;
+ RECT 379.170 1221.290 410.030 1243.240 ;
+ RECT 70.700 931.510 410.030 1221.290 ;
+ RECT 70.700 807.290 105.470 931.510 ;
+ RECT 109.170 807.290 150.470 931.510 ;
+ RECT 154.170 807.290 195.470 931.510 ;
+ RECT 199.170 930.560 285.470 931.510 ;
+ RECT 199.170 809.360 240.470 930.560 ;
+ RECT 244.170 809.360 285.470 930.560 ;
+ RECT 199.170 807.290 285.470 809.360 ;
+ RECT 289.170 807.290 330.470 931.510 ;
+ RECT 334.170 807.290 375.470 931.510 ;
+ RECT 379.170 912.760 410.030 931.510 ;
+ RECT 413.730 912.760 420.470 1243.240 ;
+ RECT 379.170 827.765 420.470 912.760 ;
+ RECT 379.170 807.290 410.030 827.765 ;
+ RECT 70.700 517.510 410.030 807.290 ;
+ RECT 70.700 393.290 105.470 517.510 ;
+ RECT 109.170 393.290 150.470 517.510 ;
+ RECT 154.170 393.290 195.470 517.510 ;
+ RECT 199.170 516.560 285.470 517.510 ;
+ RECT 199.170 395.360 240.470 516.560 ;
+ RECT 244.170 395.360 285.470 516.560 ;
+ RECT 199.170 393.290 285.470 395.360 ;
+ RECT 289.170 393.290 330.470 517.510 ;
+ RECT 334.170 393.290 375.470 517.510 ;
+ RECT 379.170 497.240 410.030 517.510 ;
+ RECT 413.730 497.240 420.470 827.765 ;
+ RECT 379.170 420.040 420.470 497.240 ;
+ RECT 379.170 393.290 410.030 420.040 ;
+ RECT 70.700 103.510 410.030 393.290 ;
+ RECT 70.700 16.330 105.470 103.510 ;
+ RECT 109.170 16.330 150.470 103.510 ;
+ RECT 154.170 16.330 195.470 103.510 ;
+ RECT 199.170 102.560 285.470 103.510 ;
+ RECT 199.170 16.330 240.470 102.560 ;
+ RECT 244.170 16.330 285.470 102.560 ;
+ RECT 289.170 16.330 330.470 103.510 ;
+ RECT 334.170 16.330 375.470 103.510 ;
+ RECT 379.170 81.720 410.030 103.510 ;
+ RECT 413.730 81.720 420.470 420.040 ;
+ RECT 379.170 16.330 420.470 81.720 ;
+ RECT 424.170 2587.510 735.470 2874.380 ;
+ RECT 424.170 2463.290 465.470 2587.510 ;
+ RECT 469.170 2463.290 510.470 2587.510 ;
+ RECT 514.170 2463.290 555.470 2587.510 ;
+ RECT 559.170 2586.560 645.470 2587.510 ;
+ RECT 559.170 2465.360 600.470 2586.560 ;
+ RECT 604.170 2465.360 645.470 2586.560 ;
+ RECT 559.170 2463.290 645.470 2465.360 ;
+ RECT 649.170 2463.290 690.470 2587.510 ;
+ RECT 694.170 2463.290 735.470 2587.510 ;
+ RECT 424.170 2173.510 735.470 2463.290 ;
+ RECT 424.170 2049.290 465.470 2173.510 ;
+ RECT 469.170 2049.290 510.470 2173.510 ;
+ RECT 514.170 2049.290 555.470 2173.510 ;
+ RECT 559.170 2172.560 645.470 2173.510 ;
+ RECT 559.170 2051.360 600.470 2172.560 ;
+ RECT 604.170 2051.360 645.470 2172.560 ;
+ RECT 559.170 2049.290 645.470 2051.360 ;
+ RECT 649.170 2049.290 690.470 2173.510 ;
+ RECT 694.170 2049.290 735.470 2173.510 ;
+ RECT 424.170 1759.510 735.470 2049.290 ;
+ RECT 424.170 1635.290 465.470 1759.510 ;
+ RECT 469.170 1635.290 510.470 1759.510 ;
+ RECT 514.170 1635.290 555.470 1759.510 ;
+ RECT 559.170 1758.560 645.470 1759.510 ;
+ RECT 559.170 1637.360 600.470 1758.560 ;
+ RECT 604.170 1637.360 645.470 1758.560 ;
+ RECT 559.170 1635.290 645.470 1637.360 ;
+ RECT 649.170 1635.290 690.470 1759.510 ;
+ RECT 694.170 1635.290 735.470 1759.510 ;
+ RECT 424.170 1345.510 735.470 1635.290 ;
+ RECT 424.170 1221.290 465.470 1345.510 ;
+ RECT 469.170 1221.290 510.470 1345.510 ;
+ RECT 514.170 1221.290 555.470 1345.510 ;
+ RECT 559.170 1344.560 645.470 1345.510 ;
+ RECT 559.170 1223.360 600.470 1344.560 ;
+ RECT 604.170 1223.360 645.470 1344.560 ;
+ RECT 559.170 1221.290 645.470 1223.360 ;
+ RECT 649.170 1221.290 690.470 1345.510 ;
+ RECT 694.170 1221.290 735.470 1345.510 ;
+ RECT 424.170 931.510 735.470 1221.290 ;
+ RECT 424.170 807.290 465.470 931.510 ;
+ RECT 469.170 807.290 510.470 931.510 ;
+ RECT 514.170 807.290 555.470 931.510 ;
+ RECT 559.170 930.560 645.470 931.510 ;
+ RECT 559.170 809.360 600.470 930.560 ;
+ RECT 604.170 809.360 645.470 930.560 ;
+ RECT 559.170 807.290 645.470 809.360 ;
+ RECT 649.170 807.290 690.470 931.510 ;
+ RECT 694.170 807.290 735.470 931.510 ;
+ RECT 424.170 517.510 735.470 807.290 ;
+ RECT 424.170 393.290 465.470 517.510 ;
+ RECT 469.170 393.290 510.470 517.510 ;
+ RECT 514.170 393.290 555.470 517.510 ;
+ RECT 559.170 516.560 645.470 517.510 ;
+ RECT 559.170 395.360 600.470 516.560 ;
+ RECT 604.170 395.360 645.470 516.560 ;
+ RECT 559.170 393.290 645.470 395.360 ;
+ RECT 649.170 393.290 690.470 517.510 ;
+ RECT 694.170 393.290 735.470 517.510 ;
+ RECT 424.170 103.510 735.470 393.290 ;
+ RECT 424.170 16.330 465.470 103.510 ;
+ RECT 469.170 16.330 510.470 103.510 ;
+ RECT 514.170 16.330 555.470 103.510 ;
+ RECT 559.170 102.560 645.470 103.510 ;
+ RECT 559.170 16.330 600.470 102.560 ;
+ RECT 604.170 16.330 645.470 102.560 ;
+ RECT 649.170 16.330 690.470 103.510 ;
+ RECT 694.170 16.330 735.470 103.510 ;
+ RECT 739.170 2697.560 780.470 2874.380 ;
+ RECT 739.170 2570.920 745.470 2697.560 ;
+ RECT 749.170 2671.750 780.470 2697.560 ;
+ RECT 784.170 2671.750 825.470 2874.380 ;
+ RECT 829.170 2671.750 870.470 2874.380 ;
+ RECT 874.170 2671.750 915.470 2874.380 ;
+ RECT 919.170 2671.750 960.470 2874.380 ;
+ RECT 964.170 2671.750 1005.470 2874.380 ;
+ RECT 1009.170 2671.750 1050.470 2874.380 ;
+ RECT 1054.170 2671.750 1095.470 2874.380 ;
+ RECT 1099.170 2671.750 1140.470 2874.380 ;
+ RECT 1144.170 2674.380 1185.470 2874.380 ;
+ RECT 1189.170 2674.380 1230.470 2874.380 ;
+ RECT 1144.170 2671.750 1230.470 2674.380 ;
+ RECT 1234.170 2671.750 1275.470 2874.380 ;
+ RECT 1279.170 2671.750 1320.470 2874.380 ;
+ RECT 1324.170 2674.380 1365.470 2874.380 ;
+ RECT 1369.170 2674.380 1410.470 2874.380 ;
+ RECT 1324.170 2671.750 1410.470 2674.380 ;
+ RECT 1414.170 2671.750 1455.470 2874.380 ;
+ RECT 1459.170 2671.750 1500.470 2874.380 ;
+ RECT 1504.170 2671.750 1545.470 2874.380 ;
+ RECT 1549.170 2671.750 1590.470 2874.380 ;
+ RECT 1594.170 2671.750 1635.470 2874.380 ;
+ RECT 1639.170 2671.750 1680.470 2874.380 ;
+ RECT 1684.170 2671.750 1725.470 2874.380 ;
+ RECT 1729.170 2671.750 1770.470 2874.380 ;
+ RECT 1774.170 2671.750 1815.470 2874.380 ;
+ RECT 1819.170 2671.750 1860.470 2874.380 ;
+ RECT 1864.170 2671.750 1905.470 2874.380 ;
+ RECT 1909.170 2671.750 1950.470 2874.380 ;
+ RECT 1954.170 2671.750 1995.470 2874.380 ;
+ RECT 1999.170 2671.750 2040.470 2874.380 ;
+ RECT 2044.170 2671.750 2085.470 2874.380 ;
+ RECT 2089.170 2671.750 2130.470 2874.380 ;
+ RECT 2134.170 2671.750 2175.470 2874.380 ;
+ RECT 2179.170 2671.750 2220.470 2874.380 ;
+ RECT 2224.170 2671.750 2265.470 2874.380 ;
+ RECT 2269.170 2671.750 2310.470 2874.380 ;
+ RECT 2314.170 2671.750 2355.470 2874.380 ;
+ RECT 2359.170 2671.750 2400.470 2874.380 ;
+ RECT 2404.170 2671.750 2445.470 2874.380 ;
+ RECT 2449.170 2671.750 2490.470 2874.380 ;
+ RECT 2494.170 2671.750 2535.470 2874.380 ;
+ RECT 2539.170 2671.750 2580.470 2874.380 ;
+ RECT 2584.170 2671.750 2625.470 2874.380 ;
+ RECT 2629.170 2671.750 2670.470 2874.380 ;
+ RECT 2674.170 2671.750 2715.470 2874.380 ;
+ RECT 2719.170 2671.750 2760.470 2874.380 ;
+ RECT 2764.170 2671.750 2805.470 2874.380 ;
+ RECT 2809.170 2671.750 2850.470 2874.380 ;
+ RECT 2854.170 2674.380 2895.470 2874.380 ;
+ RECT 2899.170 2674.380 2940.470 2874.380 ;
+ RECT 2854.170 2671.750 2940.470 2674.380 ;
+ RECT 749.170 2570.920 2940.470 2671.750 ;
+ RECT 739.170 2485.880 2940.470 2570.920 ;
+ RECT 739.170 2155.400 745.470 2485.880 ;
+ RECT 749.170 2155.400 2940.470 2485.880 ;
+ RECT 739.170 2070.360 2940.470 2155.400 ;
+ RECT 739.170 1739.880 745.470 2070.360 ;
+ RECT 749.170 1739.880 2940.470 2070.360 ;
+ RECT 739.170 1654.840 2940.470 1739.880 ;
+ RECT 739.170 1324.360 745.470 1654.840 ;
+ RECT 749.170 1324.360 2940.470 1654.840 ;
+ RECT 739.170 1247.160 2940.470 1324.360 ;
+ RECT 739.170 916.680 745.470 1247.160 ;
+ RECT 749.170 916.680 2940.470 1247.160 ;
+ RECT 739.170 831.640 2940.470 916.680 ;
+ RECT 739.170 501.160 745.470 831.640 ;
+ RECT 749.170 501.160 2940.470 831.640 ;
+ RECT 739.170 416.120 2940.470 501.160 ;
+ RECT 739.170 320.840 745.470 416.120 ;
+ RECT 749.170 332.930 2940.470 416.120 ;
+ RECT 749.170 320.840 780.470 332.930 ;
+ RECT 739.170 16.330 780.470 320.840 ;
+ RECT 784.170 16.330 825.470 332.930 ;
+ RECT 829.170 16.330 870.470 332.930 ;
+ RECT 874.170 16.330 915.470 332.930 ;
+ RECT 919.170 16.330 960.470 332.930 ;
+ RECT 964.170 16.330 1005.470 332.930 ;
+ RECT 1009.170 16.330 1050.470 332.930 ;
+ RECT 1054.170 16.330 1095.470 332.930 ;
+ RECT 1099.170 16.330 1140.470 332.930 ;
+ RECT 1144.170 16.330 1185.470 332.930 ;
+ RECT 1189.170 16.330 1230.470 332.930 ;
+ RECT 1234.170 16.330 1275.470 332.930 ;
+ RECT 1279.170 16.330 1320.470 332.930 ;
+ RECT 1324.170 16.330 1365.470 332.930 ;
+ RECT 1369.170 16.330 1410.470 332.930 ;
+ RECT 1414.170 16.330 1455.470 332.930 ;
+ RECT 1459.170 16.330 1500.470 332.930 ;
+ RECT 1504.170 16.330 1545.470 332.930 ;
+ RECT 1549.170 16.330 1590.470 332.930 ;
+ RECT 1594.170 16.330 1635.470 332.930 ;
+ RECT 1639.170 16.330 1680.470 332.930 ;
+ RECT 1684.170 16.330 1725.470 332.930 ;
+ RECT 1729.170 16.330 1770.470 332.930 ;
+ RECT 1774.170 16.330 1815.470 332.930 ;
+ RECT 1819.170 16.330 1860.470 332.930 ;
+ RECT 1864.170 16.330 1905.470 332.930 ;
+ RECT 1909.170 16.330 1950.470 332.930 ;
+ RECT 1954.170 16.330 1995.470 332.930 ;
+ RECT 1999.170 16.330 2040.470 332.930 ;
+ RECT 2044.170 16.330 2085.470 332.930 ;
+ RECT 2089.170 16.330 2130.470 332.930 ;
+ RECT 2134.170 16.330 2175.470 332.930 ;
+ RECT 2179.170 16.330 2220.470 332.930 ;
+ RECT 2224.170 16.330 2265.470 332.930 ;
+ RECT 2269.170 16.330 2310.470 332.930 ;
+ RECT 2314.170 16.330 2355.470 332.930 ;
+ RECT 2359.170 16.330 2400.470 332.930 ;
+ RECT 2404.170 16.330 2445.470 332.930 ;
+ RECT 2449.170 16.330 2490.470 332.930 ;
+ RECT 2494.170 16.330 2535.470 332.930 ;
+ RECT 2539.170 16.330 2580.470 332.930 ;
+ RECT 2584.170 16.330 2625.470 332.930 ;
+ RECT 2629.170 16.330 2670.470 332.930 ;
+ RECT 2674.170 16.330 2715.470 332.930 ;
+ RECT 2719.170 16.330 2760.470 332.930 ;
+ RECT 2764.170 16.330 2805.470 332.930 ;
+ RECT 2809.170 16.330 2850.470 332.930 ;
+ RECT 2854.170 16.330 2895.470 332.930 ;
+ RECT 2899.170 16.330 2940.470 332.930 ;
+ RECT 2944.170 16.330 2958.340 2874.380 ;
+ LAYER Metal5 ;
+ RECT 71.180 2675.730 2958.420 2676.180 ;
+ RECT 71.180 2630.730 2958.420 2671.630 ;
+ RECT 71.180 2585.730 2958.420 2626.630 ;
+ RECT 71.180 2540.730 2958.420 2581.630 ;
+ RECT 71.180 2495.730 2958.420 2536.630 ;
+ RECT 71.180 2450.730 2958.420 2491.630 ;
+ RECT 71.180 2405.730 2958.420 2446.630 ;
+ RECT 71.180 2360.730 2958.420 2401.630 ;
+ RECT 71.180 2315.730 2958.420 2356.630 ;
+ RECT 71.180 2270.730 2958.420 2311.630 ;
+ RECT 71.180 2225.730 2958.420 2266.630 ;
+ RECT 71.180 2180.730 2958.420 2221.630 ;
+ RECT 71.180 2135.730 2958.420 2176.630 ;
+ RECT 71.180 2090.730 2958.420 2131.630 ;
+ RECT 71.180 2045.730 2958.420 2086.630 ;
+ RECT 71.180 2000.730 2958.420 2041.630 ;
+ RECT 71.180 1955.730 2958.420 1996.630 ;
+ RECT 71.180 1910.730 2958.420 1951.630 ;
+ RECT 71.180 1865.730 2958.420 1906.630 ;
+ RECT 71.180 1820.730 2958.420 1861.630 ;
+ RECT 71.180 1775.730 2958.420 1816.630 ;
+ RECT 71.180 1730.730 2958.420 1771.630 ;
+ RECT 71.180 1685.730 2958.420 1726.630 ;
+ RECT 71.180 1640.730 2958.420 1681.630 ;
+ RECT 71.180 1595.730 2958.420 1636.630 ;
+ RECT 71.180 1550.730 2958.420 1591.630 ;
+ RECT 71.180 1505.730 2958.420 1546.630 ;
+ RECT 71.180 1460.730 2958.420 1501.630 ;
+ RECT 71.180 1415.730 2958.420 1456.630 ;
+ RECT 71.180 1370.730 2958.420 1411.630 ;
+ RECT 71.180 1325.730 2958.420 1366.630 ;
+ RECT 71.180 1280.730 2958.420 1321.630 ;
+ RECT 71.180 1235.730 2958.420 1276.630 ;
+ RECT 71.180 1190.730 2958.420 1231.630 ;
+ RECT 71.180 1145.730 2958.420 1186.630 ;
+ RECT 71.180 1100.730 2958.420 1141.630 ;
+ RECT 71.180 1055.730 2958.420 1096.630 ;
+ RECT 71.180 1010.730 2958.420 1051.630 ;
+ RECT 71.180 965.730 2958.420 1006.630 ;
+ RECT 71.180 920.730 2958.420 961.630 ;
+ RECT 71.180 875.730 2958.420 916.630 ;
+ RECT 71.180 830.730 2958.420 871.630 ;
+ RECT 71.180 785.730 2958.420 826.630 ;
+ RECT 71.180 740.730 2958.420 781.630 ;
+ RECT 71.180 695.730 2958.420 736.630 ;
+ RECT 71.180 650.730 2958.420 691.630 ;
+ RECT 71.180 605.730 2958.420 646.630 ;
+ RECT 71.180 560.730 2958.420 601.630 ;
+ RECT 71.180 515.730 2958.420 556.630 ;
+ RECT 71.180 470.730 2958.420 511.630 ;
+ RECT 71.180 425.730 2958.420 466.630 ;
+ RECT 71.180 380.730 2958.420 421.630 ;
+ RECT 71.180 335.730 2958.420 376.630 ;
+ RECT 775.840 331.630 2940.760 335.730 ;
+ RECT 71.180 290.730 2958.420 331.630 ;
+ RECT 71.180 245.730 2958.420 286.630 ;
+ RECT 71.180 200.730 2958.420 241.630 ;
+ RECT 71.180 155.730 2958.420 196.630 ;
+ RECT 71.180 110.730 2958.420 151.630 ;
+ RECT 71.180 65.730 2958.420 106.630 ;
+ RECT 71.180 37.020 2958.420 61.630 ;
+ END
+END user_project_wrapper
+END LIBRARY
+
diff --git a/openlane/.gitignore b/openlane/.gitignore
new file mode 100644
index 0000000..e4867d8
--- /dev/null
+++ b/openlane/.gitignore
@@ -0,0 +1,2 @@
+*/runs
+default.cvcrc
diff --git a/openlane/Makefile b/openlane/Makefile
new file mode 100644
index 0000000..e1e116f
--- /dev/null
+++ b/openlane/Makefile
@@ -0,0 +1,98 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+MAKEFLAGS+=--warn-undefined-variables
+
+export OPENLANE_RUN_TAG = $(shell date '+%y_%m_%d_%H_%M')
+OPENLANE_TAG ?= 2022.11.29
+OPENLANE_IMAGE_NAME ?= efabless/openlane:$(OPENLANE_TAG)
+designs = $(shell find * -maxdepth 0 -type d)
+current_design = null
+
+openlane_cmd = \
+ "flow.tcl \
+ -design $$(realpath ./$*) \
+ -save_path $$(realpath ..) \
+ -save \
+ -tag $(OPENLANE_RUN_TAG) \
+ -overwrite \
+ -ignore_mismatches"
+openlane_cmd_interactive = "flow.tcl -it -file $$(realpath ./$*/interactive.tcl)"
+
+docker_mounts = \
+ -v $$(realpath $(PWD)/..):$$(realpath $(PWD)/..) \
+ -v $(PDK_ROOT):$(PDK_ROOT) \
+ -v $(CARAVEL_ROOT):$(CARAVEL_ROOT) \
+ -v $(OPENLANE_ROOT):/openlane
+
+docker_env = \
+ -e PDK_ROOT=$(PDK_ROOT) \
+ -e PDK=$(PDK) \
+ -e MISMATCHES_OK=1 \
+ -e CARAVEL_ROOT=$(CARAVEL_ROOT) \
+ -e OPENLANE_RUN_TAG=$(OPENLANE_RUN_TAG)
+
+ifneq ($(MCW_ROOT),)
+docker_env += -e MCW_ROOT=$(MCW_ROOT)
+docker_mounts += -v $(MCW_ROOT):$(MCW_ROOT)
+endif
+
+docker_startup_mode = $(shell test -t 0 && echo "-it" || echo "--rm" )
+docker_run = \
+ docker run $(docker_startup_mode) \
+ $(docker_mounts) \
+ $(docker_env) \
+ -u $(shell id -u $(USER)):$(shell id -g $(USER))
+
+list:
+ @echo $(designs)
+
+.PHONY: $(designs)
+$(designs) : export current_design=$@
+$(designs) : % : ./%/config.tcl
+ifneq (,$(wildcard ./$(current_design)/interactive.tcl))
+ $(docker_run) \
+ $(OPENLANE_IMAGE_NAME) sh -c $(openlane_cmd_interactive)
+else
+ # $(current_design)
+ mkdir -p ./$*/runs/$(OPENLANE_RUN_TAG)
+ rm -rf ./$*/runs/$*
+ ln -s $$(realpath ./$*/runs/$(OPENLANE_RUN_TAG)) ./$*/runs/$*
+ $(docker_run) \
+ $(OPENLANE_IMAGE_NAME) sh -c $(openlane_cmd)
+endif
+ @mkdir -p ../signoff/$*/
+ @cp ./$*/runs/$*/OPENLANE_VERSION ../signoff/$*/
+ @cp ./$*/runs/$*/PDK_SOURCES ../signoff/$*/
+ @cp ./$*/runs/$*/reports/*.csv ../signoff/$*/
+
+.PHONY: openlane
+openlane: check-openlane-env
+ if [ -d "$(OPENLANE_ROOT)" ]; then\
+ echo "Deleting exisiting $(OPENLANE_ROOT)" && \
+ rm -rf $(OPENLANE_ROOT) && sleep 2; \
+ fi
+ git clone https://github.com/The-OpenROAD-Project/OpenLane -b $(OPENLANE_TAG) --depth=1 $(OPENLANE_ROOT) && \
+ cd $(OPENLANE_ROOT) && \
+ export OPENLANE_IMAGE_NAME=efabless/openlane:$(OPENLANE_TAG) && \
+ export IMAGE_NAME=efabless/openlane:$(OPENLANE_TAG) && \
+ $(MAKE) pull-openlane
+
+.PHONY: check-openlane-env
+check-openlane-env:
+ifeq ($(OPENLANE_ROOT),)
+ @echo "Please export OPENLANE_ROOT"
+ @exit 1
+endif
diff --git a/openlane/config.tcl b/openlane/config.tcl
new file mode 100644
index 0000000..95cd6b8
--- /dev/null
+++ b/openlane/config.tcl
@@ -0,0 +1,41 @@
+source $::env(CARAVEL_UPRJ_ROOT)/openlane/user_project_wrapper/fixed_dont_change/default_wrapper_cfgs.tcl
+ source $::env(CARAVEL_UPRJ_ROOT)/openlane/user_project_wrapper/fixed_dont_change/fixed_wrapper_cfgs.tcl
+set ::env(DESIGN_IS_CORE) 1
+set ::env(SYNTH_STRATEGY) "AREA 0"
+set ::env(CLOCK_PERIOD) 100
+set ::env(CLOCK_PORT) "wb_clk_i"
+set ::env(CLOCK_NET) "wb_clk_i"
+set ::env(CLOCK_NETS_EVAL) "{get_full_name \[get_nets -of_objects ariel_fpga_top_inst.config_block_clk_buf.tech_clkbuf/X\]} {get_full_name \[get_nets -of_objects ariel_fpga_top_inst.config_vrnode_clk_buf.tech_clkbuf/X\]} {get_full_name \[get_nets -of_objects ariel_fpga_top_inst.config_hrnode_clk_buf.tech_clkbuf/X\]} "
+set ::env(PL_MAX_DISPLACEMENT_X) 3000
+set ::env(PL_MAX_DISPLACEMENT_Y) 1000
+set ::env(FP_PDN_AUTO_ADJUST) 0
+set ::env(FP_PDN_IRDROP) 0
+set ::env(FP_PDN_HOFFSET) 3
+set ::env(FP_PDN_HORIZONTAL_HALO) 5
+set ::env(FP_PDN_VERTICAL_HALO) 5
+set ::env(PL_TIME_DRIVEN) 1
+set ::env(PL_TARGET_DENSITY) 0.45
+set ::env(DIODE_INSERTION_STRATEGY) 3
+set ::env(PL_RESIZER_MAX_WIRE_LENGTH) 2000.0
+set ::env(PL_RESIZER_ALLOW_SETUP_VIOS) 1
+set ::env(PL_RESIZER_HOLD_SLACK_MARGIN) 0.1
+set ::env(PL_RESIZER_MAX_SLEW_MARGIN) 40
+set ::env(GLB_RESIZER_MAX_SLEW_MARGIN) 40
+set ::env(GLB_RESIZER_HOLD_SLACK_MARGIN) 0.1
+set ::env(GLB_RESIZER_ALLOW_SETUP_VIOS) 1
+set ::env(GLB_RESIZER_TIMING_OPTIMIZATIONS) 1
+set ::env(GRT_ADJUSTMENT) 0.5
+set ::env(PDN_CFG) "/home/egor/proj/fpga/impl/open/pdn_cfg.tcl"
+set ::env(RUN_KLAYOUT_XOR) 0
+set ::env(VERILOG_FILES_BLACKBOX) "/home/egor/proj/fpga/impl/open/macros.v"
+set ::env(EXTRA_LEFS) "/home/egor/proj/fpga/impl/open/best/fpga_struct_block/results/final/lef/fpga_struct_block.lef /home/egor/proj/fpga/impl/open/best/efuse_ctrl/results/final/lef/efuse_ctrl.lef"
+set ::env(EXTRA_GDS_FILES) "/home/egor/proj/fpga/impl/open/best/fpga_struct_block/results/final/gds/fpga_struct_block.gds /home/egor/proj/fpga/impl/open/best/efuse_ctrl/results/final/gds/efuse_ctrl.gds"
+set ::env(MACRO_PLACEMENT_CFG) "designs/user_project_wrapper/macro.cfg"
+set ::env(DESIGN_NAME) user_project_wrapper
+set ::env(VERILOG_FILES) "designs/user_project_wrapper/ariel_fpga_top_fromvhdl.v designs/user_project_wrapper/fpga_tech.v designs/user_project_wrapper/user_project_wrapper.v"
+set ::env(BASE_SDC_FILE) "designs/user_project_wrapper/user_project_wrapper.sdc"
+set ::env(FP_PIN_ORDER_CFG) "designs/user_project_wrapper/pin.cfg"
+set ::env(SYNTH_DRIVING_CELL) "gf180mcu_fd_sc_mcu7t5v0__buf_1"
+set ::env(SYNTH_DRIVING_CELL_PIN) "Z"
+set ::env(ROUTING_CORES) 24
+
diff --git a/openlane/efuse_ctrl/config.tcl b/openlane/efuse_ctrl/config.tcl
new file mode 100644
index 0000000..2c63f34
--- /dev/null
+++ b/openlane/efuse_ctrl/config.tcl
@@ -0,0 +1,748 @@
+# Run configs
+set ::env(PDK_ROOT) {/home/egor/.volare}
+set ::env(BASE_SDC_FILE) {/opt/openeda/OpenLane/scripts/base.sdc}
+set ::env(BOTTOM_MARGIN_MULT) {4}
+set ::env(CARRY_SELECT_ADDER_MAP) {/home/egor/.volare/gf180mcuC/libs.tech/openlane/gf180mcu_fd_sc_mcu7t5v0/csa_map.v}
+set ::env(CELLS_LEF) {/home/egor/.volare/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/lef/gf180mcu_fd_sc_mcu7t5v0.lef}
+set ::env(CELL_PAD_EXCLUDE) {gf180mcu_fd_sc_mcu7t5v0__filltie_* gf180mcu_fd_sc_mcu7t5v0__filldecap_* gf180mcu_fd_sc_mcu7t5v0__fill_* gf180mcu_fd_sc_mcu7t5v0__endcap_*}
+set ::env(CHECK_ASSIGN_STATEMENTS) {0}
+set ::env(CHECK_UNMAPPED_CELLS) {1}
+set ::env(CLOCK_BUFFER_FANOUT) {16}
+set ::env(CLOCK_PERIOD) {20}
+set ::env(CLOCK_PORT) {wb_clk_i}
+set ::env(CLOCK_TREE_SYNTH) {1}
+set ::env(CLOCK_WIRE_RC_LAYER) {Metal4}
+set ::env(CONFIGS) {general.tcl checkers.tcl synthesis.tcl floorplan.tcl cts.tcl placement.tcl routing.tcl extraction.tcl}
+set ::env(CTS_CLK_BUFFER_LIST) {gf180mcu_fd_sc_mcu7t5v0__clkbuf_2 gf180mcu_fd_sc_mcu7t5v0__clkbuf_4 gf180mcu_fd_sc_mcu7t5v0__clkbuf_8}
+set ::env(CTS_CLK_MAX_WIRE_LENGTH) {0}
+set ::env(CTS_DISABLE_POST_PROCESSING) {0}
+set ::env(CTS_DISTANCE_BETWEEN_BUFFERS) {0}
+set ::env(CTS_MAX_CAP) {0.5}
+set ::env(CTS_REPORT_TIMING) {1}
+set ::env(CTS_ROOT_BUFFER) {gf180mcu_fd_sc_mcu7t5v0__clkbuf_16}
+set ::env(CTS_SINK_CLUSTERING_MAX_DIAMETER) {50}
+set ::env(CTS_SINK_CLUSTERING_SIZE) {25}
+set ::env(CTS_TARGET_SKEW) {200}
+set ::env(CTS_TOLERANCE) {100}
+set ::env(DATA_WIRE_RC_LAYER) {Metal2}
+set ::env(DECAP_CELL) {gf180mcu_fd_sc_mcu7t5v0__fillcap_*}
+set ::env(DEFAULT_MAX_TRAN) {3}
+set ::env(DEF_UNITS_PER_MICRON) {2000}
+set ::env(DESIGN_CONFIG) {/home/egor/proj/gf180/gf180_efuse/openlane/config.json}
+set ::env(DESIGN_IS_CORE) {0}
+set ::env(DESIGN_NAME) {efuse_ctrl}
+set ::env(DETAILED_ROUTER) {tritonroute}
+set ::env(DIE_AREA) {0 0 2175 2350}
+set ::env(DIODE_CELL) {gf180mcu_fd_sc_mcu7t5v0__antenna}
+set ::env(DIODE_CELL_PIN) {I}
+set ::env(DIODE_INSERTION_STRATEGY) {4}
+set ::env(DIODE_PADDING) {2}
+set ::env(DPL_CELL_PADDING) {2}
+set ::env(DRC_EXCLUDE_CELL_LIST) {/home/egor/.volare/gf180mcuC/libs.tech/openlane/gf180mcu_fd_sc_mcu7t5v0/drc_exclude.cells}
+set ::env(DRC_EXCLUDE_CELL_LIST_OPT) {/home/egor/.volare/gf180mcuC/libs.tech/openlane/gf180mcu_fd_sc_mcu7t5v0/drc_exclude.cells}
+set ::env(DRT_MIN_LAYER) {Metal1}
+set ::env(DRT_OPT_ITERS) {64}
+set ::env(ECO_ENABLE) {0}
+set ::env(ECO_FINISH) {0}
+set ::env(ECO_ITER) {0}
+set ::env(ECO_SKIP_PIN) {1}
+set ::env(EXTRA_GDS_FILES) {/home/egor/proj/gf180/gf180_efuse/macros/efuse_array.gds}
+set ::env(EXTRA_LEFS) {/home/egor/proj/gf180/gf180_efuse/macros/efuse_array.lef}
+set ::env(FILL_CELL) {gf180mcu_fd_sc_mcu7t5v0__fill_*}
+set ::env(FP_ASPECT_RATIO) {1}
+set ::env(FP_CORE_UTIL) {50}
+set ::env(FP_ENDCAP_CELL) {gf180mcu_fd_sc_mcu7t5v0__endcap}
+set ::env(FP_IO_HEXTEND) {-1}
+set ::env(FP_IO_HLAYER) {Metal3}
+set ::env(FP_IO_HLENGTH) {4}
+set ::env(FP_IO_HTHICKNESS_MULT) {2}
+set ::env(FP_IO_MIN_DISTANCE) {3}
+set ::env(FP_IO_MODE) {1}
+set ::env(FP_IO_UNMATCHED_ERROR) {1}
+set ::env(FP_IO_VEXTEND) {-1}
+set ::env(FP_IO_VLAYER) {Metal2}
+set ::env(FP_IO_VLENGTH) {4}
+set ::env(FP_IO_VTHICKNESS_MULT) {2}
+set ::env(FP_PDN_AUTO_ADJUST) {0}
+set ::env(FP_PDN_CHECK_NODES) {1}
+set ::env(FP_PDN_CORE_RING) {0}
+set ::env(FP_PDN_CORE_RING_HOFFSET) {6}
+set ::env(FP_PDN_CORE_RING_HSPACING) {1.7}
+set ::env(FP_PDN_CORE_RING_HWIDTH) {1.6}
+set ::env(FP_PDN_CORE_RING_VOFFSET) {6}
+set ::env(FP_PDN_CORE_RING_VSPACING) {1.7}
+set ::env(FP_PDN_CORE_RING_VWIDTH) {1.6}
+set ::env(FP_PDN_ENABLE_GLOBAL_CONNECTIONS) {1}
+set ::env(FP_PDN_ENABLE_MACROS_GRID) {1}
+set ::env(FP_PDN_ENABLE_RAILS) {1}
+set ::env(FP_PDN_HOFFSET) {16.65}
+set ::env(FP_PDN_HORIZONTAL_HALO) {3}
+set ::env(FP_PDN_HPITCH) {153.18}
+set ::env(FP_PDN_HSPACING) {1.7}
+set ::env(FP_PDN_HWIDTH) {1.6}
+set ::env(FP_PDN_IRDROP) {1}
+set ::env(FP_PDN_LOWER_LAYER) {Metal4}
+set ::env(FP_PDN_RAILS_LAYER) {Metal1}
+set ::env(FP_PDN_RAIL_OFFSET) {0}
+set ::env(FP_PDN_RAIL_WIDTH) {0.6}
+set ::env(FP_PDN_SKIPTRIM) {0}
+set ::env(FP_PDN_UPPER_LAYER) {Metal5}
+set ::env(FP_PDN_VERTICAL_HALO) {10}
+set ::env(FP_PDN_VOFFSET) {20}
+set ::env(FP_PDN_VPITCH) {190}
+set ::env(FP_PDN_VSPACING) {8}
+set ::env(FP_PDN_VWIDTH) {1.6}
+set ::env(FP_SIZING) {absolute}
+set ::env(FP_TAPCELL_DIST) {20}
+set ::env(FP_TAP_HORIZONTAL_HALO) {3}
+set ::env(FP_TAP_VERTICAL_HALO) {10}
+set ::env(FP_WELLTAP_CELL) {gf180mcu_fd_sc_mcu7t5v0__filltie}
+set ::env(FULL_ADDER_MAP) {/home/egor/.volare/gf180mcuC/libs.tech/openlane/gf180mcu_fd_sc_mcu7t5v0/fa_map.v}
+set ::env(GDS_FILES) {/home/egor/.volare/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/gds/gf180mcu_fd_sc_mcu7t5v0.gds}
+set ::env(GENERATE_FINAL_SUMMARY_REPORT) {1}
+set ::env(GLB_CFG_FILE) {/home/egor/proj/gf180/gf180_efuse/openlane/runs/RUN_2022.12.03_13.12.24/config.tcl}
+set ::env(GLB_OPTIMIZE_MIRRORING) {1}
+set ::env(GLB_RESIZER_ALLOW_SETUP_VIOS) {0}
+set ::env(GLB_RESIZER_HOLD_MAX_BUFFER_PERCENT) {50}
+set ::env(GLB_RESIZER_HOLD_SLACK_MARGIN) {0.05}
+set ::env(GLB_RESIZER_MAX_CAP_MARGIN) {10}
+set ::env(GLB_RESIZER_MAX_SLEW_MARGIN) {10}
+set ::env(GLB_RESIZER_MAX_WIRE_LENGTH) {0}
+set ::env(GLB_RESIZER_SETUP_MAX_BUFFER_PERCENT) {50}
+set ::env(GLB_RESIZER_SETUP_SLACK_MARGIN) {0.025}
+set ::env(GLB_RESIZER_TIMING_OPTIMIZATIONS) {1}
+set ::env(GLOBAL_ROUTER) {fastroute}
+set ::env(GND_PIN) {VSS}
+set ::env(GPIO_PADS_LEF) { /home/egor/.volare/gf180mcuC/libs.ref/gf180mcu_io/lef/GF018green_ipio_5p0c_75_5lm.lef
+}
+set ::env(GPIO_PADS_VERILOG) { /home/egor/.volare/gf180mcuC/libs.ref/gf180mcu_io/verilog/GF018green_ipio_5p0c_75_5lm.v
+}
+set ::env(GPL_CELL_PADDING) {0}
+set ::env(GRT_ADJUSTMENT) {0.3}
+set ::env(GRT_ALLOW_CONGESTION) {1}
+set ::env(GRT_ANT_ITERS) {3}
+set ::env(GRT_ESTIMATE_PARASITICS) {1}
+set ::env(GRT_LAYER_ADJUSTMENTS) {0,0,0,0,0}
+set ::env(GRT_MACRO_EXTENSION) {0}
+set ::env(GRT_MAX_DIODE_INS_ITERS) {1}
+set ::env(GRT_OBS) {Metal5 0 30.5 2175 53.5, Metal5 0 75.5 2175 98.5, Metal5 0 120.5 2175 143.5, Metal5 0 165.5 2175 188.5, Metal5 0 210.5 2175 233.5, Metal5 0 255.5 2175 278.5, Metal5 0 300.5 2175 323.5, Metal5 0 345.5 2175 368.5, Metal5 0 390.5 2175 413.5, Metal5 0 435.5 2175 458.5, Metal5 0 480.5 2175 503.5, Metal5 0 525.5 2175 548.5, Metal5 0 570.5 2175 593.5, Metal5 0 615.5 2175 638.5, Metal5 0 660.5 2175 683.5, Metal5 0 705.5 2175 728.5, Metal5 0 750.5 2175 773.5, Metal5 0 795.5 2175 818.5, Metal5 0 840.5 2175 863.5, Metal5 0 885.5 2175 908.5, Metal5 0 930.5 2175 953.5, Metal5 0 975.5 2175 998.5, Metal5 0 1020.5 2175 1043.5, Metal5 0 1065.5 2175 1088.5, Metal5 0 1110.5 2175 1133.5, Metal5 0 1155.5 2175 1178.5, Metal5 0 1200.5 2175 1223.5, Metal5 0 1245.5 2175 1268.5, Metal5 0 1290.5 2175 1313.5, Metal5 0 1335.5 2175 1358.5, Metal5 0 1380.5 2175 1403.5, Metal5 0 1425.5 2175 1448.5, Metal5 0 1470.5 2175 1493.5, Metal5 0 1515.5 2175 1538.5, Metal5 0 1560.5 2175 1583.5, Metal5 0 1605.5 2175 1628.5, Metal5 0 1650.5 2175 1673.5, Metal5 0 1695.5 2175 1718.5, Metal5 0 1740.5 2175 1763.5, Metal5 0 1785.5 2175 1808.5, Metal5 0 1830.5 2175 1853.5, Metal5 0 1875.5 2175 1898.5, Metal5 0 1920.5 2175 1943.5, Metal5 0 1965.5 2175 1988.5, Metal5 0 2010.5 2175 2033.5, Metal5 0 2055.5 2175 2078.5, Metal5 0 2100.5 2175 2123.5, Metal5 0 2145.5 2175 2168.5, Metal5 0 2190.5 2175 2213.5, Metal5 0 2235.5 2175 2258.5, Metal5 0 2280.5 2175 2303.5, Metal5 0 2325.5 2175 2348.5}
+set ::env(GRT_OVERFLOW_ITERS) {50}
+set ::env(IO_PCT) {0.2}
+set ::env(KLAYOUT_DRC_KLAYOUT_GDS) {0}
+set ::env(KLAYOUT_DRC_TECH_SCRIPT) {/home/egor/.volare/gf180mcuC/libs.tech/klayout/gf180mcuC_mr.drc}
+set ::env(KLAYOUT_PROPERTIES) {/home/egor/.volare/gf180mcuC/libs.tech/klayout/gf180mcuC.lyp}
+set ::env(KLAYOUT_TECH) {/home/egor/.volare/gf180mcuC/libs.tech/klayout/gf180mcuC.lyt}
+set ::env(KLAYOUT_XOR_GDS) {1}
+set ::env(KLAYOUT_XOR_XML) {1}
+set ::env(LEC_ENABLE) {0}
+set ::env(LEFT_MARGIN_MULT) {12}
+set ::env(LIB_FASTEST) {/home/egor/.volare/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/liberty/gf180mcu_fd_sc_mcu7t5v0__ff_n40C_5v50.lib}
+set ::env(LIB_SLOWEST) {/home/egor/.volare/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/liberty/gf180mcu_fd_sc_mcu7t5v0__ss_125C_4v50.lib}
+set ::env(LIB_SYNTH) {/home/egor/.volare/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/liberty/gf180mcu_fd_sc_mcu7t5v0__tt_025C_5v00.lib}
+set ::env(LIB_TYPICAL) {/home/egor/.volare/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/liberty/gf180mcu_fd_sc_mcu7t5v0__tt_025C_5v00.lib}
+set ::env(LOGS_DIR) {/home/egor/proj/gf180/gf180_efuse/openlane/runs/RUN_2022.12.03_13.12.24/logs}
+set ::env(LVS_CONNECT_BY_LABEL) {1}
+set ::env(LVS_INSERT_POWER_PINS) {1}
+set ::env(MACRO_BLOCKAGES_LAYER) {Metal1 Metal2 Metal3 Metal4 Metal5}
+set ::env(MACRO_PLACEMENT_CFG) {macro_placement.cfg}
+set ::env(MAGIC_CONVERT_DRC_TO_RDB) {1}
+set ::env(MAGIC_DEF_LABELS) {1}
+set ::env(MAGIC_DEF_NO_BLOCKAGES) {1}
+set ::env(MAGIC_DISABLE_HIER_GDS) {1}
+set ::env(MAGIC_DRC_USE_GDS) {1}
+set ::env(MAGIC_EXT_USE_GDS) {0}
+set ::env(MAGIC_GENERATE_GDS) {1}
+set ::env(MAGIC_GENERATE_LEF) {1}
+set ::env(MAGIC_GENERATE_MAGLEF) {1}
+set ::env(MAGIC_INCLUDE_GDS_POINTERS) {0}
+set ::env(MAGIC_MAGICRC) {/home/egor/.volare/gf180mcuC/libs.tech/magic/gf180mcuC.magicrc}
+set ::env(MAGIC_PAD) {0}
+set ::env(MAGIC_TECH_FILE) {/home/egor/.volare/gf180mcuC/libs.tech/magic/gf180mcuC.tech}
+set ::env(MAGIC_WRITE_FULL_LEF) {0}
+set ::env(MAGIC_ZEROIZE_ORIGIN) {0}
+set ::env(METAL_LAYER_NAMES) {Metal1 Metal2 Metal3 Metal4 Metal5}
+set ::env(NETGEN_SETUP_FILE) {/home/egor/.volare/gf180mcuC/libs.tech/netgen/gf180mcuC_setup.tcl}
+set ::env(NO_SYNTH_CELL_LIST) {/home/egor/.volare/gf180mcuC/libs.tech/openlane/gf180mcu_fd_sc_mcu7t5v0/no_synth.cells}
+set ::env(OPENLANE_VERBOSE) {0}
+set ::env(PDKPATH) {/home/egor/.volare/gf180mcuC}
+set ::env(PLACE_SITE) {GF018hv5v_mcu_sc7}
+set ::env(PLACE_SITE_HEIGHT) {3.92}
+set ::env(PLACE_SITE_WIDTH) {0.56}
+set ::env(PL_BASIC_PLACEMENT) {0}
+set ::env(PL_ESTIMATE_PARASITICS) {1}
+set ::env(PL_LIB) {/home/egor/.volare/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/liberty/gf180mcu_fd_sc_mcu7t5v0__tt_025C_5v00.lib}
+set ::env(PL_MACRO_CHANNEL) {0 0}
+set ::env(PL_MACRO_HALO) {100 100}
+set ::env(PL_MAX_DISPLACEMENT_X) {2000}
+set ::env(PL_MAX_DISPLACEMENT_Y) {2000}
+set ::env(PL_OPTIMIZE_MIRRORING) {1}
+set ::env(PL_RANDOM_GLB_PLACEMENT) {0}
+set ::env(PL_RANDOM_INITIAL_PLACEMENT) {0}
+set ::env(PL_RESIZER_ALLOW_SETUP_VIOS) {0}
+set ::env(PL_RESIZER_BUFFER_INPUT_PORTS) {1}
+set ::env(PL_RESIZER_BUFFER_OUTPUT_PORTS) {1}
+set ::env(PL_RESIZER_DESIGN_OPTIMIZATIONS) {1}
+set ::env(PL_RESIZER_HOLD_MAX_BUFFER_PERCENT) {50}
+set ::env(PL_RESIZER_HOLD_SLACK_MARGIN) {0.1}
+set ::env(PL_RESIZER_MAX_CAP_MARGIN) {20}
+set ::env(PL_RESIZER_MAX_SLEW_MARGIN) {20}
+set ::env(PL_RESIZER_MAX_WIRE_LENGTH) {0}
+set ::env(PL_RESIZER_REPAIR_TIE_FANOUT) {1}
+set ::env(PL_RESIZER_SETUP_MAX_BUFFER_PERCENT) {50}
+set ::env(PL_RESIZER_SETUP_SLACK_MARGIN) {0.05}
+set ::env(PL_RESIZER_TIE_SEPERATION) {0}
+set ::env(PL_RESIZER_TIMING_OPTIMIZATIONS) {1}
+set ::env(PL_ROUTABILITY_DRIVEN) {1}
+set ::env(PL_SKIP_INITIAL_PLACEMENT) {0}
+set ::env(PL_TARGET_DENSITY) {0.75}
+set ::env(PL_TIME_DRIVEN) {1}
+set ::env(PRIMARY_SIGNOFF_TOOL) {magic}
+set ::env(PROCESS) {180}
+set ::env(QUIT_ON_HOLD_VIOLATIONS) {1}
+set ::env(QUIT_ON_ILLEGAL_OVERLAPS) {1}
+set ::env(QUIT_ON_LONG_WIRE) {0}
+set ::env(QUIT_ON_LVS_ERROR) {1}
+set ::env(QUIT_ON_MAGIC_DRC) {1}
+set ::env(QUIT_ON_SETUP_VIOLATIONS) {1}
+set ::env(QUIT_ON_TIMING_VIOLATIONS) {1}
+set ::env(QUIT_ON_TR_DRC) {1}
+set ::env(RCX_CC_MODEL) {10}
+set ::env(RCX_CONTEXT_DEPTH) {5}
+set ::env(RCX_CORNER_COUNT) {1}
+set ::env(RCX_COUPLING_THRESHOLD) {0.1}
+set ::env(RCX_MAX_RESISTANCE) {50}
+set ::env(RCX_MERGE_VIA_WIRE_RES) {1}
+set ::env(RCX_RULES) {/home/egor/.volare/gf180mcuC/libs.tech/openlane/rules.openrcx.gf180mcuC.nom}
+set ::env(RCX_RULES_MAX) {/home/egor/.volare/gf180mcuC/libs.tech/openlane/rules.openrcx.gf180mcuC.max}
+set ::env(RCX_RULES_MIN) {/home/egor/.volare/gf180mcuC/libs.tech/openlane/rules.openrcx.gf180mcuC.min}
+set ::env(REPORTS_DIR) {/home/egor/proj/gf180/gf180_efuse/openlane/runs/RUN_2022.12.03_13.12.24/reports}
+set ::env(RESULTS_DIR) {/home/egor/proj/gf180/gf180_efuse/openlane/runs/RUN_2022.12.03_13.12.24/results}
+set ::env(RIGHT_MARGIN_MULT) {12}
+set ::env(RIPPLE_CARRY_ADDER_MAP) {/home/egor/.volare/gf180mcuC/libs.tech/openlane/gf180mcu_fd_sc_mcu7t5v0/rca_map.v}
+set ::env(ROUTING_CORES) {24}
+set ::env(RSZ_DONT_TOUCH_RX) {$^}
+set ::env(RSZ_USE_OLD_REMOVER) {0}
+set ::env(RT_MAX_LAYER) {Metal5}
+set ::env(RT_MIN_LAYER) {Metal2}
+set ::env(RUN_CVC) {1}
+set ::env(RUN_DIR) {/home/egor/proj/gf180/gf180_efuse/openlane/runs/RUN_2022.12.03_13.12.24}
+set ::env(RUN_DRT) {1}
+set ::env(RUN_FILL_INSERTION) {1}
+set ::env(RUN_IRDROP_REPORT) {0}
+set ::env(RUN_KLAYOUT) {0}
+set ::env(RUN_KLAYOUT_DRC) {0}
+set ::env(RUN_KLAYOUT_XOR) {0}
+set ::env(RUN_LVS) {1}
+set ::env(RUN_MAGIC) {1}
+set ::env(RUN_MAGIC_DRC) {1}
+set ::env(RUN_SPEF_EXTRACTION) {1}
+set ::env(RUN_TAG) {RUN_2022.12.03_13.12.24}
+set ::env(RUN_TAP_DECAP_INSERTION) {1}
+set ::env(SCLPATH) {/home/egor/.volare/gf180mcuC/gf180mcu_fd_sc_mcu7t5v0}
+set ::env(SPEF_EXTRACTOR) {openrcx}
+set ::env(START_TIME) {2022.12.03_13.12.24}
+set ::env(STA_REPORT_POWER) {1}
+set ::env(STA_WRITE_LIB) {1}
+set ::env(STD_CELL_GROUND_PINS) {VSS}
+set ::env(STD_CELL_LIBRARY_CDL) {/home/egor/.volare/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/cdl/gf180mcu_fd_sc_mcu7t5v0.cdl}
+set ::env(STD_CELL_LIBRARY_OPT) {gf180mcu_fd_sc_mcu7t5v0}
+set ::env(STD_CELL_POWER_PINS) {VDD}
+set ::env(SYNTH_ADDER_TYPE) {YOSYS}
+set ::env(SYNTH_BIN) {yosys}
+set ::env(SYNTH_BUFFERING) {1}
+set ::env(SYNTH_CAP_LOAD) {72.91}
+set ::env(SYNTH_CLK_DRIVING_CELL) {gf180mcu_fd_sc_mcu7t5v0__inv_4}
+set ::env(SYNTH_CLK_DRIVING_CELL_PIN) {ZN}
+set ::env(SYNTH_CLOCK_TRANSITION) {0.15}
+set ::env(SYNTH_CLOCK_UNCERTAINTY) {0.25}
+set ::env(SYNTH_DRIVING_CELL) {gf180mcu_fd_sc_mcu7t5v0__inv_1}
+set ::env(SYNTH_DRIVING_CELL_PIN) {ZN}
+set ::env(SYNTH_ELABORATE_ONLY) {0}
+set ::env(SYNTH_EXTRA_MAPPING_FILE) {}
+set ::env(SYNTH_FLAT_TOP) {0}
+set ::env(SYNTH_LATCH_MAP) {/home/egor/.volare/gf180mcuC/libs.tech/openlane/gf180mcu_fd_sc_mcu7t5v0/latch_map.v}
+set ::env(SYNTH_MAX_FANOUT) {10}
+set ::env(SYNTH_MIN_BUF_PORT) {gf180mcu_fd_sc_mcu7t5v0__buf_1 I Z}
+set ::env(SYNTH_NO_FLAT) {0}
+set ::env(SYNTH_READ_BLACKBOX_LIB) {0}
+set ::env(SYNTH_SCRIPT) {/opt/openeda/OpenLane/scripts/yosys/synth.tcl}
+set ::env(SYNTH_SHARE_RESOURCES) {1}
+set ::env(SYNTH_SIZING) {0}
+set ::env(SYNTH_STRATEGY) {AREA 3}
+set ::env(SYNTH_TIEHI_PORT) {gf180mcu_fd_sc_mcu7t5v0__tieh Z}
+set ::env(SYNTH_TIELO_PORT) {gf180mcu_fd_sc_mcu7t5v0__tiel ZN}
+set ::env(SYNTH_TIMING_DERATE) {0.05}
+set ::env(TAKE_LAYOUT_SCROT) {0}
+set ::env(TECH_LEF) {/home/egor/.volare/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/techlef/gf180mcu_fd_sc_mcu7t5v0.tlef}
+set ::env(TERMINAL_OUTPUT) {/dev/null}
+set ::env(TMP_DIR) {/home/egor/proj/gf180/gf180_efuse/openlane/runs/RUN_2022.12.03_13.12.24/tmp}
+set ::env(TOP_MARGIN_MULT) {4}
+set ::env(TRACKS_INFO_FILE) {/home/egor/.volare/gf180mcuC/libs.tech/openlane/gf180mcu_fd_sc_mcu7t5v0/tracks.info}
+set ::env(TRISTATE_BUFFER_MAP) {/home/egor/.volare/gf180mcuC/libs.tech/openlane/gf180mcu_fd_sc_mcu7t5v0/tribuff_map.v}
+set ::env(USE_ARC_ANTENNA_CHECK) {1}
+set ::env(USE_GPIO_PADS) {0}
+set ::env(VDD_PIN) {VDD}
+set ::env(VERILOG_FILES) {efuse_ctrl_fromvhdl.v ../macros/cells.v}
+set ::env(VERILOG_FILES_BLACKBOX) {/home/egor/proj/gf180/gf180_efuse/macros/efuse_array.v}
+set ::env(WIRE_RC_LAYER) {Metal2}
+set ::env(YOSYS_REWRITE_VERILOG) {0}
+set ::env(cts_logs) {/home/egor/proj/gf180/gf180_efuse/openlane/runs/RUN_2022.12.03_13.12.24/logs/cts}
+set ::env(cts_reports) {/home/egor/proj/gf180/gf180_efuse/openlane/runs/RUN_2022.12.03_13.12.24/reports/cts}
+set ::env(cts_results) {/home/egor/proj/gf180/gf180_efuse/openlane/runs/RUN_2022.12.03_13.12.24/results/cts}
+set ::env(cts_tmpfiles) {/home/egor/proj/gf180/gf180_efuse/openlane/runs/RUN_2022.12.03_13.12.24/tmp/cts}
+set ::env(eco_logs) {/home/egor/proj/gf180/gf180_efuse/openlane/runs/RUN_2022.12.03_13.12.24/logs/eco}
+set ::env(eco_reports) {/home/egor/proj/gf180/gf180_efuse/openlane/runs/RUN_2022.12.03_13.12.24/reports/eco}
+set ::env(eco_results) {/home/egor/proj/gf180/gf180_efuse/openlane/runs/RUN_2022.12.03_13.12.24/results/eco}
+set ::env(eco_tmpfiles) {/home/egor/proj/gf180/gf180_efuse/openlane/runs/RUN_2022.12.03_13.12.24/tmp/eco}
+set ::env(floorplan_logs) {/home/egor/proj/gf180/gf180_efuse/openlane/runs/RUN_2022.12.03_13.12.24/logs/floorplan}
+set ::env(floorplan_reports) {/home/egor/proj/gf180/gf180_efuse/openlane/runs/RUN_2022.12.03_13.12.24/reports/floorplan}
+set ::env(floorplan_results) {/home/egor/proj/gf180/gf180_efuse/openlane/runs/RUN_2022.12.03_13.12.24/results/floorplan}
+set ::env(floorplan_tmpfiles) {/home/egor/proj/gf180/gf180_efuse/openlane/runs/RUN_2022.12.03_13.12.24/tmp/floorplan}
+set ::env(placement_logs) {/home/egor/proj/gf180/gf180_efuse/openlane/runs/RUN_2022.12.03_13.12.24/logs/placement}
+set ::env(placement_reports) {/home/egor/proj/gf180/gf180_efuse/openlane/runs/RUN_2022.12.03_13.12.24/reports/placement}
+set ::env(placement_results) {/home/egor/proj/gf180/gf180_efuse/openlane/runs/RUN_2022.12.03_13.12.24/results/placement}
+set ::env(placement_tmpfiles) {/home/egor/proj/gf180/gf180_efuse/openlane/runs/RUN_2022.12.03_13.12.24/tmp/placement}
+set ::env(routing_logs) {/home/egor/proj/gf180/gf180_efuse/openlane/runs/RUN_2022.12.03_13.12.24/logs/routing}
+set ::env(routing_reports) {/home/egor/proj/gf180/gf180_efuse/openlane/runs/RUN_2022.12.03_13.12.24/reports/routing}
+set ::env(routing_results) {/home/egor/proj/gf180/gf180_efuse/openlane/runs/RUN_2022.12.03_13.12.24/results/routing}
+set ::env(routing_tmpfiles) {/home/egor/proj/gf180/gf180_efuse/openlane/runs/RUN_2022.12.03_13.12.24/tmp/routing}
+set ::env(signoff_logs) {/home/egor/proj/gf180/gf180_efuse/openlane/runs/RUN_2022.12.03_13.12.24/logs/signoff}
+set ::env(signoff_reports) {/home/egor/proj/gf180/gf180_efuse/openlane/runs/RUN_2022.12.03_13.12.24/reports/signoff}
+set ::env(signoff_results) {/home/egor/proj/gf180/gf180_efuse/openlane/runs/RUN_2022.12.03_13.12.24/results/signoff}
+set ::env(signoff_tmpfiles) {/home/egor/proj/gf180/gf180_efuse/openlane/runs/RUN_2022.12.03_13.12.24/tmp/signoff}
+set ::env(synthesis_logs) {/home/egor/proj/gf180/gf180_efuse/openlane/runs/RUN_2022.12.03_13.12.24/logs/synthesis}
+set ::env(synthesis_reports) {/home/egor/proj/gf180/gf180_efuse/openlane/runs/RUN_2022.12.03_13.12.24/reports/synthesis}
+set ::env(synthesis_results) {/home/egor/proj/gf180/gf180_efuse/openlane/runs/RUN_2022.12.03_13.12.24/results/synthesis}
+set ::env(synthesis_tmpfiles) {/home/egor/proj/gf180/gf180_efuse/openlane/runs/RUN_2022.12.03_13.12.24/tmp/synthesis}
+set ::env(SYNTH_MAX_TRAN) {2.0}
+set ::env(CURRENT_INDEX) 29
+set ::env(CURRENT_DEF) /home/egor/proj/gf180/gf180_efuse/openlane/runs/RUN_2022.12.03_13.12.24/results/routing/efuse_ctrl.def
+set ::env(CURRENT_GUIDE) /home/egor/proj/gf180/gf180_efuse/openlane/runs/RUN_2022.12.03_13.12.24/tmp/routing/18-global.guide
+set ::env(CURRENT_NETLIST) /home/egor/proj/gf180/gf180_efuse/openlane/runs/RUN_2022.12.03_13.12.24/tmp/signoff/26-efuse_ctrl.nl.v
+set ::env(CURRENT_POWERED_NETLIST) {0}
+set ::env(CURRENT_ODB) /home/egor/proj/gf180/gf180_efuse/openlane/runs/RUN_2022.12.03_13.12.24/results/routing/efuse_ctrl.odb
+set ::env(PDK_ROOT) {/home/egor/.volare}
+set ::env(BASE_SDC_FILE) {/opt/openeda/OpenLane/scripts/base.sdc}
+set ::env(BASIC_PREP_COMPLETE) {1}
+set ::env(BOTTOM_MARGIN_MULT) {4}
+set ::env(CARRY_SELECT_ADDER_MAP) {/home/egor/.volare/gf180mcuC/libs.tech/openlane/gf180mcu_fd_sc_mcu7t5v0/csa_map.v}
+set ::env(CELLS_LEF) {/home/egor/.volare/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/lef/gf180mcu_fd_sc_mcu7t5v0.lef}
+set ::env(CELL_PAD_EXCLUDE) {gf180mcu_fd_sc_mcu7t5v0__filltie_* gf180mcu_fd_sc_mcu7t5v0__filldecap_* gf180mcu_fd_sc_mcu7t5v0__fill_* gf180mcu_fd_sc_mcu7t5v0__endcap_*}
+set ::env(CHECK_ASSIGN_STATEMENTS) {0}
+set ::env(CHECK_UNMAPPED_CELLS) {1}
+set ::env(CLOCK_BUFFER_FANOUT) {16}
+set ::env(CLOCK_NET) {wb_clk_i}
+set ::env(CLOCK_PERIOD) {20}
+set ::env(CLOCK_PORT) {wb_clk_i}
+set ::env(CLOCK_TREE_SYNTH) {1}
+set ::env(CLOCK_WIRE_RC_LAYER) {Metal4}
+set ::env(COLORTERM) {truecolor}
+set ::env(CONFIGS) {general.tcl checkers.tcl synthesis.tcl floorplan.tcl cts.tcl placement.tcl routing.tcl extraction.tcl}
+set ::env(CORE_AREA) {6.72 15.68 2167.76 2332.4}
+set ::env(CORE_HEIGHT) {2316.72}
+set ::env(CORE_WIDTH) {2161.04}
+set ::env(CTS_CLK_BUFFER_LIST) {gf180mcu_fd_sc_mcu7t5v0__clkbuf_2 gf180mcu_fd_sc_mcu7t5v0__clkbuf_4 gf180mcu_fd_sc_mcu7t5v0__clkbuf_8}
+set ::env(CTS_CLK_MAX_WIRE_LENGTH) {0}
+set ::env(CTS_CURRENT_DEF) {/home/egor/proj/gf180/gf180_efuse/openlane/runs/RUN_2022.12.03_13.12.24/results/placement/efuse_ctrl.def}
+set ::env(CTS_DISABLE_POST_PROCESSING) {0}
+set ::env(CTS_DISTANCE_BETWEEN_BUFFERS) {0}
+set ::env(CTS_MAX_CAP) {0.5}
+set ::env(CTS_REPORT_TIMING) {1}
+set ::env(CTS_ROOT_BUFFER) {gf180mcu_fd_sc_mcu7t5v0__clkbuf_16}
+set ::env(CTS_SINK_CLUSTERING_MAX_DIAMETER) {50}
+set ::env(CTS_SINK_CLUSTERING_SIZE) {25}
+set ::env(CTS_TARGET_SKEW) {200}
+set ::env(CTS_TOLERANCE) {100}
+set ::env(CURRENT_DEF) {/home/egor/proj/gf180/gf180_efuse/openlane/runs/RUN_2022.12.03_13.12.24/tmp/signoff/26-efuse_ctrl.p.def}
+set ::env(CURRENT_DIR) {/home/egor/proj/gf180/gf180_efuse/openlane/runs/RUN_2022.12.03_13.12.24/tmp/routing}
+set ::env(CURRENT_GDS) {/home/egor/proj/gf180/gf180_efuse/openlane/runs/RUN_2022.12.03_13.12.24/results/signoff/efuse_ctrl.gds}
+set ::env(CURRENT_GUIDE) {/home/egor/proj/gf180/gf180_efuse/openlane/runs/RUN_2022.12.03_13.12.24/tmp/routing/18-global.guide}
+set ::env(CURRENT_INDEX) {29}
+set ::env(CURRENT_LIB) {/home/egor/proj/gf180/gf180_efuse/openlane/runs/RUN_2022.12.03_13.12.24/results/routing/mca/process_corner_nom/efuse_ctrl.lib}
+set ::env(CURRENT_NETLIST) {/home/egor/proj/gf180/gf180_efuse/openlane/runs/RUN_2022.12.03_13.12.24/tmp/signoff/26-efuse_ctrl.nl.v}
+set ::env(CURRENT_ODB) {/home/egor/proj/gf180/gf180_efuse/openlane/runs/RUN_2022.12.03_13.12.24/results/routing/efuse_ctrl.odb}
+set ::env(CURRENT_POWERED_NETLIST) {/home/egor/proj/gf180/gf180_efuse/openlane/runs/RUN_2022.12.03_13.12.24/tmp/signoff/26-efuse_ctrl.pnl.v}
+set ::env(CURRENT_SDC) {/home/egor/proj/gf180/gf180_efuse/openlane/runs/RUN_2022.12.03_13.12.24/tmp/13-efuse_ctrl.sdc}
+set ::env(CURRENT_SDF) {/home/egor/proj/gf180/gf180_efuse/openlane/runs/RUN_2022.12.03_13.12.24/results/routing/mca/process_corner_nom/efuse_ctrl.sdf}
+set ::env(CURRENT_SPEF) {/home/egor/proj/gf180/gf180_efuse/openlane/runs/RUN_2022.12.03_13.12.24/results/routing/mca/process_corner_nom/efuse_ctrl.spef}
+set ::env(CURRENT_STEP) {lvs}
+set ::env(DATA_WIRE_RC_LAYER) {Metal2}
+set ::env(DBUS_SESSION_BUS_ADDRESS) {unix:path=/run/user/1000/bus}
+set ::env(DECAP_CELL) {gf180mcu_fd_sc_mcu7t5v0__fillcap_*}
+set ::env(DEFAULT_MAX_TRAN) {3}
+set ::env(DEF_UNITS_PER_MICRON) {2000}
+set ::env(DESIGN_CONFIG) {/home/egor/proj/gf180/gf180_efuse/openlane/config.json}
+set ::env(DESIGN_DIR) {/home/egor/proj/gf180/gf180_efuse/openlane}
+set ::env(DESIGN_IS_CORE) {0}
+set ::env(DESIGN_NAME) {efuse_ctrl}
+set ::env(DESKTOP_SESSION) {gnome}
+set ::env(DETAILED_ROUTER) {tritonroute}
+set ::env(DIE_AREA) {0.0 0.0 2175.0 2350.0}
+set ::env(DIODE_CELL) {gf180mcu_fd_sc_mcu7t5v0__antenna}
+set ::env(DIODE_CELL_PIN) {I}
+set ::env(DIODE_INSERTION_CURRENT_DEF) {/home/egor/proj/gf180/gf180_efuse/openlane/runs/RUN_2022.12.03_13.12.24/results/routing/efuse_ctrl.def}
+set ::env(DIODE_INSERTION_STRATEGY) {4}
+set ::env(DIODE_PADDING) {2}
+set ::env(DISPLAY) {:0}
+set ::env(DONT_USE_CELLS) {gf180mcu_fd_sc_mcu7t5v0__mux2_1 gf180mcu_fd_sc_mcu7t5v0__oai33_2 }
+set ::env(DPL_CELL_PADDING) {2}
+set ::env(DRC_EXCLUDE_CELL_LIST) {/home/egor/.volare/gf180mcuC/libs.tech/openlane/gf180mcu_fd_sc_mcu7t5v0/drc_exclude.cells}
+set ::env(DRC_EXCLUDE_CELL_LIST_OPT) {/home/egor/.volare/gf180mcuC/libs.tech/openlane/gf180mcu_fd_sc_mcu7t5v0/drc_exclude.cells}
+set ::env(DRT_MIN_LAYER) {Metal1}
+set ::env(DRT_OPT_ITERS) {64}
+set ::env(ECO_ENABLE) {0}
+set ::env(ECO_FINISH) {0}
+set ::env(ECO_ITER) {0}
+set ::env(ECO_SKIP_PIN) {1}
+set ::env(EXTRA_GDS_FILES) {/home/egor/proj/gf180/gf180_efuse/macros/efuse_array.gds}
+set ::env(EXTRA_LEFS) {/home/egor/proj/gf180/gf180_efuse/macros/efuse_array.lef}
+set ::env(EXT_NETLIST) {/home/egor/proj/gf180/gf180_efuse/openlane/runs/RUN_2022.12.03_13.12.24/results/signoff/efuse_ctrl.spice}
+set ::env(FILL_CELL) {gf180mcu_fd_sc_mcu7t5v0__fill_*}
+set ::env(FLOW_FAILED) {1}
+set ::env(FP_ASPECT_RATIO) {1}
+set ::env(FP_CORE_UTIL) {50}
+set ::env(FP_ENDCAP_CELL) {gf180mcu_fd_sc_mcu7t5v0__endcap}
+set ::env(FP_IO_HEXTEND) {-1}
+set ::env(FP_IO_HLAYER) {Metal3}
+set ::env(FP_IO_HLENGTH) {4}
+set ::env(FP_IO_HTHICKNESS_MULT) {2}
+set ::env(FP_IO_MIN_DISTANCE) {3}
+set ::env(FP_IO_MODE) {1}
+set ::env(FP_IO_UNMATCHED_ERROR) {1}
+set ::env(FP_IO_VEXTEND) {-1}
+set ::env(FP_IO_VLAYER) {Metal2}
+set ::env(FP_IO_VLENGTH) {4}
+set ::env(FP_IO_VTHICKNESS_MULT) {2}
+set ::env(FP_PDN_AUTO_ADJUST) {0}
+set ::env(FP_PDN_CHECK_NODES) {1}
+set ::env(FP_PDN_CORE_RING) {0}
+set ::env(FP_PDN_CORE_RING_HOFFSET) {6}
+set ::env(FP_PDN_CORE_RING_HSPACING) {1.7}
+set ::env(FP_PDN_CORE_RING_HWIDTH) {1.6}
+set ::env(FP_PDN_CORE_RING_VOFFSET) {6}
+set ::env(FP_PDN_CORE_RING_VSPACING) {1.7}
+set ::env(FP_PDN_CORE_RING_VWIDTH) {1.6}
+set ::env(FP_PDN_ENABLE_GLOBAL_CONNECTIONS) {1}
+set ::env(FP_PDN_ENABLE_MACROS_GRID) {1}
+set ::env(FP_PDN_ENABLE_RAILS) {1}
+set ::env(FP_PDN_HOFFSET) {16.65}
+set ::env(FP_PDN_HORIZONTAL_HALO) {3}
+set ::env(FP_PDN_HPITCH) {153.18}
+set ::env(FP_PDN_HSPACING) {1.7}
+set ::env(FP_PDN_HWIDTH) {1.6}
+set ::env(FP_PDN_IRDROP) {1}
+set ::env(FP_PDN_LOWER_LAYER) {Metal4}
+set ::env(FP_PDN_RAILS_LAYER) {Metal1}
+set ::env(FP_PDN_RAIL_OFFSET) {0}
+set ::env(FP_PDN_RAIL_WIDTH) {0.6}
+set ::env(FP_PDN_SKIPTRIM) {0}
+set ::env(FP_PDN_UPPER_LAYER) {Metal5}
+set ::env(FP_PDN_VERTICAL_HALO) {10}
+set ::env(FP_PDN_VOFFSET) {20}
+set ::env(FP_PDN_VPITCH) {190}
+set ::env(FP_PDN_VSPACING) {8}
+set ::env(FP_PDN_VWIDTH) {1.6}
+set ::env(FP_SIZING) {absolute}
+set ::env(FP_TAPCELL_DIST) {20}
+set ::env(FP_TAP_HORIZONTAL_HALO) {3}
+set ::env(FP_TAP_VERTICAL_HALO) {10}
+set ::env(FP_WELLTAP_CELL) {gf180mcu_fd_sc_mcu7t5v0__filltie}
+set ::env(FULL_ADDER_MAP) {/home/egor/.volare/gf180mcuC/libs.tech/openlane/gf180mcu_fd_sc_mcu7t5v0/fa_map.v}
+set ::env(GDMSESSION) {gnome}
+set ::env(GDM_LANG) {ru_RU.UTF-8}
+set ::env(GDS_FILES) {/home/egor/.volare/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/gds/gf180mcu_fd_sc_mcu7t5v0.gds}
+set ::env(GENERATE_FINAL_SUMMARY_REPORT) {1}
+set ::env(GLB_CFG_FILE) {/home/egor/proj/gf180/gf180_efuse/openlane/runs/RUN_2022.12.03_13.12.24/config.tcl}
+set ::env(GLB_OPTIMIZE_MIRRORING) {1}
+set ::env(GLB_RESIZER_ALLOW_SETUP_VIOS) {0}
+set ::env(GLB_RESIZER_HOLD_MAX_BUFFER_PERCENT) {50}
+set ::env(GLB_RESIZER_HOLD_SLACK_MARGIN) {0.05}
+set ::env(GLB_RESIZER_MAX_CAP_MARGIN) {10}
+set ::env(GLB_RESIZER_MAX_SLEW_MARGIN) {10}
+set ::env(GLB_RESIZER_MAX_WIRE_LENGTH) {0}
+set ::env(GLB_RESIZER_SETUP_MAX_BUFFER_PERCENT) {50}
+set ::env(GLB_RESIZER_SETUP_SLACK_MARGIN) {0.025}
+set ::env(GLB_RESIZER_TIMING_OPTIMIZATIONS) {1}
+set ::env(GLOBAL_ROUTER) {fastroute}
+set ::env(GND_NET) {VSS}
+set ::env(GND_NETS) {VSS}
+set ::env(GND_PIN) {VSS}
+set ::env(GNOME_DESKTOP_SESSION_ID) {this-is-deprecated}
+set ::env(GNOME_SETUP_DISPLAY) {:1}
+set ::env(GNOME_TERMINAL_SCREEN) {/org/gnome/Terminal/screen/417f9199_5a5c_474b_8e46_3e0718de05f5}
+set ::env(GNOME_TERMINAL_SERVICE) {:1.131}
+set ::env(GPIO_PADS_LEF) { /home/egor/.volare/gf180mcuC/libs.ref/gf180mcu_io/lef/GF018green_ipio_5p0c_75_5lm.lef
+}
+set ::env(GPIO_PADS_VERILOG) { /home/egor/.volare/gf180mcuC/libs.ref/gf180mcu_io/verilog/GF018green_ipio_5p0c_75_5lm.v
+}
+set ::env(GPL_CELL_PADDING) {0}
+set ::env(GRT_ADJUSTMENT) {0.3}
+set ::env(GRT_ALLOW_CONGESTION) {1}
+set ::env(GRT_ANT_ITERS) {3}
+set ::env(GRT_ESTIMATE_PARASITICS) {1}
+set ::env(GRT_LAYER_ADJUSTMENTS) {0,0,0,0,0}
+set ::env(GRT_MACRO_EXTENSION) {0}
+set ::env(GRT_MAX_DIODE_INS_ITERS) {1}
+set ::env(GRT_OBS) {Metal5 0 30.5 2175 53.5, Metal5 0 75.5 2175 98.5, Metal5 0 120.5 2175 143.5, Metal5 0 165.5 2175 188.5, Metal5 0 210.5 2175 233.5, Metal5 0 255.5 2175 278.5, Metal5 0 300.5 2175 323.5, Metal5 0 345.5 2175 368.5, Metal5 0 390.5 2175 413.5, Metal5 0 435.5 2175 458.5, Metal5 0 480.5 2175 503.5, Metal5 0 525.5 2175 548.5, Metal5 0 570.5 2175 593.5, Metal5 0 615.5 2175 638.5, Metal5 0 660.5 2175 683.5, Metal5 0 705.5 2175 728.5, Metal5 0 750.5 2175 773.5, Metal5 0 795.5 2175 818.5, Metal5 0 840.5 2175 863.5, Metal5 0 885.5 2175 908.5, Metal5 0 930.5 2175 953.5, Metal5 0 975.5 2175 998.5, Metal5 0 1020.5 2175 1043.5, Metal5 0 1065.5 2175 1088.5, Metal5 0 1110.5 2175 1133.5, Metal5 0 1155.5 2175 1178.5, Metal5 0 1200.5 2175 1223.5, Metal5 0 1245.5 2175 1268.5, Metal5 0 1290.5 2175 1313.5, Metal5 0 1335.5 2175 1358.5, Metal5 0 1380.5 2175 1403.5, Metal5 0 1425.5 2175 1448.5, Metal5 0 1470.5 2175 1493.5, Metal5 0 1515.5 2175 1538.5, Metal5 0 1560.5 2175 1583.5, Metal5 0 1605.5 2175 1628.5, Metal5 0 1650.5 2175 1673.5, Metal5 0 1695.5 2175 1718.5, Metal5 0 1740.5 2175 1763.5, Metal5 0 1785.5 2175 1808.5, Metal5 0 1830.5 2175 1853.5, Metal5 0 1875.5 2175 1898.5, Metal5 0 1920.5 2175 1943.5, Metal5 0 1965.5 2175 1988.5, Metal5 0 2010.5 2175 2033.5, Metal5 0 2055.5 2175 2078.5, Metal5 0 2100.5 2175 2123.5, Metal5 0 2145.5 2175 2168.5, Metal5 0 2190.5 2175 2213.5, Metal5 0 2235.5 2175 2258.5, Metal5 0 2280.5 2175 2303.5, Metal5 0 2325.5 2175 2348.5}
+set ::env(GRT_OVERFLOW_ITERS) {50}
+set ::env(GTK_MODULES) {gail:atk-bridge}
+set ::env(HOME) {/home/egor}
+set ::env(IO_PCT) {0.2}
+set ::env(KLAYOUT_DRC_KLAYOUT_GDS) {0}
+set ::env(KLAYOUT_DRC_TECH_SCRIPT) {/home/egor/.volare/gf180mcuC/libs.tech/klayout/gf180mcuC_mr.drc}
+set ::env(KLAYOUT_PROPERTIES) {/home/egor/.volare/gf180mcuC/libs.tech/klayout/gf180mcuC.lyp}
+set ::env(KLAYOUT_TECH) {/home/egor/.volare/gf180mcuC/libs.tech/klayout/gf180mcuC.lyt}
+set ::env(KLAYOUT_XOR_GDS) {1}
+set ::env(KLAYOUT_XOR_XML) {1}
+set ::env(LANG) {ru_RU.UTF-8}
+set ::env(LANGUAGE) {ru_RU:ru}
+set ::env(LAST_TIMING_REPORT_TAG) {/home/egor/proj/gf180/gf180_efuse/openlane/runs/RUN_2022.12.03_13.12.24/reports/signoff/24-rcx_sta}
+set ::env(LEC_ENABLE) {0}
+set ::env(LEFT_MARGIN_MULT) {12}
+set ::env(LIB_CTS) {/home/egor/proj/gf180/gf180_efuse/openlane/runs/RUN_2022.12.03_13.12.24/tmp/cts/cts.lib}
+set ::env(LIB_FASTEST) {/home/egor/.volare/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/liberty/gf180mcu_fd_sc_mcu7t5v0__ff_n40C_5v50.lib}
+set ::env(LIB_SLOWEST) {/home/egor/.volare/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/liberty/gf180mcu_fd_sc_mcu7t5v0__ss_125C_4v50.lib}
+set ::env(LIB_SYNTH) {/home/egor/proj/gf180/gf180_efuse/openlane/runs/RUN_2022.12.03_13.12.24/tmp/synthesis/trimmed.lib}
+set ::env(LIB_SYNTH_COMPLETE) {/home/egor/.volare/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/liberty/gf180mcu_fd_sc_mcu7t5v0__tt_025C_5v00.lib}
+set ::env(LIB_SYNTH_COMPLETE_NO_PG) {/home/egor/proj/gf180/gf180_efuse/openlane/runs/RUN_2022.12.03_13.12.24/tmp/synthesis/1-gf180mcu_fd_sc_mcu7t5v0__tt_025C_5v00.no_pg.lib}
+set ::env(LIB_SYNTH_MERGED) {/home/egor/proj/gf180/gf180_efuse/openlane/runs/RUN_2022.12.03_13.12.24/tmp/synthesis/merged.lib}
+set ::env(LIB_SYNTH_NO_PG) {/home/egor/proj/gf180/gf180_efuse/openlane/runs/RUN_2022.12.03_13.12.24/tmp/synthesis/1-trimmed.no_pg.lib}
+set ::env(LIB_TYPICAL) {/home/egor/.volare/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/liberty/gf180mcu_fd_sc_mcu7t5v0__tt_025C_5v00.lib}
+set ::env(LOGNAME) {egor}
+set ::env(LOGS_DIR) {/home/egor/proj/gf180/gf180_efuse/openlane/runs/RUN_2022.12.03_13.12.24/logs}
+set ::env(LS_COLORS) {rs=0:di=01;34:ln=01;36:mh=00:pi=40;33:so=01;35:do=01;35:bd=40;33;01:cd=40;33;01:or=40;31;01:mi=00:su=37;41:sg=30;43:ca=30;41:tw=30;42:ow=34;42:st=37;44:ex=01;32:*.tar=01;31:*.tgz=01;31:*.arc=01;31:*.arj=01;31:*.taz=01;31:*.lha=01;31:*.lz4=01;31:*.lzh=01;31:*.lzma=01;31:*.tlz=01;31:*.txz=01;31:*.tzo=01;31:*.t7z=01;31:*.zip=01;31:*.z=01;31:*.dz=01;31:*.gz=01;31:*.lrz=01;31:*.lz=01;31:*.lzo=01;31:*.xz=01;31:*.zst=01;31:*.tzst=01;31:*.bz2=01;31:*.bz=01;31:*.tbz=01;31:*.tbz2=01;31:*.tz=01;31:*.deb=01;31:*.rpm=01;31:*.jar=01;31:*.war=01;31:*.ear=01;31:*.sar=01;31:*.rar=01;31:*.alz=01;31:*.ace=01;31:*.zoo=01;31:*.cpio=01;31:*.7z=01;31:*.rz=01;31:*.cab=01;31:*.wim=01;31:*.swm=01;31:*.dwm=01;31:*.esd=01;31:*.jpg=01;35:*.jpeg=01;35:*.mjpg=01;35:*.mjpeg=01;35:*.gif=01;35:*.bmp=01;35:*.pbm=01;35:*.pgm=01;35:*.ppm=01;35:*.tga=01;35:*.xbm=01;35:*.xpm=01;35:*.tif=01;35:*.tiff=01;35:*.png=01;35:*.svg=01;35:*.svgz=01;35:*.mng=01;35:*.pcx=01;35:*.mov=01;35:*.mpg=01;35:*.mpeg=01;35:*.m2v=01;35:*.mkv=01;35:*.webm=01;35:*.webp=01;35:*.ogm=01;35:*.mp4=01;35:*.m4v=01;35:*.mp4v=01;35:*.vob=01;35:*.qt=01;35:*.nuv=01;35:*.wmv=01;35:*.asf=01;35:*.rm=01;35:*.rmvb=01;35:*.flc=01;35:*.avi=01;35:*.fli=01;35:*.flv=01;35:*.gl=01;35:*.dl=01;35:*.xcf=01;35:*.xwd=01;35:*.yuv=01;35:*.cgm=01;35:*.emf=01;35:*.ogv=01;35:*.ogx=01;35:*.aac=00;36:*.au=00;36:*.flac=00;36:*.m4a=00;36:*.mid=00;36:*.midi=00;36:*.mka=00;36:*.mp3=00;36:*.mpc=00;36:*.ogg=00;36:*.ra=00;36:*.wav=00;36:*.oga=00;36:*.opus=00;36:*.spx=00;36:*.xspf=00;36:}
+set ::env(LVS_CONNECT_BY_LABEL) {1}
+set ::env(LVS_CURRENT_DEF) {/home/egor/proj/gf180/gf180_efuse/openlane/runs/RUN_2022.12.03_13.12.24/results/routing/efuse_ctrl.def}
+set ::env(LVS_INSERT_POWER_PINS) {1}
+set ::env(MACRO_BLOCKAGES_LAYER) {Metal1 Metal2 Metal3 Metal4 Metal5}
+set ::env(MACRO_PLACEMENT_CFG) {macro_placement.cfg}
+set ::env(MAGIC_CONVERT_DRC_TO_RDB) {1}
+set ::env(MAGIC_DEF_LABELS) {1}
+set ::env(MAGIC_DEF_NO_BLOCKAGES) {1}
+set ::env(MAGIC_DISABLE_HIER_GDS) {1}
+set ::env(MAGIC_DRC_USE_GDS) {1}
+set ::env(MAGIC_EXT_USE_GDS) {0}
+set ::env(MAGIC_GDS) {/home/egor/proj/gf180/gf180_efuse/openlane/runs/RUN_2022.12.03_13.12.24/results/signoff/efuse_ctrl.magic.gds}
+set ::env(MAGIC_GENERATE_GDS) {1}
+set ::env(MAGIC_GENERATE_LEF) {1}
+set ::env(MAGIC_GENERATE_MAGLEF) {1}
+set ::env(MAGIC_INCLUDE_GDS_POINTERS) {0}
+set ::env(MAGIC_MAGICRC) {/home/egor/.volare/gf180mcuC/libs.tech/magic/gf180mcuC.magicrc}
+set ::env(MAGIC_PAD) {0}
+set ::env(MAGIC_TECH_FILE) {/home/egor/.volare/gf180mcuC/libs.tech/magic/gf180mcuC.tech}
+set ::env(MAGIC_WRITE_FULL_LEF) {0}
+set ::env(MAGIC_ZEROIZE_ORIGIN) {0}
+set ::env(MAGTYPE) {maglef}
+set ::env(MAX_METAL_LAYER) {5}
+set ::env(MC_SDF_DIR) {/home/egor/proj/gf180/gf180_efuse/openlane/runs/RUN_2022.12.03_13.12.24/results/routing/mca/sdf}
+set ::env(MC_SPEF_DIR) {/home/egor/proj/gf180/gf180_efuse/openlane/runs/RUN_2022.12.03_13.12.24/results/routing/mca/spef}
+set ::env(MERGED_LEF) {/home/egor/proj/gf180/gf180_efuse/openlane/runs/RUN_2022.12.03_13.12.24/tmp/merged.nom.lef}
+set ::env(METAL_LAYER_NAMES) {Metal1 Metal2 Metal3 Metal4 Metal5}
+set ::env(NETGEN_SETUP_FILE) {/home/egor/.volare/gf180mcuC/libs.tech/netgen/gf180mcuC_setup.tcl}
+set ::env(NO_SYNTH_CELL_LIST) {/home/egor/.volare/gf180mcuC/libs.tech/openlane/gf180mcu_fd_sc_mcu7t5v0/no_synth.cells}
+set ::env(OL_INSTALL_DIR) {/opt/openeda/OpenLane/install}
+set ::env(OPENLANE) {/opt/openeda/OpenLane/flow.tcl}
+set ::env(OPENLANE_LOCAL_INSTALL) {1}
+set ::env(OPENLANE_ROOT) {/opt/openeda/OpenLane}
+set ::env(OPENLANE_VERBOSE) {0}
+set ::env(OPENLANE_VERSION) {5035e1e6e2a58783683b6ca5b4e010f76394a3be}
+set ::env(OPENROAD_BIN) {openroad}
+set ::env(PARSITICS_CURRENT_DEF) {/home/egor/proj/gf180/gf180_efuse/openlane/runs/RUN_2022.12.03_13.12.24/results/routing/efuse_ctrl.def}
+set ::env(PATH) {/opt/openeda/OpenLane/install/bin:/opt/openeda/OpenLane/install/venv/bin:/opt/openeda/bin/:/opt/openeda/OpenLane/install/bin/:/usr/local/bin:/usr/bin:/bin:/usr/games}
+set ::env(PDK) {gf180mcuC}
+set ::env(PDKPATH) {/home/egor/.volare/gf180mcuC}
+set ::env(PDK_ROOT) {/home/egor/.volare}
+set ::env(PDN_CFG) {/home/egor/proj/gf180/gf180_efuse/openlane/pdn_cfg.tcl}
+set ::env(PLACEMENT_CURRENT_DEF) {/home/egor/proj/gf180/gf180_efuse/openlane/runs/RUN_2022.12.03_13.12.24/tmp/floorplan/7-pdn.def}
+set ::env(PLACE_SITE) {GF018hv5v_mcu_sc7}
+set ::env(PLACE_SITE_HEIGHT) {3.92}
+set ::env(PLACE_SITE_WIDTH) {0.56}
+set ::env(PL_BASIC_PLACEMENT) {0}
+set ::env(PL_ESTIMATE_PARASITICS) {1}
+set ::env(PL_INIT_COEFF) {0.00002}
+set ::env(PL_IO_ITER) {5}
+set ::env(PL_LIB) {/home/egor/.volare/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/liberty/gf180mcu_fd_sc_mcu7t5v0__tt_025C_5v00.lib}
+set ::env(PL_MACRO_CHANNEL) {0 0}
+set ::env(PL_MACRO_HALO) {100 100}
+set ::env(PL_MAX_DISPLACEMENT_X) {2000}
+set ::env(PL_MAX_DISPLACEMENT_Y) {2000}
+set ::env(PL_OPTIMIZE_MIRRORING) {1}
+set ::env(PL_RANDOM_GLB_PLACEMENT) {0}
+set ::env(PL_RANDOM_INITIAL_PLACEMENT) {0}
+set ::env(PL_RESIZER_ALLOW_SETUP_VIOS) {0}
+set ::env(PL_RESIZER_BUFFER_INPUT_PORTS) {1}
+set ::env(PL_RESIZER_BUFFER_OUTPUT_PORTS) {1}
+set ::env(PL_RESIZER_DESIGN_OPTIMIZATIONS) {1}
+set ::env(PL_RESIZER_HOLD_MAX_BUFFER_PERCENT) {50}
+set ::env(PL_RESIZER_HOLD_SLACK_MARGIN) {0.1}
+set ::env(PL_RESIZER_MAX_CAP_MARGIN) {20}
+set ::env(PL_RESIZER_MAX_SLEW_MARGIN) {20}
+set ::env(PL_RESIZER_MAX_WIRE_LENGTH) {0}
+set ::env(PL_RESIZER_REPAIR_TIE_FANOUT) {1}
+set ::env(PL_RESIZER_SETUP_MAX_BUFFER_PERCENT) {50}
+set ::env(PL_RESIZER_SETUP_SLACK_MARGIN) {0.05}
+set ::env(PL_RESIZER_TIE_SEPERATION) {0}
+set ::env(PL_RESIZER_TIMING_OPTIMIZATIONS) {1}
+set ::env(PL_ROUTABILITY_DRIVEN) {1}
+set ::env(PL_SKIP_INITIAL_PLACEMENT) {0}
+set ::env(PL_TARGET_DENSITY) {0.75}
+set ::env(PL_TIME_DRIVEN) {1}
+set ::env(PRIMARY_SIGNOFF_TOOL) {magic}
+set ::env(PROCESS) {180}
+set ::env(PWD) {/home/egor/proj/gf180/gf180_efuse/openlane}
+set ::env(QT_ACCESSIBILITY) {1}
+set ::env(QT_IM_MODULE) {ibus}
+set ::env(QUIT_ON_HOLD_VIOLATIONS) {1}
+set ::env(QUIT_ON_ILLEGAL_OVERLAPS) {1}
+set ::env(QUIT_ON_LONG_WIRE) {0}
+set ::env(QUIT_ON_LVS_ERROR) {1}
+set ::env(QUIT_ON_MAGIC_DRC) {1}
+set ::env(QUIT_ON_SETUP_VIOLATIONS) {1}
+set ::env(QUIT_ON_TIMING_VIOLATIONS) {1}
+set ::env(QUIT_ON_TR_DRC) {1}
+set ::env(RCX_CC_MODEL) {10}
+set ::env(RCX_CONTEXT_DEPTH) {5}
+set ::env(RCX_CORNER_COUNT) {1}
+set ::env(RCX_COUPLING_THRESHOLD) {0.1}
+set ::env(RCX_MAX_RESISTANCE) {50}
+set ::env(RCX_MERGE_VIA_WIRE_RES) {1}
+set ::env(RCX_RULES) {/home/egor/.volare/gf180mcuC/libs.tech/openlane/rules.openrcx.gf180mcuC.nom}
+set ::env(RCX_RULES_MAX) {/home/egor/.volare/gf180mcuC/libs.tech/openlane/rules.openrcx.gf180mcuC.max}
+set ::env(RCX_RULES_MIN) {/home/egor/.volare/gf180mcuC/libs.tech/openlane/rules.openrcx.gf180mcuC.min}
+set ::env(RCX_SDC_FILE) {/home/egor/proj/gf180/gf180_efuse/openlane/runs/RUN_2022.12.03_13.12.24/tmp/13-efuse_ctrl.sdc}
+set ::env(REPORTS_DIR) {/home/egor/proj/gf180/gf180_efuse/openlane/runs/RUN_2022.12.03_13.12.24/reports}
+set ::env(RESULTS_DIR) {/home/egor/proj/gf180/gf180_efuse/openlane/runs/RUN_2022.12.03_13.12.24/results}
+set ::env(RIGHT_MARGIN_MULT) {12}
+set ::env(RIPPLE_CARRY_ADDER_MAP) {/home/egor/.volare/gf180mcuC/libs.tech/openlane/gf180mcu_fd_sc_mcu7t5v0/rca_map.v}
+set ::env(ROUTING_CORES) {24}
+set ::env(ROUTING_CURRENT_DEF) {/home/egor/proj/gf180/gf180_efuse/openlane/runs/RUN_2022.12.03_13.12.24/tmp/cts/12-efuse_ctrl.resized.def}
+set ::env(RSZ_DONT_TOUCH_RX) {\$^}
+set ::env(RSZ_LIB) {/home/egor/proj/gf180/gf180_efuse/openlane/runs/RUN_2022.12.03_13.12.24/tmp/synthesis/resizer_gf180mcu_fd_sc_mcu7t5v0__tt_025C_5v00.lib}
+set ::env(RSZ_USE_OLD_REMOVER) {0}
+set ::env(RT_MAX_LAYER) {Metal5}
+set ::env(RT_MIN_LAYER) {Metal2}
+set ::env(RUN_CVC) {1}
+set ::env(RUN_DIR) {/home/egor/proj/gf180/gf180_efuse/openlane/runs/RUN_2022.12.03_13.12.24}
+set ::env(RUN_DRT) {1}
+set ::env(RUN_FILL_INSERTION) {1}
+set ::env(RUN_IRDROP_REPORT) {0}
+set ::env(RUN_KLAYOUT) {0}
+set ::env(RUN_KLAYOUT_DRC) {0}
+set ::env(RUN_KLAYOUT_XOR) {0}
+set ::env(RUN_LVS) {1}
+set ::env(RUN_MAGIC) {1}
+set ::env(RUN_MAGIC_DRC) {1}
+set ::env(RUN_SPEF_EXTRACTION) {1}
+set ::env(RUN_STANDALONE) {1}
+set ::env(RUN_TAG) {RUN_2022.12.03_13.12.24}
+set ::env(RUN_TAP_DECAP_INSERTION) {1}
+set ::env(SCLPATH) {/home/egor/.volare/gf180mcuC/gf180mcu_fd_sc_mcu7t5v0}
+set ::env(SCRIPTS_DIR) {/opt/openeda/OpenLane/scripts}
+set ::env(SESSION_MANAGER) {local/duohead:@/tmp/.ICE-unix/1612,unix/duohead:/tmp/.ICE-unix/1612}
+set ::env(SHELL) {/usr/bin/fish}
+set ::env(SHLVL) {2}
+set ::env(SPEF_EXTRACTOR) {openrcx}
+set ::env(SSH_AGENT_LAUNCHER) {openssh}
+set ::env(SSH_AUTH_SOCK) {/run/user/1000/keyring/ssh}
+set ::env(START_TIME) {2022.12.03_13.12.24}
+set ::env(STA_PRE_CTS) {0}
+set ::env(STA_REPORT_POWER) {1}
+set ::env(STA_WRITE_LIB) {1}
+set ::env(STD_CELL_GROUND_PINS) {VSS}
+set ::env(STD_CELL_LIBRARY) {gf180mcu_fd_sc_mcu7t5v0}
+set ::env(STD_CELL_LIBRARY_CDL) {/home/egor/.volare/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/cdl/gf180mcu_fd_sc_mcu7t5v0.cdl}
+set ::env(STD_CELL_LIBRARY_OPT) {gf180mcu_fd_sc_mcu7t5v0}
+set ::env(STD_CELL_POWER_PINS) {VDD}
+set ::env(SYNTH_ADDER_TYPE) {YOSYS}
+set ::env(SYNTH_BIN) {yosys}
+set ::env(SYNTH_BUFFERING) {1}
+set ::env(SYNTH_CAP_LOAD) {72.91}
+set ::env(SYNTH_CLK_DRIVING_CELL) {gf180mcu_fd_sc_mcu7t5v0__inv_4}
+set ::env(SYNTH_CLK_DRIVING_CELL_PIN) {ZN}
+set ::env(SYNTH_CLOCK_TRANSITION) {0.15}
+set ::env(SYNTH_CLOCK_UNCERTAINTY) {0.25}
+set ::env(SYNTH_DRIVING_CELL) {gf180mcu_fd_sc_mcu7t5v0__inv_1}
+set ::env(SYNTH_DRIVING_CELL_PIN) {ZN}
+set ::env(SYNTH_ELABORATE_ONLY) {0}
+set ::env(SYNTH_EXTRA_MAPPING_FILE) {}
+set ::env(SYNTH_FLAT_TOP) {0}
+set ::env(SYNTH_LATCH_MAP) {/home/egor/.volare/gf180mcuC/libs.tech/openlane/gf180mcu_fd_sc_mcu7t5v0/latch_map.v}
+set ::env(SYNTH_MAX_FANOUT) {10}
+set ::env(SYNTH_MAX_TRAN) {2.0}
+set ::env(SYNTH_MIN_BUF_PORT) {gf180mcu_fd_sc_mcu7t5v0__buf_1 I Z}
+set ::env(SYNTH_NO_FLAT) {0}
+set ::env(SYNTH_OPT) {0}
+set ::env(SYNTH_READ_BLACKBOX_LIB) {0}
+set ::env(SYNTH_SCRIPT) {/opt/openeda/OpenLane/scripts/yosys/synth.tcl}
+set ::env(SYNTH_SHARE_RESOURCES) {1}
+set ::env(SYNTH_SIZING) {0}
+set ::env(SYNTH_STRATEGY) {AREA 3}
+set ::env(SYNTH_TIEHI_PORT) {gf180mcu_fd_sc_mcu7t5v0__tieh Z}
+set ::env(SYNTH_TIELO_PORT) {gf180mcu_fd_sc_mcu7t5v0__tiel ZN}
+set ::env(SYNTH_TIMING_DERATE) {0.05}
+set ::env(TAKE_LAYOUT_SCROT) {0}
+set ::env(TECH_LEF) {/home/egor/.volare/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/techlef/gf180mcu_fd_sc_mcu7t5v0.tlef}
+set ::env(TECH_METAL_LAYERS) {Metal1 Metal2 Metal3 Metal4 Metal5}
+set ::env(TERM) {xterm-256color}
+set ::env(TERMINAL_OUTPUT) {/dev/null}
+set ::env(TMP_DIR) {/home/egor/proj/gf180/gf180_efuse/openlane/runs/RUN_2022.12.03_13.12.24/tmp}
+set ::env(TOP_MARGIN_MULT) {4}
+set ::env(TRACKS_INFO_FILE) {/home/egor/.volare/gf180mcuC/libs.tech/openlane/gf180mcu_fd_sc_mcu7t5v0/tracks.info}
+set ::env(TRACKS_INFO_FILE_PROCESSED) {/home/egor/proj/gf180/gf180_efuse/openlane/runs/RUN_2022.12.03_13.12.24/tmp/routing/config.tracks}
+set ::env(TRISTATE_BUFFER_MAP) {/home/egor/.volare/gf180mcuC/libs.tech/openlane/gf180mcu_fd_sc_mcu7t5v0/tribuff_map.v}
+set ::env(USER) {egor}
+set ::env(USERNAME) {egor}
+set ::env(USE_ARC_ANTENNA_CHECK) {1}
+set ::env(USE_GPIO_PADS) {0}
+set ::env(VCHECK_OUTPUT) {}
+set ::env(VDD_NET) {VDD}
+set ::env(VDD_NETS) {VDD}
+set ::env(VDD_PIN) {VDD}
+set ::env(VERILOG_FILES) {efuse_ctrl_fromvhdl.v ../macros/cells.v}
+set ::env(VERILOG_FILES_BLACKBOX) {/home/egor/proj/gf180/gf180_efuse/macros/efuse_array.v}
+set ::env(VIRTUAL_ENV) {/opt/openeda/OpenLane/install/venv}
+set ::env(VTE_VERSION) {6203}
+set ::env(WAYLAND_DISPLAY) {wayland-0}
+set ::env(WIRE_RC_LAYER) {Metal2}
+set ::env(XAUTHORITY) {/run/user/1000/.mutter-Xwaylandauth.2E58V1}
+set ::env(XDG_CURRENT_DESKTOP) {GNOME}
+set ::env(XDG_MENU_PREFIX) {gnome-}
+set ::env(XDG_RUNTIME_DIR) {/run/user/1000}
+set ::env(XDG_SESSION_CLASS) {user}
+set ::env(XDG_SESSION_DESKTOP) {gnome}
+set ::env(XDG_SESSION_TYPE) {wayland}
+set ::env(XMODIFIERS) {@im=ibus}
+set ::env(YOSYS_REWRITE_VERILOG) {0}
+set ::env(cts_logs) {/home/egor/proj/gf180/gf180_efuse/openlane/runs/RUN_2022.12.03_13.12.24/logs/cts}
+set ::env(cts_reports) {/home/egor/proj/gf180/gf180_efuse/openlane/runs/RUN_2022.12.03_13.12.24/reports/cts}
+set ::env(cts_results) {/home/egor/proj/gf180/gf180_efuse/openlane/runs/RUN_2022.12.03_13.12.24/results/cts}
+set ::env(cts_tmpfiles) {/home/egor/proj/gf180/gf180_efuse/openlane/runs/RUN_2022.12.03_13.12.24/tmp/cts}
+set ::env(eco_logs) {/home/egor/proj/gf180/gf180_efuse/openlane/runs/RUN_2022.12.03_13.12.24/logs/eco}
+set ::env(eco_reports) {/home/egor/proj/gf180/gf180_efuse/openlane/runs/RUN_2022.12.03_13.12.24/reports/eco}
+set ::env(eco_results) {/home/egor/proj/gf180/gf180_efuse/openlane/runs/RUN_2022.12.03_13.12.24/results/eco}
+set ::env(eco_tmpfiles) {/home/egor/proj/gf180/gf180_efuse/openlane/runs/RUN_2022.12.03_13.12.24/tmp/eco}
+set ::env(floorplan_logs) {/home/egor/proj/gf180/gf180_efuse/openlane/runs/RUN_2022.12.03_13.12.24/logs/floorplan}
+set ::env(floorplan_reports) {/home/egor/proj/gf180/gf180_efuse/openlane/runs/RUN_2022.12.03_13.12.24/reports/floorplan}
+set ::env(floorplan_results) {/home/egor/proj/gf180/gf180_efuse/openlane/runs/RUN_2022.12.03_13.12.24/results/floorplan}
+set ::env(floorplan_tmpfiles) {/home/egor/proj/gf180/gf180_efuse/openlane/runs/RUN_2022.12.03_13.12.24/tmp/floorplan}
+set ::env(fp_report_prefix) {/home/egor/proj/gf180/gf180_efuse/openlane/runs/RUN_2022.12.03_13.12.24/reports/floorplan/3-initial_fp}
+set ::env(placement_logs) {/home/egor/proj/gf180/gf180_efuse/openlane/runs/RUN_2022.12.03_13.12.24/logs/placement}
+set ::env(placement_reports) {/home/egor/proj/gf180/gf180_efuse/openlane/runs/RUN_2022.12.03_13.12.24/reports/placement}
+set ::env(placement_results) {/home/egor/proj/gf180/gf180_efuse/openlane/runs/RUN_2022.12.03_13.12.24/results/placement}
+set ::env(placement_tmpfiles) {/home/egor/proj/gf180/gf180_efuse/openlane/runs/RUN_2022.12.03_13.12.24/tmp/placement}
+set ::env(routing_logs) {/home/egor/proj/gf180/gf180_efuse/openlane/runs/RUN_2022.12.03_13.12.24/logs/routing}
+set ::env(routing_reports) {/home/egor/proj/gf180/gf180_efuse/openlane/runs/RUN_2022.12.03_13.12.24/reports/routing}
+set ::env(routing_results) {/home/egor/proj/gf180/gf180_efuse/openlane/runs/RUN_2022.12.03_13.12.24/results/routing}
+set ::env(routing_tmpfiles) {/home/egor/proj/gf180/gf180_efuse/openlane/runs/RUN_2022.12.03_13.12.24/tmp/routing}
+set ::env(signoff_logs) {/home/egor/proj/gf180/gf180_efuse/openlane/runs/RUN_2022.12.03_13.12.24/logs/signoff}
+set ::env(signoff_reports) {/home/egor/proj/gf180/gf180_efuse/openlane/runs/RUN_2022.12.03_13.12.24/reports/signoff}
+set ::env(signoff_results) {/home/egor/proj/gf180/gf180_efuse/openlane/runs/RUN_2022.12.03_13.12.24/results/signoff}
+set ::env(signoff_tmpfiles) {/home/egor/proj/gf180/gf180_efuse/openlane/runs/RUN_2022.12.03_13.12.24/tmp/signoff}
+set ::env(synth_report_prefix) {/home/egor/proj/gf180/gf180_efuse/openlane/runs/RUN_2022.12.03_13.12.24/reports/synthesis/1-synthesis}
+set ::env(synthesis_logs) {/home/egor/proj/gf180/gf180_efuse/openlane/runs/RUN_2022.12.03_13.12.24/logs/synthesis}
+set ::env(synthesis_reports) {/home/egor/proj/gf180/gf180_efuse/openlane/runs/RUN_2022.12.03_13.12.24/reports/synthesis}
+set ::env(synthesis_results) {/home/egor/proj/gf180/gf180_efuse/openlane/runs/RUN_2022.12.03_13.12.24/results/synthesis}
+set ::env(synthesis_tmpfiles) {/home/egor/proj/gf180/gf180_efuse/openlane/runs/RUN_2022.12.03_13.12.24/tmp/synthesis}
+set ::env(timer_end) {1670053395}
+set ::env(timer_routed) {1670053198}
+set ::env(timer_start) {1670051544}
diff --git a/openlane/fpga_struct_block/config.tcl b/openlane/fpga_struct_block/config.tcl
new file mode 100644
index 0000000..4fe01d1
--- /dev/null
+++ b/openlane/fpga_struct_block/config.tcl
@@ -0,0 +1,31 @@
+set ::env(DESIGN_IS_CORE) 0
+set ::env(SYNTH_STRATEGY) "AREA 3"
+set ::env(CLOCK_PERIOD) 100
+set ::env(CLOCK_PORT) "clk_i config_clk_i"
+set ::env(FP_CORE_UTIL) 59
+set ::env(PL_TARGET_DENSITY) 0.7
+set ::env(SYNTH_TIMING_DERATE) 0.07
+set ::env(PL_TIME_DRIVEN) 1
+set ::env(PL_ROUTABILITY_DRIVEN) 1
+set ::env(RT_MAX_LAYER) Metal4
+set ::env(FP_PDN_VPITCH) 50
+set ::env(FP_PDN_AUTO_ADJUST) 0
+set ::env(GLB_RESIZER_TIMING_OPTIMIZATIONS) 1
+set ::env(GRT_ALLOW_CONGESTION) 1
+set ::env(DIODE_INSERTION_STRATEGY) 3
+set ::env(PL_RESIZER_TIMING_OPTIMIZATIONS) 1
+set ::env(PL_RESIZER_HOLD_SLACK_MARGIN) 0.1
+set ::env(PL_RESIZER_BUFFER_INPUT_PORTS) 0
+set ::env(PL_RESIZER_BUFFER_OUTPUT_PORTS) 1
+set ::env(RIGHT_MARGIN_MULT) 2
+set ::env(LEFT_MARGIN_MULT) 2
+set ::env(TOP_MARGIN_MULT) 2
+set ::env(BOTTOM_MARGIN_MULT) 2
+set ::env(DESIGN_NAME) fpga_struct_block
+set ::env(VERILOG_FILES) "designs/fpga_struct_block/fpga_struct_block_fromvhdl.v designs/fpga_struct_block/fpga_tech.v"
+set ::env(BASE_SDC_FILE) "designs/fpga_struct_block/fpga_struct_block.sdc"
+set ::env(FP_PIN_ORDER_CFG) "designs/fpga_struct_block/pin.cfg"
+set ::env(SYNTH_DRIVING_CELL) "gf180mcu_fd_sc_mcu7t5v0__buf_1"
+set ::env(SYNTH_DRIVING_CELL_PIN) "Z"
+set ::env(ROUTING_CORES) 24
+
diff --git a/openlane/fpga_struct_block/fpga_struct_block.sdc b/openlane/fpga_struct_block/fpga_struct_block.sdc
new file mode 100644
index 0000000..7c3f5b8
--- /dev/null
+++ b/openlane/fpga_struct_block/fpga_struct_block.sdc
@@ -0,0 +1,110 @@
+create_clock -name "clk_i" -add -period 40 [get_ports clk_i]
+create_clock -name "config_clk_i" -add -period 1000 [get_ports config_clk_i]
+
+set_units -time 1ns
+
+#set input_delay_value [expr $::env(CLOCK_PERIOD) * $::env(IO_PCT)]
+#set output_delay_value [expr $::env(CLOCK_PERIOD) * $::env(IO_PCT)]
+#puts "\[INFO\]: Setting output delay to: $output_delay_value"
+#puts "\[INFO\]: Setting input delay to: $input_delay_value"
+
+set_max_fanout $::env(SYNTH_MAX_FANOUT) [current_design]
+
+if {[info exists CLOCK_PORT]} {
+ set clk_indx [lsearch [all_inputs] [get_port $::env(CLOCK_PORT)]]
+ #set rst_indx [lsearch [all_inputs] [get_port resetn]]
+ set all_inputs_wo_clk [lreplace [all_inputs] $clk_indx $clk_indx]
+ #set all_inputs_wo_clk_rst [lreplace $all_inputs_wo_clk $rst_indx $rst_indx]
+ set all_inputs_wo_clk_rst $all_inputs_wo_clk
+ puts "\[INFO\]: Setting clock uncertainity to: $::env(SYNTH_CLOCK_UNCERTAINITY)"
+ set_clock_uncertainty $::env(SYNTH_CLOCK_UNCERTAINITY) [get_clocks $::env(CLOCK_PORT)]
+}
+
+# TODO set this as parameter
+set_driving_cell -lib_cell $::env(SYNTH_DRIVING_CELL) -pin $::env(SYNTH_DRIVING_CELL_PIN) [all_inputs]
+set cap_load [expr $::env(SYNTH_CAP_LOAD) / 1000.0]
+puts "\[INFO\]: Setting load to: $cap_load"
+set_load $cap_load [all_outputs]
+
+puts "\[INFO\]: Setting clock transition to: $::env(SYNTH_CLOCK_TRANSITION)"
+#set_clock_transition $::env(SYNTH_CLOCK_TRANSITION) [get_clocks $::env(CLOCK_PORT)]
+
+puts "\[INFO\]: Setting timing derate to: [expr {$::env(SYNTH_TIMING_DERATE) * 10}] %"
+set_timing_derate -early [expr {1-$::env(SYNTH_TIMING_DERATE)}]
+set_timing_derate -late [expr {1+$::env(SYNTH_TIMING_DERATE)}]
+
+
+# Disable all cross-clocking paths
+set_false_path -from [get_clocks clk_i] -to [get_clocks config_clk_i]
+set_false_path -from [get_clocks config_clk_i] -to [get_clocks clk_i]
+
+set BUFIPIN [lindex [lreverse [split [lindex [get_name [lindex [get_pin -hier *tech_buf/*] 0]] 0] /]] 0]
+set BUFOPIN [lindex [lreverse [split [lindex [get_name [lindex [get_pin -hier *tech_buf/*] 1]] 0] /]] 0]
+
+# Logic cell constraints
+set_disable_timing [get_cells *logic_block*logic_cells***cell.lut.breaker*loop_breaker.tech_buf]
+
+set_max_delay -ignore_clock_latency 2.0 -from [get_pins *logic_block*logic_cells*1*cell.in_bufs*1*cell_tstart.tech_buf/$BUFIPIN] -to [get_pins *logic_block*logic_cells*1*cell.lut.breaker*lut_tfinish.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 2.0 -from [get_pins *logic_block*logic_cells*1*cell.in_bufs*2*cell_tstart.tech_buf/$BUFIPIN] -to [get_pins *logic_block*logic_cells*1*cell.lut.breaker*lut_tfinish.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 4.0 -from [get_pins *logic_block*logic_cells*1*cell.in_bufs*3*cell_tstart.tech_buf/$BUFIPIN] -to [get_pins *logic_block*logic_cells*1*cell.lut.breaker*lut_tfinish.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 4.0 -from [get_pins *logic_block*logic_cells*1*cell.in_bufs*4*cell_tstart.tech_buf/$BUFIPIN] -to [get_pins *logic_block*logic_cells*1*cell.lut.breaker*lut_tfinish.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.32 -from [get_pins *logic_block*logic_cells*1*cell.lut.breaker*lut_tfinish.tech_buf/$BUFIPIN] -to [get_pins *logic_block*logic_cells*1*cell.cell_reg.register/D]
+set_max_delay -ignore_clock_latency 2.0 -from [get_pins *logic_block*logic_cells*2*cell.in_bufs*1*cell_tstart.tech_buf/$BUFIPIN] -to [get_pins *logic_block*logic_cells*2*cell.lut.breaker*lut_tfinish.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 2.0 -from [get_pins *logic_block*logic_cells*2*cell.in_bufs*2*cell_tstart.tech_buf/$BUFIPIN] -to [get_pins *logic_block*logic_cells*2*cell.lut.breaker*lut_tfinish.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 4.0 -from [get_pins *logic_block*logic_cells*2*cell.in_bufs*3*cell_tstart.tech_buf/$BUFIPIN] -to [get_pins *logic_block*logic_cells*2*cell.lut.breaker*lut_tfinish.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 4.0 -from [get_pins *logic_block*logic_cells*2*cell.in_bufs*4*cell_tstart.tech_buf/$BUFIPIN] -to [get_pins *logic_block*logic_cells*2*cell.lut.breaker*lut_tfinish.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.32 -from [get_pins *logic_block*logic_cells*2*cell.lut.breaker*lut_tfinish.tech_buf/$BUFIPIN] -to [get_pins *logic_block*logic_cells*2*cell.cell_reg.register/D]
+set_max_delay -ignore_clock_latency 2.0 -from [get_pins *logic_block*logic_cells*3*cell.in_bufs*1*cell_tstart.tech_buf/$BUFIPIN] -to [get_pins *logic_block*logic_cells*3*cell.lut.breaker*lut_tfinish.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 2.0 -from [get_pins *logic_block*logic_cells*3*cell.in_bufs*2*cell_tstart.tech_buf/$BUFIPIN] -to [get_pins *logic_block*logic_cells*3*cell.lut.breaker*lut_tfinish.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 4.0 -from [get_pins *logic_block*logic_cells*3*cell.in_bufs*3*cell_tstart.tech_buf/$BUFIPIN] -to [get_pins *logic_block*logic_cells*3*cell.lut.breaker*lut_tfinish.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 4.0 -from [get_pins *logic_block*logic_cells*3*cell.in_bufs*4*cell_tstart.tech_buf/$BUFIPIN] -to [get_pins *logic_block*logic_cells*3*cell.lut.breaker*lut_tfinish.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.32 -from [get_pins *logic_block*logic_cells*3*cell.lut.breaker*lut_tfinish.tech_buf/$BUFIPIN] -to [get_pins *logic_block*logic_cells*3*cell.cell_reg.register/D]
+set_max_delay -ignore_clock_latency 2.0 -from [get_pins *logic_block*logic_cells*4*cell.in_bufs*1*cell_tstart.tech_buf/$BUFIPIN] -to [get_pins *logic_block*logic_cells*4*cell.lut.breaker*lut_tfinish.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 2.0 -from [get_pins *logic_block*logic_cells*4*cell.in_bufs*2*cell_tstart.tech_buf/$BUFIPIN] -to [get_pins *logic_block*logic_cells*4*cell.lut.breaker*lut_tfinish.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 4.0 -from [get_pins *logic_block*logic_cells*4*cell.in_bufs*3*cell_tstart.tech_buf/$BUFIPIN] -to [get_pins *logic_block*logic_cells*4*cell.lut.breaker*lut_tfinish.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 4.0 -from [get_pins *logic_block*logic_cells*4*cell.in_bufs*4*cell_tstart.tech_buf/$BUFIPIN] -to [get_pins *logic_block*logic_cells*4*cell.lut.breaker*lut_tfinish.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.32 -from [get_pins *logic_block*logic_cells*4*cell.lut.breaker*lut_tfinish.tech_buf/$BUFIPIN] -to [get_pins *logic_block*logic_cells*4*cell.cell_reg.register/D]
+set_max_delay -ignore_clock_latency 2.0 -from [get_pins *logic_block*logic_cells*5*cell.in_bufs*1*cell_tstart.tech_buf/$BUFIPIN] -to [get_pins *logic_block*logic_cells*5*cell.lut.breaker*lut_tfinish.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 2.0 -from [get_pins *logic_block*logic_cells*5*cell.in_bufs*2*cell_tstart.tech_buf/$BUFIPIN] -to [get_pins *logic_block*logic_cells*5*cell.lut.breaker*lut_tfinish.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 4.0 -from [get_pins *logic_block*logic_cells*5*cell.in_bufs*3*cell_tstart.tech_buf/$BUFIPIN] -to [get_pins *logic_block*logic_cells*5*cell.lut.breaker*lut_tfinish.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 4.0 -from [get_pins *logic_block*logic_cells*5*cell.in_bufs*4*cell_tstart.tech_buf/$BUFIPIN] -to [get_pins *logic_block*logic_cells*5*cell.lut.breaker*lut_tfinish.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.32 -from [get_pins *logic_block*logic_cells*5*cell.lut.breaker*lut_tfinish.tech_buf/$BUFIPIN] -to [get_pins *logic_block*logic_cells*5*cell.cell_reg.register/D]
+set_max_delay -ignore_clock_latency 2.0 -from [get_pins *logic_block*logic_cells*6*cell.in_bufs*1*cell_tstart.tech_buf/$BUFIPIN] -to [get_pins *logic_block*logic_cells*6*cell.lut.breaker*lut_tfinish.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 2.0 -from [get_pins *logic_block*logic_cells*6*cell.in_bufs*2*cell_tstart.tech_buf/$BUFIPIN] -to [get_pins *logic_block*logic_cells*6*cell.lut.breaker*lut_tfinish.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 4.0 -from [get_pins *logic_block*logic_cells*6*cell.in_bufs*3*cell_tstart.tech_buf/$BUFIPIN] -to [get_pins *logic_block*logic_cells*6*cell.lut.breaker*lut_tfinish.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 4.0 -from [get_pins *logic_block*logic_cells*6*cell.in_bufs*4*cell_tstart.tech_buf/$BUFIPIN] -to [get_pins *logic_block*logic_cells*6*cell.lut.breaker*lut_tfinish.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.32 -from [get_pins *logic_block*logic_cells*6*cell.lut.breaker*lut_tfinish.tech_buf/$BUFIPIN] -to [get_pins *logic_block*logic_cells*6*cell.cell_reg.register/D]
+set_max_delay -ignore_clock_latency 2.0 -from [get_pins *logic_block*logic_cells*7*cell.in_bufs*1*cell_tstart.tech_buf/$BUFIPIN] -to [get_pins *logic_block*logic_cells*7*cell.lut.breaker*lut_tfinish.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 2.0 -from [get_pins *logic_block*logic_cells*7*cell.in_bufs*2*cell_tstart.tech_buf/$BUFIPIN] -to [get_pins *logic_block*logic_cells*7*cell.lut.breaker*lut_tfinish.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 4.0 -from [get_pins *logic_block*logic_cells*7*cell.in_bufs*3*cell_tstart.tech_buf/$BUFIPIN] -to [get_pins *logic_block*logic_cells*7*cell.lut.breaker*lut_tfinish.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 4.0 -from [get_pins *logic_block*logic_cells*7*cell.in_bufs*4*cell_tstart.tech_buf/$BUFIPIN] -to [get_pins *logic_block*logic_cells*7*cell.lut.breaker*lut_tfinish.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.32 -from [get_pins *logic_block*logic_cells*7*cell.lut.breaker*lut_tfinish.tech_buf/$BUFIPIN] -to [get_pins *logic_block*logic_cells*7*cell.cell_reg.register/D]
+set_max_delay -ignore_clock_latency 2.0 -from [get_pins *logic_block*logic_cells*8*cell.in_bufs*1*cell_tstart.tech_buf/$BUFIPIN] -to [get_pins *logic_block*logic_cells*8*cell.lut.breaker*lut_tfinish.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 2.0 -from [get_pins *logic_block*logic_cells*8*cell.in_bufs*2*cell_tstart.tech_buf/$BUFIPIN] -to [get_pins *logic_block*logic_cells*8*cell.lut.breaker*lut_tfinish.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 4.0 -from [get_pins *logic_block*logic_cells*8*cell.in_bufs*3*cell_tstart.tech_buf/$BUFIPIN] -to [get_pins *logic_block*logic_cells*8*cell.lut.breaker*lut_tfinish.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 4.0 -from [get_pins *logic_block*logic_cells*8*cell.in_bufs*4*cell_tstart.tech_buf/$BUFIPIN] -to [get_pins *logic_block*logic_cells*8*cell.lut.breaker*lut_tfinish.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.32 -from [get_pins *logic_block*logic_cells*8*cell.lut.breaker*lut_tfinish.tech_buf/$BUFIPIN] -to [get_pins *logic_block*logic_cells*8*cell.cell_reg.register/D]
+
+# Crossbar constraints
+set_max_delay -ignore_clock_latency 7.2 -from [get_pins *logic_block*logic_cells***cell.lut.breaker*lut_tfinish.tech_buf/$BUFIPIN] -to [get_pins *logic_block*logic_cells***cell.in_bufs***cell_tstart.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 7.2 -from [get_ports inputs_i*] -to [get_pins *logic_block*logic_cells***cell.in_bufs***cell_tstart.tech_buf/$BUFOPIN]
+
+# Output constraints
+set_max_delay -ignore_clock_latency 2.4 -from [get_pins *logic_block*logic_cells*1*cell.lut.breaker*lut_tfinish.tech_buf/$BUFIPIN] -to [get_ports outputs_o[0]]
+set_max_delay -ignore_clock_latency 2.4 -from [get_pins *logic_block*logic_cells*1*cell.cell_reg.register/Q] -to [get_ports outputs_o[0]]
+set_max_delay -ignore_clock_latency 2.4 -from [get_pins *logic_block*logic_cells*2*cell.lut.breaker*lut_tfinish.tech_buf/$BUFIPIN] -to [get_ports outputs_o[1]]
+set_max_delay -ignore_clock_latency 2.4 -from [get_pins *logic_block*logic_cells*2*cell.cell_reg.register/Q] -to [get_ports outputs_o[1]]
+set_max_delay -ignore_clock_latency 2.4 -from [get_pins *logic_block*logic_cells*3*cell.lut.breaker*lut_tfinish.tech_buf/$BUFIPIN] -to [get_ports outputs_o[2]]
+set_max_delay -ignore_clock_latency 2.4 -from [get_pins *logic_block*logic_cells*3*cell.cell_reg.register/Q] -to [get_ports outputs_o[2]]
+set_max_delay -ignore_clock_latency 2.4 -from [get_pins *logic_block*logic_cells*4*cell.lut.breaker*lut_tfinish.tech_buf/$BUFIPIN] -to [get_ports outputs_o[3]]
+set_max_delay -ignore_clock_latency 2.4 -from [get_pins *logic_block*logic_cells*4*cell.cell_reg.register/Q] -to [get_ports outputs_o[3]]
+set_max_delay -ignore_clock_latency 2.4 -from [get_pins *logic_block*logic_cells*5*cell.lut.breaker*lut_tfinish.tech_buf/$BUFIPIN] -to [get_ports outputs_o[4]]
+set_max_delay -ignore_clock_latency 2.4 -from [get_pins *logic_block*logic_cells*5*cell.cell_reg.register/Q] -to [get_ports outputs_o[4]]
+set_max_delay -ignore_clock_latency 2.4 -from [get_pins *logic_block*logic_cells*6*cell.lut.breaker*lut_tfinish.tech_buf/$BUFIPIN] -to [get_ports outputs_o[5]]
+set_max_delay -ignore_clock_latency 2.4 -from [get_pins *logic_block*logic_cells*6*cell.cell_reg.register/Q] -to [get_ports outputs_o[5]]
+set_max_delay -ignore_clock_latency 2.4 -from [get_pins *logic_block*logic_cells*7*cell.lut.breaker*lut_tfinish.tech_buf/$BUFIPIN] -to [get_ports outputs_o[6]]
+set_max_delay -ignore_clock_latency 2.4 -from [get_pins *logic_block*logic_cells*7*cell.cell_reg.register/Q] -to [get_ports outputs_o[6]]
+set_max_delay -ignore_clock_latency 2.4 -from [get_pins *logic_block*logic_cells*8*cell.lut.breaker*lut_tfinish.tech_buf/$BUFIPIN] -to [get_ports outputs_o[7]]
+set_max_delay -ignore_clock_latency 2.4 -from [get_pins *logic_block*logic_cells*8*cell.cell_reg.register/Q] -to [get_ports outputs_o[7]]
+set_input_delay 0.0 -clock [get_clocks config_clk_i] [get_ports config_shift_i]
+
diff --git a/openlane/fpga_struct_block/pin.cfg b/openlane/fpga_struct_block/pin.cfg
new file mode 100644
index 0000000..3a307d1
--- /dev/null
+++ b/openlane/fpga_struct_block/pin.cfg
@@ -0,0 +1,151 @@
+#N
+config_clk_i
+config_ena_i
+config_shift_i
+glb_rstn_i
+outputs_o\[0\]
+outputs_o\[4\]
+inputs_up_i\[0\]
+inputs_up_i\[1\]
+inputs_up_i\[2\]
+inputs_up_i\[3\]
+inputs_up_i\[4\]
+inputs_up_i\[5\]
+inputs_up_i\[6\]
+inputs_up_i\[7\]
+inputs_up_i\[8\]
+inputs_up_i\[9\]
+inputs_up_i\[10\]
+inputs_up_i\[11\]
+inputs_up_i\[12\]
+inputs_up_i\[13\]
+inputs_up_i\[14\]
+inputs_up_i\[15\]
+inputs_up_i\[16\]
+inputs_up_i\[17\]
+inputs_up_i\[18\]
+inputs_up_i\[19\]
+inputs_up_i\[20\]
+inputs_up_i\[21\]
+inputs_up_i\[22\]
+inputs_up_i\[23\]
+inputs_up_i\[24\]
+inputs_up_i\[25\]
+inputs_up_i\[26\]
+inputs_up_i\[27\]
+inputs_up_i\[28\]
+inputs_up_i\[29\]
+inputs_up_i\[30\]
+inputs_up_i\[31\]
+
+#E
+clk_i
+outputs_o\[1\]
+outputs_o\[5\]
+inputs_right_i\[0\]
+inputs_right_i\[1\]
+inputs_right_i\[2\]
+inputs_right_i\[3\]
+inputs_right_i\[4\]
+inputs_right_i\[5\]
+inputs_right_i\[6\]
+inputs_right_i\[7\]
+inputs_right_i\[8\]
+inputs_right_i\[9\]
+inputs_right_i\[10\]
+inputs_right_i\[11\]
+inputs_right_i\[12\]
+inputs_right_i\[13\]
+inputs_right_i\[14\]
+inputs_right_i\[15\]
+inputs_right_i\[16\]
+inputs_right_i\[17\]
+inputs_right_i\[18\]
+inputs_right_i\[19\]
+inputs_right_i\[20\]
+inputs_right_i\[21\]
+inputs_right_i\[22\]
+inputs_right_i\[23\]
+inputs_right_i\[24\]
+inputs_right_i\[25\]
+inputs_right_i\[26\]
+inputs_right_i\[27\]
+inputs_right_i\[28\]
+inputs_right_i\[29\]
+inputs_right_i\[30\]
+inputs_right_i\[31\]
+
+#S
+config_shift_o
+outputs_o\[2\]
+outputs_o\[6\]
+inputs_down_i\[0\]
+inputs_down_i\[1\]
+inputs_down_i\[2\]
+inputs_down_i\[3\]
+inputs_down_i\[4\]
+inputs_down_i\[5\]
+inputs_down_i\[6\]
+inputs_down_i\[7\]
+inputs_down_i\[8\]
+inputs_down_i\[9\]
+inputs_down_i\[10\]
+inputs_down_i\[11\]
+inputs_down_i\[12\]
+inputs_down_i\[13\]
+inputs_down_i\[14\]
+inputs_down_i\[15\]
+inputs_down_i\[16\]
+inputs_down_i\[17\]
+inputs_down_i\[18\]
+inputs_down_i\[19\]
+inputs_down_i\[20\]
+inputs_down_i\[21\]
+inputs_down_i\[22\]
+inputs_down_i\[23\]
+inputs_down_i\[24\]
+inputs_down_i\[25\]
+inputs_down_i\[26\]
+inputs_down_i\[27\]
+inputs_down_i\[28\]
+inputs_down_i\[29\]
+inputs_down_i\[30\]
+inputs_down_i\[31\]
+
+#W
+outputs_o\[3\]
+outputs_o\[7\]
+inputs_left_i\[0\]
+inputs_left_i\[1\]
+inputs_left_i\[2\]
+inputs_left_i\[3\]
+inputs_left_i\[4\]
+inputs_left_i\[5\]
+inputs_left_i\[6\]
+inputs_left_i\[7\]
+inputs_left_i\[8\]
+inputs_left_i\[9\]
+inputs_left_i\[10\]
+inputs_left_i\[11\]
+inputs_left_i\[12\]
+inputs_left_i\[13\]
+inputs_left_i\[14\]
+inputs_left_i\[15\]
+inputs_left_i\[16\]
+inputs_left_i\[17\]
+inputs_left_i\[18\]
+inputs_left_i\[19\]
+inputs_left_i\[20\]
+inputs_left_i\[21\]
+inputs_left_i\[22\]
+inputs_left_i\[23\]
+inputs_left_i\[24\]
+inputs_left_i\[25\]
+inputs_left_i\[26\]
+inputs_left_i\[27\]
+inputs_left_i\[28\]
+inputs_left_i\[29\]
+inputs_left_i\[30\]
+inputs_left_i\[31\]
+
+
diff --git a/openlane/macro.cfg b/openlane/macro.cfg
new file mode 100644
index 0000000..7dbb66e
--- /dev/null
+++ b/openlane/macro.cfg
@@ -0,0 +1,16 @@
+ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:1.struct_block 100.0 100.0 N
+ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:2.struct_block 100.0 514.0 N
+ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:3.struct_block 100.0 927.9999999999999 N
+ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:4.struct_block 100.0 1341.9999999999998 N
+ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:5.struct_block 100.0 1755.9999999999998 N
+ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:6.struct_block 100.0 2169.9999999999995 N
+ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:7.struct_block 100.0 2583.9999999999995 N
+ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:1.struct_block 435.40000000000003 100.0 N
+ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:2.struct_block 435.40000000000003 514.0 N
+ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:3.struct_block 435.40000000000003 927.9999999999999 N
+ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:4.struct_block 435.40000000000003 1341.9999999999998 N
+ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:5.struct_block 435.40000000000003 1755.9999999999998 N
+ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:6.struct_block 435.40000000000003 2169.9999999999995 N
+ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:7.struct_block 435.40000000000003 2583.9999999999995 N
+ariel_fpga_top_inst.efuse 770.8000000000001 336.7 N
+
diff --git a/openlane/pin.cfg b/openlane/pin.cfg
new file mode 100644
index 0000000..b515bf6
--- /dev/null
+++ b/openlane/pin.cfg
@@ -0,0 +1,157 @@
+#BUS_SORT
+#NR
+analog_io\[8\]
+io_in\[15\]
+io_out\[15\]
+io_oeb\[15\]
+analog_io\[9\]
+io_in\[16\]
+io_out\[16\]
+io_oeb\[16\]
+analog_io\[10\]
+io_in\[17\]
+io_out\[17\]
+io_oeb\[17\]
+analog_io\[11\]
+io_in\[18\]
+io_out\[18\]
+io_oeb\[18\]
+analog_io\[12\]
+io_in\[19\]
+io_out\[19\]
+io_oeb\[19\]
+analog_io\[13\]
+io_in\[20\]
+io_out\[20\]
+io_oeb\[20\]
+analog_io\[14\]
+io_in\[21\]
+io_out\[21\]
+io_oeb\[21\]
+analog_io\[15\]
+io_in\[22\]
+io_out\[22\]
+io_oeb\[22\]
+analog_io\[16\]
+io_in\[23\]
+io_out\[23\]
+io_oeb\[23\]
+
+#S
+wb_.*
+wbs_.*
+la_.*
+user_clock2
+user_irq.*
+
+#E
+io_in\[0\]
+io_out\[0\]
+io_oeb\[0\]
+io_in\[1\]
+io_out\[1\]
+io_oeb\[1\]
+io_in\[2\]
+io_out\[2\]
+io_oeb\[2\]
+io_in\[3\]
+io_out\[3\]
+io_oeb\[3\]
+io_in\[4\]
+io_out\[4\]
+io_oeb\[4\]
+io_in\[5\]
+io_out\[5\]
+io_oeb\[5\]
+io_in\[6\]
+io_out\[6\]
+io_oeb\[6\]
+analog_io\[0\]
+io_in\[7\]
+io_out\[7\]
+io_oeb\[7\]
+analog_io\[1\]
+io_in\[8\]
+io_out\[8\]
+io_oeb\[8\]
+analog_io\[2\]
+io_in\[9\]
+io_out\[9\]
+io_oeb\[9\]
+analog_io\[3\]
+io_in\[10\]
+io_out\[10\]
+io_oeb\[10\]
+analog_io\[4\]
+io_in\[11\]
+io_out\[11\]
+io_oeb\[11\]
+analog_io\[5\]
+io_in\[12\]
+io_out\[12\]
+io_oeb\[12\]
+analog_io\[6\]
+io_in\[13\]
+io_out\[13\]
+io_oeb\[13\]
+analog_io\[7\]
+io_in\[14\]
+io_out\[14\]
+io_oeb\[14\]
+
+#WR
+analog_io\[17\]
+io_in\[24\]
+io_out\[24\]
+io_oeb\[24\]
+analog_io\[18\]
+io_in\[25\]
+io_out\[25\]
+io_oeb\[25\]
+analog_io\[19\]
+io_in\[26\]
+io_out\[26\]
+io_oeb\[26\]
+analog_io\[20\]
+io_in\[27\]
+io_out\[27\]
+io_oeb\[27\]
+analog_io\[21\]
+io_in\[28\]
+io_out\[28\]
+io_oeb\[28\]
+analog_io\[22\]
+io_in\[29\]
+io_out\[29\]
+io_oeb\[29\]
+analog_io\[23\]
+io_in\[30\]
+io_out\[30\]
+io_oeb\[30\]
+analog_io\[24\]
+io_in\[31\]
+io_out\[31\]
+io_oeb\[31\]
+analog_io\[25\]
+io_in\[32\]
+io_out\[32\]
+io_oeb\[32\]
+analog_io\[26\]
+io_in\[33\]
+io_out\[33\]
+io_oeb\[33\]
+analog_io\[27\]
+io_in\[34\]
+io_out\[34\]
+io_oeb\[34\]
+analog_io\[28\]
+io_in\[35\]
+io_out\[35\]
+io_oeb\[35\]
+io_in\[36\]
+io_out\[36\]
+io_oeb\[36\]
+io_in\[37\]
+io_out\[37\]
+io_oeb\[37\]
+
diff --git a/openlane/user_project_wrapper.sdc b/openlane/user_project_wrapper.sdc
new file mode 100644
index 0000000..8ac36b6
--- /dev/null
+++ b/openlane/user_project_wrapper.sdc
@@ -0,0 +1,532 @@
+create_clock -name "wb_clk_i" -add -period 40 [get_ports wb_clk_i]
+create_clock -name "ariel_fpga_top_inst.config_block_clk_buf.tech_clkbuf" -add -period 1000 [get_pins ariel_fpga_top_inst.config_block_clk_buf.tech_clkbuf/X]
+create_clock -name "ariel_fpga_top_inst.config_vrnode_clk_buf.tech_clkbuf" -add -period 1000 [get_pins ariel_fpga_top_inst.config_vrnode_clk_buf.tech_clkbuf/X]
+create_clock -name "ariel_fpga_top_inst.config_hrnode_clk_buf.tech_clkbuf" -add -period 1000 [get_pins ariel_fpga_top_inst.config_hrnode_clk_buf.tech_clkbuf/X]
+
+set_units -time 1ns
+
+#set input_delay_value [expr $::env(CLOCK_PERIOD) * $::env(IO_PCT)]
+#set output_delay_value [expr $::env(CLOCK_PERIOD) * $::env(IO_PCT)]
+#puts "\[INFO\]: Setting output delay to: $output_delay_value"
+#puts "\[INFO\]: Setting input delay to: $input_delay_value"
+
+set_max_fanout $::env(SYNTH_MAX_FANOUT) [current_design]
+
+if {[info exists CLOCK_PORT]} {
+ set clk_indx [lsearch [all_inputs] [get_port $::env(CLOCK_PORT)]]
+ #set rst_indx [lsearch [all_inputs] [get_port resetn]]
+ set all_inputs_wo_clk [lreplace [all_inputs] $clk_indx $clk_indx]
+ #set all_inputs_wo_clk_rst [lreplace $all_inputs_wo_clk $rst_indx $rst_indx]
+ set all_inputs_wo_clk_rst $all_inputs_wo_clk
+ puts "\[INFO\]: Setting clock uncertainity to: $::env(SYNTH_CLOCK_UNCERTAINITY)"
+ set_clock_uncertainty $::env(SYNTH_CLOCK_UNCERTAINITY) [get_clocks $::env(CLOCK_PORT)]
+}
+
+# TODO set this as parameter
+set_driving_cell -lib_cell $::env(SYNTH_DRIVING_CELL) -pin $::env(SYNTH_DRIVING_CELL_PIN) [all_inputs]
+set cap_load [expr $::env(SYNTH_CAP_LOAD) / 1000.0]
+puts "\[INFO\]: Setting load to: $cap_load"
+set_load $cap_load [all_outputs]
+
+puts "\[INFO\]: Setting clock transition to: $::env(SYNTH_CLOCK_TRANSITION)"
+#set_clock_transition $::env(SYNTH_CLOCK_TRANSITION) [get_clocks $::env(CLOCK_PORT)]
+
+puts "\[INFO\]: Setting timing derate to: [expr {$::env(SYNTH_TIMING_DERATE) * 10}] %"
+set_timing_derate -early [expr {1-$::env(SYNTH_TIMING_DERATE)}]
+set_timing_derate -late [expr {1+$::env(SYNTH_TIMING_DERATE)}]
+
+
+# Disable all cross-clocking paths
+set_false_path -from [get_clocks wb_clk_i] -to [get_clocks ariel_fpga_top_inst.config_block_clk_buf.tech_clkbuf]
+set_false_path -from [get_clocks wb_clk_i] -to [get_clocks ariel_fpga_top_inst.config_vrnode_clk_buf.tech_clkbuf]
+set_false_path -from [get_clocks wb_clk_i] -to [get_clocks ariel_fpga_top_inst.config_hrnode_clk_buf.tech_clkbuf]
+set_false_path -from [get_clocks ariel_fpga_top_inst.config_block_clk_buf.tech_clkbuf] -to [get_clocks wb_clk_i]
+set_false_path -from [get_clocks ariel_fpga_top_inst.config_block_clk_buf.tech_clkbuf] -to [get_clocks ariel_fpga_top_inst.config_vrnode_clk_buf.tech_clkbuf]
+set_false_path -from [get_clocks ariel_fpga_top_inst.config_block_clk_buf.tech_clkbuf] -to [get_clocks ariel_fpga_top_inst.config_hrnode_clk_buf.tech_clkbuf]
+set_false_path -from [get_clocks ariel_fpga_top_inst.config_vrnode_clk_buf.tech_clkbuf] -to [get_clocks wb_clk_i]
+set_false_path -from [get_clocks ariel_fpga_top_inst.config_vrnode_clk_buf.tech_clkbuf] -to [get_clocks ariel_fpga_top_inst.config_block_clk_buf.tech_clkbuf]
+set_false_path -from [get_clocks ariel_fpga_top_inst.config_vrnode_clk_buf.tech_clkbuf] -to [get_clocks ariel_fpga_top_inst.config_hrnode_clk_buf.tech_clkbuf]
+set_false_path -from [get_clocks ariel_fpga_top_inst.config_hrnode_clk_buf.tech_clkbuf] -to [get_clocks wb_clk_i]
+set_false_path -from [get_clocks ariel_fpga_top_inst.config_hrnode_clk_buf.tech_clkbuf] -to [get_clocks ariel_fpga_top_inst.config_block_clk_buf.tech_clkbuf]
+set_false_path -from [get_clocks ariel_fpga_top_inst.config_hrnode_clk_buf.tech_clkbuf] -to [get_clocks ariel_fpga_top_inst.config_vrnode_clk_buf.tech_clkbuf]
+
+set BUFIPIN [lindex [lreverse [split [lindex [get_name [lindex [get_pin -hier *tech_buf/*] 0]] 0] /]] 0]
+set BUFOPIN [lindex [lreverse [split [lindex [get_name [lindex [get_pin -hier *tech_buf/*] 1]] 0] /]] 0]
+set_disable_timing [get_cells *loop_breaker*]
+
+# Routing node <-> LB constraints
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:1.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:1.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:1.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:1.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:1.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:1.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:1.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:1.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:2.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:1.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:1.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:2.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:1.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:1.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:1.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:1.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:1.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:1.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:1.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:1.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:1.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:1.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:1.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:1.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:2.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:1.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:1.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:2.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:1.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:1.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:1.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:1.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:2.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:2.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:2.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:2.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:2.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:2.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:2.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:2.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:3.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:2.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:2.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:3.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:2.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:2.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:2.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:2.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:2.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:2.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:2.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:2.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:2.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:2.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:2.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:2.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:3.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:2.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:2.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:3.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:2.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:2.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:2.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:2.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:3.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:3.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:3.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:3.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:3.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:3.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:3.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:3.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:4.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:3.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:3.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:4.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:3.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:3.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:3.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:3.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:3.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:3.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:3.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:3.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:3.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:3.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:3.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:3.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:4.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:3.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:3.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:4.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:3.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:3.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:3.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:3.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:4.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:4.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:4.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:4.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:4.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:4.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:4.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:4.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:5.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:4.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:4.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:5.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:4.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:4.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:4.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:4.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:4.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:4.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:4.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:4.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:4.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:4.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:4.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:4.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:5.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:4.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:4.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:5.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:4.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:4.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:4.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:4.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:5.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:5.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:5.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:5.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:5.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:5.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:5.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:5.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:6.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:5.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:5.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:6.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:5.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:5.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:5.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:5.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:5.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:5.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:5.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:5.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:5.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:5.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:5.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:5.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:6.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:5.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:5.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:6.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:5.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:5.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:5.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:5.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:6.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:6.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:6.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:6.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:6.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:6.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:6.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:6.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:7.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:6.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:6.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:7.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:6.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:6.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:6.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:6.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:6.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:6.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:6.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:6.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:6.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:6.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:6.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:6.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:7.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:6.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:6.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:7.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:6.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:6.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:6.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:6.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:7.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:7.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:7.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:7.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:7.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:7.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:7.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:7.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:8.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:7.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:7.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:8.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:7.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:7.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:7.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:7.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:7.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:7.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:7.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:7.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:7.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:7.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:7.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:7.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:8.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:7.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:7.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:8.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:7.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:7.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:7.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:7.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:1.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:1.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:1.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:1.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:1.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:1.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:1.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:1.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:2.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:1.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:1.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:2.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:1.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:1.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:1.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:1.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:1.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:1.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:1.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:1.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:1.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:1.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:1.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:1.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:2.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:1.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:1.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:2.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:1.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:1.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:1.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:1.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:2.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:2.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:2.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:2.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:2.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:2.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:2.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:2.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:3.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:2.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:2.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:3.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:2.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:2.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:2.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:2.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:2.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:2.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:2.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:2.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:2.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:2.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:2.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:2.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:3.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:2.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:2.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:3.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:2.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:2.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:2.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:2.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:3.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:3.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:3.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:3.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:3.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:3.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:3.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:3.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:4.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:3.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:3.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:4.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:3.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:3.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:3.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:3.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:3.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:3.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:3.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:3.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:3.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:3.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:3.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:3.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:4.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:3.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:3.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:4.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:3.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:3.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:3.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:3.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:4.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:4.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:4.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:4.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:4.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:4.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:4.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:4.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:5.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:4.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:4.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:5.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:4.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:4.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:4.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:4.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:4.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:4.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:4.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:4.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:4.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:4.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:4.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:4.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:5.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:4.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:4.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:5.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:4.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:4.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:4.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:4.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:5.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:5.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:5.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:5.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:5.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:5.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:5.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:5.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:6.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:5.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:5.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:6.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:5.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:5.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:5.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:5.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:5.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:5.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:5.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:5.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:5.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:5.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:5.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:5.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:6.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:5.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:5.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:6.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:5.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:5.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:5.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:5.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:6.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:6.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:6.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:6.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:6.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:6.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:6.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:6.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:7.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:6.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:6.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:7.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:6.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:6.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:6.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:6.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:6.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:6.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:6.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:6.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:6.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:6.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:6.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:6.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:7.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:6.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:6.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:7.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:6.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:6.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:6.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:6.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:7.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:7.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:7.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:7.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:7.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:7.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:7.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:7.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:8.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:7.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:7.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:8.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:7.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:7.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:7.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:7.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:7.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:7.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:7.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:7.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:7.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:7.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:7.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:7.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:8.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:7.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:7.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:8.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:7.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:7.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:7.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:7.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+
+# Routing node internal && RN <-> RN constraints
+set_max_delay -ignore_clock_latency 2.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:1.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:1.routing_node_up.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:1.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:2.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:1.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:2.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 2.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:1.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:1.routing_node_down.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:1.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:1.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 2.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:2.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:2.routing_node_up.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:2.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:3.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:2.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:3.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 2.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:2.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:2.routing_node_down.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:2.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:1.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:2.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:2.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 2.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:3.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:3.routing_node_up.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:3.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:4.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:3.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:4.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 2.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:3.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:3.routing_node_down.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:3.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:2.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:3.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:3.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 2.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:4.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:4.routing_node_up.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:4.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:5.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:4.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:5.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 2.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:4.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:4.routing_node_down.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:4.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:3.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:4.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:4.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 2.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:5.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:5.routing_node_up.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:5.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:6.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:5.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:6.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 2.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:5.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:5.routing_node_down.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:5.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:4.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:5.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:5.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 2.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:6.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:6.routing_node_up.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:6.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:7.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:6.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:7.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 2.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:6.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:6.routing_node_down.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:6.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:5.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:6.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:6.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 2.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:7.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:7.routing_node_up.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:7.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:8.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 2.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:7.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:7.routing_node_down.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:7.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:6.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:7.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:7.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 2.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:1.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:1.routing_node_right.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:1.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:1.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:1.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:1.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 2.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:1.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:1.routing_node_left.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:1.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:1.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 2.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:1.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:1.routing_node_up.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:1.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:2.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:1.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:2.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:1.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:2.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 2.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:2.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:2.routing_node_right.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:2.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:2.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:2.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:1.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:2.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:2.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 2.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:1.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:1.routing_node_down.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:1.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:1.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:1.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:1.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 2.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:2.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:2.routing_node_left.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:2.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:2.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:2.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:1.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 2.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:2.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:2.routing_node_up.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:2.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:3.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:2.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:3.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:2.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:3.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 2.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:3.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:3.routing_node_right.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:3.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:3.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:3.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:2.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:3.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:3.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 2.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:2.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:2.routing_node_down.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:2.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:1.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:2.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:2.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:2.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:2.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 2.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:3.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:3.routing_node_left.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:3.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:3.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:3.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:2.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 2.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:3.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:3.routing_node_up.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:3.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:4.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:3.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:4.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:3.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:4.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 2.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:4.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:4.routing_node_right.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:4.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:4.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:4.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:3.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:4.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:4.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 2.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:3.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:3.routing_node_down.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:3.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:2.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:3.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:3.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:3.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:3.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 2.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:4.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:4.routing_node_left.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:4.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:4.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:4.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:3.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 2.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:4.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:4.routing_node_up.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:4.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:5.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:4.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:5.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:4.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:5.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 2.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:5.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:5.routing_node_right.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:5.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:5.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:5.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:4.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:5.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:5.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 2.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:4.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:4.routing_node_down.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:4.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:3.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:4.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:4.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:4.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:4.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 2.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:5.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:5.routing_node_left.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:5.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:5.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:5.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:4.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 2.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:5.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:5.routing_node_up.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:5.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:6.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:5.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:6.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:5.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:6.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 2.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:6.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:6.routing_node_right.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:6.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:6.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:6.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:5.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:6.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:6.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 2.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:5.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:5.routing_node_down.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:5.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:4.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:5.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:5.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:5.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:5.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 2.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:6.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:6.routing_node_left.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:6.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:6.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:6.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:5.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 2.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:6.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:6.routing_node_up.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:6.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:7.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:6.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:7.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:6.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:7.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 2.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:7.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:7.routing_node_right.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:7.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:7.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:7.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:6.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:7.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:7.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 2.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:6.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:6.routing_node_down.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:6.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:5.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:6.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:6.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:6.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:6.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 2.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:7.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:7.routing_node_left.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:7.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:7.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:7.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:6.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 2.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:7.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:7.routing_node_up.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:7.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:8.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:7.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:8.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 2.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:8.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:8.routing_node_right.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:8.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:8.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:8.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:7.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 2.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:7.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:7.routing_node_down.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:7.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:6.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:7.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:7.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:7.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:7.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 2.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:8.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:8.routing_node_left.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:8.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:7.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 2.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:1.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:1.routing_node_right.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:1.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:1.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 2.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:1.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:1.routing_node_left.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:1.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:1.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:1.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:1.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 2.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:1.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:1.routing_node_up.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:1.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:2.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:1.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:2.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 2.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:2.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:2.routing_node_right.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:2.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:1.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:2.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:2.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 2.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:1.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:1.routing_node_down.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:1.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:1.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 2.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:2.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:2.routing_node_left.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:2.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:2.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:2.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:2.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:2.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:1.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 2.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:2.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:2.routing_node_up.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:2.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:3.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:2.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:3.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 2.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:3.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:3.routing_node_right.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:3.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:2.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:3.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:3.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 2.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:2.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:2.routing_node_down.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:2.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:1.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:2.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:2.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 2.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:3.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:3.routing_node_left.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:3.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:3.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:3.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:3.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:3.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:2.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 2.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:3.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:3.routing_node_up.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:3.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:4.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:3.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:4.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 2.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:4.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:4.routing_node_right.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:4.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:3.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:4.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:4.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 2.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:3.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:3.routing_node_down.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:3.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:2.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:3.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:3.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 2.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:4.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:4.routing_node_left.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:4.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:4.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:4.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:4.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:4.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:3.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 2.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:4.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:4.routing_node_up.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:4.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:5.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:4.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:5.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 2.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:5.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:5.routing_node_right.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:5.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:4.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:5.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:5.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 2.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:4.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:4.routing_node_down.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:4.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:3.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:4.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:4.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 2.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:5.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:5.routing_node_left.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:5.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:5.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:5.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:5.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:5.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:4.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 2.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:5.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:5.routing_node_up.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:5.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:6.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:5.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:6.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 2.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:6.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:6.routing_node_right.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:6.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:5.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:6.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:6.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 2.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:5.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:5.routing_node_down.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:5.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:4.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:5.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:5.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 2.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:6.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:6.routing_node_left.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:6.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:6.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:6.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:6.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:6.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:5.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 2.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:6.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:6.routing_node_up.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:6.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:7.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:6.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:7.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 2.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:7.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:7.routing_node_right.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:7.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:6.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:7.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:7.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 2.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:6.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:6.routing_node_down.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:6.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:5.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:6.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:6.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 2.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:7.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:7.routing_node_left.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:7.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:7.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:7.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:7.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:7.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:6.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 2.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:7.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:7.routing_node_up.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:7.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:8.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 2.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:8.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:8.routing_node_right.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:8.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:7.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 2.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:7.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:7.routing_node_down.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:7.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:6.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:7.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:7.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 2.2 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:8.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:8.routing_node_left.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:8.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:8.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:8.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:7.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+
+# From IO to routing nodes constraints
+set_max_delay -ignore_clock_latency 2.0 -from [get_ports io_in*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.*_routing_network_x:1.*_routing_network_y:*.routing_node_*.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 5.0 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.*_routing_network_x:1.*_routing_network_y:*.routing_node_*.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_ports io_out*]
+set_max_delay -ignore_clock_latency 2.0 -from [get_ports io_in*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.*_routing_network_x:3.*_routing_network_y:*.routing_node_*.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 5.0 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.*_routing_network_x:3.*_routing_network_y:*.routing_node_*.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_ports io_out*]
+set_max_delay -ignore_clock_latency 2.0 -from [get_ports io_in*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.*_routing_network_x:*.*_routing_network_y:1.routing_node_*.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 5.0 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.*_routing_network_x:*.*_routing_network_y:1.routing_node_*.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_ports io_out*]
+set_max_delay -ignore_clock_latency 2.0 -from [get_ports io_in*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.*_routing_network_x:*.*_routing_network_y:8.routing_node_*.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 5.0 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.*_routing_network_x:*.*_routing_network_y:8.routing_node_*.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_ports io_out*]
+set_input_delay 0 -clock [get_clocks wb_clk_i] [get_ports wbs*_i]
diff --git a/openlane/user_project_wrapper/config.tcl b/openlane/user_project_wrapper/config.tcl
new file mode 100644
index 0000000..df19160
--- /dev/null
+++ b/openlane/user_project_wrapper/config.tcl
@@ -0,0 +1,83 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+
+# Base Configurations. Don't Touch
+# section begin
+
+set ::env(PDK) "gf180mcuC"
+set ::env(STD_CELL_LIBRARY) "gf180mcu_fd_sc_mcu7t5v0"
+
+# YOU CAN CHANGE ANY VARIABLES DEFINED IN THE DEFAULT WRAPPER CFGS BY OVERRIDING THEM IN THIS CONFIG.TCL
+source $::env(DESIGN_DIR)/fixed_dont_change/default_wrapper_cfgs.tcl
+
+set ::env(DESIGN_NAME) user_project_wrapper
+#section end
+
+# User Configurations
+
+## Source Verilog Files
+set ::env(VERILOG_FILES) "\
+ $::env(CARAVEL_ROOT)/verilog/rtl/defines.v \
+ $::env(DESIGN_DIR)/../../verilog/rtl/user_project_wrapper.v"
+
+## Clock configurations
+set ::env(CLOCK_PORT) "user_clock2"
+set ::env(CLOCK_NET) "mprj.clk"
+
+set ::env(CLOCK_PERIOD) "10"
+
+## Internal Macros
+### Macro PDN Connections
+set ::env(FP_PDN_MACRO_HOOKS) "\
+ mprj vdd vss vdd vss"
+
+### Macro Placement
+set ::env(MACRO_PLACEMENT_CFG) $::env(DESIGN_DIR)/macro.cfg
+
+### Black-box verilog and views
+set ::env(VERILOG_FILES_BLACKBOX) "\
+ $::env(CARAVEL_ROOT)/verilog/rtl/defines.v \
+ $::env(DESIGN_DIR)/../../verilog/rtl/user_proj_example.v"
+
+set ::env(EXTRA_LEFS) "\
+ $::env(DESIGN_DIR)/../../lef/user_proj_example.lef"
+
+set ::env(EXTRA_GDS_FILES) "\
+ $::env(DESIGN_DIR)/../../gds/user_proj_example.gds"
+
+set ::env(RT_MAX_LAYER) {Metal4}
+
+# disable pdn check nodes becuase it hangs with multiple power domains.
+# any issue with pdn connections will be flagged with LVS so it is not a critical check.
+set ::env(FP_PDN_CHECK_NODES) 0
+
+# The following is because there are no std cells in the example wrapper project.
+set ::env(SYNTH_ELABORATE_ONLY) 1
+set ::env(PL_RANDOM_GLB_PLACEMENT) 1
+
+set ::env(PL_RESIZER_DESIGN_OPTIMIZATIONS) 0
+set ::env(PL_RESIZER_TIMING_OPTIMIZATIONS) 0
+set ::env(PL_RESIZER_BUFFER_INPUT_PORTS) 0
+set ::env(PL_RESIZER_BUFFER_OUTPUT_PORTS) 0
+
+set ::env(FP_PDN_ENABLE_RAILS) 0
+
+set ::env(DIODE_INSERTION_STRATEGY) 0
+set ::env(RUN_FILL_INSERTION) 0
+set ::env(RUN_TAP_DECAP_INSERTION) 0
+set ::env(CLOCK_TREE_SYNTH) 0
+
+# YOU ARE NOT ALLOWED TO CHANGE ANY VARIABLES DEFINED IN THE FIXED WRAPPER CFGS
+source $::env(DESIGN_DIR)/fixed_dont_change/fixed_wrapper_cfgs.tcl
\ No newline at end of file
diff --git a/openlane/user_project_wrapper/fixed_dont_change/default_wrapper_cfgs.tcl b/openlane/user_project_wrapper/fixed_dont_change/default_wrapper_cfgs.tcl
new file mode 100644
index 0000000..66a5084
--- /dev/null
+++ b/openlane/user_project_wrapper/fixed_dont_change/default_wrapper_cfgs.tcl
@@ -0,0 +1,28 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+
+# THE FOLLOWING SECTIONS CAN BE CHANGED IF NEEDED
+
+# PDN Horizontal Pitch as mutliples of 30. Horizontal Pitch = 60 + FP_PDN_HPITCH_MULT * 30.
+# FP_PDN_HPITCH_MULT is an integer. Minimum value is 0.
+set ::env(FP_PDN_HPITCH_MULT) 1
+
+##
+# PDN Vertical Pitch. Can be changed to any value.
+set ::env(FP_PDN_VPITCH) 90
+
+##
+# PDN vertical Offset. Can be changed to any value.
+set ::env(FP_PDN_VOFFSET) 5
\ No newline at end of file
diff --git a/openlane/user_project_wrapper/fixed_dont_change/fixed_wrapper_cfgs.tcl b/openlane/user_project_wrapper/fixed_dont_change/fixed_wrapper_cfgs.tcl
new file mode 100644
index 0000000..636e68b
--- /dev/null
+++ b/openlane/user_project_wrapper/fixed_dont_change/fixed_wrapper_cfgs.tcl
@@ -0,0 +1,59 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+
+# DON'T TOUCH THE FOLLOWING SECTIONS
+
+# This makes sure that the core rings are outside the boundaries
+# of your block.
+set ::env(MAGIC_ZEROIZE_ORIGIN) 0
+
+# Area Configurations. DON'T TOUCH.
+set ::env(FP_SIZING) absolute
+set ::env(DIE_AREA) "0 0 2980.2 2980.2"
+set ::env(CORE_AREA) "12 12 2968.2 2968.2"
+
+set ::env(RUN_CVC) 0
+
+# Pin Configurations. DON'T TOUCH
+set ::env(FP_PIN_ORDER_CFG) $::env(DESIGN_DIR)/pin_order.cfg
+
+set ::unit 2.4
+set ::env(FP_IO_VEXTEND) [expr 2*$::unit]
+set ::env(FP_IO_HEXTEND) [expr 2*$::unit]
+set ::env(FP_IO_VLENGTH) $::unit
+set ::env(FP_IO_HLENGTH) $::unit
+
+set ::env(FP_IO_VTHICKNESS_MULT) 4
+set ::env(FP_IO_HTHICKNESS_MULT) 4
+
+# Power & Pin Configurations. DON'T TOUCH.
+set ::env(FP_PDN_CORE_RING) 1
+set ::env(FP_PDN_CORE_RING_VWIDTH) 3.1
+set ::env(FP_PDN_CORE_RING_HWIDTH) 3.1
+set ::env(FP_PDN_CORE_RING_VOFFSET) 14
+set ::env(FP_PDN_CORE_RING_HOFFSET) 16
+set ::env(FP_PDN_CORE_RING_VSPACING) 1.7
+set ::env(FP_PDN_CORE_RING_HSPACING) $::env(FP_PDN_CORE_RING_VSPACING)
+set ::env(FP_PDN_HOFFSET) 5
+set ::env(FP_PDN_HPITCH) [expr 60 + abs(int($::env(FP_PDN_HPITCH_MULT))) * 30]
+
+set ::env(FP_PDN_VWIDTH) 3.1
+set ::env(FP_PDN_HWIDTH) 3.1
+set ::env(FP_PDN_VSPACING) [expr 5*$::env(FP_PDN_CORE_RING_VWIDTH)]
+set ::env(FP_PDN_HSPACING) 26.9
+
+set ::env(VDD_NETS) [list {vdd}]
+set ::env(GND_NETS) [list {vss}]
+set ::env(SYNTH_USE_PG_PINS_DEFINES) "USE_POWER_PINS"
\ No newline at end of file
diff --git a/openlane/user_project_wrapper/fixed_dont_change/user_project_wrapper.def b/openlane/user_project_wrapper/fixed_dont_change/user_project_wrapper.def
new file mode 100644
index 0000000..0647d54
--- /dev/null
+++ b/openlane/user_project_wrapper/fixed_dont_change/user_project_wrapper.def
@@ -0,0 +1,7656 @@
+VERSION 5.8 ;
+DIVIDERCHAR "/" ;
+BUSBITCHARS "[]" ;
+DESIGN user_project_wrapper ;
+UNITS DISTANCE MICRONS 1000 ;
+DIEAREA ( 0 0 ) ( 2920000 3520000 ) ;
+ROW ROW_0 unithd 5520 10880 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1 unithd 5520 13600 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_2 unithd 5520 16320 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_3 unithd 5520 19040 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_4 unithd 5520 21760 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_5 unithd 5520 24480 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_6 unithd 5520 27200 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_7 unithd 5520 29920 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_8 unithd 5520 32640 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_9 unithd 5520 35360 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_10 unithd 5520 38080 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_11 unithd 5520 40800 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_12 unithd 5520 43520 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_13 unithd 5520 46240 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_14 unithd 5520 48960 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_15 unithd 5520 51680 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_16 unithd 5520 54400 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_17 unithd 5520 57120 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_18 unithd 5520 59840 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_19 unithd 5520 62560 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_20 unithd 5520 65280 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_21 unithd 5520 68000 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_22 unithd 5520 70720 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_23 unithd 5520 73440 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_24 unithd 5520 76160 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_25 unithd 5520 78880 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_26 unithd 5520 81600 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_27 unithd 5520 84320 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_28 unithd 5520 87040 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_29 unithd 5520 89760 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_30 unithd 5520 92480 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_31 unithd 5520 95200 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_32 unithd 5520 97920 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_33 unithd 5520 100640 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_34 unithd 5520 103360 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_35 unithd 5520 106080 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_36 unithd 5520 108800 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_37 unithd 5520 111520 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_38 unithd 5520 114240 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_39 unithd 5520 116960 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_40 unithd 5520 119680 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_41 unithd 5520 122400 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_42 unithd 5520 125120 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_43 unithd 5520 127840 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_44 unithd 5520 130560 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_45 unithd 5520 133280 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_46 unithd 5520 136000 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_47 unithd 5520 138720 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_48 unithd 5520 141440 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_49 unithd 5520 144160 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_50 unithd 5520 146880 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_51 unithd 5520 149600 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_52 unithd 5520 152320 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_53 unithd 5520 155040 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_54 unithd 5520 157760 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_55 unithd 5520 160480 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_56 unithd 5520 163200 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_57 unithd 5520 165920 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_58 unithd 5520 168640 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_59 unithd 5520 171360 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_60 unithd 5520 174080 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_61 unithd 5520 176800 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_62 unithd 5520 179520 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_63 unithd 5520 182240 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_64 unithd 5520 184960 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_65 unithd 5520 187680 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_66 unithd 5520 190400 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_67 unithd 5520 193120 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_68 unithd 5520 195840 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_69 unithd 5520 198560 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_70 unithd 5520 201280 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_71 unithd 5520 204000 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_72 unithd 5520 206720 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_73 unithd 5520 209440 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_74 unithd 5520 212160 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_75 unithd 5520 214880 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_76 unithd 5520 217600 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_77 unithd 5520 220320 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_78 unithd 5520 223040 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_79 unithd 5520 225760 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_80 unithd 5520 228480 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_81 unithd 5520 231200 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_82 unithd 5520 233920 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_83 unithd 5520 236640 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_84 unithd 5520 239360 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_85 unithd 5520 242080 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_86 unithd 5520 244800 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_87 unithd 5520 247520 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_88 unithd 5520 250240 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_89 unithd 5520 252960 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_90 unithd 5520 255680 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_91 unithd 5520 258400 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_92 unithd 5520 261120 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_93 unithd 5520 263840 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_94 unithd 5520 266560 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_95 unithd 5520 269280 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_96 unithd 5520 272000 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_97 unithd 5520 274720 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_98 unithd 5520 277440 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_99 unithd 5520 280160 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_100 unithd 5520 282880 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_101 unithd 5520 285600 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_102 unithd 5520 288320 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_103 unithd 5520 291040 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_104 unithd 5520 293760 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_105 unithd 5520 296480 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_106 unithd 5520 299200 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_107 unithd 5520 301920 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_108 unithd 5520 304640 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_109 unithd 5520 307360 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_110 unithd 5520 310080 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_111 unithd 5520 312800 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_112 unithd 5520 315520 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_113 unithd 5520 318240 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_114 unithd 5520 320960 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_115 unithd 5520 323680 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_116 unithd 5520 326400 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_117 unithd 5520 329120 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_118 unithd 5520 331840 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_119 unithd 5520 334560 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_120 unithd 5520 337280 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_121 unithd 5520 340000 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_122 unithd 5520 342720 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_123 unithd 5520 345440 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_124 unithd 5520 348160 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_125 unithd 5520 350880 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_126 unithd 5520 353600 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_127 unithd 5520 356320 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_128 unithd 5520 359040 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_129 unithd 5520 361760 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_130 unithd 5520 364480 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_131 unithd 5520 367200 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_132 unithd 5520 369920 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_133 unithd 5520 372640 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_134 unithd 5520 375360 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_135 unithd 5520 378080 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_136 unithd 5520 380800 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_137 unithd 5520 383520 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_138 unithd 5520 386240 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_139 unithd 5520 388960 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_140 unithd 5520 391680 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_141 unithd 5520 394400 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_142 unithd 5520 397120 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_143 unithd 5520 399840 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_144 unithd 5520 402560 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_145 unithd 5520 405280 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_146 unithd 5520 408000 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_147 unithd 5520 410720 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_148 unithd 5520 413440 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_149 unithd 5520 416160 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_150 unithd 5520 418880 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_151 unithd 5520 421600 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_152 unithd 5520 424320 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_153 unithd 5520 427040 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_154 unithd 5520 429760 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_155 unithd 5520 432480 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_156 unithd 5520 435200 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_157 unithd 5520 437920 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_158 unithd 5520 440640 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_159 unithd 5520 443360 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_160 unithd 5520 446080 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_161 unithd 5520 448800 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_162 unithd 5520 451520 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_163 unithd 5520 454240 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_164 unithd 5520 456960 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_165 unithd 5520 459680 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_166 unithd 5520 462400 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_167 unithd 5520 465120 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_168 unithd 5520 467840 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_169 unithd 5520 470560 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_170 unithd 5520 473280 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_171 unithd 5520 476000 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_172 unithd 5520 478720 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_173 unithd 5520 481440 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_174 unithd 5520 484160 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_175 unithd 5520 486880 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_176 unithd 5520 489600 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_177 unithd 5520 492320 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_178 unithd 5520 495040 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_179 unithd 5520 497760 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_180 unithd 5520 500480 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_181 unithd 5520 503200 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_182 unithd 5520 505920 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_183 unithd 5520 508640 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_184 unithd 5520 511360 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_185 unithd 5520 514080 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_186 unithd 5520 516800 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_187 unithd 5520 519520 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_188 unithd 5520 522240 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_189 unithd 5520 524960 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_190 unithd 5520 527680 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_191 unithd 5520 530400 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_192 unithd 5520 533120 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_193 unithd 5520 535840 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_194 unithd 5520 538560 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_195 unithd 5520 541280 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_196 unithd 5520 544000 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_197 unithd 5520 546720 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_198 unithd 5520 549440 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_199 unithd 5520 552160 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_200 unithd 5520 554880 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_201 unithd 5520 557600 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_202 unithd 5520 560320 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_203 unithd 5520 563040 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_204 unithd 5520 565760 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_205 unithd 5520 568480 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_206 unithd 5520 571200 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_207 unithd 5520 573920 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_208 unithd 5520 576640 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_209 unithd 5520 579360 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_210 unithd 5520 582080 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_211 unithd 5520 584800 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_212 unithd 5520 587520 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_213 unithd 5520 590240 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_214 unithd 5520 592960 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_215 unithd 5520 595680 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_216 unithd 5520 598400 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_217 unithd 5520 601120 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_218 unithd 5520 603840 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_219 unithd 5520 606560 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_220 unithd 5520 609280 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_221 unithd 5520 612000 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_222 unithd 5520 614720 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_223 unithd 5520 617440 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_224 unithd 5520 620160 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_225 unithd 5520 622880 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_226 unithd 5520 625600 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_227 unithd 5520 628320 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_228 unithd 5520 631040 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_229 unithd 5520 633760 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_230 unithd 5520 636480 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_231 unithd 5520 639200 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_232 unithd 5520 641920 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_233 unithd 5520 644640 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_234 unithd 5520 647360 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_235 unithd 5520 650080 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_236 unithd 5520 652800 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_237 unithd 5520 655520 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_238 unithd 5520 658240 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_239 unithd 5520 660960 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_240 unithd 5520 663680 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_241 unithd 5520 666400 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_242 unithd 5520 669120 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_243 unithd 5520 671840 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_244 unithd 5520 674560 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_245 unithd 5520 677280 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_246 unithd 5520 680000 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_247 unithd 5520 682720 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_248 unithd 5520 685440 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_249 unithd 5520 688160 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_250 unithd 5520 690880 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_251 unithd 5520 693600 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_252 unithd 5520 696320 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_253 unithd 5520 699040 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_254 unithd 5520 701760 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_255 unithd 5520 704480 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_256 unithd 5520 707200 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_257 unithd 5520 709920 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_258 unithd 5520 712640 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_259 unithd 5520 715360 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_260 unithd 5520 718080 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_261 unithd 5520 720800 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_262 unithd 5520 723520 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_263 unithd 5520 726240 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_264 unithd 5520 728960 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_265 unithd 5520 731680 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_266 unithd 5520 734400 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_267 unithd 5520 737120 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_268 unithd 5520 739840 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_269 unithd 5520 742560 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_270 unithd 5520 745280 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_271 unithd 5520 748000 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_272 unithd 5520 750720 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_273 unithd 5520 753440 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_274 unithd 5520 756160 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_275 unithd 5520 758880 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_276 unithd 5520 761600 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_277 unithd 5520 764320 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_278 unithd 5520 767040 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_279 unithd 5520 769760 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_280 unithd 5520 772480 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_281 unithd 5520 775200 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_282 unithd 5520 777920 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_283 unithd 5520 780640 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_284 unithd 5520 783360 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_285 unithd 5520 786080 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_286 unithd 5520 788800 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_287 unithd 5520 791520 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_288 unithd 5520 794240 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_289 unithd 5520 796960 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_290 unithd 5520 799680 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_291 unithd 5520 802400 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_292 unithd 5520 805120 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_293 unithd 5520 807840 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_294 unithd 5520 810560 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_295 unithd 5520 813280 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_296 unithd 5520 816000 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_297 unithd 5520 818720 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_298 unithd 5520 821440 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_299 unithd 5520 824160 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_300 unithd 5520 826880 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_301 unithd 5520 829600 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_302 unithd 5520 832320 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_303 unithd 5520 835040 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_304 unithd 5520 837760 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_305 unithd 5520 840480 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_306 unithd 5520 843200 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_307 unithd 5520 845920 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_308 unithd 5520 848640 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_309 unithd 5520 851360 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_310 unithd 5520 854080 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_311 unithd 5520 856800 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_312 unithd 5520 859520 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_313 unithd 5520 862240 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_314 unithd 5520 864960 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_315 unithd 5520 867680 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_316 unithd 5520 870400 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_317 unithd 5520 873120 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_318 unithd 5520 875840 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_319 unithd 5520 878560 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_320 unithd 5520 881280 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_321 unithd 5520 884000 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_322 unithd 5520 886720 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_323 unithd 5520 889440 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_324 unithd 5520 892160 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_325 unithd 5520 894880 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_326 unithd 5520 897600 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_327 unithd 5520 900320 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_328 unithd 5520 903040 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_329 unithd 5520 905760 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_330 unithd 5520 908480 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_331 unithd 5520 911200 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_332 unithd 5520 913920 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_333 unithd 5520 916640 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_334 unithd 5520 919360 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_335 unithd 5520 922080 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_336 unithd 5520 924800 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_337 unithd 5520 927520 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_338 unithd 5520 930240 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_339 unithd 5520 932960 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_340 unithd 5520 935680 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_341 unithd 5520 938400 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_342 unithd 5520 941120 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_343 unithd 5520 943840 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_344 unithd 5520 946560 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_345 unithd 5520 949280 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_346 unithd 5520 952000 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_347 unithd 5520 954720 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_348 unithd 5520 957440 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_349 unithd 5520 960160 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_350 unithd 5520 962880 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_351 unithd 5520 965600 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_352 unithd 5520 968320 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_353 unithd 5520 971040 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_354 unithd 5520 973760 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_355 unithd 5520 976480 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_356 unithd 5520 979200 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_357 unithd 5520 981920 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_358 unithd 5520 984640 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_359 unithd 5520 987360 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_360 unithd 5520 990080 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_361 unithd 5520 992800 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_362 unithd 5520 995520 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_363 unithd 5520 998240 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_364 unithd 5520 1000960 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_365 unithd 5520 1003680 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_366 unithd 5520 1006400 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_367 unithd 5520 1009120 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_368 unithd 5520 1011840 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_369 unithd 5520 1014560 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_370 unithd 5520 1017280 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_371 unithd 5520 1020000 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_372 unithd 5520 1022720 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_373 unithd 5520 1025440 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_374 unithd 5520 1028160 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_375 unithd 5520 1030880 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_376 unithd 5520 1033600 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_377 unithd 5520 1036320 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_378 unithd 5520 1039040 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_379 unithd 5520 1041760 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_380 unithd 5520 1044480 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_381 unithd 5520 1047200 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_382 unithd 5520 1049920 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_383 unithd 5520 1052640 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_384 unithd 5520 1055360 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_385 unithd 5520 1058080 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_386 unithd 5520 1060800 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_387 unithd 5520 1063520 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_388 unithd 5520 1066240 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_389 unithd 5520 1068960 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_390 unithd 5520 1071680 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_391 unithd 5520 1074400 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_392 unithd 5520 1077120 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_393 unithd 5520 1079840 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_394 unithd 5520 1082560 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_395 unithd 5520 1085280 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_396 unithd 5520 1088000 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_397 unithd 5520 1090720 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_398 unithd 5520 1093440 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_399 unithd 5520 1096160 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_400 unithd 5520 1098880 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_401 unithd 5520 1101600 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_402 unithd 5520 1104320 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_403 unithd 5520 1107040 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_404 unithd 5520 1109760 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_405 unithd 5520 1112480 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_406 unithd 5520 1115200 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_407 unithd 5520 1117920 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_408 unithd 5520 1120640 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_409 unithd 5520 1123360 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_410 unithd 5520 1126080 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_411 unithd 5520 1128800 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_412 unithd 5520 1131520 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_413 unithd 5520 1134240 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_414 unithd 5520 1136960 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_415 unithd 5520 1139680 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_416 unithd 5520 1142400 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_417 unithd 5520 1145120 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_418 unithd 5520 1147840 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_419 unithd 5520 1150560 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_420 unithd 5520 1153280 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_421 unithd 5520 1156000 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_422 unithd 5520 1158720 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_423 unithd 5520 1161440 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_424 unithd 5520 1164160 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_425 unithd 5520 1166880 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_426 unithd 5520 1169600 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_427 unithd 5520 1172320 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_428 unithd 5520 1175040 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_429 unithd 5520 1177760 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_430 unithd 5520 1180480 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_431 unithd 5520 1183200 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_432 unithd 5520 1185920 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_433 unithd 5520 1188640 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_434 unithd 5520 1191360 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_435 unithd 5520 1194080 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_436 unithd 5520 1196800 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_437 unithd 5520 1199520 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_438 unithd 5520 1202240 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_439 unithd 5520 1204960 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_440 unithd 5520 1207680 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_441 unithd 5520 1210400 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_442 unithd 5520 1213120 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_443 unithd 5520 1215840 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_444 unithd 5520 1218560 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_445 unithd 5520 1221280 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_446 unithd 5520 1224000 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_447 unithd 5520 1226720 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_448 unithd 5520 1229440 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_449 unithd 5520 1232160 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_450 unithd 5520 1234880 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_451 unithd 5520 1237600 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_452 unithd 5520 1240320 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_453 unithd 5520 1243040 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_454 unithd 5520 1245760 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_455 unithd 5520 1248480 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_456 unithd 5520 1251200 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_457 unithd 5520 1253920 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_458 unithd 5520 1256640 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_459 unithd 5520 1259360 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_460 unithd 5520 1262080 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_461 unithd 5520 1264800 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_462 unithd 5520 1267520 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_463 unithd 5520 1270240 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_464 unithd 5520 1272960 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_465 unithd 5520 1275680 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_466 unithd 5520 1278400 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_467 unithd 5520 1281120 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_468 unithd 5520 1283840 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_469 unithd 5520 1286560 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_470 unithd 5520 1289280 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_471 unithd 5520 1292000 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_472 unithd 5520 1294720 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_473 unithd 5520 1297440 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_474 unithd 5520 1300160 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_475 unithd 5520 1302880 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_476 unithd 5520 1305600 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_477 unithd 5520 1308320 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_478 unithd 5520 1311040 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_479 unithd 5520 1313760 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_480 unithd 5520 1316480 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_481 unithd 5520 1319200 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_482 unithd 5520 1321920 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_483 unithd 5520 1324640 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_484 unithd 5520 1327360 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_485 unithd 5520 1330080 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_486 unithd 5520 1332800 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_487 unithd 5520 1335520 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_488 unithd 5520 1338240 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_489 unithd 5520 1340960 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_490 unithd 5520 1343680 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_491 unithd 5520 1346400 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_492 unithd 5520 1349120 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_493 unithd 5520 1351840 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_494 unithd 5520 1354560 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_495 unithd 5520 1357280 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_496 unithd 5520 1360000 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_497 unithd 5520 1362720 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_498 unithd 5520 1365440 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_499 unithd 5520 1368160 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_500 unithd 5520 1370880 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_501 unithd 5520 1373600 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_502 unithd 5520 1376320 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_503 unithd 5520 1379040 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_504 unithd 5520 1381760 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_505 unithd 5520 1384480 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_506 unithd 5520 1387200 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_507 unithd 5520 1389920 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_508 unithd 5520 1392640 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_509 unithd 5520 1395360 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_510 unithd 5520 1398080 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_511 unithd 5520 1400800 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_512 unithd 5520 1403520 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_513 unithd 5520 1406240 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_514 unithd 5520 1408960 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_515 unithd 5520 1411680 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_516 unithd 5520 1414400 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_517 unithd 5520 1417120 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_518 unithd 5520 1419840 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_519 unithd 5520 1422560 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_520 unithd 5520 1425280 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_521 unithd 5520 1428000 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_522 unithd 5520 1430720 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_523 unithd 5520 1433440 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_524 unithd 5520 1436160 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_525 unithd 5520 1438880 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_526 unithd 5520 1441600 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_527 unithd 5520 1444320 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_528 unithd 5520 1447040 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_529 unithd 5520 1449760 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_530 unithd 5520 1452480 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_531 unithd 5520 1455200 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_532 unithd 5520 1457920 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_533 unithd 5520 1460640 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_534 unithd 5520 1463360 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_535 unithd 5520 1466080 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_536 unithd 5520 1468800 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_537 unithd 5520 1471520 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_538 unithd 5520 1474240 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_539 unithd 5520 1476960 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_540 unithd 5520 1479680 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_541 unithd 5520 1482400 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_542 unithd 5520 1485120 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_543 unithd 5520 1487840 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_544 unithd 5520 1490560 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_545 unithd 5520 1493280 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_546 unithd 5520 1496000 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_547 unithd 5520 1498720 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_548 unithd 5520 1501440 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_549 unithd 5520 1504160 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_550 unithd 5520 1506880 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_551 unithd 5520 1509600 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_552 unithd 5520 1512320 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_553 unithd 5520 1515040 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_554 unithd 5520 1517760 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_555 unithd 5520 1520480 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_556 unithd 5520 1523200 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_557 unithd 5520 1525920 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_558 unithd 5520 1528640 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_559 unithd 5520 1531360 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_560 unithd 5520 1534080 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_561 unithd 5520 1536800 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_562 unithd 5520 1539520 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_563 unithd 5520 1542240 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_564 unithd 5520 1544960 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_565 unithd 5520 1547680 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_566 unithd 5520 1550400 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_567 unithd 5520 1553120 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_568 unithd 5520 1555840 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_569 unithd 5520 1558560 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_570 unithd 5520 1561280 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_571 unithd 5520 1564000 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_572 unithd 5520 1566720 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_573 unithd 5520 1569440 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_574 unithd 5520 1572160 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_575 unithd 5520 1574880 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_576 unithd 5520 1577600 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_577 unithd 5520 1580320 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_578 unithd 5520 1583040 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_579 unithd 5520 1585760 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_580 unithd 5520 1588480 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_581 unithd 5520 1591200 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_582 unithd 5520 1593920 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_583 unithd 5520 1596640 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_584 unithd 5520 1599360 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_585 unithd 5520 1602080 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_586 unithd 5520 1604800 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_587 unithd 5520 1607520 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_588 unithd 5520 1610240 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_589 unithd 5520 1612960 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_590 unithd 5520 1615680 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_591 unithd 5520 1618400 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_592 unithd 5520 1621120 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_593 unithd 5520 1623840 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_594 unithd 5520 1626560 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_595 unithd 5520 1629280 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_596 unithd 5520 1632000 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_597 unithd 5520 1634720 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_598 unithd 5520 1637440 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_599 unithd 5520 1640160 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_600 unithd 5520 1642880 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_601 unithd 5520 1645600 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_602 unithd 5520 1648320 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_603 unithd 5520 1651040 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_604 unithd 5520 1653760 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_605 unithd 5520 1656480 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_606 unithd 5520 1659200 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_607 unithd 5520 1661920 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_608 unithd 5520 1664640 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_609 unithd 5520 1667360 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_610 unithd 5520 1670080 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_611 unithd 5520 1672800 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_612 unithd 5520 1675520 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_613 unithd 5520 1678240 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_614 unithd 5520 1680960 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_615 unithd 5520 1683680 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_616 unithd 5520 1686400 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_617 unithd 5520 1689120 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_618 unithd 5520 1691840 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_619 unithd 5520 1694560 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_620 unithd 5520 1697280 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_621 unithd 5520 1700000 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_622 unithd 5520 1702720 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_623 unithd 5520 1705440 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_624 unithd 5520 1708160 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_625 unithd 5520 1710880 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_626 unithd 5520 1713600 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_627 unithd 5520 1716320 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_628 unithd 5520 1719040 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_629 unithd 5520 1721760 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_630 unithd 5520 1724480 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_631 unithd 5520 1727200 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_632 unithd 5520 1729920 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_633 unithd 5520 1732640 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_634 unithd 5520 1735360 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_635 unithd 5520 1738080 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_636 unithd 5520 1740800 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_637 unithd 5520 1743520 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_638 unithd 5520 1746240 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_639 unithd 5520 1748960 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_640 unithd 5520 1751680 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_641 unithd 5520 1754400 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_642 unithd 5520 1757120 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_643 unithd 5520 1759840 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_644 unithd 5520 1762560 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_645 unithd 5520 1765280 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_646 unithd 5520 1768000 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_647 unithd 5520 1770720 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_648 unithd 5520 1773440 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_649 unithd 5520 1776160 FS DO 6323 BY 1 STEP 460 0 ;
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+ROW ROW_653 unithd 5520 1787040 FS DO 6323 BY 1 STEP 460 0 ;
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+ROW ROW_667 unithd 5520 1825120 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_668 unithd 5520 1827840 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_669 unithd 5520 1830560 FS DO 6323 BY 1 STEP 460 0 ;
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+ROW ROW_673 unithd 5520 1841440 FS DO 6323 BY 1 STEP 460 0 ;
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+ROW ROW_712 unithd 5520 1947520 N DO 6323 BY 1 STEP 460 0 ;
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+ROW ROW_714 unithd 5520 1952960 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_715 unithd 5520 1955680 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_716 unithd 5520 1958400 N DO 6323 BY 1 STEP 460 0 ;
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+ROW ROW_720 unithd 5520 1969280 N DO 6323 BY 1 STEP 460 0 ;
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+ROW ROW_722 unithd 5520 1974720 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_723 unithd 5520 1977440 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_724 unithd 5520 1980160 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_725 unithd 5520 1982880 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_726 unithd 5520 1985600 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_727 unithd 5520 1988320 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_728 unithd 5520 1991040 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_729 unithd 5520 1993760 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_730 unithd 5520 1996480 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_731 unithd 5520 1999200 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_732 unithd 5520 2001920 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_733 unithd 5520 2004640 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_734 unithd 5520 2007360 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_735 unithd 5520 2010080 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_736 unithd 5520 2012800 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_737 unithd 5520 2015520 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_738 unithd 5520 2018240 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_739 unithd 5520 2020960 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_740 unithd 5520 2023680 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_741 unithd 5520 2026400 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_742 unithd 5520 2029120 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_743 unithd 5520 2031840 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_744 unithd 5520 2034560 N DO 6323 BY 1 STEP 460 0 ;
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+ROW ROW_746 unithd 5520 2040000 N DO 6323 BY 1 STEP 460 0 ;
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+ROW ROW_748 unithd 5520 2045440 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_749 unithd 5520 2048160 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_750 unithd 5520 2050880 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_751 unithd 5520 2053600 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_752 unithd 5520 2056320 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_753 unithd 5520 2059040 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_754 unithd 5520 2061760 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_755 unithd 5520 2064480 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_756 unithd 5520 2067200 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_757 unithd 5520 2069920 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_758 unithd 5520 2072640 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_759 unithd 5520 2075360 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_760 unithd 5520 2078080 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_761 unithd 5520 2080800 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_762 unithd 5520 2083520 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_763 unithd 5520 2086240 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_764 unithd 5520 2088960 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_765 unithd 5520 2091680 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_766 unithd 5520 2094400 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_767 unithd 5520 2097120 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_768 unithd 5520 2099840 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_769 unithd 5520 2102560 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_770 unithd 5520 2105280 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_771 unithd 5520 2108000 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_772 unithd 5520 2110720 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_773 unithd 5520 2113440 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_774 unithd 5520 2116160 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_775 unithd 5520 2118880 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_776 unithd 5520 2121600 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_777 unithd 5520 2124320 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_778 unithd 5520 2127040 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_779 unithd 5520 2129760 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_780 unithd 5520 2132480 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_781 unithd 5520 2135200 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_782 unithd 5520 2137920 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_783 unithd 5520 2140640 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_784 unithd 5520 2143360 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_785 unithd 5520 2146080 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_786 unithd 5520 2148800 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_787 unithd 5520 2151520 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_788 unithd 5520 2154240 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_789 unithd 5520 2156960 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_790 unithd 5520 2159680 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_791 unithd 5520 2162400 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_792 unithd 5520 2165120 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_793 unithd 5520 2167840 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_794 unithd 5520 2170560 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_795 unithd 5520 2173280 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_796 unithd 5520 2176000 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_797 unithd 5520 2178720 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_798 unithd 5520 2181440 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_799 unithd 5520 2184160 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_800 unithd 5520 2186880 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_801 unithd 5520 2189600 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_802 unithd 5520 2192320 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_803 unithd 5520 2195040 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_804 unithd 5520 2197760 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_805 unithd 5520 2200480 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_806 unithd 5520 2203200 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_807 unithd 5520 2205920 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_808 unithd 5520 2208640 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_809 unithd 5520 2211360 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_810 unithd 5520 2214080 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_811 unithd 5520 2216800 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_812 unithd 5520 2219520 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_813 unithd 5520 2222240 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_814 unithd 5520 2224960 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_815 unithd 5520 2227680 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_816 unithd 5520 2230400 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_817 unithd 5520 2233120 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_818 unithd 5520 2235840 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_819 unithd 5520 2238560 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_820 unithd 5520 2241280 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_821 unithd 5520 2244000 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_822 unithd 5520 2246720 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_823 unithd 5520 2249440 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_824 unithd 5520 2252160 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_825 unithd 5520 2254880 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_826 unithd 5520 2257600 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_827 unithd 5520 2260320 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_828 unithd 5520 2263040 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_829 unithd 5520 2265760 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_830 unithd 5520 2268480 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_831 unithd 5520 2271200 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_832 unithd 5520 2273920 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_833 unithd 5520 2276640 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_834 unithd 5520 2279360 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_835 unithd 5520 2282080 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_836 unithd 5520 2284800 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_837 unithd 5520 2287520 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_838 unithd 5520 2290240 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_839 unithd 5520 2292960 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_840 unithd 5520 2295680 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_841 unithd 5520 2298400 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_842 unithd 5520 2301120 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_843 unithd 5520 2303840 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_844 unithd 5520 2306560 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_845 unithd 5520 2309280 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_846 unithd 5520 2312000 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_847 unithd 5520 2314720 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_848 unithd 5520 2317440 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_849 unithd 5520 2320160 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_850 unithd 5520 2322880 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_851 unithd 5520 2325600 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_852 unithd 5520 2328320 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_853 unithd 5520 2331040 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_854 unithd 5520 2333760 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_855 unithd 5520 2336480 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_856 unithd 5520 2339200 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_857 unithd 5520 2341920 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_858 unithd 5520 2344640 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_859 unithd 5520 2347360 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_860 unithd 5520 2350080 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_861 unithd 5520 2352800 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_862 unithd 5520 2355520 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_863 unithd 5520 2358240 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_864 unithd 5520 2360960 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_865 unithd 5520 2363680 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_866 unithd 5520 2366400 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_867 unithd 5520 2369120 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_868 unithd 5520 2371840 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_869 unithd 5520 2374560 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_870 unithd 5520 2377280 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_871 unithd 5520 2380000 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_872 unithd 5520 2382720 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_873 unithd 5520 2385440 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_874 unithd 5520 2388160 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_875 unithd 5520 2390880 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_876 unithd 5520 2393600 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_877 unithd 5520 2396320 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_878 unithd 5520 2399040 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_879 unithd 5520 2401760 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_880 unithd 5520 2404480 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_881 unithd 5520 2407200 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_882 unithd 5520 2409920 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_883 unithd 5520 2412640 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_884 unithd 5520 2415360 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_885 unithd 5520 2418080 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_886 unithd 5520 2420800 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_887 unithd 5520 2423520 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_888 unithd 5520 2426240 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_889 unithd 5520 2428960 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_890 unithd 5520 2431680 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_891 unithd 5520 2434400 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_892 unithd 5520 2437120 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_893 unithd 5520 2439840 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_894 unithd 5520 2442560 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_895 unithd 5520 2445280 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_896 unithd 5520 2448000 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_897 unithd 5520 2450720 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_898 unithd 5520 2453440 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_899 unithd 5520 2456160 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_900 unithd 5520 2458880 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_901 unithd 5520 2461600 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_902 unithd 5520 2464320 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_903 unithd 5520 2467040 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_904 unithd 5520 2469760 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_905 unithd 5520 2472480 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_906 unithd 5520 2475200 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_907 unithd 5520 2477920 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_908 unithd 5520 2480640 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_909 unithd 5520 2483360 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_910 unithd 5520 2486080 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_911 unithd 5520 2488800 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_912 unithd 5520 2491520 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_913 unithd 5520 2494240 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_914 unithd 5520 2496960 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_915 unithd 5520 2499680 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_916 unithd 5520 2502400 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_917 unithd 5520 2505120 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_918 unithd 5520 2507840 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_919 unithd 5520 2510560 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_920 unithd 5520 2513280 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_921 unithd 5520 2516000 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_922 unithd 5520 2518720 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_923 unithd 5520 2521440 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_924 unithd 5520 2524160 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_925 unithd 5520 2526880 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_926 unithd 5520 2529600 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_927 unithd 5520 2532320 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_928 unithd 5520 2535040 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_929 unithd 5520 2537760 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_930 unithd 5520 2540480 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_931 unithd 5520 2543200 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_932 unithd 5520 2545920 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_933 unithd 5520 2548640 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_934 unithd 5520 2551360 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_935 unithd 5520 2554080 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_936 unithd 5520 2556800 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_937 unithd 5520 2559520 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_938 unithd 5520 2562240 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_939 unithd 5520 2564960 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_940 unithd 5520 2567680 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_941 unithd 5520 2570400 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_942 unithd 5520 2573120 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_943 unithd 5520 2575840 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_944 unithd 5520 2578560 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_945 unithd 5520 2581280 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_946 unithd 5520 2584000 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_947 unithd 5520 2586720 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_948 unithd 5520 2589440 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_949 unithd 5520 2592160 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_950 unithd 5520 2594880 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_951 unithd 5520 2597600 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_952 unithd 5520 2600320 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_953 unithd 5520 2603040 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_954 unithd 5520 2605760 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_955 unithd 5520 2608480 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_956 unithd 5520 2611200 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_957 unithd 5520 2613920 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_958 unithd 5520 2616640 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_959 unithd 5520 2619360 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_960 unithd 5520 2622080 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_961 unithd 5520 2624800 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_962 unithd 5520 2627520 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_963 unithd 5520 2630240 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_964 unithd 5520 2632960 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_965 unithd 5520 2635680 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_966 unithd 5520 2638400 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_967 unithd 5520 2641120 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_968 unithd 5520 2643840 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_969 unithd 5520 2646560 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_970 unithd 5520 2649280 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_971 unithd 5520 2652000 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_972 unithd 5520 2654720 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_973 unithd 5520 2657440 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_974 unithd 5520 2660160 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_975 unithd 5520 2662880 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_976 unithd 5520 2665600 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_977 unithd 5520 2668320 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_978 unithd 5520 2671040 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_979 unithd 5520 2673760 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_980 unithd 5520 2676480 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_981 unithd 5520 2679200 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_982 unithd 5520 2681920 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_983 unithd 5520 2684640 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_984 unithd 5520 2687360 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_985 unithd 5520 2690080 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_986 unithd 5520 2692800 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_987 unithd 5520 2695520 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_988 unithd 5520 2698240 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_989 unithd 5520 2700960 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_990 unithd 5520 2703680 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_991 unithd 5520 2706400 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_992 unithd 5520 2709120 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_993 unithd 5520 2711840 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_994 unithd 5520 2714560 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_995 unithd 5520 2717280 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_996 unithd 5520 2720000 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_997 unithd 5520 2722720 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_998 unithd 5520 2725440 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_999 unithd 5520 2728160 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1000 unithd 5520 2730880 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1001 unithd 5520 2733600 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1002 unithd 5520 2736320 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1003 unithd 5520 2739040 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1004 unithd 5520 2741760 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1005 unithd 5520 2744480 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1006 unithd 5520 2747200 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1007 unithd 5520 2749920 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1008 unithd 5520 2752640 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1009 unithd 5520 2755360 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1010 unithd 5520 2758080 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1011 unithd 5520 2760800 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1012 unithd 5520 2763520 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1013 unithd 5520 2766240 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1014 unithd 5520 2768960 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1015 unithd 5520 2771680 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1016 unithd 5520 2774400 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1017 unithd 5520 2777120 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1018 unithd 5520 2779840 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1019 unithd 5520 2782560 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1020 unithd 5520 2785280 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1021 unithd 5520 2788000 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1022 unithd 5520 2790720 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1023 unithd 5520 2793440 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1024 unithd 5520 2796160 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1025 unithd 5520 2798880 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1026 unithd 5520 2801600 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1027 unithd 5520 2804320 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1028 unithd 5520 2807040 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1029 unithd 5520 2809760 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1030 unithd 5520 2812480 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1031 unithd 5520 2815200 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1032 unithd 5520 2817920 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1033 unithd 5520 2820640 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1034 unithd 5520 2823360 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1035 unithd 5520 2826080 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1036 unithd 5520 2828800 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1037 unithd 5520 2831520 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1038 unithd 5520 2834240 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1039 unithd 5520 2836960 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1040 unithd 5520 2839680 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1041 unithd 5520 2842400 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1042 unithd 5520 2845120 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1043 unithd 5520 2847840 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1044 unithd 5520 2850560 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1045 unithd 5520 2853280 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1046 unithd 5520 2856000 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1047 unithd 5520 2858720 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1048 unithd 5520 2861440 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1049 unithd 5520 2864160 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1050 unithd 5520 2866880 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1051 unithd 5520 2869600 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1052 unithd 5520 2872320 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1053 unithd 5520 2875040 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1054 unithd 5520 2877760 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1055 unithd 5520 2880480 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1056 unithd 5520 2883200 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1057 unithd 5520 2885920 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1058 unithd 5520 2888640 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1059 unithd 5520 2891360 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1060 unithd 5520 2894080 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1061 unithd 5520 2896800 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1062 unithd 5520 2899520 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1063 unithd 5520 2902240 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1064 unithd 5520 2904960 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1065 unithd 5520 2907680 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1066 unithd 5520 2910400 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1067 unithd 5520 2913120 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1068 unithd 5520 2915840 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1069 unithd 5520 2918560 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1070 unithd 5520 2921280 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1071 unithd 5520 2924000 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1072 unithd 5520 2926720 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1073 unithd 5520 2929440 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1074 unithd 5520 2932160 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1075 unithd 5520 2934880 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1076 unithd 5520 2937600 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1077 unithd 5520 2940320 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1078 unithd 5520 2943040 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1079 unithd 5520 2945760 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1080 unithd 5520 2948480 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1081 unithd 5520 2951200 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1082 unithd 5520 2953920 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1083 unithd 5520 2956640 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1084 unithd 5520 2959360 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1085 unithd 5520 2962080 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1086 unithd 5520 2964800 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1087 unithd 5520 2967520 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1088 unithd 5520 2970240 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1089 unithd 5520 2972960 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1090 unithd 5520 2975680 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1091 unithd 5520 2978400 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1092 unithd 5520 2981120 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1093 unithd 5520 2983840 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1094 unithd 5520 2986560 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1095 unithd 5520 2989280 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1096 unithd 5520 2992000 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1097 unithd 5520 2994720 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1098 unithd 5520 2997440 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1099 unithd 5520 3000160 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1100 unithd 5520 3002880 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1101 unithd 5520 3005600 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1102 unithd 5520 3008320 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1103 unithd 5520 3011040 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1104 unithd 5520 3013760 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1105 unithd 5520 3016480 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1106 unithd 5520 3019200 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1107 unithd 5520 3021920 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1108 unithd 5520 3024640 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1109 unithd 5520 3027360 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1110 unithd 5520 3030080 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1111 unithd 5520 3032800 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1112 unithd 5520 3035520 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1113 unithd 5520 3038240 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1114 unithd 5520 3040960 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1115 unithd 5520 3043680 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1116 unithd 5520 3046400 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1117 unithd 5520 3049120 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1118 unithd 5520 3051840 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1119 unithd 5520 3054560 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1120 unithd 5520 3057280 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1121 unithd 5520 3060000 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1122 unithd 5520 3062720 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1123 unithd 5520 3065440 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1124 unithd 5520 3068160 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1125 unithd 5520 3070880 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1126 unithd 5520 3073600 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1127 unithd 5520 3076320 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1128 unithd 5520 3079040 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1129 unithd 5520 3081760 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1130 unithd 5520 3084480 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1131 unithd 5520 3087200 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1132 unithd 5520 3089920 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1133 unithd 5520 3092640 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1134 unithd 5520 3095360 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1135 unithd 5520 3098080 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1136 unithd 5520 3100800 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1137 unithd 5520 3103520 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1138 unithd 5520 3106240 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1139 unithd 5520 3108960 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1140 unithd 5520 3111680 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1141 unithd 5520 3114400 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1142 unithd 5520 3117120 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1143 unithd 5520 3119840 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1144 unithd 5520 3122560 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1145 unithd 5520 3125280 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1146 unithd 5520 3128000 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1147 unithd 5520 3130720 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1148 unithd 5520 3133440 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1149 unithd 5520 3136160 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1150 unithd 5520 3138880 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1151 unithd 5520 3141600 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1152 unithd 5520 3144320 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1153 unithd 5520 3147040 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1154 unithd 5520 3149760 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1155 unithd 5520 3152480 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1156 unithd 5520 3155200 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1157 unithd 5520 3157920 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1158 unithd 5520 3160640 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1159 unithd 5520 3163360 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1160 unithd 5520 3166080 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1161 unithd 5520 3168800 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1162 unithd 5520 3171520 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1163 unithd 5520 3174240 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1164 unithd 5520 3176960 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1165 unithd 5520 3179680 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1166 unithd 5520 3182400 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1167 unithd 5520 3185120 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1168 unithd 5520 3187840 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1169 unithd 5520 3190560 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1170 unithd 5520 3193280 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1171 unithd 5520 3196000 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1172 unithd 5520 3198720 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1173 unithd 5520 3201440 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1174 unithd 5520 3204160 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1175 unithd 5520 3206880 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1176 unithd 5520 3209600 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1177 unithd 5520 3212320 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1178 unithd 5520 3215040 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1179 unithd 5520 3217760 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1180 unithd 5520 3220480 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1181 unithd 5520 3223200 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1182 unithd 5520 3225920 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1183 unithd 5520 3228640 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1184 unithd 5520 3231360 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1185 unithd 5520 3234080 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1186 unithd 5520 3236800 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1187 unithd 5520 3239520 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1188 unithd 5520 3242240 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1189 unithd 5520 3244960 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1190 unithd 5520 3247680 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1191 unithd 5520 3250400 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1192 unithd 5520 3253120 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1193 unithd 5520 3255840 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1194 unithd 5520 3258560 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1195 unithd 5520 3261280 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1196 unithd 5520 3264000 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1197 unithd 5520 3266720 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1198 unithd 5520 3269440 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1199 unithd 5520 3272160 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1200 unithd 5520 3274880 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1201 unithd 5520 3277600 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1202 unithd 5520 3280320 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1203 unithd 5520 3283040 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1204 unithd 5520 3285760 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1205 unithd 5520 3288480 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1206 unithd 5520 3291200 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1207 unithd 5520 3293920 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1208 unithd 5520 3296640 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1209 unithd 5520 3299360 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1210 unithd 5520 3302080 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1211 unithd 5520 3304800 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1212 unithd 5520 3307520 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1213 unithd 5520 3310240 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1214 unithd 5520 3312960 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1215 unithd 5520 3315680 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1216 unithd 5520 3318400 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1217 unithd 5520 3321120 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1218 unithd 5520 3323840 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1219 unithd 5520 3326560 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1220 unithd 5520 3329280 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1221 unithd 5520 3332000 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1222 unithd 5520 3334720 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1223 unithd 5520 3337440 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1224 unithd 5520 3340160 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1225 unithd 5520 3342880 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1226 unithd 5520 3345600 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1227 unithd 5520 3348320 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1228 unithd 5520 3351040 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1229 unithd 5520 3353760 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1230 unithd 5520 3356480 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1231 unithd 5520 3359200 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1232 unithd 5520 3361920 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1233 unithd 5520 3364640 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1234 unithd 5520 3367360 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1235 unithd 5520 3370080 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1236 unithd 5520 3372800 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1237 unithd 5520 3375520 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1238 unithd 5520 3378240 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1239 unithd 5520 3380960 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1240 unithd 5520 3383680 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1241 unithd 5520 3386400 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1242 unithd 5520 3389120 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1243 unithd 5520 3391840 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1244 unithd 5520 3394560 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1245 unithd 5520 3397280 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1246 unithd 5520 3400000 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1247 unithd 5520 3402720 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1248 unithd 5520 3405440 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1249 unithd 5520 3408160 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1250 unithd 5520 3410880 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1251 unithd 5520 3413600 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1252 unithd 5520 3416320 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1253 unithd 5520 3419040 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1254 unithd 5520 3421760 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1255 unithd 5520 3424480 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1256 unithd 5520 3427200 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1257 unithd 5520 3429920 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1258 unithd 5520 3432640 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1259 unithd 5520 3435360 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1260 unithd 5520 3438080 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1261 unithd 5520 3440800 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1262 unithd 5520 3443520 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1263 unithd 5520 3446240 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1264 unithd 5520 3448960 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1265 unithd 5520 3451680 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1266 unithd 5520 3454400 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1267 unithd 5520 3457120 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1268 unithd 5520 3459840 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1269 unithd 5520 3462560 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1270 unithd 5520 3465280 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1271 unithd 5520 3468000 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1272 unithd 5520 3470720 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1273 unithd 5520 3473440 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1274 unithd 5520 3476160 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1275 unithd 5520 3478880 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1276 unithd 5520 3481600 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1277 unithd 5520 3484320 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1278 unithd 5520 3487040 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1279 unithd 5520 3489760 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1280 unithd 5520 3492480 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1281 unithd 5520 3495200 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1282 unithd 5520 3497920 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1283 unithd 5520 3500640 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1284 unithd 5520 3503360 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1285 unithd 5520 3506080 FS DO 6323 BY 1 STEP 460 0 ;
+TRACKS X 230 DO 6348 STEP 460 LAYER li1 ;
+TRACKS Y 170 DO 10353 STEP 340 LAYER li1 ;
+TRACKS X 170 DO 8588 STEP 340 LAYER met1 ;
+TRACKS Y 170 DO 10353 STEP 340 LAYER met1 ;
+TRACKS X 230 DO 6348 STEP 460 LAYER met2 ;
+TRACKS Y 230 DO 7652 STEP 460 LAYER met2 ;
+TRACKS X 340 DO 4294 STEP 680 LAYER met3 ;
+TRACKS Y 340 DO 5176 STEP 680 LAYER met3 ;
+TRACKS X 460 DO 3174 STEP 920 LAYER met4 ;
+TRACKS Y 460 DO 3826 STEP 920 LAYER met4 ;
+TRACKS X 1700 DO 859 STEP 3400 LAYER met5 ;
+TRACKS Y 1700 DO 1035 STEP 3400 LAYER met5 ;
+GCELLGRID X 0 DO 423 STEP 6900 ;
+GCELLGRID Y 0 DO 510 STEP 6900 ;
+VIAS 2 ;
+ - via4_3100x3100 + VIARULE M4M5_PR + CUTSIZE 800 800 + LAYERS met4 via4 met5 + CUTSPACING 800 800 + ENCLOSURE 350 350 350 350 + ROWCOL 2 2 ;
+ - via4_1600x3100 + VIARULE M4M5_PR + CUTSIZE 800 800 + LAYERS met4 via4 met5 + CUTSPACING 800 800 + ENCLOSURE 400 350 400 350 + ROWCOL 2 1 ;
+END VIAS
+PINS 645 ;
+ - analog_io[0] + NET analog_io[0] + DIRECTION INOUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( 2921200 1426980 ) N ;
+ - analog_io[10] + NET analog_io[10] + DIRECTION INOUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2230770 3521200 ) N ;
+ - analog_io[11] + NET analog_io[11] + DIRECTION INOUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1906010 3521200 ) N ;
+ - analog_io[12] + NET analog_io[12] + DIRECTION INOUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1581710 3521200 ) N ;
+ - analog_io[13] + NET analog_io[13] + DIRECTION INOUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1257410 3521200 ) N ;
+ - analog_io[14] + NET analog_io[14] + DIRECTION INOUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 932650 3521200 ) N ;
+ - analog_io[15] + NET analog_io[15] + DIRECTION INOUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 608350 3521200 ) N ;
+ - analog_io[16] + NET analog_io[16] + DIRECTION INOUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 284050 3521200 ) N ;
+ - analog_io[17] + NET analog_io[17] + DIRECTION INOUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( -1200 3486700 ) N ;
+ - analog_io[18] + NET analog_io[18] + DIRECTION INOUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( -1200 3225580 ) N ;
+ - analog_io[19] + NET analog_io[19] + DIRECTION INOUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( -1200 2965140 ) N ;
+ - analog_io[1] + NET analog_io[1] + DIRECTION INOUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( 2921200 1692860 ) N ;
+ - analog_io[20] + NET analog_io[20] + DIRECTION INOUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( -1200 2704020 ) N ;
+ - analog_io[21] + NET analog_io[21] + DIRECTION INOUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( -1200 2443580 ) N ;
+ - analog_io[22] + NET analog_io[22] + DIRECTION INOUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( -1200 2183140 ) N ;
+ - analog_io[23] + NET analog_io[23] + DIRECTION INOUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( -1200 1922020 ) N ;
+ - analog_io[24] + NET analog_io[24] + DIRECTION INOUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( -1200 1661580 ) N ;
+ - analog_io[25] + NET analog_io[25] + DIRECTION INOUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( -1200 1400460 ) N ;
+ - analog_io[26] + NET analog_io[26] + DIRECTION INOUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( -1200 1140020 ) N ;
+ - analog_io[27] + NET analog_io[27] + DIRECTION INOUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( -1200 879580 ) N ;
+ - analog_io[28] + NET analog_io[28] + DIRECTION INOUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( -1200 618460 ) N ;
+ - analog_io[2] + NET analog_io[2] + DIRECTION INOUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( 2921200 1958740 ) N ;
+ - analog_io[3] + NET analog_io[3] + DIRECTION INOUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( 2921200 2223940 ) N ;
+ - analog_io[4] + NET analog_io[4] + DIRECTION INOUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( 2921200 2489820 ) N ;
+ - analog_io[5] + NET analog_io[5] + DIRECTION INOUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( 2921200 2755700 ) N ;
+ - analog_io[6] + NET analog_io[6] + DIRECTION INOUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( 2921200 3020900 ) N ;
+ - analog_io[7] + NET analog_io[7] + DIRECTION INOUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( 2921200 3286780 ) N ;
+ - analog_io[8] + NET analog_io[8] + DIRECTION INOUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2879370 3521200 ) N ;
+ - analog_io[9] + NET analog_io[9] + DIRECTION INOUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2555070 3521200 ) N ;
+ - io_in[0] + NET io_in[0] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( 2921200 32980 ) N ;
+ - io_in[10] + NET io_in[10] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( 2921200 2290580 ) N ;
+ - io_in[11] + NET io_in[11] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( 2921200 2556460 ) N ;
+ - io_in[12] + NET io_in[12] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( 2921200 2821660 ) N ;
+ - io_in[13] + NET io_in[13] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( 2921200 3087540 ) N ;
+ - io_in[14] + NET io_in[14] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( 2921200 3353420 ) N ;
+ - io_in[15] + NET io_in[15] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2798410 3521200 ) N ;
+ - io_in[16] + NET io_in[16] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2474110 3521200 ) N ;
+ - io_in[17] + NET io_in[17] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2149350 3521200 ) N ;
+ - io_in[18] + NET io_in[18] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1825050 3521200 ) N ;
+ - io_in[19] + NET io_in[19] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1500750 3521200 ) N ;
+ - io_in[1] + NET io_in[1] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( 2921200 231540 ) N ;
+ - io_in[20] + NET io_in[20] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1175990 3521200 ) N ;
+ - io_in[21] + NET io_in[21] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 851690 3521200 ) N ;
+ - io_in[22] + NET io_in[22] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 527390 3521200 ) N ;
+ - io_in[23] + NET io_in[23] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 202630 3521200 ) N ;
+ - io_in[24] + NET io_in[24] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( -1200 3421420 ) N ;
+ - io_in[25] + NET io_in[25] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( -1200 3160300 ) N ;
+ - io_in[26] + NET io_in[26] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( -1200 2899860 ) N ;
+ - io_in[27] + NET io_in[27] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( -1200 2639420 ) N ;
+ - io_in[28] + NET io_in[28] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( -1200 2378300 ) N ;
+ - io_in[29] + NET io_in[29] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( -1200 2117860 ) N ;
+ - io_in[2] + NET io_in[2] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( 2921200 430780 ) N ;
+ - io_in[30] + NET io_in[30] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( -1200 1856740 ) N ;
+ - io_in[31] + NET io_in[31] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( -1200 1596300 ) N ;
+ - io_in[32] + NET io_in[32] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( -1200 1335860 ) N ;
+ - io_in[33] + NET io_in[33] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( -1200 1074740 ) N ;
+ - io_in[34] + NET io_in[34] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( -1200 814300 ) N ;
+ - io_in[35] + NET io_in[35] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( -1200 553180 ) N ;
+ - io_in[36] + NET io_in[36] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( -1200 358020 ) N ;
+ - io_in[37] + NET io_in[37] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( -1200 162180 ) N ;
+ - io_in[3] + NET io_in[3] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( 2921200 630020 ) N ;
+ - io_in[4] + NET io_in[4] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( 2921200 829260 ) N ;
+ - io_in[5] + NET io_in[5] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( 2921200 1028500 ) N ;
+ - io_in[6] + NET io_in[6] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( 2921200 1227740 ) N ;
+ - io_in[7] + NET io_in[7] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( 2921200 1493620 ) N ;
+ - io_in[8] + NET io_in[8] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( 2921200 1759500 ) N ;
+ - io_in[9] + NET io_in[9] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( 2921200 2024700 ) N ;
+ - io_oeb[0] + NET io_oeb[0] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( 2921200 165580 ) N ;
+ - io_oeb[10] + NET io_oeb[10] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( 2921200 2423180 ) N ;
+ - io_oeb[11] + NET io_oeb[11] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( 2921200 2689060 ) N ;
+ - io_oeb[12] + NET io_oeb[12] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( 2921200 2954940 ) N ;
+ - io_oeb[13] + NET io_oeb[13] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( 2921200 3220140 ) N ;
+ - io_oeb[14] + NET io_oeb[14] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( 2921200 3486020 ) N ;
+ - io_oeb[15] + NET io_oeb[15] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2636030 3521200 ) N ;
+ - io_oeb[16] + NET io_oeb[16] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2311730 3521200 ) N ;
+ - io_oeb[17] + NET io_oeb[17] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1987430 3521200 ) N ;
+ - io_oeb[18] + NET io_oeb[18] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1662670 3521200 ) N ;
+ - io_oeb[19] + NET io_oeb[19] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1338370 3521200 ) N ;
+ - io_oeb[1] + NET io_oeb[1] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( 2921200 364820 ) N ;
+ - io_oeb[20] + NET io_oeb[20] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1014070 3521200 ) N ;
+ - io_oeb[21] + NET io_oeb[21] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 689310 3521200 ) N ;
+ - io_oeb[22] + NET io_oeb[22] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 365010 3521200 ) N ;
+ - io_oeb[23] + NET io_oeb[23] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 40710 3521200 ) N ;
+ - io_oeb[24] + NET io_oeb[24] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( -1200 3290860 ) N ;
+ - io_oeb[25] + NET io_oeb[25] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( -1200 3030420 ) N ;
+ - io_oeb[26] + NET io_oeb[26] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( -1200 2769300 ) N ;
+ - io_oeb[27] + NET io_oeb[27] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( -1200 2508860 ) N ;
+ - io_oeb[28] + NET io_oeb[28] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( -1200 2247740 ) N ;
+ - io_oeb[29] + NET io_oeb[29] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( -1200 1987300 ) N ;
+ - io_oeb[2] + NET io_oeb[2] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( 2921200 564060 ) N ;
+ - io_oeb[30] + NET io_oeb[30] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( -1200 1726860 ) N ;
+ - io_oeb[31] + NET io_oeb[31] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( -1200 1465740 ) N ;
+ - io_oeb[32] + NET io_oeb[32] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( -1200 1205300 ) N ;
+ - io_oeb[33] + NET io_oeb[33] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( -1200 944180 ) N ;
+ - io_oeb[34] + NET io_oeb[34] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( -1200 683740 ) N ;
+ - io_oeb[35] + NET io_oeb[35] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( -1200 423300 ) N ;
+ - io_oeb[36] + NET io_oeb[36] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( -1200 227460 ) N ;
+ - io_oeb[37] + NET io_oeb[37] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( -1200 32300 ) N ;
+ - io_oeb[3] + NET io_oeb[3] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( 2921200 763300 ) N ;
+ - io_oeb[4] + NET io_oeb[4] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( 2921200 962540 ) N ;
+ - io_oeb[5] + NET io_oeb[5] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( 2921200 1161780 ) N ;
+ - io_oeb[6] + NET io_oeb[6] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( 2921200 1361020 ) N ;
+ - io_oeb[7] + NET io_oeb[7] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( 2921200 1626220 ) N ;
+ - io_oeb[8] + NET io_oeb[8] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( 2921200 1892100 ) N ;
+ - io_oeb[9] + NET io_oeb[9] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( 2921200 2157980 ) N ;
+ - io_out[0] + NET io_out[0] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( 2921200 98940 ) N ;
+ - io_out[10] + NET io_out[10] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( 2921200 2357220 ) N ;
+ - io_out[11] + NET io_out[11] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( 2921200 2622420 ) N ;
+ - io_out[12] + NET io_out[12] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( 2921200 2888300 ) N ;
+ - io_out[13] + NET io_out[13] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( 2921200 3154180 ) N ;
+ - io_out[14] + NET io_out[14] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( 2921200 3419380 ) N ;
+ - io_out[15] + NET io_out[15] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2717450 3521200 ) N ;
+ - io_out[16] + NET io_out[16] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2392690 3521200 ) N ;
+ - io_out[17] + NET io_out[17] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2068390 3521200 ) N ;
+ - io_out[18] + NET io_out[18] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1744090 3521200 ) N ;
+ - io_out[19] + NET io_out[19] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1419330 3521200 ) N ;
+ - io_out[1] + NET io_out[1] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( 2921200 298180 ) N ;
+ - io_out[20] + NET io_out[20] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1095030 3521200 ) N ;
+ - io_out[21] + NET io_out[21] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 770730 3521200 ) N ;
+ - io_out[22] + NET io_out[22] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 445970 3521200 ) N ;
+ - io_out[23] + NET io_out[23] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 121670 3521200 ) N ;
+ - io_out[24] + NET io_out[24] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( -1200 3356140 ) N ;
+ - io_out[25] + NET io_out[25] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( -1200 3095700 ) N ;
+ - io_out[26] + NET io_out[26] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( -1200 2834580 ) N ;
+ - io_out[27] + NET io_out[27] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( -1200 2574140 ) N ;
+ - io_out[28] + NET io_out[28] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( -1200 2313020 ) N ;
+ - io_out[29] + NET io_out[29] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( -1200 2052580 ) N ;
+ - io_out[2] + NET io_out[2] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( 2921200 497420 ) N ;
+ - io_out[30] + NET io_out[30] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( -1200 1792140 ) N ;
+ - io_out[31] + NET io_out[31] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( -1200 1531020 ) N ;
+ - io_out[32] + NET io_out[32] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( -1200 1270580 ) N ;
+ - io_out[33] + NET io_out[33] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( -1200 1009460 ) N ;
+ - io_out[34] + NET io_out[34] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( -1200 749020 ) N ;
+ - io_out[35] + NET io_out[35] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( -1200 487900 ) N ;
+ - io_out[36] + NET io_out[36] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( -1200 292740 ) N ;
+ - io_out[37] + NET io_out[37] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( -1200 96900 ) N ;
+ - io_out[3] + NET io_out[3] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( 2921200 696660 ) N ;
+ - io_out[4] + NET io_out[4] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( 2921200 895900 ) N ;
+ - io_out[5] + NET io_out[5] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( 2921200 1095140 ) N ;
+ - io_out[6] + NET io_out[6] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( 2921200 1294380 ) N ;
+ - io_out[7] + NET io_out[7] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( 2921200 1560260 ) N ;
+ - io_out[8] + NET io_out[8] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( 2921200 1825460 ) N ;
+ - io_out[9] + NET io_out[9] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( 2921200 2091340 ) N ;
+ - la_data_in[0] + NET la_data_in[0] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 629510 -1200 ) N ;
+ - la_data_in[100] + NET la_data_in[100] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2402810 -1200 ) N ;
+ - la_data_in[101] + NET la_data_in[101] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2420290 -1200 ) N ;
+ - la_data_in[102] + NET la_data_in[102] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2438230 -1200 ) N ;
+ - la_data_in[103] + NET la_data_in[103] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2455710 -1200 ) N ;
+ - la_data_in[104] + NET la_data_in[104] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2473650 -1200 ) N ;
+ - la_data_in[105] + NET la_data_in[105] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2491130 -1200 ) N ;
+ - la_data_in[106] + NET la_data_in[106] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2509070 -1200 ) N ;
+ - la_data_in[107] + NET la_data_in[107] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2527010 -1200 ) N ;
+ - la_data_in[108] + NET la_data_in[108] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2544490 -1200 ) N ;
+ - la_data_in[109] + NET la_data_in[109] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2562430 -1200 ) N ;
+ - la_data_in[10] + NET la_data_in[10] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 806610 -1200 ) N ;
+ - la_data_in[110] + NET la_data_in[110] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2579910 -1200 ) N ;
+ - la_data_in[111] + NET la_data_in[111] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2597850 -1200 ) N ;
+ - la_data_in[112] + NET la_data_in[112] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2615330 -1200 ) N ;
+ - la_data_in[113] + NET la_data_in[113] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2633270 -1200 ) N ;
+ - la_data_in[114] + NET la_data_in[114] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2650750 -1200 ) N ;
+ - la_data_in[115] + NET la_data_in[115] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2668690 -1200 ) N ;
+ - la_data_in[116] + NET la_data_in[116] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2686170 -1200 ) N ;
+ - la_data_in[117] + NET la_data_in[117] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2704110 -1200 ) N ;
+ - la_data_in[118] + NET la_data_in[118] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2722050 -1200 ) N ;
+ - la_data_in[119] + NET la_data_in[119] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2739530 -1200 ) N ;
+ - la_data_in[11] + NET la_data_in[11] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 824550 -1200 ) N ;
+ - la_data_in[120] + NET la_data_in[120] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2757470 -1200 ) N ;
+ - la_data_in[121] + NET la_data_in[121] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2774950 -1200 ) N ;
+ - la_data_in[122] + NET la_data_in[122] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2792890 -1200 ) N ;
+ - la_data_in[123] + NET la_data_in[123] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2810370 -1200 ) N ;
+ - la_data_in[124] + NET la_data_in[124] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2828310 -1200 ) N ;
+ - la_data_in[125] + NET la_data_in[125] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2845790 -1200 ) N ;
+ - la_data_in[126] + NET la_data_in[126] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2863730 -1200 ) N ;
+ - la_data_in[127] + NET la_data_in[127] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2881670 -1200 ) N ;
+ - la_data_in[12] + NET la_data_in[12] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 842030 -1200 ) N ;
+ - la_data_in[13] + NET la_data_in[13] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 859970 -1200 ) N ;
+ - la_data_in[14] + NET la_data_in[14] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 877450 -1200 ) N ;
+ - la_data_in[15] + NET la_data_in[15] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 895390 -1200 ) N ;
+ - la_data_in[16] + NET la_data_in[16] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 912870 -1200 ) N ;
+ - la_data_in[17] + NET la_data_in[17] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 930810 -1200 ) N ;
+ - la_data_in[18] + NET la_data_in[18] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 948750 -1200 ) N ;
+ - la_data_in[19] + NET la_data_in[19] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 966230 -1200 ) N ;
+ - la_data_in[1] + NET la_data_in[1] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 646990 -1200 ) N ;
+ - la_data_in[20] + NET la_data_in[20] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 984170 -1200 ) N ;
+ - la_data_in[21] + NET la_data_in[21] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1001650 -1200 ) N ;
+ - la_data_in[22] + NET la_data_in[22] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1019590 -1200 ) N ;
+ - la_data_in[23] + NET la_data_in[23] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1037070 -1200 ) N ;
+ - la_data_in[24] + NET la_data_in[24] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1055010 -1200 ) N ;
+ - la_data_in[25] + NET la_data_in[25] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1072490 -1200 ) N ;
+ - la_data_in[26] + NET la_data_in[26] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1090430 -1200 ) N ;
+ - la_data_in[27] + NET la_data_in[27] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1107910 -1200 ) N ;
+ - la_data_in[28] + NET la_data_in[28] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1125850 -1200 ) N ;
+ - la_data_in[29] + NET la_data_in[29] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1143790 -1200 ) N ;
+ - la_data_in[2] + NET la_data_in[2] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 664930 -1200 ) N ;
+ - la_data_in[30] + NET la_data_in[30] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1161270 -1200 ) N ;
+ - la_data_in[31] + NET la_data_in[31] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1179210 -1200 ) N ;
+ - la_data_in[32] + NET la_data_in[32] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1196690 -1200 ) N ;
+ - la_data_in[33] + NET la_data_in[33] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1214630 -1200 ) N ;
+ - la_data_in[34] + NET la_data_in[34] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1232110 -1200 ) N ;
+ - la_data_in[35] + NET la_data_in[35] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1250050 -1200 ) N ;
+ - la_data_in[36] + NET la_data_in[36] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1267530 -1200 ) N ;
+ - la_data_in[37] + NET la_data_in[37] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1285470 -1200 ) N ;
+ - la_data_in[38] + NET la_data_in[38] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1303410 -1200 ) N ;
+ - la_data_in[39] + NET la_data_in[39] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1320890 -1200 ) N ;
+ - la_data_in[3] + NET la_data_in[3] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 682410 -1200 ) N ;
+ - la_data_in[40] + NET la_data_in[40] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1338830 -1200 ) N ;
+ - la_data_in[41] + NET la_data_in[41] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1356310 -1200 ) N ;
+ - la_data_in[42] + NET la_data_in[42] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1374250 -1200 ) N ;
+ - la_data_in[43] + NET la_data_in[43] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1391730 -1200 ) N ;
+ - la_data_in[44] + NET la_data_in[44] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1409670 -1200 ) N ;
+ - la_data_in[45] + NET la_data_in[45] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1427150 -1200 ) N ;
+ - la_data_in[46] + NET la_data_in[46] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1445090 -1200 ) N ;
+ - la_data_in[47] + NET la_data_in[47] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1463030 -1200 ) N ;
+ - la_data_in[48] + NET la_data_in[48] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1480510 -1200 ) N ;
+ - la_data_in[49] + NET la_data_in[49] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1498450 -1200 ) N ;
+ - la_data_in[4] + NET la_data_in[4] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 700350 -1200 ) N ;
+ - la_data_in[50] + NET la_data_in[50] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1515930 -1200 ) N ;
+ - la_data_in[51] + NET la_data_in[51] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1533870 -1200 ) N ;
+ - la_data_in[52] + NET la_data_in[52] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1551350 -1200 ) N ;
+ - la_data_in[53] + NET la_data_in[53] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1569290 -1200 ) N ;
+ - la_data_in[54] + NET la_data_in[54] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1586770 -1200 ) N ;
+ - la_data_in[55] + NET la_data_in[55] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1604710 -1200 ) N ;
+ - la_data_in[56] + NET la_data_in[56] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1622190 -1200 ) N ;
+ - la_data_in[57] + NET la_data_in[57] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1640130 -1200 ) N ;
+ - la_data_in[58] + NET la_data_in[58] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1658070 -1200 ) N ;
+ - la_data_in[59] + NET la_data_in[59] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1675550 -1200 ) N ;
+ - la_data_in[5] + NET la_data_in[5] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 717830 -1200 ) N ;
+ - la_data_in[60] + NET la_data_in[60] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1693490 -1200 ) N ;
+ - la_data_in[61] + NET la_data_in[61] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1710970 -1200 ) N ;
+ - la_data_in[62] + NET la_data_in[62] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1728910 -1200 ) N ;
+ - la_data_in[63] + NET la_data_in[63] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1746390 -1200 ) N ;
+ - la_data_in[64] + NET la_data_in[64] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1764330 -1200 ) N ;
+ - la_data_in[65] + NET la_data_in[65] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1781810 -1200 ) N ;
+ - la_data_in[66] + NET la_data_in[66] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1799750 -1200 ) N ;
+ - la_data_in[67] + NET la_data_in[67] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1817690 -1200 ) N ;
+ - la_data_in[68] + NET la_data_in[68] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1835170 -1200 ) N ;
+ - la_data_in[69] + NET la_data_in[69] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1853110 -1200 ) N ;
+ - la_data_in[6] + NET la_data_in[6] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 735770 -1200 ) N ;
+ - la_data_in[70] + NET la_data_in[70] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1870590 -1200 ) N ;
+ - la_data_in[71] + NET la_data_in[71] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1888530 -1200 ) N ;
+ - la_data_in[72] + NET la_data_in[72] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1906010 -1200 ) N ;
+ - la_data_in[73] + NET la_data_in[73] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1923950 -1200 ) N ;
+ - la_data_in[74] + NET la_data_in[74] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1941430 -1200 ) N ;
+ - la_data_in[75] + NET la_data_in[75] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1959370 -1200 ) N ;
+ - la_data_in[76] + NET la_data_in[76] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1976850 -1200 ) N ;
+ - la_data_in[77] + NET la_data_in[77] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1994790 -1200 ) N ;
+ - la_data_in[78] + NET la_data_in[78] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2012730 -1200 ) N ;
+ - la_data_in[79] + NET la_data_in[79] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2030210 -1200 ) N ;
+ - la_data_in[7] + NET la_data_in[7] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 753250 -1200 ) N ;
+ - la_data_in[80] + NET la_data_in[80] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2048150 -1200 ) N ;
+ - la_data_in[81] + NET la_data_in[81] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2065630 -1200 ) N ;
+ - la_data_in[82] + NET la_data_in[82] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2083570 -1200 ) N ;
+ - la_data_in[83] + NET la_data_in[83] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2101050 -1200 ) N ;
+ - la_data_in[84] + NET la_data_in[84] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2118990 -1200 ) N ;
+ - la_data_in[85] + NET la_data_in[85] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2136470 -1200 ) N ;
+ - la_data_in[86] + NET la_data_in[86] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2154410 -1200 ) N ;
+ - la_data_in[87] + NET la_data_in[87] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2172350 -1200 ) N ;
+ - la_data_in[88] + NET la_data_in[88] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2189830 -1200 ) N ;
+ - la_data_in[89] + NET la_data_in[89] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2207770 -1200 ) N ;
+ - la_data_in[8] + NET la_data_in[8] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 771190 -1200 ) N ;
+ - la_data_in[90] + NET la_data_in[90] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2225250 -1200 ) N ;
+ - la_data_in[91] + NET la_data_in[91] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2243190 -1200 ) N ;
+ - la_data_in[92] + NET la_data_in[92] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2260670 -1200 ) N ;
+ - la_data_in[93] + NET la_data_in[93] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2278610 -1200 ) N ;
+ - la_data_in[94] + NET la_data_in[94] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2296090 -1200 ) N ;
+ - la_data_in[95] + NET la_data_in[95] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2314030 -1200 ) N ;
+ - la_data_in[96] + NET la_data_in[96] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2331510 -1200 ) N ;
+ - la_data_in[97] + NET la_data_in[97] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2349450 -1200 ) N ;
+ - la_data_in[98] + NET la_data_in[98] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2367390 -1200 ) N ;
+ - la_data_in[99] + NET la_data_in[99] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2384870 -1200 ) N ;
+ - la_data_in[9] + NET la_data_in[9] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 789130 -1200 ) N ;
+ - la_data_out[0] + NET la_data_out[0] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 635030 -1200 ) N ;
+ - la_data_out[100] + NET la_data_out[100] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2408790 -1200 ) N ;
+ - la_data_out[101] + NET la_data_out[101] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2426270 -1200 ) N ;
+ - la_data_out[102] + NET la_data_out[102] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2444210 -1200 ) N ;
+ - la_data_out[103] + NET la_data_out[103] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2461690 -1200 ) N ;
+ - la_data_out[104] + NET la_data_out[104] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2479630 -1200 ) N ;
+ - la_data_out[105] + NET la_data_out[105] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2497110 -1200 ) N ;
+ - la_data_out[106] + NET la_data_out[106] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2515050 -1200 ) N ;
+ - la_data_out[107] + NET la_data_out[107] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2532530 -1200 ) N ;
+ - la_data_out[108] + NET la_data_out[108] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2550470 -1200 ) N ;
+ - la_data_out[109] + NET la_data_out[109] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2567950 -1200 ) N ;
+ - la_data_out[10] + NET la_data_out[10] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 812590 -1200 ) N ;
+ - la_data_out[110] + NET la_data_out[110] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2585890 -1200 ) N ;
+ - la_data_out[111] + NET la_data_out[111] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2603830 -1200 ) N ;
+ - la_data_out[112] + NET la_data_out[112] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2621310 -1200 ) N ;
+ - la_data_out[113] + NET la_data_out[113] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2639250 -1200 ) N ;
+ - la_data_out[114] + NET la_data_out[114] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2656730 -1200 ) N ;
+ - la_data_out[115] + NET la_data_out[115] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2674670 -1200 ) N ;
+ - la_data_out[116] + NET la_data_out[116] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2692150 -1200 ) N ;
+ - la_data_out[117] + NET la_data_out[117] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2710090 -1200 ) N ;
+ - la_data_out[118] + NET la_data_out[118] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2727570 -1200 ) N ;
+ - la_data_out[119] + NET la_data_out[119] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2745510 -1200 ) N ;
+ - la_data_out[11] + NET la_data_out[11] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 830530 -1200 ) N ;
+ - la_data_out[120] + NET la_data_out[120] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2763450 -1200 ) N ;
+ - la_data_out[121] + NET la_data_out[121] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2780930 -1200 ) N ;
+ - la_data_out[122] + NET la_data_out[122] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2798870 -1200 ) N ;
+ - la_data_out[123] + NET la_data_out[123] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2816350 -1200 ) N ;
+ - la_data_out[124] + NET la_data_out[124] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2834290 -1200 ) N ;
+ - la_data_out[125] + NET la_data_out[125] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2851770 -1200 ) N ;
+ - la_data_out[126] + NET la_data_out[126] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2869710 -1200 ) N ;
+ - la_data_out[127] + NET la_data_out[127] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2887190 -1200 ) N ;
+ - la_data_out[12] + NET la_data_out[12] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 848010 -1200 ) N ;
+ - la_data_out[13] + NET la_data_out[13] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 865950 -1200 ) N ;
+ - la_data_out[14] + NET la_data_out[14] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 883430 -1200 ) N ;
+ - la_data_out[15] + NET la_data_out[15] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 901370 -1200 ) N ;
+ - la_data_out[16] + NET la_data_out[16] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 918850 -1200 ) N ;
+ - la_data_out[17] + NET la_data_out[17] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 936790 -1200 ) N ;
+ - la_data_out[18] + NET la_data_out[18] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 954270 -1200 ) N ;
+ - la_data_out[19] + NET la_data_out[19] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 972210 -1200 ) N ;
+ - la_data_out[1] + NET la_data_out[1] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 652970 -1200 ) N ;
+ - la_data_out[20] + NET la_data_out[20] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 989690 -1200 ) N ;
+ - la_data_out[21] + NET la_data_out[21] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1007630 -1200 ) N ;
+ - la_data_out[22] + NET la_data_out[22] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1025570 -1200 ) N ;
+ - la_data_out[23] + NET la_data_out[23] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1043050 -1200 ) N ;
+ - la_data_out[24] + NET la_data_out[24] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1060990 -1200 ) N ;
+ - la_data_out[25] + NET la_data_out[25] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1078470 -1200 ) N ;
+ - la_data_out[26] + NET la_data_out[26] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1096410 -1200 ) N ;
+ - la_data_out[27] + NET la_data_out[27] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1113890 -1200 ) N ;
+ - la_data_out[28] + NET la_data_out[28] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1131830 -1200 ) N ;
+ - la_data_out[29] + NET la_data_out[29] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1149310 -1200 ) N ;
+ - la_data_out[2] + NET la_data_out[2] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 670910 -1200 ) N ;
+ - la_data_out[30] + NET la_data_out[30] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1167250 -1200 ) N ;
+ - la_data_out[31] + NET la_data_out[31] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1185190 -1200 ) N ;
+ - la_data_out[32] + NET la_data_out[32] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1202670 -1200 ) N ;
+ - la_data_out[33] + NET la_data_out[33] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1220610 -1200 ) N ;
+ - la_data_out[34] + NET la_data_out[34] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1238090 -1200 ) N ;
+ - la_data_out[35] + NET la_data_out[35] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1256030 -1200 ) N ;
+ - la_data_out[36] + NET la_data_out[36] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1273510 -1200 ) N ;
+ - la_data_out[37] + NET la_data_out[37] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1291450 -1200 ) N ;
+ - la_data_out[38] + NET la_data_out[38] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1308930 -1200 ) N ;
+ - la_data_out[39] + NET la_data_out[39] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1326870 -1200 ) N ;
+ - la_data_out[3] + NET la_data_out[3] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 688390 -1200 ) N ;
+ - la_data_out[40] + NET la_data_out[40] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1344350 -1200 ) N ;
+ - la_data_out[41] + NET la_data_out[41] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1362290 -1200 ) N ;
+ - la_data_out[42] + NET la_data_out[42] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1380230 -1200 ) N ;
+ - la_data_out[43] + NET la_data_out[43] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1397710 -1200 ) N ;
+ - la_data_out[44] + NET la_data_out[44] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1415650 -1200 ) N ;
+ - la_data_out[45] + NET la_data_out[45] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1433130 -1200 ) N ;
+ - la_data_out[46] + NET la_data_out[46] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1451070 -1200 ) N ;
+ - la_data_out[47] + NET la_data_out[47] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1468550 -1200 ) N ;
+ - la_data_out[48] + NET la_data_out[48] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1486490 -1200 ) N ;
+ - la_data_out[49] + NET la_data_out[49] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1503970 -1200 ) N ;
+ - la_data_out[4] + NET la_data_out[4] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 706330 -1200 ) N ;
+ - la_data_out[50] + NET la_data_out[50] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1521910 -1200 ) N ;
+ - la_data_out[51] + NET la_data_out[51] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1539850 -1200 ) N ;
+ - la_data_out[52] + NET la_data_out[52] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1557330 -1200 ) N ;
+ - la_data_out[53] + NET la_data_out[53] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1575270 -1200 ) N ;
+ - la_data_out[54] + NET la_data_out[54] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1592750 -1200 ) N ;
+ - la_data_out[55] + NET la_data_out[55] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1610690 -1200 ) N ;
+ - la_data_out[56] + NET la_data_out[56] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1628170 -1200 ) N ;
+ - la_data_out[57] + NET la_data_out[57] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1646110 -1200 ) N ;
+ - la_data_out[58] + NET la_data_out[58] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1663590 -1200 ) N ;
+ - la_data_out[59] + NET la_data_out[59] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1681530 -1200 ) N ;
+ - la_data_out[5] + NET la_data_out[5] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 723810 -1200 ) N ;
+ - la_data_out[60] + NET la_data_out[60] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1699470 -1200 ) N ;
+ - la_data_out[61] + NET la_data_out[61] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1716950 -1200 ) N ;
+ - la_data_out[62] + NET la_data_out[62] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1734890 -1200 ) N ;
+ - la_data_out[63] + NET la_data_out[63] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1752370 -1200 ) N ;
+ - la_data_out[64] + NET la_data_out[64] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1770310 -1200 ) N ;
+ - la_data_out[65] + NET la_data_out[65] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1787790 -1200 ) N ;
+ - la_data_out[66] + NET la_data_out[66] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1805730 -1200 ) N ;
+ - la_data_out[67] + NET la_data_out[67] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1823210 -1200 ) N ;
+ - la_data_out[68] + NET la_data_out[68] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1841150 -1200 ) N ;
+ - la_data_out[69] + NET la_data_out[69] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1858630 -1200 ) N ;
+ - la_data_out[6] + NET la_data_out[6] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 741750 -1200 ) N ;
+ - la_data_out[70] + NET la_data_out[70] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1876570 -1200 ) N ;
+ - la_data_out[71] + NET la_data_out[71] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1894510 -1200 ) N ;
+ - la_data_out[72] + NET la_data_out[72] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1911990 -1200 ) N ;
+ - la_data_out[73] + NET la_data_out[73] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1929930 -1200 ) N ;
+ - la_data_out[74] + NET la_data_out[74] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1947410 -1200 ) N ;
+ - la_data_out[75] + NET la_data_out[75] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1965350 -1200 ) N ;
+ - la_data_out[76] + NET la_data_out[76] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1982830 -1200 ) N ;
+ - la_data_out[77] + NET la_data_out[77] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2000770 -1200 ) N ;
+ - la_data_out[78] + NET la_data_out[78] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2018250 -1200 ) N ;
+ - la_data_out[79] + NET la_data_out[79] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2036190 -1200 ) N ;
+ - la_data_out[7] + NET la_data_out[7] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 759230 -1200 ) N ;
+ - la_data_out[80] + NET la_data_out[80] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2054130 -1200 ) N ;
+ - la_data_out[81] + NET la_data_out[81] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2071610 -1200 ) N ;
+ - la_data_out[82] + NET la_data_out[82] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2089550 -1200 ) N ;
+ - la_data_out[83] + NET la_data_out[83] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2107030 -1200 ) N ;
+ - la_data_out[84] + NET la_data_out[84] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2124970 -1200 ) N ;
+ - la_data_out[85] + NET la_data_out[85] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2142450 -1200 ) N ;
+ - la_data_out[86] + NET la_data_out[86] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2160390 -1200 ) N ;
+ - la_data_out[87] + NET la_data_out[87] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2177870 -1200 ) N ;
+ - la_data_out[88] + NET la_data_out[88] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2195810 -1200 ) N ;
+ - la_data_out[89] + NET la_data_out[89] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2213290 -1200 ) N ;
+ - la_data_out[8] + NET la_data_out[8] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 777170 -1200 ) N ;
+ - la_data_out[90] + NET la_data_out[90] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2231230 -1200 ) N ;
+ - la_data_out[91] + NET la_data_out[91] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2249170 -1200 ) N ;
+ - la_data_out[92] + NET la_data_out[92] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2266650 -1200 ) N ;
+ - la_data_out[93] + NET la_data_out[93] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2284590 -1200 ) N ;
+ - la_data_out[94] + NET la_data_out[94] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2302070 -1200 ) N ;
+ - la_data_out[95] + NET la_data_out[95] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2320010 -1200 ) N ;
+ - la_data_out[96] + NET la_data_out[96] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2337490 -1200 ) N ;
+ - la_data_out[97] + NET la_data_out[97] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2355430 -1200 ) N ;
+ - la_data_out[98] + NET la_data_out[98] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2372910 -1200 ) N ;
+ - la_data_out[99] + NET la_data_out[99] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2390850 -1200 ) N ;
+ - la_data_out[9] + NET la_data_out[9] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 794650 -1200 ) N ;
+ - la_oenb[0] + NET la_oenb[0] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 641010 -1200 ) N ;
+ - la_oenb[100] + NET la_oenb[100] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2414310 -1200 ) N ;
+ - la_oenb[101] + NET la_oenb[101] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2432250 -1200 ) N ;
+ - la_oenb[102] + NET la_oenb[102] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2449730 -1200 ) N ;
+ - la_oenb[103] + NET la_oenb[103] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2467670 -1200 ) N ;
+ - la_oenb[104] + NET la_oenb[104] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2485610 -1200 ) N ;
+ - la_oenb[105] + NET la_oenb[105] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2503090 -1200 ) N ;
+ - la_oenb[106] + NET la_oenb[106] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2521030 -1200 ) N ;
+ - la_oenb[107] + NET la_oenb[107] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2538510 -1200 ) N ;
+ - la_oenb[108] + NET la_oenb[108] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2556450 -1200 ) N ;
+ - la_oenb[109] + NET la_oenb[109] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2573930 -1200 ) N ;
+ - la_oenb[10] + NET la_oenb[10] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 818570 -1200 ) N ;
+ - la_oenb[110] + NET la_oenb[110] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2591870 -1200 ) N ;
+ - la_oenb[111] + NET la_oenb[111] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2609350 -1200 ) N ;
+ - la_oenb[112] + NET la_oenb[112] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2627290 -1200 ) N ;
+ - la_oenb[113] + NET la_oenb[113] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2645230 -1200 ) N ;
+ - la_oenb[114] + NET la_oenb[114] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2662710 -1200 ) N ;
+ - la_oenb[115] + NET la_oenb[115] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2680650 -1200 ) N ;
+ - la_oenb[116] + NET la_oenb[116] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2698130 -1200 ) N ;
+ - la_oenb[117] + NET la_oenb[117] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2716070 -1200 ) N ;
+ - la_oenb[118] + NET la_oenb[118] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2733550 -1200 ) N ;
+ - la_oenb[119] + NET la_oenb[119] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2751490 -1200 ) N ;
+ - la_oenb[11] + NET la_oenb[11] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 836050 -1200 ) N ;
+ - la_oenb[120] + NET la_oenb[120] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2768970 -1200 ) N ;
+ - la_oenb[121] + NET la_oenb[121] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2786910 -1200 ) N ;
+ - la_oenb[122] + NET la_oenb[122] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2804390 -1200 ) N ;
+ - la_oenb[123] + NET la_oenb[123] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2822330 -1200 ) N ;
+ - la_oenb[124] + NET la_oenb[124] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2840270 -1200 ) N ;
+ - la_oenb[125] + NET la_oenb[125] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2857750 -1200 ) N ;
+ - la_oenb[126] + NET la_oenb[126] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2875690 -1200 ) N ;
+ - la_oenb[127] + NET la_oenb[127] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2893170 -1200 ) N ;
+ - la_oenb[12] + NET la_oenb[12] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 853990 -1200 ) N ;
+ - la_oenb[13] + NET la_oenb[13] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 871470 -1200 ) N ;
+ - la_oenb[14] + NET la_oenb[14] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 889410 -1200 ) N ;
+ - la_oenb[15] + NET la_oenb[15] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 907350 -1200 ) N ;
+ - la_oenb[16] + NET la_oenb[16] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 924830 -1200 ) N ;
+ - la_oenb[17] + NET la_oenb[17] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 942770 -1200 ) N ;
+ - la_oenb[18] + NET la_oenb[18] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 960250 -1200 ) N ;
+ - la_oenb[19] + NET la_oenb[19] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 978190 -1200 ) N ;
+ - la_oenb[1] + NET la_oenb[1] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 658950 -1200 ) N ;
+ - la_oenb[20] + NET la_oenb[20] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 995670 -1200 ) N ;
+ - la_oenb[21] + NET la_oenb[21] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1013610 -1200 ) N ;
+ - la_oenb[22] + NET la_oenb[22] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1031090 -1200 ) N ;
+ - la_oenb[23] + NET la_oenb[23] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1049030 -1200 ) N ;
+ - la_oenb[24] + NET la_oenb[24] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1066970 -1200 ) N ;
+ - la_oenb[25] + NET la_oenb[25] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1084450 -1200 ) N ;
+ - la_oenb[26] + NET la_oenb[26] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1102390 -1200 ) N ;
+ - la_oenb[27] + NET la_oenb[27] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1119870 -1200 ) N ;
+ - la_oenb[28] + NET la_oenb[28] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1137810 -1200 ) N ;
+ - la_oenb[29] + NET la_oenb[29] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1155290 -1200 ) N ;
+ - la_oenb[2] + NET la_oenb[2] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 676430 -1200 ) N ;
+ - la_oenb[30] + NET la_oenb[30] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1173230 -1200 ) N ;
+ - la_oenb[31] + NET la_oenb[31] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1190710 -1200 ) N ;
+ - la_oenb[32] + NET la_oenb[32] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1208650 -1200 ) N ;
+ - la_oenb[33] + NET la_oenb[33] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1226130 -1200 ) N ;
+ - la_oenb[34] + NET la_oenb[34] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1244070 -1200 ) N ;
+ - la_oenb[35] + NET la_oenb[35] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1262010 -1200 ) N ;
+ - la_oenb[36] + NET la_oenb[36] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1279490 -1200 ) N ;
+ - la_oenb[37] + NET la_oenb[37] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1297430 -1200 ) N ;
+ - la_oenb[38] + NET la_oenb[38] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1314910 -1200 ) N ;
+ - la_oenb[39] + NET la_oenb[39] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1332850 -1200 ) N ;
+ - la_oenb[3] + NET la_oenb[3] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 694370 -1200 ) N ;
+ - la_oenb[40] + NET la_oenb[40] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1350330 -1200 ) N ;
+ - la_oenb[41] + NET la_oenb[41] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1368270 -1200 ) N ;
+ - la_oenb[42] + NET la_oenb[42] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1385750 -1200 ) N ;
+ - la_oenb[43] + NET la_oenb[43] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1403690 -1200 ) N ;
+ - la_oenb[44] + NET la_oenb[44] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1421630 -1200 ) N ;
+ - la_oenb[45] + NET la_oenb[45] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1439110 -1200 ) N ;
+ - la_oenb[46] + NET la_oenb[46] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1457050 -1200 ) N ;
+ - la_oenb[47] + NET la_oenb[47] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1474530 -1200 ) N ;
+ - la_oenb[48] + NET la_oenb[48] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1492470 -1200 ) N ;
+ - la_oenb[49] + NET la_oenb[49] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1509950 -1200 ) N ;
+ - la_oenb[4] + NET la_oenb[4] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 712310 -1200 ) N ;
+ - la_oenb[50] + NET la_oenb[50] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1527890 -1200 ) N ;
+ - la_oenb[51] + NET la_oenb[51] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1545370 -1200 ) N ;
+ - la_oenb[52] + NET la_oenb[52] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1563310 -1200 ) N ;
+ - la_oenb[53] + NET la_oenb[53] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1581250 -1200 ) N ;
+ - la_oenb[54] + NET la_oenb[54] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1598730 -1200 ) N ;
+ - la_oenb[55] + NET la_oenb[55] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1616670 -1200 ) N ;
+ - la_oenb[56] + NET la_oenb[56] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1634150 -1200 ) N ;
+ - la_oenb[57] + NET la_oenb[57] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1652090 -1200 ) N ;
+ - la_oenb[58] + NET la_oenb[58] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1669570 -1200 ) N ;
+ - la_oenb[59] + NET la_oenb[59] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1687510 -1200 ) N ;
+ - la_oenb[5] + NET la_oenb[5] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 729790 -1200 ) N ;
+ - la_oenb[60] + NET la_oenb[60] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1704990 -1200 ) N ;
+ - la_oenb[61] + NET la_oenb[61] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1722930 -1200 ) N ;
+ - la_oenb[62] + NET la_oenb[62] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1740410 -1200 ) N ;
+ - la_oenb[63] + NET la_oenb[63] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1758350 -1200 ) N ;
+ - la_oenb[64] + NET la_oenb[64] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1776290 -1200 ) N ;
+ - la_oenb[65] + NET la_oenb[65] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1793770 -1200 ) N ;
+ - la_oenb[66] + NET la_oenb[66] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1811710 -1200 ) N ;
+ - la_oenb[67] + NET la_oenb[67] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1829190 -1200 ) N ;
+ - la_oenb[68] + NET la_oenb[68] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1847130 -1200 ) N ;
+ - la_oenb[69] + NET la_oenb[69] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1864610 -1200 ) N ;
+ - la_oenb[6] + NET la_oenb[6] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 747730 -1200 ) N ;
+ - la_oenb[70] + NET la_oenb[70] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1882550 -1200 ) N ;
+ - la_oenb[71] + NET la_oenb[71] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1900030 -1200 ) N ;
+ - la_oenb[72] + NET la_oenb[72] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1917970 -1200 ) N ;
+ - la_oenb[73] + NET la_oenb[73] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1935910 -1200 ) N ;
+ - la_oenb[74] + NET la_oenb[74] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1953390 -1200 ) N ;
+ - la_oenb[75] + NET la_oenb[75] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1971330 -1200 ) N ;
+ - la_oenb[76] + NET la_oenb[76] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1988810 -1200 ) N ;
+ - la_oenb[77] + NET la_oenb[77] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2006750 -1200 ) N ;
+ - la_oenb[78] + NET la_oenb[78] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2024230 -1200 ) N ;
+ - la_oenb[79] + NET la_oenb[79] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2042170 -1200 ) N ;
+ - la_oenb[7] + NET la_oenb[7] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 765210 -1200 ) N ;
+ - la_oenb[80] + NET la_oenb[80] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2059650 -1200 ) N ;
+ - la_oenb[81] + NET la_oenb[81] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2077590 -1200 ) N ;
+ - la_oenb[82] + NET la_oenb[82] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2095070 -1200 ) N ;
+ - la_oenb[83] + NET la_oenb[83] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2113010 -1200 ) N ;
+ - la_oenb[84] + NET la_oenb[84] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2130950 -1200 ) N ;
+ - la_oenb[85] + NET la_oenb[85] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2148430 -1200 ) N ;
+ - la_oenb[86] + NET la_oenb[86] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2166370 -1200 ) N ;
+ - la_oenb[87] + NET la_oenb[87] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2183850 -1200 ) N ;
+ - la_oenb[88] + NET la_oenb[88] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2201790 -1200 ) N ;
+ - la_oenb[89] + NET la_oenb[89] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2219270 -1200 ) N ;
+ - la_oenb[8] + NET la_oenb[8] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 783150 -1200 ) N ;
+ - la_oenb[90] + NET la_oenb[90] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2237210 -1200 ) N ;
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+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2254690 -1200 ) N ;
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+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2272630 -1200 ) N ;
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+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2290570 -1200 ) N ;
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+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2308050 -1200 ) N ;
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+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2325990 -1200 ) N ;
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+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2343470 -1200 ) N ;
+ - la_oenb[97] + NET la_oenb[97] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2361410 -1200 ) N ;
+ - la_oenb[98] + NET la_oenb[98] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2378890 -1200 ) N ;
+ - la_oenb[99] + NET la_oenb[99] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2396830 -1200 ) N ;
+ - la_oenb[9] + NET la_oenb[9] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 800630 -1200 ) N ;
+ - user_clock2 + NET user_clock2 + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2899150 -1200 ) N ;
+ - user_irq[0] + NET user_irq[0] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2905130 -1200 ) N ;
+ - user_irq[1] + NET user_irq[1] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2911110 -1200 ) N ;
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+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2917090 -1200 ) N ;
+ - vccd1 + NET vccd1 + SPECIAL + DIRECTION INPUT + USE POWER
+ + PORT
+ + LAYER met4 ( -1550 -1769310 ) ( 1550 1769310 )
+ + LAYER met4 ( -181550 -1769310 ) ( -178450 1769310 )
+ + LAYER met4 ( -361550 -1769310 ) ( -358450 1769310 )
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+ + LAYER met4 ( -721550 -1769310 ) ( -718450 1769310 )
+ + LAYER met4 ( -901550 540160 ) ( -898450 1769310 )
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+ + LAYER met4 ( -1801550 -1769310 ) ( -1798450 1769310 )
+ + LAYER met4 ( -1981550 -1769310 ) ( -1978450 1769310 )
+ + LAYER met4 ( -2161550 -1769310 ) ( -2158450 1769310 )
+ + LAYER met4 ( -2341550 -1769310 ) ( -2338450 1769310 )
+ + LAYER met4 ( -2521550 -1769310 ) ( -2518450 1769310 )
+ + LAYER met4 ( -2701550 -1769310 ) ( -2698450 1769310 )
+ + LAYER met4 ( -2881550 -1769310 ) ( -2878450 1769310 )
+ + LAYER met4 ( 36030 -1764510 ) ( 39130 1764510 )
+ + LAYER met4 ( -2900550 -1764510 ) ( -2897450 1764510 )
+ + LAYER met4 ( -901550 -1769310 ) ( -898450 -79840 )
+ + LAYER met4 ( -1081550 -1769310 ) ( -1078450 -79840 )
+ + LAYER met4 ( -1261550 -1769310 ) ( -1258450 -79840 )
+ + LAYER met4 ( -1441550 -1769310 ) ( -1438450 -79840 )
+ + LAYER met4 ( -1621550 -1769310 ) ( -1618450 -79840 )
+ + LAYER met5 ( -2900550 1761410 ) ( 39130 1764510 )
+ + LAYER met5 ( -2905350 1674490 ) ( 43930 1677590 )
+ + LAYER met5 ( -2905350 1494490 ) ( 43930 1497590 )
+ + LAYER met5 ( -2905350 1314490 ) ( 43930 1317590 )
+ + LAYER met5 ( -2905350 1134490 ) ( 43930 1137590 )
+ + LAYER met5 ( -2905350 954490 ) ( 43930 957590 )
+ + LAYER met5 ( -2905350 774490 ) ( 43930 777590 )
+ + LAYER met5 ( -2905350 594490 ) ( 43930 597590 )
+ + LAYER met5 ( -2905350 414490 ) ( 43930 417590 )
+ + LAYER met5 ( -2905350 234490 ) ( 43930 237590 )
+ + LAYER met5 ( -2905350 54490 ) ( 43930 57590 )
+ + LAYER met5 ( -2905350 -125510 ) ( 43930 -122410 )
+ + LAYER met5 ( -2905350 -305510 ) ( 43930 -302410 )
+ + LAYER met5 ( -2905350 -485510 ) ( 43930 -482410 )
+ + LAYER met5 ( -2905350 -665510 ) ( 43930 -662410 )
+ + LAYER met5 ( -2905350 -845510 ) ( 43930 -842410 )
+ + LAYER met5 ( -2905350 -1025510 ) ( 43930 -1022410 )
+ + LAYER met5 ( -2905350 -1205510 ) ( 43930 -1202410 )
+ + LAYER met5 ( -2905350 -1385510 ) ( 43930 -1382410 )
+ + LAYER met5 ( -2905350 -1565510 ) ( 43930 -1562410 )
+ + LAYER met5 ( -2905350 -1745510 ) ( 43930 -1742410 )
+ + LAYER met5 ( -2900550 -1764510 ) ( 39130 -1761410 )
+ + FIXED ( 2890520 1759840 ) N ;
+ - vccd2 + NET vccd2 + SPECIAL + DIRECTION INPUT + USE POWER
+ + PORT
+ + LAYER met4 ( -1550 -1778910 ) ( 1550 1778910 )
+ + LAYER met4 ( -181550 -1778910 ) ( -178450 1778910 )
+ + LAYER met4 ( -361550 -1778910 ) ( -358450 1778910 )
+ + LAYER met4 ( -541550 -1778910 ) ( -538450 1778910 )
+ + LAYER met4 ( -721550 -1778910 ) ( -718450 1778910 )
+ + LAYER met4 ( -901550 540160 ) ( -898450 1778910 )
+ + LAYER met4 ( -1081550 540160 ) ( -1078450 1778910 )
+ + LAYER met4 ( -1261550 540160 ) ( -1258450 1778910 )
+ + LAYER met4 ( -1441550 540160 ) ( -1438450 1778910 )
+ + LAYER met4 ( -1621550 540160 ) ( -1618450 1778910 )
+ + LAYER met4 ( -1801550 -1778910 ) ( -1798450 1778910 )
+ + LAYER met4 ( -1981550 -1778910 ) ( -1978450 1778910 )
+ + LAYER met4 ( -2161550 -1778910 ) ( -2158450 1778910 )
+ + LAYER met4 ( -2341550 -1778910 ) ( -2338450 1778910 )
+ + LAYER met4 ( -2521550 -1778910 ) ( -2518450 1778910 )
+ + LAYER met4 ( -2701550 -1778910 ) ( -2698450 1778910 )
+ + LAYER met4 ( -2881550 -1778910 ) ( -2878450 1778910 )
+ + LAYER met4 ( 27030 -1774110 ) ( 30130 1774110 )
+ + LAYER met4 ( -2928750 -1774110 ) ( -2925650 1774110 )
+ + LAYER met4 ( -901550 -1778910 ) ( -898450 -79840 )
+ + LAYER met4 ( -1081550 -1778910 ) ( -1078450 -79840 )
+ + LAYER met4 ( -1261550 -1778910 ) ( -1258450 -79840 )
+ + LAYER met4 ( -1441550 -1778910 ) ( -1438450 -79840 )
+ + LAYER met4 ( -1621550 -1778910 ) ( -1618450 -79840 )
+ + LAYER met5 ( -2928750 1771010 ) ( 30130 1774110 )
+ + LAYER met5 ( -2933550 1693090 ) ( 34930 1696190 )
+ + LAYER met5 ( -2933550 1513090 ) ( 34930 1516190 )
+ + LAYER met5 ( -2933550 1333090 ) ( 34930 1336190 )
+ + LAYER met5 ( -2933550 1153090 ) ( 34930 1156190 )
+ + LAYER met5 ( -2933550 973090 ) ( 34930 976190 )
+ + LAYER met5 ( -2933550 793090 ) ( 34930 796190 )
+ + LAYER met5 ( -2933550 613090 ) ( 34930 616190 )
+ + LAYER met5 ( -2933550 433090 ) ( 34930 436190 )
+ + LAYER met5 ( -2933550 253090 ) ( 34930 256190 )
+ + LAYER met5 ( -2933550 73090 ) ( 34930 76190 )
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+ + LAYER met5 ( -2933550 -286910 ) ( 34930 -283810 )
+ + LAYER met5 ( -2933550 -466910 ) ( 34930 -463810 )
+ + LAYER met5 ( -2933550 -646910 ) ( 34930 -643810 )
+ + LAYER met5 ( -2933550 -826910 ) ( 34930 -823810 )
+ + LAYER met5 ( -2933550 -1006910 ) ( 34930 -1003810 )
+ + LAYER met5 ( -2933550 -1186910 ) ( 34930 -1183810 )
+ + LAYER met5 ( -2933550 -1366910 ) ( 34930 -1363810 )
+ + LAYER met5 ( -2933550 -1546910 ) ( 34930 -1543810 )
+ + LAYER met5 ( -2933550 -1726910 ) ( 34930 -1723810 )
+ + LAYER met5 ( -2928750 -1774110 ) ( 30130 -1771010 )
+ + FIXED ( 2909120 1759840 ) N ;
+ - vdda1 + NET vdda1 + SPECIAL + DIRECTION INPUT + USE POWER
+ + PORT
+ + LAYER met4 ( -1550 -1788510 ) ( 1550 1788510 )
+ + LAYER met4 ( -181550 -1788510 ) ( -178450 1788510 )
+ + LAYER met4 ( -361550 -1788510 ) ( -358450 1788510 )
+ + LAYER met4 ( -541550 -1788510 ) ( -538450 1788510 )
+ + LAYER met4 ( -721550 540160 ) ( -718450 1788510 )
+ + LAYER met4 ( -901550 540160 ) ( -898450 1788510 )
+ + LAYER met4 ( -1081550 540160 ) ( -1078450 1788510 )
+ + LAYER met4 ( -1261550 540160 ) ( -1258450 1788510 )
+ + LAYER met4 ( -1441550 540160 ) ( -1438450 1788510 )
+ + LAYER met4 ( -1621550 -1788510 ) ( -1618450 1788510 )
+ + LAYER met4 ( -1801550 -1788510 ) ( -1798450 1788510 )
+ + LAYER met4 ( -1981550 -1788510 ) ( -1978450 1788510 )
+ + LAYER met4 ( -2161550 -1788510 ) ( -2158450 1788510 )
+ + LAYER met4 ( -2341550 -1788510 ) ( -2338450 1788510 )
+ + LAYER met4 ( -2521550 -1788510 ) ( -2518450 1788510 )
+ + LAYER met4 ( -2701550 -1788510 ) ( -2698450 1788510 )
+ + LAYER met4 ( 198030 -1783710 ) ( 201130 1783710 )
+ + LAYER met4 ( -2776950 -1783710 ) ( -2773850 1783710 )
+ + LAYER met4 ( -721550 -1788510 ) ( -718450 -79840 )
+ + LAYER met4 ( -901550 -1788510 ) ( -898450 -79840 )
+ + LAYER met4 ( -1081550 -1788510 ) ( -1078450 -79840 )
+ + LAYER met4 ( -1261550 -1788510 ) ( -1258450 -79840 )
+ + LAYER met4 ( -1441550 -1788510 ) ( -1438450 -79840 )
+ + LAYER met5 ( -2776950 1780610 ) ( 201130 1783710 )
+ + LAYER met5 ( -2781750 1711690 ) ( 205930 1714790 )
+ + LAYER met5 ( -2781750 1531690 ) ( 205930 1534790 )
+ + LAYER met5 ( -2781750 1351690 ) ( 205930 1354790 )
+ + LAYER met5 ( -2781750 1171690 ) ( 205930 1174790 )
+ + LAYER met5 ( -2781750 991690 ) ( 205930 994790 )
+ + LAYER met5 ( -2781750 811690 ) ( 205930 814790 )
+ + LAYER met5 ( -2781750 631690 ) ( 205930 634790 )
+ + LAYER met5 ( -2781750 451690 ) ( 205930 454790 )
+ + LAYER met5 ( -2781750 271690 ) ( 205930 274790 )
+ + LAYER met5 ( -2781750 91690 ) ( 205930 94790 )
+ + LAYER met5 ( -2781750 -88310 ) ( 205930 -85210 )
+ + LAYER met5 ( -2781750 -268310 ) ( 205930 -265210 )
+ + LAYER met5 ( -2781750 -448310 ) ( 205930 -445210 )
+ + LAYER met5 ( -2781750 -628310 ) ( 205930 -625210 )
+ + LAYER met5 ( -2781750 -808310 ) ( 205930 -805210 )
+ + LAYER met5 ( -2781750 -988310 ) ( 205930 -985210 )
+ + LAYER met5 ( -2781750 -1168310 ) ( 205930 -1165210 )
+ + LAYER met5 ( -2781750 -1348310 ) ( 205930 -1345210 )
+ + LAYER met5 ( -2781750 -1528310 ) ( 205930 -1525210 )
+ + LAYER met5 ( -2781750 -1708310 ) ( 205930 -1705210 )
+ + LAYER met5 ( -2776950 -1783710 ) ( 201130 -1780610 )
+ + FIXED ( 2747720 1759840 ) N ;
+ - vdda2 + NET vdda2 + SPECIAL + DIRECTION INPUT + USE POWER
+ + PORT
+ + LAYER met4 ( -1550 -1798110 ) ( 1550 1798110 )
+ + LAYER met4 ( -181550 -1798110 ) ( -178450 1798110 )
+ + LAYER met4 ( -361550 -1798110 ) ( -358450 1798110 )
+ + LAYER met4 ( -541550 -1798110 ) ( -538450 1798110 )
+ + LAYER met4 ( -721550 540160 ) ( -718450 1798110 )
+ + LAYER met4 ( -901550 540160 ) ( -898450 1798110 )
+ + LAYER met4 ( -1081550 540160 ) ( -1078450 1798110 )
+ + LAYER met4 ( -1261550 540160 ) ( -1258450 1798110 )
+ + LAYER met4 ( -1441550 540160 ) ( -1438450 1798110 )
+ + LAYER met4 ( -1621550 -1798110 ) ( -1618450 1798110 )
+ + LAYER met4 ( -1801550 -1798110 ) ( -1798450 1798110 )
+ + LAYER met4 ( -1981550 -1798110 ) ( -1978450 1798110 )
+ + LAYER met4 ( -2161550 -1798110 ) ( -2158450 1798110 )
+ + LAYER met4 ( -2341550 -1798110 ) ( -2338450 1798110 )
+ + LAYER met4 ( -2521550 -1798110 ) ( -2518450 1798110 )
+ + LAYER met4 ( -2701550 -1798110 ) ( -2698450 1798110 )
+ + LAYER met4 ( 189030 -1793310 ) ( 192130 1793310 )
+ + LAYER met4 ( -2805150 -1793310 ) ( -2802050 1793310 )
+ + LAYER met4 ( -721550 -1798110 ) ( -718450 -79840 )
+ + LAYER met4 ( -901550 -1798110 ) ( -898450 -79840 )
+ + LAYER met4 ( -1081550 -1798110 ) ( -1078450 -79840 )
+ + LAYER met4 ( -1261550 -1798110 ) ( -1258450 -79840 )
+ + LAYER met4 ( -1441550 -1798110 ) ( -1438450 -79840 )
+ + LAYER met5 ( -2805150 1790210 ) ( 192130 1793310 )
+ + LAYER met5 ( -2809950 1730290 ) ( 196930 1733390 )
+ + LAYER met5 ( -2809950 1550290 ) ( 196930 1553390 )
+ + LAYER met5 ( -2809950 1370290 ) ( 196930 1373390 )
+ + LAYER met5 ( -2809950 1190290 ) ( 196930 1193390 )
+ + LAYER met5 ( -2809950 1010290 ) ( 196930 1013390 )
+ + LAYER met5 ( -2809950 830290 ) ( 196930 833390 )
+ + LAYER met5 ( -2809950 650290 ) ( 196930 653390 )
+ + LAYER met5 ( -2809950 470290 ) ( 196930 473390 )
+ + LAYER met5 ( -2809950 290290 ) ( 196930 293390 )
+ + LAYER met5 ( -2809950 110290 ) ( 196930 113390 )
+ + LAYER met5 ( -2809950 -69710 ) ( 196930 -66610 )
+ + LAYER met5 ( -2809950 -249710 ) ( 196930 -246610 )
+ + LAYER met5 ( -2809950 -429710 ) ( 196930 -426610 )
+ + LAYER met5 ( -2809950 -609710 ) ( 196930 -606610 )
+ + LAYER met5 ( -2809950 -789710 ) ( 196930 -786610 )
+ + LAYER met5 ( -2809950 -969710 ) ( 196930 -966610 )
+ + LAYER met5 ( -2809950 -1149710 ) ( 196930 -1146610 )
+ + LAYER met5 ( -2809950 -1329710 ) ( 196930 -1326610 )
+ + LAYER met5 ( -2809950 -1509710 ) ( 196930 -1506610 )
+ + LAYER met5 ( -2809950 -1689710 ) ( 196930 -1686610 )
+ + LAYER met5 ( -2805150 -1793310 ) ( 192130 -1790210 )
+ + FIXED ( 2766320 1759840 ) N ;
+ - vssa1 + NET vssa1 + SPECIAL + DIRECTION INPUT + USE GROUND
+ + PORT
+ + LAYER met4 ( -1550 -1788510 ) ( 1550 1788510 )
+ + LAYER met4 ( -115930 -1788510 ) ( -112830 1788510 )
+ + LAYER met4 ( -295930 -1788510 ) ( -292830 1788510 )
+ + LAYER met4 ( -475930 -1788510 ) ( -472830 1788510 )
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+ + LAYER met4 ( -1555930 540160 ) ( -1552830 1788510 )
+ + LAYER met4 ( -1735930 540160 ) ( -1732830 1788510 )
+ + LAYER met4 ( -1915930 -1788510 ) ( -1912830 1788510 )
+ + LAYER met4 ( -2095930 -1788510 ) ( -2092830 1788510 )
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+ + LAYER met4 ( -1195930 -1788510 ) ( -1192830 -79840 )
+ + LAYER met4 ( -1375930 -1788510 ) ( -1372830 -79840 )
+ + LAYER met4 ( -1555930 -1788510 ) ( -1552830 -79840 )
+ + LAYER met4 ( -1735930 -1788510 ) ( -1732830 -79840 )
+ + LAYER met5 ( -2986130 1785410 ) ( 1550 1788510 )
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+ + LAYER met5 ( -2986130 1441690 ) ( 1550 1444790 )
+ + LAYER met5 ( -2986130 1261690 ) ( 1550 1264790 )
+ + LAYER met5 ( -2986130 1081690 ) ( 1550 1084790 )
+ + LAYER met5 ( -2986130 901690 ) ( 1550 904790 )
+ + LAYER met5 ( -2986130 721690 ) ( 1550 724790 )
+ + LAYER met5 ( -2986130 541690 ) ( 1550 544790 )
+ + LAYER met5 ( -2986130 361690 ) ( 1550 364790 )
+ + LAYER met5 ( -2986130 181690 ) ( 1550 184790 )
+ + LAYER met5 ( -2986130 1690 ) ( 1550 4790 )
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+ + LAYER met5 ( -2986130 -358310 ) ( 1550 -355210 )
+ + LAYER met5 ( -2986130 -538310 ) ( 1550 -535210 )
+ + LAYER met5 ( -2986130 -718310 ) ( 1550 -715210 )
+ + LAYER met5 ( -2986130 -898310 ) ( 1550 -895210 )
+ + LAYER met5 ( -2986130 -1078310 ) ( 1550 -1075210 )
+ + LAYER met5 ( -2986130 -1258310 ) ( 1550 -1255210 )
+ + LAYER met5 ( -2986130 -1438310 ) ( 1550 -1435210 )
+ + LAYER met5 ( -2986130 -1618310 ) ( 1550 -1615210 )
+ + LAYER met5 ( -2986130 -1788510 ) ( 1550 -1785410 )
+ + FIXED ( 2952100 1759840 ) N ;
+ - vssa2 + NET vssa2 + SPECIAL + DIRECTION INPUT + USE GROUND
+ + PORT
+ + LAYER met4 ( -1550 -1798110 ) ( 1550 1798110 )
+ + LAYER met4 ( -106930 -1798110 ) ( -103830 1798110 )
+ + LAYER met4 ( -286930 -1798110 ) ( -283830 1798110 )
+ + LAYER met4 ( -466930 -1798110 ) ( -463830 1798110 )
+ + LAYER met4 ( -646930 -1798110 ) ( -643830 1798110 )
+ + LAYER met4 ( -826930 -1798110 ) ( -823830 1798110 )
+ + LAYER met4 ( -1006930 540160 ) ( -1003830 1798110 )
+ + LAYER met4 ( -1186930 540160 ) ( -1183830 1798110 )
+ + LAYER met4 ( -1366930 540160 ) ( -1363830 1798110 )
+ + LAYER met4 ( -1546930 540160 ) ( -1543830 1798110 )
+ + LAYER met4 ( -1726930 540160 ) ( -1723830 1798110 )
+ + LAYER met4 ( -1906930 -1798110 ) ( -1903830 1798110 )
+ + LAYER met4 ( -2086930 -1798110 ) ( -2083830 1798110 )
+ + LAYER met4 ( -2266930 -1798110 ) ( -2263830 1798110 )
+ + LAYER met4 ( -2446930 -1798110 ) ( -2443830 1798110 )
+ + LAYER met4 ( -2626930 -1798110 ) ( -2623830 1798110 )
+ + LAYER met4 ( -2806930 -1798110 ) ( -2803830 1798110 )
+ + LAYER met4 ( -3005330 -1798110 ) ( -3002230 1798110 )
+ + LAYER met4 ( -1006930 -1798110 ) ( -1003830 -79840 )
+ + LAYER met4 ( -1186930 -1798110 ) ( -1183830 -79840 )
+ + LAYER met4 ( -1366930 -1798110 ) ( -1363830 -79840 )
+ + LAYER met4 ( -1546930 -1798110 ) ( -1543830 -79840 )
+ + LAYER met4 ( -1726930 -1798110 ) ( -1723830 -79840 )
+ + LAYER met5 ( -3005330 1795010 ) ( 1550 1798110 )
+ + LAYER met5 ( -3005330 1640290 ) ( 1550 1643390 )
+ + LAYER met5 ( -3005330 1460290 ) ( 1550 1463390 )
+ + LAYER met5 ( -3005330 1280290 ) ( 1550 1283390 )
+ + LAYER met5 ( -3005330 1100290 ) ( 1550 1103390 )
+ + LAYER met5 ( -3005330 920290 ) ( 1550 923390 )
+ + LAYER met5 ( -3005330 740290 ) ( 1550 743390 )
+ + LAYER met5 ( -3005330 560290 ) ( 1550 563390 )
+ + LAYER met5 ( -3005330 380290 ) ( 1550 383390 )
+ + LAYER met5 ( -3005330 200290 ) ( 1550 203390 )
+ + LAYER met5 ( -3005330 20290 ) ( 1550 23390 )
+ + LAYER met5 ( -3005330 -159710 ) ( 1550 -156610 )
+ + LAYER met5 ( -3005330 -339710 ) ( 1550 -336610 )
+ + LAYER met5 ( -3005330 -519710 ) ( 1550 -516610 )
+ + LAYER met5 ( -3005330 -699710 ) ( 1550 -696610 )
+ + LAYER met5 ( -3005330 -879710 ) ( 1550 -876610 )
+ + LAYER met5 ( -3005330 -1059710 ) ( 1550 -1056610 )
+ + LAYER met5 ( -3005330 -1239710 ) ( 1550 -1236610 )
+ + LAYER met5 ( -3005330 -1419710 ) ( 1550 -1416610 )
+ + LAYER met5 ( -3005330 -1599710 ) ( 1550 -1596610 )
+ + LAYER met5 ( -3005330 -1798110 ) ( 1550 -1795010 )
+ + FIXED ( 2961700 1759840 ) N ;
+ - vssd1 + NET vssd1 + SPECIAL + DIRECTION INPUT + USE GROUND
+ + PORT
+ + LAYER met4 ( -1550 -1769310 ) ( 1550 1769310 )
+ + LAYER met4 ( -133930 -1769310 ) ( -130830 1769310 )
+ + LAYER met4 ( -313930 -1769310 ) ( -310830 1769310 )
+ + LAYER met4 ( -493930 -1769310 ) ( -490830 1769310 )
+ + LAYER met4 ( -673930 -1769310 ) ( -670830 1769310 )
+ + LAYER met4 ( -853930 540160 ) ( -850830 1769310 )
+ + LAYER met4 ( -1033930 540160 ) ( -1030830 1769310 )
+ + LAYER met4 ( -1213930 540160 ) ( -1210830 1769310 )
+ + LAYER met4 ( -1393930 540160 ) ( -1390830 1769310 )
+ + LAYER met4 ( -1573930 540160 ) ( -1570830 1769310 )
+ + LAYER met4 ( -1753930 540160 ) ( -1750830 1769310 )
+ + LAYER met4 ( -1933930 -1769310 ) ( -1930830 1769310 )
+ + LAYER met4 ( -2113930 -1769310 ) ( -2110830 1769310 )
+ + LAYER met4 ( -2293930 -1769310 ) ( -2290830 1769310 )
+ + LAYER met4 ( -2473930 -1769310 ) ( -2470830 1769310 )
+ + LAYER met4 ( -2653930 -1769310 ) ( -2650830 1769310 )
+ + LAYER met4 ( -2833930 -1769310 ) ( -2830830 1769310 )
+ + LAYER met4 ( -2947730 -1769310 ) ( -2944630 1769310 )
+ + LAYER met4 ( -853930 -1769310 ) ( -850830 -79840 )
+ + LAYER met4 ( -1033930 -1769310 ) ( -1030830 -79840 )
+ + LAYER met4 ( -1213930 -1769310 ) ( -1210830 -79840 )
+ + LAYER met4 ( -1393930 -1769310 ) ( -1390830 -79840 )
+ + LAYER met4 ( -1573930 -1769310 ) ( -1570830 -79840 )
+ + LAYER met4 ( -1753930 -1769310 ) ( -1750830 -79840 )
+ + LAYER met5 ( -2947730 1766210 ) ( 1550 1769310 )
+ + LAYER met5 ( -2947730 1584490 ) ( 1550 1587590 )
+ + LAYER met5 ( -2947730 1404490 ) ( 1550 1407590 )
+ + LAYER met5 ( -2947730 1224490 ) ( 1550 1227590 )
+ + LAYER met5 ( -2947730 1044490 ) ( 1550 1047590 )
+ + LAYER met5 ( -2947730 864490 ) ( 1550 867590 )
+ + LAYER met5 ( -2947730 684490 ) ( 1550 687590 )
+ + LAYER met5 ( -2947730 504490 ) ( 1550 507590 )
+ + LAYER met5 ( -2947730 324490 ) ( 1550 327590 )
+ + LAYER met5 ( -2947730 144490 ) ( 1550 147590 )
+ + LAYER met5 ( -2947730 -35510 ) ( 1550 -32410 )
+ + LAYER met5 ( -2947730 -215510 ) ( 1550 -212410 )
+ + LAYER met5 ( -2947730 -395510 ) ( 1550 -392410 )
+ + LAYER met5 ( -2947730 -575510 ) ( 1550 -572410 )
+ + LAYER met5 ( -2947730 -755510 ) ( 1550 -752410 )
+ + LAYER met5 ( -2947730 -935510 ) ( 1550 -932410 )
+ + LAYER met5 ( -2947730 -1115510 ) ( 1550 -1112410 )
+ + LAYER met5 ( -2947730 -1295510 ) ( 1550 -1292410 )
+ + LAYER met5 ( -2947730 -1475510 ) ( 1550 -1472410 )
+ + LAYER met5 ( -2947730 -1655510 ) ( 1550 -1652410 )
+ + LAYER met5 ( -2947730 -1769310 ) ( 1550 -1766210 )
+ + FIXED ( 2932900 1759840 ) N ;
+ - vssd2 + NET vssd2 + SPECIAL + DIRECTION INPUT + USE GROUND
+ + PORT
+ + LAYER met4 ( -1550 -1778910 ) ( 1550 1778910 )
+ + LAYER met4 ( -124930 -1778910 ) ( -121830 1778910 )
+ + LAYER met4 ( -304930 -1778910 ) ( -301830 1778910 )
+ + LAYER met4 ( -484930 -1778910 ) ( -481830 1778910 )
+ + LAYER met4 ( -664930 -1778910 ) ( -661830 1778910 )
+ + LAYER met4 ( -844930 -1778910 ) ( -841830 1778910 )
+ + LAYER met4 ( -1024930 540160 ) ( -1021830 1778910 )
+ + LAYER met4 ( -1204930 540160 ) ( -1201830 1778910 )
+ + LAYER met4 ( -1384930 540160 ) ( -1381830 1778910 )
+ + LAYER met4 ( -1564930 540160 ) ( -1561830 1778910 )
+ + LAYER met4 ( -1744930 540160 ) ( -1741830 1778910 )
+ + LAYER met4 ( -1924930 -1778910 ) ( -1921830 1778910 )
+ + LAYER met4 ( -2104930 -1778910 ) ( -2101830 1778910 )
+ + LAYER met4 ( -2284930 -1778910 ) ( -2281830 1778910 )
+ + LAYER met4 ( -2464930 -1778910 ) ( -2461830 1778910 )
+ + LAYER met4 ( -2644930 -1778910 ) ( -2641830 1778910 )
+ + LAYER met4 ( -2824930 -1778910 ) ( -2821830 1778910 )
+ + LAYER met4 ( -2966930 -1778910 ) ( -2963830 1778910 )
+ + LAYER met4 ( -1024930 -1778910 ) ( -1021830 -79840 )
+ + LAYER met4 ( -1204930 -1778910 ) ( -1201830 -79840 )
+ + LAYER met4 ( -1384930 -1778910 ) ( -1381830 -79840 )
+ + LAYER met4 ( -1564930 -1778910 ) ( -1561830 -79840 )
+ + LAYER met4 ( -1744930 -1778910 ) ( -1741830 -79840 )
+ + LAYER met5 ( -2966930 1775810 ) ( 1550 1778910 )
+ + LAYER met5 ( -2966930 1603090 ) ( 1550 1606190 )
+ + LAYER met5 ( -2966930 1423090 ) ( 1550 1426190 )
+ + LAYER met5 ( -2966930 1243090 ) ( 1550 1246190 )
+ + LAYER met5 ( -2966930 1063090 ) ( 1550 1066190 )
+ + LAYER met5 ( -2966930 883090 ) ( 1550 886190 )
+ + LAYER met5 ( -2966930 703090 ) ( 1550 706190 )
+ + LAYER met5 ( -2966930 523090 ) ( 1550 526190 )
+ + LAYER met5 ( -2966930 343090 ) ( 1550 346190 )
+ + LAYER met5 ( -2966930 163090 ) ( 1550 166190 )
+ + LAYER met5 ( -2966930 -16910 ) ( 1550 -13810 )
+ + LAYER met5 ( -2966930 -196910 ) ( 1550 -193810 )
+ + LAYER met5 ( -2966930 -376910 ) ( 1550 -373810 )
+ + LAYER met5 ( -2966930 -556910 ) ( 1550 -553810 )
+ + LAYER met5 ( -2966930 -736910 ) ( 1550 -733810 )
+ + LAYER met5 ( -2966930 -916910 ) ( 1550 -913810 )
+ + LAYER met5 ( -2966930 -1096910 ) ( 1550 -1093810 )
+ + LAYER met5 ( -2966930 -1276910 ) ( 1550 -1273810 )
+ + LAYER met5 ( -2966930 -1456910 ) ( 1550 -1453810 )
+ + LAYER met5 ( -2966930 -1636910 ) ( 1550 -1633810 )
+ + LAYER met5 ( -2966930 -1778910 ) ( 1550 -1775810 )
+ + FIXED ( 2942500 1759840 ) N ;
+ - wb_clk_i + NET wb_clk_i + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2990 -1200 ) N ;
+ - wb_rst_i + NET wb_rst_i + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 8510 -1200 ) N ;
+ - wbs_ack_o + NET wbs_ack_o + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 14490 -1200 ) N ;
+ - wbs_adr_i[0] + NET wbs_adr_i[0] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 38410 -1200 ) N ;
+ - wbs_adr_i[10] + NET wbs_adr_i[10] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 239430 -1200 ) N ;
+ - wbs_adr_i[11] + NET wbs_adr_i[11] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 256910 -1200 ) N ;
+ - wbs_adr_i[12] + NET wbs_adr_i[12] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 274850 -1200 ) N ;
+ - wbs_adr_i[13] + NET wbs_adr_i[13] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 292330 -1200 ) N ;
+ - wbs_adr_i[14] + NET wbs_adr_i[14] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 310270 -1200 ) N ;
+ - wbs_adr_i[15] + NET wbs_adr_i[15] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 327750 -1200 ) N ;
+ - wbs_adr_i[16] + NET wbs_adr_i[16] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 345690 -1200 ) N ;
+ - wbs_adr_i[17] + NET wbs_adr_i[17] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 363170 -1200 ) N ;
+ - wbs_adr_i[18] + NET wbs_adr_i[18] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 381110 -1200 ) N ;
+ - wbs_adr_i[19] + NET wbs_adr_i[19] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 398590 -1200 ) N ;
+ - wbs_adr_i[1] + NET wbs_adr_i[1] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 61870 -1200 ) N ;
+ - wbs_adr_i[20] + NET wbs_adr_i[20] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 416530 -1200 ) N ;
+ - wbs_adr_i[21] + NET wbs_adr_i[21] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 434470 -1200 ) N ;
+ - wbs_adr_i[22] + NET wbs_adr_i[22] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 451950 -1200 ) N ;
+ - wbs_adr_i[23] + NET wbs_adr_i[23] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 469890 -1200 ) N ;
+ - wbs_adr_i[24] + NET wbs_adr_i[24] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 487370 -1200 ) N ;
+ - wbs_adr_i[25] + NET wbs_adr_i[25] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 505310 -1200 ) N ;
+ - wbs_adr_i[26] + NET wbs_adr_i[26] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 522790 -1200 ) N ;
+ - wbs_adr_i[27] + NET wbs_adr_i[27] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 540730 -1200 ) N ;
+ - wbs_adr_i[28] + NET wbs_adr_i[28] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 558210 -1200 ) N ;
+ - wbs_adr_i[29] + NET wbs_adr_i[29] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 576150 -1200 ) N ;
+ - wbs_adr_i[2] + NET wbs_adr_i[2] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 85330 -1200 ) N ;
+ - wbs_adr_i[30] + NET wbs_adr_i[30] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 594090 -1200 ) N ;
+ - wbs_adr_i[31] + NET wbs_adr_i[31] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 611570 -1200 ) N ;
+ - wbs_adr_i[3] + NET wbs_adr_i[3] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 109250 -1200 ) N ;
+ - wbs_adr_i[4] + NET wbs_adr_i[4] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 132710 -1200 ) N ;
+ - wbs_adr_i[5] + NET wbs_adr_i[5] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 150650 -1200 ) N ;
+ - wbs_adr_i[6] + NET wbs_adr_i[6] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 168130 -1200 ) N ;
+ - wbs_adr_i[7] + NET wbs_adr_i[7] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 186070 -1200 ) N ;
+ - wbs_adr_i[8] + NET wbs_adr_i[8] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 203550 -1200 ) N ;
+ - wbs_adr_i[9] + NET wbs_adr_i[9] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 221490 -1200 ) N ;
+ - wbs_cyc_i + NET wbs_cyc_i + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 20470 -1200 ) N ;
+ - wbs_dat_i[0] + NET wbs_dat_i[0] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 43930 -1200 ) N ;
+ - wbs_dat_i[10] + NET wbs_dat_i[10] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 244950 -1200 ) N ;
+ - wbs_dat_i[11] + NET wbs_dat_i[11] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 262890 -1200 ) N ;
+ - wbs_dat_i[12] + NET wbs_dat_i[12] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 280370 -1200 ) N ;
+ - wbs_dat_i[13] + NET wbs_dat_i[13] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 298310 -1200 ) N ;
+ - wbs_dat_i[14] + NET wbs_dat_i[14] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 316250 -1200 ) N ;
+ - wbs_dat_i[15] + NET wbs_dat_i[15] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 333730 -1200 ) N ;
+ - wbs_dat_i[16] + NET wbs_dat_i[16] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 351670 -1200 ) N ;
+ - wbs_dat_i[17] + NET wbs_dat_i[17] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 369150 -1200 ) N ;
+ - wbs_dat_i[18] + NET wbs_dat_i[18] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 387090 -1200 ) N ;
+ - wbs_dat_i[19] + NET wbs_dat_i[19] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 404570 -1200 ) N ;
+ - wbs_dat_i[1] + NET wbs_dat_i[1] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 67850 -1200 ) N ;
+ - wbs_dat_i[20] + NET wbs_dat_i[20] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 422510 -1200 ) N ;
+ - wbs_dat_i[21] + NET wbs_dat_i[21] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 439990 -1200 ) N ;
+ - wbs_dat_i[22] + NET wbs_dat_i[22] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 457930 -1200 ) N ;
+ - wbs_dat_i[23] + NET wbs_dat_i[23] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 475870 -1200 ) N ;
+ - wbs_dat_i[24] + NET wbs_dat_i[24] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 493350 -1200 ) N ;
+ - wbs_dat_i[25] + NET wbs_dat_i[25] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 511290 -1200 ) N ;
+ - wbs_dat_i[26] + NET wbs_dat_i[26] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 528770 -1200 ) N ;
+ - wbs_dat_i[27] + NET wbs_dat_i[27] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 546710 -1200 ) N ;
+ - wbs_dat_i[28] + NET wbs_dat_i[28] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 564190 -1200 ) N ;
+ - wbs_dat_i[29] + NET wbs_dat_i[29] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 582130 -1200 ) N ;
+ - wbs_dat_i[2] + NET wbs_dat_i[2] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 91310 -1200 ) N ;
+ - wbs_dat_i[30] + NET wbs_dat_i[30] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 599610 -1200 ) N ;
+ - wbs_dat_i[31] + NET wbs_dat_i[31] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 617550 -1200 ) N ;
+ - wbs_dat_i[3] + NET wbs_dat_i[3] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 115230 -1200 ) N ;
+ - wbs_dat_i[4] + NET wbs_dat_i[4] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 138690 -1200 ) N ;
+ - wbs_dat_i[5] + NET wbs_dat_i[5] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 156630 -1200 ) N ;
+ - wbs_dat_i[6] + NET wbs_dat_i[6] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 174110 -1200 ) N ;
+ - wbs_dat_i[7] + NET wbs_dat_i[7] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 192050 -1200 ) N ;
+ - wbs_dat_i[8] + NET wbs_dat_i[8] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 209530 -1200 ) N ;
+ - wbs_dat_i[9] + NET wbs_dat_i[9] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 227470 -1200 ) N ;
+ - wbs_dat_o[0] + NET wbs_dat_o[0] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 49910 -1200 ) N ;
+ - wbs_dat_o[10] + NET wbs_dat_o[10] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 250930 -1200 ) N ;
+ - wbs_dat_o[11] + NET wbs_dat_o[11] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 268870 -1200 ) N ;
+ - wbs_dat_o[12] + NET wbs_dat_o[12] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 286350 -1200 ) N ;
+ - wbs_dat_o[13] + NET wbs_dat_o[13] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 304290 -1200 ) N ;
+ - wbs_dat_o[14] + NET wbs_dat_o[14] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 321770 -1200 ) N ;
+ - wbs_dat_o[15] + NET wbs_dat_o[15] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 339710 -1200 ) N ;
+ - wbs_dat_o[16] + NET wbs_dat_o[16] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 357650 -1200 ) N ;
+ - wbs_dat_o[17] + NET wbs_dat_o[17] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 375130 -1200 ) N ;
+ - wbs_dat_o[18] + NET wbs_dat_o[18] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 393070 -1200 ) N ;
+ - wbs_dat_o[19] + NET wbs_dat_o[19] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 410550 -1200 ) N ;
+ - wbs_dat_o[1] + NET wbs_dat_o[1] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 73830 -1200 ) N ;
+ - wbs_dat_o[20] + NET wbs_dat_o[20] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 428490 -1200 ) N ;
+ - wbs_dat_o[21] + NET wbs_dat_o[21] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 445970 -1200 ) N ;
+ - wbs_dat_o[22] + NET wbs_dat_o[22] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 463910 -1200 ) N ;
+ - wbs_dat_o[23] + NET wbs_dat_o[23] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 481390 -1200 ) N ;
+ - wbs_dat_o[24] + NET wbs_dat_o[24] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 499330 -1200 ) N ;
+ - wbs_dat_o[25] + NET wbs_dat_o[25] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 516810 -1200 ) N ;
+ - wbs_dat_o[26] + NET wbs_dat_o[26] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 534750 -1200 ) N ;
+ - wbs_dat_o[27] + NET wbs_dat_o[27] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 552690 -1200 ) N ;
+ - wbs_dat_o[28] + NET wbs_dat_o[28] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 570170 -1200 ) N ;
+ - wbs_dat_o[29] + NET wbs_dat_o[29] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 588110 -1200 ) N ;
+ - wbs_dat_o[2] + NET wbs_dat_o[2] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 97290 -1200 ) N ;
+ - wbs_dat_o[30] + NET wbs_dat_o[30] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 605590 -1200 ) N ;
+ - wbs_dat_o[31] + NET wbs_dat_o[31] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 623530 -1200 ) N ;
+ - wbs_dat_o[3] + NET wbs_dat_o[3] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 121210 -1200 ) N ;
+ - wbs_dat_o[4] + NET wbs_dat_o[4] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 144670 -1200 ) N ;
+ - wbs_dat_o[5] + NET wbs_dat_o[5] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 162150 -1200 ) N ;
+ - wbs_dat_o[6] + NET wbs_dat_o[6] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 180090 -1200 ) N ;
+ - wbs_dat_o[7] + NET wbs_dat_o[7] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 198030 -1200 ) N ;
+ - wbs_dat_o[8] + NET wbs_dat_o[8] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 215510 -1200 ) N ;
+ - wbs_dat_o[9] + NET wbs_dat_o[9] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 233450 -1200 ) N ;
+ - wbs_sel_i[0] + NET wbs_sel_i[0] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 55890 -1200 ) N ;
+ - wbs_sel_i[1] + NET wbs_sel_i[1] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 79810 -1200 ) N ;
+ - wbs_sel_i[2] + NET wbs_sel_i[2] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 103270 -1200 ) N ;
+ - wbs_sel_i[3] + NET wbs_sel_i[3] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 126730 -1200 ) N ;
+ - wbs_stb_i + NET wbs_stb_i + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 26450 -1200 ) N ;
+ - wbs_we_i + NET wbs_we_i + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 32430 -1200 ) N ;
+END PINS
+SPECIALNETS 8 ;
+ - vccd1 ( PIN vccd1 ) + USE POWER
+ + ROUTED met4 0 + SHAPE STRIPE ( 1964840 2175880 ) via4_1600x3100
+ NEW met4 0 + SHAPE STRIPE ( 1811240 2175880 ) via4_1600x3100
+ NEW met4 0 + SHAPE STRIPE ( 1657640 2175880 ) via4_1600x3100
+ NEW met4 0 + SHAPE STRIPE ( 1504040 2175880 ) via4_1600x3100
+ NEW met4 0 + SHAPE STRIPE ( 1350440 2175880 ) via4_1600x3100
+ NEW met4 0 + SHAPE STRIPE ( 1196840 2175880 ) via4_1600x3100
+ NEW met4 0 + SHAPE STRIPE ( 1964840 1995880 ) via4_1600x3100
+ NEW met4 0 + SHAPE STRIPE ( 1811240 1995880 ) via4_1600x3100
+ NEW met4 0 + SHAPE STRIPE ( 1657640 1995880 ) via4_1600x3100
+ NEW met4 0 + SHAPE STRIPE ( 1504040 1995880 ) via4_1600x3100
+ NEW met4 0 + SHAPE STRIPE ( 1350440 1995880 ) via4_1600x3100
+ NEW met4 0 + SHAPE STRIPE ( 1196840 1995880 ) via4_1600x3100
+ NEW met4 0 + SHAPE STRIPE ( 1964840 1815880 ) via4_1600x3100
+ NEW met4 0 + SHAPE STRIPE ( 1811240 1815880 ) via4_1600x3100
+ NEW met4 0 + SHAPE STRIPE ( 1657640 1815880 ) via4_1600x3100
+ NEW met4 0 + SHAPE STRIPE ( 1504040 1815880 ) via4_1600x3100
+ NEW met4 0 + SHAPE STRIPE ( 1350440 1815880 ) via4_1600x3100
+ NEW met4 0 + SHAPE STRIPE ( 1196840 1815880 ) via4_1600x3100
+ NEW met4 0 + SHAPE STRIPE ( 2928100 3522800 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2890520 3522800 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2710520 3522800 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2530520 3522800 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2350520 3522800 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2170520 3522800 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1990520 3522800 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1810520 3522800 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1630520 3522800 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1450520 3522800 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1270520 3522800 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1090520 3522800 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 910520 3522800 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 730520 3522800 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 550520 3522800 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 370520 3522800 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 190520 3522800 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 10520 3522800 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -8480 3522800 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2928100 3435880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2890520 3435880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2710520 3435880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2530520 3435880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2350520 3435880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2170520 3435880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1990520 3435880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1810520 3435880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1630520 3435880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1450520 3435880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1270520 3435880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1090520 3435880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 910520 3435880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 730520 3435880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 550520 3435880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 370520 3435880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 190520 3435880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 10520 3435880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -8480 3435880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2928100 3255880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2890520 3255880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2710520 3255880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2530520 3255880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2350520 3255880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2170520 3255880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1990520 3255880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1810520 3255880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1630520 3255880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1450520 3255880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1270520 3255880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1090520 3255880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 910520 3255880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 730520 3255880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 550520 3255880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 370520 3255880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 190520 3255880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 10520 3255880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -8480 3255880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2928100 3075880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2890520 3075880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2710520 3075880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2530520 3075880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2350520 3075880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2170520 3075880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1990520 3075880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1810520 3075880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1630520 3075880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1450520 3075880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1270520 3075880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1090520 3075880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 910520 3075880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 730520 3075880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 550520 3075880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 370520 3075880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 190520 3075880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 10520 3075880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -8480 3075880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2928100 2895880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2890520 2895880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2710520 2895880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2530520 2895880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2350520 2895880 ) via4_3100x3100
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+ NEW met4 0 + SHAPE STRIPE ( 1270520 15880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1090520 15880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 910520 15880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 730520 15880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 550520 15880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 370520 15880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 190520 15880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 10520 15880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -8480 15880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2928100 -3120 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2890520 -3120 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2710520 -3120 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2530520 -3120 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2350520 -3120 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2170520 -3120 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1990520 -3120 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1810520 -3120 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1630520 -3120 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1450520 -3120 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1270520 -3120 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1090520 -3120 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 910520 -3120 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 730520 -3120 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 550520 -3120 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 370520 -3120 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 190520 -3120 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 10520 -3120 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -8480 -3120 ) via4_3100x3100
+ NEW met5 3100 + SHAPE STRIPE ( -10030 3522800 ) ( 2929650 3522800 )
+ NEW met5 3100 + SHAPE STRIPE ( -14830 3435880 ) ( 2934450 3435880 )
+ NEW met5 3100 + SHAPE STRIPE ( -14830 3255880 ) ( 2934450 3255880 )
+ NEW met5 3100 + SHAPE STRIPE ( -14830 3075880 ) ( 2934450 3075880 )
+ NEW met5 3100 + SHAPE STRIPE ( -14830 2895880 ) ( 2934450 2895880 )
+ NEW met5 3100 + SHAPE STRIPE ( -14830 2715880 ) ( 2934450 2715880 )
+ NEW met5 3100 + SHAPE STRIPE ( -14830 2535880 ) ( 2934450 2535880 )
+ NEW met5 3100 + SHAPE STRIPE ( -14830 2355880 ) ( 2934450 2355880 )
+ NEW met5 3100 + SHAPE STRIPE ( -14830 2175880 ) ( 2934450 2175880 )
+ NEW met5 3100 + SHAPE STRIPE ( -14830 1995880 ) ( 2934450 1995880 )
+ NEW met5 3100 + SHAPE STRIPE ( -14830 1815880 ) ( 2934450 1815880 )
+ NEW met5 3100 + SHAPE STRIPE ( -14830 1635880 ) ( 2934450 1635880 )
+ NEW met5 3100 + SHAPE STRIPE ( -14830 1455880 ) ( 2934450 1455880 )
+ NEW met5 3100 + SHAPE STRIPE ( -14830 1275880 ) ( 2934450 1275880 )
+ NEW met5 3100 + SHAPE STRIPE ( -14830 1095880 ) ( 2934450 1095880 )
+ NEW met5 3100 + SHAPE STRIPE ( -14830 915880 ) ( 2934450 915880 )
+ NEW met5 3100 + SHAPE STRIPE ( -14830 735880 ) ( 2934450 735880 )
+ NEW met5 3100 + SHAPE STRIPE ( -14830 555880 ) ( 2934450 555880 )
+ NEW met5 3100 + SHAPE STRIPE ( -14830 375880 ) ( 2934450 375880 )
+ NEW met5 3100 + SHAPE STRIPE ( -14830 195880 ) ( 2934450 195880 )
+ NEW met5 3100 + SHAPE STRIPE ( -14830 15880 ) ( 2934450 15880 )
+ NEW met5 3100 + SHAPE STRIPE ( -10030 -3120 ) ( 2929650 -3120 )
+ NEW met4 3100 + SHAPE STRIPE ( 2890520 -9470 ) ( 2890520 3529150 )
+ NEW met4 3100 + SHAPE STRIPE ( 2710520 -9470 ) ( 2710520 3529150 )
+ NEW met4 3100 + SHAPE STRIPE ( 2530520 -9470 ) ( 2530520 3529150 )
+ NEW met4 3100 + SHAPE STRIPE ( 2350520 -9470 ) ( 2350520 3529150 )
+ NEW met4 3100 + SHAPE STRIPE ( 2170520 -9470 ) ( 2170520 3529150 )
+ NEW met4 3100 + SHAPE STRIPE ( 1990520 2300000 ) ( 1990520 3529150 )
+ NEW met4 3100 + SHAPE STRIPE ( 1810520 2300000 ) ( 1810520 3529150 )
+ NEW met4 3100 + SHAPE STRIPE ( 1630520 2300000 ) ( 1630520 3529150 )
+ NEW met4 3100 + SHAPE STRIPE ( 1450520 2300000 ) ( 1450520 3529150 )
+ NEW met4 3100 + SHAPE STRIPE ( 1270520 2300000 ) ( 1270520 3529150 )
+ NEW met4 3100 + SHAPE STRIPE ( 1090520 -9470 ) ( 1090520 3529150 )
+ NEW met4 3100 + SHAPE STRIPE ( 910520 -9470 ) ( 910520 3529150 )
+ NEW met4 3100 + SHAPE STRIPE ( 730520 -9470 ) ( 730520 3529150 )
+ NEW met4 3100 + SHAPE STRIPE ( 550520 -9470 ) ( 550520 3529150 )
+ NEW met4 3100 + SHAPE STRIPE ( 370520 -9470 ) ( 370520 3529150 )
+ NEW met4 3100 + SHAPE STRIPE ( 190520 -9470 ) ( 190520 3529150 )
+ NEW met4 3100 + SHAPE STRIPE ( 10520 -9470 ) ( 10520 3529150 )
+ NEW met4 3100 + SHAPE STRIPE ( 2928100 -4670 ) ( 2928100 3524350 )
+ NEW met4 3100 + SHAPE STRIPE ( -8480 -4670 ) ( -8480 3524350 )
+ NEW met4 3100 + SHAPE STRIPE ( 1990520 -9470 ) ( 1990520 1680000 )
+ NEW met4 3100 + SHAPE STRIPE ( 1810520 -9470 ) ( 1810520 1680000 )
+ NEW met4 3100 + SHAPE STRIPE ( 1630520 -9470 ) ( 1630520 1680000 )
+ NEW met4 3100 + SHAPE STRIPE ( 1450520 -9470 ) ( 1450520 1680000 )
+ NEW met4 3100 + SHAPE STRIPE ( 1270520 -9470 ) ( 1270520 1680000 ) ;
+ - vccd2 ( PIN vccd2 ) + USE POWER
+ + ROUTED met4 0 + SHAPE STRIPE ( 2937700 3532400 ) via4_3100x3100
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+ NEW met4 0 + SHAPE STRIPE ( 1469120 3532400 ) via4_3100x3100
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+ NEW met4 0 + SHAPE STRIPE ( 2937700 3454480 ) via4_3100x3100
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+ NEW met4 0 + SHAPE STRIPE ( 749120 3454480 ) via4_3100x3100
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+ NEW met4 0 + SHAPE STRIPE ( 2937700 3274480 ) via4_3100x3100
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+ NEW met4 0 + SHAPE STRIPE ( 2549120 3274480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2369120 3274480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2189120 3274480 ) via4_3100x3100
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+ NEW met4 0 + SHAPE STRIPE ( 1649120 3274480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1469120 3274480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1289120 3274480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1109120 3274480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 929120 3274480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 749120 3274480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 569120 3274480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 389120 3274480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 209120 3274480 ) via4_3100x3100
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+ NEW met4 0 + SHAPE STRIPE ( -18080 3274480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2937700 3094480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2909120 3094480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2729120 3094480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2549120 3094480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2369120 3094480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2189120 3094480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2009120 3094480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1829120 3094480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1649120 3094480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1469120 3094480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1289120 3094480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1109120 3094480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 929120 3094480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 749120 3094480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 569120 3094480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 389120 3094480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 209120 3094480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 29120 3094480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -18080 3094480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2937700 2914480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2909120 2914480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2729120 2914480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2549120 2914480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2369120 2914480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2189120 2914480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2009120 2914480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1829120 2914480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1649120 2914480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1469120 2914480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1289120 2914480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1109120 2914480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 929120 2914480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 749120 2914480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 569120 2914480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 389120 2914480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 209120 2914480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 29120 2914480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -18080 2914480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2937700 2734480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2909120 2734480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2729120 2734480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2549120 2734480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2369120 2734480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2189120 2734480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2009120 2734480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1829120 2734480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1649120 2734480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1469120 2734480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1289120 2734480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1109120 2734480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 929120 2734480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 749120 2734480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 569120 2734480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 389120 2734480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 209120 2734480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 29120 2734480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -18080 2734480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2937700 2554480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2909120 2554480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2729120 2554480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2549120 2554480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2369120 2554480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2189120 2554480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2009120 2554480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1829120 2554480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1649120 2554480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1469120 2554480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1289120 2554480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1109120 2554480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 929120 2554480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 749120 2554480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 569120 2554480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 389120 2554480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 209120 2554480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 29120 2554480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -18080 2554480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2937700 2374480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2909120 2374480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2729120 2374480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2549120 2374480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2369120 2374480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2189120 2374480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2009120 2374480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1829120 2374480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1649120 2374480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1469120 2374480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1289120 2374480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1109120 2374480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 929120 2374480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 749120 2374480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 569120 2374480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 389120 2374480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 209120 2374480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 29120 2374480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -18080 2374480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2937700 2194480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2909120 2194480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2729120 2194480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2549120 2194480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2369120 2194480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2189120 2194480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1109120 2194480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 929120 2194480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 749120 2194480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 569120 2194480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 389120 2194480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 209120 2194480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 29120 2194480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -18080 2194480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2937700 2014480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2909120 2014480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2729120 2014480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2549120 2014480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2369120 2014480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2189120 2014480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1109120 2014480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 929120 2014480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 749120 2014480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 569120 2014480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 389120 2014480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 209120 2014480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 29120 2014480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -18080 2014480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2937700 1834480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2909120 1834480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2729120 1834480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2549120 1834480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2369120 1834480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2189120 1834480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1109120 1834480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 929120 1834480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 749120 1834480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 569120 1834480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 389120 1834480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 209120 1834480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 29120 1834480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -18080 1834480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2937700 1654480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2909120 1654480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2729120 1654480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2549120 1654480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2369120 1654480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2189120 1654480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2009120 1654480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1829120 1654480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1649120 1654480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1469120 1654480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1289120 1654480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1109120 1654480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 929120 1654480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 749120 1654480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 569120 1654480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 389120 1654480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 209120 1654480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 29120 1654480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -18080 1654480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2937700 1474480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2909120 1474480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2729120 1474480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2549120 1474480 ) via4_3100x3100
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+ NEW met4 0 + SHAPE STRIPE ( 1469120 1474480 ) via4_3100x3100
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+ NEW met4 0 + SHAPE STRIPE ( 929120 1474480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 749120 1474480 ) via4_3100x3100
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+ NEW met4 0 + SHAPE STRIPE ( 209120 1474480 ) via4_3100x3100
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+ NEW met4 0 + SHAPE STRIPE ( 2729120 1294480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2549120 1294480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2369120 1294480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2189120 1294480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2009120 1294480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1829120 1294480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1649120 1294480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1469120 1294480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1289120 1294480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1109120 1294480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 929120 1294480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 749120 1294480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 569120 1294480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 389120 1294480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 209120 1294480 ) via4_3100x3100
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+ NEW met4 0 + SHAPE STRIPE ( -18080 1294480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2937700 1114480 ) via4_3100x3100
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+ NEW met4 0 + SHAPE STRIPE ( 2729120 1114480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2549120 1114480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2369120 1114480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2189120 1114480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2009120 1114480 ) via4_3100x3100
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+ NEW met4 0 + SHAPE STRIPE ( 1469120 1114480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1289120 1114480 ) via4_3100x3100
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+ NEW met4 0 + SHAPE STRIPE ( 929120 1114480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 749120 1114480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 569120 1114480 ) via4_3100x3100
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+ NEW met4 0 + SHAPE STRIPE ( 2937700 934480 ) via4_3100x3100
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+ NEW met4 0 + SHAPE STRIPE ( 2549120 934480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2369120 934480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2189120 934480 ) via4_3100x3100
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+ NEW met4 0 + SHAPE STRIPE ( 1469120 934480 ) via4_3100x3100
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+ NEW met4 0 + SHAPE STRIPE ( 929120 934480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 749120 934480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 569120 934480 ) via4_3100x3100
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+ NEW met4 0 + SHAPE STRIPE ( -18080 934480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2937700 754480 ) via4_3100x3100
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+ NEW met4 0 + SHAPE STRIPE ( 2549120 754480 ) via4_3100x3100
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+ NEW met4 0 + SHAPE STRIPE ( 1469120 754480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1289120 754480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1109120 754480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 929120 754480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 749120 754480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 569120 754480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 389120 754480 ) via4_3100x3100
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+ NEW met4 0 + SHAPE STRIPE ( -18080 754480 ) via4_3100x3100
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+ NEW met4 0 + SHAPE STRIPE ( 2729120 574480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2549120 574480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2369120 574480 ) via4_3100x3100
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+ NEW met4 0 + SHAPE STRIPE ( 929120 574480 ) via4_3100x3100
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+ NEW met4 0 + SHAPE STRIPE ( 2369120 214480 ) via4_3100x3100
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+ NEW met4 0 + SHAPE STRIPE ( -18080 214480 ) via4_3100x3100
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+ NEW met4 0 + SHAPE STRIPE ( 2369120 -12720 ) via4_3100x3100
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+ NEW met4 0 + SHAPE STRIPE ( 1469120 -12720 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1289120 -12720 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1109120 -12720 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 929120 -12720 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 749120 -12720 ) via4_3100x3100
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+ NEW met4 0 + SHAPE STRIPE ( 29120 -12720 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -18080 -12720 ) via4_3100x3100
+ NEW met5 3100 + SHAPE STRIPE ( -19630 3532400 ) ( 2939250 3532400 )
+ NEW met5 3100 + SHAPE STRIPE ( -24430 3454480 ) ( 2944050 3454480 )
+ NEW met5 3100 + SHAPE STRIPE ( -24430 3274480 ) ( 2944050 3274480 )
+ NEW met5 3100 + SHAPE STRIPE ( -24430 3094480 ) ( 2944050 3094480 )
+ NEW met5 3100 + SHAPE STRIPE ( -24430 2914480 ) ( 2944050 2914480 )
+ NEW met5 3100 + SHAPE STRIPE ( -24430 2734480 ) ( 2944050 2734480 )
+ NEW met5 3100 + SHAPE STRIPE ( -24430 2554480 ) ( 2944050 2554480 )
+ NEW met5 3100 + SHAPE STRIPE ( -24430 2374480 ) ( 2944050 2374480 )
+ NEW met5 3100 + SHAPE STRIPE ( -24430 2194480 ) ( 2944050 2194480 )
+ NEW met5 3100 + SHAPE STRIPE ( -24430 2014480 ) ( 2944050 2014480 )
+ NEW met5 3100 + SHAPE STRIPE ( -24430 1834480 ) ( 2944050 1834480 )
+ NEW met5 3100 + SHAPE STRIPE ( -24430 1654480 ) ( 2944050 1654480 )
+ NEW met5 3100 + SHAPE STRIPE ( -24430 1474480 ) ( 2944050 1474480 )
+ NEW met5 3100 + SHAPE STRIPE ( -24430 1294480 ) ( 2944050 1294480 )
+ NEW met5 3100 + SHAPE STRIPE ( -24430 1114480 ) ( 2944050 1114480 )
+ NEW met5 3100 + SHAPE STRIPE ( -24430 934480 ) ( 2944050 934480 )
+ NEW met5 3100 + SHAPE STRIPE ( -24430 754480 ) ( 2944050 754480 )
+ NEW met5 3100 + SHAPE STRIPE ( -24430 574480 ) ( 2944050 574480 )
+ NEW met5 3100 + SHAPE STRIPE ( -24430 394480 ) ( 2944050 394480 )
+ NEW met5 3100 + SHAPE STRIPE ( -24430 214480 ) ( 2944050 214480 )
+ NEW met5 3100 + SHAPE STRIPE ( -24430 34480 ) ( 2944050 34480 )
+ NEW met5 3100 + SHAPE STRIPE ( -19630 -12720 ) ( 2939250 -12720 )
+ NEW met4 3100 + SHAPE STRIPE ( 2909120 -19070 ) ( 2909120 3538750 )
+ NEW met4 3100 + SHAPE STRIPE ( 2729120 -19070 ) ( 2729120 3538750 )
+ NEW met4 3100 + SHAPE STRIPE ( 2549120 -19070 ) ( 2549120 3538750 )
+ NEW met4 3100 + SHAPE STRIPE ( 2369120 -19070 ) ( 2369120 3538750 )
+ NEW met4 3100 + SHAPE STRIPE ( 2189120 -19070 ) ( 2189120 3538750 )
+ NEW met4 3100 + SHAPE STRIPE ( 2009120 2300000 ) ( 2009120 3538750 )
+ NEW met4 3100 + SHAPE STRIPE ( 1829120 2300000 ) ( 1829120 3538750 )
+ NEW met4 3100 + SHAPE STRIPE ( 1649120 2300000 ) ( 1649120 3538750 )
+ NEW met4 3100 + SHAPE STRIPE ( 1469120 2300000 ) ( 1469120 3538750 )
+ NEW met4 3100 + SHAPE STRIPE ( 1289120 2300000 ) ( 1289120 3538750 )
+ NEW met4 3100 + SHAPE STRIPE ( 1109120 -19070 ) ( 1109120 3538750 )
+ NEW met4 3100 + SHAPE STRIPE ( 929120 -19070 ) ( 929120 3538750 )
+ NEW met4 3100 + SHAPE STRIPE ( 749120 -19070 ) ( 749120 3538750 )
+ NEW met4 3100 + SHAPE STRIPE ( 569120 -19070 ) ( 569120 3538750 )
+ NEW met4 3100 + SHAPE STRIPE ( 389120 -19070 ) ( 389120 3538750 )
+ NEW met4 3100 + SHAPE STRIPE ( 209120 -19070 ) ( 209120 3538750 )
+ NEW met4 3100 + SHAPE STRIPE ( 29120 -19070 ) ( 29120 3538750 )
+ NEW met4 3100 + SHAPE STRIPE ( 2937700 -14270 ) ( 2937700 3533950 )
+ NEW met4 3100 + SHAPE STRIPE ( -18080 -14270 ) ( -18080 3533950 )
+ NEW met4 3100 + SHAPE STRIPE ( 2009120 -19070 ) ( 2009120 1680000 )
+ NEW met4 3100 + SHAPE STRIPE ( 1829120 -19070 ) ( 1829120 1680000 )
+ NEW met4 3100 + SHAPE STRIPE ( 1649120 -19070 ) ( 1649120 1680000 )
+ NEW met4 3100 + SHAPE STRIPE ( 1469120 -19070 ) ( 1469120 1680000 )
+ NEW met4 3100 + SHAPE STRIPE ( 1289120 -19070 ) ( 1289120 1680000 ) ;
+ - vdda1 ( PIN vdda1 ) + USE POWER
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+ NEW met4 0 + SHAPE STRIPE ( 947720 3542000 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 767720 3542000 ) via4_3100x3100
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+ NEW met4 0 + SHAPE STRIPE ( 407720 3542000 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 227720 3542000 ) via4_3100x3100
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+ NEW met4 0 + SHAPE STRIPE ( -27680 3542000 ) via4_3100x3100
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+ NEW met4 0 + SHAPE STRIPE ( 2567720 3473080 ) via4_3100x3100
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+ NEW met4 0 + SHAPE STRIPE ( 1667720 3473080 ) via4_3100x3100
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+ NEW met4 0 + SHAPE STRIPE ( 947720 3473080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 767720 3473080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 587720 3473080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 407720 3473080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 227720 3473080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 47720 3473080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -27680 3473080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2947300 3293080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2747720 3293080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2567720 3293080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2387720 3293080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2207720 3293080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2027720 3293080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1847720 3293080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1667720 3293080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1487720 3293080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1307720 3293080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1127720 3293080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 947720 3293080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 767720 3293080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 587720 3293080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 407720 3293080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 227720 3293080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 47720 3293080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -27680 3293080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2947300 3113080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2747720 3113080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2567720 3113080 ) via4_3100x3100
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+ NEW met5 3100 + SHAPE STRIPE ( -34030 233080 ) ( 2953650 233080 )
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+ NEW met4 3100 + SHAPE STRIPE ( 1487720 -28670 ) ( 1487720 1680000 )
+ NEW met4 3100 + SHAPE STRIPE ( 1307720 -28670 ) ( 1307720 1680000 ) ;
+ - vdda2 ( PIN vdda2 ) + USE POWER
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+ NEW met5 3100 + SHAPE STRIPE ( -38830 3551600 ) ( 2958450 3551600 )
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+ NEW met5 3100 + SHAPE STRIPE ( -43630 3311680 ) ( 2963250 3311680 )
+ NEW met5 3100 + SHAPE STRIPE ( -43630 3131680 ) ( 2963250 3131680 )
+ NEW met5 3100 + SHAPE STRIPE ( -43630 2951680 ) ( 2963250 2951680 )
+ NEW met5 3100 + SHAPE STRIPE ( -43630 2771680 ) ( 2963250 2771680 )
+ NEW met5 3100 + SHAPE STRIPE ( -43630 2591680 ) ( 2963250 2591680 )
+ NEW met5 3100 + SHAPE STRIPE ( -43630 2411680 ) ( 2963250 2411680 )
+ NEW met5 3100 + SHAPE STRIPE ( -43630 2231680 ) ( 2963250 2231680 )
+ NEW met5 3100 + SHAPE STRIPE ( -43630 2051680 ) ( 2963250 2051680 )
+ NEW met5 3100 + SHAPE STRIPE ( -43630 1871680 ) ( 2963250 1871680 )
+ NEW met5 3100 + SHAPE STRIPE ( -43630 1691680 ) ( 2963250 1691680 )
+ NEW met5 3100 + SHAPE STRIPE ( -43630 1511680 ) ( 2963250 1511680 )
+ NEW met5 3100 + SHAPE STRIPE ( -43630 1331680 ) ( 2963250 1331680 )
+ NEW met5 3100 + SHAPE STRIPE ( -43630 1151680 ) ( 2963250 1151680 )
+ NEW met5 3100 + SHAPE STRIPE ( -43630 971680 ) ( 2963250 971680 )
+ NEW met5 3100 + SHAPE STRIPE ( -43630 791680 ) ( 2963250 791680 )
+ NEW met5 3100 + SHAPE STRIPE ( -43630 611680 ) ( 2963250 611680 )
+ NEW met5 3100 + SHAPE STRIPE ( -43630 431680 ) ( 2963250 431680 )
+ NEW met5 3100 + SHAPE STRIPE ( -43630 251680 ) ( 2963250 251680 )
+ NEW met5 3100 + SHAPE STRIPE ( -43630 71680 ) ( 2963250 71680 )
+ NEW met5 3100 + SHAPE STRIPE ( -38830 -31920 ) ( 2958450 -31920 )
+ NEW met4 3100 + SHAPE STRIPE ( 2766320 -38270 ) ( 2766320 3557950 )
+ NEW met4 3100 + SHAPE STRIPE ( 2586320 -38270 ) ( 2586320 3557950 )
+ NEW met4 3100 + SHAPE STRIPE ( 2406320 -38270 ) ( 2406320 3557950 )
+ NEW met4 3100 + SHAPE STRIPE ( 2226320 -38270 ) ( 2226320 3557950 )
+ NEW met4 3100 + SHAPE STRIPE ( 2046320 2300000 ) ( 2046320 3557950 )
+ NEW met4 3100 + SHAPE STRIPE ( 1866320 2300000 ) ( 1866320 3557950 )
+ NEW met4 3100 + SHAPE STRIPE ( 1686320 2300000 ) ( 1686320 3557950 )
+ NEW met4 3100 + SHAPE STRIPE ( 1506320 2300000 ) ( 1506320 3557950 )
+ NEW met4 3100 + SHAPE STRIPE ( 1326320 2300000 ) ( 1326320 3557950 )
+ NEW met4 3100 + SHAPE STRIPE ( 1146320 -38270 ) ( 1146320 3557950 )
+ NEW met4 3100 + SHAPE STRIPE ( 966320 -38270 ) ( 966320 3557950 )
+ NEW met4 3100 + SHAPE STRIPE ( 786320 -38270 ) ( 786320 3557950 )
+ NEW met4 3100 + SHAPE STRIPE ( 606320 -38270 ) ( 606320 3557950 )
+ NEW met4 3100 + SHAPE STRIPE ( 426320 -38270 ) ( 426320 3557950 )
+ NEW met4 3100 + SHAPE STRIPE ( 246320 -38270 ) ( 246320 3557950 )
+ NEW met4 3100 + SHAPE STRIPE ( 66320 -38270 ) ( 66320 3557950 )
+ NEW met4 3100 + SHAPE STRIPE ( 2956900 -33470 ) ( 2956900 3553150 )
+ NEW met4 3100 + SHAPE STRIPE ( -37280 -33470 ) ( -37280 3553150 )
+ NEW met4 3100 + SHAPE STRIPE ( 2046320 -38270 ) ( 2046320 1680000 )
+ NEW met4 3100 + SHAPE STRIPE ( 1866320 -38270 ) ( 1866320 1680000 )
+ NEW met4 3100 + SHAPE STRIPE ( 1686320 -38270 ) ( 1686320 1680000 )
+ NEW met4 3100 + SHAPE STRIPE ( 1506320 -38270 ) ( 1506320 1680000 )
+ NEW met4 3100 + SHAPE STRIPE ( 1326320 -38270 ) ( 1326320 1680000 ) ;
+ - vssa1 ( PIN vssa1 ) + USE GROUND
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+ NEW met5 3100 + SHAPE STRIPE ( -34030 1403080 ) ( 2953650 1403080 )
+ NEW met5 3100 + SHAPE STRIPE ( -34030 1223080 ) ( 2953650 1223080 )
+ NEW met5 3100 + SHAPE STRIPE ( -34030 1043080 ) ( 2953650 1043080 )
+ NEW met5 3100 + SHAPE STRIPE ( -34030 863080 ) ( 2953650 863080 )
+ NEW met5 3100 + SHAPE STRIPE ( -34030 683080 ) ( 2953650 683080 )
+ NEW met5 3100 + SHAPE STRIPE ( -34030 503080 ) ( 2953650 503080 )
+ NEW met5 3100 + SHAPE STRIPE ( -34030 323080 ) ( 2953650 323080 )
+ NEW met5 3100 + SHAPE STRIPE ( -34030 143080 ) ( 2953650 143080 )
+ NEW met5 3100 + SHAPE STRIPE ( -34030 -27120 ) ( 2953650 -27120 )
+ NEW met4 3100 + SHAPE STRIPE ( 2952100 -28670 ) ( 2952100 3548350 )
+ NEW met4 3100 + SHAPE STRIPE ( 2837720 -28670 ) ( 2837720 3548350 )
+ NEW met4 3100 + SHAPE STRIPE ( 2657720 -28670 ) ( 2657720 3548350 )
+ NEW met4 3100 + SHAPE STRIPE ( 2477720 -28670 ) ( 2477720 3548350 )
+ NEW met4 3100 + SHAPE STRIPE ( 2297720 -28670 ) ( 2297720 3548350 )
+ NEW met4 3100 + SHAPE STRIPE ( 2117720 -28670 ) ( 2117720 3548350 )
+ NEW met4 3100 + SHAPE STRIPE ( 1937720 2300000 ) ( 1937720 3548350 )
+ NEW met4 3100 + SHAPE STRIPE ( 1757720 2300000 ) ( 1757720 3548350 )
+ NEW met4 3100 + SHAPE STRIPE ( 1577720 2300000 ) ( 1577720 3548350 )
+ NEW met4 3100 + SHAPE STRIPE ( 1397720 2300000 ) ( 1397720 3548350 )
+ NEW met4 3100 + SHAPE STRIPE ( 1217720 2300000 ) ( 1217720 3548350 )
+ NEW met4 3100 + SHAPE STRIPE ( 1037720 -28670 ) ( 1037720 3548350 )
+ NEW met4 3100 + SHAPE STRIPE ( 857720 -28670 ) ( 857720 3548350 )
+ NEW met4 3100 + SHAPE STRIPE ( 677720 -28670 ) ( 677720 3548350 )
+ NEW met4 3100 + SHAPE STRIPE ( 497720 -28670 ) ( 497720 3548350 )
+ NEW met4 3100 + SHAPE STRIPE ( 317720 -28670 ) ( 317720 3548350 )
+ NEW met4 3100 + SHAPE STRIPE ( 137720 -28670 ) ( 137720 3548350 )
+ NEW met4 3100 + SHAPE STRIPE ( -32480 -28670 ) ( -32480 3548350 )
+ NEW met4 3100 + SHAPE STRIPE ( 1937720 -28670 ) ( 1937720 1680000 )
+ NEW met4 3100 + SHAPE STRIPE ( 1757720 -28670 ) ( 1757720 1680000 )
+ NEW met4 3100 + SHAPE STRIPE ( 1577720 -28670 ) ( 1577720 1680000 )
+ NEW met4 3100 + SHAPE STRIPE ( 1397720 -28670 ) ( 1397720 1680000 )
+ NEW met4 3100 + SHAPE STRIPE ( 1217720 -28670 ) ( 1217720 1680000 ) ;
+ - vssa2 ( PIN vssa2 ) + USE GROUND
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+ NEW met5 3100 + SHAPE STRIPE ( -43630 1961680 ) ( 2963250 1961680 )
+ NEW met5 3100 + SHAPE STRIPE ( -43630 1781680 ) ( 2963250 1781680 )
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+ NEW met5 3100 + SHAPE STRIPE ( -43630 1421680 ) ( 2963250 1421680 )
+ NEW met5 3100 + SHAPE STRIPE ( -43630 1241680 ) ( 2963250 1241680 )
+ NEW met5 3100 + SHAPE STRIPE ( -43630 1061680 ) ( 2963250 1061680 )
+ NEW met5 3100 + SHAPE STRIPE ( -43630 881680 ) ( 2963250 881680 )
+ NEW met5 3100 + SHAPE STRIPE ( -43630 701680 ) ( 2963250 701680 )
+ NEW met5 3100 + SHAPE STRIPE ( -43630 521680 ) ( 2963250 521680 )
+ NEW met5 3100 + SHAPE STRIPE ( -43630 341680 ) ( 2963250 341680 )
+ NEW met5 3100 + SHAPE STRIPE ( -43630 161680 ) ( 2963250 161680 )
+ NEW met5 3100 + SHAPE STRIPE ( -43630 -36720 ) ( 2963250 -36720 )
+ NEW met4 3100 + SHAPE STRIPE ( 2961700 -38270 ) ( 2961700 3557950 )
+ NEW met4 3100 + SHAPE STRIPE ( 2856320 -38270 ) ( 2856320 3557950 )
+ NEW met4 3100 + SHAPE STRIPE ( 2676320 -38270 ) ( 2676320 3557950 )
+ NEW met4 3100 + SHAPE STRIPE ( 2496320 -38270 ) ( 2496320 3557950 )
+ NEW met4 3100 + SHAPE STRIPE ( 2316320 -38270 ) ( 2316320 3557950 )
+ NEW met4 3100 + SHAPE STRIPE ( 2136320 -38270 ) ( 2136320 3557950 )
+ NEW met4 3100 + SHAPE STRIPE ( 1956320 2300000 ) ( 1956320 3557950 )
+ NEW met4 3100 + SHAPE STRIPE ( 1776320 2300000 ) ( 1776320 3557950 )
+ NEW met4 3100 + SHAPE STRIPE ( 1596320 2300000 ) ( 1596320 3557950 )
+ NEW met4 3100 + SHAPE STRIPE ( 1416320 2300000 ) ( 1416320 3557950 )
+ NEW met4 3100 + SHAPE STRIPE ( 1236320 2300000 ) ( 1236320 3557950 )
+ NEW met4 3100 + SHAPE STRIPE ( 1056320 -38270 ) ( 1056320 3557950 )
+ NEW met4 3100 + SHAPE STRIPE ( 876320 -38270 ) ( 876320 3557950 )
+ NEW met4 3100 + SHAPE STRIPE ( 696320 -38270 ) ( 696320 3557950 )
+ NEW met4 3100 + SHAPE STRIPE ( 516320 -38270 ) ( 516320 3557950 )
+ NEW met4 3100 + SHAPE STRIPE ( 336320 -38270 ) ( 336320 3557950 )
+ NEW met4 3100 + SHAPE STRIPE ( 156320 -38270 ) ( 156320 3557950 )
+ NEW met4 3100 + SHAPE STRIPE ( -42080 -38270 ) ( -42080 3557950 )
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+ NEW met4 3100 + SHAPE STRIPE ( 1596320 -38270 ) ( 1596320 1680000 )
+ NEW met4 3100 + SHAPE STRIPE ( 1416320 -38270 ) ( 1416320 1680000 )
+ NEW met4 3100 + SHAPE STRIPE ( 1236320 -38270 ) ( 1236320 1680000 ) ;
+ - vssd1 ( PIN vssd1 ) + USE GROUND
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+ NEW met4 0 + SHAPE STRIPE ( 1900520 2445880 ) via4_3100x3100
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+ NEW met4 0 + SHAPE STRIPE ( 1540520 2445880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1360520 2445880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1180520 2445880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1000520 2445880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 820520 2445880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 640520 2445880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 460520 2445880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 280520 2445880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 100520 2445880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -13280 2445880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2932900 2265880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2800520 2265880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2620520 2265880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2440520 2265880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2260520 2265880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1000520 2265880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 820520 2265880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 640520 2265880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 460520 2265880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 280520 2265880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 100520 2265880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -13280 2265880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2932900 2085880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2800520 2085880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2620520 2085880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2440520 2085880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2260520 2085880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1000520 2085880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 820520 2085880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 640520 2085880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 460520 2085880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 280520 2085880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 100520 2085880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -13280 2085880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2932900 1905880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2800520 1905880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2620520 1905880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2440520 1905880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2260520 1905880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1000520 1905880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 820520 1905880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 640520 1905880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 460520 1905880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 280520 1905880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 100520 1905880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -13280 1905880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2932900 1725880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2800520 1725880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2620520 1725880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2440520 1725880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2260520 1725880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1000520 1725880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 820520 1725880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 640520 1725880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 460520 1725880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 280520 1725880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 100520 1725880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -13280 1725880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2932900 1545880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2800520 1545880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2620520 1545880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2440520 1545880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2260520 1545880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2080520 1545880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1900520 1545880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1720520 1545880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1540520 1545880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1360520 1545880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1180520 1545880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1000520 1545880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 820520 1545880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 640520 1545880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 460520 1545880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 280520 1545880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 100520 1545880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -13280 1545880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2932900 1365880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2800520 1365880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2620520 1365880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2440520 1365880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2260520 1365880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2080520 1365880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1900520 1365880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1720520 1365880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1540520 1365880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1360520 1365880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1180520 1365880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1000520 1365880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 820520 1365880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 640520 1365880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 460520 1365880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 280520 1365880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 100520 1365880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -13280 1365880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2932900 1185880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2800520 1185880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2620520 1185880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2440520 1185880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2260520 1185880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2080520 1185880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1900520 1185880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1720520 1185880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1540520 1185880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1360520 1185880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1180520 1185880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1000520 1185880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 820520 1185880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 640520 1185880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 460520 1185880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 280520 1185880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 100520 1185880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -13280 1185880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2932900 1005880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2800520 1005880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2620520 1005880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2440520 1005880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2260520 1005880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2080520 1005880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1900520 1005880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1720520 1005880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1540520 1005880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1360520 1005880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1180520 1005880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1000520 1005880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 820520 1005880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 640520 1005880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 460520 1005880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 280520 1005880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 100520 1005880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -13280 1005880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2932900 825880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2800520 825880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2620520 825880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2440520 825880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2260520 825880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2080520 825880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1900520 825880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1720520 825880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1540520 825880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1360520 825880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1180520 825880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1000520 825880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 820520 825880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 640520 825880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 460520 825880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 280520 825880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 100520 825880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -13280 825880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2932900 645880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2800520 645880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2620520 645880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2440520 645880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2260520 645880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2080520 645880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1900520 645880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1720520 645880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1540520 645880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1360520 645880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1180520 645880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1000520 645880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 820520 645880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 640520 645880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 460520 645880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 280520 645880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 100520 645880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -13280 645880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2932900 465880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2800520 465880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2620520 465880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2440520 465880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2260520 465880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2080520 465880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1900520 465880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1720520 465880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1540520 465880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1360520 465880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1180520 465880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1000520 465880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 820520 465880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 640520 465880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 460520 465880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 280520 465880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 100520 465880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -13280 465880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2932900 285880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2800520 285880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2620520 285880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2440520 285880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2260520 285880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2080520 285880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1900520 285880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1720520 285880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1540520 285880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1360520 285880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1180520 285880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1000520 285880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 820520 285880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 640520 285880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 460520 285880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 280520 285880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 100520 285880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -13280 285880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2932900 105880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2800520 105880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2620520 105880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2440520 105880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2260520 105880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2080520 105880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1900520 105880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1720520 105880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1540520 105880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1360520 105880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1180520 105880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1000520 105880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 820520 105880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 640520 105880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 460520 105880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 280520 105880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 100520 105880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -13280 105880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2932900 -7920 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2800520 -7920 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2620520 -7920 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2440520 -7920 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2260520 -7920 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2080520 -7920 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1900520 -7920 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1720520 -7920 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1540520 -7920 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1360520 -7920 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1180520 -7920 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1000520 -7920 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 820520 -7920 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 640520 -7920 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 460520 -7920 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 280520 -7920 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 100520 -7920 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -13280 -7920 ) via4_3100x3100
+ NEW met5 3100 + SHAPE STRIPE ( -14830 3527600 ) ( 2934450 3527600 )
+ NEW met5 3100 + SHAPE STRIPE ( -14830 3345880 ) ( 2934450 3345880 )
+ NEW met5 3100 + SHAPE STRIPE ( -14830 3165880 ) ( 2934450 3165880 )
+ NEW met5 3100 + SHAPE STRIPE ( -14830 2985880 ) ( 2934450 2985880 )
+ NEW met5 3100 + SHAPE STRIPE ( -14830 2805880 ) ( 2934450 2805880 )
+ NEW met5 3100 + SHAPE STRIPE ( -14830 2625880 ) ( 2934450 2625880 )
+ NEW met5 3100 + SHAPE STRIPE ( -14830 2445880 ) ( 2934450 2445880 )
+ NEW met5 3100 + SHAPE STRIPE ( -14830 2265880 ) ( 2934450 2265880 )
+ NEW met5 3100 + SHAPE STRIPE ( -14830 2085880 ) ( 2934450 2085880 )
+ NEW met5 3100 + SHAPE STRIPE ( -14830 1905880 ) ( 2934450 1905880 )
+ NEW met5 3100 + SHAPE STRIPE ( -14830 1725880 ) ( 2934450 1725880 )
+ NEW met5 3100 + SHAPE STRIPE ( -14830 1545880 ) ( 2934450 1545880 )
+ NEW met5 3100 + SHAPE STRIPE ( -14830 1365880 ) ( 2934450 1365880 )
+ NEW met5 3100 + SHAPE STRIPE ( -14830 1185880 ) ( 2934450 1185880 )
+ NEW met5 3100 + SHAPE STRIPE ( -14830 1005880 ) ( 2934450 1005880 )
+ NEW met5 3100 + SHAPE STRIPE ( -14830 825880 ) ( 2934450 825880 )
+ NEW met5 3100 + SHAPE STRIPE ( -14830 645880 ) ( 2934450 645880 )
+ NEW met5 3100 + SHAPE STRIPE ( -14830 465880 ) ( 2934450 465880 )
+ NEW met5 3100 + SHAPE STRIPE ( -14830 285880 ) ( 2934450 285880 )
+ NEW met5 3100 + SHAPE STRIPE ( -14830 105880 ) ( 2934450 105880 )
+ NEW met5 3100 + SHAPE STRIPE ( -14830 -7920 ) ( 2934450 -7920 )
+ NEW met4 3100 + SHAPE STRIPE ( 2932900 -9470 ) ( 2932900 3529150 )
+ NEW met4 3100 + SHAPE STRIPE ( 2800520 -9470 ) ( 2800520 3529150 )
+ NEW met4 3100 + SHAPE STRIPE ( 2620520 -9470 ) ( 2620520 3529150 )
+ NEW met4 3100 + SHAPE STRIPE ( 2440520 -9470 ) ( 2440520 3529150 )
+ NEW met4 3100 + SHAPE STRIPE ( 2260520 -9470 ) ( 2260520 3529150 )
+ NEW met4 3100 + SHAPE STRIPE ( 2080520 2300000 ) ( 2080520 3529150 )
+ NEW met4 3100 + SHAPE STRIPE ( 1900520 2300000 ) ( 1900520 3529150 )
+ NEW met4 3100 + SHAPE STRIPE ( 1720520 2300000 ) ( 1720520 3529150 )
+ NEW met4 3100 + SHAPE STRIPE ( 1540520 2300000 ) ( 1540520 3529150 )
+ NEW met4 3100 + SHAPE STRIPE ( 1360520 2300000 ) ( 1360520 3529150 )
+ NEW met4 3100 + SHAPE STRIPE ( 1180520 2300000 ) ( 1180520 3529150 )
+ NEW met4 3100 + SHAPE STRIPE ( 1000520 -9470 ) ( 1000520 3529150 )
+ NEW met4 3100 + SHAPE STRIPE ( 820520 -9470 ) ( 820520 3529150 )
+ NEW met4 3100 + SHAPE STRIPE ( 640520 -9470 ) ( 640520 3529150 )
+ NEW met4 3100 + SHAPE STRIPE ( 460520 -9470 ) ( 460520 3529150 )
+ NEW met4 3100 + SHAPE STRIPE ( 280520 -9470 ) ( 280520 3529150 )
+ NEW met4 3100 + SHAPE STRIPE ( 100520 -9470 ) ( 100520 3529150 )
+ NEW met4 3100 + SHAPE STRIPE ( -13280 -9470 ) ( -13280 3529150 )
+ NEW met4 3100 + SHAPE STRIPE ( 2080520 -9470 ) ( 2080520 1680000 )
+ NEW met4 3100 + SHAPE STRIPE ( 1900520 -9470 ) ( 1900520 1680000 )
+ NEW met4 3100 + SHAPE STRIPE ( 1720520 -9470 ) ( 1720520 1680000 )
+ NEW met4 3100 + SHAPE STRIPE ( 1540520 -9470 ) ( 1540520 1680000 )
+ NEW met4 3100 + SHAPE STRIPE ( 1360520 -9470 ) ( 1360520 1680000 )
+ NEW met4 3100 + SHAPE STRIPE ( 1180520 -9470 ) ( 1180520 1680000 ) ;
+ - vssd2 ( PIN vssd2 ) + USE GROUND
+ + ROUTED met4 0 + SHAPE STRIPE ( 2942500 3537200 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2819120 3537200 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2639120 3537200 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2459120 3537200 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2279120 3537200 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2099120 3537200 ) via4_3100x3100
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+ NEW met4 0 + SHAPE STRIPE ( 839120 484480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 659120 484480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 479120 484480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 299120 484480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 119120 484480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -22880 484480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2942500 304480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2819120 304480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2639120 304480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2459120 304480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2279120 304480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2099120 304480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1919120 304480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1739120 304480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1559120 304480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1379120 304480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1199120 304480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1019120 304480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 839120 304480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 659120 304480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 479120 304480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 299120 304480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 119120 304480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -22880 304480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2942500 124480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2819120 124480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2639120 124480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2459120 124480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2279120 124480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2099120 124480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1919120 124480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1739120 124480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1559120 124480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1379120 124480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1199120 124480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1019120 124480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 839120 124480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 659120 124480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 479120 124480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 299120 124480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 119120 124480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -22880 124480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2942500 -17520 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2819120 -17520 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2639120 -17520 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2459120 -17520 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2279120 -17520 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2099120 -17520 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1919120 -17520 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1739120 -17520 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1559120 -17520 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1379120 -17520 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1199120 -17520 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1019120 -17520 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 839120 -17520 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 659120 -17520 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 479120 -17520 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 299120 -17520 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 119120 -17520 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -22880 -17520 ) via4_3100x3100
+ NEW met5 3100 + SHAPE STRIPE ( -24430 3537200 ) ( 2944050 3537200 )
+ NEW met5 3100 + SHAPE STRIPE ( -24430 3364480 ) ( 2944050 3364480 )
+ NEW met5 3100 + SHAPE STRIPE ( -24430 3184480 ) ( 2944050 3184480 )
+ NEW met5 3100 + SHAPE STRIPE ( -24430 3004480 ) ( 2944050 3004480 )
+ NEW met5 3100 + SHAPE STRIPE ( -24430 2824480 ) ( 2944050 2824480 )
+ NEW met5 3100 + SHAPE STRIPE ( -24430 2644480 ) ( 2944050 2644480 )
+ NEW met5 3100 + SHAPE STRIPE ( -24430 2464480 ) ( 2944050 2464480 )
+ NEW met5 3100 + SHAPE STRIPE ( -24430 2284480 ) ( 2944050 2284480 )
+ NEW met5 3100 + SHAPE STRIPE ( -24430 2104480 ) ( 2944050 2104480 )
+ NEW met5 3100 + SHAPE STRIPE ( -24430 1924480 ) ( 2944050 1924480 )
+ NEW met5 3100 + SHAPE STRIPE ( -24430 1744480 ) ( 2944050 1744480 )
+ NEW met5 3100 + SHAPE STRIPE ( -24430 1564480 ) ( 2944050 1564480 )
+ NEW met5 3100 + SHAPE STRIPE ( -24430 1384480 ) ( 2944050 1384480 )
+ NEW met5 3100 + SHAPE STRIPE ( -24430 1204480 ) ( 2944050 1204480 )
+ NEW met5 3100 + SHAPE STRIPE ( -24430 1024480 ) ( 2944050 1024480 )
+ NEW met5 3100 + SHAPE STRIPE ( -24430 844480 ) ( 2944050 844480 )
+ NEW met5 3100 + SHAPE STRIPE ( -24430 664480 ) ( 2944050 664480 )
+ NEW met5 3100 + SHAPE STRIPE ( -24430 484480 ) ( 2944050 484480 )
+ NEW met5 3100 + SHAPE STRIPE ( -24430 304480 ) ( 2944050 304480 )
+ NEW met5 3100 + SHAPE STRIPE ( -24430 124480 ) ( 2944050 124480 )
+ NEW met5 3100 + SHAPE STRIPE ( -24430 -17520 ) ( 2944050 -17520 )
+ NEW met4 3100 + SHAPE STRIPE ( 2942500 -19070 ) ( 2942500 3538750 )
+ NEW met4 3100 + SHAPE STRIPE ( 2819120 -19070 ) ( 2819120 3538750 )
+ NEW met4 3100 + SHAPE STRIPE ( 2639120 -19070 ) ( 2639120 3538750 )
+ NEW met4 3100 + SHAPE STRIPE ( 2459120 -19070 ) ( 2459120 3538750 )
+ NEW met4 3100 + SHAPE STRIPE ( 2279120 -19070 ) ( 2279120 3538750 )
+ NEW met4 3100 + SHAPE STRIPE ( 2099120 -19070 ) ( 2099120 3538750 )
+ NEW met4 3100 + SHAPE STRIPE ( 1919120 2300000 ) ( 1919120 3538750 )
+ NEW met4 3100 + SHAPE STRIPE ( 1739120 2300000 ) ( 1739120 3538750 )
+ NEW met4 3100 + SHAPE STRIPE ( 1559120 2300000 ) ( 1559120 3538750 )
+ NEW met4 3100 + SHAPE STRIPE ( 1379120 2300000 ) ( 1379120 3538750 )
+ NEW met4 3100 + SHAPE STRIPE ( 1199120 2300000 ) ( 1199120 3538750 )
+ NEW met4 3100 + SHAPE STRIPE ( 1019120 -19070 ) ( 1019120 3538750 )
+ NEW met4 3100 + SHAPE STRIPE ( 839120 -19070 ) ( 839120 3538750 )
+ NEW met4 3100 + SHAPE STRIPE ( 659120 -19070 ) ( 659120 3538750 )
+ NEW met4 3100 + SHAPE STRIPE ( 479120 -19070 ) ( 479120 3538750 )
+ NEW met4 3100 + SHAPE STRIPE ( 299120 -19070 ) ( 299120 3538750 )
+ NEW met4 3100 + SHAPE STRIPE ( 119120 -19070 ) ( 119120 3538750 )
+ NEW met4 3100 + SHAPE STRIPE ( -22880 -19070 ) ( -22880 3538750 )
+ NEW met4 3100 + SHAPE STRIPE ( 1919120 -19070 ) ( 1919120 1680000 )
+ NEW met4 3100 + SHAPE STRIPE ( 1739120 -19070 ) ( 1739120 1680000 )
+ NEW met4 3100 + SHAPE STRIPE ( 1559120 -19070 ) ( 1559120 1680000 )
+ NEW met4 3100 + SHAPE STRIPE ( 1379120 -19070 ) ( 1379120 1680000 )
+ NEW met4 3100 + SHAPE STRIPE ( 1199120 -19070 ) ( 1199120 1680000 ) ;
+END SPECIALNETS
+END DESIGN
diff --git a/openlane/user_project_wrapper/fixed_dont_change/user_project_wrapper_gf180mcu.def b/openlane/user_project_wrapper/fixed_dont_change/user_project_wrapper_gf180mcu.def
new file mode 100644
index 0000000..690921f
--- /dev/null
+++ b/openlane/user_project_wrapper/fixed_dont_change/user_project_wrapper_gf180mcu.def
@@ -0,0 +1,5181 @@
+VERSION 5.8 ;
+DIVIDERCHAR "/" ;
+BUSBITCHARS "[]" ;
+DESIGN user_project_wrapper ;
+UNITS DISTANCE MICRONS 2000 ;
+DIEAREA ( 0 0 ) ( 6000000 6000000 ) ;
+ROW ROW_0 GF018hv5v_mcu_sc7 43680 47040 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_1 GF018hv5v_mcu_sc7 43680 54880 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_2 GF018hv5v_mcu_sc7 43680 62720 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_3 GF018hv5v_mcu_sc7 43680 70560 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_4 GF018hv5v_mcu_sc7 43680 78400 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_5 GF018hv5v_mcu_sc7 43680 86240 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_6 GF018hv5v_mcu_sc7 43680 94080 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_7 GF018hv5v_mcu_sc7 43680 101920 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_8 GF018hv5v_mcu_sc7 43680 109760 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_9 GF018hv5v_mcu_sc7 43680 117600 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_10 GF018hv5v_mcu_sc7 43680 125440 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_11 GF018hv5v_mcu_sc7 43680 133280 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_12 GF018hv5v_mcu_sc7 43680 141120 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_13 GF018hv5v_mcu_sc7 43680 148960 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_14 GF018hv5v_mcu_sc7 43680 156800 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_15 GF018hv5v_mcu_sc7 43680 164640 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_16 GF018hv5v_mcu_sc7 43680 172480 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_17 GF018hv5v_mcu_sc7 43680 180320 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_18 GF018hv5v_mcu_sc7 43680 188160 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_19 GF018hv5v_mcu_sc7 43680 196000 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_20 GF018hv5v_mcu_sc7 43680 203840 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_21 GF018hv5v_mcu_sc7 43680 211680 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_22 GF018hv5v_mcu_sc7 43680 219520 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_23 GF018hv5v_mcu_sc7 43680 227360 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_24 GF018hv5v_mcu_sc7 43680 235200 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_25 GF018hv5v_mcu_sc7 43680 243040 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_26 GF018hv5v_mcu_sc7 43680 250880 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_27 GF018hv5v_mcu_sc7 43680 258720 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_28 GF018hv5v_mcu_sc7 43680 266560 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_29 GF018hv5v_mcu_sc7 43680 274400 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_30 GF018hv5v_mcu_sc7 43680 282240 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_31 GF018hv5v_mcu_sc7 43680 290080 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_32 GF018hv5v_mcu_sc7 43680 297920 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_33 GF018hv5v_mcu_sc7 43680 305760 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_34 GF018hv5v_mcu_sc7 43680 313600 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_35 GF018hv5v_mcu_sc7 43680 321440 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_36 GF018hv5v_mcu_sc7 43680 329280 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_37 GF018hv5v_mcu_sc7 43680 337120 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_38 GF018hv5v_mcu_sc7 43680 344960 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_39 GF018hv5v_mcu_sc7 43680 352800 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_40 GF018hv5v_mcu_sc7 43680 360640 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_41 GF018hv5v_mcu_sc7 43680 368480 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_42 GF018hv5v_mcu_sc7 43680 376320 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_43 GF018hv5v_mcu_sc7 43680 384160 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_44 GF018hv5v_mcu_sc7 43680 392000 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_45 GF018hv5v_mcu_sc7 43680 399840 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_46 GF018hv5v_mcu_sc7 43680 407680 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_47 GF018hv5v_mcu_sc7 43680 415520 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_48 GF018hv5v_mcu_sc7 43680 423360 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_49 GF018hv5v_mcu_sc7 43680 431200 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_50 GF018hv5v_mcu_sc7 43680 439040 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_51 GF018hv5v_mcu_sc7 43680 446880 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_52 GF018hv5v_mcu_sc7 43680 454720 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_53 GF018hv5v_mcu_sc7 43680 462560 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_54 GF018hv5v_mcu_sc7 43680 470400 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_55 GF018hv5v_mcu_sc7 43680 478240 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_56 GF018hv5v_mcu_sc7 43680 486080 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_57 GF018hv5v_mcu_sc7 43680 493920 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_58 GF018hv5v_mcu_sc7 43680 501760 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_59 GF018hv5v_mcu_sc7 43680 509600 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_60 GF018hv5v_mcu_sc7 43680 517440 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_61 GF018hv5v_mcu_sc7 43680 525280 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_62 GF018hv5v_mcu_sc7 43680 533120 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_63 GF018hv5v_mcu_sc7 43680 540960 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_64 GF018hv5v_mcu_sc7 43680 548800 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_65 GF018hv5v_mcu_sc7 43680 556640 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_66 GF018hv5v_mcu_sc7 43680 564480 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_67 GF018hv5v_mcu_sc7 43680 572320 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_68 GF018hv5v_mcu_sc7 43680 580160 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_69 GF018hv5v_mcu_sc7 43680 588000 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_70 GF018hv5v_mcu_sc7 43680 595840 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_71 GF018hv5v_mcu_sc7 43680 603680 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_72 GF018hv5v_mcu_sc7 43680 611520 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_73 GF018hv5v_mcu_sc7 43680 619360 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_74 GF018hv5v_mcu_sc7 43680 627200 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_75 GF018hv5v_mcu_sc7 43680 635040 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_76 GF018hv5v_mcu_sc7 43680 642880 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_77 GF018hv5v_mcu_sc7 43680 650720 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_78 GF018hv5v_mcu_sc7 43680 658560 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_79 GF018hv5v_mcu_sc7 43680 666400 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_80 GF018hv5v_mcu_sc7 43680 674240 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_81 GF018hv5v_mcu_sc7 43680 682080 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_82 GF018hv5v_mcu_sc7 43680 689920 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_83 GF018hv5v_mcu_sc7 43680 697760 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_84 GF018hv5v_mcu_sc7 43680 705600 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_85 GF018hv5v_mcu_sc7 43680 713440 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_86 GF018hv5v_mcu_sc7 43680 721280 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_87 GF018hv5v_mcu_sc7 43680 729120 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_88 GF018hv5v_mcu_sc7 43680 736960 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_89 GF018hv5v_mcu_sc7 43680 744800 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_90 GF018hv5v_mcu_sc7 43680 752640 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_91 GF018hv5v_mcu_sc7 43680 760480 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_92 GF018hv5v_mcu_sc7 43680 768320 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_93 GF018hv5v_mcu_sc7 43680 776160 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_94 GF018hv5v_mcu_sc7 43680 784000 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_95 GF018hv5v_mcu_sc7 43680 791840 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_96 GF018hv5v_mcu_sc7 43680 799680 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_97 GF018hv5v_mcu_sc7 43680 807520 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_98 GF018hv5v_mcu_sc7 43680 815360 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_99 GF018hv5v_mcu_sc7 43680 823200 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_100 GF018hv5v_mcu_sc7 43680 831040 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_101 GF018hv5v_mcu_sc7 43680 838880 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_102 GF018hv5v_mcu_sc7 43680 846720 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_103 GF018hv5v_mcu_sc7 43680 854560 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_104 GF018hv5v_mcu_sc7 43680 862400 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_105 GF018hv5v_mcu_sc7 43680 870240 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_106 GF018hv5v_mcu_sc7 43680 878080 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_107 GF018hv5v_mcu_sc7 43680 885920 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_108 GF018hv5v_mcu_sc7 43680 893760 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_109 GF018hv5v_mcu_sc7 43680 901600 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_110 GF018hv5v_mcu_sc7 43680 909440 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_111 GF018hv5v_mcu_sc7 43680 917280 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_112 GF018hv5v_mcu_sc7 43680 925120 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_113 GF018hv5v_mcu_sc7 43680 932960 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_114 GF018hv5v_mcu_sc7 43680 940800 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_115 GF018hv5v_mcu_sc7 43680 948640 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_116 GF018hv5v_mcu_sc7 43680 956480 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_117 GF018hv5v_mcu_sc7 43680 964320 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_118 GF018hv5v_mcu_sc7 43680 972160 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_119 GF018hv5v_mcu_sc7 43680 980000 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_120 GF018hv5v_mcu_sc7 43680 987840 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_121 GF018hv5v_mcu_sc7 43680 995680 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_122 GF018hv5v_mcu_sc7 43680 1003520 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_123 GF018hv5v_mcu_sc7 43680 1011360 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_124 GF018hv5v_mcu_sc7 43680 1019200 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_125 GF018hv5v_mcu_sc7 43680 1027040 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_126 GF018hv5v_mcu_sc7 43680 1034880 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_127 GF018hv5v_mcu_sc7 43680 1042720 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_128 GF018hv5v_mcu_sc7 43680 1050560 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_129 GF018hv5v_mcu_sc7 43680 1058400 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_130 GF018hv5v_mcu_sc7 43680 1066240 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_131 GF018hv5v_mcu_sc7 43680 1074080 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_132 GF018hv5v_mcu_sc7 43680 1081920 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_133 GF018hv5v_mcu_sc7 43680 1089760 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_134 GF018hv5v_mcu_sc7 43680 1097600 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_135 GF018hv5v_mcu_sc7 43680 1105440 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_136 GF018hv5v_mcu_sc7 43680 1113280 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_137 GF018hv5v_mcu_sc7 43680 1121120 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_138 GF018hv5v_mcu_sc7 43680 1128960 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_139 GF018hv5v_mcu_sc7 43680 1136800 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_140 GF018hv5v_mcu_sc7 43680 1144640 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_141 GF018hv5v_mcu_sc7 43680 1152480 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_142 GF018hv5v_mcu_sc7 43680 1160320 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_143 GF018hv5v_mcu_sc7 43680 1168160 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_144 GF018hv5v_mcu_sc7 43680 1176000 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_145 GF018hv5v_mcu_sc7 43680 1183840 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_146 GF018hv5v_mcu_sc7 43680 1191680 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_147 GF018hv5v_mcu_sc7 43680 1199520 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_148 GF018hv5v_mcu_sc7 43680 1207360 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_149 GF018hv5v_mcu_sc7 43680 1215200 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_150 GF018hv5v_mcu_sc7 43680 1223040 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_151 GF018hv5v_mcu_sc7 43680 1230880 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_152 GF018hv5v_mcu_sc7 43680 1238720 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_153 GF018hv5v_mcu_sc7 43680 1246560 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_154 GF018hv5v_mcu_sc7 43680 1254400 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_155 GF018hv5v_mcu_sc7 43680 1262240 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_156 GF018hv5v_mcu_sc7 43680 1270080 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_157 GF018hv5v_mcu_sc7 43680 1277920 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_158 GF018hv5v_mcu_sc7 43680 1285760 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_159 GF018hv5v_mcu_sc7 43680 1293600 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_160 GF018hv5v_mcu_sc7 43680 1301440 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_161 GF018hv5v_mcu_sc7 43680 1309280 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_162 GF018hv5v_mcu_sc7 43680 1317120 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_163 GF018hv5v_mcu_sc7 43680 1324960 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_164 GF018hv5v_mcu_sc7 43680 1332800 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_165 GF018hv5v_mcu_sc7 43680 1340640 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_166 GF018hv5v_mcu_sc7 43680 1348480 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_167 GF018hv5v_mcu_sc7 43680 1356320 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_168 GF018hv5v_mcu_sc7 43680 1364160 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_169 GF018hv5v_mcu_sc7 43680 1372000 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_170 GF018hv5v_mcu_sc7 43680 1379840 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_171 GF018hv5v_mcu_sc7 43680 1387680 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_172 GF018hv5v_mcu_sc7 43680 1395520 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_173 GF018hv5v_mcu_sc7 43680 1403360 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_174 GF018hv5v_mcu_sc7 43680 1411200 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_175 GF018hv5v_mcu_sc7 43680 1419040 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_176 GF018hv5v_mcu_sc7 43680 1426880 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_177 GF018hv5v_mcu_sc7 43680 1434720 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_178 GF018hv5v_mcu_sc7 43680 1442560 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_179 GF018hv5v_mcu_sc7 43680 1450400 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_180 GF018hv5v_mcu_sc7 43680 1458240 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_181 GF018hv5v_mcu_sc7 43680 1466080 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_182 GF018hv5v_mcu_sc7 43680 1473920 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_183 GF018hv5v_mcu_sc7 43680 1481760 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_184 GF018hv5v_mcu_sc7 43680 1489600 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_185 GF018hv5v_mcu_sc7 43680 1497440 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_186 GF018hv5v_mcu_sc7 43680 1505280 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_187 GF018hv5v_mcu_sc7 43680 1513120 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_188 GF018hv5v_mcu_sc7 43680 1520960 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_189 GF018hv5v_mcu_sc7 43680 1528800 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_190 GF018hv5v_mcu_sc7 43680 1536640 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_191 GF018hv5v_mcu_sc7 43680 1544480 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_192 GF018hv5v_mcu_sc7 43680 1552320 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_193 GF018hv5v_mcu_sc7 43680 1560160 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_194 GF018hv5v_mcu_sc7 43680 1568000 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_195 GF018hv5v_mcu_sc7 43680 1575840 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_196 GF018hv5v_mcu_sc7 43680 1583680 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_197 GF018hv5v_mcu_sc7 43680 1591520 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_198 GF018hv5v_mcu_sc7 43680 1599360 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_199 GF018hv5v_mcu_sc7 43680 1607200 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_200 GF018hv5v_mcu_sc7 43680 1615040 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_201 GF018hv5v_mcu_sc7 43680 1622880 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_202 GF018hv5v_mcu_sc7 43680 1630720 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_203 GF018hv5v_mcu_sc7 43680 1638560 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_204 GF018hv5v_mcu_sc7 43680 1646400 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_205 GF018hv5v_mcu_sc7 43680 1654240 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_206 GF018hv5v_mcu_sc7 43680 1662080 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_207 GF018hv5v_mcu_sc7 43680 1669920 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_208 GF018hv5v_mcu_sc7 43680 1677760 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_209 GF018hv5v_mcu_sc7 43680 1685600 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_210 GF018hv5v_mcu_sc7 43680 1693440 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_211 GF018hv5v_mcu_sc7 43680 1701280 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_212 GF018hv5v_mcu_sc7 43680 1709120 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_213 GF018hv5v_mcu_sc7 43680 1716960 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_214 GF018hv5v_mcu_sc7 43680 1724800 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_215 GF018hv5v_mcu_sc7 43680 1732640 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_216 GF018hv5v_mcu_sc7 43680 1740480 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_217 GF018hv5v_mcu_sc7 43680 1748320 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_218 GF018hv5v_mcu_sc7 43680 1756160 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_219 GF018hv5v_mcu_sc7 43680 1764000 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_220 GF018hv5v_mcu_sc7 43680 1771840 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_221 GF018hv5v_mcu_sc7 43680 1779680 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_222 GF018hv5v_mcu_sc7 43680 1787520 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_223 GF018hv5v_mcu_sc7 43680 1795360 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_224 GF018hv5v_mcu_sc7 43680 1803200 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_225 GF018hv5v_mcu_sc7 43680 1811040 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_226 GF018hv5v_mcu_sc7 43680 1818880 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_227 GF018hv5v_mcu_sc7 43680 1826720 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_228 GF018hv5v_mcu_sc7 43680 1834560 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_229 GF018hv5v_mcu_sc7 43680 1842400 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_230 GF018hv5v_mcu_sc7 43680 1850240 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_231 GF018hv5v_mcu_sc7 43680 1858080 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_232 GF018hv5v_mcu_sc7 43680 1865920 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_233 GF018hv5v_mcu_sc7 43680 1873760 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_234 GF018hv5v_mcu_sc7 43680 1881600 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_235 GF018hv5v_mcu_sc7 43680 1889440 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_236 GF018hv5v_mcu_sc7 43680 1897280 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_237 GF018hv5v_mcu_sc7 43680 1905120 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_238 GF018hv5v_mcu_sc7 43680 1912960 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_239 GF018hv5v_mcu_sc7 43680 1920800 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_240 GF018hv5v_mcu_sc7 43680 1928640 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_241 GF018hv5v_mcu_sc7 43680 1936480 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_242 GF018hv5v_mcu_sc7 43680 1944320 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_243 GF018hv5v_mcu_sc7 43680 1952160 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_244 GF018hv5v_mcu_sc7 43680 1960000 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_245 GF018hv5v_mcu_sc7 43680 1967840 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_246 GF018hv5v_mcu_sc7 43680 1975680 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_247 GF018hv5v_mcu_sc7 43680 1983520 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_248 GF018hv5v_mcu_sc7 43680 1991360 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_249 GF018hv5v_mcu_sc7 43680 1999200 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_250 GF018hv5v_mcu_sc7 43680 2007040 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_251 GF018hv5v_mcu_sc7 43680 2014880 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_252 GF018hv5v_mcu_sc7 43680 2022720 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_253 GF018hv5v_mcu_sc7 43680 2030560 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_254 GF018hv5v_mcu_sc7 43680 2038400 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_255 GF018hv5v_mcu_sc7 43680 2046240 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_256 GF018hv5v_mcu_sc7 43680 2054080 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_257 GF018hv5v_mcu_sc7 43680 2061920 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_258 GF018hv5v_mcu_sc7 43680 2069760 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_259 GF018hv5v_mcu_sc7 43680 2077600 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_260 GF018hv5v_mcu_sc7 43680 2085440 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_261 GF018hv5v_mcu_sc7 43680 2093280 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_262 GF018hv5v_mcu_sc7 43680 2101120 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_263 GF018hv5v_mcu_sc7 43680 2108960 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_264 GF018hv5v_mcu_sc7 43680 2116800 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_265 GF018hv5v_mcu_sc7 43680 2124640 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_266 GF018hv5v_mcu_sc7 43680 2132480 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_267 GF018hv5v_mcu_sc7 43680 2140320 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_268 GF018hv5v_mcu_sc7 43680 2148160 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_269 GF018hv5v_mcu_sc7 43680 2156000 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_270 GF018hv5v_mcu_sc7 43680 2163840 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_271 GF018hv5v_mcu_sc7 43680 2171680 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_272 GF018hv5v_mcu_sc7 43680 2179520 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_273 GF018hv5v_mcu_sc7 43680 2187360 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_274 GF018hv5v_mcu_sc7 43680 2195200 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_275 GF018hv5v_mcu_sc7 43680 2203040 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_276 GF018hv5v_mcu_sc7 43680 2210880 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_277 GF018hv5v_mcu_sc7 43680 2218720 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_278 GF018hv5v_mcu_sc7 43680 2226560 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_279 GF018hv5v_mcu_sc7 43680 2234400 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_280 GF018hv5v_mcu_sc7 43680 2242240 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_281 GF018hv5v_mcu_sc7 43680 2250080 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_282 GF018hv5v_mcu_sc7 43680 2257920 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_283 GF018hv5v_mcu_sc7 43680 2265760 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_284 GF018hv5v_mcu_sc7 43680 2273600 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_285 GF018hv5v_mcu_sc7 43680 2281440 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_286 GF018hv5v_mcu_sc7 43680 2289280 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_287 GF018hv5v_mcu_sc7 43680 2297120 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_288 GF018hv5v_mcu_sc7 43680 2304960 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_289 GF018hv5v_mcu_sc7 43680 2312800 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_290 GF018hv5v_mcu_sc7 43680 2320640 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_291 GF018hv5v_mcu_sc7 43680 2328480 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_292 GF018hv5v_mcu_sc7 43680 2336320 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_293 GF018hv5v_mcu_sc7 43680 2344160 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_294 GF018hv5v_mcu_sc7 43680 2352000 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_295 GF018hv5v_mcu_sc7 43680 2359840 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_296 GF018hv5v_mcu_sc7 43680 2367680 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_297 GF018hv5v_mcu_sc7 43680 2375520 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_298 GF018hv5v_mcu_sc7 43680 2383360 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_299 GF018hv5v_mcu_sc7 43680 2391200 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_300 GF018hv5v_mcu_sc7 43680 2399040 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_301 GF018hv5v_mcu_sc7 43680 2406880 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_302 GF018hv5v_mcu_sc7 43680 2414720 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_303 GF018hv5v_mcu_sc7 43680 2422560 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_304 GF018hv5v_mcu_sc7 43680 2430400 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_305 GF018hv5v_mcu_sc7 43680 2438240 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_306 GF018hv5v_mcu_sc7 43680 2446080 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_307 GF018hv5v_mcu_sc7 43680 2453920 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_308 GF018hv5v_mcu_sc7 43680 2461760 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_309 GF018hv5v_mcu_sc7 43680 2469600 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_310 GF018hv5v_mcu_sc7 43680 2477440 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_311 GF018hv5v_mcu_sc7 43680 2485280 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_312 GF018hv5v_mcu_sc7 43680 2493120 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_313 GF018hv5v_mcu_sc7 43680 2500960 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_314 GF018hv5v_mcu_sc7 43680 2508800 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_315 GF018hv5v_mcu_sc7 43680 2516640 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_316 GF018hv5v_mcu_sc7 43680 2524480 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_317 GF018hv5v_mcu_sc7 43680 2532320 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_318 GF018hv5v_mcu_sc7 43680 2540160 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_319 GF018hv5v_mcu_sc7 43680 2548000 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_320 GF018hv5v_mcu_sc7 43680 2555840 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_321 GF018hv5v_mcu_sc7 43680 2563680 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_322 GF018hv5v_mcu_sc7 43680 2571520 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_323 GF018hv5v_mcu_sc7 43680 2579360 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_324 GF018hv5v_mcu_sc7 43680 2587200 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_325 GF018hv5v_mcu_sc7 43680 2595040 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_326 GF018hv5v_mcu_sc7 43680 2602880 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_327 GF018hv5v_mcu_sc7 43680 2610720 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_328 GF018hv5v_mcu_sc7 43680 2618560 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_329 GF018hv5v_mcu_sc7 43680 2626400 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_330 GF018hv5v_mcu_sc7 43680 2634240 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_331 GF018hv5v_mcu_sc7 43680 2642080 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_332 GF018hv5v_mcu_sc7 43680 2649920 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_333 GF018hv5v_mcu_sc7 43680 2657760 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_334 GF018hv5v_mcu_sc7 43680 2665600 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_335 GF018hv5v_mcu_sc7 43680 2673440 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_336 GF018hv5v_mcu_sc7 43680 2681280 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_337 GF018hv5v_mcu_sc7 43680 2689120 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_338 GF018hv5v_mcu_sc7 43680 2696960 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_339 GF018hv5v_mcu_sc7 43680 2704800 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_340 GF018hv5v_mcu_sc7 43680 2712640 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_341 GF018hv5v_mcu_sc7 43680 2720480 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_342 GF018hv5v_mcu_sc7 43680 2728320 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_343 GF018hv5v_mcu_sc7 43680 2736160 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_344 GF018hv5v_mcu_sc7 43680 2744000 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_345 GF018hv5v_mcu_sc7 43680 2751840 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_346 GF018hv5v_mcu_sc7 43680 2759680 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_347 GF018hv5v_mcu_sc7 43680 2767520 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_348 GF018hv5v_mcu_sc7 43680 2775360 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_349 GF018hv5v_mcu_sc7 43680 2783200 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_350 GF018hv5v_mcu_sc7 43680 2791040 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_351 GF018hv5v_mcu_sc7 43680 2798880 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_352 GF018hv5v_mcu_sc7 43680 2806720 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_353 GF018hv5v_mcu_sc7 43680 2814560 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_354 GF018hv5v_mcu_sc7 43680 2822400 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_355 GF018hv5v_mcu_sc7 43680 2830240 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_356 GF018hv5v_mcu_sc7 43680 2838080 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_357 GF018hv5v_mcu_sc7 43680 2845920 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_358 GF018hv5v_mcu_sc7 43680 2853760 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_359 GF018hv5v_mcu_sc7 43680 2861600 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_360 GF018hv5v_mcu_sc7 43680 2869440 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_361 GF018hv5v_mcu_sc7 43680 2877280 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_362 GF018hv5v_mcu_sc7 43680 2885120 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_363 GF018hv5v_mcu_sc7 43680 2892960 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_364 GF018hv5v_mcu_sc7 43680 2900800 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_365 GF018hv5v_mcu_sc7 43680 2908640 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_366 GF018hv5v_mcu_sc7 43680 2916480 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_367 GF018hv5v_mcu_sc7 43680 2924320 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_368 GF018hv5v_mcu_sc7 43680 2932160 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_369 GF018hv5v_mcu_sc7 43680 2940000 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_370 GF018hv5v_mcu_sc7 43680 2947840 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_371 GF018hv5v_mcu_sc7 43680 2955680 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_372 GF018hv5v_mcu_sc7 43680 2963520 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_373 GF018hv5v_mcu_sc7 43680 2971360 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_374 GF018hv5v_mcu_sc7 43680 2979200 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_375 GF018hv5v_mcu_sc7 43680 2987040 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_376 GF018hv5v_mcu_sc7 43680 2994880 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_377 GF018hv5v_mcu_sc7 43680 3002720 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_378 GF018hv5v_mcu_sc7 43680 3010560 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_379 GF018hv5v_mcu_sc7 43680 3018400 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_380 GF018hv5v_mcu_sc7 43680 3026240 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_381 GF018hv5v_mcu_sc7 43680 3034080 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_382 GF018hv5v_mcu_sc7 43680 3041920 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_383 GF018hv5v_mcu_sc7 43680 3049760 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_384 GF018hv5v_mcu_sc7 43680 3057600 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_385 GF018hv5v_mcu_sc7 43680 3065440 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_386 GF018hv5v_mcu_sc7 43680 3073280 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_387 GF018hv5v_mcu_sc7 43680 3081120 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_388 GF018hv5v_mcu_sc7 43680 3088960 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_389 GF018hv5v_mcu_sc7 43680 3096800 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_390 GF018hv5v_mcu_sc7 43680 3104640 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_391 GF018hv5v_mcu_sc7 43680 3112480 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_392 GF018hv5v_mcu_sc7 43680 3120320 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_393 GF018hv5v_mcu_sc7 43680 3128160 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_394 GF018hv5v_mcu_sc7 43680 3136000 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_395 GF018hv5v_mcu_sc7 43680 3143840 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_396 GF018hv5v_mcu_sc7 43680 3151680 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_397 GF018hv5v_mcu_sc7 43680 3159520 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_398 GF018hv5v_mcu_sc7 43680 3167360 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_399 GF018hv5v_mcu_sc7 43680 3175200 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_400 GF018hv5v_mcu_sc7 43680 3183040 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_401 GF018hv5v_mcu_sc7 43680 3190880 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_402 GF018hv5v_mcu_sc7 43680 3198720 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_403 GF018hv5v_mcu_sc7 43680 3206560 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_404 GF018hv5v_mcu_sc7 43680 3214400 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_405 GF018hv5v_mcu_sc7 43680 3222240 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_406 GF018hv5v_mcu_sc7 43680 3230080 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_407 GF018hv5v_mcu_sc7 43680 3237920 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_408 GF018hv5v_mcu_sc7 43680 3245760 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_409 GF018hv5v_mcu_sc7 43680 3253600 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_410 GF018hv5v_mcu_sc7 43680 3261440 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_411 GF018hv5v_mcu_sc7 43680 3269280 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_412 GF018hv5v_mcu_sc7 43680 3277120 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_413 GF018hv5v_mcu_sc7 43680 3284960 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_414 GF018hv5v_mcu_sc7 43680 3292800 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_415 GF018hv5v_mcu_sc7 43680 3300640 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_416 GF018hv5v_mcu_sc7 43680 3308480 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_417 GF018hv5v_mcu_sc7 43680 3316320 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_418 GF018hv5v_mcu_sc7 43680 3324160 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_419 GF018hv5v_mcu_sc7 43680 3332000 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_420 GF018hv5v_mcu_sc7 43680 3339840 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_421 GF018hv5v_mcu_sc7 43680 3347680 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_422 GF018hv5v_mcu_sc7 43680 3355520 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_423 GF018hv5v_mcu_sc7 43680 3363360 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_424 GF018hv5v_mcu_sc7 43680 3371200 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_425 GF018hv5v_mcu_sc7 43680 3379040 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_426 GF018hv5v_mcu_sc7 43680 3386880 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_427 GF018hv5v_mcu_sc7 43680 3394720 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_428 GF018hv5v_mcu_sc7 43680 3402560 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_429 GF018hv5v_mcu_sc7 43680 3410400 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_430 GF018hv5v_mcu_sc7 43680 3418240 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_431 GF018hv5v_mcu_sc7 43680 3426080 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_432 GF018hv5v_mcu_sc7 43680 3433920 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_433 GF018hv5v_mcu_sc7 43680 3441760 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_434 GF018hv5v_mcu_sc7 43680 3449600 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_435 GF018hv5v_mcu_sc7 43680 3457440 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_436 GF018hv5v_mcu_sc7 43680 3465280 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_437 GF018hv5v_mcu_sc7 43680 3473120 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_438 GF018hv5v_mcu_sc7 43680 3480960 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_439 GF018hv5v_mcu_sc7 43680 3488800 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_440 GF018hv5v_mcu_sc7 43680 3496640 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_441 GF018hv5v_mcu_sc7 43680 3504480 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_442 GF018hv5v_mcu_sc7 43680 3512320 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_443 GF018hv5v_mcu_sc7 43680 3520160 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_444 GF018hv5v_mcu_sc7 43680 3528000 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_445 GF018hv5v_mcu_sc7 43680 3535840 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_446 GF018hv5v_mcu_sc7 43680 3543680 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_447 GF018hv5v_mcu_sc7 43680 3551520 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_448 GF018hv5v_mcu_sc7 43680 3559360 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_449 GF018hv5v_mcu_sc7 43680 3567200 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_450 GF018hv5v_mcu_sc7 43680 3575040 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_451 GF018hv5v_mcu_sc7 43680 3582880 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_452 GF018hv5v_mcu_sc7 43680 3590720 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_453 GF018hv5v_mcu_sc7 43680 3598560 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_454 GF018hv5v_mcu_sc7 43680 3606400 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_455 GF018hv5v_mcu_sc7 43680 3614240 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_456 GF018hv5v_mcu_sc7 43680 3622080 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_457 GF018hv5v_mcu_sc7 43680 3629920 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_458 GF018hv5v_mcu_sc7 43680 3637760 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_459 GF018hv5v_mcu_sc7 43680 3645600 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_460 GF018hv5v_mcu_sc7 43680 3653440 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_461 GF018hv5v_mcu_sc7 43680 3661280 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_462 GF018hv5v_mcu_sc7 43680 3669120 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_463 GF018hv5v_mcu_sc7 43680 3676960 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_464 GF018hv5v_mcu_sc7 43680 3684800 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_465 GF018hv5v_mcu_sc7 43680 3692640 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_466 GF018hv5v_mcu_sc7 43680 3700480 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_467 GF018hv5v_mcu_sc7 43680 3708320 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_468 GF018hv5v_mcu_sc7 43680 3716160 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_469 GF018hv5v_mcu_sc7 43680 3724000 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_470 GF018hv5v_mcu_sc7 43680 3731840 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_471 GF018hv5v_mcu_sc7 43680 3739680 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_472 GF018hv5v_mcu_sc7 43680 3747520 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_473 GF018hv5v_mcu_sc7 43680 3755360 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_474 GF018hv5v_mcu_sc7 43680 3763200 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_475 GF018hv5v_mcu_sc7 43680 3771040 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_476 GF018hv5v_mcu_sc7 43680 3778880 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_477 GF018hv5v_mcu_sc7 43680 3786720 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_478 GF018hv5v_mcu_sc7 43680 3794560 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_479 GF018hv5v_mcu_sc7 43680 3802400 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_480 GF018hv5v_mcu_sc7 43680 3810240 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_481 GF018hv5v_mcu_sc7 43680 3818080 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_482 GF018hv5v_mcu_sc7 43680 3825920 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_483 GF018hv5v_mcu_sc7 43680 3833760 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_484 GF018hv5v_mcu_sc7 43680 3841600 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_485 GF018hv5v_mcu_sc7 43680 3849440 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_486 GF018hv5v_mcu_sc7 43680 3857280 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_487 GF018hv5v_mcu_sc7 43680 3865120 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_488 GF018hv5v_mcu_sc7 43680 3872960 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_489 GF018hv5v_mcu_sc7 43680 3880800 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_490 GF018hv5v_mcu_sc7 43680 3888640 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_491 GF018hv5v_mcu_sc7 43680 3896480 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_492 GF018hv5v_mcu_sc7 43680 3904320 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_493 GF018hv5v_mcu_sc7 43680 3912160 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_494 GF018hv5v_mcu_sc7 43680 3920000 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_495 GF018hv5v_mcu_sc7 43680 3927840 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_496 GF018hv5v_mcu_sc7 43680 3935680 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_497 GF018hv5v_mcu_sc7 43680 3943520 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_498 GF018hv5v_mcu_sc7 43680 3951360 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_499 GF018hv5v_mcu_sc7 43680 3959200 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_500 GF018hv5v_mcu_sc7 43680 3967040 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_501 GF018hv5v_mcu_sc7 43680 3974880 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_502 GF018hv5v_mcu_sc7 43680 3982720 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_503 GF018hv5v_mcu_sc7 43680 3990560 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_504 GF018hv5v_mcu_sc7 43680 3998400 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_505 GF018hv5v_mcu_sc7 43680 4006240 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_506 GF018hv5v_mcu_sc7 43680 4014080 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_507 GF018hv5v_mcu_sc7 43680 4021920 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_508 GF018hv5v_mcu_sc7 43680 4029760 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_509 GF018hv5v_mcu_sc7 43680 4037600 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_510 GF018hv5v_mcu_sc7 43680 4045440 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_511 GF018hv5v_mcu_sc7 43680 4053280 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_512 GF018hv5v_mcu_sc7 43680 4061120 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_513 GF018hv5v_mcu_sc7 43680 4068960 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_514 GF018hv5v_mcu_sc7 43680 4076800 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_515 GF018hv5v_mcu_sc7 43680 4084640 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_516 GF018hv5v_mcu_sc7 43680 4092480 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_517 GF018hv5v_mcu_sc7 43680 4100320 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_518 GF018hv5v_mcu_sc7 43680 4108160 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_519 GF018hv5v_mcu_sc7 43680 4116000 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_520 GF018hv5v_mcu_sc7 43680 4123840 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_521 GF018hv5v_mcu_sc7 43680 4131680 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_522 GF018hv5v_mcu_sc7 43680 4139520 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_523 GF018hv5v_mcu_sc7 43680 4147360 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_524 GF018hv5v_mcu_sc7 43680 4155200 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_525 GF018hv5v_mcu_sc7 43680 4163040 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_526 GF018hv5v_mcu_sc7 43680 4170880 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_527 GF018hv5v_mcu_sc7 43680 4178720 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_528 GF018hv5v_mcu_sc7 43680 4186560 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_529 GF018hv5v_mcu_sc7 43680 4194400 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_530 GF018hv5v_mcu_sc7 43680 4202240 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_531 GF018hv5v_mcu_sc7 43680 4210080 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_532 GF018hv5v_mcu_sc7 43680 4217920 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_533 GF018hv5v_mcu_sc7 43680 4225760 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_534 GF018hv5v_mcu_sc7 43680 4233600 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_535 GF018hv5v_mcu_sc7 43680 4241440 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_536 GF018hv5v_mcu_sc7 43680 4249280 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_537 GF018hv5v_mcu_sc7 43680 4257120 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_538 GF018hv5v_mcu_sc7 43680 4264960 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_539 GF018hv5v_mcu_sc7 43680 4272800 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_540 GF018hv5v_mcu_sc7 43680 4280640 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_541 GF018hv5v_mcu_sc7 43680 4288480 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_542 GF018hv5v_mcu_sc7 43680 4296320 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_543 GF018hv5v_mcu_sc7 43680 4304160 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_544 GF018hv5v_mcu_sc7 43680 4312000 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_545 GF018hv5v_mcu_sc7 43680 4319840 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_546 GF018hv5v_mcu_sc7 43680 4327680 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_547 GF018hv5v_mcu_sc7 43680 4335520 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_548 GF018hv5v_mcu_sc7 43680 4343360 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_549 GF018hv5v_mcu_sc7 43680 4351200 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_550 GF018hv5v_mcu_sc7 43680 4359040 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_551 GF018hv5v_mcu_sc7 43680 4366880 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_552 GF018hv5v_mcu_sc7 43680 4374720 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_553 GF018hv5v_mcu_sc7 43680 4382560 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_554 GF018hv5v_mcu_sc7 43680 4390400 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_555 GF018hv5v_mcu_sc7 43680 4398240 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_556 GF018hv5v_mcu_sc7 43680 4406080 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_557 GF018hv5v_mcu_sc7 43680 4413920 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_558 GF018hv5v_mcu_sc7 43680 4421760 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_559 GF018hv5v_mcu_sc7 43680 4429600 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_560 GF018hv5v_mcu_sc7 43680 4437440 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_561 GF018hv5v_mcu_sc7 43680 4445280 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_562 GF018hv5v_mcu_sc7 43680 4453120 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_563 GF018hv5v_mcu_sc7 43680 4460960 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_564 GF018hv5v_mcu_sc7 43680 4468800 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_565 GF018hv5v_mcu_sc7 43680 4476640 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_566 GF018hv5v_mcu_sc7 43680 4484480 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_567 GF018hv5v_mcu_sc7 43680 4492320 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_568 GF018hv5v_mcu_sc7 43680 4500160 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_569 GF018hv5v_mcu_sc7 43680 4508000 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_570 GF018hv5v_mcu_sc7 43680 4515840 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_571 GF018hv5v_mcu_sc7 43680 4523680 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_572 GF018hv5v_mcu_sc7 43680 4531520 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_573 GF018hv5v_mcu_sc7 43680 4539360 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_574 GF018hv5v_mcu_sc7 43680 4547200 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_575 GF018hv5v_mcu_sc7 43680 4555040 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_576 GF018hv5v_mcu_sc7 43680 4562880 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_577 GF018hv5v_mcu_sc7 43680 4570720 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_578 GF018hv5v_mcu_sc7 43680 4578560 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_579 GF018hv5v_mcu_sc7 43680 4586400 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_580 GF018hv5v_mcu_sc7 43680 4594240 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_581 GF018hv5v_mcu_sc7 43680 4602080 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_582 GF018hv5v_mcu_sc7 43680 4609920 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_583 GF018hv5v_mcu_sc7 43680 4617760 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_584 GF018hv5v_mcu_sc7 43680 4625600 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_585 GF018hv5v_mcu_sc7 43680 4633440 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_586 GF018hv5v_mcu_sc7 43680 4641280 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_587 GF018hv5v_mcu_sc7 43680 4649120 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_588 GF018hv5v_mcu_sc7 43680 4656960 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_589 GF018hv5v_mcu_sc7 43680 4664800 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_590 GF018hv5v_mcu_sc7 43680 4672640 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_591 GF018hv5v_mcu_sc7 43680 4680480 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_592 GF018hv5v_mcu_sc7 43680 4688320 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_593 GF018hv5v_mcu_sc7 43680 4696160 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_594 GF018hv5v_mcu_sc7 43680 4704000 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_595 GF018hv5v_mcu_sc7 43680 4711840 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_596 GF018hv5v_mcu_sc7 43680 4719680 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_597 GF018hv5v_mcu_sc7 43680 4727520 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_598 GF018hv5v_mcu_sc7 43680 4735360 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_599 GF018hv5v_mcu_sc7 43680 4743200 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_600 GF018hv5v_mcu_sc7 43680 4751040 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_601 GF018hv5v_mcu_sc7 43680 4758880 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_602 GF018hv5v_mcu_sc7 43680 4766720 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_603 GF018hv5v_mcu_sc7 43680 4774560 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_604 GF018hv5v_mcu_sc7 43680 4782400 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_605 GF018hv5v_mcu_sc7 43680 4790240 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_606 GF018hv5v_mcu_sc7 43680 4798080 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_607 GF018hv5v_mcu_sc7 43680 4805920 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_608 GF018hv5v_mcu_sc7 43680 4813760 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_609 GF018hv5v_mcu_sc7 43680 4821600 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_610 GF018hv5v_mcu_sc7 43680 4829440 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_611 GF018hv5v_mcu_sc7 43680 4837280 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_612 GF018hv5v_mcu_sc7 43680 4845120 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_613 GF018hv5v_mcu_sc7 43680 4852960 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_614 GF018hv5v_mcu_sc7 43680 4860800 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_615 GF018hv5v_mcu_sc7 43680 4868640 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_616 GF018hv5v_mcu_sc7 43680 4876480 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_617 GF018hv5v_mcu_sc7 43680 4884320 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_618 GF018hv5v_mcu_sc7 43680 4892160 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_619 GF018hv5v_mcu_sc7 43680 4900000 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_620 GF018hv5v_mcu_sc7 43680 4907840 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_621 GF018hv5v_mcu_sc7 43680 4915680 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_622 GF018hv5v_mcu_sc7 43680 4923520 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_623 GF018hv5v_mcu_sc7 43680 4931360 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_624 GF018hv5v_mcu_sc7 43680 4939200 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_625 GF018hv5v_mcu_sc7 43680 4947040 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_626 GF018hv5v_mcu_sc7 43680 4954880 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_627 GF018hv5v_mcu_sc7 43680 4962720 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_628 GF018hv5v_mcu_sc7 43680 4970560 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_629 GF018hv5v_mcu_sc7 43680 4978400 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_630 GF018hv5v_mcu_sc7 43680 4986240 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_631 GF018hv5v_mcu_sc7 43680 4994080 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_632 GF018hv5v_mcu_sc7 43680 5001920 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_633 GF018hv5v_mcu_sc7 43680 5009760 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_634 GF018hv5v_mcu_sc7 43680 5017600 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_635 GF018hv5v_mcu_sc7 43680 5025440 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_636 GF018hv5v_mcu_sc7 43680 5033280 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_637 GF018hv5v_mcu_sc7 43680 5041120 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_638 GF018hv5v_mcu_sc7 43680 5048960 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_639 GF018hv5v_mcu_sc7 43680 5056800 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_640 GF018hv5v_mcu_sc7 43680 5064640 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_641 GF018hv5v_mcu_sc7 43680 5072480 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_642 GF018hv5v_mcu_sc7 43680 5080320 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_643 GF018hv5v_mcu_sc7 43680 5088160 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_644 GF018hv5v_mcu_sc7 43680 5096000 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_645 GF018hv5v_mcu_sc7 43680 5103840 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_646 GF018hv5v_mcu_sc7 43680 5111680 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_647 GF018hv5v_mcu_sc7 43680 5119520 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_648 GF018hv5v_mcu_sc7 43680 5127360 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_649 GF018hv5v_mcu_sc7 43680 5135200 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_650 GF018hv5v_mcu_sc7 43680 5143040 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_651 GF018hv5v_mcu_sc7 43680 5150880 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_652 GF018hv5v_mcu_sc7 43680 5158720 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_653 GF018hv5v_mcu_sc7 43680 5166560 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_654 GF018hv5v_mcu_sc7 43680 5174400 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_655 GF018hv5v_mcu_sc7 43680 5182240 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_656 GF018hv5v_mcu_sc7 43680 5190080 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_657 GF018hv5v_mcu_sc7 43680 5197920 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_658 GF018hv5v_mcu_sc7 43680 5205760 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_659 GF018hv5v_mcu_sc7 43680 5213600 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_660 GF018hv5v_mcu_sc7 43680 5221440 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_661 GF018hv5v_mcu_sc7 43680 5229280 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_662 GF018hv5v_mcu_sc7 43680 5237120 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_663 GF018hv5v_mcu_sc7 43680 5244960 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_664 GF018hv5v_mcu_sc7 43680 5252800 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_665 GF018hv5v_mcu_sc7 43680 5260640 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_666 GF018hv5v_mcu_sc7 43680 5268480 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_667 GF018hv5v_mcu_sc7 43680 5276320 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_668 GF018hv5v_mcu_sc7 43680 5284160 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_669 GF018hv5v_mcu_sc7 43680 5292000 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_670 GF018hv5v_mcu_sc7 43680 5299840 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_671 GF018hv5v_mcu_sc7 43680 5307680 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_672 GF018hv5v_mcu_sc7 43680 5315520 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_673 GF018hv5v_mcu_sc7 43680 5323360 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_674 GF018hv5v_mcu_sc7 43680 5331200 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_675 GF018hv5v_mcu_sc7 43680 5339040 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_676 GF018hv5v_mcu_sc7 43680 5346880 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_677 GF018hv5v_mcu_sc7 43680 5354720 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_678 GF018hv5v_mcu_sc7 43680 5362560 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_679 GF018hv5v_mcu_sc7 43680 5370400 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_680 GF018hv5v_mcu_sc7 43680 5378240 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_681 GF018hv5v_mcu_sc7 43680 5386080 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_682 GF018hv5v_mcu_sc7 43680 5393920 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_683 GF018hv5v_mcu_sc7 43680 5401760 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_684 GF018hv5v_mcu_sc7 43680 5409600 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_685 GF018hv5v_mcu_sc7 43680 5417440 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_686 GF018hv5v_mcu_sc7 43680 5425280 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_687 GF018hv5v_mcu_sc7 43680 5433120 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_688 GF018hv5v_mcu_sc7 43680 5440960 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_689 GF018hv5v_mcu_sc7 43680 5448800 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_690 GF018hv5v_mcu_sc7 43680 5456640 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_691 GF018hv5v_mcu_sc7 43680 5464480 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_692 GF018hv5v_mcu_sc7 43680 5472320 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_693 GF018hv5v_mcu_sc7 43680 5480160 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_694 GF018hv5v_mcu_sc7 43680 5488000 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_695 GF018hv5v_mcu_sc7 43680 5495840 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_696 GF018hv5v_mcu_sc7 43680 5503680 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_697 GF018hv5v_mcu_sc7 43680 5511520 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_698 GF018hv5v_mcu_sc7 43680 5519360 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_699 GF018hv5v_mcu_sc7 43680 5527200 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_700 GF018hv5v_mcu_sc7 43680 5535040 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_701 GF018hv5v_mcu_sc7 43680 5542880 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_702 GF018hv5v_mcu_sc7 43680 5550720 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_703 GF018hv5v_mcu_sc7 43680 5558560 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_704 GF018hv5v_mcu_sc7 43680 5566400 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_705 GF018hv5v_mcu_sc7 43680 5574240 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_706 GF018hv5v_mcu_sc7 43680 5582080 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_707 GF018hv5v_mcu_sc7 43680 5589920 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_708 GF018hv5v_mcu_sc7 43680 5597760 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_709 GF018hv5v_mcu_sc7 43680 5605600 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_710 GF018hv5v_mcu_sc7 43680 5613440 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_711 GF018hv5v_mcu_sc7 43680 5621280 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_712 GF018hv5v_mcu_sc7 43680 5629120 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_713 GF018hv5v_mcu_sc7 43680 5636960 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_714 GF018hv5v_mcu_sc7 43680 5644800 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_715 GF018hv5v_mcu_sc7 43680 5652640 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_716 GF018hv5v_mcu_sc7 43680 5660480 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_717 GF018hv5v_mcu_sc7 43680 5668320 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_718 GF018hv5v_mcu_sc7 43680 5676160 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_719 GF018hv5v_mcu_sc7 43680 5684000 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_720 GF018hv5v_mcu_sc7 43680 5691840 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_721 GF018hv5v_mcu_sc7 43680 5699680 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_722 GF018hv5v_mcu_sc7 43680 5707520 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_723 GF018hv5v_mcu_sc7 43680 5715360 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_724 GF018hv5v_mcu_sc7 43680 5723200 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_725 GF018hv5v_mcu_sc7 43680 5731040 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_726 GF018hv5v_mcu_sc7 43680 5738880 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_727 GF018hv5v_mcu_sc7 43680 5746720 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_728 GF018hv5v_mcu_sc7 43680 5754560 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_729 GF018hv5v_mcu_sc7 43680 5762400 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_730 GF018hv5v_mcu_sc7 43680 5770240 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_731 GF018hv5v_mcu_sc7 43680 5778080 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_732 GF018hv5v_mcu_sc7 43680 5785920 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_733 GF018hv5v_mcu_sc7 43680 5793760 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_734 GF018hv5v_mcu_sc7 43680 5801600 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_735 GF018hv5v_mcu_sc7 43680 5809440 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_736 GF018hv5v_mcu_sc7 43680 5817280 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_737 GF018hv5v_mcu_sc7 43680 5825120 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_738 GF018hv5v_mcu_sc7 43680 5832960 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_739 GF018hv5v_mcu_sc7 43680 5840800 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_740 GF018hv5v_mcu_sc7 43680 5848640 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_741 GF018hv5v_mcu_sc7 43680 5856480 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_742 GF018hv5v_mcu_sc7 43680 5864320 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_743 GF018hv5v_mcu_sc7 43680 5872160 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_744 GF018hv5v_mcu_sc7 43680 5880000 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_745 GF018hv5v_mcu_sc7 43680 5887840 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_746 GF018hv5v_mcu_sc7 43680 5895680 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_747 GF018hv5v_mcu_sc7 43680 5903520 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_748 GF018hv5v_mcu_sc7 43680 5911360 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_749 GF018hv5v_mcu_sc7 43680 5919200 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_750 GF018hv5v_mcu_sc7 43680 5927040 N DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_751 GF018hv5v_mcu_sc7 43680 5934880 FS DO 5279 BY 1 STEP 1120 0 ;
+ROW ROW_752 GF018hv5v_mcu_sc7 43680 5942720 N DO 5279 BY 1 STEP 1120 0 ;
+TRACKS X 560 DO 5357 STEP 1120 LAYER Metal1 ;
+TRACKS Y 560 DO 5357 STEP 1120 LAYER Metal1 ;
+TRACKS X 560 DO 5357 STEP 1120 LAYER Metal2 ;
+TRACKS Y 560 DO 5357 STEP 1120 LAYER Metal2 ;
+TRACKS X 560 DO 5357 STEP 1120 LAYER Metal3 ;
+TRACKS Y 560 DO 5357 STEP 1120 LAYER Metal3 ;
+TRACKS X 560 DO 5357 STEP 1120 LAYER Metal4 ;
+TRACKS Y 560 DO 5357 STEP 1120 LAYER Metal4 ;
+TRACKS X 560 DO 5357 STEP 1120 LAYER Metal5 ;
+TRACKS Y 560 DO 5357 STEP 1120 LAYER Metal5 ;
+GCELLGRID X 0 DO 357 STEP 16800 ;
+GCELLGRID Y 0 DO 357 STEP 16800 ;
+VIAS 1 ;
+ - via4_5_6200_6200_6_6_1040_1040 + VIARULE Via4_GEN_HH + CUTSIZE 520 520 + LAYERS Metal4 Via4 Metal5 + CUTSPACING 520 520 + ENCLOSURE 240 120 120 240 + ROWCOL 6 6 ;
+END VIAS
+PINS 418 ;
+ - io_in[0] + NET io_in[0] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -7200 -1120 ) ( 7200 1120 )
+ + PLACED ( 6002400 67760 ) N ;
+ - io_in[10] + NET io_in[10] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -7200 -1120 ) ( 7200 1120 )
+ + PLACED ( 6002400 4066160 ) N ;
+ - io_in[11] + NET io_in[11] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -7200 -1120 ) ( 7200 1120 )
+ + PLACED ( 6002400 4466000 ) N ;
+ - io_in[12] + NET io_in[12] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -7200 -1120 ) ( 7200 1120 )
+ + PLACED ( 6002400 4865840 ) N ;
+ - io_in[13] + NET io_in[13] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -7200 -1120 ) ( 7200 1120 )
+ + PLACED ( 6002400 5265680 ) N ;
+ - io_in[14] + NET io_in[14] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -7200 -1120 ) ( 7200 1120 )
+ + PLACED ( 6002400 5665520 ) N ;
+ - io_in[15] + NET io_in[15] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 5882800 6002400 ) N ;
+ - io_in[16] + NET io_in[16] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 5217520 6002400 ) N ;
+ - io_in[17] + NET io_in[17] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 4552240 6002400 ) N ;
+ - io_in[18] + NET io_in[18] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 3886960 6002400 ) N ;
+ - io_in[19] + NET io_in[19] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 3221680 6002400 ) N ;
+ - io_in[1] + NET io_in[1] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -7200 -1120 ) ( 7200 1120 )
+ + PLACED ( 6002400 467600 ) N ;
+ - io_in[20] + NET io_in[20] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 2556400 6002400 ) N ;
+ - io_in[21] + NET io_in[21] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 1891120 6002400 ) N ;
+ - io_in[22] + NET io_in[22] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 1225840 6002400 ) N ;
+ - io_in[23] + NET io_in[23] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 560560 6002400 ) N ;
+ - io_in[24] + NET io_in[24] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -7200 -1120 ) ( 7200 1120 )
+ + PLACED ( -2400 5915280 ) N ;
+ - io_in[25] + NET io_in[25] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -7200 -1120 ) ( 7200 1120 )
+ + PLACED ( -2400 5488560 ) N ;
+ - io_in[26] + NET io_in[26] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -7200 -1120 ) ( 7200 1120 )
+ + PLACED ( -2400 5061840 ) N ;
+ - io_in[27] + NET io_in[27] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -7200 -1120 ) ( 7200 1120 )
+ + PLACED ( -2400 4635120 ) N ;
+ - io_in[28] + NET io_in[28] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -7200 -1120 ) ( 7200 1120 )
+ + PLACED ( -2400 4208400 ) N ;
+ - io_in[29] + NET io_in[29] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -7200 -1120 ) ( 7200 1120 )
+ + PLACED ( -2400 3781680 ) N ;
+ - io_in[2] + NET io_in[2] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -7200 -1120 ) ( 7200 1120 )
+ + PLACED ( 6002400 867440 ) N ;
+ - io_in[30] + NET io_in[30] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -7200 -1120 ) ( 7200 1120 )
+ + PLACED ( -2400 3354960 ) N ;
+ - io_in[31] + NET io_in[31] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -7200 -1120 ) ( 7200 1120 )
+ + PLACED ( -2400 2928240 ) N ;
+ - io_in[32] + NET io_in[32] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -7200 -1120 ) ( 7200 1120 )
+ + PLACED ( -2400 2501520 ) N ;
+ - io_in[33] + NET io_in[33] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -7200 -1120 ) ( 7200 1120 )
+ + PLACED ( -2400 2074800 ) N ;
+ - io_in[34] + NET io_in[34] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -7200 -1120 ) ( 7200 1120 )
+ + PLACED ( -2400 1648080 ) N ;
+ - io_in[35] + NET io_in[35] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -7200 -1120 ) ( 7200 1120 )
+ + PLACED ( -2400 1221360 ) N ;
+ - io_in[36] + NET io_in[36] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -7200 -1120 ) ( 7200 1120 )
+ + PLACED ( -2400 794640 ) N ;
+ - io_in[37] + NET io_in[37] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -7200 -1120 ) ( 7200 1120 )
+ + PLACED ( -2400 367920 ) N ;
+ - io_in[3] + NET io_in[3] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -7200 -1120 ) ( 7200 1120 )
+ + PLACED ( 6002400 1267280 ) N ;
+ - io_in[4] + NET io_in[4] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -7200 -1120 ) ( 7200 1120 )
+ + PLACED ( 6002400 1667120 ) N ;
+ - io_in[5] + NET io_in[5] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -7200 -1120 ) ( 7200 1120 )
+ + PLACED ( 6002400 2066960 ) N ;
+ - io_in[6] + NET io_in[6] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -7200 -1120 ) ( 7200 1120 )
+ + PLACED ( 6002400 2466800 ) N ;
+ - io_in[7] + NET io_in[7] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -7200 -1120 ) ( 7200 1120 )
+ + PLACED ( 6002400 2866640 ) N ;
+ - io_in[8] + NET io_in[8] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -7200 -1120 ) ( 7200 1120 )
+ + PLACED ( 6002400 3266480 ) N ;
+ - io_in[9] + NET io_in[9] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -7200 -1120 ) ( 7200 1120 )
+ + PLACED ( 6002400 3666320 ) N ;
+ - io_oeb[0] + NET net205 + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -7200 -1120 ) ( 7200 1120 )
+ + PLACED ( 6002400 334320 ) N ;
+ - io_oeb[10] + NET net77 + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -7200 -1120 ) ( 7200 1120 )
+ + PLACED ( 6002400 4332720 ) N ;
+ - io_oeb[11] + NET net78 + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -7200 -1120 ) ( 7200 1120 )
+ + PLACED ( 6002400 4732560 ) N ;
+ - io_oeb[12] + NET net79 + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -7200 -1120 ) ( 7200 1120 )
+ + PLACED ( 6002400 5132400 ) N ;
+ - io_oeb[13] + NET net80 + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -7200 -1120 ) ( 7200 1120 )
+ + PLACED ( 6002400 5532240 ) N ;
+ - io_oeb[14] + NET net81 + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -7200 -1120 ) ( 7200 1120 )
+ + PLACED ( 6002400 5932080 ) N ;
+ - io_oeb[15] + NET net82 + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 5439280 6002400 ) N ;
+ - io_oeb[16] + NET net83 + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 4774000 6002400 ) N ;
+ - io_oeb[17] + NET net84 + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 4108720 6002400 ) N ;
+ - io_oeb[18] + NET net85 + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 3443440 6002400 ) N ;
+ - io_oeb[19] + NET net86 + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 2778160 6002400 ) N ;
+ - io_oeb[1] + NET net206 + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -7200 -1120 ) ( 7200 1120 )
+ + PLACED ( 6002400 734160 ) N ;
+ - io_oeb[20] + NET net87 + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 2112880 6002400 ) N ;
+ - io_oeb[21] + NET net88 + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 1447600 6002400 ) N ;
+ - io_oeb[22] + NET net89 + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 782320 6002400 ) N ;
+ - io_oeb[23] + NET net90 + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 117040 6002400 ) N ;
+ - io_oeb[24] + NET net91 + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -7200 -1120 ) ( 7200 1120 )
+ + PLACED ( -2400 5630800 ) N ;
+ - io_oeb[25] + NET net92 + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -7200 -1120 ) ( 7200 1120 )
+ + PLACED ( -2400 5204080 ) N ;
+ - io_oeb[26] + NET net93 + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -7200 -1120 ) ( 7200 1120 )
+ + PLACED ( -2400 4777360 ) N ;
+ - io_oeb[27] + NET net94 + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -7200 -1120 ) ( 7200 1120 )
+ + PLACED ( -2400 4350640 ) N ;
+ - io_oeb[28] + NET net95 + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -7200 -1120 ) ( 7200 1120 )
+ + PLACED ( -2400 3923920 ) N ;
+ - io_oeb[29] + NET net96 + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -7200 -1120 ) ( 7200 1120 )
+ + PLACED ( -2400 3497200 ) N ;
+ - io_oeb[2] + NET net207 + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -7200 -1120 ) ( 7200 1120 )
+ + PLACED ( 6002400 1134000 ) N ;
+ - io_oeb[30] + NET net97 + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -7200 -1120 ) ( 7200 1120 )
+ + PLACED ( -2400 3070480 ) N ;
+ - io_oeb[31] + NET net98 + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -7200 -1120 ) ( 7200 1120 )
+ + PLACED ( -2400 2643760 ) N ;
+ - io_oeb[32] + NET net99 + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -7200 -1120 ) ( 7200 1120 )
+ + PLACED ( -2400 2217040 ) N ;
+ - io_oeb[33] + NET net100 + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -7200 -1120 ) ( 7200 1120 )
+ + PLACED ( -2400 1790320 ) N ;
+ - io_oeb[34] + NET net101 + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -7200 -1120 ) ( 7200 1120 )
+ + PLACED ( -2400 1363600 ) N ;
+ - io_oeb[35] + NET net102 + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -7200 -1120 ) ( 7200 1120 )
+ + PLACED ( -2400 936880 ) N ;
+ - io_oeb[36] + NET net103 + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -7200 -1120 ) ( 7200 1120 )
+ + PLACED ( -2400 510160 ) N ;
+ - io_oeb[37] + NET net104 + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -7200 -1120 ) ( 7200 1120 )
+ + PLACED ( -2400 83440 ) N ;
+ - io_oeb[3] + NET net208 + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -7200 -1120 ) ( 7200 1120 )
+ + PLACED ( 6002400 1533840 ) N ;
+ - io_oeb[4] + NET net209 + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -7200 -1120 ) ( 7200 1120 )
+ + PLACED ( 6002400 1933680 ) N ;
+ - io_oeb[5] + NET net210 + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -7200 -1120 ) ( 7200 1120 )
+ + PLACED ( 6002400 2333520 ) N ;
+ - io_oeb[6] + NET net211 + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -7200 -1120 ) ( 7200 1120 )
+ + PLACED ( 6002400 2733360 ) N ;
+ - io_oeb[7] + NET net212 + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -7200 -1120 ) ( 7200 1120 )
+ + PLACED ( 6002400 3133200 ) N ;
+ - io_oeb[8] + NET net213 + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -7200 -1120 ) ( 7200 1120 )
+ + PLACED ( 6002400 3533040 ) N ;
+ - io_oeb[9] + NET net214 + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -7200 -1120 ) ( 7200 1120 )
+ + PLACED ( 6002400 3932880 ) N ;
+ - io_out[0] + NET io_out[0] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -7200 -1120 ) ( 7200 1120 )
+ + PLACED ( 6002400 201040 ) N ;
+ - io_out[10] + NET io_out[10] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -7200 -1120 ) ( 7200 1120 )
+ + PLACED ( 6002400 4199440 ) N ;
+ - io_out[11] + NET io_out[11] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -7200 -1120 ) ( 7200 1120 )
+ + PLACED ( 6002400 4599280 ) N ;
+ - io_out[12] + NET io_out[12] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -7200 -1120 ) ( 7200 1120 )
+ + PLACED ( 6002400 4999120 ) N ;
+ - io_out[13] + NET io_out[13] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -7200 -1120 ) ( 7200 1120 )
+ + PLACED ( 6002400 5398960 ) N ;
+ - io_out[14] + NET io_out[14] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -7200 -1120 ) ( 7200 1120 )
+ + PLACED ( 6002400 5798800 ) N ;
+ - io_out[15] + NET io_out[15] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 5661040 6002400 ) N ;
+ - io_out[16] + NET io_out[16] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 4995760 6002400 ) N ;
+ - io_out[17] + NET io_out[17] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 4330480 6002400 ) N ;
+ - io_out[18] + NET io_out[18] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 3665200 6002400 ) N ;
+ - io_out[19] + NET io_out[19] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 2999920 6002400 ) N ;
+ - io_out[1] + NET io_out[1] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -7200 -1120 ) ( 7200 1120 )
+ + PLACED ( 6002400 600880 ) N ;
+ - io_out[20] + NET io_out[20] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 2334640 6002400 ) N ;
+ - io_out[21] + NET io_out[21] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 1669360 6002400 ) N ;
+ - io_out[22] + NET io_out[22] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 1004080 6002400 ) N ;
+ - io_out[23] + NET io_out[23] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 338800 6002400 ) N ;
+ - io_out[24] + NET io_out[24] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -7200 -1120 ) ( 7200 1120 )
+ + PLACED ( -2400 5773040 ) N ;
+ - io_out[25] + NET io_out[25] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -7200 -1120 ) ( 7200 1120 )
+ + PLACED ( -2400 5346320 ) N ;
+ - io_out[26] + NET io_out[26] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -7200 -1120 ) ( 7200 1120 )
+ + PLACED ( -2400 4919600 ) N ;
+ - io_out[27] + NET io_out[27] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -7200 -1120 ) ( 7200 1120 )
+ + PLACED ( -2400 4492880 ) N ;
+ - io_out[28] + NET io_out[28] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -7200 -1120 ) ( 7200 1120 )
+ + PLACED ( -2400 4066160 ) N ;
+ - io_out[29] + NET io_out[29] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -7200 -1120 ) ( 7200 1120 )
+ + PLACED ( -2400 3639440 ) N ;
+ - io_out[2] + NET io_out[2] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -7200 -1120 ) ( 7200 1120 )
+ + PLACED ( 6002400 1000720 ) N ;
+ - io_out[30] + NET io_out[30] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -7200 -1120 ) ( 7200 1120 )
+ + PLACED ( -2400 3212720 ) N ;
+ - io_out[31] + NET io_out[31] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -7200 -1120 ) ( 7200 1120 )
+ + PLACED ( -2400 2786000 ) N ;
+ - io_out[32] + NET io_out[32] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -7200 -1120 ) ( 7200 1120 )
+ + PLACED ( -2400 2359280 ) N ;
+ - io_out[33] + NET io_out[33] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -7200 -1120 ) ( 7200 1120 )
+ + PLACED ( -2400 1932560 ) N ;
+ - io_out[34] + NET io_out[34] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -7200 -1120 ) ( 7200 1120 )
+ + PLACED ( -2400 1505840 ) N ;
+ - io_out[35] + NET io_out[35] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -7200 -1120 ) ( 7200 1120 )
+ + PLACED ( -2400 1079120 ) N ;
+ - io_out[36] + NET io_out[36] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -7200 -1120 ) ( 7200 1120 )
+ + PLACED ( -2400 652400 ) N ;
+ - io_out[37] + NET io_out[37] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -7200 -1120 ) ( 7200 1120 )
+ + PLACED ( -2400 225680 ) N ;
+ - io_out[3] + NET io_out[3] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -7200 -1120 ) ( 7200 1120 )
+ + PLACED ( 6002400 1400560 ) N ;
+ - io_out[4] + NET io_out[4] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -7200 -1120 ) ( 7200 1120 )
+ + PLACED ( 6002400 1800400 ) N ;
+ - io_out[5] + NET io_out[5] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -7200 -1120 ) ( 7200 1120 )
+ + PLACED ( 6002400 2200240 ) N ;
+ - io_out[6] + NET io_out[6] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -7200 -1120 ) ( 7200 1120 )
+ + PLACED ( 6002400 2600080 ) N ;
+ - io_out[7] + NET io_out[7] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -7200 -1120 ) ( 7200 1120 )
+ + PLACED ( 6002400 2999920 ) N ;
+ - io_out[8] + NET io_out[8] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -7200 -1120 ) ( 7200 1120 )
+ + PLACED ( 6002400 3399760 ) N ;
+ - io_out[9] + NET io_out[9] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -7200 -1120 ) ( 7200 1120 )
+ + PLACED ( 6002400 3799600 ) N ;
+ - la_data_in[0] + NET la_data_in[0] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 2152080 -2400 ) N ;
+ - la_data_in[10] + NET la_data_in[10] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 2723280 -2400 ) N ;
+ - la_data_in[11] + NET la_data_in[11] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 2780400 -2400 ) N ;
+ - la_data_in[12] + NET la_data_in[12] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 2837520 -2400 ) N ;
+ - la_data_in[13] + NET la_data_in[13] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 2894640 -2400 ) N ;
+ - la_data_in[14] + NET la_data_in[14] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 2951760 -2400 ) N ;
+ - la_data_in[15] + NET la_data_in[15] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 3008880 -2400 ) N ;
+ - la_data_in[16] + NET la_data_in[16] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 3066000 -2400 ) N ;
+ - la_data_in[17] + NET la_data_in[17] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 3123120 -2400 ) N ;
+ - la_data_in[18] + NET la_data_in[18] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 3180240 -2400 ) N ;
+ - la_data_in[19] + NET la_data_in[19] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 3237360 -2400 ) N ;
+ - la_data_in[1] + NET la_data_in[1] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 2209200 -2400 ) N ;
+ - la_data_in[20] + NET la_data_in[20] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 3294480 -2400 ) N ;
+ - la_data_in[21] + NET la_data_in[21] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 3351600 -2400 ) N ;
+ - la_data_in[22] + NET la_data_in[22] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 3408720 -2400 ) N ;
+ - la_data_in[23] + NET la_data_in[23] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 3465840 -2400 ) N ;
+ - la_data_in[24] + NET la_data_in[24] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 3522960 -2400 ) N ;
+ - la_data_in[25] + NET la_data_in[25] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 3580080 -2400 ) N ;
+ - la_data_in[26] + NET la_data_in[26] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 3637200 -2400 ) N ;
+ - la_data_in[27] + NET la_data_in[27] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 3694320 -2400 ) N ;
+ - la_data_in[28] + NET la_data_in[28] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 3751440 -2400 ) N ;
+ - la_data_in[29] + NET la_data_in[29] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 3808560 -2400 ) N ;
+ - la_data_in[2] + NET la_data_in[2] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 2266320 -2400 ) N ;
+ - la_data_in[30] + NET la_data_in[30] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 3865680 -2400 ) N ;
+ - la_data_in[31] + NET la_data_in[31] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 3922800 -2400 ) N ;
+ - la_data_in[32] + NET la_data_in[32] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 3979920 -2400 ) N ;
+ - la_data_in[33] + NET la_data_in[33] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 4037040 -2400 ) N ;
+ - la_data_in[34] + NET la_data_in[34] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 4094160 -2400 ) N ;
+ - la_data_in[35] + NET la_data_in[35] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 4151280 -2400 ) N ;
+ - la_data_in[36] + NET la_data_in[36] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 4208400 -2400 ) N ;
+ - la_data_in[37] + NET la_data_in[37] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 4265520 -2400 ) N ;
+ - la_data_in[38] + NET la_data_in[38] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 4322640 -2400 ) N ;
+ - la_data_in[39] + NET la_data_in[39] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 4379760 -2400 ) N ;
+ - la_data_in[3] + NET la_data_in[3] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 2323440 -2400 ) N ;
+ - la_data_in[40] + NET la_data_in[40] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 4436880 -2400 ) N ;
+ - la_data_in[41] + NET la_data_in[41] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 4494000 -2400 ) N ;
+ - la_data_in[42] + NET la_data_in[42] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 4551120 -2400 ) N ;
+ - la_data_in[43] + NET la_data_in[43] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 4608240 -2400 ) N ;
+ - la_data_in[44] + NET la_data_in[44] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 4665360 -2400 ) N ;
+ - la_data_in[45] + NET la_data_in[45] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 4722480 -2400 ) N ;
+ - la_data_in[46] + NET la_data_in[46] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 4779600 -2400 ) N ;
+ - la_data_in[47] + NET la_data_in[47] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 4836720 -2400 ) N ;
+ - la_data_in[48] + NET la_data_in[48] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 4893840 -2400 ) N ;
+ - la_data_in[49] + NET la_data_in[49] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 4950960 -2400 ) N ;
+ - la_data_in[4] + NET la_data_in[4] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 2380560 -2400 ) N ;
+ - la_data_in[50] + NET la_data_in[50] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 5008080 -2400 ) N ;
+ - la_data_in[51] + NET la_data_in[51] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 5065200 -2400 ) N ;
+ - la_data_in[52] + NET la_data_in[52] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 5122320 -2400 ) N ;
+ - la_data_in[53] + NET la_data_in[53] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 5179440 -2400 ) N ;
+ - la_data_in[54] + NET la_data_in[54] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 5236560 -2400 ) N ;
+ - la_data_in[55] + NET la_data_in[55] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 5293680 -2400 ) N ;
+ - la_data_in[56] + NET la_data_in[56] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 5350800 -2400 ) N ;
+ - la_data_in[57] + NET la_data_in[57] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 5407920 -2400 ) N ;
+ - la_data_in[58] + NET la_data_in[58] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 5465040 -2400 ) N ;
+ - la_data_in[59] + NET la_data_in[59] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 5522160 -2400 ) N ;
+ - la_data_in[5] + NET la_data_in[5] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 2437680 -2400 ) N ;
+ - la_data_in[60] + NET la_data_in[60] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 5579280 -2400 ) N ;
+ - la_data_in[61] + NET la_data_in[61] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 5636400 -2400 ) N ;
+ - la_data_in[62] + NET la_data_in[62] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 5693520 -2400 ) N ;
+ - la_data_in[63] + NET la_data_in[63] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 5750640 -2400 ) N ;
+ - la_data_in[6] + NET la_data_in[6] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 2494800 -2400 ) N ;
+ - la_data_in[7] + NET la_data_in[7] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 2551920 -2400 ) N ;
+ - la_data_in[8] + NET la_data_in[8] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 2609040 -2400 ) N ;
+ - la_data_in[9] + NET la_data_in[9] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 2666160 -2400 ) N ;
+ - la_data_out[0] + NET net105 + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 2171120 -2400 ) N ;
+ - la_data_out[10] + NET net115 + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 2742320 -2400 ) N ;
+ - la_data_out[11] + NET net116 + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 2799440 -2400 ) N ;
+ - la_data_out[12] + NET net117 + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 2856560 -2400 ) N ;
+ - la_data_out[13] + NET net118 + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 2913680 -2400 ) N ;
+ - la_data_out[14] + NET net119 + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 2970800 -2400 ) N ;
+ - la_data_out[15] + NET net120 + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 3027920 -2400 ) N ;
+ - la_data_out[16] + NET net121 + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 3085040 -2400 ) N ;
+ - la_data_out[17] + NET net122 + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 3142160 -2400 ) N ;
+ - la_data_out[18] + NET net123 + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 3199280 -2400 ) N ;
+ - la_data_out[19] + NET net124 + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 3256400 -2400 ) N ;
+ - la_data_out[1] + NET net106 + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 2228240 -2400 ) N ;
+ - la_data_out[20] + NET net125 + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 3313520 -2400 ) N ;
+ - la_data_out[21] + NET net126 + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 3370640 -2400 ) N ;
+ - la_data_out[22] + NET net127 + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 3427760 -2400 ) N ;
+ - la_data_out[23] + NET net128 + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 3484880 -2400 ) N ;
+ - la_data_out[24] + NET net129 + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 3542000 -2400 ) N ;
+ - la_data_out[25] + NET net130 + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 3599120 -2400 ) N ;
+ - la_data_out[26] + NET net131 + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 3656240 -2400 ) N ;
+ - la_data_out[27] + NET net132 + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 3713360 -2400 ) N ;
+ - la_data_out[28] + NET net133 + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 3770480 -2400 ) N ;
+ - la_data_out[29] + NET net134 + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 3827600 -2400 ) N ;
+ - la_data_out[2] + NET net107 + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 2285360 -2400 ) N ;
+ - la_data_out[30] + NET net135 + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 3884720 -2400 ) N ;
+ - la_data_out[31] + NET net136 + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 3941840 -2400 ) N ;
+ - la_data_out[32] + NET net137 + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 3998960 -2400 ) N ;
+ - la_data_out[33] + NET net138 + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 4056080 -2400 ) N ;
+ - la_data_out[34] + NET net139 + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 4113200 -2400 ) N ;
+ - la_data_out[35] + NET net140 + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 4170320 -2400 ) N ;
+ - la_data_out[36] + NET net141 + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 4227440 -2400 ) N ;
+ - la_data_out[37] + NET net142 + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 4284560 -2400 ) N ;
+ - la_data_out[38] + NET net143 + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 4341680 -2400 ) N ;
+ - la_data_out[39] + NET net144 + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 4398800 -2400 ) N ;
+ - la_data_out[3] + NET net108 + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 2342480 -2400 ) N ;
+ - la_data_out[40] + NET net145 + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 4455920 -2400 ) N ;
+ - la_data_out[41] + NET net146 + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 4513040 -2400 ) N ;
+ - la_data_out[42] + NET net147 + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 4570160 -2400 ) N ;
+ - la_data_out[43] + NET net148 + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 4627280 -2400 ) N ;
+ - la_data_out[44] + NET net149 + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 4684400 -2400 ) N ;
+ - la_data_out[45] + NET net150 + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 4741520 -2400 ) N ;
+ - la_data_out[46] + NET net151 + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 4798640 -2400 ) N ;
+ - la_data_out[47] + NET net152 + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 4855760 -2400 ) N ;
+ - la_data_out[48] + NET net153 + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 4912880 -2400 ) N ;
+ - la_data_out[49] + NET net154 + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 4970000 -2400 ) N ;
+ - la_data_out[4] + NET net109 + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 2399600 -2400 ) N ;
+ - la_data_out[50] + NET net155 + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 5027120 -2400 ) N ;
+ - la_data_out[51] + NET net156 + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 5084240 -2400 ) N ;
+ - la_data_out[52] + NET net157 + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 5141360 -2400 ) N ;
+ - la_data_out[53] + NET net158 + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 5198480 -2400 ) N ;
+ - la_data_out[54] + NET net159 + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 5255600 -2400 ) N ;
+ - la_data_out[55] + NET net160 + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 5312720 -2400 ) N ;
+ - la_data_out[56] + NET net161 + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 5369840 -2400 ) N ;
+ - la_data_out[57] + NET net162 + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 5426960 -2400 ) N ;
+ - la_data_out[58] + NET net163 + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 5484080 -2400 ) N ;
+ - la_data_out[59] + NET net164 + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 5541200 -2400 ) N ;
+ - la_data_out[5] + NET net110 + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 2456720 -2400 ) N ;
+ - la_data_out[60] + NET net165 + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 5598320 -2400 ) N ;
+ - la_data_out[61] + NET net166 + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 5655440 -2400 ) N ;
+ - la_data_out[62] + NET net167 + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 5712560 -2400 ) N ;
+ - la_data_out[63] + NET net168 + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 5769680 -2400 ) N ;
+ - la_data_out[6] + NET net111 + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 2513840 -2400 ) N ;
+ - la_data_out[7] + NET net112 + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 2570960 -2400 ) N ;
+ - la_data_out[8] + NET net113 + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 2628080 -2400 ) N ;
+ - la_data_out[9] + NET net114 + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 2685200 -2400 ) N ;
+ - la_oenb[0] + NET la_oenb[0] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 2190160 -2400 ) N ;
+ - la_oenb[10] + NET la_oenb[10] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 2761360 -2400 ) N ;
+ - la_oenb[11] + NET la_oenb[11] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 2818480 -2400 ) N ;
+ - la_oenb[12] + NET la_oenb[12] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 2875600 -2400 ) N ;
+ - la_oenb[13] + NET la_oenb[13] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 2932720 -2400 ) N ;
+ - la_oenb[14] + NET la_oenb[14] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 2989840 -2400 ) N ;
+ - la_oenb[15] + NET la_oenb[15] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 3046960 -2400 ) N ;
+ - la_oenb[16] + NET la_oenb[16] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 3104080 -2400 ) N ;
+ - la_oenb[17] + NET la_oenb[17] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 3161200 -2400 ) N ;
+ - la_oenb[18] + NET la_oenb[18] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 3218320 -2400 ) N ;
+ - la_oenb[19] + NET la_oenb[19] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 3275440 -2400 ) N ;
+ - la_oenb[1] + NET la_oenb[1] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 2247280 -2400 ) N ;
+ - la_oenb[20] + NET la_oenb[20] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 3332560 -2400 ) N ;
+ - la_oenb[21] + NET la_oenb[21] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 3389680 -2400 ) N ;
+ - la_oenb[22] + NET la_oenb[22] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 3446800 -2400 ) N ;
+ - la_oenb[23] + NET la_oenb[23] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 3503920 -2400 ) N ;
+ - la_oenb[24] + NET la_oenb[24] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 3561040 -2400 ) N ;
+ - la_oenb[25] + NET la_oenb[25] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 3618160 -2400 ) N ;
+ - la_oenb[26] + NET la_oenb[26] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 3675280 -2400 ) N ;
+ - la_oenb[27] + NET la_oenb[27] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 3732400 -2400 ) N ;
+ - la_oenb[28] + NET la_oenb[28] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 3789520 -2400 ) N ;
+ - la_oenb[29] + NET la_oenb[29] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 3846640 -2400 ) N ;
+ - la_oenb[2] + NET la_oenb[2] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 2304400 -2400 ) N ;
+ - la_oenb[30] + NET la_oenb[30] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 3903760 -2400 ) N ;
+ - la_oenb[31] + NET la_oenb[31] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 3960880 -2400 ) N ;
+ - la_oenb[32] + NET la_oenb[32] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 4018000 -2400 ) N ;
+ - la_oenb[33] + NET la_oenb[33] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 4075120 -2400 ) N ;
+ - la_oenb[34] + NET la_oenb[34] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 4132240 -2400 ) N ;
+ - la_oenb[35] + NET la_oenb[35] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 4189360 -2400 ) N ;
+ - la_oenb[36] + NET la_oenb[36] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 4246480 -2400 ) N ;
+ - la_oenb[37] + NET la_oenb[37] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 4303600 -2400 ) N ;
+ - la_oenb[38] + NET la_oenb[38] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 4360720 -2400 ) N ;
+ - la_oenb[39] + NET la_oenb[39] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 4417840 -2400 ) N ;
+ - la_oenb[3] + NET la_oenb[3] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 2361520 -2400 ) N ;
+ - la_oenb[40] + NET la_oenb[40] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 4474960 -2400 ) N ;
+ - la_oenb[41] + NET la_oenb[41] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 4532080 -2400 ) N ;
+ - la_oenb[42] + NET la_oenb[42] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 4589200 -2400 ) N ;
+ - la_oenb[43] + NET la_oenb[43] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 4646320 -2400 ) N ;
+ - la_oenb[44] + NET la_oenb[44] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 4703440 -2400 ) N ;
+ - la_oenb[45] + NET la_oenb[45] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 4760560 -2400 ) N ;
+ - la_oenb[46] + NET la_oenb[46] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 4817680 -2400 ) N ;
+ - la_oenb[47] + NET la_oenb[47] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 4874800 -2400 ) N ;
+ - la_oenb[48] + NET la_oenb[48] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 4931920 -2400 ) N ;
+ - la_oenb[49] + NET la_oenb[49] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 4989040 -2400 ) N ;
+ - la_oenb[4] + NET la_oenb[4] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 2418640 -2400 ) N ;
+ - la_oenb[50] + NET la_oenb[50] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 5046160 -2400 ) N ;
+ - la_oenb[51] + NET la_oenb[51] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 5103280 -2400 ) N ;
+ - la_oenb[52] + NET la_oenb[52] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 5160400 -2400 ) N ;
+ - la_oenb[53] + NET la_oenb[53] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 5217520 -2400 ) N ;
+ - la_oenb[54] + NET la_oenb[54] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 5274640 -2400 ) N ;
+ - la_oenb[55] + NET la_oenb[55] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 5331760 -2400 ) N ;
+ - la_oenb[56] + NET la_oenb[56] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 5388880 -2400 ) N ;
+ - la_oenb[57] + NET la_oenb[57] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 5446000 -2400 ) N ;
+ - la_oenb[58] + NET la_oenb[58] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 5503120 -2400 ) N ;
+ - la_oenb[59] + NET la_oenb[59] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 5560240 -2400 ) N ;
+ - la_oenb[5] + NET la_oenb[5] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 2475760 -2400 ) N ;
+ - la_oenb[60] + NET la_oenb[60] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 5617360 -2400 ) N ;
+ - la_oenb[61] + NET la_oenb[61] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 5674480 -2400 ) N ;
+ - la_oenb[62] + NET la_oenb[62] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 5731600 -2400 ) N ;
+ - la_oenb[63] + NET la_oenb[63] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 5788720 -2400 ) N ;
+ - la_oenb[6] + NET la_oenb[6] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 2532880 -2400 ) N ;
+ - la_oenb[7] + NET la_oenb[7] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 2590000 -2400 ) N ;
+ - la_oenb[8] + NET la_oenb[8] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 2647120 -2400 ) N ;
+ - la_oenb[9] + NET la_oenb[9] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 2704240 -2400 ) N ;
+ - user_clock2 + NET user_clock2 + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 5807760 -2400 ) N ;
+ - user_irq[0] + NET net169 + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 5826800 -2400 ) N ;
+ - user_irq[1] + NET net170 + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 5845840 -2400 ) N ;
+ - user_irq[2] + NET net171 + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 5864880 -2400 ) N ;
+ - vdd + NET vdd + SPECIAL + DIRECTION INOUT + USE POWER
+ + PORT
+ + LAYER Metal5 ( -3000040 -3100 ) ( 3000040 3100 )
+ + LAYER Metal5 ( -3000040 -183100 ) ( 3000040 -176900 )
+ + LAYER Metal5 ( -3000040 -363100 ) ( 3000040 -356900 )
+ + LAYER Metal5 ( -3000040 -543100 ) ( 3000040 -536900 )
+ + LAYER Metal5 ( -3000040 -723100 ) ( 3000040 -716900 )
+ + LAYER Metal5 ( -3000040 -903100 ) ( 3000040 -896900 )
+ + LAYER Metal5 ( -3000040 -1083100 ) ( 3000040 -1076900 )
+ + LAYER Metal5 ( -3000040 -1263100 ) ( 3000040 -1256900 )
+ + LAYER Metal5 ( -3000040 -1443100 ) ( 3000040 -1436900 )
+ + LAYER Metal5 ( -3000040 -1623100 ) ( 3000040 -1616900 )
+ + LAYER Metal5 ( -3000040 -1803100 ) ( 3000040 -1796900 )
+ + LAYER Metal5 ( -3000040 -1983100 ) ( 3000040 -1976900 )
+ + LAYER Metal5 ( -3000040 -2163100 ) ( 3000040 -2156900 )
+ + LAYER Metal5 ( -3000040 -2343100 ) ( 3000040 -2336900 )
+ + LAYER Metal5 ( -3000040 -2523100 ) ( 3000040 -2516900 )
+ + LAYER Metal5 ( -3000040 -2703100 ) ( 3000040 -2696900 )
+ + LAYER Metal5 ( -3000040 -2883100 ) ( 3000040 -2876900 )
+ + LAYER Metal5 ( -3000040 -3063100 ) ( 3000040 -3056900 )
+ + LAYER Metal5 ( -3000040 -3243100 ) ( 3000040 -3236900 )
+ + LAYER Metal5 ( -3000040 -3423100 ) ( 3000040 -3416900 )
+ + LAYER Metal5 ( -3000040 -3603100 ) ( 3000040 -3596900 )
+ + LAYER Metal5 ( -3000040 -3783100 ) ( 3000040 -3776900 )
+ + LAYER Metal5 ( -3000040 -3963100 ) ( 3000040 -3956900 )
+ + LAYER Metal5 ( -3000040 -4143100 ) ( 3000040 -4136900 )
+ + LAYER Metal5 ( -3000040 -4323100 ) ( 3000040 -4316900 )
+ + LAYER Metal5 ( -3000040 -4503100 ) ( 3000040 -4496900 )
+ + LAYER Metal5 ( -3000040 -4683100 ) ( 3000040 -4676900 )
+ + LAYER Metal5 ( -3000040 -4863100 ) ( 3000040 -4856900 )
+ + LAYER Metal5 ( -3000040 -5043100 ) ( 3000040 -5036900 )
+ + LAYER Metal5 ( -3000040 -5223100 ) ( 3000040 -5216900 )
+ + LAYER Metal5 ( -3000040 -5403100 ) ( 3000040 -5396900 )
+ + LAYER Metal5 ( -3000040 -5583100 ) ( 3000040 -5576900 )
+ + LAYER Metal5 ( -3000040 -5763100 ) ( 3000040 -5756900 )
+ + LAYER Metal4 ( 2810660 -5813800 ) ( 2816860 177320 )
+ + LAYER Metal4 ( 2630660 -5813800 ) ( 2636860 177320 )
+ + LAYER Metal4 ( 2450660 -5813800 ) ( 2456860 177320 )
+ + LAYER Metal4 ( 2270660 -5813800 ) ( 2276860 177320 )
+ + LAYER Metal4 ( 2090660 -5813800 ) ( 2096860 177320 )
+ + LAYER Metal4 ( 1910660 -5813800 ) ( 1916860 177320 )
+ + LAYER Metal4 ( 1730660 -5813800 ) ( 1736860 177320 )
+ + LAYER Metal4 ( 1550660 -5813800 ) ( 1556860 177320 )
+ + LAYER Metal4 ( 1370660 -5813800 ) ( 1376860 177320 )
+ + LAYER Metal4 ( 1190660 -5813800 ) ( 1196860 177320 )
+ + LAYER Metal4 ( 1010660 -5813800 ) ( 1016860 177320 )
+ + LAYER Metal4 ( 830660 -5813800 ) ( 836860 177320 )
+ + LAYER Metal4 ( 650660 -5813800 ) ( 656860 177320 )
+ + LAYER Metal4 ( 470660 -5813800 ) ( 476860 177320 )
+ + LAYER Metal4 ( 290660 -5813800 ) ( 296860 177320 )
+ + LAYER Metal4 ( 110660 -5813800 ) ( 116860 177320 )
+ + LAYER Metal4 ( -69340 -5813800 ) ( -63140 177320 )
+ + LAYER Metal4 ( -249340 -5813800 ) ( -243140 177320 )
+ + LAYER Metal4 ( -429340 -5813800 ) ( -423140 177320 )
+ + LAYER Metal4 ( -609340 -5813800 ) ( -603140 177320 )
+ + LAYER Metal4 ( -789340 -5813800 ) ( -783140 177320 )
+ + LAYER Metal4 ( -969340 -5813800 ) ( -963140 177320 )
+ + LAYER Metal4 ( -1149340 -5813800 ) ( -1143140 177320 )
+ + LAYER Metal4 ( -1329340 -5813800 ) ( -1323140 177320 )
+ + LAYER Metal4 ( -1509340 -5813800 ) ( -1503140 177320 )
+ + LAYER Metal4 ( -1689340 -5813800 ) ( -1683140 177320 )
+ + LAYER Metal4 ( -1869340 -5813800 ) ( -1863140 177320 )
+ + LAYER Metal4 ( -2049340 -5813800 ) ( -2043140 177320 )
+ + LAYER Metal4 ( -2229340 -5813800 ) ( -2223140 177320 )
+ + LAYER Metal4 ( -2409340 -5813800 ) ( -2403140 177320 )
+ + LAYER Metal4 ( -2589340 -5813800 ) ( -2583140 177320 )
+ + LAYER Metal4 ( -2769340 -5813800 ) ( -2763140 177320 )
+ + LAYER Metal4 ( -2949340 -5813800 ) ( -2943140 177320 )
+ + LAYER Metal4 ( 2984240 -5804200 ) ( 2990440 167720 )
+ + LAYER Metal5 ( -2990440 161520 ) ( 2990440 167720 )
+ + LAYER Metal5 ( -2990440 -5804200 ) ( 2990440 -5798000 )
+ + LAYER Metal4 ( -2990440 -5804200 ) ( -2984240 167720 )
+ + FIXED ( 2999920 5817040 ) N ;
+ - vss + NET vss + SPECIAL + DIRECTION INOUT + USE GROUND
+ + PORT
+ + LAYER Metal5 ( -3000040 -3100 ) ( 3000040 3100 )
+ + LAYER Metal5 ( -3000040 -183100 ) ( 3000040 -176900 )
+ + LAYER Metal5 ( -3000040 -363100 ) ( 3000040 -356900 )
+ + LAYER Metal5 ( -3000040 -543100 ) ( 3000040 -536900 )
+ + LAYER Metal5 ( -3000040 -723100 ) ( 3000040 -716900 )
+ + LAYER Metal5 ( -3000040 -903100 ) ( 3000040 -896900 )
+ + LAYER Metal5 ( -3000040 -1083100 ) ( 3000040 -1076900 )
+ + LAYER Metal5 ( -3000040 -1263100 ) ( 3000040 -1256900 )
+ + LAYER Metal5 ( -3000040 -1443100 ) ( 3000040 -1436900 )
+ + LAYER Metal5 ( -3000040 -1623100 ) ( 3000040 -1616900 )
+ + LAYER Metal5 ( -3000040 -1803100 ) ( 3000040 -1796900 )
+ + LAYER Metal5 ( -3000040 -1983100 ) ( 3000040 -1976900 )
+ + LAYER Metal5 ( -3000040 -2163100 ) ( 3000040 -2156900 )
+ + LAYER Metal5 ( -3000040 -2343100 ) ( 3000040 -2336900 )
+ + LAYER Metal5 ( -3000040 -2523100 ) ( 3000040 -2516900 )
+ + LAYER Metal5 ( -3000040 -2703100 ) ( 3000040 -2696900 )
+ + LAYER Metal5 ( -3000040 -2883100 ) ( 3000040 -2876900 )
+ + LAYER Metal5 ( -3000040 -3063100 ) ( 3000040 -3056900 )
+ + LAYER Metal5 ( -3000040 -3243100 ) ( 3000040 -3236900 )
+ + LAYER Metal5 ( -3000040 -3423100 ) ( 3000040 -3416900 )
+ + LAYER Metal5 ( -3000040 -3603100 ) ( 3000040 -3596900 )
+ + LAYER Metal5 ( -3000040 -3783100 ) ( 3000040 -3776900 )
+ + LAYER Metal5 ( -3000040 -3963100 ) ( 3000040 -3956900 )
+ + LAYER Metal5 ( -3000040 -4143100 ) ( 3000040 -4136900 )
+ + LAYER Metal5 ( -3000040 -4323100 ) ( 3000040 -4316900 )
+ + LAYER Metal5 ( -3000040 -4503100 ) ( 3000040 -4496900 )
+ + LAYER Metal5 ( -3000040 -4683100 ) ( 3000040 -4676900 )
+ + LAYER Metal5 ( -3000040 -4863100 ) ( 3000040 -4856900 )
+ + LAYER Metal5 ( -3000040 -5043100 ) ( 3000040 -5036900 )
+ + LAYER Metal5 ( -3000040 -5223100 ) ( 3000040 -5216900 )
+ + LAYER Metal5 ( -3000040 -5403100 ) ( 3000040 -5396900 )
+ + LAYER Metal5 ( -3000040 -5583100 ) ( 3000040 -5576900 )
+ + LAYER Metal5 ( -3000040 -5763100 ) ( 3000040 -5756900 )
+ + LAYER Metal4 ( 2847860 -5873800 ) ( 2854060 117320 )
+ + LAYER Metal4 ( 2667860 -5873800 ) ( 2674060 117320 )
+ + LAYER Metal4 ( 2487860 -5873800 ) ( 2494060 117320 )
+ + LAYER Metal4 ( 2307860 -5873800 ) ( 2314060 117320 )
+ + LAYER Metal4 ( 2127860 -5873800 ) ( 2134060 117320 )
+ + LAYER Metal4 ( 1947860 -5873800 ) ( 1954060 117320 )
+ + LAYER Metal4 ( 1767860 -5873800 ) ( 1774060 117320 )
+ + LAYER Metal4 ( 1587860 -5873800 ) ( 1594060 117320 )
+ + LAYER Metal4 ( 1407860 -5873800 ) ( 1414060 117320 )
+ + LAYER Metal4 ( 1227860 -5873800 ) ( 1234060 117320 )
+ + LAYER Metal4 ( 1047860 -5873800 ) ( 1054060 117320 )
+ + LAYER Metal4 ( 867860 -5873800 ) ( 874060 117320 )
+ + LAYER Metal4 ( 687860 -5873800 ) ( 694060 117320 )
+ + LAYER Metal4 ( 507860 -5873800 ) ( 514060 117320 )
+ + LAYER Metal4 ( 327860 -5873800 ) ( 334060 117320 )
+ + LAYER Metal4 ( 147860 -5873800 ) ( 154060 117320 )
+ + LAYER Metal4 ( -32140 -5873800 ) ( -25940 117320 )
+ + LAYER Metal4 ( -212140 -5873800 ) ( -205940 117320 )
+ + LAYER Metal4 ( -392140 -5873800 ) ( -385940 117320 )
+ + LAYER Metal4 ( -572140 -5873800 ) ( -565940 117320 )
+ + LAYER Metal4 ( -752140 -5873800 ) ( -745940 117320 )
+ + LAYER Metal4 ( -932140 -5873800 ) ( -925940 117320 )
+ + LAYER Metal4 ( -1112140 -5873800 ) ( -1105940 117320 )
+ + LAYER Metal4 ( -1292140 -5873800 ) ( -1285940 117320 )
+ + LAYER Metal4 ( -1472140 -5873800 ) ( -1465940 117320 )
+ + LAYER Metal4 ( -1652140 -5873800 ) ( -1645940 117320 )
+ + LAYER Metal4 ( -1832140 -5873800 ) ( -1825940 117320 )
+ + LAYER Metal4 ( -2012140 -5873800 ) ( -2005940 117320 )
+ + LAYER Metal4 ( -2192140 -5873800 ) ( -2185940 117320 )
+ + LAYER Metal4 ( -2372140 -5873800 ) ( -2365940 117320 )
+ + LAYER Metal4 ( -2552140 -5873800 ) ( -2545940 117320 )
+ + LAYER Metal4 ( -2732140 -5873800 ) ( -2725940 117320 )
+ + LAYER Metal4 ( -2912140 -5873800 ) ( -2905940 117320 )
+ + LAYER Metal4 ( 2993840 -5873800 ) ( 3000040 117320 )
+ + LAYER Metal5 ( -3000040 111120 ) ( 3000040 117320 )
+ + LAYER Metal5 ( -3000040 -5873800 ) ( 3000040 -5867600 )
+ + LAYER Metal4 ( -3000040 -5873800 ) ( -2993840 117320 )
+ + FIXED ( 2999920 5877040 ) N ;
+ - wb_clk_i + NET wb_clk_i + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 133840 -2400 ) N ;
+ - wb_rst_i + NET wb_rst_i + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 152880 -2400 ) N ;
+ - wbs_ack_o + NET net172 + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 171920 -2400 ) N ;
+ - wbs_adr_i[0] + NET wbs_adr_i[0] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 248080 -2400 ) N ;
+ - wbs_adr_i[10] + NET wbs_adr_i[10] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 895440 -2400 ) N ;
+ - wbs_adr_i[11] + NET wbs_adr_i[11] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 952560 -2400 ) N ;
+ - wbs_adr_i[12] + NET wbs_adr_i[12] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 1009680 -2400 ) N ;
+ - wbs_adr_i[13] + NET wbs_adr_i[13] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 1066800 -2400 ) N ;
+ - wbs_adr_i[14] + NET wbs_adr_i[14] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 1123920 -2400 ) N ;
+ - wbs_adr_i[15] + NET wbs_adr_i[15] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 1181040 -2400 ) N ;
+ - wbs_adr_i[16] + NET wbs_adr_i[16] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 1238160 -2400 ) N ;
+ - wbs_adr_i[17] + NET wbs_adr_i[17] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 1295280 -2400 ) N ;
+ - wbs_adr_i[18] + NET wbs_adr_i[18] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 1352400 -2400 ) N ;
+ - wbs_adr_i[19] + NET wbs_adr_i[19] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 1409520 -2400 ) N ;
+ - wbs_adr_i[1] + NET wbs_adr_i[1] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 324240 -2400 ) N ;
+ - wbs_adr_i[20] + NET wbs_adr_i[20] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 1466640 -2400 ) N ;
+ - wbs_adr_i[21] + NET wbs_adr_i[21] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 1523760 -2400 ) N ;
+ - wbs_adr_i[22] + NET wbs_adr_i[22] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 1580880 -2400 ) N ;
+ - wbs_adr_i[23] + NET wbs_adr_i[23] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 1638000 -2400 ) N ;
+ - wbs_adr_i[24] + NET wbs_adr_i[24] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 1695120 -2400 ) N ;
+ - wbs_adr_i[25] + NET wbs_adr_i[25] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 1752240 -2400 ) N ;
+ - wbs_adr_i[26] + NET wbs_adr_i[26] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 1809360 -2400 ) N ;
+ - wbs_adr_i[27] + NET wbs_adr_i[27] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 1866480 -2400 ) N ;
+ - wbs_adr_i[28] + NET wbs_adr_i[28] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 1923600 -2400 ) N ;
+ - wbs_adr_i[29] + NET wbs_adr_i[29] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 1980720 -2400 ) N ;
+ - wbs_adr_i[2] + NET wbs_adr_i[2] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 400400 -2400 ) N ;
+ - wbs_adr_i[30] + NET wbs_adr_i[30] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 2037840 -2400 ) N ;
+ - wbs_adr_i[31] + NET wbs_adr_i[31] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 2094960 -2400 ) N ;
+ - wbs_adr_i[3] + NET wbs_adr_i[3] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 476560 -2400 ) N ;
+ - wbs_adr_i[4] + NET wbs_adr_i[4] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 552720 -2400 ) N ;
+ - wbs_adr_i[5] + NET wbs_adr_i[5] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 609840 -2400 ) N ;
+ - wbs_adr_i[6] + NET wbs_adr_i[6] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 666960 -2400 ) N ;
+ - wbs_adr_i[7] + NET wbs_adr_i[7] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 724080 -2400 ) N ;
+ - wbs_adr_i[8] + NET wbs_adr_i[8] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 781200 -2400 ) N ;
+ - wbs_adr_i[9] + NET wbs_adr_i[9] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 838320 -2400 ) N ;
+ - wbs_cyc_i + NET wbs_cyc_i + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 190960 -2400 ) N ;
+ - wbs_dat_i[0] + NET wbs_dat_i[0] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 267120 -2400 ) N ;
+ - wbs_dat_i[10] + NET wbs_dat_i[10] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 914480 -2400 ) N ;
+ - wbs_dat_i[11] + NET wbs_dat_i[11] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 971600 -2400 ) N ;
+ - wbs_dat_i[12] + NET wbs_dat_i[12] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 1028720 -2400 ) N ;
+ - wbs_dat_i[13] + NET wbs_dat_i[13] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 1085840 -2400 ) N ;
+ - wbs_dat_i[14] + NET wbs_dat_i[14] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 1142960 -2400 ) N ;
+ - wbs_dat_i[15] + NET wbs_dat_i[15] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 1200080 -2400 ) N ;
+ - wbs_dat_i[16] + NET wbs_dat_i[16] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 1257200 -2400 ) N ;
+ - wbs_dat_i[17] + NET wbs_dat_i[17] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 1314320 -2400 ) N ;
+ - wbs_dat_i[18] + NET wbs_dat_i[18] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 1371440 -2400 ) N ;
+ - wbs_dat_i[19] + NET wbs_dat_i[19] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 1428560 -2400 ) N ;
+ - wbs_dat_i[1] + NET wbs_dat_i[1] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 343280 -2400 ) N ;
+ - wbs_dat_i[20] + NET wbs_dat_i[20] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 1485680 -2400 ) N ;
+ - wbs_dat_i[21] + NET wbs_dat_i[21] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 1542800 -2400 ) N ;
+ - wbs_dat_i[22] + NET wbs_dat_i[22] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 1599920 -2400 ) N ;
+ - wbs_dat_i[23] + NET wbs_dat_i[23] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 1657040 -2400 ) N ;
+ - wbs_dat_i[24] + NET wbs_dat_i[24] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 1714160 -2400 ) N ;
+ - wbs_dat_i[25] + NET wbs_dat_i[25] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 1771280 -2400 ) N ;
+ - wbs_dat_i[26] + NET wbs_dat_i[26] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 1828400 -2400 ) N ;
+ - wbs_dat_i[27] + NET wbs_dat_i[27] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 1885520 -2400 ) N ;
+ - wbs_dat_i[28] + NET wbs_dat_i[28] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 1942640 -2400 ) N ;
+ - wbs_dat_i[29] + NET wbs_dat_i[29] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 1999760 -2400 ) N ;
+ - wbs_dat_i[2] + NET wbs_dat_i[2] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 419440 -2400 ) N ;
+ - wbs_dat_i[30] + NET wbs_dat_i[30] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 2056880 -2400 ) N ;
+ - wbs_dat_i[31] + NET wbs_dat_i[31] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 2114000 -2400 ) N ;
+ - wbs_dat_i[3] + NET wbs_dat_i[3] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 495600 -2400 ) N ;
+ - wbs_dat_i[4] + NET wbs_dat_i[4] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 571760 -2400 ) N ;
+ - wbs_dat_i[5] + NET wbs_dat_i[5] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 628880 -2400 ) N ;
+ - wbs_dat_i[6] + NET wbs_dat_i[6] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 686000 -2400 ) N ;
+ - wbs_dat_i[7] + NET wbs_dat_i[7] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 743120 -2400 ) N ;
+ - wbs_dat_i[8] + NET wbs_dat_i[8] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 800240 -2400 ) N ;
+ - wbs_dat_i[9] + NET wbs_dat_i[9] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 857360 -2400 ) N ;
+ - wbs_dat_o[0] + NET net173 + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 286160 -2400 ) N ;
+ - wbs_dat_o[10] + NET net183 + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 933520 -2400 ) N ;
+ - wbs_dat_o[11] + NET net184 + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 990640 -2400 ) N ;
+ - wbs_dat_o[12] + NET net185 + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 1047760 -2400 ) N ;
+ - wbs_dat_o[13] + NET net186 + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 1104880 -2400 ) N ;
+ - wbs_dat_o[14] + NET net187 + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 1162000 -2400 ) N ;
+ - wbs_dat_o[15] + NET net188 + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 1219120 -2400 ) N ;
+ - wbs_dat_o[16] + NET net189 + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 1276240 -2400 ) N ;
+ - wbs_dat_o[17] + NET net190 + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 1333360 -2400 ) N ;
+ - wbs_dat_o[18] + NET net191 + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 1390480 -2400 ) N ;
+ - wbs_dat_o[19] + NET net192 + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 1447600 -2400 ) N ;
+ - wbs_dat_o[1] + NET net174 + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 362320 -2400 ) N ;
+ - wbs_dat_o[20] + NET net193 + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 1504720 -2400 ) N ;
+ - wbs_dat_o[21] + NET net194 + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 1561840 -2400 ) N ;
+ - wbs_dat_o[22] + NET net195 + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 1618960 -2400 ) N ;
+ - wbs_dat_o[23] + NET net196 + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 1676080 -2400 ) N ;
+ - wbs_dat_o[24] + NET net197 + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 1733200 -2400 ) N ;
+ - wbs_dat_o[25] + NET net198 + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 1790320 -2400 ) N ;
+ - wbs_dat_o[26] + NET net199 + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 1847440 -2400 ) N ;
+ - wbs_dat_o[27] + NET net200 + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 1904560 -2400 ) N ;
+ - wbs_dat_o[28] + NET net201 + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 1961680 -2400 ) N ;
+ - wbs_dat_o[29] + NET net202 + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 2018800 -2400 ) N ;
+ - wbs_dat_o[2] + NET net175 + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 438480 -2400 ) N ;
+ - wbs_dat_o[30] + NET net203 + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 2075920 -2400 ) N ;
+ - wbs_dat_o[31] + NET net204 + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 2133040 -2400 ) N ;
+ - wbs_dat_o[3] + NET net176 + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 514640 -2400 ) N ;
+ - wbs_dat_o[4] + NET net177 + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 590800 -2400 ) N ;
+ - wbs_dat_o[5] + NET net178 + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 647920 -2400 ) N ;
+ - wbs_dat_o[6] + NET net179 + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 705040 -2400 ) N ;
+ - wbs_dat_o[7] + NET net180 + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 762160 -2400 ) N ;
+ - wbs_dat_o[8] + NET net181 + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 819280 -2400 ) N ;
+ - wbs_dat_o[9] + NET net182 + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 876400 -2400 ) N ;
+ - wbs_sel_i[0] + NET wbs_sel_i[0] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 305200 -2400 ) N ;
+ - wbs_sel_i[1] + NET wbs_sel_i[1] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 381360 -2400 ) N ;
+ - wbs_sel_i[2] + NET wbs_sel_i[2] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 457520 -2400 ) N ;
+ - wbs_sel_i[3] + NET wbs_sel_i[3] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 533680 -2400 ) N ;
+ - wbs_stb_i + NET wbs_stb_i + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 210000 -2400 ) N ;
+ - wbs_we_i + NET wbs_we_i + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 229040 -2400 ) N ;
+END PINS
+SPECIALNETS 2 ;
+ - vdd ( PIN vdd ) ( * VDD ) + USE POWER
+ + ROUTED Metal5 6200 + SHAPE STRIPE ( -120 5817040 ) ( 5999960 5817040 )
+ NEW Metal5 6200 + SHAPE STRIPE ( -120 5637040 ) ( 5999960 5637040 )
+ NEW Metal5 6200 + SHAPE STRIPE ( -120 5457040 ) ( 5999960 5457040 )
+ NEW Metal5 6200 + SHAPE STRIPE ( -120 5277040 ) ( 5999960 5277040 )
+ NEW Metal5 6200 + SHAPE STRIPE ( -120 5097040 ) ( 5999960 5097040 )
+ NEW Metal5 6200 + SHAPE STRIPE ( -120 4917040 ) ( 5999960 4917040 )
+ NEW Metal5 6200 + SHAPE STRIPE ( -120 4737040 ) ( 5999960 4737040 )
+ NEW Metal5 6200 + SHAPE STRIPE ( -120 4557040 ) ( 5999960 4557040 )
+ NEW Metal5 6200 + SHAPE STRIPE ( -120 4377040 ) ( 5999960 4377040 )
+ NEW Metal5 6200 + SHAPE STRIPE ( -120 4197040 ) ( 5999960 4197040 )
+ NEW Metal5 6200 + SHAPE STRIPE ( -120 4017040 ) ( 5999960 4017040 )
+ NEW Metal5 6200 + SHAPE STRIPE ( -120 3837040 ) ( 5999960 3837040 )
+ NEW Metal5 6200 + SHAPE STRIPE ( -120 3657040 ) ( 5999960 3657040 )
+ NEW Metal5 6200 + SHAPE STRIPE ( -120 3477040 ) ( 5999960 3477040 )
+ NEW Metal5 6200 + SHAPE STRIPE ( -120 3297040 ) ( 5999960 3297040 )
+ NEW Metal5 6200 + SHAPE STRIPE ( -120 3117040 ) ( 5999960 3117040 )
+ NEW Metal5 6200 + SHAPE STRIPE ( -120 2937040 ) ( 5999960 2937040 )
+ NEW Metal5 6200 + SHAPE STRIPE ( -120 2757040 ) ( 5999960 2757040 )
+ NEW Metal5 6200 + SHAPE STRIPE ( -120 2577040 ) ( 5999960 2577040 )
+ NEW Metal5 6200 + SHAPE STRIPE ( -120 2397040 ) ( 5999960 2397040 )
+ NEW Metal5 6200 + SHAPE STRIPE ( -120 2217040 ) ( 5999960 2217040 )
+ NEW Metal5 6200 + SHAPE STRIPE ( -120 2037040 ) ( 5999960 2037040 )
+ NEW Metal5 6200 + SHAPE STRIPE ( -120 1857040 ) ( 5999960 1857040 )
+ NEW Metal5 6200 + SHAPE STRIPE ( -120 1677040 ) ( 5999960 1677040 )
+ NEW Metal5 6200 + SHAPE STRIPE ( -120 1497040 ) ( 5999960 1497040 )
+ NEW Metal5 6200 + SHAPE STRIPE ( -120 1317040 ) ( 5999960 1317040 )
+ NEW Metal5 6200 + SHAPE STRIPE ( -120 1137040 ) ( 5999960 1137040 )
+ NEW Metal5 6200 + SHAPE STRIPE ( -120 957040 ) ( 5999960 957040 )
+ NEW Metal5 6200 + SHAPE STRIPE ( -120 777040 ) ( 5999960 777040 )
+ NEW Metal5 6200 + SHAPE STRIPE ( -120 597040 ) ( 5999960 597040 )
+ NEW Metal5 6200 + SHAPE STRIPE ( -120 417040 ) ( 5999960 417040 )
+ NEW Metal5 6200 + SHAPE STRIPE ( -120 237040 ) ( 5999960 237040 )
+ NEW Metal5 6200 + SHAPE STRIPE ( -120 57040 ) ( 5999960 57040 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 5813680 3240 ) ( 5813680 5994360 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 5633680 3240 ) ( 5633680 5994360 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 5453680 3240 ) ( 5453680 5994360 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 5273680 3240 ) ( 5273680 5994360 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 5093680 3240 ) ( 5093680 5994360 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 4913680 3240 ) ( 4913680 5994360 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 4733680 3240 ) ( 4733680 5994360 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 4553680 3240 ) ( 4553680 5994360 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 4373680 3240 ) ( 4373680 5994360 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 4193680 3240 ) ( 4193680 5994360 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 4013680 3240 ) ( 4013680 5994360 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 3833680 3240 ) ( 3833680 5994360 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 3653680 3240 ) ( 3653680 5994360 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 3473680 3240 ) ( 3473680 5994360 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 3293680 3240 ) ( 3293680 5994360 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 3113680 3240 ) ( 3113680 5994360 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 2933680 3240 ) ( 2933680 5994360 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 2753680 3240 ) ( 2753680 5994360 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 2573680 3240 ) ( 2573680 5994360 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 2393680 3240 ) ( 2393680 5994360 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 2213680 3240 ) ( 2213680 5994360 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 2033680 3240 ) ( 2033680 5994360 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 1853680 3240 ) ( 1853680 5994360 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 1673680 3240 ) ( 1673680 5994360 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 1493680 3240 ) ( 1493680 5994360 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 1313680 3240 ) ( 1313680 5994360 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 1133680 3240 ) ( 1133680 5994360 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 953680 3240 ) ( 953680 5994360 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 773680 3240 ) ( 773680 5994360 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 593680 3240 ) ( 593680 5994360 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 413680 3240 ) ( 413680 5994360 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 233680 3240 ) ( 233680 5994360 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 53680 3240 ) ( 53680 5994360 )
+ NEW Metal4 6200 + SHAPE RING ( 5987260 12840 ) ( 5987260 5984760 )
+ NEW Metal5 6200 + SHAPE RING ( 9480 5981660 ) ( 5990360 5981660 )
+ NEW Metal5 6200 + SHAPE RING ( 9480 15940 ) ( 5990360 15940 )
+ NEW Metal4 6200 + SHAPE RING ( 12580 12840 ) ( 12580 5984760 )
+ NEW Metal4 0 + SHAPE RING ( 5987260 5981660 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5987260 5817040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5987260 5637040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5987260 5457040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5987260 5277040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5987260 5097040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5987260 4917040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5987260 4737040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5987260 4557040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5987260 4377040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5987260 4197040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5987260 4017040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5987260 3837040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5987260 3657040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5987260 3477040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5987260 3297040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5987260 3117040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5987260 2937040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5987260 2757040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5987260 2577040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5987260 2397040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5987260 2217040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5987260 2037040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5987260 1857040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5987260 1677040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5987260 1497040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5987260 1317040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5987260 1137040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5987260 957040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5987260 777040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5987260 597040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5987260 417040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5987260 237040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5987260 57040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE RING ( 5987260 15940 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5813680 5981660 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5813680 5817040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5813680 5637040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5813680 5457040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5813680 5277040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5813680 5097040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5813680 4917040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5813680 4737040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5813680 4557040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5813680 4377040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5813680 4197040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5813680 4017040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5813680 3837040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5813680 3657040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5813680 3477040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5813680 3297040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5813680 3117040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5813680 2937040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5813680 2757040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5813680 2577040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5813680 2397040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5813680 2217040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5813680 2037040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5813680 1857040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5813680 1677040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5813680 1497040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5813680 1317040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5813680 1137040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5813680 957040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5813680 777040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5813680 597040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5813680 417040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5813680 237040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5813680 57040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5813680 15940 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5633680 5981660 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5633680 5817040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5633680 5637040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5633680 5457040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5633680 5277040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5633680 5097040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5633680 4917040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5633680 4737040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5633680 4557040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5633680 4377040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5633680 4197040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5633680 4017040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5633680 3837040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5633680 3657040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5633680 3477040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5633680 3297040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5633680 3117040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5633680 2937040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5633680 2757040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5633680 2577040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5633680 2397040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5633680 2217040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5633680 2037040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5633680 1857040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5633680 1677040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5633680 1497040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5633680 1317040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5633680 1137040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5633680 957040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5633680 777040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5633680 597040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5633680 417040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5633680 237040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5633680 57040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5633680 15940 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5453680 5981660 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5453680 5817040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5453680 5637040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5453680 5457040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5453680 5277040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5453680 5097040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5453680 4917040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5453680 4737040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5453680 4557040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5453680 4377040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5453680 4197040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5453680 4017040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5453680 3837040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5453680 3657040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5453680 3477040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5453680 3297040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5453680 3117040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5453680 2937040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5453680 2757040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5453680 2577040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5453680 2397040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5453680 2217040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5453680 2037040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5453680 1857040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5453680 1677040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5453680 1497040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5453680 1317040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5453680 1137040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5453680 957040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5453680 777040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5453680 597040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5453680 417040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5453680 237040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5453680 57040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5453680 15940 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5273680 5981660 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5273680 5817040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5273680 5637040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5273680 5457040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5273680 5277040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5273680 5097040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5273680 4917040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5273680 4737040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5273680 4557040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5273680 4377040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5273680 4197040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5273680 4017040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5273680 3837040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5273680 3657040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5273680 3477040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5273680 3297040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5273680 3117040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5273680 2937040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5273680 2757040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5273680 2577040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5273680 2397040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5273680 2217040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5273680 2037040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5273680 1857040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5273680 1677040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5273680 1497040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5273680 1317040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5273680 1137040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5273680 957040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5273680 777040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5273680 597040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5273680 417040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5273680 237040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5273680 57040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5273680 15940 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5093680 5981660 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5093680 5817040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5093680 5637040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5093680 5457040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5093680 5277040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5093680 5097040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5093680 4917040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5093680 4737040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5093680 4557040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5093680 4377040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5093680 4197040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5093680 4017040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5093680 3837040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5093680 3657040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5093680 3477040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5093680 3297040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5093680 3117040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5093680 2937040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5093680 2757040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5093680 2577040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5093680 2397040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5093680 2217040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5093680 2037040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5093680 1857040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5093680 1677040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5093680 1497040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5093680 1317040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5093680 1137040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5093680 957040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5093680 777040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5093680 597040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5093680 417040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5093680 237040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5093680 57040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5093680 15940 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4913680 5981660 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4913680 5817040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4913680 5637040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4913680 5457040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4913680 5277040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4913680 5097040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4913680 4917040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4913680 4737040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4913680 4557040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4913680 4377040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4913680 4197040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4913680 4017040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4913680 3837040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4913680 3657040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4913680 3477040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4913680 3297040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4913680 3117040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4913680 2937040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4913680 2757040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4913680 2577040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4913680 2397040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4913680 2217040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4913680 2037040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4913680 1857040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4913680 1677040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4913680 1497040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4913680 1317040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4913680 1137040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4913680 957040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4913680 777040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4913680 597040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4913680 417040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4913680 237040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4913680 57040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4913680 15940 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4733680 5981660 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4733680 5817040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4733680 5637040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4733680 5457040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4733680 5277040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4733680 5097040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4733680 4917040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4733680 4737040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4733680 4557040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4733680 4377040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4733680 4197040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4733680 4017040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4733680 3837040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4733680 3657040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4733680 3477040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4733680 3297040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4733680 3117040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4733680 2937040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4733680 2757040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4733680 2577040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4733680 2397040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4733680 2217040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4733680 2037040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4733680 1857040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4733680 1677040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4733680 1497040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4733680 1317040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4733680 1137040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4733680 957040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4733680 777040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4733680 597040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4733680 417040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4733680 237040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4733680 57040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4733680 15940 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4553680 5981660 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4553680 5817040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4553680 5637040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4553680 5457040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4553680 5277040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4553680 5097040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4553680 4917040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4553680 4737040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4553680 4557040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4553680 4377040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4553680 4197040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4553680 4017040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4553680 3837040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4553680 3657040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4553680 3477040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4553680 3297040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4553680 3117040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4553680 2937040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4553680 2757040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4553680 2577040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4553680 2397040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4553680 2217040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4553680 2037040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4553680 1857040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4553680 1677040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4553680 1497040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4553680 1317040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4553680 1137040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4553680 957040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4553680 777040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4553680 597040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4553680 417040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4553680 237040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4553680 57040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4553680 15940 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4373680 5981660 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4373680 5817040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4373680 5637040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4373680 5457040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4373680 5277040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4373680 5097040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4373680 4917040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4373680 4737040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4373680 4557040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4373680 4377040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4373680 4197040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4373680 4017040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4373680 3837040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4373680 3657040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4373680 3477040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4373680 3297040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4373680 3117040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4373680 2937040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4373680 2757040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4373680 2577040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4373680 2397040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4373680 2217040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4373680 2037040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4373680 1857040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4373680 1677040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4373680 1497040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4373680 1317040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4373680 1137040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4373680 957040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4373680 777040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4373680 597040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4373680 417040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4373680 237040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4373680 57040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4373680 15940 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4193680 5981660 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4193680 5817040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4193680 5637040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4193680 5457040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4193680 5277040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4193680 5097040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4193680 4917040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4193680 4737040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4193680 4557040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4193680 4377040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4193680 4197040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4193680 4017040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4193680 3837040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4193680 3657040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4193680 3477040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4193680 3297040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4193680 3117040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4193680 2937040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4193680 2757040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4193680 2577040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4193680 2397040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4193680 2217040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4193680 2037040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4193680 1857040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4193680 1677040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4193680 1497040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4193680 1317040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4193680 1137040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4193680 957040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4193680 777040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4193680 597040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4193680 417040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4193680 237040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4193680 57040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4193680 15940 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4013680 5981660 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4013680 5817040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4013680 5637040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4013680 5457040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4013680 5277040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4013680 5097040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4013680 4917040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4013680 4737040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4013680 4557040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4013680 4377040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4013680 4197040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4013680 4017040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4013680 3837040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4013680 3657040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4013680 3477040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4013680 3297040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4013680 3117040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4013680 2937040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4013680 2757040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4013680 2577040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4013680 2397040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4013680 2217040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4013680 2037040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4013680 1857040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4013680 1677040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4013680 1497040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4013680 1317040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4013680 1137040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4013680 957040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4013680 777040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4013680 597040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4013680 417040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4013680 237040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4013680 57040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4013680 15940 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3833680 5981660 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3833680 5817040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3833680 5637040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3833680 5457040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3833680 5277040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3833680 5097040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3833680 4917040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3833680 4737040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3833680 4557040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3833680 4377040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3833680 4197040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3833680 4017040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3833680 3837040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3833680 3657040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3833680 3477040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3833680 3297040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3833680 3117040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3833680 2937040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3833680 2757040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3833680 2577040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3833680 2397040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3833680 2217040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3833680 2037040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3833680 1857040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3833680 1677040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3833680 1497040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3833680 1317040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3833680 1137040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3833680 957040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3833680 777040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3833680 597040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3833680 417040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3833680 237040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3833680 57040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3833680 15940 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3653680 5981660 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3653680 5817040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3653680 5637040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3653680 5457040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3653680 5277040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3653680 5097040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3653680 4917040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3653680 4737040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3653680 4557040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3653680 4377040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3653680 4197040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3653680 4017040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3653680 3837040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3653680 3657040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3653680 3477040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3653680 3297040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3653680 3117040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3653680 2937040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3653680 2757040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3653680 2577040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3653680 2397040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3653680 2217040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3653680 2037040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3653680 1857040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3653680 1677040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3653680 1497040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3653680 1317040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3653680 1137040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3653680 957040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3653680 777040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3653680 597040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3653680 417040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3653680 237040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3653680 57040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3653680 15940 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3473680 5981660 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3473680 5817040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3473680 5637040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3473680 5457040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3473680 5277040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3473680 5097040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3473680 4917040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3473680 4737040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3473680 4557040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3473680 4377040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3473680 4197040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3473680 4017040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3473680 3837040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3473680 3657040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3473680 3477040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3473680 3297040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3473680 3117040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3473680 2937040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3473680 2757040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3473680 2577040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3473680 2397040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3473680 2217040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3473680 2037040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3473680 1857040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3473680 1677040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3473680 1497040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3473680 1317040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3473680 1137040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3473680 957040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3473680 777040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3473680 597040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3473680 417040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3473680 237040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3473680 57040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3473680 15940 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3293680 5981660 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3293680 5817040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3293680 5637040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3293680 5457040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3293680 5277040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3293680 5097040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3293680 4917040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3293680 4737040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3293680 4557040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3293680 4377040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3293680 4197040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3293680 4017040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3293680 3837040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3293680 3657040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3293680 3477040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3293680 3297040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3293680 3117040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3293680 2937040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3293680 2757040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3293680 2577040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3293680 2397040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3293680 2217040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3293680 2037040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3293680 1857040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3293680 1677040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3293680 1497040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3293680 1317040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3293680 1137040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3293680 957040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3293680 777040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3293680 597040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3293680 417040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3293680 237040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3293680 57040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3293680 15940 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3113680 5981660 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3113680 5817040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3113680 5637040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3113680 5457040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3113680 5277040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3113680 5097040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3113680 4917040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3113680 4737040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3113680 4557040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3113680 4377040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3113680 4197040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3113680 4017040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3113680 3837040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3113680 3657040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3113680 3477040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3113680 3297040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3113680 3117040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3113680 2937040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3113680 2757040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3113680 2577040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3113680 2397040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3113680 2217040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3113680 2037040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3113680 1857040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3113680 1677040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3113680 1497040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3113680 1317040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3113680 1137040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3113680 957040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3113680 777040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3113680 597040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3113680 417040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3113680 237040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3113680 57040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3113680 15940 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2933680 5981660 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2933680 5817040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2933680 5637040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2933680 5457040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2933680 5277040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2933680 5097040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2933680 4917040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2933680 4737040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2933680 4557040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2933680 4377040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2933680 4197040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2933680 4017040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2933680 3837040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2933680 3657040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2933680 3477040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2933680 3297040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2933680 3117040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2933680 2937040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2933680 2757040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2933680 2577040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2933680 2397040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2933680 2217040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2933680 2037040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2933680 1857040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2933680 1677040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2933680 1497040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2933680 1317040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2933680 1137040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2933680 957040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2933680 777040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2933680 597040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2933680 417040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2933680 237040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2933680 57040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2933680 15940 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2753680 5981660 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2753680 5817040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2753680 5637040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2753680 5457040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2753680 5277040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2753680 5097040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2753680 4917040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2753680 4737040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2753680 4557040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2753680 4377040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2753680 4197040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2753680 4017040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2753680 3837040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2753680 3657040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2753680 3477040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2753680 3297040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2753680 3117040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2753680 2937040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2753680 2757040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2753680 2577040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2753680 2397040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2753680 2217040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2753680 2037040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2753680 1857040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2753680 1677040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2753680 1497040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2753680 1317040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2753680 1137040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2753680 957040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2753680 777040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2753680 597040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2753680 417040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2753680 237040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2753680 57040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2753680 15940 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2573680 5981660 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2573680 5817040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2573680 5637040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2573680 5457040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2573680 5277040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2573680 5097040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2573680 4917040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2573680 4737040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2573680 4557040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2573680 4377040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2573680 4197040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2573680 4017040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2573680 3837040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2573680 3657040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2573680 3477040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2573680 3297040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2573680 3117040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2573680 2937040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2573680 2757040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2573680 2577040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2573680 2397040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2573680 2217040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2573680 2037040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2573680 1857040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2573680 1677040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2573680 1497040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2573680 1317040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2573680 1137040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2573680 957040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2573680 777040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2573680 597040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2573680 417040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2573680 237040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2573680 57040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2573680 15940 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2393680 5981660 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2393680 5817040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2393680 5637040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2393680 5457040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2393680 5277040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2393680 5097040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2393680 4917040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2393680 4737040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2393680 4557040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2393680 4377040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2393680 4197040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2393680 4017040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2393680 3837040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2393680 3657040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2393680 3477040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2393680 3297040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2393680 3117040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2393680 2937040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2393680 2757040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2393680 2577040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2393680 2397040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2393680 2217040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2393680 2037040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2393680 1857040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2393680 1677040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2393680 1497040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2393680 1317040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2393680 1137040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2393680 957040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2393680 777040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2393680 597040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2393680 417040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2393680 237040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2393680 57040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2393680 15940 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2213680 5981660 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2213680 5817040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2213680 5637040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2213680 5457040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2213680 5277040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2213680 5097040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2213680 4917040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2213680 4737040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2213680 4557040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2213680 4377040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2213680 4197040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2213680 4017040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2213680 3837040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2213680 3657040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2213680 3477040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2213680 3297040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2213680 3117040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2213680 2937040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2213680 2757040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2213680 2577040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2213680 2397040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2213680 2217040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2213680 2037040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2213680 1857040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2213680 1677040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2213680 1497040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2213680 1317040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2213680 1137040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2213680 957040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2213680 777040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2213680 597040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2213680 417040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2213680 237040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2213680 57040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2213680 15940 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2033680 5981660 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2033680 5817040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2033680 5637040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2033680 5457040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2033680 5277040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2033680 5097040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2033680 4917040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2033680 4737040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2033680 4557040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2033680 4377040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2033680 4197040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2033680 4017040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2033680 3837040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2033680 3657040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2033680 3477040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2033680 3297040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2033680 3117040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2033680 2937040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2033680 2757040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2033680 2577040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2033680 2397040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2033680 2217040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2033680 2037040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2033680 1857040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2033680 1677040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2033680 1497040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2033680 1317040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2033680 1137040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2033680 957040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2033680 777040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2033680 597040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2033680 417040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2033680 237040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2033680 57040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2033680 15940 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1853680 5981660 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1853680 5817040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1853680 5637040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1853680 5457040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1853680 5277040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1853680 5097040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1853680 4917040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1853680 4737040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1853680 4557040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1853680 4377040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1853680 4197040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1853680 4017040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1853680 3837040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1853680 3657040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1853680 3477040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1853680 3297040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1853680 3117040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1853680 2937040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1853680 2757040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1853680 2577040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1853680 2397040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1853680 2217040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1853680 2037040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1853680 1857040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1853680 1677040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1853680 1497040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1853680 1317040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1853680 1137040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1853680 957040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1853680 777040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1853680 597040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1853680 417040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1853680 237040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1853680 57040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1853680 15940 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1673680 5981660 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1673680 5817040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1673680 5637040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1673680 5457040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1673680 5277040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1673680 5097040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1673680 4917040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1673680 4737040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1673680 4557040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1673680 4377040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1673680 4197040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1673680 4017040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1673680 3837040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1673680 3657040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1673680 3477040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1673680 3297040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1673680 3117040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1673680 2937040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1673680 2757040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1673680 2577040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1673680 2397040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1673680 2217040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1673680 2037040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1673680 1857040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1673680 1677040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1673680 1497040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1673680 1317040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1673680 1137040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1673680 957040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1673680 777040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1673680 597040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1673680 417040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1673680 237040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1673680 57040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1673680 15940 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1493680 5981660 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1493680 5817040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1493680 5637040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1493680 5457040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1493680 5277040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1493680 5097040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1493680 4917040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1493680 4737040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1493680 4557040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1493680 4377040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1493680 4197040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1493680 4017040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1493680 3837040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1493680 3657040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1493680 3477040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1493680 3297040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1493680 3117040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1493680 2937040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1493680 2757040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1493680 2577040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1493680 2397040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1493680 2217040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1493680 2037040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1493680 1857040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1493680 1677040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1493680 1497040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1493680 1317040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1493680 1137040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1493680 957040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1493680 777040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1493680 597040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1493680 417040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1493680 237040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1493680 57040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1493680 15940 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1313680 5981660 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1313680 5817040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1313680 5637040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1313680 5457040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1313680 5277040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1313680 5097040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1313680 4917040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1313680 4737040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1313680 4557040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1313680 4377040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1313680 4197040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1313680 4017040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1313680 3837040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1313680 3657040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1313680 3477040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1313680 3297040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1313680 3117040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1313680 2937040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1313680 2757040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1313680 2577040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1313680 2397040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1313680 2217040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1313680 2037040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1313680 1857040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1313680 1677040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1313680 1497040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1313680 1317040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1313680 1137040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1313680 957040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1313680 777040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1313680 597040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1313680 417040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1313680 237040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1313680 57040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1313680 15940 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1133680 5981660 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1133680 5817040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1133680 5637040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1133680 5457040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1133680 5277040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1133680 5097040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1133680 4917040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1133680 4737040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1133680 4557040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1133680 4377040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1133680 4197040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1133680 4017040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1133680 3837040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1133680 3657040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1133680 3477040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1133680 3297040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1133680 3117040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1133680 2937040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1133680 2757040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1133680 2577040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1133680 2397040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1133680 2217040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1133680 2037040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1133680 1857040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1133680 1677040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1133680 1497040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1133680 1317040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1133680 1137040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1133680 957040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1133680 777040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1133680 597040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1133680 417040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1133680 237040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1133680 57040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1133680 15940 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 953680 5981660 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 953680 5817040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 953680 5637040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 953680 5457040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 953680 5277040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 953680 5097040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 953680 4917040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 953680 4737040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 953680 4557040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 953680 4377040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 953680 4197040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 953680 4017040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 953680 3837040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 953680 3657040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 953680 3477040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 953680 3297040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 953680 3117040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 953680 2937040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 953680 2757040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 953680 2577040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 953680 2397040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 953680 2217040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 953680 2037040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 953680 1857040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 953680 1677040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 953680 1497040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 953680 1317040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 953680 1137040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 953680 957040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 953680 777040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 953680 597040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 953680 417040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 953680 237040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 953680 57040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 953680 15940 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 773680 5981660 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 773680 5817040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 773680 5637040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 773680 5457040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 773680 5277040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 773680 5097040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 773680 4917040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 773680 4737040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 773680 4557040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 773680 4377040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 773680 4197040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 773680 4017040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 773680 3837040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 773680 3657040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 773680 3477040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 773680 3297040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 773680 3117040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 773680 2937040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 773680 2757040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 773680 2577040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 773680 2397040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 773680 2217040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 773680 2037040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 773680 1857040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 773680 1677040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 773680 1497040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 773680 1317040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 773680 1137040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 773680 957040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 773680 777040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 773680 597040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 773680 417040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 773680 237040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 773680 57040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 773680 15940 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 593680 5981660 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 593680 5817040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 593680 5637040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 593680 5457040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 593680 5277040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 593680 5097040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 593680 4917040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 593680 4737040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 593680 4557040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 593680 4377040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 593680 4197040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 593680 4017040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 593680 3837040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 593680 3657040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 593680 3477040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 593680 3297040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 593680 3117040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 593680 2937040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 593680 2757040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 593680 2577040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 593680 2397040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 593680 2217040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 593680 2037040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 593680 1857040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 593680 1677040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 593680 1497040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 593680 1317040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 593680 1137040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 593680 957040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 593680 777040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 593680 597040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 593680 417040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 593680 237040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 593680 57040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 593680 15940 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 413680 5981660 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 413680 5817040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 413680 5637040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 413680 5457040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 413680 5277040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 413680 5097040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 413680 4917040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 413680 4737040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 413680 4557040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 413680 4377040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 413680 4197040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 413680 4017040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 413680 3837040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 413680 3657040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 413680 3477040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 413680 3297040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 413680 3117040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 413680 2937040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 413680 2757040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 413680 2577040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 413680 2397040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 413680 2217040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 413680 2037040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 413680 1857040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 413680 1677040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 413680 1497040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 413680 1317040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 413680 1137040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 413680 957040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 413680 777040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 413680 597040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 413680 417040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 413680 237040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 413680 57040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 413680 15940 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 233680 5981660 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 233680 5817040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 233680 5637040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 233680 5457040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 233680 5277040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 233680 5097040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 233680 4917040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 233680 4737040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 233680 4557040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 233680 4377040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 233680 4197040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 233680 4017040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 233680 3837040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 233680 3657040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 233680 3477040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 233680 3297040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 233680 3117040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 233680 2937040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 233680 2757040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 233680 2577040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 233680 2397040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 233680 2217040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 233680 2037040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 233680 1857040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 233680 1677040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 233680 1497040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 233680 1317040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 233680 1137040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 233680 957040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 233680 777040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 233680 597040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 233680 417040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 233680 237040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 233680 57040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 233680 15940 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 53680 5981660 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 53680 5817040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 53680 5637040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 53680 5457040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 53680 5277040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 53680 5097040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 53680 4917040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 53680 4737040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 53680 4557040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 53680 4377040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 53680 4197040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 53680 4017040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 53680 3837040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 53680 3657040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 53680 3477040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 53680 3297040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 53680 3117040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 53680 2937040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 53680 2757040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 53680 2577040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 53680 2397040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 53680 2217040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 53680 2037040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 53680 1857040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 53680 1677040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 53680 1497040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 53680 1317040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 53680 1137040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 53680 957040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 53680 777040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 53680 597040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 53680 417040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 53680 237040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 53680 57040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 53680 15940 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE RING ( 12580 5981660 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 12580 5817040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 12580 5637040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 12580 5457040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 12580 5277040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 12580 5097040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 12580 4917040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 12580 4737040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 12580 4557040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 12580 4377040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 12580 4197040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 12580 4017040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 12580 3837040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 12580 3657040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 12580 3477040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 12580 3297040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 12580 3117040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 12580 2937040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 12580 2757040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 12580 2577040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 12580 2397040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 12580 2217040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 12580 2037040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 12580 1857040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 12580 1677040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 12580 1497040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 12580 1317040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 12580 1137040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 12580 957040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 12580 777040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 12580 597040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 12580 417040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 12580 237040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 12580 57040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE RING ( 12580 15940 ) via4_5_6200_6200_6_6_1040_1040 ;
+ - vss ( PIN vss ) ( * VSS ) + USE GROUND
+ + ROUTED Metal5 6200 + SHAPE STRIPE ( -120 5877040 ) ( 5999960 5877040 )
+ NEW Metal5 6200 + SHAPE STRIPE ( -120 5697040 ) ( 5999960 5697040 )
+ NEW Metal5 6200 + SHAPE STRIPE ( -120 5517040 ) ( 5999960 5517040 )
+ NEW Metal5 6200 + SHAPE STRIPE ( -120 5337040 ) ( 5999960 5337040 )
+ NEW Metal5 6200 + SHAPE STRIPE ( -120 5157040 ) ( 5999960 5157040 )
+ NEW Metal5 6200 + SHAPE STRIPE ( -120 4977040 ) ( 5999960 4977040 )
+ NEW Metal5 6200 + SHAPE STRIPE ( -120 4797040 ) ( 5999960 4797040 )
+ NEW Metal5 6200 + SHAPE STRIPE ( -120 4617040 ) ( 5999960 4617040 )
+ NEW Metal5 6200 + SHAPE STRIPE ( -120 4437040 ) ( 5999960 4437040 )
+ NEW Metal5 6200 + SHAPE STRIPE ( -120 4257040 ) ( 5999960 4257040 )
+ NEW Metal5 6200 + SHAPE STRIPE ( -120 4077040 ) ( 5999960 4077040 )
+ NEW Metal5 6200 + SHAPE STRIPE ( -120 3897040 ) ( 5999960 3897040 )
+ NEW Metal5 6200 + SHAPE STRIPE ( -120 3717040 ) ( 5999960 3717040 )
+ NEW Metal5 6200 + SHAPE STRIPE ( -120 3537040 ) ( 5999960 3537040 )
+ NEW Metal5 6200 + SHAPE STRIPE ( -120 3357040 ) ( 5999960 3357040 )
+ NEW Metal5 6200 + SHAPE STRIPE ( -120 3177040 ) ( 5999960 3177040 )
+ NEW Metal5 6200 + SHAPE STRIPE ( -120 2997040 ) ( 5999960 2997040 )
+ NEW Metal5 6200 + SHAPE STRIPE ( -120 2817040 ) ( 5999960 2817040 )
+ NEW Metal5 6200 + SHAPE STRIPE ( -120 2637040 ) ( 5999960 2637040 )
+ NEW Metal5 6200 + SHAPE STRIPE ( -120 2457040 ) ( 5999960 2457040 )
+ NEW Metal5 6200 + SHAPE STRIPE ( -120 2277040 ) ( 5999960 2277040 )
+ NEW Metal5 6200 + SHAPE STRIPE ( -120 2097040 ) ( 5999960 2097040 )
+ NEW Metal5 6200 + SHAPE STRIPE ( -120 1917040 ) ( 5999960 1917040 )
+ NEW Metal5 6200 + SHAPE STRIPE ( -120 1737040 ) ( 5999960 1737040 )
+ NEW Metal5 6200 + SHAPE STRIPE ( -120 1557040 ) ( 5999960 1557040 )
+ NEW Metal5 6200 + SHAPE STRIPE ( -120 1377040 ) ( 5999960 1377040 )
+ NEW Metal5 6200 + SHAPE STRIPE ( -120 1197040 ) ( 5999960 1197040 )
+ NEW Metal5 6200 + SHAPE STRIPE ( -120 1017040 ) ( 5999960 1017040 )
+ NEW Metal5 6200 + SHAPE STRIPE ( -120 837040 ) ( 5999960 837040 )
+ NEW Metal5 6200 + SHAPE STRIPE ( -120 657040 ) ( 5999960 657040 )
+ NEW Metal5 6200 + SHAPE STRIPE ( -120 477040 ) ( 5999960 477040 )
+ NEW Metal5 6200 + SHAPE STRIPE ( -120 297040 ) ( 5999960 297040 )
+ NEW Metal5 6200 + SHAPE STRIPE ( -120 117040 ) ( 5999960 117040 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 5850880 3240 ) ( 5850880 5994360 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 5670880 3240 ) ( 5670880 5994360 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 5490880 3240 ) ( 5490880 5994360 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 5310880 3240 ) ( 5310880 5994360 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 5130880 3240 ) ( 5130880 5994360 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 4950880 3240 ) ( 4950880 5994360 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 4770880 3240 ) ( 4770880 5994360 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 4590880 3240 ) ( 4590880 5994360 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 4410880 3240 ) ( 4410880 5994360 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 4230880 3240 ) ( 4230880 5994360 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 4050880 3240 ) ( 4050880 5994360 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 3870880 3240 ) ( 3870880 5994360 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 3690880 3240 ) ( 3690880 5994360 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 3510880 3240 ) ( 3510880 5994360 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 3330880 3240 ) ( 3330880 5994360 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 3150880 3240 ) ( 3150880 5994360 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 2970880 3240 ) ( 2970880 5994360 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 2790880 3240 ) ( 2790880 5994360 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 2610880 3240 ) ( 2610880 5994360 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 2430880 3240 ) ( 2430880 5994360 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 2250880 3240 ) ( 2250880 5994360 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 2070880 3240 ) ( 2070880 5994360 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 1890880 3240 ) ( 1890880 5994360 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 1710880 3240 ) ( 1710880 5994360 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 1530880 3240 ) ( 1530880 5994360 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 1350880 3240 ) ( 1350880 5994360 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 1170880 3240 ) ( 1170880 5994360 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 990880 3240 ) ( 990880 5994360 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 810880 3240 ) ( 810880 5994360 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 630880 3240 ) ( 630880 5994360 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 450880 3240 ) ( 450880 5994360 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 270880 3240 ) ( 270880 5994360 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 90880 3240 ) ( 90880 5994360 )
+ NEW Metal4 6200 + SHAPE RING ( 5996860 3240 ) ( 5996860 5994360 )
+ NEW Metal5 6200 + SHAPE RING ( -120 5991260 ) ( 5999960 5991260 )
+ NEW Metal5 6200 + SHAPE RING ( -120 6340 ) ( 5999960 6340 )
+ NEW Metal4 6200 + SHAPE RING ( 2980 3240 ) ( 2980 5994360 )
+ NEW Metal4 0 + SHAPE RING ( 5996860 5991260 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5996860 5877040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5996860 5697040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5996860 5517040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5996860 5337040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5996860 5157040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5996860 4977040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5996860 4797040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5996860 4617040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5996860 4437040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5996860 4257040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5996860 4077040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5996860 3897040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5996860 3717040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5996860 3537040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5996860 3357040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5996860 3177040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5996860 2997040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5996860 2817040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5996860 2637040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5996860 2457040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5996860 2277040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5996860 2097040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5996860 1917040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5996860 1737040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5996860 1557040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5996860 1377040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5996860 1197040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5996860 1017040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5996860 837040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5996860 657040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5996860 477040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5996860 297040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5996860 117040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE RING ( 5996860 6340 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5850880 5991260 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5850880 5877040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5850880 5697040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5850880 5517040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5850880 5337040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5850880 5157040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5850880 4977040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5850880 4797040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5850880 4617040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5850880 4437040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5850880 4257040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5850880 4077040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5850880 3897040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5850880 3717040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5850880 3537040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5850880 3357040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5850880 3177040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5850880 2997040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5850880 2817040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5850880 2637040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5850880 2457040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5850880 2277040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5850880 2097040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5850880 1917040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5850880 1737040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5850880 1557040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5850880 1377040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5850880 1197040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5850880 1017040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5850880 837040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5850880 657040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5850880 477040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5850880 297040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5850880 117040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5850880 6340 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5670880 5991260 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5670880 5877040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5670880 5697040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5670880 5517040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5670880 5337040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5670880 5157040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5670880 4977040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5670880 4797040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5670880 4617040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5670880 4437040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5670880 4257040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5670880 4077040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5670880 3897040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5670880 3717040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5670880 3537040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5670880 3357040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5670880 3177040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5670880 2997040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5670880 2817040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5670880 2637040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5670880 2457040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5670880 2277040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5670880 2097040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5670880 1917040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5670880 1737040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5670880 1557040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5670880 1377040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5670880 1197040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5670880 1017040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5670880 837040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5670880 657040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5670880 477040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5670880 297040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5670880 117040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5670880 6340 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5490880 5991260 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5490880 5877040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5490880 5697040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5490880 5517040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5490880 5337040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5490880 5157040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5490880 4977040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5490880 4797040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5490880 4617040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5490880 4437040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5490880 4257040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5490880 4077040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5490880 3897040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5490880 3717040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5490880 3537040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5490880 3357040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5490880 3177040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5490880 2997040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5490880 2817040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5490880 2637040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5490880 2457040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5490880 2277040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5490880 2097040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5490880 1917040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5490880 1737040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5490880 1557040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5490880 1377040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5490880 1197040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5490880 1017040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5490880 837040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5490880 657040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5490880 477040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5490880 297040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5490880 117040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5490880 6340 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5310880 5991260 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5310880 5877040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5310880 5697040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5310880 5517040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5310880 5337040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5310880 5157040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5310880 4977040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5310880 4797040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5310880 4617040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5310880 4437040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5310880 4257040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5310880 4077040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5310880 3897040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5310880 3717040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5310880 3537040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5310880 3357040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5310880 3177040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5310880 2997040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5310880 2817040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5310880 2637040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5310880 2457040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5310880 2277040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5310880 2097040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5310880 1917040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5310880 1737040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5310880 1557040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5310880 1377040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5310880 1197040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5310880 1017040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5310880 837040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5310880 657040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5310880 477040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5310880 297040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5310880 117040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5310880 6340 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5130880 5991260 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5130880 5877040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5130880 5697040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5130880 5517040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5130880 5337040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5130880 5157040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5130880 4977040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5130880 4797040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5130880 4617040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5130880 4437040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5130880 4257040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5130880 4077040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5130880 3897040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5130880 3717040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5130880 3537040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5130880 3357040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5130880 3177040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5130880 2997040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5130880 2817040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5130880 2637040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5130880 2457040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5130880 2277040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5130880 2097040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5130880 1917040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5130880 1737040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5130880 1557040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5130880 1377040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5130880 1197040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5130880 1017040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5130880 837040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5130880 657040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5130880 477040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5130880 297040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5130880 117040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5130880 6340 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4950880 5991260 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4950880 5877040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4950880 5697040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4950880 5517040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4950880 5337040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4950880 5157040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4950880 4977040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4950880 4797040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4950880 4617040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4950880 4437040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4950880 4257040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4950880 4077040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4950880 3897040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4950880 3717040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4950880 3537040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4950880 3357040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4950880 3177040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4950880 2997040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4950880 2817040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4950880 2637040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4950880 2457040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4950880 2277040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4950880 2097040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4950880 1917040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4950880 1737040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4950880 1557040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4950880 1377040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4950880 1197040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4950880 1017040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4950880 837040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4950880 657040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4950880 477040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4950880 297040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4950880 117040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4950880 6340 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4770880 5991260 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4770880 5877040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4770880 5697040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4770880 5517040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4770880 5337040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4770880 5157040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4770880 4977040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4770880 4797040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4770880 4617040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4770880 4437040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4770880 4257040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4770880 4077040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4770880 3897040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4770880 3717040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4770880 3537040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4770880 3357040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4770880 3177040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4770880 2997040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4770880 2817040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4770880 2637040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4770880 2457040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4770880 2277040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4770880 2097040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4770880 1917040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4770880 1737040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4770880 1557040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4770880 1377040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4770880 1197040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4770880 1017040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4770880 837040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4770880 657040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4770880 477040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4770880 297040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4770880 117040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4770880 6340 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4590880 5991260 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4590880 5877040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4590880 5697040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4590880 5517040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4590880 5337040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4590880 5157040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4590880 4977040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4590880 4797040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4590880 4617040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4590880 4437040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4590880 4257040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4590880 4077040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4590880 3897040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4590880 3717040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4590880 3537040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4590880 3357040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4590880 3177040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4590880 2997040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4590880 2817040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4590880 2637040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4590880 2457040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4590880 2277040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4590880 2097040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4590880 1917040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4590880 1737040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4590880 1557040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4590880 1377040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4590880 1197040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4590880 1017040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4590880 837040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4590880 657040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4590880 477040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4590880 297040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4590880 117040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4590880 6340 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4410880 5991260 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4410880 5877040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4410880 5697040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4410880 5517040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4410880 5337040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4410880 5157040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4410880 4977040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4410880 4797040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4410880 4617040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4410880 4437040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4410880 4257040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4410880 4077040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4410880 3897040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4410880 3717040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4410880 3537040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4410880 3357040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4410880 3177040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4410880 2997040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4410880 2817040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4410880 2637040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4410880 2457040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4410880 2277040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4410880 2097040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4410880 1917040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4410880 1737040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4410880 1557040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4410880 1377040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4410880 1197040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4410880 1017040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4410880 837040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4410880 657040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4410880 477040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4410880 297040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4410880 117040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4410880 6340 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4230880 5991260 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4230880 5877040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4230880 5697040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4230880 5517040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4230880 5337040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4230880 5157040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4230880 4977040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4230880 4797040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4230880 4617040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4230880 4437040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4230880 4257040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4230880 4077040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4230880 3897040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4230880 3717040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4230880 3537040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4230880 3357040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4230880 3177040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4230880 2997040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4230880 2817040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4230880 2637040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4230880 2457040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4230880 2277040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4230880 2097040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4230880 1917040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4230880 1737040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4230880 1557040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4230880 1377040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4230880 1197040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4230880 1017040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4230880 837040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4230880 657040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4230880 477040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4230880 297040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4230880 117040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4230880 6340 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4050880 5991260 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4050880 5877040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4050880 5697040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4050880 5517040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4050880 5337040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4050880 5157040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4050880 4977040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4050880 4797040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4050880 4617040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4050880 4437040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4050880 4257040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4050880 4077040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4050880 3897040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4050880 3717040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4050880 3537040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4050880 3357040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4050880 3177040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4050880 2997040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4050880 2817040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4050880 2637040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4050880 2457040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4050880 2277040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4050880 2097040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4050880 1917040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4050880 1737040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4050880 1557040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4050880 1377040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4050880 1197040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4050880 1017040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4050880 837040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4050880 657040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4050880 477040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4050880 297040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4050880 117040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4050880 6340 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3870880 5991260 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3870880 5877040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3870880 5697040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3870880 5517040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3870880 5337040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3870880 5157040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3870880 4977040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3870880 4797040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3870880 4617040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3870880 4437040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3870880 4257040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3870880 4077040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3870880 3897040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3870880 3717040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3870880 3537040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3870880 3357040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3870880 3177040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3870880 2997040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3870880 2817040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3870880 2637040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3870880 2457040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3870880 2277040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3870880 2097040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3870880 1917040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3870880 1737040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3870880 1557040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3870880 1377040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3870880 1197040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3870880 1017040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3870880 837040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3870880 657040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3870880 477040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3870880 297040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3870880 117040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3870880 6340 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3690880 5991260 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3690880 5877040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3690880 5697040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3690880 5517040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3690880 5337040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3690880 5157040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3690880 4977040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3690880 4797040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3690880 4617040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3690880 4437040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3690880 4257040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3690880 4077040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3690880 3897040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3690880 3717040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3690880 3537040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3690880 3357040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3690880 3177040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3690880 2997040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3690880 2817040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3690880 2637040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3690880 2457040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3690880 2277040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3690880 2097040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3690880 1917040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3690880 1737040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3690880 1557040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3690880 1377040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3690880 1197040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3690880 1017040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3690880 837040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3690880 657040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3690880 477040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3690880 297040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3690880 117040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3690880 6340 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3510880 5991260 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3510880 5877040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3510880 5697040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3510880 5517040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3510880 5337040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3510880 5157040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3510880 4977040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3510880 4797040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3510880 4617040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3510880 4437040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3510880 4257040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3510880 4077040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3510880 3897040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3510880 3717040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3510880 3537040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3510880 3357040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3510880 3177040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3510880 2997040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3510880 2817040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3510880 2637040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3510880 2457040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3510880 2277040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3510880 2097040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3510880 1917040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3510880 1737040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3510880 1557040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3510880 1377040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3510880 1197040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3510880 1017040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3510880 837040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3510880 657040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3510880 477040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3510880 297040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3510880 117040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3510880 6340 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3330880 5991260 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3330880 5877040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3330880 5697040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3330880 5517040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3330880 5337040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3330880 5157040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3330880 4977040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3330880 4797040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3330880 4617040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3330880 4437040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3330880 4257040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3330880 4077040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3330880 3897040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3330880 3717040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3330880 3537040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3330880 3357040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3330880 3177040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3330880 2997040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3330880 2817040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3330880 2637040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3330880 2457040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3330880 2277040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3330880 2097040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3330880 1917040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3330880 1737040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3330880 1557040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3330880 1377040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3330880 1197040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3330880 1017040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3330880 837040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3330880 657040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3330880 477040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3330880 297040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3330880 117040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3330880 6340 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3150880 5991260 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3150880 5877040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3150880 5697040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3150880 5517040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3150880 5337040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3150880 5157040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3150880 4977040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3150880 4797040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3150880 4617040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3150880 4437040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3150880 4257040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3150880 4077040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3150880 3897040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3150880 3717040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3150880 3537040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3150880 3357040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3150880 3177040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3150880 2997040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3150880 2817040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3150880 2637040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3150880 2457040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3150880 2277040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3150880 2097040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3150880 1917040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3150880 1737040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3150880 1557040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3150880 1377040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3150880 1197040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3150880 1017040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3150880 837040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3150880 657040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3150880 477040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3150880 297040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3150880 117040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3150880 6340 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2970880 5991260 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2970880 5877040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2970880 5697040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2970880 5517040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2970880 5337040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2970880 5157040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2970880 4977040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2970880 4797040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2970880 4617040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2970880 4437040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2970880 4257040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2970880 4077040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2970880 3897040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2970880 3717040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2970880 3537040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2970880 3357040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2970880 3177040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2970880 2997040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2970880 2817040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2970880 2637040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2970880 2457040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2970880 2277040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2970880 2097040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2970880 1917040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2970880 1737040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2970880 1557040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2970880 1377040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2970880 1197040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2970880 1017040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2970880 837040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2970880 657040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2970880 477040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2970880 297040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2970880 117040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2970880 6340 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2790880 5991260 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2790880 5877040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2790880 5697040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2790880 5517040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2790880 5337040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2790880 5157040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2790880 4977040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2790880 4797040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2790880 4617040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2790880 4437040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2790880 4257040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2790880 4077040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2790880 3897040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2790880 3717040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2790880 3537040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2790880 3357040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2790880 3177040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2790880 2997040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2790880 2817040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2790880 2637040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2790880 2457040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2790880 2277040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2790880 2097040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2790880 1917040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2790880 1737040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2790880 1557040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2790880 1377040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2790880 1197040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2790880 1017040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2790880 837040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2790880 657040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2790880 477040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2790880 297040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2790880 117040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2790880 6340 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2610880 5991260 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2610880 5877040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2610880 5697040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2610880 5517040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2610880 5337040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2610880 5157040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2610880 4977040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2610880 4797040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2610880 4617040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2610880 4437040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2610880 4257040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2610880 4077040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2610880 3897040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2610880 3717040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2610880 3537040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2610880 3357040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2610880 3177040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2610880 2997040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2610880 2817040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2610880 2637040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2610880 2457040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2610880 2277040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2610880 2097040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2610880 1917040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2610880 1737040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2610880 1557040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2610880 1377040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2610880 1197040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2610880 1017040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2610880 837040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2610880 657040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2610880 477040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2610880 297040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2610880 117040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2610880 6340 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2430880 5991260 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2430880 5877040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2430880 5697040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2430880 5517040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2430880 5337040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2430880 5157040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2430880 4977040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2430880 4797040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2430880 4617040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2430880 4437040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2430880 4257040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2430880 4077040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2430880 3897040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2430880 3717040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2430880 3537040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2430880 3357040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2430880 3177040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2430880 2997040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2430880 2817040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2430880 2637040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2430880 2457040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2430880 2277040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2430880 2097040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2430880 1917040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2430880 1737040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2430880 1557040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2430880 1377040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2430880 1197040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2430880 1017040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2430880 837040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2430880 657040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2430880 477040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2430880 297040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2430880 117040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2430880 6340 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2250880 5991260 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2250880 5877040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2250880 5697040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2250880 5517040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2250880 5337040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2250880 5157040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2250880 4977040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2250880 4797040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2250880 4617040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2250880 4437040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2250880 4257040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2250880 4077040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2250880 3897040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2250880 3717040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2250880 3537040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2250880 3357040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2250880 3177040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2250880 2997040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2250880 2817040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2250880 2637040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2250880 2457040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2250880 2277040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2250880 2097040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2250880 1917040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2250880 1737040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2250880 1557040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2250880 1377040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2250880 1197040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2250880 1017040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2250880 837040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2250880 657040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2250880 477040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2250880 297040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2250880 117040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2250880 6340 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2070880 5991260 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2070880 5877040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2070880 5697040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2070880 5517040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2070880 5337040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2070880 5157040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2070880 4977040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2070880 4797040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2070880 4617040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2070880 4437040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2070880 4257040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2070880 4077040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2070880 3897040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2070880 3717040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2070880 3537040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2070880 3357040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2070880 3177040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2070880 2997040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2070880 2817040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2070880 2637040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2070880 2457040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2070880 2277040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2070880 2097040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2070880 1917040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2070880 1737040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2070880 1557040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2070880 1377040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2070880 1197040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2070880 1017040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2070880 837040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2070880 657040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2070880 477040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2070880 297040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2070880 117040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2070880 6340 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1890880 5991260 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1890880 5877040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1890880 5697040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1890880 5517040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1890880 5337040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1890880 5157040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1890880 4977040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1890880 4797040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1890880 4617040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1890880 4437040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1890880 4257040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1890880 4077040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1890880 3897040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1890880 3717040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1890880 3537040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1890880 3357040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1890880 3177040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1890880 2997040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1890880 2817040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1890880 2637040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1890880 2457040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1890880 2277040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1890880 2097040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1890880 1917040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1890880 1737040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1890880 1557040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1890880 1377040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1890880 1197040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1890880 1017040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1890880 837040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1890880 657040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1890880 477040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1890880 297040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1890880 117040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1890880 6340 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1710880 5991260 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1710880 5877040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1710880 5697040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1710880 5517040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1710880 5337040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1710880 5157040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1710880 4977040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1710880 4797040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1710880 4617040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1710880 4437040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1710880 4257040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1710880 4077040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1710880 3897040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1710880 3717040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1710880 3537040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1710880 3357040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1710880 3177040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1710880 2997040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1710880 2817040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1710880 2637040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1710880 2457040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1710880 2277040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1710880 2097040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1710880 1917040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1710880 1737040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1710880 1557040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1710880 1377040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1710880 1197040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1710880 1017040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1710880 837040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1710880 657040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1710880 477040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1710880 297040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1710880 117040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1710880 6340 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1530880 5991260 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1530880 5877040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1530880 5697040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1530880 5517040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1530880 5337040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1530880 5157040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1530880 4977040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1530880 4797040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1530880 4617040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1530880 4437040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1530880 4257040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1530880 4077040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1530880 3897040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1530880 3717040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1530880 3537040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1530880 3357040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1530880 3177040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1530880 2997040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1530880 2817040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1530880 2637040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1530880 2457040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1530880 2277040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1530880 2097040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1530880 1917040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1530880 1737040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1530880 1557040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1530880 1377040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1530880 1197040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1530880 1017040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1530880 837040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1530880 657040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1530880 477040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1530880 297040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1530880 117040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1530880 6340 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1350880 5991260 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1350880 5877040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1350880 5697040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1350880 5517040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1350880 5337040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1350880 5157040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1350880 4977040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1350880 4797040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1350880 4617040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1350880 4437040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1350880 4257040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1350880 4077040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1350880 3897040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1350880 3717040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1350880 3537040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1350880 3357040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1350880 3177040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1350880 2997040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1350880 2817040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1350880 2637040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1350880 2457040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1350880 2277040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1350880 2097040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1350880 1917040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1350880 1737040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1350880 1557040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1350880 1377040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1350880 1197040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1350880 1017040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1350880 837040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1350880 657040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1350880 477040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1350880 297040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1350880 117040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1350880 6340 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1170880 5991260 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1170880 5877040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1170880 5697040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1170880 5517040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1170880 5337040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1170880 5157040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1170880 4977040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1170880 4797040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1170880 4617040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1170880 4437040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1170880 4257040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1170880 4077040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1170880 3897040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1170880 3717040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1170880 3537040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1170880 3357040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1170880 3177040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1170880 2997040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1170880 2817040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1170880 2637040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1170880 2457040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1170880 2277040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1170880 2097040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1170880 1917040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1170880 1737040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1170880 1557040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1170880 1377040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1170880 1197040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1170880 1017040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1170880 837040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1170880 657040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1170880 477040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1170880 297040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1170880 117040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1170880 6340 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 990880 5991260 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 990880 5877040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 990880 5697040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 990880 5517040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 990880 5337040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 990880 5157040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 990880 4977040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 990880 4797040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 990880 4617040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 990880 4437040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 990880 4257040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 990880 4077040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 990880 3897040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 990880 3717040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 990880 3537040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 990880 3357040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 990880 3177040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 990880 2997040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 990880 2817040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 990880 2637040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 990880 2457040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 990880 2277040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 990880 2097040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 990880 1917040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 990880 1737040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 990880 1557040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 990880 1377040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 990880 1197040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 990880 1017040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 990880 837040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 990880 657040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 990880 477040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 990880 297040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 990880 117040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 990880 6340 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 810880 5991260 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 810880 5877040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 810880 5697040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 810880 5517040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 810880 5337040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 810880 5157040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 810880 4977040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 810880 4797040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 810880 4617040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 810880 4437040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 810880 4257040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 810880 4077040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 810880 3897040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 810880 3717040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 810880 3537040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 810880 3357040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 810880 3177040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 810880 2997040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 810880 2817040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 810880 2637040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 810880 2457040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 810880 2277040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 810880 2097040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 810880 1917040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 810880 1737040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 810880 1557040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 810880 1377040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 810880 1197040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 810880 1017040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 810880 837040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 810880 657040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 810880 477040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 810880 297040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 810880 117040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 810880 6340 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 630880 5991260 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 630880 5877040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 630880 5697040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 630880 5517040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 630880 5337040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 630880 5157040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 630880 4977040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 630880 4797040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 630880 4617040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 630880 4437040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 630880 4257040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 630880 4077040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 630880 3897040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 630880 3717040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 630880 3537040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 630880 3357040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 630880 3177040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 630880 2997040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 630880 2817040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 630880 2637040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 630880 2457040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 630880 2277040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 630880 2097040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 630880 1917040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 630880 1737040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 630880 1557040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 630880 1377040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 630880 1197040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 630880 1017040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 630880 837040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 630880 657040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 630880 477040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 630880 297040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 630880 117040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 630880 6340 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 450880 5991260 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 450880 5877040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 450880 5697040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 450880 5517040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 450880 5337040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 450880 5157040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 450880 4977040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 450880 4797040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 450880 4617040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 450880 4437040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 450880 4257040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 450880 4077040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 450880 3897040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 450880 3717040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 450880 3537040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 450880 3357040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 450880 3177040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 450880 2997040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 450880 2817040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 450880 2637040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 450880 2457040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 450880 2277040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 450880 2097040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 450880 1917040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 450880 1737040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 450880 1557040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 450880 1377040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 450880 1197040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 450880 1017040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 450880 837040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 450880 657040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 450880 477040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 450880 297040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 450880 117040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 450880 6340 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 270880 5991260 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 270880 5877040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 270880 5697040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 270880 5517040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 270880 5337040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 270880 5157040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 270880 4977040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 270880 4797040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 270880 4617040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 270880 4437040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 270880 4257040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 270880 4077040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 270880 3897040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 270880 3717040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 270880 3537040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 270880 3357040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 270880 3177040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 270880 2997040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 270880 2817040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 270880 2637040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 270880 2457040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 270880 2277040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 270880 2097040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 270880 1917040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 270880 1737040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 270880 1557040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 270880 1377040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 270880 1197040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 270880 1017040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 270880 837040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 270880 657040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 270880 477040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 270880 297040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 270880 117040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 270880 6340 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 90880 5991260 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 90880 5877040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 90880 5697040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 90880 5517040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 90880 5337040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 90880 5157040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 90880 4977040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 90880 4797040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 90880 4617040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 90880 4437040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 90880 4257040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 90880 4077040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 90880 3897040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 90880 3717040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 90880 3537040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 90880 3357040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 90880 3177040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 90880 2997040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 90880 2817040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 90880 2637040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 90880 2457040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 90880 2277040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 90880 2097040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 90880 1917040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 90880 1737040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 90880 1557040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 90880 1377040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 90880 1197040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 90880 1017040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 90880 837040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 90880 657040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 90880 477040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 90880 297040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 90880 117040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 90880 6340 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE RING ( 2980 5991260 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2980 5877040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2980 5697040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2980 5517040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2980 5337040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2980 5157040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2980 4977040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2980 4797040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2980 4617040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2980 4437040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2980 4257040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2980 4077040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2980 3897040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2980 3717040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2980 3537040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2980 3357040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2980 3177040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2980 2997040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2980 2817040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2980 2637040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2980 2457040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2980 2277040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2980 2097040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2980 1917040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2980 1737040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2980 1557040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2980 1377040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2980 1197040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2980 1017040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2980 837040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2980 657040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2980 477040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2980 297040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2980 117040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE RING ( 2980 6340 ) via4_5_6200_6200_6_6_1040_1040 ;
+END SPECIALNETS
+END DESIGN
diff --git a/openlane/user_project_wrapper/macro.cfg b/openlane/user_project_wrapper/macro.cfg
new file mode 100644
index 0000000..a7365ab
--- /dev/null
+++ b/openlane/user_project_wrapper/macro.cfg
@@ -0,0 +1 @@
+mprj 1175 1690 N
diff --git a/openlane/user_project_wrapper/pin_order.cfg b/openlane/user_project_wrapper/pin_order.cfg
new file mode 100644
index 0000000..c9632da
--- /dev/null
+++ b/openlane/user_project_wrapper/pin_order.cfg
@@ -0,0 +1,156 @@
+#BUS_SORT
+#NR
+analog_io\[8\]
+io_in\[15\]
+io_out\[15\]
+io_oeb\[15\]
+analog_io\[9\]
+io_in\[16\]
+io_out\[16\]
+io_oeb\[16\]
+analog_io\[10\]
+io_in\[17\]
+io_out\[17\]
+io_oeb\[17\]
+analog_io\[11\]
+io_in\[18\]
+io_out\[18\]
+io_oeb\[18\]
+analog_io\[12\]
+io_in\[19\]
+io_out\[19\]
+io_oeb\[19\]
+analog_io\[13\]
+io_in\[20\]
+io_out\[20\]
+io_oeb\[20\]
+analog_io\[14\]
+io_in\[21\]
+io_out\[21\]
+io_oeb\[21\]
+analog_io\[15\]
+io_in\[22\]
+io_out\[22\]
+io_oeb\[22\]
+analog_io\[16\]
+io_in\[23\]
+io_out\[23\]
+io_oeb\[23\]
+
+#S
+wb_.*
+wbs_.*
+la_.*
+user_clock2
+user_irq.*
+
+#E
+io_in\[0\]
+io_out\[0\]
+io_oeb\[0\]
+io_in\[1\]
+io_out\[1\]
+io_oeb\[1\]
+io_in\[2\]
+io_out\[2\]
+io_oeb\[2\]
+io_in\[3\]
+io_out\[3\]
+io_oeb\[3\]
+io_in\[4\]
+io_out\[4\]
+io_oeb\[4\]
+io_in\[5\]
+io_out\[5\]
+io_oeb\[5\]
+io_in\[6\]
+io_out\[6\]
+io_oeb\[6\]
+analog_io\[0\]
+io_in\[7\]
+io_out\[7\]
+io_oeb\[7\]
+analog_io\[1\]
+io_in\[8\]
+io_out\[8\]
+io_oeb\[8\]
+analog_io\[2\]
+io_in\[9\]
+io_out\[9\]
+io_oeb\[9\]
+analog_io\[3\]
+io_in\[10\]
+io_out\[10\]
+io_oeb\[10\]
+analog_io\[4\]
+io_in\[11\]
+io_out\[11\]
+io_oeb\[11\]
+analog_io\[5\]
+io_in\[12\]
+io_out\[12\]
+io_oeb\[12\]
+analog_io\[6\]
+io_in\[13\]
+io_out\[13\]
+io_oeb\[13\]
+analog_io\[7\]
+io_in\[14\]
+io_out\[14\]
+io_oeb\[14\]
+
+#WR
+analog_io\[17\]
+io_in\[24\]
+io_out\[24\]
+io_oeb\[24\]
+analog_io\[18\]
+io_in\[25\]
+io_out\[25\]
+io_oeb\[25\]
+analog_io\[19\]
+io_in\[26\]
+io_out\[26\]
+io_oeb\[26\]
+analog_io\[20\]
+io_in\[27\]
+io_out\[27\]
+io_oeb\[27\]
+analog_io\[21\]
+io_in\[28\]
+io_out\[28\]
+io_oeb\[28\]
+analog_io\[22\]
+io_in\[29\]
+io_out\[29\]
+io_oeb\[29\]
+analog_io\[23\]
+io_in\[30\]
+io_out\[30\]
+io_oeb\[30\]
+analog_io\[24\]
+io_in\[31\]
+io_out\[31\]
+io_oeb\[31\]
+analog_io\[25\]
+io_in\[32\]
+io_out\[32\]
+io_oeb\[32\]
+analog_io\[26\]
+io_in\[33\]
+io_out\[33\]
+io_oeb\[33\]
+analog_io\[27\]
+io_in\[34\]
+io_out\[34\]
+io_oeb\[34\]
+analog_io\[28\]
+io_in\[35\]
+io_out\[35\]
+io_oeb\[35\]
+io_in\[36\]
+io_out\[36\]
+io_oeb\[36\]
+io_in\[37\]
+io_out\[37\]
+io_oeb\[37\]
\ No newline at end of file
diff --git a/sdf/efuse_ctrl.sdf.gz b/sdf/efuse_ctrl.sdf.gz
new file mode 100644
index 0000000..590e87e
--- /dev/null
+++ b/sdf/efuse_ctrl.sdf.gz
Binary files differ
diff --git a/sdf/fpga_struct_block.sdf.gz b/sdf/fpga_struct_block.sdf.gz
new file mode 100644
index 0000000..811a7b5
--- /dev/null
+++ b/sdf/fpga_struct_block.sdf.gz
Binary files differ
diff --git a/sdf/user_project_wrapper.sdf.gz b/sdf/user_project_wrapper.sdf.gz
new file mode 100644
index 0000000..75f8c79
--- /dev/null
+++ b/sdf/user_project_wrapper.sdf.gz
Binary files differ
diff --git a/verilog/dv/README.md b/verilog/dv/README.md
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/verilog/dv/README.md
diff --git a/verilog/gl/efuse_ctrl.v.gz b/verilog/gl/efuse_ctrl.v.gz
new file mode 100644
index 0000000..227b046
--- /dev/null
+++ b/verilog/gl/efuse_ctrl.v.gz
Binary files differ
diff --git a/verilog/gl/fpga_struct_block.v.gz b/verilog/gl/fpga_struct_block.v.gz
new file mode 100644
index 0000000..c8471cb
--- /dev/null
+++ b/verilog/gl/fpga_struct_block.v.gz
Binary files differ
diff --git a/verilog/gl/user_project_wrapper.v.gz b/verilog/gl/user_project_wrapper.v.gz
new file mode 100644
index 0000000..b09c8c9
--- /dev/null
+++ b/verilog/gl/user_project_wrapper.v.gz
Binary files differ
diff --git a/verilog/includes/includes.gl+sdf.caravel_user_project b/verilog/includes/includes.gl+sdf.caravel_user_project
new file mode 100644
index 0000000..284a97c
--- /dev/null
+++ b/verilog/includes/includes.gl+sdf.caravel_user_project
@@ -0,0 +1,3 @@
+// Caravel user project includes
+$USER_PROJECT_VERILOG/gl/user_project_wrapper.v
+$USER_PROJECT_VERILOG/gl/user_proj_example.v
diff --git a/verilog/includes/includes.gl.caravel_user_project b/verilog/includes/includes.gl.caravel_user_project
new file mode 100644
index 0000000..f5047d5
--- /dev/null
+++ b/verilog/includes/includes.gl.caravel_user_project
@@ -0,0 +1,3 @@
+# Caravel user project includes
+-v $(USER_PROJECT_VERILOG)/gl/user_project_wrapper.v
+-v $(USER_PROJECT_VERILOG)/gl/user_proj_example.v
diff --git a/verilog/includes/includes.rtl.caravel_user_project b/verilog/includes/includes.rtl.caravel_user_project
new file mode 100644
index 0000000..31ab09b
--- /dev/null
+++ b/verilog/includes/includes.rtl.caravel_user_project
@@ -0,0 +1,5 @@
+# Caravel user project includes
+-v $(USER_PROJECT_VERILOG)/rtl/user_project_wrapper.v
+-v $(USER_PROJECT_VERILOG)/rtl/user_proj_example.v
+
+
\ No newline at end of file
diff --git a/verilog/rtl/ariel_fpga_top_fromvhdl.v b/verilog/rtl/ariel_fpga_top_fromvhdl.v
new file mode 100644
index 0000000..fd30de2
--- /dev/null
+++ b/verilog/rtl/ariel_fpga_top_fromvhdl.v
@@ -0,0 +1,3294 @@
+/* Generated by Yosys 0.22 (git sha1 f109fa3d4, gcc 10.2.1-6 -fPIC -Os) */
+
+(* top = 1 *)
+module ariel_fpga_top(wb_clk_i, wb_rst_i, wbs_stb_i, wbs_cyc_i, wbs_we_i, wbs_dat_i, wbs_adr_i, la_data_in, la_oenb, io_in, user_clock2, wbs_ack_o, wbs_dat_o, la_data_out, io_out, io_oeb, user_irq);
+ wire _00_;
+ wire [31:0] _01_;
+ wire _02_;
+ wire [31:0] _03_;
+ wire [31:0] _04_;
+ wire _05_;
+ wire [31:0] _06_;
+ wire [31:0] _07_;
+ wire _08_;
+ wire [31:0] _09_;
+ wire [31:0] _10_;
+ wire [31:0] _11_;
+ wire _12_;
+ wire [31:0] _13_;
+ wire [31:0] _14_;
+ wire [7:0] _15_;
+ wire _16_;
+ wire _17_;
+ wire _18_;
+ wire _19_;
+ wire _20_;
+ wire [143:0] _21_;
+ wire [401:0] _22_;
+ wire _23_;
+ wire [143:0] _24_;
+ wire [1:0] _25_;
+ wire [6:0] _26_;
+ wire [1:0] _27_;
+ wire [143:0] _28_;
+ wire _29_;
+ wire [31:0] _30_;
+ wire [31:0] block_data;
+ wire [31:0] block_data_out;
+ wire config_block_clk;
+ wire [3:0] config_block_i;
+ wire [1:0] config_block_o;
+ wire config_hrnode_clk;
+ wire [3:0] config_hrnode_i;
+ wire [1:0] config_hrnode_o;
+ wire config_vrnode_clk;
+ wire [13:0] config_vrnode_i;
+ wire [6:0] config_vrnode_o;
+ wire [31:0] fpga_rst;
+ wire [31:0] fw_tap_bus;
+ wire [31:0] hrnode_data;
+ wire [31:0] hrnode_data_out;
+ wire [143:0] inputs_i;
+ wire [143:0] inputs_i_buf;
+ input [37:0] io_in;
+ wire [37:0] io_in;
+ output [37:0] io_oeb;
+ wire [37:0] io_oeb;
+ output [37:0] io_out;
+ wire [37:0] io_out;
+ input [63:0] la_data_in;
+ wire [63:0] la_data_in;
+ output [63:0] la_data_out;
+ wire [63:0] la_data_out;
+ input [63:0] la_oenb;
+ wire [63:0] la_oenb;
+ wire [143:0] outputs_o;
+ wire [143:0] outputs_o_buf;
+ input user_clock2;
+ wire user_clock2;
+ output [2:0] user_irq;
+ wire [2:0] user_irq;
+ wire [31:0] vrnode_data;
+ wire [31:0] vrnode_data_out;
+ wire [401:0] \wb_arbiter_inst:11 ;
+ wire [32:0] \wb_arbiter_inst:9 ;
+ input wb_clk_i;
+ wire wb_clk_i;
+ wire [66:0] wb_from_caravel;
+ wire [197:0] wb_i_bottom;
+ wire [401:0] wb_o_bottom;
+ input wb_rst_i;
+ wire wb_rst_i;
+ wire [32:0] wb_to_caravel;
+ output wbs_ack_o;
+ wire wbs_ack_o;
+ input [31:0] wbs_adr_i;
+ wire [31:0] wbs_adr_i;
+ input wbs_cyc_i;
+ wire wbs_cyc_i;
+ input [31:0] wbs_dat_i;
+ wire [31:0] wbs_dat_i;
+ output [31:0] wbs_dat_o;
+ wire [31:0] wbs_dat_o;
+ input wbs_stb_i;
+ wire wbs_stb_i;
+ input wbs_we_i;
+ wire wbs_we_i;
+ assign _20_ = ~ fpga_rst[1];
+ assign _21_ = _20_ ? inputs_i : { fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2] };
+ assign _23_ = ~ fpga_rst[1];
+ assign _24_ = _23_ ? outputs_o_buf : { fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2], fpga_rst[2] };
+ wb_register32_14ace0e78520e59d309b4c0f3f681129bf7f2ebe block_write_fw_reg_inst (
+ .reg_i(block_data_out),
+ .reg_o(_01_),
+ .wb_clk_i(wb_clk_i),
+ .\wb_i.adr_i (wb_o_bottom[66:35]),
+ .\wb_i.cyc_i (wb_o_bottom[1]),
+ .\wb_i.dat_i (wb_o_bottom[34:3]),
+ .\wb_i.stb_i (wb_o_bottom[0]),
+ .\wb_i.we_i (wb_o_bottom[2]),
+ .\wb_o.ack_o (_29_),
+ .\wb_o.dat_o (_30_),
+ .wb_rst_i(wb_rst_i)
+ );
+ fpga_tech_clkbuffer config_block_clk_buf (
+ .i(fw_tap_bus[0]),
+ .z(_17_)
+ );
+ fpga_tech_clkbuffer config_hrnode_clk_buf (
+ .i(fw_tap_bus[2]),
+ .z(_19_)
+ );
+ fpga_tech_clkbuffer config_vrnode_clk_buf (
+ .i(fw_tap_bus[1]),
+ .z(_18_)
+ );
+ efuse_ctrl efuse (
+ .wb_ack_o(_16_),
+ .wb_adr_i(wb_o_bottom[379:370]),
+ .wb_clk_i(wb_clk_i),
+ .wb_cyc_i(wb_o_bottom[336]),
+ .wb_dat_i(wb_o_bottom[345:338]),
+ .wb_dat_o(_15_),
+ .wb_rst_i(wb_rst_i),
+ .wb_sel_i(2'h0),
+ .wb_stb_i(wb_o_bottom[335]),
+ .wb_we_i(wb_o_bottom[337])
+ );
+ wb_register32_81b45b9a32734d4367912d54c45d3716474431dc fabric_reset_reg_inst (
+ .reg_i(32'd0),
+ .reg_o(_10_),
+ .wb_clk_i(wb_clk_i),
+ .\wb_i.adr_i (wb_o_bottom[267:236]),
+ .\wb_i.cyc_i (wb_o_bottom[202]),
+ .\wb_i.dat_i (wb_o_bottom[235:204]),
+ .\wb_i.stb_i (wb_o_bottom[201]),
+ .\wb_i.we_i (wb_o_bottom[203]),
+ .\wb_o.ack_o (_08_),
+ .\wb_o.dat_o (_09_),
+ .wb_rst_i(wb_rst_i)
+ );
+ fpga_fabric_4_9_144_144 fpga_fabric_inst (
+ .clk_i(wb_clk_i),
+ .config_block_i(config_block_i),
+ .config_block_o(_25_),
+ .config_hrnode_i(config_hrnode_i),
+ .config_hrnode_o(_27_),
+ .config_vrnode_i(config_vrnode_i),
+ .config_vrnode_o(_26_),
+ .glb_rst_i(fpga_rst[0]),
+ .inputs_i(inputs_i_buf),
+ .outputs_o(_28_)
+ );
+ wb_register32_14ace0e78520e59d309b4c0f3f681129bf7f2ebe hrnode_write_fw_reg_inst (
+ .reg_i(hrnode_data_out),
+ .reg_o(_07_),
+ .wb_clk_i(wb_clk_i),
+ .\wb_i.adr_i (wb_o_bottom[200:169]),
+ .\wb_i.cyc_i (wb_o_bottom[135]),
+ .\wb_i.dat_i (wb_o_bottom[168:137]),
+ .\wb_i.stb_i (wb_o_bottom[134]),
+ .\wb_i.we_i (wb_o_bottom[136]),
+ .\wb_o.ack_o (_05_),
+ .\wb_o.dat_o (_06_),
+ .wb_rst_i(wb_rst_i)
+ );
+ wb_register32_91a7f356ca6ce41b6122bd41e60c1f2eb8f0f0e3 tap_write_fw_reg_inst (
+ .reg_i(32'd0),
+ .reg_o(_14_),
+ .wb_clk_i(wb_clk_i),
+ .\wb_i.adr_i (wb_o_bottom[334:303]),
+ .\wb_i.cyc_i (wb_o_bottom[269]),
+ .\wb_i.dat_i (wb_o_bottom[302:271]),
+ .\wb_i.stb_i (wb_o_bottom[268]),
+ .\wb_i.we_i (wb_o_bottom[270]),
+ .\wb_o.ack_o (_12_),
+ .\wb_o.dat_o (_13_),
+ .wb_rst_i(wb_rst_i)
+ );
+ wb_register32_14ace0e78520e59d309b4c0f3f681129bf7f2ebe vrnode_write_fw_reg_inst (
+ .reg_i(vrnode_data_out),
+ .reg_o(_04_),
+ .wb_clk_i(wb_clk_i),
+ .\wb_i.adr_i (wb_o_bottom[133:102]),
+ .\wb_i.cyc_i (wb_o_bottom[68]),
+ .\wb_i.dat_i (wb_o_bottom[101:70]),
+ .\wb_i.stb_i (wb_o_bottom[67]),
+ .\wb_i.we_i (wb_o_bottom[69]),
+ .\wb_o.ack_o (_02_),
+ .\wb_o.dat_o (_03_),
+ .wb_rst_i(wb_rst_i)
+ );
+ wb_arbiter_sync_6 wb_arbiter_inst (
+ .addr_map(192'h300200003001e0003001a000300120003001100030010000),
+ .wb_clk_i(wb_clk_i),
+ .wb_i_bottom(wb_i_bottom),
+ .\wb_i_up.adr_i (wb_from_caravel[66:35]),
+ .\wb_i_up.cyc_i (wb_from_caravel[1]),
+ .\wb_i_up.dat_i (wb_from_caravel[34:3]),
+ .\wb_i_up.stb_i (wb_from_caravel[0]),
+ .\wb_i_up.we_i (wb_from_caravel[2]),
+ .wb_o_bottom(_22_),
+ .\wb_o_up.ack_o (_00_),
+ .\wb_o_up.dat_o (_11_),
+ .wb_rst_i(wb_rst_i)
+ );
+ assign block_data = _01_;
+ assign block_data_out = { 30'h00000000, config_block_o };
+ assign vrnode_data = _04_;
+ assign vrnode_data_out = { 25'h0000000, config_vrnode_o };
+ assign hrnode_data = _07_;
+ assign hrnode_data_out = { 30'h00000000, config_hrnode_o };
+ assign fw_tap_bus = _14_;
+ assign fpga_rst = _10_;
+ assign config_block_clk = _17_;
+ assign config_vrnode_clk = _18_;
+ assign config_hrnode_clk = _19_;
+ assign config_block_i = { block_data[1], config_block_clk, block_data[0], config_block_clk };
+ assign config_block_o = _25_;
+ assign config_vrnode_i = { vrnode_data[6], config_vrnode_clk, vrnode_data[5], config_vrnode_clk, vrnode_data[4], config_vrnode_clk, vrnode_data[3], config_vrnode_clk, vrnode_data[2], config_vrnode_clk, vrnode_data[1], config_vrnode_clk, vrnode_data[0], config_vrnode_clk };
+ assign config_vrnode_o = _26_;
+ assign config_hrnode_i = { hrnode_data[1], config_hrnode_clk, hrnode_data[0], config_hrnode_clk };
+ assign config_hrnode_o = _27_;
+ assign inputs_i = 144'h000000000000000000000000000000000000;
+ assign outputs_o = _24_;
+ assign outputs_o_buf = _28_;
+ assign inputs_i_buf = _21_;
+ assign wb_from_caravel = { wbs_adr_i, wbs_dat_i, wbs_we_i, wbs_cyc_i, wbs_stb_i };
+ assign wb_to_caravel = \wb_arbiter_inst:9 ;
+ assign wb_i_bottom = { 24'hzzzzzz, _15_, _16_, _13_, _12_, _09_, _08_, _06_, _05_, _03_, _02_, _30_, _29_ };
+ assign wb_o_bottom = \wb_arbiter_inst:11 ;
+ assign \wb_arbiter_inst:9 = { _11_, _00_ };
+ assign \wb_arbiter_inst:11 = _22_;
+ assign wbs_ack_o = wb_to_caravel[0];
+ assign wbs_dat_o = wb_to_caravel[32:1];
+ assign la_data_out = 64'h0000000000000000;
+ assign io_out = outputs_o[37:0];
+ assign io_oeb = 38'hzzzzzzzzzz;
+ assign user_irq = 3'hz;
+endmodule
+
+module fpga_cfg_shiftreg_2(config_clk_i, config_ena_i, config_shift_i, config_shift_o, config_o);
+ reg [1:0] _0_;
+ input config_clk_i;
+ wire config_clk_i;
+ wire [1:0] config_data;
+ input config_ena_i;
+ wire config_ena_i;
+ output [1:0] config_o;
+ wire [1:0] config_o;
+ input config_shift_i;
+ wire config_shift_i;
+ output config_shift_o;
+ wire config_shift_o;
+ always @(posedge config_clk_i)
+ _0_ <= { config_shift_i, config_data[1] };
+ assign config_data = _0_;
+ assign config_shift_o = config_data[0];
+ assign config_o = config_data;
+endmodule
+
+module fpga_cfg_shiftreg_48(config_clk_i, config_ena_i, config_shift_i, config_shift_o, config_o);
+ reg [47:0] _0_;
+ input config_clk_i;
+ wire config_clk_i;
+ wire [47:0] config_data;
+ input config_ena_i;
+ wire config_ena_i;
+ output [47:0] config_o;
+ wire [47:0] config_o;
+ input config_shift_i;
+ wire config_shift_i;
+ output config_shift_o;
+ wire config_shift_o;
+ always @(posedge config_clk_i)
+ _0_ <= { config_shift_i, config_data[47:1] };
+ assign config_data = _0_;
+ assign config_shift_o = config_data[0];
+ assign config_o = config_data;
+endmodule
+
+module fpga_fabric_4_9_144_144(clk_i, glb_rst_i, config_block_i, config_vrnode_i, config_hrnode_i, inputs_i, config_block_o, config_vrnode_o, config_hrnode_o, outputs_o);
+ wire _000_;
+ wire _001_;
+ wire [7:0] _002_;
+ wire _003_;
+ wire [7:0] _004_;
+ wire _005_;
+ wire [7:0] _006_;
+ wire _007_;
+ wire [7:0] _008_;
+ wire _009_;
+ wire [7:0] _010_;
+ wire _011_;
+ wire [7:0] _012_;
+ wire _013_;
+ wire [7:0] _014_;
+ wire _015_;
+ wire [7:0] _016_;
+ wire _017_;
+ wire [7:0] _018_;
+ wire _019_;
+ wire [7:0] _020_;
+ wire _021_;
+ wire [7:0] _022_;
+ wire _023_;
+ wire [7:0] _024_;
+ wire _025_;
+ wire [7:0] _026_;
+ wire _027_;
+ wire [7:0] _028_;
+ wire _029_;
+ wire [7:0] _030_;
+ wire _031_;
+ wire [15:0] _032_;
+ wire _033_;
+ wire [15:0] _034_;
+ wire _035_;
+ wire [7:0] _036_;
+ wire _037_;
+ wire [15:0] _038_;
+ wire _039_;
+ wire [15:0] _040_;
+ wire _041_;
+ wire [7:0] _042_;
+ wire _043_;
+ wire [15:0] _044_;
+ wire _045_;
+ wire [15:0] _046_;
+ wire _047_;
+ wire [7:0] _048_;
+ wire _049_;
+ wire [15:0] _050_;
+ wire _051_;
+ wire [15:0] _052_;
+ wire _053_;
+ wire [7:0] _054_;
+ wire _055_;
+ wire [15:0] _056_;
+ wire _057_;
+ wire [15:0] _058_;
+ wire _059_;
+ wire [7:0] _060_;
+ wire _061_;
+ wire [15:0] _062_;
+ wire _063_;
+ wire [15:0] _064_;
+ wire _065_;
+ wire [7:0] _066_;
+ wire _067_;
+ wire [15:0] _068_;
+ wire _069_;
+ wire [15:0] _070_;
+ wire _071_;
+ wire [15:0] _072_;
+ wire _073_;
+ wire [15:0] _074_;
+ wire _075_;
+ wire [15:0] _076_;
+ wire _077_;
+ wire [15:0] _078_;
+ wire _079_;
+ wire [15:0] _080_;
+ wire _081_;
+ wire [15:0] _082_;
+ wire _083_;
+ wire [15:0] _084_;
+ wire _085_;
+ wire [15:0] _086_;
+ wire _087_;
+ wire [15:0] _088_;
+ wire _089_;
+ wire [15:0] _090_;
+ wire _091_;
+ wire [15:0] _092_;
+ wire _093_;
+ wire [15:0] _094_;
+ wire _095_;
+ wire [15:0] _096_;
+ wire _097_;
+ wire [15:0] _098_;
+ wire _099_;
+ wire [15:0] _100_;
+ wire _101_;
+ wire [7:0] _102_;
+ wire _103_;
+ wire [15:0] _104_;
+ wire _105_;
+ wire [15:0] _106_;
+ wire _107_;
+ wire [7:0] _108_;
+ wire _109_;
+ wire [15:0] _110_;
+ wire _111_;
+ wire [15:0] _112_;
+ wire _113_;
+ wire [7:0] _114_;
+ wire _115_;
+ wire [15:0] _116_;
+ wire _117_;
+ wire [15:0] _118_;
+ wire _119_;
+ wire [7:0] _120_;
+ wire _121_;
+ wire [15:0] _122_;
+ wire _123_;
+ wire [15:0] _124_;
+ wire _125_;
+ wire [7:0] _126_;
+ wire _127_;
+ wire [15:0] _128_;
+ wire _129_;
+ wire [15:0] _130_;
+ wire _131_;
+ wire [7:0] _132_;
+ wire _133_;
+ wire [15:0] _134_;
+ wire _135_;
+ wire [15:0] _136_;
+ wire _137_;
+ wire [7:0] _138_;
+ wire _139_;
+ wire [15:0] _140_;
+ wire _141_;
+ wire [7:0] _142_;
+ wire _143_;
+ wire [15:0] _144_;
+ wire _145_;
+ wire [15:0] _146_;
+ wire _147_;
+ wire [15:0] _148_;
+ wire _149_;
+ wire [15:0] _150_;
+ wire _151_;
+ wire [15:0] _152_;
+ wire _153_;
+ wire [15:0] _154_;
+ wire _155_;
+ wire [15:0] _156_;
+ wire _157_;
+ wire [15:0] _158_;
+ wire _159_;
+ wire [15:0] _160_;
+ wire _161_;
+ wire [15:0] _162_;
+ wire _163_;
+ wire [15:0] _164_;
+ wire _165_;
+ wire [15:0] _166_;
+ wire _167_;
+ wire [15:0] _168_;
+ wire _169_;
+ wire [15:0] _170_;
+ wire _171_;
+ wire [15:0] _172_;
+ wire _173_;
+ wire [7:0] _174_;
+ wire _175_;
+ wire [15:0] _176_;
+ wire _177_;
+ wire [7:0] _178_;
+ wire _179_;
+ wire [15:0] _180_;
+ wire _181_;
+ wire [15:0] _182_;
+ wire _183_;
+ wire [15:0] _184_;
+ wire _185_;
+ wire [15:0] _186_;
+ wire _187_;
+ wire [15:0] _188_;
+ wire _189_;
+ wire [15:0] _190_;
+ wire _191_;
+ wire [15:0] _192_;
+ wire _193_;
+ wire [15:0] _194_;
+ wire _195_;
+ wire [15:0] _196_;
+ wire _197_;
+ wire [15:0] _198_;
+ wire _199_;
+ wire [15:0] _200_;
+ wire _201_;
+ wire [15:0] _202_;
+ wire _203_;
+ wire [15:0] _204_;
+ wire _205_;
+ wire [15:0] _206_;
+ wire _207_;
+ wire [15:0] _208_;
+ wire _209_;
+ wire [7:0] _210_;
+ wire _211_;
+ wire [15:0] _212_;
+ wire [15:0] block_cfg_shift_chain;
+ wire [111:0] block_out;
+ input clk_i;
+ wire clk_i;
+ input [3:0] config_block_i;
+ wire [3:0] config_block_i;
+ output [1:0] config_block_o;
+ wire [1:0] config_block_o;
+ input [3:0] config_hrnode_i;
+ wire [3:0] config_hrnode_i;
+ output [1:0] config_hrnode_o;
+ wire [1:0] config_hrnode_o;
+ input [13:0] config_vrnode_i;
+ wire [13:0] config_vrnode_i;
+ output [6:0] config_vrnode_o;
+ wire [6:0] config_vrnode_o;
+ wire [335:0] down_tracks_fwd;
+ wire [2351:0] down_tracks_in;
+ wire [335:0] down_tracks_out;
+ input glb_rst_i;
+ wire glb_rst_i;
+ wire glb_rstn;
+ wire \horizontal_routing_network_x:1.horizontal_routing_network_y:1.routing_node_left:31081 ;
+ wire [15:0] \horizontal_routing_network_x:1.horizontal_routing_network_y:1.routing_node_left:31083 ;
+ wire \horizontal_routing_network_x:1.horizontal_routing_network_y:1.routing_node_right:31091 ;
+ wire [15:0] \horizontal_routing_network_x:1.horizontal_routing_network_y:1.routing_node_right:31093 ;
+ wire \horizontal_routing_network_x:1.horizontal_routing_network_y:2.routing_node_left:32223 ;
+ wire [15:0] \horizontal_routing_network_x:1.horizontal_routing_network_y:2.routing_node_left:32225 ;
+ wire \horizontal_routing_network_x:1.horizontal_routing_network_y:2.routing_node_right:32233 ;
+ wire [15:0] \horizontal_routing_network_x:1.horizontal_routing_network_y:2.routing_node_right:32235 ;
+ wire \horizontal_routing_network_x:1.horizontal_routing_network_y:3.routing_node_left:33365 ;
+ wire [15:0] \horizontal_routing_network_x:1.horizontal_routing_network_y:3.routing_node_left:33367 ;
+ wire \horizontal_routing_network_x:1.horizontal_routing_network_y:3.routing_node_right:33375 ;
+ wire [15:0] \horizontal_routing_network_x:1.horizontal_routing_network_y:3.routing_node_right:33377 ;
+ wire \horizontal_routing_network_x:1.horizontal_routing_network_y:4.routing_node_left:34507 ;
+ wire [15:0] \horizontal_routing_network_x:1.horizontal_routing_network_y:4.routing_node_left:34509 ;
+ wire \horizontal_routing_network_x:1.horizontal_routing_network_y:4.routing_node_right:34517 ;
+ wire [15:0] \horizontal_routing_network_x:1.horizontal_routing_network_y:4.routing_node_right:34519 ;
+ wire \horizontal_routing_network_x:1.horizontal_routing_network_y:5.routing_node_left:35649 ;
+ wire [15:0] \horizontal_routing_network_x:1.horizontal_routing_network_y:5.routing_node_left:35651 ;
+ wire \horizontal_routing_network_x:1.horizontal_routing_network_y:5.routing_node_right:35659 ;
+ wire [15:0] \horizontal_routing_network_x:1.horizontal_routing_network_y:5.routing_node_right:35661 ;
+ wire \horizontal_routing_network_x:1.horizontal_routing_network_y:6.routing_node_left:36791 ;
+ wire [15:0] \horizontal_routing_network_x:1.horizontal_routing_network_y:6.routing_node_left:36793 ;
+ wire \horizontal_routing_network_x:1.horizontal_routing_network_y:6.routing_node_right:36801 ;
+ wire [15:0] \horizontal_routing_network_x:1.horizontal_routing_network_y:6.routing_node_right:36803 ;
+ wire \horizontal_routing_network_x:1.horizontal_routing_network_y:7.routing_node_left:37933 ;
+ wire [15:0] \horizontal_routing_network_x:1.horizontal_routing_network_y:7.routing_node_left:37935 ;
+ wire \horizontal_routing_network_x:1.horizontal_routing_network_y:7.routing_node_right:37943 ;
+ wire [15:0] \horizontal_routing_network_x:1.horizontal_routing_network_y:7.routing_node_right:37945 ;
+ wire \horizontal_routing_network_x:1.horizontal_routing_network_y:8.routing_node_left:37955 ;
+ wire [15:0] \horizontal_routing_network_x:1.horizontal_routing_network_y:8.routing_node_left:37957 ;
+ wire \horizontal_routing_network_x:1.horizontal_routing_network_y:8.routing_node_right:39418 ;
+ wire [15:0] \horizontal_routing_network_x:1.horizontal_routing_network_y:8.routing_node_right:39420 ;
+ wire \horizontal_routing_network_x:2.horizontal_routing_network_y:1.routing_node_left:40886 ;
+ wire [15:0] \horizontal_routing_network_x:2.horizontal_routing_network_y:1.routing_node_left:40888 ;
+ wire \horizontal_routing_network_x:2.horizontal_routing_network_y:1.routing_node_right:40896 ;
+ wire [15:0] \horizontal_routing_network_x:2.horizontal_routing_network_y:1.routing_node_right:40898 ;
+ wire \horizontal_routing_network_x:2.horizontal_routing_network_y:2.routing_node_left:42028 ;
+ wire [15:0] \horizontal_routing_network_x:2.horizontal_routing_network_y:2.routing_node_left:42030 ;
+ wire \horizontal_routing_network_x:2.horizontal_routing_network_y:2.routing_node_right:42038 ;
+ wire [15:0] \horizontal_routing_network_x:2.horizontal_routing_network_y:2.routing_node_right:42040 ;
+ wire \horizontal_routing_network_x:2.horizontal_routing_network_y:3.routing_node_left:43170 ;
+ wire [15:0] \horizontal_routing_network_x:2.horizontal_routing_network_y:3.routing_node_left:43172 ;
+ wire \horizontal_routing_network_x:2.horizontal_routing_network_y:3.routing_node_right:43180 ;
+ wire [15:0] \horizontal_routing_network_x:2.horizontal_routing_network_y:3.routing_node_right:43182 ;
+ wire \horizontal_routing_network_x:2.horizontal_routing_network_y:4.routing_node_left:44312 ;
+ wire [15:0] \horizontal_routing_network_x:2.horizontal_routing_network_y:4.routing_node_left:44314 ;
+ wire \horizontal_routing_network_x:2.horizontal_routing_network_y:4.routing_node_right:44322 ;
+ wire [15:0] \horizontal_routing_network_x:2.horizontal_routing_network_y:4.routing_node_right:44324 ;
+ wire \horizontal_routing_network_x:2.horizontal_routing_network_y:5.routing_node_left:45454 ;
+ wire [15:0] \horizontal_routing_network_x:2.horizontal_routing_network_y:5.routing_node_left:45456 ;
+ wire \horizontal_routing_network_x:2.horizontal_routing_network_y:5.routing_node_right:45464 ;
+ wire [15:0] \horizontal_routing_network_x:2.horizontal_routing_network_y:5.routing_node_right:45466 ;
+ wire \horizontal_routing_network_x:2.horizontal_routing_network_y:6.routing_node_left:46596 ;
+ wire [15:0] \horizontal_routing_network_x:2.horizontal_routing_network_y:6.routing_node_left:46598 ;
+ wire \horizontal_routing_network_x:2.horizontal_routing_network_y:6.routing_node_right:46606 ;
+ wire [15:0] \horizontal_routing_network_x:2.horizontal_routing_network_y:6.routing_node_right:46608 ;
+ wire \horizontal_routing_network_x:2.horizontal_routing_network_y:7.routing_node_left:47738 ;
+ wire [15:0] \horizontal_routing_network_x:2.horizontal_routing_network_y:7.routing_node_left:47740 ;
+ wire \horizontal_routing_network_x:2.horizontal_routing_network_y:7.routing_node_right:47748 ;
+ wire [15:0] \horizontal_routing_network_x:2.horizontal_routing_network_y:7.routing_node_right:47750 ;
+ wire \horizontal_routing_network_x:2.horizontal_routing_network_y:8.routing_node_left:47760 ;
+ wire [15:0] \horizontal_routing_network_x:2.horizontal_routing_network_y:8.routing_node_left:47762 ;
+ wire \horizontal_routing_network_x:2.horizontal_routing_network_y:8.routing_node_right:49223 ;
+ wire [15:0] \horizontal_routing_network_x:2.horizontal_routing_network_y:8.routing_node_right:49225 ;
+ wire [37:0] hrnode_cfg_shift_chain;
+ input [143:0] inputs_i;
+ wire [143:0] inputs_i;
+ wire [255:0] left_tracks_fwd;
+ wire [1791:0] left_tracks_in;
+ wire [255:0] left_tracks_out;
+ output [143:0] outputs_o;
+ wire [143:0] outputs_o;
+ wire [255:0] right_tracks_fwd;
+ wire [1791:0] right_tracks_in;
+ wire [255:0] right_tracks_out;
+ wire [335:0] up_tracks_fwd;
+ wire [2351:0] up_tracks_in;
+ wire [335:0] up_tracks_out;
+ wire \vertical_routing_network_x:1.vertical_routing_network_y:1.routing_node_down:2426 ;
+ wire [15:0] \vertical_routing_network_x:1.vertical_routing_network_y:1.routing_node_down:2428 ;
+ wire \vertical_routing_network_x:1.vertical_routing_network_y:1.routing_node_up:2416 ;
+ wire [15:0] \vertical_routing_network_x:1.vertical_routing_network_y:1.routing_node_up:2418 ;
+ wire \vertical_routing_network_x:1.vertical_routing_network_y:2.routing_node_down:3904 ;
+ wire [15:0] \vertical_routing_network_x:1.vertical_routing_network_y:2.routing_node_down:3906 ;
+ wire \vertical_routing_network_x:1.vertical_routing_network_y:2.routing_node_up:3894 ;
+ wire [15:0] \vertical_routing_network_x:1.vertical_routing_network_y:2.routing_node_up:3896 ;
+ wire \vertical_routing_network_x:1.vertical_routing_network_y:3.routing_node_down:5382 ;
+ wire [15:0] \vertical_routing_network_x:1.vertical_routing_network_y:3.routing_node_down:5384 ;
+ wire \vertical_routing_network_x:1.vertical_routing_network_y:3.routing_node_up:5372 ;
+ wire [15:0] \vertical_routing_network_x:1.vertical_routing_network_y:3.routing_node_up:5374 ;
+ wire \vertical_routing_network_x:1.vertical_routing_network_y:4.routing_node_down:6860 ;
+ wire [15:0] \vertical_routing_network_x:1.vertical_routing_network_y:4.routing_node_down:6862 ;
+ wire \vertical_routing_network_x:1.vertical_routing_network_y:4.routing_node_up:6850 ;
+ wire [15:0] \vertical_routing_network_x:1.vertical_routing_network_y:4.routing_node_up:6852 ;
+ wire \vertical_routing_network_x:1.vertical_routing_network_y:5.routing_node_down:8338 ;
+ wire [15:0] \vertical_routing_network_x:1.vertical_routing_network_y:5.routing_node_down:8340 ;
+ wire \vertical_routing_network_x:1.vertical_routing_network_y:5.routing_node_up:8328 ;
+ wire [15:0] \vertical_routing_network_x:1.vertical_routing_network_y:5.routing_node_up:8330 ;
+ wire \vertical_routing_network_x:1.vertical_routing_network_y:6.routing_node_down:9816 ;
+ wire [15:0] \vertical_routing_network_x:1.vertical_routing_network_y:6.routing_node_down:9818 ;
+ wire \vertical_routing_network_x:1.vertical_routing_network_y:6.routing_node_up:9806 ;
+ wire [15:0] \vertical_routing_network_x:1.vertical_routing_network_y:6.routing_node_up:9808 ;
+ wire \vertical_routing_network_x:1.vertical_routing_network_y:7.routing_node_down:11294 ;
+ wire [15:0] \vertical_routing_network_x:1.vertical_routing_network_y:7.routing_node_down:11296 ;
+ wire \vertical_routing_network_x:1.vertical_routing_network_y:7.routing_node_up:11284 ;
+ wire [15:0] \vertical_routing_network_x:1.vertical_routing_network_y:7.routing_node_up:11286 ;
+ wire \vertical_routing_network_x:2.vertical_routing_network_y:1.routing_node_down:12436 ;
+ wire [15:0] \vertical_routing_network_x:2.vertical_routing_network_y:1.routing_node_down:12438 ;
+ wire \vertical_routing_network_x:2.vertical_routing_network_y:1.routing_node_up:12426 ;
+ wire [15:0] \vertical_routing_network_x:2.vertical_routing_network_y:1.routing_node_up:12428 ;
+ wire \vertical_routing_network_x:2.vertical_routing_network_y:2.routing_node_down:13578 ;
+ wire [15:0] \vertical_routing_network_x:2.vertical_routing_network_y:2.routing_node_down:13580 ;
+ wire \vertical_routing_network_x:2.vertical_routing_network_y:2.routing_node_up:13568 ;
+ wire [15:0] \vertical_routing_network_x:2.vertical_routing_network_y:2.routing_node_up:13570 ;
+ wire \vertical_routing_network_x:2.vertical_routing_network_y:3.routing_node_down:14720 ;
+ wire [15:0] \vertical_routing_network_x:2.vertical_routing_network_y:3.routing_node_down:14722 ;
+ wire \vertical_routing_network_x:2.vertical_routing_network_y:3.routing_node_up:14710 ;
+ wire [15:0] \vertical_routing_network_x:2.vertical_routing_network_y:3.routing_node_up:14712 ;
+ wire \vertical_routing_network_x:2.vertical_routing_network_y:4.routing_node_down:15862 ;
+ wire [15:0] \vertical_routing_network_x:2.vertical_routing_network_y:4.routing_node_down:15864 ;
+ wire \vertical_routing_network_x:2.vertical_routing_network_y:4.routing_node_up:15852 ;
+ wire [15:0] \vertical_routing_network_x:2.vertical_routing_network_y:4.routing_node_up:15854 ;
+ wire \vertical_routing_network_x:2.vertical_routing_network_y:5.routing_node_down:17004 ;
+ wire [15:0] \vertical_routing_network_x:2.vertical_routing_network_y:5.routing_node_down:17006 ;
+ wire \vertical_routing_network_x:2.vertical_routing_network_y:5.routing_node_up:16994 ;
+ wire [15:0] \vertical_routing_network_x:2.vertical_routing_network_y:5.routing_node_up:16996 ;
+ wire \vertical_routing_network_x:2.vertical_routing_network_y:6.routing_node_down:18146 ;
+ wire [15:0] \vertical_routing_network_x:2.vertical_routing_network_y:6.routing_node_down:18148 ;
+ wire \vertical_routing_network_x:2.vertical_routing_network_y:6.routing_node_up:18136 ;
+ wire [15:0] \vertical_routing_network_x:2.vertical_routing_network_y:6.routing_node_up:18138 ;
+ wire \vertical_routing_network_x:2.vertical_routing_network_y:7.routing_node_down:19288 ;
+ wire [15:0] \vertical_routing_network_x:2.vertical_routing_network_y:7.routing_node_down:19290 ;
+ wire \vertical_routing_network_x:2.vertical_routing_network_y:7.routing_node_up:19278 ;
+ wire [15:0] \vertical_routing_network_x:2.vertical_routing_network_y:7.routing_node_up:19280 ;
+ wire \vertical_routing_network_x:3.vertical_routing_network_y:1.routing_node_down:20763 ;
+ wire [15:0] \vertical_routing_network_x:3.vertical_routing_network_y:1.routing_node_down:20765 ;
+ wire \vertical_routing_network_x:3.vertical_routing_network_y:1.routing_node_up:19300 ;
+ wire [15:0] \vertical_routing_network_x:3.vertical_routing_network_y:1.routing_node_up:19302 ;
+ wire \vertical_routing_network_x:3.vertical_routing_network_y:2.routing_node_down:22238 ;
+ wire [15:0] \vertical_routing_network_x:3.vertical_routing_network_y:2.routing_node_down:22240 ;
+ wire \vertical_routing_network_x:3.vertical_routing_network_y:2.routing_node_up:20775 ;
+ wire [15:0] \vertical_routing_network_x:3.vertical_routing_network_y:2.routing_node_up:20777 ;
+ wire \vertical_routing_network_x:3.vertical_routing_network_y:3.routing_node_down:23713 ;
+ wire [15:0] \vertical_routing_network_x:3.vertical_routing_network_y:3.routing_node_down:23715 ;
+ wire \vertical_routing_network_x:3.vertical_routing_network_y:3.routing_node_up:22250 ;
+ wire [15:0] \vertical_routing_network_x:3.vertical_routing_network_y:3.routing_node_up:22252 ;
+ wire \vertical_routing_network_x:3.vertical_routing_network_y:4.routing_node_down:25188 ;
+ wire [15:0] \vertical_routing_network_x:3.vertical_routing_network_y:4.routing_node_down:25190 ;
+ wire \vertical_routing_network_x:3.vertical_routing_network_y:4.routing_node_up:23725 ;
+ wire [15:0] \vertical_routing_network_x:3.vertical_routing_network_y:4.routing_node_up:23727 ;
+ wire \vertical_routing_network_x:3.vertical_routing_network_y:5.routing_node_down:26663 ;
+ wire [15:0] \vertical_routing_network_x:3.vertical_routing_network_y:5.routing_node_down:26665 ;
+ wire \vertical_routing_network_x:3.vertical_routing_network_y:5.routing_node_up:25200 ;
+ wire [15:0] \vertical_routing_network_x:3.vertical_routing_network_y:5.routing_node_up:25202 ;
+ wire \vertical_routing_network_x:3.vertical_routing_network_y:6.routing_node_down:28138 ;
+ wire [15:0] \vertical_routing_network_x:3.vertical_routing_network_y:6.routing_node_down:28140 ;
+ wire \vertical_routing_network_x:3.vertical_routing_network_y:6.routing_node_up:26675 ;
+ wire [15:0] \vertical_routing_network_x:3.vertical_routing_network_y:6.routing_node_up:26677 ;
+ wire \vertical_routing_network_x:3.vertical_routing_network_y:7.routing_node_down:29613 ;
+ wire [15:0] \vertical_routing_network_x:3.vertical_routing_network_y:7.routing_node_down:29615 ;
+ wire \vertical_routing_network_x:3.vertical_routing_network_y:7.routing_node_up:28150 ;
+ wire [15:0] \vertical_routing_network_x:3.vertical_routing_network_y:7.routing_node_up:28152 ;
+ wire [62:0] vrnode_cfg_shift_chain;
+ assign _000_ = ~ glb_rst_i;
+ fpga_io_mux \horizontal_routing_network_x:1.horizontal_routing_network_y:1.down_io.routing_down_io (
+ .config_clk_i(config_hrnode_i[0]),
+ .config_ena_i(glb_rst_i),
+ .config_shift_i(hrnode_cfg_shift_chain[36]),
+ .config_shift_o(_141_),
+ .pins_o(_142_),
+ .route_i({ right_tracks_out[255:240], left_tracks_out[255:240] })
+ );
+ fpga_routing_node_wcfg \horizontal_routing_network_x:1.horizontal_routing_network_y:1.routing_node_left (
+ .config_clk_i(config_hrnode_i[0]),
+ .config_ena_i(glb_rst_i),
+ .config_shift_i(hrnode_cfg_shift_chain[35]),
+ .config_shift_o(_143_),
+ .route_i(left_tracks_in[1791:1680]),
+ .route_o(_144_)
+ );
+ fpga_routing_node_wcfg \horizontal_routing_network_x:1.horizontal_routing_network_y:1.routing_node_right (
+ .config_clk_i(config_hrnode_i[0]),
+ .config_ena_i(glb_rst_i),
+ .config_shift_i(hrnode_cfg_shift_chain[34]),
+ .config_shift_o(_145_),
+ .route_i(right_tracks_in[1791:1680]),
+ .route_o(_146_)
+ );
+ fpga_routing_node_wcfg \horizontal_routing_network_x:1.horizontal_routing_network_y:2.routing_node_left (
+ .config_clk_i(config_hrnode_i[0]),
+ .config_ena_i(glb_rst_i),
+ .config_shift_i(hrnode_cfg_shift_chain[33]),
+ .config_shift_o(_147_),
+ .route_i(left_tracks_in[1679:1568]),
+ .route_o(_148_)
+ );
+ fpga_routing_node_wcfg \horizontal_routing_network_x:1.horizontal_routing_network_y:2.routing_node_right (
+ .config_clk_i(config_hrnode_i[0]),
+ .config_ena_i(glb_rst_i),
+ .config_shift_i(hrnode_cfg_shift_chain[32]),
+ .config_shift_o(_149_),
+ .route_i(right_tracks_in[1679:1568]),
+ .route_o(_150_)
+ );
+ fpga_routing_node_wcfg \horizontal_routing_network_x:1.horizontal_routing_network_y:3.routing_node_left (
+ .config_clk_i(config_hrnode_i[0]),
+ .config_ena_i(glb_rst_i),
+ .config_shift_i(hrnode_cfg_shift_chain[31]),
+ .config_shift_o(_151_),
+ .route_i(left_tracks_in[1567:1456]),
+ .route_o(_152_)
+ );
+ fpga_routing_node_wcfg \horizontal_routing_network_x:1.horizontal_routing_network_y:3.routing_node_right (
+ .config_clk_i(config_hrnode_i[0]),
+ .config_ena_i(glb_rst_i),
+ .config_shift_i(hrnode_cfg_shift_chain[30]),
+ .config_shift_o(_153_),
+ .route_i(right_tracks_in[1567:1456]),
+ .route_o(_154_)
+ );
+ fpga_routing_node_wcfg \horizontal_routing_network_x:1.horizontal_routing_network_y:4.routing_node_left (
+ .config_clk_i(config_hrnode_i[0]),
+ .config_ena_i(glb_rst_i),
+ .config_shift_i(hrnode_cfg_shift_chain[29]),
+ .config_shift_o(_155_),
+ .route_i(left_tracks_in[1455:1344]),
+ .route_o(_156_)
+ );
+ fpga_routing_node_wcfg \horizontal_routing_network_x:1.horizontal_routing_network_y:4.routing_node_right (
+ .config_clk_i(config_hrnode_i[0]),
+ .config_ena_i(glb_rst_i),
+ .config_shift_i(hrnode_cfg_shift_chain[28]),
+ .config_shift_o(_157_),
+ .route_i(right_tracks_in[1455:1344]),
+ .route_o(_158_)
+ );
+ fpga_routing_node_wcfg \horizontal_routing_network_x:1.horizontal_routing_network_y:5.routing_node_left (
+ .config_clk_i(config_hrnode_i[0]),
+ .config_ena_i(glb_rst_i),
+ .config_shift_i(hrnode_cfg_shift_chain[27]),
+ .config_shift_o(_159_),
+ .route_i(left_tracks_in[1343:1232]),
+ .route_o(_160_)
+ );
+ fpga_routing_node_wcfg \horizontal_routing_network_x:1.horizontal_routing_network_y:5.routing_node_right (
+ .config_clk_i(config_hrnode_i[0]),
+ .config_ena_i(glb_rst_i),
+ .config_shift_i(hrnode_cfg_shift_chain[26]),
+ .config_shift_o(_161_),
+ .route_i(right_tracks_in[1343:1232]),
+ .route_o(_162_)
+ );
+ fpga_routing_node_wcfg \horizontal_routing_network_x:1.horizontal_routing_network_y:6.routing_node_left (
+ .config_clk_i(config_hrnode_i[0]),
+ .config_ena_i(glb_rst_i),
+ .config_shift_i(hrnode_cfg_shift_chain[25]),
+ .config_shift_o(_163_),
+ .route_i(left_tracks_in[1231:1120]),
+ .route_o(_164_)
+ );
+ fpga_routing_node_wcfg \horizontal_routing_network_x:1.horizontal_routing_network_y:6.routing_node_right (
+ .config_clk_i(config_hrnode_i[0]),
+ .config_ena_i(glb_rst_i),
+ .config_shift_i(hrnode_cfg_shift_chain[24]),
+ .config_shift_o(_165_),
+ .route_i(right_tracks_in[1231:1120]),
+ .route_o(_166_)
+ );
+ fpga_routing_node_wcfg \horizontal_routing_network_x:1.horizontal_routing_network_y:7.routing_node_left (
+ .config_clk_i(config_hrnode_i[0]),
+ .config_ena_i(glb_rst_i),
+ .config_shift_i(hrnode_cfg_shift_chain[23]),
+ .config_shift_o(_167_),
+ .route_i(left_tracks_in[1119:1008]),
+ .route_o(_168_)
+ );
+ fpga_routing_node_wcfg \horizontal_routing_network_x:1.horizontal_routing_network_y:7.routing_node_right (
+ .config_clk_i(config_hrnode_i[0]),
+ .config_ena_i(glb_rst_i),
+ .config_shift_i(hrnode_cfg_shift_chain[22]),
+ .config_shift_o(_169_),
+ .route_i(right_tracks_in[1119:1008]),
+ .route_o(_170_)
+ );
+ fpga_routing_node_wcfg \horizontal_routing_network_x:1.horizontal_routing_network_y:8.routing_node_left (
+ .config_clk_i(config_hrnode_i[0]),
+ .config_ena_i(glb_rst_i),
+ .config_shift_i(hrnode_cfg_shift_chain[21]),
+ .config_shift_o(_171_),
+ .route_i(left_tracks_in[1007:896]),
+ .route_o(_172_)
+ );
+ fpga_routing_node_wcfg \horizontal_routing_network_x:1.horizontal_routing_network_y:8.routing_node_right (
+ .config_clk_i(config_hrnode_i[0]),
+ .config_ena_i(glb_rst_i),
+ .config_shift_i(hrnode_cfg_shift_chain[20]),
+ .config_shift_o(_175_),
+ .route_i(right_tracks_in[1007:896]),
+ .route_o(_176_)
+ );
+ fpga_io_mux \horizontal_routing_network_x:1.horizontal_routing_network_y:8.up_io.routing_up_io (
+ .config_clk_i(config_hrnode_i[0]),
+ .config_ena_i(glb_rst_i),
+ .config_shift_i(hrnode_cfg_shift_chain[19]),
+ .config_shift_o(_173_),
+ .pins_o(_174_),
+ .route_i({ right_tracks_out[143:128], left_tracks_out[143:128] })
+ );
+ fpga_io_mux \horizontal_routing_network_x:2.horizontal_routing_network_y:1.down_io.routing_down_io (
+ .config_clk_i(config_hrnode_i[2]),
+ .config_ena_i(glb_rst_i),
+ .config_shift_i(hrnode_cfg_shift_chain[17]),
+ .config_shift_o(_177_),
+ .pins_o(_178_),
+ .route_i({ right_tracks_out[127:112], left_tracks_out[127:112] })
+ );
+ fpga_routing_node_wcfg \horizontal_routing_network_x:2.horizontal_routing_network_y:1.routing_node_left (
+ .config_clk_i(config_hrnode_i[2]),
+ .config_ena_i(glb_rst_i),
+ .config_shift_i(hrnode_cfg_shift_chain[16]),
+ .config_shift_o(_179_),
+ .route_i(left_tracks_in[895:784]),
+ .route_o(_180_)
+ );
+ fpga_routing_node_wcfg \horizontal_routing_network_x:2.horizontal_routing_network_y:1.routing_node_right (
+ .config_clk_i(config_hrnode_i[2]),
+ .config_ena_i(glb_rst_i),
+ .config_shift_i(hrnode_cfg_shift_chain[15]),
+ .config_shift_o(_181_),
+ .route_i(right_tracks_in[895:784]),
+ .route_o(_182_)
+ );
+ fpga_routing_node_wcfg \horizontal_routing_network_x:2.horizontal_routing_network_y:2.routing_node_left (
+ .config_clk_i(config_hrnode_i[2]),
+ .config_ena_i(glb_rst_i),
+ .config_shift_i(hrnode_cfg_shift_chain[14]),
+ .config_shift_o(_183_),
+ .route_i(left_tracks_in[783:672]),
+ .route_o(_184_)
+ );
+ fpga_routing_node_wcfg \horizontal_routing_network_x:2.horizontal_routing_network_y:2.routing_node_right (
+ .config_clk_i(config_hrnode_i[2]),
+ .config_ena_i(glb_rst_i),
+ .config_shift_i(hrnode_cfg_shift_chain[13]),
+ .config_shift_o(_185_),
+ .route_i(right_tracks_in[783:672]),
+ .route_o(_186_)
+ );
+ fpga_routing_node_wcfg \horizontal_routing_network_x:2.horizontal_routing_network_y:3.routing_node_left (
+ .config_clk_i(config_hrnode_i[2]),
+ .config_ena_i(glb_rst_i),
+ .config_shift_i(hrnode_cfg_shift_chain[12]),
+ .config_shift_o(_187_),
+ .route_i(left_tracks_in[671:560]),
+ .route_o(_188_)
+ );
+ fpga_routing_node_wcfg \horizontal_routing_network_x:2.horizontal_routing_network_y:3.routing_node_right (
+ .config_clk_i(config_hrnode_i[2]),
+ .config_ena_i(glb_rst_i),
+ .config_shift_i(hrnode_cfg_shift_chain[11]),
+ .config_shift_o(_189_),
+ .route_i(right_tracks_in[671:560]),
+ .route_o(_190_)
+ );
+ fpga_routing_node_wcfg \horizontal_routing_network_x:2.horizontal_routing_network_y:4.routing_node_left (
+ .config_clk_i(config_hrnode_i[2]),
+ .config_ena_i(glb_rst_i),
+ .config_shift_i(hrnode_cfg_shift_chain[10]),
+ .config_shift_o(_191_),
+ .route_i(left_tracks_in[559:448]),
+ .route_o(_192_)
+ );
+ fpga_routing_node_wcfg \horizontal_routing_network_x:2.horizontal_routing_network_y:4.routing_node_right (
+ .config_clk_i(config_hrnode_i[2]),
+ .config_ena_i(glb_rst_i),
+ .config_shift_i(hrnode_cfg_shift_chain[9]),
+ .config_shift_o(_193_),
+ .route_i(right_tracks_in[559:448]),
+ .route_o(_194_)
+ );
+ fpga_routing_node_wcfg \horizontal_routing_network_x:2.horizontal_routing_network_y:5.routing_node_left (
+ .config_clk_i(config_hrnode_i[2]),
+ .config_ena_i(glb_rst_i),
+ .config_shift_i(hrnode_cfg_shift_chain[8]),
+ .config_shift_o(_195_),
+ .route_i(left_tracks_in[447:336]),
+ .route_o(_196_)
+ );
+ fpga_routing_node_wcfg \horizontal_routing_network_x:2.horizontal_routing_network_y:5.routing_node_right (
+ .config_clk_i(config_hrnode_i[2]),
+ .config_ena_i(glb_rst_i),
+ .config_shift_i(hrnode_cfg_shift_chain[7]),
+ .config_shift_o(_197_),
+ .route_i(right_tracks_in[447:336]),
+ .route_o(_198_)
+ );
+ fpga_routing_node_wcfg \horizontal_routing_network_x:2.horizontal_routing_network_y:6.routing_node_left (
+ .config_clk_i(config_hrnode_i[2]),
+ .config_ena_i(glb_rst_i),
+ .config_shift_i(hrnode_cfg_shift_chain[6]),
+ .config_shift_o(_199_),
+ .route_i(left_tracks_in[335:224]),
+ .route_o(_200_)
+ );
+ fpga_routing_node_wcfg \horizontal_routing_network_x:2.horizontal_routing_network_y:6.routing_node_right (
+ .config_clk_i(config_hrnode_i[2]),
+ .config_ena_i(glb_rst_i),
+ .config_shift_i(hrnode_cfg_shift_chain[5]),
+ .config_shift_o(_201_),
+ .route_i(right_tracks_in[335:224]),
+ .route_o(_202_)
+ );
+ fpga_routing_node_wcfg \horizontal_routing_network_x:2.horizontal_routing_network_y:7.routing_node_left (
+ .config_clk_i(config_hrnode_i[2]),
+ .config_ena_i(glb_rst_i),
+ .config_shift_i(hrnode_cfg_shift_chain[4]),
+ .config_shift_o(_203_),
+ .route_i(left_tracks_in[223:112]),
+ .route_o(_204_)
+ );
+ fpga_routing_node_wcfg \horizontal_routing_network_x:2.horizontal_routing_network_y:7.routing_node_right (
+ .config_clk_i(config_hrnode_i[2]),
+ .config_ena_i(glb_rst_i),
+ .config_shift_i(hrnode_cfg_shift_chain[3]),
+ .config_shift_o(_205_),
+ .route_i(right_tracks_in[223:112]),
+ .route_o(_206_)
+ );
+ fpga_routing_node_wcfg \horizontal_routing_network_x:2.horizontal_routing_network_y:8.routing_node_left (
+ .config_clk_i(config_hrnode_i[2]),
+ .config_ena_i(glb_rst_i),
+ .config_shift_i(hrnode_cfg_shift_chain[2]),
+ .config_shift_o(_207_),
+ .route_i(left_tracks_in[111:0]),
+ .route_o(_208_)
+ );
+ fpga_routing_node_wcfg \horizontal_routing_network_x:2.horizontal_routing_network_y:8.routing_node_right (
+ .config_clk_i(config_hrnode_i[2]),
+ .config_ena_i(glb_rst_i),
+ .config_shift_i(hrnode_cfg_shift_chain[1]),
+ .config_shift_o(_211_),
+ .route_i(right_tracks_in[111:0]),
+ .route_o(_212_)
+ );
+ fpga_io_mux \horizontal_routing_network_x:2.horizontal_routing_network_y:8.up_io.routing_up_io (
+ .config_clk_i(config_hrnode_i[2]),
+ .config_ena_i(glb_rst_i),
+ .config_shift_i(hrnode_cfg_shift_chain[0]),
+ .config_shift_o(_209_),
+ .pins_o(_210_),
+ .route_i({ right_tracks_out[15:0], left_tracks_out[15:0] })
+ );
+ fpga_struct_block \struct_blocks_x:1.struct_blocks_y:1.struct_block (
+ .clk_i(clk_i),
+ .config_clk_i(config_block_i[0]),
+ .config_ena_i(glb_rst_i),
+ .config_shift_i(block_cfg_shift_chain[9]),
+ .config_shift_o(_001_),
+ .glb_rstn_i(glb_rstn),
+ .inputs_down_i({ right_tracks_out[255:240], left_tracks_out[255:240] }),
+ .inputs_left_i({ down_tracks_out[335:320], up_tracks_out[335:320] }),
+ .inputs_right_i({ down_tracks_out[223:208], up_tracks_out[223:208] }),
+ .inputs_up_i({ right_tracks_out[239:224], left_tracks_out[239:224] }),
+ .outputs_o(_002_)
+ );
+ fpga_struct_block \struct_blocks_x:1.struct_blocks_y:2.struct_block (
+ .clk_i(clk_i),
+ .config_clk_i(config_block_i[0]),
+ .config_ena_i(glb_rst_i),
+ .config_shift_i(block_cfg_shift_chain[10]),
+ .config_shift_o(_003_),
+ .glb_rstn_i(glb_rstn),
+ .inputs_down_i({ right_tracks_out[239:224], left_tracks_out[239:224] }),
+ .inputs_left_i({ down_tracks_out[319:304], up_tracks_out[319:304] }),
+ .inputs_right_i({ down_tracks_out[207:192], up_tracks_out[207:192] }),
+ .inputs_up_i({ right_tracks_out[223:208], left_tracks_out[223:208] }),
+ .outputs_o(_004_)
+ );
+ fpga_struct_block \struct_blocks_x:1.struct_blocks_y:3.struct_block (
+ .clk_i(clk_i),
+ .config_clk_i(config_block_i[0]),
+ .config_ena_i(glb_rst_i),
+ .config_shift_i(block_cfg_shift_chain[11]),
+ .config_shift_o(_005_),
+ .glb_rstn_i(glb_rstn),
+ .inputs_down_i({ right_tracks_out[223:208], left_tracks_out[223:208] }),
+ .inputs_left_i({ down_tracks_out[303:288], up_tracks_out[303:288] }),
+ .inputs_right_i({ down_tracks_out[191:176], up_tracks_out[191:176] }),
+ .inputs_up_i({ right_tracks_out[207:192], left_tracks_out[207:192] }),
+ .outputs_o(_006_)
+ );
+ fpga_struct_block \struct_blocks_x:1.struct_blocks_y:4.struct_block (
+ .clk_i(clk_i),
+ .config_clk_i(config_block_i[0]),
+ .config_ena_i(glb_rst_i),
+ .config_shift_i(block_cfg_shift_chain[12]),
+ .config_shift_o(_007_),
+ .glb_rstn_i(glb_rstn),
+ .inputs_down_i({ right_tracks_out[207:192], left_tracks_out[207:192] }),
+ .inputs_left_i({ down_tracks_out[287:272], up_tracks_out[287:272] }),
+ .inputs_right_i({ down_tracks_out[175:160], up_tracks_out[175:160] }),
+ .inputs_up_i({ right_tracks_out[191:176], left_tracks_out[191:176] }),
+ .outputs_o(_008_)
+ );
+ fpga_struct_block \struct_blocks_x:1.struct_blocks_y:5.struct_block (
+ .clk_i(clk_i),
+ .config_clk_i(config_block_i[0]),
+ .config_ena_i(glb_rst_i),
+ .config_shift_i(block_cfg_shift_chain[13]),
+ .config_shift_o(_009_),
+ .glb_rstn_i(glb_rstn),
+ .inputs_down_i({ right_tracks_out[191:176], left_tracks_out[191:176] }),
+ .inputs_left_i({ down_tracks_out[271:256], up_tracks_out[271:256] }),
+ .inputs_right_i({ down_tracks_out[159:144], up_tracks_out[159:144] }),
+ .inputs_up_i({ right_tracks_out[175:160], left_tracks_out[175:160] }),
+ .outputs_o(_010_)
+ );
+ fpga_struct_block \struct_blocks_x:1.struct_blocks_y:6.struct_block (
+ .clk_i(clk_i),
+ .config_clk_i(config_block_i[0]),
+ .config_ena_i(glb_rst_i),
+ .config_shift_i(block_cfg_shift_chain[14]),
+ .config_shift_o(_011_),
+ .glb_rstn_i(glb_rstn),
+ .inputs_down_i({ right_tracks_out[175:160], left_tracks_out[175:160] }),
+ .inputs_left_i({ down_tracks_out[255:240], up_tracks_out[255:240] }),
+ .inputs_right_i({ down_tracks_out[143:128], up_tracks_out[143:128] }),
+ .inputs_up_i({ right_tracks_out[159:144], left_tracks_out[159:144] }),
+ .outputs_o(_012_)
+ );
+ fpga_struct_block \struct_blocks_x:1.struct_blocks_y:7.struct_block (
+ .clk_i(clk_i),
+ .config_clk_i(config_block_i[0]),
+ .config_ena_i(glb_rst_i),
+ .config_shift_i(block_cfg_shift_chain[15]),
+ .config_shift_o(_013_),
+ .glb_rstn_i(glb_rstn),
+ .inputs_down_i({ right_tracks_out[159:144], left_tracks_out[159:144] }),
+ .inputs_left_i({ down_tracks_out[239:224], up_tracks_out[239:224] }),
+ .inputs_right_i({ down_tracks_out[127:112], up_tracks_out[127:112] }),
+ .inputs_up_i({ right_tracks_out[143:128], left_tracks_out[143:128] }),
+ .outputs_o(_014_)
+ );
+ fpga_struct_block \struct_blocks_x:2.struct_blocks_y:1.struct_block (
+ .clk_i(clk_i),
+ .config_clk_i(config_block_i[2]),
+ .config_ena_i(glb_rst_i),
+ .config_shift_i(block_cfg_shift_chain[1]),
+ .config_shift_o(_015_),
+ .glb_rstn_i(glb_rstn),
+ .inputs_down_i({ right_tracks_out[127:112], left_tracks_out[127:112] }),
+ .inputs_left_i({ down_tracks_out[223:208], up_tracks_out[223:208] }),
+ .inputs_right_i({ down_tracks_out[111:96], up_tracks_out[111:96] }),
+ .inputs_up_i({ right_tracks_out[111:96], left_tracks_out[111:96] }),
+ .outputs_o(_016_)
+ );
+ fpga_struct_block \struct_blocks_x:2.struct_blocks_y:2.struct_block (
+ .clk_i(clk_i),
+ .config_clk_i(config_block_i[2]),
+ .config_ena_i(glb_rst_i),
+ .config_shift_i(block_cfg_shift_chain[2]),
+ .config_shift_o(_017_),
+ .glb_rstn_i(glb_rstn),
+ .inputs_down_i({ right_tracks_out[111:96], left_tracks_out[111:96] }),
+ .inputs_left_i({ down_tracks_out[207:192], up_tracks_out[207:192] }),
+ .inputs_right_i({ down_tracks_out[95:80], up_tracks_out[95:80] }),
+ .inputs_up_i({ right_tracks_out[95:80], left_tracks_out[95:80] }),
+ .outputs_o(_018_)
+ );
+ fpga_struct_block \struct_blocks_x:2.struct_blocks_y:3.struct_block (
+ .clk_i(clk_i),
+ .config_clk_i(config_block_i[2]),
+ .config_ena_i(glb_rst_i),
+ .config_shift_i(block_cfg_shift_chain[3]),
+ .config_shift_o(_019_),
+ .glb_rstn_i(glb_rstn),
+ .inputs_down_i({ right_tracks_out[95:80], left_tracks_out[95:80] }),
+ .inputs_left_i({ down_tracks_out[191:176], up_tracks_out[191:176] }),
+ .inputs_right_i({ down_tracks_out[79:64], up_tracks_out[79:64] }),
+ .inputs_up_i({ right_tracks_out[79:64], left_tracks_out[79:64] }),
+ .outputs_o(_020_)
+ );
+ fpga_struct_block \struct_blocks_x:2.struct_blocks_y:4.struct_block (
+ .clk_i(clk_i),
+ .config_clk_i(config_block_i[2]),
+ .config_ena_i(glb_rst_i),
+ .config_shift_i(block_cfg_shift_chain[4]),
+ .config_shift_o(_021_),
+ .glb_rstn_i(glb_rstn),
+ .inputs_down_i({ right_tracks_out[79:64], left_tracks_out[79:64] }),
+ .inputs_left_i({ down_tracks_out[175:160], up_tracks_out[175:160] }),
+ .inputs_right_i({ down_tracks_out[63:48], up_tracks_out[63:48] }),
+ .inputs_up_i({ right_tracks_out[63:48], left_tracks_out[63:48] }),
+ .outputs_o(_022_)
+ );
+ fpga_struct_block \struct_blocks_x:2.struct_blocks_y:5.struct_block (
+ .clk_i(clk_i),
+ .config_clk_i(config_block_i[2]),
+ .config_ena_i(glb_rst_i),
+ .config_shift_i(block_cfg_shift_chain[5]),
+ .config_shift_o(_023_),
+ .glb_rstn_i(glb_rstn),
+ .inputs_down_i({ right_tracks_out[63:48], left_tracks_out[63:48] }),
+ .inputs_left_i({ down_tracks_out[159:144], up_tracks_out[159:144] }),
+ .inputs_right_i({ down_tracks_out[47:32], up_tracks_out[47:32] }),
+ .inputs_up_i({ right_tracks_out[47:32], left_tracks_out[47:32] }),
+ .outputs_o(_024_)
+ );
+ fpga_struct_block \struct_blocks_x:2.struct_blocks_y:6.struct_block (
+ .clk_i(clk_i),
+ .config_clk_i(config_block_i[2]),
+ .config_ena_i(glb_rst_i),
+ .config_shift_i(block_cfg_shift_chain[6]),
+ .config_shift_o(_025_),
+ .glb_rstn_i(glb_rstn),
+ .inputs_down_i({ right_tracks_out[47:32], left_tracks_out[47:32] }),
+ .inputs_left_i({ down_tracks_out[143:128], up_tracks_out[143:128] }),
+ .inputs_right_i({ down_tracks_out[31:16], up_tracks_out[31:16] }),
+ .inputs_up_i({ right_tracks_out[31:16], left_tracks_out[31:16] }),
+ .outputs_o(_026_)
+ );
+ fpga_struct_block \struct_blocks_x:2.struct_blocks_y:7.struct_block (
+ .clk_i(clk_i),
+ .config_clk_i(config_block_i[2]),
+ .config_ena_i(glb_rst_i),
+ .config_shift_i(block_cfg_shift_chain[7]),
+ .config_shift_o(_027_),
+ .glb_rstn_i(glb_rstn),
+ .inputs_down_i({ right_tracks_out[31:16], left_tracks_out[31:16] }),
+ .inputs_left_i({ down_tracks_out[127:112], up_tracks_out[127:112] }),
+ .inputs_right_i({ down_tracks_out[15:0], up_tracks_out[15:0] }),
+ .inputs_up_i({ right_tracks_out[15:0], left_tracks_out[15:0] }),
+ .outputs_o(_028_)
+ );
+ fpga_io_mux \vertical_routing_network_x:1.vertical_routing_network_y:1.left_io.routing_left_io (
+ .config_clk_i(config_vrnode_i[0]),
+ .config_ena_i(glb_rst_i),
+ .config_shift_i(vrnode_cfg_shift_chain[61]),
+ .config_shift_o(_029_),
+ .pins_o(_030_),
+ .route_i({ down_tracks_out[335:320], up_tracks_out[335:320] })
+ );
+ fpga_routing_node_wcfg \vertical_routing_network_x:1.vertical_routing_network_y:1.routing_node_down (
+ .config_clk_i(config_vrnode_i[0]),
+ .config_ena_i(glb_rst_i),
+ .config_shift_i(vrnode_cfg_shift_chain[59]),
+ .config_shift_o(_033_),
+ .route_i(down_tracks_in[2351:2240]),
+ .route_o(_034_)
+ );
+ fpga_routing_node_wcfg \vertical_routing_network_x:1.vertical_routing_network_y:1.routing_node_up (
+ .config_clk_i(config_vrnode_i[0]),
+ .config_ena_i(glb_rst_i),
+ .config_shift_i(vrnode_cfg_shift_chain[60]),
+ .config_shift_o(_031_),
+ .route_i(up_tracks_in[2351:2240]),
+ .route_o(_032_)
+ );
+ fpga_io_mux \vertical_routing_network_x:1.vertical_routing_network_y:2.left_io.routing_left_io (
+ .config_clk_i(config_vrnode_i[2]),
+ .config_ena_i(glb_rst_i),
+ .config_shift_i(vrnode_cfg_shift_chain[52]),
+ .config_shift_o(_035_),
+ .pins_o(_036_),
+ .route_i({ down_tracks_out[319:304], up_tracks_out[319:304] })
+ );
+ fpga_routing_node_wcfg \vertical_routing_network_x:1.vertical_routing_network_y:2.routing_node_down (
+ .config_clk_i(config_vrnode_i[2]),
+ .config_ena_i(glb_rst_i),
+ .config_shift_i(vrnode_cfg_shift_chain[50]),
+ .config_shift_o(_039_),
+ .route_i(down_tracks_in[2239:2128]),
+ .route_o(_040_)
+ );
+ fpga_routing_node_wcfg \vertical_routing_network_x:1.vertical_routing_network_y:2.routing_node_up (
+ .config_clk_i(config_vrnode_i[2]),
+ .config_ena_i(glb_rst_i),
+ .config_shift_i(vrnode_cfg_shift_chain[51]),
+ .config_shift_o(_037_),
+ .route_i(up_tracks_in[2239:2128]),
+ .route_o(_038_)
+ );
+ fpga_io_mux \vertical_routing_network_x:1.vertical_routing_network_y:3.left_io.routing_left_io (
+ .config_clk_i(config_vrnode_i[4]),
+ .config_ena_i(glb_rst_i),
+ .config_shift_i(vrnode_cfg_shift_chain[43]),
+ .config_shift_o(_041_),
+ .pins_o(_042_),
+ .route_i({ down_tracks_out[303:288], up_tracks_out[303:288] })
+ );
+ fpga_routing_node_wcfg \vertical_routing_network_x:1.vertical_routing_network_y:3.routing_node_down (
+ .config_clk_i(config_vrnode_i[4]),
+ .config_ena_i(glb_rst_i),
+ .config_shift_i(vrnode_cfg_shift_chain[41]),
+ .config_shift_o(_045_),
+ .route_i(down_tracks_in[2127:2016]),
+ .route_o(_046_)
+ );
+ fpga_routing_node_wcfg \vertical_routing_network_x:1.vertical_routing_network_y:3.routing_node_up (
+ .config_clk_i(config_vrnode_i[4]),
+ .config_ena_i(glb_rst_i),
+ .config_shift_i(vrnode_cfg_shift_chain[42]),
+ .config_shift_o(_043_),
+ .route_i(up_tracks_in[2127:2016]),
+ .route_o(_044_)
+ );
+ fpga_io_mux \vertical_routing_network_x:1.vertical_routing_network_y:4.left_io.routing_left_io (
+ .config_clk_i(config_vrnode_i[6]),
+ .config_ena_i(glb_rst_i),
+ .config_shift_i(vrnode_cfg_shift_chain[34]),
+ .config_shift_o(_047_),
+ .pins_o(_048_),
+ .route_i({ down_tracks_out[287:272], up_tracks_out[287:272] })
+ );
+ fpga_routing_node_wcfg \vertical_routing_network_x:1.vertical_routing_network_y:4.routing_node_down (
+ .config_clk_i(config_vrnode_i[6]),
+ .config_ena_i(glb_rst_i),
+ .config_shift_i(vrnode_cfg_shift_chain[32]),
+ .config_shift_o(_051_),
+ .route_i(down_tracks_in[2015:1904]),
+ .route_o(_052_)
+ );
+ fpga_routing_node_wcfg \vertical_routing_network_x:1.vertical_routing_network_y:4.routing_node_up (
+ .config_clk_i(config_vrnode_i[6]),
+ .config_ena_i(glb_rst_i),
+ .config_shift_i(vrnode_cfg_shift_chain[33]),
+ .config_shift_o(_049_),
+ .route_i(up_tracks_in[2015:1904]),
+ .route_o(_050_)
+ );
+ fpga_io_mux \vertical_routing_network_x:1.vertical_routing_network_y:5.left_io.routing_left_io (
+ .config_clk_i(config_vrnode_i[8]),
+ .config_ena_i(glb_rst_i),
+ .config_shift_i(vrnode_cfg_shift_chain[25]),
+ .config_shift_o(_053_),
+ .pins_o(_054_),
+ .route_i({ down_tracks_out[271:256], up_tracks_out[271:256] })
+ );
+ fpga_routing_node_wcfg \vertical_routing_network_x:1.vertical_routing_network_y:5.routing_node_down (
+ .config_clk_i(config_vrnode_i[8]),
+ .config_ena_i(glb_rst_i),
+ .config_shift_i(vrnode_cfg_shift_chain[23]),
+ .config_shift_o(_057_),
+ .route_i(down_tracks_in[1903:1792]),
+ .route_o(_058_)
+ );
+ fpga_routing_node_wcfg \vertical_routing_network_x:1.vertical_routing_network_y:5.routing_node_up (
+ .config_clk_i(config_vrnode_i[8]),
+ .config_ena_i(glb_rst_i),
+ .config_shift_i(vrnode_cfg_shift_chain[24]),
+ .config_shift_o(_055_),
+ .route_i(up_tracks_in[1903:1792]),
+ .route_o(_056_)
+ );
+ fpga_io_mux \vertical_routing_network_x:1.vertical_routing_network_y:6.left_io.routing_left_io (
+ .config_clk_i(config_vrnode_i[10]),
+ .config_ena_i(glb_rst_i),
+ .config_shift_i(vrnode_cfg_shift_chain[16]),
+ .config_shift_o(_059_),
+ .pins_o(_060_),
+ .route_i({ down_tracks_out[255:240], up_tracks_out[255:240] })
+ );
+ fpga_routing_node_wcfg \vertical_routing_network_x:1.vertical_routing_network_y:6.routing_node_down (
+ .config_clk_i(config_vrnode_i[10]),
+ .config_ena_i(glb_rst_i),
+ .config_shift_i(vrnode_cfg_shift_chain[14]),
+ .config_shift_o(_063_),
+ .route_i(down_tracks_in[1791:1680]),
+ .route_o(_064_)
+ );
+ fpga_routing_node_wcfg \vertical_routing_network_x:1.vertical_routing_network_y:6.routing_node_up (
+ .config_clk_i(config_vrnode_i[10]),
+ .config_ena_i(glb_rst_i),
+ .config_shift_i(vrnode_cfg_shift_chain[15]),
+ .config_shift_o(_061_),
+ .route_i(up_tracks_in[1791:1680]),
+ .route_o(_062_)
+ );
+ fpga_io_mux \vertical_routing_network_x:1.vertical_routing_network_y:7.left_io.routing_left_io (
+ .config_clk_i(config_vrnode_i[12]),
+ .config_ena_i(glb_rst_i),
+ .config_shift_i(vrnode_cfg_shift_chain[7]),
+ .config_shift_o(_065_),
+ .pins_o(_066_),
+ .route_i({ down_tracks_out[239:224], up_tracks_out[239:224] })
+ );
+ fpga_routing_node_wcfg \vertical_routing_network_x:1.vertical_routing_network_y:7.routing_node_down (
+ .config_clk_i(config_vrnode_i[12]),
+ .config_ena_i(glb_rst_i),
+ .config_shift_i(vrnode_cfg_shift_chain[5]),
+ .config_shift_o(_069_),
+ .route_i(down_tracks_in[1679:1568]),
+ .route_o(_070_)
+ );
+ fpga_routing_node_wcfg \vertical_routing_network_x:1.vertical_routing_network_y:7.routing_node_up (
+ .config_clk_i(config_vrnode_i[12]),
+ .config_ena_i(glb_rst_i),
+ .config_shift_i(vrnode_cfg_shift_chain[6]),
+ .config_shift_o(_067_),
+ .route_i(up_tracks_in[1679:1568]),
+ .route_o(_068_)
+ );
+ fpga_routing_node_wcfg \vertical_routing_network_x:2.vertical_routing_network_y:1.routing_node_down (
+ .config_clk_i(config_vrnode_i[0]),
+ .config_ena_i(glb_rst_i),
+ .config_shift_i(vrnode_cfg_shift_chain[57]),
+ .config_shift_o(_073_),
+ .route_i(down_tracks_in[1567:1456]),
+ .route_o(_074_)
+ );
+ fpga_routing_node_wcfg \vertical_routing_network_x:2.vertical_routing_network_y:1.routing_node_up (
+ .config_clk_i(config_vrnode_i[0]),
+ .config_ena_i(glb_rst_i),
+ .config_shift_i(vrnode_cfg_shift_chain[58]),
+ .config_shift_o(_071_),
+ .route_i(up_tracks_in[1567:1456]),
+ .route_o(_072_)
+ );
+ fpga_routing_node_wcfg \vertical_routing_network_x:2.vertical_routing_network_y:2.routing_node_down (
+ .config_clk_i(config_vrnode_i[2]),
+ .config_ena_i(glb_rst_i),
+ .config_shift_i(vrnode_cfg_shift_chain[48]),
+ .config_shift_o(_077_),
+ .route_i(down_tracks_in[1455:1344]),
+ .route_o(_078_)
+ );
+ fpga_routing_node_wcfg \vertical_routing_network_x:2.vertical_routing_network_y:2.routing_node_up (
+ .config_clk_i(config_vrnode_i[2]),
+ .config_ena_i(glb_rst_i),
+ .config_shift_i(vrnode_cfg_shift_chain[49]),
+ .config_shift_o(_075_),
+ .route_i(up_tracks_in[1455:1344]),
+ .route_o(_076_)
+ );
+ fpga_routing_node_wcfg \vertical_routing_network_x:2.vertical_routing_network_y:3.routing_node_down (
+ .config_clk_i(config_vrnode_i[4]),
+ .config_ena_i(glb_rst_i),
+ .config_shift_i(vrnode_cfg_shift_chain[39]),
+ .config_shift_o(_081_),
+ .route_i(down_tracks_in[1343:1232]),
+ .route_o(_082_)
+ );
+ fpga_routing_node_wcfg \vertical_routing_network_x:2.vertical_routing_network_y:3.routing_node_up (
+ .config_clk_i(config_vrnode_i[4]),
+ .config_ena_i(glb_rst_i),
+ .config_shift_i(vrnode_cfg_shift_chain[40]),
+ .config_shift_o(_079_),
+ .route_i(up_tracks_in[1343:1232]),
+ .route_o(_080_)
+ );
+ fpga_routing_node_wcfg \vertical_routing_network_x:2.vertical_routing_network_y:4.routing_node_down (
+ .config_clk_i(config_vrnode_i[6]),
+ .config_ena_i(glb_rst_i),
+ .config_shift_i(vrnode_cfg_shift_chain[30]),
+ .config_shift_o(_085_),
+ .route_i(down_tracks_in[1231:1120]),
+ .route_o(_086_)
+ );
+ fpga_routing_node_wcfg \vertical_routing_network_x:2.vertical_routing_network_y:4.routing_node_up (
+ .config_clk_i(config_vrnode_i[6]),
+ .config_ena_i(glb_rst_i),
+ .config_shift_i(vrnode_cfg_shift_chain[31]),
+ .config_shift_o(_083_),
+ .route_i(up_tracks_in[1231:1120]),
+ .route_o(_084_)
+ );
+ fpga_routing_node_wcfg \vertical_routing_network_x:2.vertical_routing_network_y:5.routing_node_down (
+ .config_clk_i(config_vrnode_i[8]),
+ .config_ena_i(glb_rst_i),
+ .config_shift_i(vrnode_cfg_shift_chain[21]),
+ .config_shift_o(_089_),
+ .route_i(down_tracks_in[1119:1008]),
+ .route_o(_090_)
+ );
+ fpga_routing_node_wcfg \vertical_routing_network_x:2.vertical_routing_network_y:5.routing_node_up (
+ .config_clk_i(config_vrnode_i[8]),
+ .config_ena_i(glb_rst_i),
+ .config_shift_i(vrnode_cfg_shift_chain[22]),
+ .config_shift_o(_087_),
+ .route_i(up_tracks_in[1119:1008]),
+ .route_o(_088_)
+ );
+ fpga_routing_node_wcfg \vertical_routing_network_x:2.vertical_routing_network_y:6.routing_node_down (
+ .config_clk_i(config_vrnode_i[10]),
+ .config_ena_i(glb_rst_i),
+ .config_shift_i(vrnode_cfg_shift_chain[12]),
+ .config_shift_o(_093_),
+ .route_i(down_tracks_in[1007:896]),
+ .route_o(_094_)
+ );
+ fpga_routing_node_wcfg \vertical_routing_network_x:2.vertical_routing_network_y:6.routing_node_up (
+ .config_clk_i(config_vrnode_i[10]),
+ .config_ena_i(glb_rst_i),
+ .config_shift_i(vrnode_cfg_shift_chain[13]),
+ .config_shift_o(_091_),
+ .route_i(up_tracks_in[1007:896]),
+ .route_o(_092_)
+ );
+ fpga_routing_node_wcfg \vertical_routing_network_x:2.vertical_routing_network_y:7.routing_node_down (
+ .config_clk_i(config_vrnode_i[12]),
+ .config_ena_i(glb_rst_i),
+ .config_shift_i(vrnode_cfg_shift_chain[3]),
+ .config_shift_o(_097_),
+ .route_i(down_tracks_in[895:784]),
+ .route_o(_098_)
+ );
+ fpga_routing_node_wcfg \vertical_routing_network_x:2.vertical_routing_network_y:7.routing_node_up (
+ .config_clk_i(config_vrnode_i[12]),
+ .config_ena_i(glb_rst_i),
+ .config_shift_i(vrnode_cfg_shift_chain[4]),
+ .config_shift_o(_095_),
+ .route_i(up_tracks_in[895:784]),
+ .route_o(_096_)
+ );
+ fpga_io_mux \vertical_routing_network_x:3.vertical_routing_network_y:1.right_io.routing_right_io (
+ .config_clk_i(config_vrnode_i[0]),
+ .config_ena_i(glb_rst_i),
+ .config_shift_i(vrnode_cfg_shift_chain[54]),
+ .config_shift_o(_101_),
+ .pins_o(_102_),
+ .route_i({ down_tracks_out[111:96], up_tracks_out[111:96] })
+ );
+ fpga_routing_node_wcfg \vertical_routing_network_x:3.vertical_routing_network_y:1.routing_node_down (
+ .config_clk_i(config_vrnode_i[0]),
+ .config_ena_i(glb_rst_i),
+ .config_shift_i(vrnode_cfg_shift_chain[55]),
+ .config_shift_o(_103_),
+ .route_i(down_tracks_in[783:672]),
+ .route_o(_104_)
+ );
+ fpga_routing_node_wcfg \vertical_routing_network_x:3.vertical_routing_network_y:1.routing_node_up (
+ .config_clk_i(config_vrnode_i[0]),
+ .config_ena_i(glb_rst_i),
+ .config_shift_i(vrnode_cfg_shift_chain[56]),
+ .config_shift_o(_099_),
+ .route_i(up_tracks_in[783:672]),
+ .route_o(_100_)
+ );
+ fpga_io_mux \vertical_routing_network_x:3.vertical_routing_network_y:2.right_io.routing_right_io (
+ .config_clk_i(config_vrnode_i[2]),
+ .config_ena_i(glb_rst_i),
+ .config_shift_i(vrnode_cfg_shift_chain[45]),
+ .config_shift_o(_107_),
+ .pins_o(_108_),
+ .route_i({ down_tracks_out[95:80], up_tracks_out[95:80] })
+ );
+ fpga_routing_node_wcfg \vertical_routing_network_x:3.vertical_routing_network_y:2.routing_node_down (
+ .config_clk_i(config_vrnode_i[2]),
+ .config_ena_i(glb_rst_i),
+ .config_shift_i(vrnode_cfg_shift_chain[46]),
+ .config_shift_o(_109_),
+ .route_i(down_tracks_in[671:560]),
+ .route_o(_110_)
+ );
+ fpga_routing_node_wcfg \vertical_routing_network_x:3.vertical_routing_network_y:2.routing_node_up (
+ .config_clk_i(config_vrnode_i[2]),
+ .config_ena_i(glb_rst_i),
+ .config_shift_i(vrnode_cfg_shift_chain[47]),
+ .config_shift_o(_105_),
+ .route_i(up_tracks_in[671:560]),
+ .route_o(_106_)
+ );
+ fpga_io_mux \vertical_routing_network_x:3.vertical_routing_network_y:3.right_io.routing_right_io (
+ .config_clk_i(config_vrnode_i[4]),
+ .config_ena_i(glb_rst_i),
+ .config_shift_i(vrnode_cfg_shift_chain[36]),
+ .config_shift_o(_113_),
+ .pins_o(_114_),
+ .route_i({ down_tracks_out[79:64], up_tracks_out[79:64] })
+ );
+ fpga_routing_node_wcfg \vertical_routing_network_x:3.vertical_routing_network_y:3.routing_node_down (
+ .config_clk_i(config_vrnode_i[4]),
+ .config_ena_i(glb_rst_i),
+ .config_shift_i(vrnode_cfg_shift_chain[37]),
+ .config_shift_o(_115_),
+ .route_i(down_tracks_in[559:448]),
+ .route_o(_116_)
+ );
+ fpga_routing_node_wcfg \vertical_routing_network_x:3.vertical_routing_network_y:3.routing_node_up (
+ .config_clk_i(config_vrnode_i[4]),
+ .config_ena_i(glb_rst_i),
+ .config_shift_i(vrnode_cfg_shift_chain[38]),
+ .config_shift_o(_111_),
+ .route_i(up_tracks_in[559:448]),
+ .route_o(_112_)
+ );
+ fpga_io_mux \vertical_routing_network_x:3.vertical_routing_network_y:4.right_io.routing_right_io (
+ .config_clk_i(config_vrnode_i[6]),
+ .config_ena_i(glb_rst_i),
+ .config_shift_i(vrnode_cfg_shift_chain[27]),
+ .config_shift_o(_119_),
+ .pins_o(_120_),
+ .route_i({ down_tracks_out[63:48], up_tracks_out[63:48] })
+ );
+ fpga_routing_node_wcfg \vertical_routing_network_x:3.vertical_routing_network_y:4.routing_node_down (
+ .config_clk_i(config_vrnode_i[6]),
+ .config_ena_i(glb_rst_i),
+ .config_shift_i(vrnode_cfg_shift_chain[28]),
+ .config_shift_o(_121_),
+ .route_i(down_tracks_in[447:336]),
+ .route_o(_122_)
+ );
+ fpga_routing_node_wcfg \vertical_routing_network_x:3.vertical_routing_network_y:4.routing_node_up (
+ .config_clk_i(config_vrnode_i[6]),
+ .config_ena_i(glb_rst_i),
+ .config_shift_i(vrnode_cfg_shift_chain[29]),
+ .config_shift_o(_117_),
+ .route_i(up_tracks_in[447:336]),
+ .route_o(_118_)
+ );
+ fpga_io_mux \vertical_routing_network_x:3.vertical_routing_network_y:5.right_io.routing_right_io (
+ .config_clk_i(config_vrnode_i[8]),
+ .config_ena_i(glb_rst_i),
+ .config_shift_i(vrnode_cfg_shift_chain[18]),
+ .config_shift_o(_125_),
+ .pins_o(_126_),
+ .route_i({ down_tracks_out[47:32], up_tracks_out[47:32] })
+ );
+ fpga_routing_node_wcfg \vertical_routing_network_x:3.vertical_routing_network_y:5.routing_node_down (
+ .config_clk_i(config_vrnode_i[8]),
+ .config_ena_i(glb_rst_i),
+ .config_shift_i(vrnode_cfg_shift_chain[19]),
+ .config_shift_o(_127_),
+ .route_i(down_tracks_in[335:224]),
+ .route_o(_128_)
+ );
+ fpga_routing_node_wcfg \vertical_routing_network_x:3.vertical_routing_network_y:5.routing_node_up (
+ .config_clk_i(config_vrnode_i[8]),
+ .config_ena_i(glb_rst_i),
+ .config_shift_i(vrnode_cfg_shift_chain[20]),
+ .config_shift_o(_123_),
+ .route_i(up_tracks_in[335:224]),
+ .route_o(_124_)
+ );
+ fpga_io_mux \vertical_routing_network_x:3.vertical_routing_network_y:6.right_io.routing_right_io (
+ .config_clk_i(config_vrnode_i[10]),
+ .config_ena_i(glb_rst_i),
+ .config_shift_i(vrnode_cfg_shift_chain[9]),
+ .config_shift_o(_131_),
+ .pins_o(_132_),
+ .route_i({ down_tracks_out[31:16], up_tracks_out[31:16] })
+ );
+ fpga_routing_node_wcfg \vertical_routing_network_x:3.vertical_routing_network_y:6.routing_node_down (
+ .config_clk_i(config_vrnode_i[10]),
+ .config_ena_i(glb_rst_i),
+ .config_shift_i(vrnode_cfg_shift_chain[10]),
+ .config_shift_o(_133_),
+ .route_i(down_tracks_in[223:112]),
+ .route_o(_134_)
+ );
+ fpga_routing_node_wcfg \vertical_routing_network_x:3.vertical_routing_network_y:6.routing_node_up (
+ .config_clk_i(config_vrnode_i[10]),
+ .config_ena_i(glb_rst_i),
+ .config_shift_i(vrnode_cfg_shift_chain[11]),
+ .config_shift_o(_129_),
+ .route_i(up_tracks_in[223:112]),
+ .route_o(_130_)
+ );
+ fpga_io_mux \vertical_routing_network_x:3.vertical_routing_network_y:7.right_io.routing_right_io (
+ .config_clk_i(config_vrnode_i[12]),
+ .config_ena_i(glb_rst_i),
+ .config_shift_i(vrnode_cfg_shift_chain[0]),
+ .config_shift_o(_137_),
+ .pins_o(_138_),
+ .route_i({ down_tracks_out[15:0], up_tracks_out[15:0] })
+ );
+ fpga_routing_node_wcfg \vertical_routing_network_x:3.vertical_routing_network_y:7.routing_node_down (
+ .config_clk_i(config_vrnode_i[12]),
+ .config_ena_i(glb_rst_i),
+ .config_shift_i(vrnode_cfg_shift_chain[1]),
+ .config_shift_o(_139_),
+ .route_i(down_tracks_in[111:0]),
+ .route_o(_140_)
+ );
+ fpga_routing_node_wcfg \vertical_routing_network_x:3.vertical_routing_network_y:7.routing_node_up (
+ .config_clk_i(config_vrnode_i[12]),
+ .config_ena_i(glb_rst_i),
+ .config_shift_i(vrnode_cfg_shift_chain[2]),
+ .config_shift_o(_135_),
+ .route_i(up_tracks_in[111:0]),
+ .route_o(_136_)
+ );
+ assign block_out = { _002_, _004_, _006_, _008_, _010_, _012_, _014_, _016_, _018_, _020_, _022_, _024_, _026_, _028_ };
+ assign glb_rstn = _000_;
+ assign block_cfg_shift_chain = { config_block_i[1], _013_, _011_, _009_, _007_, _005_, _003_, _001_, config_block_i[3], _027_, _025_, _023_, _021_, _019_, _017_, _015_ };
+ assign hrnode_cfg_shift_chain = { _141_, \horizontal_routing_network_x:1.horizontal_routing_network_y:1.routing_node_left:31081 , \horizontal_routing_network_x:1.horizontal_routing_network_y:1.routing_node_right:31091 , \horizontal_routing_network_x:1.horizontal_routing_network_y:2.routing_node_left:32223 , \horizontal_routing_network_x:1.horizontal_routing_network_y:2.routing_node_right:32233 , \horizontal_routing_network_x:1.horizontal_routing_network_y:3.routing_node_left:33365 , \horizontal_routing_network_x:1.horizontal_routing_network_y:3.routing_node_right:33375 , \horizontal_routing_network_x:1.horizontal_routing_network_y:4.routing_node_left:34507 , \horizontal_routing_network_x:1.horizontal_routing_network_y:4.routing_node_right:34517 , \horizontal_routing_network_x:1.horizontal_routing_network_y:5.routing_node_left:35649 , \horizontal_routing_network_x:1.horizontal_routing_network_y:5.routing_node_right:35659 , \horizontal_routing_network_x:1.horizontal_routing_network_y:6.routing_node_left:36791 , \horizontal_routing_network_x:1.horizontal_routing_network_y:6.routing_node_right:36801 , \horizontal_routing_network_x:1.horizontal_routing_network_y:7.routing_node_left:37933 , \horizontal_routing_network_x:1.horizontal_routing_network_y:7.routing_node_right:37943 , \horizontal_routing_network_x:1.horizontal_routing_network_y:8.routing_node_left:37955 , \horizontal_routing_network_x:1.horizontal_routing_network_y:8.routing_node_right:39418 , _173_, config_hrnode_i[1], _177_, \horizontal_routing_network_x:2.horizontal_routing_network_y:1.routing_node_left:40886 , \horizontal_routing_network_x:2.horizontal_routing_network_y:1.routing_node_right:40896 , \horizontal_routing_network_x:2.horizontal_routing_network_y:2.routing_node_left:42028 , \horizontal_routing_network_x:2.horizontal_routing_network_y:2.routing_node_right:42038 , \horizontal_routing_network_x:2.horizontal_routing_network_y:3.routing_node_left:43170 , \horizontal_routing_network_x:2.horizontal_routing_network_y:3.routing_node_right:43180 , \horizontal_routing_network_x:2.horizontal_routing_network_y:4.routing_node_left:44312 , \horizontal_routing_network_x:2.horizontal_routing_network_y:4.routing_node_right:44322 , \horizontal_routing_network_x:2.horizontal_routing_network_y:5.routing_node_left:45454 , \horizontal_routing_network_x:2.horizontal_routing_network_y:5.routing_node_right:45464 , \horizontal_routing_network_x:2.horizontal_routing_network_y:6.routing_node_left:46596 , \horizontal_routing_network_x:2.horizontal_routing_network_y:6.routing_node_right:46606 , \horizontal_routing_network_x:2.horizontal_routing_network_y:7.routing_node_left:47738 , \horizontal_routing_network_x:2.horizontal_routing_network_y:7.routing_node_right:47748 , \horizontal_routing_network_x:2.horizontal_routing_network_y:8.routing_node_left:47760 , \horizontal_routing_network_x:2.horizontal_routing_network_y:8.routing_node_right:49223 , _209_, config_hrnode_i[3] };
+ assign vrnode_cfg_shift_chain = { _029_, \vertical_routing_network_x:1.vertical_routing_network_y:1.routing_node_up:2416 , \vertical_routing_network_x:1.vertical_routing_network_y:1.routing_node_down:2426 , \vertical_routing_network_x:2.vertical_routing_network_y:1.routing_node_up:12426 , \vertical_routing_network_x:2.vertical_routing_network_y:1.routing_node_down:12436 , \vertical_routing_network_x:3.vertical_routing_network_y:1.routing_node_up:19300 , \vertical_routing_network_x:3.vertical_routing_network_y:1.routing_node_down:20763 , _101_, config_vrnode_i[1], _035_, \vertical_routing_network_x:1.vertical_routing_network_y:2.routing_node_up:3894 , \vertical_routing_network_x:1.vertical_routing_network_y:2.routing_node_down:3904 , \vertical_routing_network_x:2.vertical_routing_network_y:2.routing_node_up:13568 , \vertical_routing_network_x:2.vertical_routing_network_y:2.routing_node_down:13578 , \vertical_routing_network_x:3.vertical_routing_network_y:2.routing_node_up:20775 , \vertical_routing_network_x:3.vertical_routing_network_y:2.routing_node_down:22238 , _107_, config_vrnode_i[3], _041_, \vertical_routing_network_x:1.vertical_routing_network_y:3.routing_node_up:5372 , \vertical_routing_network_x:1.vertical_routing_network_y:3.routing_node_down:5382 , \vertical_routing_network_x:2.vertical_routing_network_y:3.routing_node_up:14710 , \vertical_routing_network_x:2.vertical_routing_network_y:3.routing_node_down:14720 , \vertical_routing_network_x:3.vertical_routing_network_y:3.routing_node_up:22250 , \vertical_routing_network_x:3.vertical_routing_network_y:3.routing_node_down:23713 , _113_, config_vrnode_i[5], _047_, \vertical_routing_network_x:1.vertical_routing_network_y:4.routing_node_up:6850 , \vertical_routing_network_x:1.vertical_routing_network_y:4.routing_node_down:6860 , \vertical_routing_network_x:2.vertical_routing_network_y:4.routing_node_up:15852 , \vertical_routing_network_x:2.vertical_routing_network_y:4.routing_node_down:15862 , \vertical_routing_network_x:3.vertical_routing_network_y:4.routing_node_up:23725 , \vertical_routing_network_x:3.vertical_routing_network_y:4.routing_node_down:25188 , _119_, config_vrnode_i[7], _053_, \vertical_routing_network_x:1.vertical_routing_network_y:5.routing_node_up:8328 , \vertical_routing_network_x:1.vertical_routing_network_y:5.routing_node_down:8338 , \vertical_routing_network_x:2.vertical_routing_network_y:5.routing_node_up:16994 , \vertical_routing_network_x:2.vertical_routing_network_y:5.routing_node_down:17004 , \vertical_routing_network_x:3.vertical_routing_network_y:5.routing_node_up:25200 , \vertical_routing_network_x:3.vertical_routing_network_y:5.routing_node_down:26663 , _125_, config_vrnode_i[9], _059_, \vertical_routing_network_x:1.vertical_routing_network_y:6.routing_node_up:9806 , \vertical_routing_network_x:1.vertical_routing_network_y:6.routing_node_down:9816 , \vertical_routing_network_x:2.vertical_routing_network_y:6.routing_node_up:18136 , \vertical_routing_network_x:2.vertical_routing_network_y:6.routing_node_down:18146 , \vertical_routing_network_x:3.vertical_routing_network_y:6.routing_node_up:26675 , \vertical_routing_network_x:3.vertical_routing_network_y:6.routing_node_down:28138 , _131_, config_vrnode_i[11], _065_, \vertical_routing_network_x:1.vertical_routing_network_y:7.routing_node_up:11284 , \vertical_routing_network_x:1.vertical_routing_network_y:7.routing_node_down:11294 , \vertical_routing_network_x:2.vertical_routing_network_y:7.routing_node_up:19278 , \vertical_routing_network_x:2.vertical_routing_network_y:7.routing_node_down:19288 , \vertical_routing_network_x:3.vertical_routing_network_y:7.routing_node_up:28150 , \vertical_routing_network_x:3.vertical_routing_network_y:7.routing_node_down:29613 , _137_, config_vrnode_i[13] };
+ assign up_tracks_in = { left_tracks_out[241], 1'h0, up_tracks_fwd[320], block_out[111], block_out[107], 1'h0, inputs_i[0], left_tracks_out[242], 1'h0, up_tracks_fwd[321], block_out[111], block_out[107], 1'h0, inputs_i[0], left_tracks_out[243], 1'h0, up_tracks_fwd[322], block_out[111], block_out[107], 1'h0, inputs_i[1], left_tracks_out[244], 1'h0, up_tracks_fwd[323], block_out[111], block_out[107], 1'h0, inputs_i[1], left_tracks_out[245], 1'h0, up_tracks_fwd[324], block_out[111], block_out[107], 1'h0, inputs_i[2], left_tracks_out[246], 1'h0, up_tracks_fwd[325], block_out[111], block_out[107], 1'h0, inputs_i[2], left_tracks_out[247], 1'h0, up_tracks_fwd[326], block_out[111], block_out[107], 1'h0, inputs_i[3], left_tracks_out[248], 1'h0, up_tracks_fwd[327], block_out[111], block_out[107], 1'h0, inputs_i[3], left_tracks_out[249], 1'h0, up_tracks_fwd[328], block_out[111], block_out[107], 1'h0, inputs_i[4], left_tracks_out[250], 1'h0, up_tracks_fwd[329], block_out[111], block_out[107], 1'h0, inputs_i[4], left_tracks_out[251], 1'h0, up_tracks_fwd[330], block_out[111], block_out[107], 1'h0, inputs_i[5], left_tracks_out[252], 1'h0, up_tracks_fwd[331], block_out[111], block_out[107], 1'h0, inputs_i[5], left_tracks_out[253], 1'h0, up_tracks_fwd[332], block_out[111], block_out[107], 1'h0, inputs_i[6], left_tracks_out[254], 1'h0, up_tracks_fwd[333], block_out[111], block_out[107], 1'h0, inputs_i[6], left_tracks_out[255], 1'h0, up_tracks_fwd[334], block_out[111], block_out[107], 1'h0, inputs_i[7], left_tracks_out[240], 1'h0, up_tracks_fwd[335], block_out[111], block_out[107], 1'h0, inputs_i[7], left_tracks_out[225], 1'h0, up_tracks_fwd[304], block_out[103], block_out[99], 1'h0, inputs_i[8], left_tracks_out[226], 1'h0, up_tracks_fwd[305], block_out[103], block_out[99], 1'h0, inputs_i[8], left_tracks_out[227], 1'h0, up_tracks_fwd[306], block_out[103], block_out[99], 1'h0, inputs_i[9], left_tracks_out[228], 1'h0, up_tracks_fwd[307], block_out[103], block_out[99], 1'h0, inputs_i[9], left_tracks_out[229], 1'h0, up_tracks_fwd[308], block_out[103], block_out[99], 1'h0, inputs_i[10], left_tracks_out[230], 1'h0, up_tracks_fwd[309], block_out[103], block_out[99], 1'h0, inputs_i[10], left_tracks_out[231], 1'h0, up_tracks_fwd[310], block_out[103], block_out[99], 1'h0, inputs_i[11], left_tracks_out[232], 1'h0, up_tracks_fwd[311], block_out[103], block_out[99], 1'h0, inputs_i[11], left_tracks_out[233], 1'h0, up_tracks_fwd[312], block_out[103], block_out[99], 1'h0, inputs_i[12], left_tracks_out[234], 1'h0, up_tracks_fwd[313], block_out[103], block_out[99], 1'h0, inputs_i[12], left_tracks_out[235], 1'h0, up_tracks_fwd[314], block_out[103], block_out[99], 1'h0, inputs_i[13], left_tracks_out[236], 1'h0, up_tracks_fwd[315], block_out[103], block_out[99], 1'h0, inputs_i[13], left_tracks_out[237], 1'h0, up_tracks_fwd[316], block_out[103], block_out[99], 1'h0, inputs_i[14], left_tracks_out[238], 1'h0, up_tracks_fwd[317], block_out[103], block_out[99], 1'h0, inputs_i[14], left_tracks_out[239], 1'h0, up_tracks_fwd[318], block_out[103], block_out[99], 1'h0, inputs_i[15], left_tracks_out[224], 1'h0, up_tracks_fwd[319], block_out[103], block_out[99], 1'h0, inputs_i[15], left_tracks_out[209], 1'h0, up_tracks_fwd[288], block_out[95], block_out[91], 1'h0, inputs_i[16], left_tracks_out[210], 1'h0, up_tracks_fwd[289], block_out[95], block_out[91], 1'h0, inputs_i[16], left_tracks_out[211], 1'h0, up_tracks_fwd[290], block_out[95], block_out[91], 1'h0, inputs_i[17], left_tracks_out[212], 1'h0, up_tracks_fwd[291], block_out[95], block_out[91], 1'h0, inputs_i[17], left_tracks_out[213], 1'h0, up_tracks_fwd[292], block_out[95], block_out[91], 1'h0, inputs_i[18], left_tracks_out[214], 1'h0, up_tracks_fwd[293], block_out[95], block_out[91], 1'h0, inputs_i[18], left_tracks_out[215], 1'h0, up_tracks_fwd[294], block_out[95], block_out[91], 1'h0, inputs_i[19], left_tracks_out[216], 1'h0, up_tracks_fwd[295], block_out[95], block_out[91], 1'h0, inputs_i[19], left_tracks_out[217], 1'h0, up_tracks_fwd[296], block_out[95], block_out[91], 1'h0, inputs_i[20], left_tracks_out[218], 1'h0, up_tracks_fwd[297], block_out[95], block_out[91], 1'h0, inputs_i[20], left_tracks_out[219], 1'h0, up_tracks_fwd[298], block_out[95], block_out[91], 1'h0, inputs_i[21], left_tracks_out[220], 1'h0, up_tracks_fwd[299], block_out[95], block_out[91], 1'h0, inputs_i[21], left_tracks_out[221], 1'h0, up_tracks_fwd[300], block_out[95], block_out[91], 1'h0, inputs_i[22], left_tracks_out[222], 1'h0, up_tracks_fwd[301], block_out[95], block_out[91], 1'h0, inputs_i[22], left_tracks_out[223], 1'h0, up_tracks_fwd[302], block_out[95], block_out[91], 1'h0, inputs_i[23], left_tracks_out[208], 1'h0, up_tracks_fwd[303], block_out[95], block_out[91], 1'h0, inputs_i[23], left_tracks_out[193], 1'h0, up_tracks_fwd[272], block_out[87], block_out[83], 1'h0, inputs_i[24], left_tracks_out[194], 1'h0, up_tracks_fwd[273], block_out[87], block_out[83], 1'h0, inputs_i[24], left_tracks_out[195], 1'h0, up_tracks_fwd[274], block_out[87], block_out[83], 1'h0, inputs_i[25], left_tracks_out[196], 1'h0, up_tracks_fwd[275], block_out[87], block_out[83], 1'h0, inputs_i[25], left_tracks_out[197], 1'h0, up_tracks_fwd[276], block_out[87], block_out[83], 1'h0, inputs_i[26], left_tracks_out[198], 1'h0, up_tracks_fwd[277], block_out[87], block_out[83], 1'h0, inputs_i[26], left_tracks_out[199], 1'h0, up_tracks_fwd[278], block_out[87], block_out[83], 1'h0, inputs_i[27], left_tracks_out[200], 1'h0, up_tracks_fwd[279], block_out[87], block_out[83], 1'h0, inputs_i[27], left_tracks_out[201], 1'h0, up_tracks_fwd[280], block_out[87], block_out[83], 1'h0, inputs_i[28], left_tracks_out[202], 1'h0, up_tracks_fwd[281], block_out[87], block_out[83], 1'h0, inputs_i[28], left_tracks_out[203], 1'h0, up_tracks_fwd[282], block_out[87], block_out[83], 1'h0, inputs_i[29], left_tracks_out[204], 1'h0, up_tracks_fwd[283], block_out[87], block_out[83], 1'h0, inputs_i[29], left_tracks_out[205], 1'h0, up_tracks_fwd[284], block_out[87], block_out[83], 1'h0, inputs_i[30], left_tracks_out[206], 1'h0, up_tracks_fwd[285], block_out[87], block_out[83], 1'h0, inputs_i[30], left_tracks_out[207], 1'h0, up_tracks_fwd[286], block_out[87], block_out[83], 1'h0, inputs_i[31], left_tracks_out[192], 1'h0, up_tracks_fwd[287], block_out[87], block_out[83], 1'h0, inputs_i[31], left_tracks_out[177], 1'h0, up_tracks_fwd[256], block_out[79], block_out[75], 1'h0, inputs_i[32], left_tracks_out[178], 1'h0, up_tracks_fwd[257], block_out[79], block_out[75], 1'h0, inputs_i[32], left_tracks_out[179], 1'h0, up_tracks_fwd[258], block_out[79], block_out[75], 1'h0, inputs_i[33], left_tracks_out[180], 1'h0, up_tracks_fwd[259], block_out[79], block_out[75], 1'h0, inputs_i[33], left_tracks_out[181], 1'h0, up_tracks_fwd[260], block_out[79], block_out[75], 1'h0, inputs_i[34], left_tracks_out[182], 1'h0, up_tracks_fwd[261], block_out[79], block_out[75], 1'h0, inputs_i[34], left_tracks_out[183], 1'h0, up_tracks_fwd[262], block_out[79], block_out[75], 1'h0, inputs_i[35], left_tracks_out[184], 1'h0, up_tracks_fwd[263], block_out[79], block_out[75], 1'h0, inputs_i[35], left_tracks_out[185], 1'h0, up_tracks_fwd[264], block_out[79], block_out[75], 1'h0, inputs_i[36], left_tracks_out[186], 1'h0, up_tracks_fwd[265], block_out[79], block_out[75], 1'h0, inputs_i[36], left_tracks_out[187], 1'h0, up_tracks_fwd[266], block_out[79], block_out[75], 1'h0, inputs_i[37], left_tracks_out[188], 1'h0, up_tracks_fwd[267], block_out[79], block_out[75], 1'h0, inputs_i[37], left_tracks_out[189], 1'h0, up_tracks_fwd[268], block_out[79], block_out[75], 1'h0, inputs_i[38], left_tracks_out[190], 1'h0, up_tracks_fwd[269], block_out[79], block_out[75], 1'h0, inputs_i[38], left_tracks_out[191], 1'h0, up_tracks_fwd[270], block_out[79], block_out[75], 1'h0, inputs_i[39], left_tracks_out[176], 1'h0, up_tracks_fwd[271], block_out[79], block_out[75], 1'h0, inputs_i[39], left_tracks_out[161], 1'h0, up_tracks_fwd[240], block_out[71], block_out[67], 1'h0, inputs_i[40], left_tracks_out[162], 1'h0, up_tracks_fwd[241], block_out[71], block_out[67], 1'h0, inputs_i[40], left_tracks_out[163], 1'h0, up_tracks_fwd[242], block_out[71], block_out[67], 1'h0, inputs_i[41], left_tracks_out[164], 1'h0, up_tracks_fwd[243], block_out[71], block_out[67], 1'h0, inputs_i[41], left_tracks_out[165], 1'h0, up_tracks_fwd[244], block_out[71], block_out[67], 1'h0, inputs_i[42], left_tracks_out[166], 1'h0, up_tracks_fwd[245], block_out[71], block_out[67], 1'h0, inputs_i[42], left_tracks_out[167], 1'h0, up_tracks_fwd[246], block_out[71], block_out[67], 1'h0, inputs_i[43], left_tracks_out[168], 1'h0, up_tracks_fwd[247], block_out[71], block_out[67], 1'h0, inputs_i[43], left_tracks_out[169], 1'h0, up_tracks_fwd[248], block_out[71], block_out[67], 1'h0, inputs_i[44], left_tracks_out[170], 1'h0, up_tracks_fwd[249], block_out[71], block_out[67], 1'h0, inputs_i[44], left_tracks_out[171], 1'h0, up_tracks_fwd[250], block_out[71], block_out[67], 1'h0, inputs_i[45], left_tracks_out[172], 1'h0, up_tracks_fwd[251], block_out[71], block_out[67], 1'h0, inputs_i[45], left_tracks_out[173], 1'h0, up_tracks_fwd[252], block_out[71], block_out[67], 1'h0, inputs_i[46], left_tracks_out[174], 1'h0, up_tracks_fwd[253], block_out[71], block_out[67], 1'h0, inputs_i[46], left_tracks_out[175], 1'h0, up_tracks_fwd[254], block_out[71], block_out[67], 1'h0, inputs_i[47], left_tracks_out[160], 1'h0, up_tracks_fwd[255], block_out[71], block_out[67], 1'h0, inputs_i[47], left_tracks_out[145], 1'h0, up_tracks_fwd[224], block_out[63], block_out[59], 1'h0, inputs_i[48], left_tracks_out[146], 1'h0, up_tracks_fwd[225], block_out[63], block_out[59], 1'h0, inputs_i[48], left_tracks_out[147], 1'h0, up_tracks_fwd[226], block_out[63], block_out[59], 1'h0, inputs_i[49], left_tracks_out[148], 1'h0, up_tracks_fwd[227], block_out[63], block_out[59], 1'h0, inputs_i[49], left_tracks_out[149], 1'h0, up_tracks_fwd[228], block_out[63], block_out[59], 1'h0, inputs_i[50], left_tracks_out[150], 1'h0, up_tracks_fwd[229], block_out[63], block_out[59], 1'h0, inputs_i[50], left_tracks_out[151], 1'h0, up_tracks_fwd[230], block_out[63], block_out[59], 1'h0, inputs_i[51], left_tracks_out[152], 1'h0, up_tracks_fwd[231], block_out[63], block_out[59], 1'h0, inputs_i[51], left_tracks_out[153], 1'h0, up_tracks_fwd[232], block_out[63], block_out[59], 1'h0, inputs_i[52], left_tracks_out[154], 1'h0, up_tracks_fwd[233], block_out[63], block_out[59], 1'h0, inputs_i[52], left_tracks_out[155], 1'h0, up_tracks_fwd[234], block_out[63], block_out[59], 1'h0, inputs_i[53], left_tracks_out[156], 1'h0, up_tracks_fwd[235], block_out[63], block_out[59], 1'h0, inputs_i[53], left_tracks_out[157], 1'h0, up_tracks_fwd[236], block_out[63], block_out[59], 1'h0, inputs_i[54], left_tracks_out[158], 1'h0, up_tracks_fwd[237], block_out[63], block_out[59], 1'h0, inputs_i[54], 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inputs_i[75], block_out[53], block_out[49], 1'h0, right_tracks_out[120], up_tracks_fwd[104], 1'h0, inputs_i[76], block_out[53], block_out[49], 1'h0, right_tracks_out[119], up_tracks_fwd[105], 1'h0, inputs_i[76], block_out[53], block_out[49], 1'h0, right_tracks_out[118], up_tracks_fwd[106], 1'h0, inputs_i[77], block_out[53], block_out[49], 1'h0, right_tracks_out[117], up_tracks_fwd[107], 1'h0, inputs_i[77], block_out[53], block_out[49], 1'h0, right_tracks_out[116], up_tracks_fwd[108], 1'h0, inputs_i[78], block_out[53], block_out[49], 1'h0, right_tracks_out[115], up_tracks_fwd[109], 1'h0, inputs_i[78], block_out[53], block_out[49], 1'h0, right_tracks_out[114], up_tracks_fwd[110], 1'h0, inputs_i[79], block_out[53], block_out[49], 1'h0, right_tracks_out[113], up_tracks_fwd[111], 1'h0, inputs_i[79], block_out[53], block_out[49], 1'h0, right_tracks_out[96], up_tracks_fwd[80], 1'h0, inputs_i[80], block_out[45], block_out[41], 1'h0, right_tracks_out[111], up_tracks_fwd[81], 1'h0, inputs_i[80], block_out[45], block_out[41], 1'h0, right_tracks_out[110], up_tracks_fwd[82], 1'h0, inputs_i[81], block_out[45], block_out[41], 1'h0, right_tracks_out[109], up_tracks_fwd[83], 1'h0, inputs_i[81], block_out[45], block_out[41], 1'h0, right_tracks_out[108], up_tracks_fwd[84], 1'h0, inputs_i[82], block_out[45], block_out[41], 1'h0, right_tracks_out[107], up_tracks_fwd[85], 1'h0, inputs_i[82], block_out[45], block_out[41], 1'h0, right_tracks_out[106], up_tracks_fwd[86], 1'h0, inputs_i[83], block_out[45], block_out[41], 1'h0, right_tracks_out[105], up_tracks_fwd[87], 1'h0, inputs_i[83], block_out[45], block_out[41], 1'h0, right_tracks_out[104], up_tracks_fwd[88], 1'h0, inputs_i[84], block_out[45], block_out[41], 1'h0, right_tracks_out[103], up_tracks_fwd[89], 1'h0, inputs_i[84], block_out[45], block_out[41], 1'h0, right_tracks_out[102], up_tracks_fwd[90], 1'h0, inputs_i[85], block_out[45], block_out[41], 1'h0, right_tracks_out[101], up_tracks_fwd[91], 1'h0, inputs_i[85], block_out[45], block_out[41], 1'h0, right_tracks_out[100], up_tracks_fwd[92], 1'h0, inputs_i[86], block_out[45], block_out[41], 1'h0, right_tracks_out[99], up_tracks_fwd[93], 1'h0, inputs_i[86], block_out[45], block_out[41], 1'h0, right_tracks_out[98], up_tracks_fwd[94], 1'h0, inputs_i[87], block_out[45], block_out[41], 1'h0, right_tracks_out[97], up_tracks_fwd[95], 1'h0, inputs_i[87], block_out[45], block_out[41], 1'h0, right_tracks_out[80], up_tracks_fwd[64], 1'h0, inputs_i[88], block_out[37], block_out[33], 1'h0, right_tracks_out[95], up_tracks_fwd[65], 1'h0, inputs_i[88], block_out[37], block_out[33], 1'h0, right_tracks_out[94], up_tracks_fwd[66], 1'h0, inputs_i[89], block_out[37], block_out[33], 1'h0, right_tracks_out[93], up_tracks_fwd[67], 1'h0, inputs_i[89], block_out[37], block_out[33], 1'h0, right_tracks_out[92], up_tracks_fwd[68], 1'h0, inputs_i[90], block_out[37], block_out[33], 1'h0, right_tracks_out[91], up_tracks_fwd[69], 1'h0, inputs_i[90], block_out[37], block_out[33], 1'h0, right_tracks_out[90], up_tracks_fwd[70], 1'h0, inputs_i[91], block_out[37], block_out[33], 1'h0, right_tracks_out[89], up_tracks_fwd[71], 1'h0, inputs_i[91], block_out[37], block_out[33], 1'h0, right_tracks_out[88], up_tracks_fwd[72], 1'h0, inputs_i[92], block_out[37], block_out[33], 1'h0, right_tracks_out[87], up_tracks_fwd[73], 1'h0, inputs_i[92], block_out[37], block_out[33], 1'h0, right_tracks_out[86], up_tracks_fwd[74], 1'h0, inputs_i[93], block_out[37], block_out[33], 1'h0, right_tracks_out[85], up_tracks_fwd[75], 1'h0, inputs_i[93], block_out[37], block_out[33], 1'h0, right_tracks_out[84], up_tracks_fwd[76], 1'h0, inputs_i[94], block_out[37], block_out[33], 1'h0, right_tracks_out[83], up_tracks_fwd[77], 1'h0, inputs_i[94], block_out[37], block_out[33], 1'h0, right_tracks_out[82], up_tracks_fwd[78], 1'h0, inputs_i[95], block_out[37], block_out[33], 1'h0, right_tracks_out[81], up_tracks_fwd[79], 1'h0, inputs_i[95], block_out[37], block_out[33], 1'h0, right_tracks_out[64], up_tracks_fwd[48], 1'h0, inputs_i[96], block_out[29], block_out[25], 1'h0, right_tracks_out[79], up_tracks_fwd[49], 1'h0, inputs_i[96], block_out[29], block_out[25], 1'h0, right_tracks_out[78], up_tracks_fwd[50], 1'h0, inputs_i[97], block_out[29], block_out[25], 1'h0, right_tracks_out[77], up_tracks_fwd[51], 1'h0, inputs_i[97], block_out[29], block_out[25], 1'h0, right_tracks_out[76], up_tracks_fwd[52], 1'h0, inputs_i[98], block_out[29], block_out[25], 1'h0, right_tracks_out[75], up_tracks_fwd[53], 1'h0, inputs_i[98], block_out[29], block_out[25], 1'h0, right_tracks_out[74], up_tracks_fwd[54], 1'h0, inputs_i[99], block_out[29], block_out[25], 1'h0, right_tracks_out[73], up_tracks_fwd[55], 1'h0, inputs_i[99], block_out[29], block_out[25], 1'h0, right_tracks_out[72], up_tracks_fwd[56], 1'h0, inputs_i[100], block_out[29], block_out[25], 1'h0, right_tracks_out[71], up_tracks_fwd[57], 1'h0, inputs_i[100], block_out[29], block_out[25], 1'h0, right_tracks_out[70], up_tracks_fwd[58], 1'h0, inputs_i[101], block_out[29], block_out[25], 1'h0, right_tracks_out[69], up_tracks_fwd[59], 1'h0, inputs_i[101], block_out[29], block_out[25], 1'h0, right_tracks_out[68], up_tracks_fwd[60], 1'h0, inputs_i[102], block_out[29], block_out[25], 1'h0, right_tracks_out[67], up_tracks_fwd[61], 1'h0, inputs_i[102], block_out[29], block_out[25], 1'h0, right_tracks_out[66], up_tracks_fwd[62], 1'h0, inputs_i[103], block_out[29], block_out[25], 1'h0, right_tracks_out[65], up_tracks_fwd[63], 1'h0, inputs_i[103], block_out[29], block_out[25], 1'h0, right_tracks_out[48], up_tracks_fwd[32], 1'h0, inputs_i[104], block_out[21], block_out[17], 1'h0, right_tracks_out[63], up_tracks_fwd[33], 1'h0, inputs_i[104], block_out[21], block_out[17], 1'h0, right_tracks_out[62], up_tracks_fwd[34], 1'h0, inputs_i[105], block_out[21], block_out[17], 1'h0, right_tracks_out[61], up_tracks_fwd[35], 1'h0, inputs_i[105], block_out[21], block_out[17], 1'h0, right_tracks_out[60], up_tracks_fwd[36], 1'h0, inputs_i[106], block_out[21], block_out[17], 1'h0, right_tracks_out[59], up_tracks_fwd[37], 1'h0, inputs_i[106], block_out[21], block_out[17], 1'h0, right_tracks_out[58], up_tracks_fwd[38], 1'h0, inputs_i[107], block_out[21], block_out[17], 1'h0, right_tracks_out[57], up_tracks_fwd[39], 1'h0, inputs_i[107], block_out[21], block_out[17], 1'h0, right_tracks_out[56], up_tracks_fwd[40], 1'h0, inputs_i[108], block_out[21], block_out[17], 1'h0, right_tracks_out[55], up_tracks_fwd[41], 1'h0, inputs_i[108], block_out[21], block_out[17], 1'h0, right_tracks_out[54], up_tracks_fwd[42], 1'h0, inputs_i[109], block_out[21], block_out[17], 1'h0, right_tracks_out[53], up_tracks_fwd[43], 1'h0, inputs_i[109], block_out[21], block_out[17], 1'h0, right_tracks_out[52], up_tracks_fwd[44], 1'h0, inputs_i[110], block_out[21], block_out[17], 1'h0, right_tracks_out[51], up_tracks_fwd[45], 1'h0, inputs_i[110], block_out[21], block_out[17], 1'h0, right_tracks_out[50], up_tracks_fwd[46], 1'h0, inputs_i[111], block_out[21], block_out[17], 1'h0, right_tracks_out[49], up_tracks_fwd[47], 1'h0, inputs_i[111], block_out[21], block_out[17], 1'h0, right_tracks_out[32], up_tracks_fwd[16], 1'h0, inputs_i[112], block_out[13], block_out[9], 1'h0, right_tracks_out[47], up_tracks_fwd[17], 1'h0, inputs_i[112], block_out[13], block_out[9], 1'h0, right_tracks_out[46], up_tracks_fwd[18], 1'h0, inputs_i[113], block_out[13], block_out[9], 1'h0, right_tracks_out[45], up_tracks_fwd[19], 1'h0, inputs_i[113], block_out[13], block_out[9], 1'h0, right_tracks_out[44], up_tracks_fwd[20], 1'h0, inputs_i[114], block_out[13], block_out[9], 1'h0, right_tracks_out[43], up_tracks_fwd[21], 1'h0, inputs_i[114], block_out[13], block_out[9], 1'h0, right_tracks_out[42], up_tracks_fwd[22], 1'h0, inputs_i[115], block_out[13], block_out[9], 1'h0, right_tracks_out[41], up_tracks_fwd[23], 1'h0, inputs_i[115], block_out[13], block_out[9], 1'h0, right_tracks_out[40], up_tracks_fwd[24], 1'h0, inputs_i[116], block_out[13], block_out[9], 1'h0, right_tracks_out[39], up_tracks_fwd[25], 1'h0, inputs_i[116], block_out[13], block_out[9], 1'h0, right_tracks_out[38], up_tracks_fwd[26], 1'h0, inputs_i[117], block_out[13], block_out[9], 1'h0, right_tracks_out[37], up_tracks_fwd[27], 1'h0, inputs_i[117], block_out[13], block_out[9], 1'h0, right_tracks_out[36], up_tracks_fwd[28], 1'h0, inputs_i[118], block_out[13], block_out[9], 1'h0, right_tracks_out[35], up_tracks_fwd[29], 1'h0, inputs_i[118], block_out[13], block_out[9], 1'h0, right_tracks_out[34], up_tracks_fwd[30], 1'h0, inputs_i[119], block_out[13], block_out[9], 1'h0, right_tracks_out[33], up_tracks_fwd[31], 1'h0, inputs_i[119], block_out[13], block_out[9], 1'h0, right_tracks_out[16], up_tracks_fwd[0], 1'h0, inputs_i[120], block_out[5], block_out[1], 1'h0, right_tracks_out[31], up_tracks_fwd[1], 1'h0, inputs_i[120], block_out[5], block_out[1], 1'h0, right_tracks_out[30], up_tracks_fwd[2], 1'h0, inputs_i[121], block_out[5], block_out[1], 1'h0, right_tracks_out[29], up_tracks_fwd[3], 1'h0, inputs_i[121], block_out[5], block_out[1], 1'h0, right_tracks_out[28], up_tracks_fwd[4], 1'h0, inputs_i[122], block_out[5], block_out[1], 1'h0, right_tracks_out[27], up_tracks_fwd[5], 1'h0, inputs_i[122], block_out[5], block_out[1], 1'h0, right_tracks_out[26], up_tracks_fwd[6], 1'h0, inputs_i[123], block_out[5], block_out[1], 1'h0, right_tracks_out[25], up_tracks_fwd[7], 1'h0, inputs_i[123], block_out[5], block_out[1], 1'h0, right_tracks_out[24], up_tracks_fwd[8], 1'h0, inputs_i[124], block_out[5], block_out[1], 1'h0, right_tracks_out[23], up_tracks_fwd[9], 1'h0, inputs_i[124], block_out[5], block_out[1], 1'h0, right_tracks_out[22], up_tracks_fwd[10], 1'h0, inputs_i[125], block_out[5], block_out[1], 1'h0, right_tracks_out[21], up_tracks_fwd[11], 1'h0, inputs_i[125], block_out[5], block_out[1], 1'h0, right_tracks_out[20], up_tracks_fwd[12], 1'h0, inputs_i[126], block_out[5], block_out[1], 1'h0, right_tracks_out[19], up_tracks_fwd[13], 1'h0, inputs_i[126], block_out[5], block_out[1], 1'h0, right_tracks_out[18], up_tracks_fwd[14], 1'h0, inputs_i[127], block_out[5], block_out[1], 1'h0, right_tracks_out[17], up_tracks_fwd[15], 1'h0, inputs_i[127], block_out[5], block_out[1] };
+ assign up_tracks_out = { \vertical_routing_network_x:1.vertical_routing_network_y:1.routing_node_up:2418 , \vertical_routing_network_x:1.vertical_routing_network_y:2.routing_node_up:3896 , \vertical_routing_network_x:1.vertical_routing_network_y:3.routing_node_up:5374 , \vertical_routing_network_x:1.vertical_routing_network_y:4.routing_node_up:6852 , \vertical_routing_network_x:1.vertical_routing_network_y:5.routing_node_up:8330 , \vertical_routing_network_x:1.vertical_routing_network_y:6.routing_node_up:9808 , \vertical_routing_network_x:1.vertical_routing_network_y:7.routing_node_up:11286 , \vertical_routing_network_x:2.vertical_routing_network_y:1.routing_node_up:12428 , \vertical_routing_network_x:2.vertical_routing_network_y:2.routing_node_up:13570 , \vertical_routing_network_x:2.vertical_routing_network_y:3.routing_node_up:14712 , \vertical_routing_network_x:2.vertical_routing_network_y:4.routing_node_up:15854 , \vertical_routing_network_x:2.vertical_routing_network_y:5.routing_node_up:16996 , \vertical_routing_network_x:2.vertical_routing_network_y:6.routing_node_up:18138 , \vertical_routing_network_x:2.vertical_routing_network_y:7.routing_node_up:19280 , \vertical_routing_network_x:3.vertical_routing_network_y:1.routing_node_up:19302 , \vertical_routing_network_x:3.vertical_routing_network_y:2.routing_node_up:20777 , \vertical_routing_network_x:3.vertical_routing_network_y:3.routing_node_up:22252 , \vertical_routing_network_x:3.vertical_routing_network_y:4.routing_node_up:23727 , \vertical_routing_network_x:3.vertical_routing_network_y:5.routing_node_up:25202 , \vertical_routing_network_x:3.vertical_routing_network_y:6.routing_node_up:26677 , \vertical_routing_network_x:3.vertical_routing_network_y:7.routing_node_up:28152 };
+ assign down_tracks_in = { 1'h0, left_tracks_out[238], down_tracks_fwd[320], block_out[111], block_out[107], 1'h0, inputs_i[0], 1'h0, left_tracks_out[237], down_tracks_fwd[321], block_out[111], block_out[107], 1'h0, inputs_i[0], 1'h0, left_tracks_out[236], down_tracks_fwd[322], block_out[111], block_out[107], 1'h0, inputs_i[1], 1'h0, left_tracks_out[235], down_tracks_fwd[323], block_out[111], block_out[107], 1'h0, inputs_i[1], 1'h0, left_tracks_out[234], down_tracks_fwd[324], block_out[111], block_out[107], 1'h0, inputs_i[2], 1'h0, left_tracks_out[233], down_tracks_fwd[325], block_out[111], block_out[107], 1'h0, inputs_i[2], 1'h0, left_tracks_out[232], down_tracks_fwd[326], block_out[111], block_out[107], 1'h0, inputs_i[3], 1'h0, left_tracks_out[231], down_tracks_fwd[327], block_out[111], block_out[107], 1'h0, inputs_i[3], 1'h0, left_tracks_out[230], down_tracks_fwd[328], block_out[111], block_out[107], 1'h0, inputs_i[4], 1'h0, left_tracks_out[229], down_tracks_fwd[329], block_out[111], block_out[107], 1'h0, inputs_i[4], 1'h0, left_tracks_out[228], down_tracks_fwd[330], block_out[111], block_out[107], 1'h0, inputs_i[5], 1'h0, left_tracks_out[227], down_tracks_fwd[331], block_out[111], block_out[107], 1'h0, inputs_i[5], 1'h0, left_tracks_out[226], down_tracks_fwd[332], block_out[111], block_out[107], 1'h0, inputs_i[6], 1'h0, left_tracks_out[225], down_tracks_fwd[333], block_out[111], block_out[107], 1'h0, inputs_i[6], 1'h0, left_tracks_out[224], down_tracks_fwd[334], block_out[111], block_out[107], 1'h0, inputs_i[7], 1'h0, left_tracks_out[239], down_tracks_fwd[335], block_out[111], block_out[107], 1'h0, inputs_i[7], 1'h0, left_tracks_out[222], down_tracks_fwd[304], block_out[103], block_out[99], 1'h0, inputs_i[8], 1'h0, left_tracks_out[221], down_tracks_fwd[305], block_out[103], block_out[99], 1'h0, inputs_i[8], 1'h0, left_tracks_out[220], down_tracks_fwd[306], block_out[103], block_out[99], 1'h0, inputs_i[9], 1'h0, left_tracks_out[219], down_tracks_fwd[307], block_out[103], block_out[99], 1'h0, inputs_i[9], 1'h0, left_tracks_out[218], down_tracks_fwd[308], block_out[103], block_out[99], 1'h0, inputs_i[10], 1'h0, left_tracks_out[217], down_tracks_fwd[309], block_out[103], block_out[99], 1'h0, inputs_i[10], 1'h0, left_tracks_out[216], down_tracks_fwd[310], block_out[103], block_out[99], 1'h0, inputs_i[11], 1'h0, left_tracks_out[215], down_tracks_fwd[311], block_out[103], block_out[99], 1'h0, inputs_i[11], 1'h0, left_tracks_out[214], down_tracks_fwd[312], block_out[103], block_out[99], 1'h0, inputs_i[12], 1'h0, left_tracks_out[213], down_tracks_fwd[313], block_out[103], block_out[99], 1'h0, inputs_i[12], 1'h0, left_tracks_out[212], down_tracks_fwd[314], block_out[103], block_out[99], 1'h0, inputs_i[13], 1'h0, left_tracks_out[211], down_tracks_fwd[315], block_out[103], block_out[99], 1'h0, inputs_i[13], 1'h0, left_tracks_out[210], down_tracks_fwd[316], block_out[103], block_out[99], 1'h0, inputs_i[14], 1'h0, left_tracks_out[209], down_tracks_fwd[317], block_out[103], block_out[99], 1'h0, inputs_i[14], 1'h0, left_tracks_out[208], down_tracks_fwd[318], block_out[103], block_out[99], 1'h0, inputs_i[15], 1'h0, left_tracks_out[223], down_tracks_fwd[319], block_out[103], block_out[99], 1'h0, inputs_i[15], 1'h0, left_tracks_out[206], down_tracks_fwd[288], block_out[95], block_out[91], 1'h0, inputs_i[16], 1'h0, left_tracks_out[205], down_tracks_fwd[289], block_out[95], block_out[91], 1'h0, inputs_i[16], 1'h0, left_tracks_out[204], down_tracks_fwd[290], block_out[95], block_out[91], 1'h0, inputs_i[17], 1'h0, left_tracks_out[203], down_tracks_fwd[291], block_out[95], block_out[91], 1'h0, inputs_i[17], 1'h0, left_tracks_out[202], down_tracks_fwd[292], block_out[95], block_out[91], 1'h0, inputs_i[18], 1'h0, left_tracks_out[201], down_tracks_fwd[293], block_out[95], block_out[91], 1'h0, inputs_i[18], 1'h0, left_tracks_out[200], down_tracks_fwd[294], block_out[95], block_out[91], 1'h0, inputs_i[19], 1'h0, left_tracks_out[199], down_tracks_fwd[295], block_out[95], block_out[91], 1'h0, inputs_i[19], 1'h0, left_tracks_out[198], down_tracks_fwd[296], block_out[95], block_out[91], 1'h0, inputs_i[20], 1'h0, left_tracks_out[197], down_tracks_fwd[297], block_out[95], block_out[91], 1'h0, inputs_i[20], 1'h0, left_tracks_out[196], down_tracks_fwd[298], block_out[95], block_out[91], 1'h0, inputs_i[21], 1'h0, left_tracks_out[195], down_tracks_fwd[299], block_out[95], block_out[91], 1'h0, inputs_i[21], 1'h0, left_tracks_out[194], down_tracks_fwd[300], block_out[95], block_out[91], 1'h0, inputs_i[22], 1'h0, left_tracks_out[193], down_tracks_fwd[301], block_out[95], block_out[91], 1'h0, inputs_i[22], 1'h0, left_tracks_out[192], down_tracks_fwd[302], block_out[95], block_out[91], 1'h0, inputs_i[23], 1'h0, left_tracks_out[207], down_tracks_fwd[303], block_out[95], block_out[91], 1'h0, inputs_i[23], 1'h0, left_tracks_out[190], down_tracks_fwd[272], block_out[87], block_out[83], 1'h0, inputs_i[24], 1'h0, left_tracks_out[189], down_tracks_fwd[273], block_out[87], block_out[83], 1'h0, inputs_i[24], 1'h0, left_tracks_out[188], down_tracks_fwd[274], block_out[87], block_out[83], 1'h0, inputs_i[25], 1'h0, left_tracks_out[187], down_tracks_fwd[275], block_out[87], block_out[83], 1'h0, inputs_i[25], 1'h0, left_tracks_out[186], down_tracks_fwd[276], block_out[87], block_out[83], 1'h0, inputs_i[26], 1'h0, left_tracks_out[185], down_tracks_fwd[277], block_out[87], block_out[83], 1'h0, inputs_i[26], 1'h0, left_tracks_out[184], down_tracks_fwd[278], block_out[87], block_out[83], 1'h0, inputs_i[27], 1'h0, left_tracks_out[183], down_tracks_fwd[279], block_out[87], block_out[83], 1'h0, inputs_i[27], 1'h0, left_tracks_out[182], down_tracks_fwd[280], block_out[87], block_out[83], 1'h0, inputs_i[28], 1'h0, left_tracks_out[181], down_tracks_fwd[281], block_out[87], block_out[83], 1'h0, inputs_i[28], 1'h0, left_tracks_out[180], down_tracks_fwd[282], block_out[87], block_out[83], 1'h0, inputs_i[29], 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block_out[77], block_out[73], right_tracks_out[173], left_tracks_out[34], down_tracks_fwd[156], block_out[23], block_out[19], block_out[77], block_out[73], right_tracks_out[174], left_tracks_out[33], down_tracks_fwd[157], block_out[23], block_out[19], block_out[77], block_out[73], right_tracks_out[175], left_tracks_out[32], down_tracks_fwd[158], block_out[23], block_out[19], block_out[77], block_out[73], right_tracks_out[160], left_tracks_out[47], down_tracks_fwd[159], block_out[23], block_out[19], block_out[77], block_out[73], right_tracks_out[145], left_tracks_out[30], down_tracks_fwd[128], block_out[15], block_out[11], block_out[69], block_out[65], right_tracks_out[146], left_tracks_out[29], down_tracks_fwd[129], block_out[15], block_out[11], block_out[69], block_out[65], right_tracks_out[147], left_tracks_out[28], down_tracks_fwd[130], block_out[15], block_out[11], block_out[69], block_out[65], right_tracks_out[148], left_tracks_out[27], down_tracks_fwd[131], block_out[15], block_out[11], block_out[69], block_out[65], right_tracks_out[149], left_tracks_out[26], down_tracks_fwd[132], block_out[15], block_out[11], block_out[69], block_out[65], right_tracks_out[150], left_tracks_out[25], down_tracks_fwd[133], block_out[15], block_out[11], block_out[69], block_out[65], right_tracks_out[151], left_tracks_out[24], down_tracks_fwd[134], block_out[15], block_out[11], block_out[69], block_out[65], right_tracks_out[152], left_tracks_out[23], down_tracks_fwd[135], block_out[15], block_out[11], block_out[69], block_out[65], right_tracks_out[153], left_tracks_out[22], down_tracks_fwd[136], block_out[15], block_out[11], block_out[69], block_out[65], right_tracks_out[154], left_tracks_out[21], down_tracks_fwd[137], block_out[15], block_out[11], block_out[69], block_out[65], right_tracks_out[155], left_tracks_out[20], down_tracks_fwd[138], block_out[15], block_out[11], block_out[69], block_out[65], right_tracks_out[156], left_tracks_out[19], down_tracks_fwd[139], block_out[15], block_out[11], block_out[69], block_out[65], right_tracks_out[157], left_tracks_out[18], down_tracks_fwd[140], block_out[15], block_out[11], block_out[69], block_out[65], right_tracks_out[158], left_tracks_out[17], down_tracks_fwd[141], block_out[15], block_out[11], block_out[69], block_out[65], right_tracks_out[159], left_tracks_out[16], down_tracks_fwd[142], block_out[15], block_out[11], block_out[69], block_out[65], right_tracks_out[144], left_tracks_out[31], down_tracks_fwd[143], block_out[15], block_out[11], block_out[69], block_out[65], right_tracks_out[129], left_tracks_out[14], down_tracks_fwd[112], block_out[7], block_out[3], block_out[61], block_out[57], right_tracks_out[130], left_tracks_out[13], down_tracks_fwd[113], block_out[7], block_out[3], block_out[61], block_out[57], right_tracks_out[131], left_tracks_out[12], down_tracks_fwd[114], block_out[7], block_out[3], block_out[61], block_out[57], right_tracks_out[132], left_tracks_out[11], down_tracks_fwd[115], block_out[7], block_out[3], block_out[61], block_out[57], right_tracks_out[133], left_tracks_out[10], down_tracks_fwd[116], block_out[7], block_out[3], block_out[61], block_out[57], right_tracks_out[134], left_tracks_out[9], down_tracks_fwd[117], block_out[7], block_out[3], block_out[61], block_out[57], right_tracks_out[135], left_tracks_out[8], down_tracks_fwd[118], block_out[7], block_out[3], block_out[61], block_out[57], right_tracks_out[136], left_tracks_out[7], down_tracks_fwd[119], block_out[7], block_out[3], block_out[61], block_out[57], right_tracks_out[137], left_tracks_out[6], down_tracks_fwd[120], block_out[7], block_out[3], block_out[61], block_out[57], right_tracks_out[138], left_tracks_out[5], down_tracks_fwd[121], block_out[7], block_out[3], block_out[61], block_out[57], right_tracks_out[139], left_tracks_out[4], down_tracks_fwd[122], block_out[7], block_out[3], block_out[61], block_out[57], right_tracks_out[140], left_tracks_out[3], down_tracks_fwd[123], block_out[7], block_out[3], block_out[61], block_out[57], right_tracks_out[141], left_tracks_out[2], down_tracks_fwd[124], block_out[7], block_out[3], block_out[61], block_out[57], right_tracks_out[142], left_tracks_out[1], down_tracks_fwd[125], block_out[7], block_out[3], block_out[61], block_out[57], right_tracks_out[143], left_tracks_out[0], down_tracks_fwd[126], block_out[7], block_out[3], block_out[61], block_out[57], right_tracks_out[128], left_tracks_out[15], down_tracks_fwd[127], block_out[7], block_out[3], block_out[61], block_out[57], right_tracks_out[97], 1'h0, down_tracks_fwd[96], 1'h0, inputs_i[72], block_out[53], block_out[49], right_tracks_out[98], 1'h0, down_tracks_fwd[97], 1'h0, inputs_i[72], block_out[53], block_out[49], right_tracks_out[99], 1'h0, down_tracks_fwd[98], 1'h0, inputs_i[73], block_out[53], block_out[49], right_tracks_out[100], 1'h0, down_tracks_fwd[99], 1'h0, inputs_i[73], block_out[53], block_out[49], right_tracks_out[101], 1'h0, down_tracks_fwd[100], 1'h0, inputs_i[74], block_out[53], block_out[49], right_tracks_out[102], 1'h0, down_tracks_fwd[101], 1'h0, inputs_i[74], block_out[53], block_out[49], right_tracks_out[103], 1'h0, down_tracks_fwd[102], 1'h0, inputs_i[75], block_out[53], block_out[49], right_tracks_out[104], 1'h0, down_tracks_fwd[103], 1'h0, inputs_i[75], block_out[53], block_out[49], right_tracks_out[105], 1'h0, down_tracks_fwd[104], 1'h0, inputs_i[76], block_out[53], block_out[49], right_tracks_out[106], 1'h0, down_tracks_fwd[105], 1'h0, inputs_i[76], block_out[53], block_out[49], right_tracks_out[107], 1'h0, down_tracks_fwd[106], 1'h0, inputs_i[77], block_out[53], block_out[49], right_tracks_out[108], 1'h0, down_tracks_fwd[107], 1'h0, inputs_i[77], block_out[53], block_out[49], right_tracks_out[109], 1'h0, down_tracks_fwd[108], 1'h0, inputs_i[78], block_out[53], block_out[49], right_tracks_out[110], 1'h0, down_tracks_fwd[109], 1'h0, inputs_i[78], block_out[53], block_out[49], right_tracks_out[111], 1'h0, down_tracks_fwd[110], 1'h0, inputs_i[79], block_out[53], block_out[49], right_tracks_out[96], 1'h0, down_tracks_fwd[111], 1'h0, inputs_i[79], block_out[53], block_out[49], right_tracks_out[81], 1'h0, down_tracks_fwd[80], 1'h0, inputs_i[80], block_out[45], block_out[41], right_tracks_out[82], 1'h0, down_tracks_fwd[81], 1'h0, inputs_i[80], block_out[45], block_out[41], right_tracks_out[83], 1'h0, down_tracks_fwd[82], 1'h0, inputs_i[81], block_out[45], block_out[41], right_tracks_out[84], 1'h0, down_tracks_fwd[83], 1'h0, inputs_i[81], block_out[45], block_out[41], right_tracks_out[85], 1'h0, down_tracks_fwd[84], 1'h0, inputs_i[82], block_out[45], block_out[41], right_tracks_out[86], 1'h0, down_tracks_fwd[85], 1'h0, inputs_i[82], block_out[45], block_out[41], right_tracks_out[87], 1'h0, down_tracks_fwd[86], 1'h0, inputs_i[83], block_out[45], block_out[41], right_tracks_out[88], 1'h0, down_tracks_fwd[87], 1'h0, inputs_i[83], block_out[45], block_out[41], right_tracks_out[89], 1'h0, down_tracks_fwd[88], 1'h0, inputs_i[84], block_out[45], block_out[41], right_tracks_out[90], 1'h0, down_tracks_fwd[89], 1'h0, inputs_i[84], block_out[45], block_out[41], right_tracks_out[91], 1'h0, down_tracks_fwd[90], 1'h0, inputs_i[85], block_out[45], block_out[41], right_tracks_out[92], 1'h0, down_tracks_fwd[91], 1'h0, inputs_i[85], block_out[45], block_out[41], right_tracks_out[93], 1'h0, down_tracks_fwd[92], 1'h0, inputs_i[86], block_out[45], block_out[41], right_tracks_out[94], 1'h0, down_tracks_fwd[93], 1'h0, inputs_i[86], block_out[45], block_out[41], right_tracks_out[95], 1'h0, down_tracks_fwd[94], 1'h0, inputs_i[87], block_out[45], block_out[41], right_tracks_out[80], 1'h0, down_tracks_fwd[95], 1'h0, inputs_i[87], block_out[45], block_out[41], right_tracks_out[65], 1'h0, down_tracks_fwd[64], 1'h0, inputs_i[88], block_out[37], block_out[33], right_tracks_out[66], 1'h0, down_tracks_fwd[65], 1'h0, inputs_i[88], block_out[37], block_out[33], right_tracks_out[67], 1'h0, down_tracks_fwd[66], 1'h0, inputs_i[89], block_out[37], block_out[33], right_tracks_out[68], 1'h0, down_tracks_fwd[67], 1'h0, inputs_i[89], block_out[37], block_out[33], right_tracks_out[69], 1'h0, down_tracks_fwd[68], 1'h0, inputs_i[90], block_out[37], block_out[33], right_tracks_out[70], 1'h0, down_tracks_fwd[69], 1'h0, inputs_i[90], block_out[37], block_out[33], right_tracks_out[71], 1'h0, down_tracks_fwd[70], 1'h0, inputs_i[91], block_out[37], block_out[33], right_tracks_out[72], 1'h0, down_tracks_fwd[71], 1'h0, inputs_i[91], block_out[37], block_out[33], right_tracks_out[73], 1'h0, down_tracks_fwd[72], 1'h0, inputs_i[92], block_out[37], block_out[33], right_tracks_out[74], 1'h0, down_tracks_fwd[73], 1'h0, inputs_i[92], block_out[37], block_out[33], right_tracks_out[75], 1'h0, down_tracks_fwd[74], 1'h0, inputs_i[93], block_out[37], block_out[33], right_tracks_out[76], 1'h0, down_tracks_fwd[75], 1'h0, inputs_i[93], block_out[37], block_out[33], right_tracks_out[77], 1'h0, down_tracks_fwd[76], 1'h0, inputs_i[94], block_out[37], block_out[33], right_tracks_out[78], 1'h0, down_tracks_fwd[77], 1'h0, inputs_i[94], block_out[37], block_out[33], right_tracks_out[79], 1'h0, down_tracks_fwd[78], 1'h0, inputs_i[95], block_out[37], block_out[33], right_tracks_out[64], 1'h0, down_tracks_fwd[79], 1'h0, inputs_i[95], block_out[37], block_out[33], right_tracks_out[49], 1'h0, down_tracks_fwd[48], 1'h0, inputs_i[96], block_out[29], block_out[25], right_tracks_out[50], 1'h0, down_tracks_fwd[49], 1'h0, inputs_i[96], block_out[29], block_out[25], right_tracks_out[51], 1'h0, down_tracks_fwd[50], 1'h0, inputs_i[97], block_out[29], block_out[25], right_tracks_out[52], 1'h0, down_tracks_fwd[51], 1'h0, inputs_i[97], block_out[29], block_out[25], right_tracks_out[53], 1'h0, down_tracks_fwd[52], 1'h0, inputs_i[98], block_out[29], block_out[25], right_tracks_out[54], 1'h0, down_tracks_fwd[53], 1'h0, inputs_i[98], block_out[29], block_out[25], right_tracks_out[55], 1'h0, down_tracks_fwd[54], 1'h0, inputs_i[99], block_out[29], block_out[25], right_tracks_out[56], 1'h0, down_tracks_fwd[55], 1'h0, inputs_i[99], block_out[29], block_out[25], right_tracks_out[57], 1'h0, down_tracks_fwd[56], 1'h0, inputs_i[100], block_out[29], block_out[25], right_tracks_out[58], 1'h0, down_tracks_fwd[57], 1'h0, inputs_i[100], block_out[29], block_out[25], right_tracks_out[59], 1'h0, down_tracks_fwd[58], 1'h0, inputs_i[101], block_out[29], block_out[25], right_tracks_out[60], 1'h0, down_tracks_fwd[59], 1'h0, inputs_i[101], block_out[29], block_out[25], right_tracks_out[61], 1'h0, down_tracks_fwd[60], 1'h0, inputs_i[102], block_out[29], block_out[25], right_tracks_out[62], 1'h0, down_tracks_fwd[61], 1'h0, inputs_i[102], block_out[29], block_out[25], right_tracks_out[63], 1'h0, down_tracks_fwd[62], 1'h0, inputs_i[103], block_out[29], block_out[25], right_tracks_out[48], 1'h0, down_tracks_fwd[63], 1'h0, inputs_i[103], block_out[29], block_out[25], right_tracks_out[33], 1'h0, down_tracks_fwd[32], 1'h0, inputs_i[104], block_out[21], block_out[17], right_tracks_out[34], 1'h0, down_tracks_fwd[33], 1'h0, inputs_i[104], block_out[21], block_out[17], right_tracks_out[35], 1'h0, down_tracks_fwd[34], 1'h0, inputs_i[105], block_out[21], block_out[17], right_tracks_out[36], 1'h0, down_tracks_fwd[35], 1'h0, inputs_i[105], block_out[21], block_out[17], right_tracks_out[37], 1'h0, down_tracks_fwd[36], 1'h0, inputs_i[106], block_out[21], block_out[17], right_tracks_out[38], 1'h0, down_tracks_fwd[37], 1'h0, inputs_i[106], block_out[21], block_out[17], right_tracks_out[39], 1'h0, down_tracks_fwd[38], 1'h0, inputs_i[107], block_out[21], block_out[17], right_tracks_out[40], 1'h0, down_tracks_fwd[39], 1'h0, inputs_i[107], block_out[21], block_out[17], right_tracks_out[41], 1'h0, down_tracks_fwd[40], 1'h0, inputs_i[108], block_out[21], block_out[17], right_tracks_out[42], 1'h0, down_tracks_fwd[41], 1'h0, inputs_i[108], block_out[21], block_out[17], right_tracks_out[43], 1'h0, down_tracks_fwd[42], 1'h0, inputs_i[109], block_out[21], block_out[17], right_tracks_out[44], 1'h0, down_tracks_fwd[43], 1'h0, inputs_i[109], block_out[21], block_out[17], right_tracks_out[45], 1'h0, down_tracks_fwd[44], 1'h0, inputs_i[110], block_out[21], block_out[17], right_tracks_out[46], 1'h0, down_tracks_fwd[45], 1'h0, inputs_i[110], block_out[21], block_out[17], right_tracks_out[47], 1'h0, down_tracks_fwd[46], 1'h0, inputs_i[111], block_out[21], block_out[17], right_tracks_out[32], 1'h0, down_tracks_fwd[47], 1'h0, inputs_i[111], block_out[21], block_out[17], right_tracks_out[17], 1'h0, down_tracks_fwd[16], 1'h0, inputs_i[112], block_out[13], block_out[9], right_tracks_out[18], 1'h0, down_tracks_fwd[17], 1'h0, inputs_i[112], block_out[13], block_out[9], right_tracks_out[19], 1'h0, down_tracks_fwd[18], 1'h0, inputs_i[113], block_out[13], block_out[9], right_tracks_out[20], 1'h0, down_tracks_fwd[19], 1'h0, inputs_i[113], block_out[13], block_out[9], right_tracks_out[21], 1'h0, down_tracks_fwd[20], 1'h0, inputs_i[114], block_out[13], block_out[9], right_tracks_out[22], 1'h0, down_tracks_fwd[21], 1'h0, inputs_i[114], block_out[13], block_out[9], right_tracks_out[23], 1'h0, down_tracks_fwd[22], 1'h0, inputs_i[115], block_out[13], block_out[9], right_tracks_out[24], 1'h0, down_tracks_fwd[23], 1'h0, inputs_i[115], block_out[13], block_out[9], right_tracks_out[25], 1'h0, down_tracks_fwd[24], 1'h0, inputs_i[116], block_out[13], block_out[9], right_tracks_out[26], 1'h0, down_tracks_fwd[25], 1'h0, inputs_i[116], block_out[13], block_out[9], right_tracks_out[27], 1'h0, down_tracks_fwd[26], 1'h0, inputs_i[117], block_out[13], block_out[9], right_tracks_out[28], 1'h0, down_tracks_fwd[27], 1'h0, inputs_i[117], block_out[13], block_out[9], right_tracks_out[29], 1'h0, down_tracks_fwd[28], 1'h0, inputs_i[118], block_out[13], block_out[9], right_tracks_out[30], 1'h0, down_tracks_fwd[29], 1'h0, inputs_i[118], block_out[13], block_out[9], right_tracks_out[31], 1'h0, down_tracks_fwd[30], 1'h0, inputs_i[119], block_out[13], block_out[9], right_tracks_out[16], 1'h0, down_tracks_fwd[31], 1'h0, inputs_i[119], block_out[13], block_out[9], right_tracks_out[1], 1'h0, down_tracks_fwd[0], 1'h0, inputs_i[120], block_out[5], block_out[1], right_tracks_out[2], 1'h0, down_tracks_fwd[1], 1'h0, inputs_i[120], block_out[5], block_out[1], right_tracks_out[3], 1'h0, down_tracks_fwd[2], 1'h0, inputs_i[121], block_out[5], block_out[1], right_tracks_out[4], 1'h0, down_tracks_fwd[3], 1'h0, inputs_i[121], block_out[5], block_out[1], right_tracks_out[5], 1'h0, down_tracks_fwd[4], 1'h0, inputs_i[122], block_out[5], block_out[1], right_tracks_out[6], 1'h0, down_tracks_fwd[5], 1'h0, inputs_i[122], block_out[5], block_out[1], right_tracks_out[7], 1'h0, down_tracks_fwd[6], 1'h0, inputs_i[123], block_out[5], block_out[1], right_tracks_out[8], 1'h0, down_tracks_fwd[7], 1'h0, inputs_i[123], block_out[5], block_out[1], right_tracks_out[9], 1'h0, down_tracks_fwd[8], 1'h0, inputs_i[124], block_out[5], block_out[1], right_tracks_out[10], 1'h0, down_tracks_fwd[9], 1'h0, inputs_i[124], block_out[5], block_out[1], right_tracks_out[11], 1'h0, down_tracks_fwd[10], 1'h0, inputs_i[125], block_out[5], block_out[1], right_tracks_out[12], 1'h0, down_tracks_fwd[11], 1'h0, inputs_i[125], block_out[5], block_out[1], right_tracks_out[13], 1'h0, down_tracks_fwd[12], 1'h0, inputs_i[126], block_out[5], block_out[1], right_tracks_out[14], 1'h0, down_tracks_fwd[13], 1'h0, inputs_i[126], block_out[5], block_out[1], right_tracks_out[15], 1'h0, down_tracks_fwd[14], 1'h0, inputs_i[127], block_out[5], block_out[1], right_tracks_out[0], 1'h0, down_tracks_fwd[15], 1'h0, inputs_i[127], block_out[5], block_out[1] };
+ assign down_tracks_out = { \vertical_routing_network_x:1.vertical_routing_network_y:1.routing_node_down:2428 , \vertical_routing_network_x:1.vertical_routing_network_y:2.routing_node_down:3906 , \vertical_routing_network_x:1.vertical_routing_network_y:3.routing_node_down:5384 , \vertical_routing_network_x:1.vertical_routing_network_y:4.routing_node_down:6862 , \vertical_routing_network_x:1.vertical_routing_network_y:5.routing_node_down:8340 , \vertical_routing_network_x:1.vertical_routing_network_y:6.routing_node_down:9818 , \vertical_routing_network_x:1.vertical_routing_network_y:7.routing_node_down:11296 , \vertical_routing_network_x:2.vertical_routing_network_y:1.routing_node_down:12438 , \vertical_routing_network_x:2.vertical_routing_network_y:2.routing_node_down:13580 , \vertical_routing_network_x:2.vertical_routing_network_y:3.routing_node_down:14722 , \vertical_routing_network_x:2.vertical_routing_network_y:4.routing_node_down:15864 , \vertical_routing_network_x:2.vertical_routing_network_y:5.routing_node_down:17006 , \vertical_routing_network_x:2.vertical_routing_network_y:6.routing_node_down:18148 , \vertical_routing_network_x:2.vertical_routing_network_y:7.routing_node_down:19290 , \vertical_routing_network_x:3.vertical_routing_network_y:1.routing_node_down:20765 , \vertical_routing_network_x:3.vertical_routing_network_y:2.routing_node_down:22240 , \vertical_routing_network_x:3.vertical_routing_network_y:3.routing_node_down:23715 , \vertical_routing_network_x:3.vertical_routing_network_y:4.routing_node_down:25190 , \vertical_routing_network_x:3.vertical_routing_network_y:5.routing_node_down:26665 , \vertical_routing_network_x:3.vertical_routing_network_y:6.routing_node_down:28140 , \vertical_routing_network_x:3.vertical_routing_network_y:7.routing_node_down:29615 };
+ assign left_tracks_in = { down_tracks_out[208], 1'h0, left_tracks_fwd[240], 1'h0, inputs_i[128], block_out[110], block_out[106], down_tracks_out[223], 1'h0, left_tracks_fwd[241], 1'h0, inputs_i[128], block_out[110], block_out[106], down_tracks_out[222], 1'h0, left_tracks_fwd[242], 1'h0, inputs_i[129], block_out[110], block_out[106], down_tracks_out[221], 1'h0, left_tracks_fwd[243], 1'h0, inputs_i[129], block_out[110], block_out[106], down_tracks_out[220], 1'h0, left_tracks_fwd[244], 1'h0, inputs_i[130], block_out[110], block_out[106], down_tracks_out[219], 1'h0, left_tracks_fwd[245], 1'h0, inputs_i[130], block_out[110], block_out[106], down_tracks_out[218], 1'h0, left_tracks_fwd[246], 1'h0, inputs_i[131], block_out[110], block_out[106], down_tracks_out[217], 1'h0, left_tracks_fwd[247], 1'h0, inputs_i[131], block_out[110], block_out[106], down_tracks_out[216], 1'h0, left_tracks_fwd[248], 1'h0, inputs_i[132], block_out[110], block_out[106], down_tracks_out[215], 1'h0, left_tracks_fwd[249], 1'h0, inputs_i[132], block_out[110], block_out[106], down_tracks_out[214], 1'h0, left_tracks_fwd[250], 1'h0, inputs_i[133], block_out[110], block_out[106], down_tracks_out[213], 1'h0, left_tracks_fwd[251], 1'h0, inputs_i[133], block_out[110], block_out[106], down_tracks_out[212], 1'h0, left_tracks_fwd[252], 1'h0, inputs_i[134], block_out[110], block_out[106], down_tracks_out[211], 1'h0, left_tracks_fwd[253], 1'h0, inputs_i[134], block_out[110], block_out[106], down_tracks_out[210], 1'h0, left_tracks_fwd[254], 1'h0, inputs_i[135], block_out[110], block_out[106], down_tracks_out[209], 1'h0, left_tracks_fwd[255], 1'h0, inputs_i[135], block_out[110], block_out[106], down_tracks_out[192], up_tracks_out[223], left_tracks_fwd[224], block_out[108], block_out[104], block_out[102], block_out[98], down_tracks_out[207], up_tracks_out[208], left_tracks_fwd[225], block_out[108], block_out[104], block_out[102], block_out[98], down_tracks_out[206], up_tracks_out[209], left_tracks_fwd[226], block_out[108], block_out[104], block_out[102], block_out[98], down_tracks_out[205], up_tracks_out[210], left_tracks_fwd[227], block_out[108], block_out[104], block_out[102], block_out[98], down_tracks_out[204], up_tracks_out[211], left_tracks_fwd[228], block_out[108], block_out[104], block_out[102], block_out[98], down_tracks_out[203], up_tracks_out[212], left_tracks_fwd[229], block_out[108], block_out[104], block_out[102], block_out[98], down_tracks_out[202], up_tracks_out[213], left_tracks_fwd[230], block_out[108], block_out[104], block_out[102], block_out[98], down_tracks_out[201], up_tracks_out[214], left_tracks_fwd[231], block_out[108], block_out[104], block_out[102], block_out[98], down_tracks_out[200], up_tracks_out[215], left_tracks_fwd[232], block_out[108], block_out[104], block_out[102], block_out[98], down_tracks_out[199], up_tracks_out[216], left_tracks_fwd[233], block_out[108], block_out[104], block_out[102], block_out[98], down_tracks_out[198], up_tracks_out[217], left_tracks_fwd[234], block_out[108], block_out[104], block_out[102], block_out[98], down_tracks_out[197], up_tracks_out[218], left_tracks_fwd[235], block_out[108], block_out[104], block_out[102], block_out[98], down_tracks_out[196], up_tracks_out[219], left_tracks_fwd[236], block_out[108], block_out[104], block_out[102], block_out[98], down_tracks_out[195], up_tracks_out[220], left_tracks_fwd[237], block_out[108], block_out[104], block_out[102], block_out[98], down_tracks_out[194], up_tracks_out[221], left_tracks_fwd[238], block_out[108], block_out[104], block_out[102], block_out[98], down_tracks_out[193], up_tracks_out[222], left_tracks_fwd[239], block_out[108], block_out[104], block_out[102], block_out[98], down_tracks_out[176], up_tracks_out[207], left_tracks_fwd[208], block_out[100], block_out[96], block_out[94], block_out[90], down_tracks_out[191], up_tracks_out[192], left_tracks_fwd[209], block_out[100], block_out[96], block_out[94], block_out[90], down_tracks_out[190], up_tracks_out[193], left_tracks_fwd[210], block_out[100], block_out[96], block_out[94], block_out[90], down_tracks_out[189], up_tracks_out[194], left_tracks_fwd[211], block_out[100], block_out[96], block_out[94], block_out[90], down_tracks_out[188], up_tracks_out[195], left_tracks_fwd[212], block_out[100], block_out[96], block_out[94], block_out[90], down_tracks_out[187], up_tracks_out[196], left_tracks_fwd[213], block_out[100], block_out[96], block_out[94], block_out[90], down_tracks_out[186], up_tracks_out[197], left_tracks_fwd[214], block_out[100], block_out[96], block_out[94], block_out[90], down_tracks_out[185], up_tracks_out[198], left_tracks_fwd[215], block_out[100], block_out[96], block_out[94], block_out[90], down_tracks_out[184], up_tracks_out[199], left_tracks_fwd[216], block_out[100], block_out[96], block_out[94], block_out[90], down_tracks_out[183], up_tracks_out[200], left_tracks_fwd[217], block_out[100], block_out[96], block_out[94], block_out[90], down_tracks_out[182], up_tracks_out[201], left_tracks_fwd[218], block_out[100], block_out[96], block_out[94], block_out[90], down_tracks_out[181], up_tracks_out[202], left_tracks_fwd[219], block_out[100], block_out[96], block_out[94], block_out[90], down_tracks_out[180], up_tracks_out[203], left_tracks_fwd[220], block_out[100], block_out[96], block_out[94], block_out[90], down_tracks_out[179], up_tracks_out[204], left_tracks_fwd[221], block_out[100], block_out[96], block_out[94], block_out[90], down_tracks_out[178], up_tracks_out[205], left_tracks_fwd[222], block_out[100], block_out[96], block_out[94], block_out[90], down_tracks_out[177], up_tracks_out[206], left_tracks_fwd[223], block_out[100], block_out[96], block_out[94], block_out[90], down_tracks_out[160], up_tracks_out[191], left_tracks_fwd[192], block_out[92], block_out[88], block_out[86], block_out[82], down_tracks_out[175], up_tracks_out[176], left_tracks_fwd[193], block_out[92], block_out[88], block_out[86], block_out[82], down_tracks_out[174], up_tracks_out[177], left_tracks_fwd[194], block_out[92], block_out[88], block_out[86], block_out[82], down_tracks_out[173], up_tracks_out[178], left_tracks_fwd[195], block_out[92], block_out[88], block_out[86], block_out[82], down_tracks_out[172], up_tracks_out[179], left_tracks_fwd[196], block_out[92], block_out[88], block_out[86], block_out[82], down_tracks_out[171], up_tracks_out[180], left_tracks_fwd[197], block_out[92], block_out[88], block_out[86], block_out[82], down_tracks_out[170], up_tracks_out[181], left_tracks_fwd[198], block_out[92], block_out[88], block_out[86], block_out[82], down_tracks_out[169], up_tracks_out[182], left_tracks_fwd[199], block_out[92], block_out[88], block_out[86], block_out[82], down_tracks_out[168], up_tracks_out[183], left_tracks_fwd[200], block_out[92], block_out[88], block_out[86], block_out[82], down_tracks_out[167], up_tracks_out[184], left_tracks_fwd[201], block_out[92], block_out[88], block_out[86], block_out[82], down_tracks_out[166], up_tracks_out[185], left_tracks_fwd[202], block_out[92], block_out[88], block_out[86], block_out[82], down_tracks_out[165], up_tracks_out[186], left_tracks_fwd[203], block_out[92], block_out[88], block_out[86], block_out[82], down_tracks_out[164], up_tracks_out[187], left_tracks_fwd[204], block_out[92], block_out[88], block_out[86], block_out[82], down_tracks_out[163], up_tracks_out[188], left_tracks_fwd[205], block_out[92], block_out[88], block_out[86], block_out[82], down_tracks_out[162], up_tracks_out[189], left_tracks_fwd[206], block_out[92], block_out[88], block_out[86], block_out[82], down_tracks_out[161], up_tracks_out[190], left_tracks_fwd[207], block_out[92], block_out[88], block_out[86], block_out[82], down_tracks_out[144], up_tracks_out[175], left_tracks_fwd[176], block_out[84], block_out[80], block_out[78], block_out[74], down_tracks_out[159], up_tracks_out[160], left_tracks_fwd[177], block_out[84], block_out[80], block_out[78], block_out[74], down_tracks_out[158], up_tracks_out[161], left_tracks_fwd[178], block_out[84], block_out[80], block_out[78], block_out[74], down_tracks_out[157], up_tracks_out[162], left_tracks_fwd[179], block_out[84], block_out[80], block_out[78], block_out[74], down_tracks_out[156], up_tracks_out[163], left_tracks_fwd[180], block_out[84], block_out[80], block_out[78], block_out[74], down_tracks_out[155], up_tracks_out[164], left_tracks_fwd[181], block_out[84], block_out[80], block_out[78], block_out[74], down_tracks_out[154], up_tracks_out[165], left_tracks_fwd[182], block_out[84], block_out[80], block_out[78], block_out[74], down_tracks_out[153], up_tracks_out[166], left_tracks_fwd[183], block_out[84], block_out[80], block_out[78], block_out[74], down_tracks_out[152], up_tracks_out[167], left_tracks_fwd[184], block_out[84], block_out[80], block_out[78], block_out[74], down_tracks_out[151], up_tracks_out[168], left_tracks_fwd[185], block_out[84], block_out[80], block_out[78], block_out[74], down_tracks_out[150], up_tracks_out[169], left_tracks_fwd[186], block_out[84], block_out[80], block_out[78], block_out[74], down_tracks_out[149], up_tracks_out[170], left_tracks_fwd[187], block_out[84], block_out[80], block_out[78], block_out[74], down_tracks_out[148], up_tracks_out[171], left_tracks_fwd[188], block_out[84], block_out[80], block_out[78], block_out[74], down_tracks_out[147], up_tracks_out[172], left_tracks_fwd[189], block_out[84], block_out[80], block_out[78], block_out[74], down_tracks_out[146], up_tracks_out[173], left_tracks_fwd[190], block_out[84], block_out[80], block_out[78], block_out[74], down_tracks_out[145], up_tracks_out[174], left_tracks_fwd[191], block_out[84], block_out[80], block_out[78], block_out[74], down_tracks_out[128], up_tracks_out[159], left_tracks_fwd[160], block_out[76], block_out[72], block_out[70], block_out[66], down_tracks_out[143], up_tracks_out[144], left_tracks_fwd[161], block_out[76], block_out[72], block_out[70], block_out[66], down_tracks_out[142], up_tracks_out[145], left_tracks_fwd[162], block_out[76], block_out[72], block_out[70], block_out[66], down_tracks_out[141], up_tracks_out[146], left_tracks_fwd[163], block_out[76], block_out[72], block_out[70], block_out[66], down_tracks_out[140], up_tracks_out[147], left_tracks_fwd[164], block_out[76], block_out[72], block_out[70], block_out[66], down_tracks_out[139], up_tracks_out[148], left_tracks_fwd[165], block_out[76], block_out[72], block_out[70], block_out[66], down_tracks_out[138], up_tracks_out[149], left_tracks_fwd[166], block_out[76], block_out[72], block_out[70], block_out[66], down_tracks_out[137], up_tracks_out[150], left_tracks_fwd[167], block_out[76], block_out[72], block_out[70], block_out[66], down_tracks_out[136], up_tracks_out[151], left_tracks_fwd[168], block_out[76], block_out[72], block_out[70], block_out[66], down_tracks_out[135], up_tracks_out[152], left_tracks_fwd[169], block_out[76], block_out[72], block_out[70], block_out[66], down_tracks_out[134], up_tracks_out[153], left_tracks_fwd[170], block_out[76], block_out[72], block_out[70], block_out[66], down_tracks_out[133], up_tracks_out[154], left_tracks_fwd[171], block_out[76], block_out[72], block_out[70], block_out[66], down_tracks_out[132], up_tracks_out[155], left_tracks_fwd[172], block_out[76], block_out[72], block_out[70], block_out[66], down_tracks_out[131], up_tracks_out[156], left_tracks_fwd[173], block_out[76], block_out[72], block_out[70], block_out[66], down_tracks_out[130], up_tracks_out[157], left_tracks_fwd[174], block_out[76], block_out[72], block_out[70], block_out[66], down_tracks_out[129], up_tracks_out[158], left_tracks_fwd[175], block_out[76], block_out[72], block_out[70], block_out[66], down_tracks_out[112], up_tracks_out[143], left_tracks_fwd[144], block_out[68], block_out[64], block_out[62], block_out[58], down_tracks_out[127], up_tracks_out[128], left_tracks_fwd[145], block_out[68], block_out[64], block_out[62], block_out[58], down_tracks_out[126], up_tracks_out[129], left_tracks_fwd[146], block_out[68], block_out[64], block_out[62], block_out[58], down_tracks_out[125], up_tracks_out[130], left_tracks_fwd[147], block_out[68], block_out[64], block_out[62], block_out[58], down_tracks_out[124], up_tracks_out[131], left_tracks_fwd[148], block_out[68], block_out[64], block_out[62], block_out[58], down_tracks_out[123], up_tracks_out[132], left_tracks_fwd[149], block_out[68], block_out[64], block_out[62], block_out[58], down_tracks_out[122], up_tracks_out[133], left_tracks_fwd[150], block_out[68], block_out[64], block_out[62], block_out[58], down_tracks_out[121], up_tracks_out[134], left_tracks_fwd[151], block_out[68], block_out[64], block_out[62], block_out[58], down_tracks_out[120], up_tracks_out[135], left_tracks_fwd[152], block_out[68], block_out[64], block_out[62], block_out[58], down_tracks_out[119], up_tracks_out[136], left_tracks_fwd[153], block_out[68], block_out[64], block_out[62], block_out[58], down_tracks_out[118], up_tracks_out[137], left_tracks_fwd[154], block_out[68], block_out[64], block_out[62], block_out[58], down_tracks_out[117], up_tracks_out[138], left_tracks_fwd[155], block_out[68], block_out[64], block_out[62], block_out[58], down_tracks_out[116], up_tracks_out[139], left_tracks_fwd[156], block_out[68], block_out[64], block_out[62], block_out[58], down_tracks_out[115], up_tracks_out[140], left_tracks_fwd[157], block_out[68], block_out[64], block_out[62], block_out[58], down_tracks_out[114], up_tracks_out[141], left_tracks_fwd[158], block_out[68], block_out[64], block_out[62], block_out[58], down_tracks_out[113], up_tracks_out[142], left_tracks_fwd[159], block_out[68], block_out[64], block_out[62], block_out[58], 1'h0, up_tracks_out[127], left_tracks_fwd[128], block_out[60], block_out[56], 1'h0, inputs_i[56], 1'h0, up_tracks_out[112], left_tracks_fwd[129], block_out[60], block_out[56], 1'h0, inputs_i[56], 1'h0, up_tracks_out[113], left_tracks_fwd[130], block_out[60], block_out[56], 1'h0, inputs_i[57], 1'h0, up_tracks_out[114], left_tracks_fwd[131], block_out[60], block_out[56], 1'h0, inputs_i[57], 1'h0, up_tracks_out[115], left_tracks_fwd[132], block_out[60], block_out[56], 1'h0, inputs_i[58], 1'h0, up_tracks_out[116], left_tracks_fwd[133], block_out[60], block_out[56], 1'h0, inputs_i[58], 1'h0, up_tracks_out[117], left_tracks_fwd[134], block_out[60], block_out[56], 1'h0, inputs_i[59], 1'h0, up_tracks_out[118], left_tracks_fwd[135], block_out[60], block_out[56], 1'h0, inputs_i[59], 1'h0, up_tracks_out[119], left_tracks_fwd[136], block_out[60], block_out[56], 1'h0, inputs_i[60], 1'h0, up_tracks_out[120], left_tracks_fwd[137], block_out[60], block_out[56], 1'h0, inputs_i[60], 1'h0, up_tracks_out[121], left_tracks_fwd[138], block_out[60], block_out[56], 1'h0, inputs_i[61], 1'h0, up_tracks_out[122], left_tracks_fwd[139], block_out[60], block_out[56], 1'h0, inputs_i[61], 1'h0, up_tracks_out[123], left_tracks_fwd[140], block_out[60], block_out[56], 1'h0, inputs_i[62], 1'h0, up_tracks_out[124], left_tracks_fwd[141], block_out[60], block_out[56], 1'h0, inputs_i[62], 1'h0, up_tracks_out[125], left_tracks_fwd[142], block_out[60], block_out[56], 1'h0, inputs_i[63], 1'h0, up_tracks_out[126], left_tracks_fwd[143], block_out[60], block_out[56], 1'h0, inputs_i[63], down_tracks_out[96], 1'h0, left_tracks_fwd[112], 1'h0, inputs_i[136], block_out[54], block_out[50], down_tracks_out[111], 1'h0, left_tracks_fwd[113], 1'h0, inputs_i[136], block_out[54], block_out[50], down_tracks_out[110], 1'h0, left_tracks_fwd[114], 1'h0, inputs_i[137], block_out[54], block_out[50], down_tracks_out[109], 1'h0, left_tracks_fwd[115], 1'h0, inputs_i[137], block_out[54], block_out[50], down_tracks_out[108], 1'h0, left_tracks_fwd[116], 1'h0, inputs_i[138], block_out[54], block_out[50], down_tracks_out[107], 1'h0, left_tracks_fwd[117], 1'h0, inputs_i[138], block_out[54], block_out[50], down_tracks_out[106], 1'h0, left_tracks_fwd[118], 1'h0, inputs_i[139], block_out[54], block_out[50], down_tracks_out[105], 1'h0, left_tracks_fwd[119], 1'h0, inputs_i[139], block_out[54], block_out[50], down_tracks_out[104], 1'h0, left_tracks_fwd[120], 1'h0, inputs_i[140], block_out[54], block_out[50], down_tracks_out[103], 1'h0, left_tracks_fwd[121], 1'h0, inputs_i[140], block_out[54], block_out[50], down_tracks_out[102], 1'h0, left_tracks_fwd[122], 1'h0, inputs_i[141], block_out[54], block_out[50], down_tracks_out[101], 1'h0, left_tracks_fwd[123], 1'h0, inputs_i[141], block_out[54], block_out[50], down_tracks_out[100], 1'h0, left_tracks_fwd[124], 1'h0, inputs_i[142], block_out[54], block_out[50], down_tracks_out[99], 1'h0, left_tracks_fwd[125], 1'h0, inputs_i[142], block_out[54], block_out[50], down_tracks_out[98], 1'h0, left_tracks_fwd[126], 1'h0, inputs_i[143], block_out[54], block_out[50], down_tracks_out[97], 1'h0, left_tracks_fwd[127], 1'h0, inputs_i[143], block_out[54], block_out[50], down_tracks_out[80], up_tracks_out[111], left_tracks_fwd[96], block_out[52], block_out[48], block_out[46], block_out[42], down_tracks_out[95], up_tracks_out[96], left_tracks_fwd[97], block_out[52], block_out[48], block_out[46], block_out[42], down_tracks_out[94], up_tracks_out[97], left_tracks_fwd[98], block_out[52], block_out[48], block_out[46], block_out[42], down_tracks_out[93], up_tracks_out[98], left_tracks_fwd[99], block_out[52], block_out[48], block_out[46], block_out[42], down_tracks_out[92], up_tracks_out[99], left_tracks_fwd[100], block_out[52], block_out[48], block_out[46], block_out[42], down_tracks_out[91], up_tracks_out[100], left_tracks_fwd[101], block_out[52], block_out[48], block_out[46], block_out[42], down_tracks_out[90], up_tracks_out[101], left_tracks_fwd[102], block_out[52], block_out[48], block_out[46], block_out[42], down_tracks_out[89], up_tracks_out[102], left_tracks_fwd[103], block_out[52], block_out[48], block_out[46], block_out[42], down_tracks_out[88], up_tracks_out[103], left_tracks_fwd[104], block_out[52], block_out[48], block_out[46], block_out[42], down_tracks_out[87], up_tracks_out[104], left_tracks_fwd[105], block_out[52], block_out[48], block_out[46], block_out[42], down_tracks_out[86], up_tracks_out[105], left_tracks_fwd[106], block_out[52], block_out[48], block_out[46], block_out[42], down_tracks_out[85], up_tracks_out[106], left_tracks_fwd[107], block_out[52], block_out[48], block_out[46], block_out[42], down_tracks_out[84], up_tracks_out[107], left_tracks_fwd[108], block_out[52], block_out[48], block_out[46], block_out[42], down_tracks_out[83], up_tracks_out[108], left_tracks_fwd[109], block_out[52], block_out[48], block_out[46], block_out[42], down_tracks_out[82], up_tracks_out[109], left_tracks_fwd[110], block_out[52], block_out[48], block_out[46], block_out[42], down_tracks_out[81], up_tracks_out[110], left_tracks_fwd[111], block_out[52], block_out[48], block_out[46], block_out[42], down_tracks_out[64], up_tracks_out[95], left_tracks_fwd[80], block_out[44], block_out[40], block_out[38], block_out[34], down_tracks_out[79], up_tracks_out[80], left_tracks_fwd[81], block_out[44], block_out[40], block_out[38], block_out[34], down_tracks_out[78], up_tracks_out[81], left_tracks_fwd[82], block_out[44], block_out[40], block_out[38], block_out[34], down_tracks_out[77], up_tracks_out[82], left_tracks_fwd[83], block_out[44], block_out[40], block_out[38], block_out[34], down_tracks_out[76], up_tracks_out[83], left_tracks_fwd[84], block_out[44], block_out[40], block_out[38], block_out[34], down_tracks_out[75], up_tracks_out[84], left_tracks_fwd[85], block_out[44], block_out[40], block_out[38], block_out[34], down_tracks_out[74], up_tracks_out[85], left_tracks_fwd[86], block_out[44], block_out[40], block_out[38], block_out[34], down_tracks_out[73], up_tracks_out[86], left_tracks_fwd[87], block_out[44], block_out[40], block_out[38], block_out[34], down_tracks_out[72], up_tracks_out[87], left_tracks_fwd[88], block_out[44], block_out[40], block_out[38], block_out[34], down_tracks_out[71], up_tracks_out[88], left_tracks_fwd[89], block_out[44], block_out[40], block_out[38], block_out[34], down_tracks_out[70], up_tracks_out[89], left_tracks_fwd[90], block_out[44], block_out[40], block_out[38], block_out[34], down_tracks_out[69], up_tracks_out[90], left_tracks_fwd[91], block_out[44], block_out[40], block_out[38], block_out[34], down_tracks_out[68], up_tracks_out[91], left_tracks_fwd[92], block_out[44], block_out[40], block_out[38], block_out[34], down_tracks_out[67], up_tracks_out[92], left_tracks_fwd[93], block_out[44], block_out[40], block_out[38], block_out[34], down_tracks_out[66], up_tracks_out[93], left_tracks_fwd[94], block_out[44], block_out[40], block_out[38], block_out[34], down_tracks_out[65], up_tracks_out[94], left_tracks_fwd[95], block_out[44], block_out[40], block_out[38], block_out[34], down_tracks_out[48], up_tracks_out[79], left_tracks_fwd[64], block_out[36], block_out[32], block_out[30], block_out[26], down_tracks_out[63], up_tracks_out[64], left_tracks_fwd[65], block_out[36], block_out[32], block_out[30], block_out[26], down_tracks_out[62], up_tracks_out[65], left_tracks_fwd[66], block_out[36], block_out[32], block_out[30], block_out[26], down_tracks_out[61], up_tracks_out[66], left_tracks_fwd[67], block_out[36], block_out[32], block_out[30], block_out[26], down_tracks_out[60], up_tracks_out[67], left_tracks_fwd[68], block_out[36], block_out[32], block_out[30], block_out[26], down_tracks_out[59], up_tracks_out[68], left_tracks_fwd[69], block_out[36], block_out[32], block_out[30], block_out[26], down_tracks_out[58], up_tracks_out[69], left_tracks_fwd[70], block_out[36], block_out[32], block_out[30], block_out[26], down_tracks_out[57], up_tracks_out[70], left_tracks_fwd[71], block_out[36], block_out[32], block_out[30], block_out[26], down_tracks_out[56], up_tracks_out[71], left_tracks_fwd[72], block_out[36], block_out[32], block_out[30], block_out[26], down_tracks_out[55], up_tracks_out[72], left_tracks_fwd[73], block_out[36], block_out[32], block_out[30], block_out[26], down_tracks_out[54], up_tracks_out[73], left_tracks_fwd[74], block_out[36], block_out[32], block_out[30], block_out[26], down_tracks_out[53], up_tracks_out[74], left_tracks_fwd[75], block_out[36], block_out[32], block_out[30], block_out[26], down_tracks_out[52], up_tracks_out[75], left_tracks_fwd[76], block_out[36], block_out[32], block_out[30], block_out[26], down_tracks_out[51], up_tracks_out[76], left_tracks_fwd[77], block_out[36], block_out[32], block_out[30], block_out[26], down_tracks_out[50], up_tracks_out[77], left_tracks_fwd[78], block_out[36], block_out[32], block_out[30], block_out[26], down_tracks_out[49], up_tracks_out[78], left_tracks_fwd[79], block_out[36], block_out[32], block_out[30], block_out[26], down_tracks_out[32], up_tracks_out[63], left_tracks_fwd[48], block_out[28], block_out[24], block_out[22], block_out[18], down_tracks_out[47], up_tracks_out[48], left_tracks_fwd[49], block_out[28], block_out[24], block_out[22], block_out[18], down_tracks_out[46], up_tracks_out[49], left_tracks_fwd[50], block_out[28], block_out[24], block_out[22], block_out[18], down_tracks_out[45], up_tracks_out[50], left_tracks_fwd[51], block_out[28], block_out[24], block_out[22], block_out[18], down_tracks_out[44], up_tracks_out[51], left_tracks_fwd[52], block_out[28], block_out[24], block_out[22], block_out[18], down_tracks_out[43], up_tracks_out[52], left_tracks_fwd[53], block_out[28], block_out[24], block_out[22], block_out[18], down_tracks_out[42], up_tracks_out[53], left_tracks_fwd[54], block_out[28], block_out[24], block_out[22], block_out[18], down_tracks_out[41], up_tracks_out[54], left_tracks_fwd[55], block_out[28], block_out[24], block_out[22], block_out[18], down_tracks_out[40], up_tracks_out[55], left_tracks_fwd[56], block_out[28], block_out[24], block_out[22], block_out[18], down_tracks_out[39], up_tracks_out[56], left_tracks_fwd[57], block_out[28], block_out[24], block_out[22], block_out[18], down_tracks_out[38], up_tracks_out[57], left_tracks_fwd[58], block_out[28], block_out[24], block_out[22], block_out[18], down_tracks_out[37], up_tracks_out[58], left_tracks_fwd[59], block_out[28], block_out[24], block_out[22], block_out[18], down_tracks_out[36], up_tracks_out[59], left_tracks_fwd[60], block_out[28], block_out[24], block_out[22], block_out[18], down_tracks_out[35], up_tracks_out[60], left_tracks_fwd[61], block_out[28], block_out[24], block_out[22], block_out[18], down_tracks_out[34], up_tracks_out[61], left_tracks_fwd[62], block_out[28], block_out[24], block_out[22], block_out[18], down_tracks_out[33], up_tracks_out[62], left_tracks_fwd[63], block_out[28], block_out[24], block_out[22], block_out[18], down_tracks_out[16], up_tracks_out[47], left_tracks_fwd[32], block_out[20], block_out[16], block_out[14], block_out[10], down_tracks_out[31], up_tracks_out[32], left_tracks_fwd[33], block_out[20], block_out[16], block_out[14], block_out[10], down_tracks_out[30], up_tracks_out[33], left_tracks_fwd[34], block_out[20], block_out[16], block_out[14], block_out[10], down_tracks_out[29], up_tracks_out[34], left_tracks_fwd[35], block_out[20], block_out[16], block_out[14], block_out[10], down_tracks_out[28], up_tracks_out[35], left_tracks_fwd[36], block_out[20], block_out[16], block_out[14], block_out[10], down_tracks_out[27], up_tracks_out[36], left_tracks_fwd[37], block_out[20], block_out[16], block_out[14], block_out[10], down_tracks_out[26], up_tracks_out[37], left_tracks_fwd[38], block_out[20], block_out[16], block_out[14], block_out[10], down_tracks_out[25], up_tracks_out[38], left_tracks_fwd[39], block_out[20], block_out[16], block_out[14], block_out[10], down_tracks_out[24], up_tracks_out[39], left_tracks_fwd[40], block_out[20], block_out[16], block_out[14], block_out[10], down_tracks_out[23], up_tracks_out[40], left_tracks_fwd[41], block_out[20], block_out[16], block_out[14], block_out[10], down_tracks_out[22], up_tracks_out[41], left_tracks_fwd[42], block_out[20], block_out[16], block_out[14], block_out[10], down_tracks_out[21], up_tracks_out[42], left_tracks_fwd[43], block_out[20], block_out[16], block_out[14], block_out[10], down_tracks_out[20], up_tracks_out[43], left_tracks_fwd[44], block_out[20], block_out[16], block_out[14], block_out[10], down_tracks_out[19], up_tracks_out[44], left_tracks_fwd[45], block_out[20], block_out[16], block_out[14], block_out[10], down_tracks_out[18], up_tracks_out[45], left_tracks_fwd[46], block_out[20], block_out[16], block_out[14], block_out[10], down_tracks_out[17], up_tracks_out[46], left_tracks_fwd[47], block_out[20], block_out[16], block_out[14], block_out[10], down_tracks_out[0], up_tracks_out[31], left_tracks_fwd[16], block_out[12], block_out[8], block_out[6], block_out[2], down_tracks_out[15], up_tracks_out[16], left_tracks_fwd[17], block_out[12], block_out[8], block_out[6], block_out[2], down_tracks_out[14], up_tracks_out[17], left_tracks_fwd[18], block_out[12], block_out[8], block_out[6], block_out[2], down_tracks_out[13], up_tracks_out[18], left_tracks_fwd[19], block_out[12], block_out[8], block_out[6], block_out[2], down_tracks_out[12], up_tracks_out[19], left_tracks_fwd[20], block_out[12], block_out[8], block_out[6], block_out[2], down_tracks_out[11], up_tracks_out[20], left_tracks_fwd[21], block_out[12], block_out[8], block_out[6], block_out[2], down_tracks_out[10], up_tracks_out[21], left_tracks_fwd[22], block_out[12], block_out[8], block_out[6], block_out[2], down_tracks_out[9], up_tracks_out[22], left_tracks_fwd[23], block_out[12], block_out[8], block_out[6], block_out[2], down_tracks_out[8], up_tracks_out[23], left_tracks_fwd[24], block_out[12], block_out[8], block_out[6], block_out[2], down_tracks_out[7], up_tracks_out[24], left_tracks_fwd[25], block_out[12], block_out[8], block_out[6], block_out[2], down_tracks_out[6], up_tracks_out[25], left_tracks_fwd[26], block_out[12], block_out[8], block_out[6], block_out[2], down_tracks_out[5], up_tracks_out[26], left_tracks_fwd[27], block_out[12], block_out[8], block_out[6], block_out[2], down_tracks_out[4], up_tracks_out[27], left_tracks_fwd[28], block_out[12], block_out[8], block_out[6], block_out[2], down_tracks_out[3], up_tracks_out[28], left_tracks_fwd[29], block_out[12], block_out[8], block_out[6], block_out[2], down_tracks_out[2], up_tracks_out[29], left_tracks_fwd[30], block_out[12], block_out[8], block_out[6], block_out[2], down_tracks_out[1], up_tracks_out[30], left_tracks_fwd[31], block_out[12], block_out[8], block_out[6], block_out[2], 1'h0, up_tracks_out[15], left_tracks_fwd[0], block_out[4], block_out[0], 1'h0, inputs_i[64], 1'h0, up_tracks_out[0], left_tracks_fwd[1], block_out[4], block_out[0], 1'h0, inputs_i[64], 1'h0, up_tracks_out[1], left_tracks_fwd[2], block_out[4], block_out[0], 1'h0, inputs_i[65], 1'h0, up_tracks_out[2], left_tracks_fwd[3], block_out[4], block_out[0], 1'h0, inputs_i[65], 1'h0, up_tracks_out[3], left_tracks_fwd[4], block_out[4], block_out[0], 1'h0, inputs_i[66], 1'h0, up_tracks_out[4], left_tracks_fwd[5], block_out[4], block_out[0], 1'h0, inputs_i[66], 1'h0, up_tracks_out[5], left_tracks_fwd[6], block_out[4], block_out[0], 1'h0, inputs_i[67], 1'h0, up_tracks_out[6], left_tracks_fwd[7], block_out[4], block_out[0], 1'h0, inputs_i[67], 1'h0, up_tracks_out[7], left_tracks_fwd[8], block_out[4], block_out[0], 1'h0, inputs_i[68], 1'h0, up_tracks_out[8], left_tracks_fwd[9], block_out[4], block_out[0], 1'h0, inputs_i[68], 1'h0, up_tracks_out[9], left_tracks_fwd[10], block_out[4], block_out[0], 1'h0, inputs_i[69], 1'h0, up_tracks_out[10], left_tracks_fwd[11], block_out[4], block_out[0], 1'h0, inputs_i[69], 1'h0, up_tracks_out[11], left_tracks_fwd[12], block_out[4], block_out[0], 1'h0, inputs_i[70], 1'h0, up_tracks_out[12], left_tracks_fwd[13], block_out[4], block_out[0], 1'h0, inputs_i[70], 1'h0, up_tracks_out[13], left_tracks_fwd[14], block_out[4], block_out[0], 1'h0, inputs_i[71], 1'h0, up_tracks_out[14], left_tracks_fwd[15], block_out[4], block_out[0], 1'h0, inputs_i[71] };
+ assign left_tracks_out = { \horizontal_routing_network_x:1.horizontal_routing_network_y:1.routing_node_left:31083 , \horizontal_routing_network_x:1.horizontal_routing_network_y:2.routing_node_left:32225 , \horizontal_routing_network_x:1.horizontal_routing_network_y:3.routing_node_left:33367 , \horizontal_routing_network_x:1.horizontal_routing_network_y:4.routing_node_left:34509 , \horizontal_routing_network_x:1.horizontal_routing_network_y:5.routing_node_left:35651 , \horizontal_routing_network_x:1.horizontal_routing_network_y:6.routing_node_left:36793 , \horizontal_routing_network_x:1.horizontal_routing_network_y:7.routing_node_left:37935 , \horizontal_routing_network_x:1.horizontal_routing_network_y:8.routing_node_left:37957 , \horizontal_routing_network_x:2.horizontal_routing_network_y:1.routing_node_left:40888 , \horizontal_routing_network_x:2.horizontal_routing_network_y:2.routing_node_left:42030 , \horizontal_routing_network_x:2.horizontal_routing_network_y:3.routing_node_left:43172 , \horizontal_routing_network_x:2.horizontal_routing_network_y:4.routing_node_left:44314 , \horizontal_routing_network_x:2.horizontal_routing_network_y:5.routing_node_left:45456 , \horizontal_routing_network_x:2.horizontal_routing_network_y:6.routing_node_left:46598 , \horizontal_routing_network_x:2.horizontal_routing_network_y:7.routing_node_left:47740 , \horizontal_routing_network_x:2.horizontal_routing_network_y:8.routing_node_left:47762 };
+ assign right_tracks_in = { 1'h0, down_tracks_out[335], right_tracks_fwd[240], 1'h0, inputs_i[128], block_out[110], block_out[106], 1'h0, down_tracks_out[320], right_tracks_fwd[241], 1'h0, inputs_i[128], block_out[110], block_out[106], 1'h0, down_tracks_out[321], right_tracks_fwd[242], 1'h0, inputs_i[129], block_out[110], block_out[106], 1'h0, down_tracks_out[322], right_tracks_fwd[243], 1'h0, inputs_i[129], block_out[110], block_out[106], 1'h0, down_tracks_out[323], right_tracks_fwd[244], 1'h0, inputs_i[130], block_out[110], block_out[106], 1'h0, down_tracks_out[324], right_tracks_fwd[245], 1'h0, inputs_i[130], block_out[110], block_out[106], 1'h0, down_tracks_out[325], right_tracks_fwd[246], 1'h0, inputs_i[131], block_out[110], block_out[106], 1'h0, down_tracks_out[326], right_tracks_fwd[247], 1'h0, inputs_i[131], block_out[110], block_out[106], 1'h0, down_tracks_out[327], right_tracks_fwd[248], 1'h0, inputs_i[132], block_out[110], block_out[106], 1'h0, down_tracks_out[328], right_tracks_fwd[249], 1'h0, inputs_i[132], block_out[110], block_out[106], 1'h0, down_tracks_out[329], right_tracks_fwd[250], 1'h0, inputs_i[133], block_out[110], block_out[106], 1'h0, down_tracks_out[330], right_tracks_fwd[251], 1'h0, inputs_i[133], block_out[110], block_out[106], 1'h0, down_tracks_out[331], right_tracks_fwd[252], 1'h0, inputs_i[134], block_out[110], block_out[106], 1'h0, down_tracks_out[332], right_tracks_fwd[253], 1'h0, inputs_i[134], block_out[110], block_out[106], 1'h0, down_tracks_out[333], right_tracks_fwd[254], 1'h0, inputs_i[135], block_out[110], block_out[106], 1'h0, down_tracks_out[334], right_tracks_fwd[255], 1'h0, inputs_i[135], block_out[110], block_out[106], up_tracks_out[334], down_tracks_out[319], right_tracks_fwd[224], block_out[108], block_out[104], block_out[102], block_out[98], up_tracks_out[333], down_tracks_out[304], right_tracks_fwd[225], block_out[108], block_out[104], block_out[102], block_out[98], up_tracks_out[332], down_tracks_out[305], right_tracks_fwd[226], block_out[108], block_out[104], block_out[102], block_out[98], up_tracks_out[331], down_tracks_out[306], right_tracks_fwd[227], block_out[108], block_out[104], block_out[102], block_out[98], up_tracks_out[330], down_tracks_out[307], right_tracks_fwd[228], block_out[108], block_out[104], block_out[102], block_out[98], up_tracks_out[329], down_tracks_out[308], right_tracks_fwd[229], block_out[108], block_out[104], block_out[102], block_out[98], up_tracks_out[328], down_tracks_out[309], right_tracks_fwd[230], block_out[108], block_out[104], block_out[102], block_out[98], up_tracks_out[327], down_tracks_out[310], right_tracks_fwd[231], block_out[108], block_out[104], block_out[102], block_out[98], up_tracks_out[326], down_tracks_out[311], right_tracks_fwd[232], block_out[108], block_out[104], block_out[102], block_out[98], up_tracks_out[325], down_tracks_out[312], right_tracks_fwd[233], block_out[108], block_out[104], block_out[102], block_out[98], up_tracks_out[324], down_tracks_out[313], right_tracks_fwd[234], block_out[108], block_out[104], block_out[102], block_out[98], up_tracks_out[323], down_tracks_out[314], right_tracks_fwd[235], block_out[108], block_out[104], block_out[102], block_out[98], up_tracks_out[322], down_tracks_out[315], right_tracks_fwd[236], block_out[108], block_out[104], block_out[102], block_out[98], up_tracks_out[321], down_tracks_out[316], right_tracks_fwd[237], block_out[108], block_out[104], block_out[102], block_out[98], up_tracks_out[320], down_tracks_out[317], right_tracks_fwd[238], block_out[108], block_out[104], block_out[102], block_out[98], up_tracks_out[335], down_tracks_out[318], right_tracks_fwd[239], block_out[108], block_out[104], block_out[102], block_out[98], up_tracks_out[318], down_tracks_out[303], right_tracks_fwd[208], block_out[100], block_out[96], block_out[94], block_out[90], up_tracks_out[317], down_tracks_out[288], right_tracks_fwd[209], block_out[100], block_out[96], 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block_out[36], block_out[32], block_out[30], block_out[26], up_tracks_out[182], down_tracks_out[167], right_tracks_fwd[72], block_out[36], block_out[32], block_out[30], block_out[26], up_tracks_out[181], down_tracks_out[168], right_tracks_fwd[73], block_out[36], block_out[32], block_out[30], block_out[26], up_tracks_out[180], down_tracks_out[169], right_tracks_fwd[74], block_out[36], block_out[32], block_out[30], block_out[26], up_tracks_out[179], down_tracks_out[170], right_tracks_fwd[75], block_out[36], block_out[32], block_out[30], block_out[26], up_tracks_out[178], down_tracks_out[171], right_tracks_fwd[76], block_out[36], block_out[32], block_out[30], block_out[26], up_tracks_out[177], down_tracks_out[172], right_tracks_fwd[77], block_out[36], block_out[32], block_out[30], block_out[26], up_tracks_out[176], down_tracks_out[173], right_tracks_fwd[78], block_out[36], block_out[32], block_out[30], block_out[26], up_tracks_out[191], down_tracks_out[174], right_tracks_fwd[79], block_out[36], block_out[32], block_out[30], block_out[26], up_tracks_out[174], down_tracks_out[159], right_tracks_fwd[48], block_out[28], block_out[24], block_out[22], block_out[18], up_tracks_out[173], down_tracks_out[144], right_tracks_fwd[49], block_out[28], block_out[24], block_out[22], block_out[18], up_tracks_out[172], down_tracks_out[145], right_tracks_fwd[50], block_out[28], block_out[24], block_out[22], block_out[18], up_tracks_out[171], down_tracks_out[146], right_tracks_fwd[51], block_out[28], block_out[24], block_out[22], block_out[18], up_tracks_out[170], down_tracks_out[147], right_tracks_fwd[52], block_out[28], block_out[24], block_out[22], block_out[18], up_tracks_out[169], down_tracks_out[148], right_tracks_fwd[53], block_out[28], block_out[24], block_out[22], block_out[18], up_tracks_out[168], down_tracks_out[149], right_tracks_fwd[54], block_out[28], block_out[24], block_out[22], block_out[18], up_tracks_out[167], down_tracks_out[150], right_tracks_fwd[55], block_out[28], block_out[24], block_out[22], block_out[18], up_tracks_out[166], down_tracks_out[151], right_tracks_fwd[56], block_out[28], block_out[24], block_out[22], block_out[18], up_tracks_out[165], down_tracks_out[152], right_tracks_fwd[57], block_out[28], block_out[24], block_out[22], block_out[18], up_tracks_out[164], down_tracks_out[153], right_tracks_fwd[58], block_out[28], block_out[24], block_out[22], block_out[18], up_tracks_out[163], down_tracks_out[154], right_tracks_fwd[59], block_out[28], block_out[24], block_out[22], block_out[18], up_tracks_out[162], down_tracks_out[155], right_tracks_fwd[60], block_out[28], block_out[24], block_out[22], block_out[18], up_tracks_out[161], down_tracks_out[156], right_tracks_fwd[61], block_out[28], block_out[24], block_out[22], block_out[18], up_tracks_out[160], down_tracks_out[157], right_tracks_fwd[62], block_out[28], block_out[24], block_out[22], block_out[18], up_tracks_out[175], down_tracks_out[158], right_tracks_fwd[63], block_out[28], block_out[24], block_out[22], block_out[18], up_tracks_out[158], down_tracks_out[143], right_tracks_fwd[32], block_out[20], block_out[16], block_out[14], block_out[10], up_tracks_out[157], down_tracks_out[128], right_tracks_fwd[33], block_out[20], block_out[16], block_out[14], block_out[10], up_tracks_out[156], down_tracks_out[129], right_tracks_fwd[34], block_out[20], block_out[16], block_out[14], block_out[10], up_tracks_out[155], down_tracks_out[130], right_tracks_fwd[35], block_out[20], block_out[16], block_out[14], block_out[10], up_tracks_out[154], down_tracks_out[131], right_tracks_fwd[36], block_out[20], block_out[16], block_out[14], block_out[10], up_tracks_out[153], down_tracks_out[132], right_tracks_fwd[37], block_out[20], block_out[16], block_out[14], block_out[10], up_tracks_out[152], down_tracks_out[133], right_tracks_fwd[38], block_out[20], block_out[16], block_out[14], block_out[10], up_tracks_out[151], down_tracks_out[134], right_tracks_fwd[39], block_out[20], block_out[16], block_out[14], block_out[10], up_tracks_out[150], down_tracks_out[135], right_tracks_fwd[40], block_out[20], block_out[16], block_out[14], block_out[10], up_tracks_out[149], down_tracks_out[136], right_tracks_fwd[41], block_out[20], block_out[16], block_out[14], block_out[10], up_tracks_out[148], down_tracks_out[137], right_tracks_fwd[42], block_out[20], block_out[16], block_out[14], block_out[10], up_tracks_out[147], down_tracks_out[138], right_tracks_fwd[43], block_out[20], block_out[16], block_out[14], block_out[10], up_tracks_out[146], down_tracks_out[139], right_tracks_fwd[44], block_out[20], block_out[16], block_out[14], block_out[10], up_tracks_out[145], down_tracks_out[140], right_tracks_fwd[45], block_out[20], block_out[16], block_out[14], block_out[10], up_tracks_out[144], down_tracks_out[141], right_tracks_fwd[46], block_out[20], block_out[16], block_out[14], block_out[10], up_tracks_out[159], down_tracks_out[142], right_tracks_fwd[47], block_out[20], block_out[16], block_out[14], block_out[10], up_tracks_out[142], down_tracks_out[127], right_tracks_fwd[16], block_out[12], block_out[8], block_out[6], block_out[2], up_tracks_out[141], down_tracks_out[112], right_tracks_fwd[17], block_out[12], block_out[8], block_out[6], block_out[2], up_tracks_out[140], down_tracks_out[113], right_tracks_fwd[18], block_out[12], block_out[8], block_out[6], block_out[2], up_tracks_out[139], down_tracks_out[114], right_tracks_fwd[19], block_out[12], block_out[8], block_out[6], block_out[2], up_tracks_out[138], down_tracks_out[115], right_tracks_fwd[20], block_out[12], block_out[8], block_out[6], block_out[2], up_tracks_out[137], down_tracks_out[116], right_tracks_fwd[21], block_out[12], block_out[8], block_out[6], block_out[2], up_tracks_out[136], down_tracks_out[117], right_tracks_fwd[22], block_out[12], block_out[8], block_out[6], block_out[2], up_tracks_out[135], down_tracks_out[118], right_tracks_fwd[23], block_out[12], block_out[8], block_out[6], block_out[2], up_tracks_out[134], down_tracks_out[119], right_tracks_fwd[24], block_out[12], block_out[8], block_out[6], block_out[2], up_tracks_out[133], down_tracks_out[120], right_tracks_fwd[25], block_out[12], block_out[8], block_out[6], block_out[2], up_tracks_out[132], down_tracks_out[121], right_tracks_fwd[26], block_out[12], block_out[8], block_out[6], block_out[2], up_tracks_out[131], down_tracks_out[122], right_tracks_fwd[27], block_out[12], block_out[8], block_out[6], block_out[2], up_tracks_out[130], down_tracks_out[123], right_tracks_fwd[28], block_out[12], block_out[8], block_out[6], block_out[2], up_tracks_out[129], down_tracks_out[124], right_tracks_fwd[29], block_out[12], block_out[8], block_out[6], block_out[2], up_tracks_out[128], down_tracks_out[125], right_tracks_fwd[30], block_out[12], block_out[8], block_out[6], block_out[2], up_tracks_out[143], down_tracks_out[126], right_tracks_fwd[31], block_out[12], block_out[8], block_out[6], block_out[2], up_tracks_out[126], 1'h0, right_tracks_fwd[0], block_out[4], block_out[0], 1'h0, inputs_i[64], up_tracks_out[125], 1'h0, right_tracks_fwd[1], block_out[4], block_out[0], 1'h0, inputs_i[64], up_tracks_out[124], 1'h0, right_tracks_fwd[2], block_out[4], block_out[0], 1'h0, inputs_i[65], up_tracks_out[123], 1'h0, right_tracks_fwd[3], block_out[4], block_out[0], 1'h0, inputs_i[65], up_tracks_out[122], 1'h0, right_tracks_fwd[4], block_out[4], block_out[0], 1'h0, inputs_i[66], up_tracks_out[121], 1'h0, right_tracks_fwd[5], block_out[4], block_out[0], 1'h0, inputs_i[66], up_tracks_out[120], 1'h0, right_tracks_fwd[6], block_out[4], block_out[0], 1'h0, inputs_i[67], up_tracks_out[119], 1'h0, right_tracks_fwd[7], block_out[4], block_out[0], 1'h0, inputs_i[67], up_tracks_out[118], 1'h0, right_tracks_fwd[8], block_out[4], block_out[0], 1'h0, inputs_i[68], up_tracks_out[117], 1'h0, right_tracks_fwd[9], block_out[4], block_out[0], 1'h0, inputs_i[68], up_tracks_out[116], 1'h0, right_tracks_fwd[10], block_out[4], block_out[0], 1'h0, inputs_i[69], up_tracks_out[115], 1'h0, right_tracks_fwd[11], block_out[4], block_out[0], 1'h0, inputs_i[69], up_tracks_out[114], 1'h0, right_tracks_fwd[12], block_out[4], block_out[0], 1'h0, inputs_i[70], up_tracks_out[113], 1'h0, right_tracks_fwd[13], block_out[4], block_out[0], 1'h0, inputs_i[70], up_tracks_out[112], 1'h0, right_tracks_fwd[14], block_out[4], block_out[0], 1'h0, inputs_i[71], up_tracks_out[127], 1'h0, right_tracks_fwd[15], block_out[4], block_out[0], 1'h0, inputs_i[71] };
+ assign right_tracks_out = { \horizontal_routing_network_x:1.horizontal_routing_network_y:1.routing_node_right:31093 , \horizontal_routing_network_x:1.horizontal_routing_network_y:2.routing_node_right:32235 , \horizontal_routing_network_x:1.horizontal_routing_network_y:3.routing_node_right:33377 , \horizontal_routing_network_x:1.horizontal_routing_network_y:4.routing_node_right:34519 , \horizontal_routing_network_x:1.horizontal_routing_network_y:5.routing_node_right:35661 , \horizontal_routing_network_x:1.horizontal_routing_network_y:6.routing_node_right:36803 , \horizontal_routing_network_x:1.horizontal_routing_network_y:7.routing_node_right:37945 , \horizontal_routing_network_x:1.horizontal_routing_network_y:8.routing_node_right:39420 , \horizontal_routing_network_x:2.horizontal_routing_network_y:1.routing_node_right:40898 , \horizontal_routing_network_x:2.horizontal_routing_network_y:2.routing_node_right:42040 , \horizontal_routing_network_x:2.horizontal_routing_network_y:3.routing_node_right:43182 , \horizontal_routing_network_x:2.horizontal_routing_network_y:4.routing_node_right:44324 , \horizontal_routing_network_x:2.horizontal_routing_network_y:5.routing_node_right:45466 , \horizontal_routing_network_x:2.horizontal_routing_network_y:6.routing_node_right:46608 , \horizontal_routing_network_x:2.horizontal_routing_network_y:7.routing_node_right:47750 , \horizontal_routing_network_x:2.horizontal_routing_network_y:8.routing_node_right:49225 };
+ assign up_tracks_fwd = { 16'h0000, up_tracks_out[335:240], 16'h0000, up_tracks_out[223:128], 16'h0000, up_tracks_out[111:16] };
+ assign down_tracks_fwd = { down_tracks_out[319:224], 16'h0000, down_tracks_out[207:112], 16'h0000, down_tracks_out[95:0], 16'h0000 };
+ assign left_tracks_fwd = { left_tracks_out[127:0], 128'h00000000000000000000000000000000 };
+ assign right_tracks_fwd = { 128'h00000000000000000000000000000000, right_tracks_out[255:128] };
+ assign \vertical_routing_network_x:1.vertical_routing_network_y:1.routing_node_up:2416 = _031_;
+ assign \vertical_routing_network_x:1.vertical_routing_network_y:1.routing_node_up:2418 = _032_;
+ assign \vertical_routing_network_x:1.vertical_routing_network_y:1.routing_node_down:2426 = _033_;
+ assign \vertical_routing_network_x:1.vertical_routing_network_y:1.routing_node_down:2428 = _034_;
+ assign \vertical_routing_network_x:1.vertical_routing_network_y:2.routing_node_up:3894 = _037_;
+ assign \vertical_routing_network_x:1.vertical_routing_network_y:2.routing_node_up:3896 = _038_;
+ assign \vertical_routing_network_x:1.vertical_routing_network_y:2.routing_node_down:3904 = _039_;
+ assign \vertical_routing_network_x:1.vertical_routing_network_y:2.routing_node_down:3906 = _040_;
+ assign \vertical_routing_network_x:1.vertical_routing_network_y:3.routing_node_up:5372 = _043_;
+ assign \vertical_routing_network_x:1.vertical_routing_network_y:3.routing_node_up:5374 = _044_;
+ assign \vertical_routing_network_x:1.vertical_routing_network_y:3.routing_node_down:5382 = _045_;
+ assign \vertical_routing_network_x:1.vertical_routing_network_y:3.routing_node_down:5384 = _046_;
+ assign \vertical_routing_network_x:1.vertical_routing_network_y:4.routing_node_up:6850 = _049_;
+ assign \vertical_routing_network_x:1.vertical_routing_network_y:4.routing_node_up:6852 = _050_;
+ assign \vertical_routing_network_x:1.vertical_routing_network_y:4.routing_node_down:6860 = _051_;
+ assign \vertical_routing_network_x:1.vertical_routing_network_y:4.routing_node_down:6862 = _052_;
+ assign \vertical_routing_network_x:1.vertical_routing_network_y:5.routing_node_up:8328 = _055_;
+ assign \vertical_routing_network_x:1.vertical_routing_network_y:5.routing_node_up:8330 = _056_;
+ assign \vertical_routing_network_x:1.vertical_routing_network_y:5.routing_node_down:8338 = _057_;
+ assign \vertical_routing_network_x:1.vertical_routing_network_y:5.routing_node_down:8340 = _058_;
+ assign \vertical_routing_network_x:1.vertical_routing_network_y:6.routing_node_up:9806 = _061_;
+ assign \vertical_routing_network_x:1.vertical_routing_network_y:6.routing_node_up:9808 = _062_;
+ assign \vertical_routing_network_x:1.vertical_routing_network_y:6.routing_node_down:9816 = _063_;
+ assign \vertical_routing_network_x:1.vertical_routing_network_y:6.routing_node_down:9818 = _064_;
+ assign \vertical_routing_network_x:1.vertical_routing_network_y:7.routing_node_up:11284 = _067_;
+ assign \vertical_routing_network_x:1.vertical_routing_network_y:7.routing_node_up:11286 = _068_;
+ assign \vertical_routing_network_x:1.vertical_routing_network_y:7.routing_node_down:11294 = _069_;
+ assign \vertical_routing_network_x:1.vertical_routing_network_y:7.routing_node_down:11296 = _070_;
+ assign \vertical_routing_network_x:2.vertical_routing_network_y:1.routing_node_up:12426 = _071_;
+ assign \vertical_routing_network_x:2.vertical_routing_network_y:1.routing_node_up:12428 = _072_;
+ assign \vertical_routing_network_x:2.vertical_routing_network_y:1.routing_node_down:12436 = _073_;
+ assign \vertical_routing_network_x:2.vertical_routing_network_y:1.routing_node_down:12438 = _074_;
+ assign \vertical_routing_network_x:2.vertical_routing_network_y:2.routing_node_up:13568 = _075_;
+ assign \vertical_routing_network_x:2.vertical_routing_network_y:2.routing_node_up:13570 = _076_;
+ assign \vertical_routing_network_x:2.vertical_routing_network_y:2.routing_node_down:13578 = _077_;
+ assign \vertical_routing_network_x:2.vertical_routing_network_y:2.routing_node_down:13580 = _078_;
+ assign \vertical_routing_network_x:2.vertical_routing_network_y:3.routing_node_up:14710 = _079_;
+ assign \vertical_routing_network_x:2.vertical_routing_network_y:3.routing_node_up:14712 = _080_;
+ assign \vertical_routing_network_x:2.vertical_routing_network_y:3.routing_node_down:14720 = _081_;
+ assign \vertical_routing_network_x:2.vertical_routing_network_y:3.routing_node_down:14722 = _082_;
+ assign \vertical_routing_network_x:2.vertical_routing_network_y:4.routing_node_up:15852 = _083_;
+ assign \vertical_routing_network_x:2.vertical_routing_network_y:4.routing_node_up:15854 = _084_;
+ assign \vertical_routing_network_x:2.vertical_routing_network_y:4.routing_node_down:15862 = _085_;
+ assign \vertical_routing_network_x:2.vertical_routing_network_y:4.routing_node_down:15864 = _086_;
+ assign \vertical_routing_network_x:2.vertical_routing_network_y:5.routing_node_up:16994 = _087_;
+ assign \vertical_routing_network_x:2.vertical_routing_network_y:5.routing_node_up:16996 = _088_;
+ assign \vertical_routing_network_x:2.vertical_routing_network_y:5.routing_node_down:17004 = _089_;
+ assign \vertical_routing_network_x:2.vertical_routing_network_y:5.routing_node_down:17006 = _090_;
+ assign \vertical_routing_network_x:2.vertical_routing_network_y:6.routing_node_up:18136 = _091_;
+ assign \vertical_routing_network_x:2.vertical_routing_network_y:6.routing_node_up:18138 = _092_;
+ assign \vertical_routing_network_x:2.vertical_routing_network_y:6.routing_node_down:18146 = _093_;
+ assign \vertical_routing_network_x:2.vertical_routing_network_y:6.routing_node_down:18148 = _094_;
+ assign \vertical_routing_network_x:2.vertical_routing_network_y:7.routing_node_up:19278 = _095_;
+ assign \vertical_routing_network_x:2.vertical_routing_network_y:7.routing_node_up:19280 = _096_;
+ assign \vertical_routing_network_x:2.vertical_routing_network_y:7.routing_node_down:19288 = _097_;
+ assign \vertical_routing_network_x:2.vertical_routing_network_y:7.routing_node_down:19290 = _098_;
+ assign \vertical_routing_network_x:3.vertical_routing_network_y:1.routing_node_up:19300 = _099_;
+ assign \vertical_routing_network_x:3.vertical_routing_network_y:1.routing_node_up:19302 = _100_;
+ assign \vertical_routing_network_x:3.vertical_routing_network_y:1.routing_node_down:20763 = _103_;
+ assign \vertical_routing_network_x:3.vertical_routing_network_y:1.routing_node_down:20765 = _104_;
+ assign \vertical_routing_network_x:3.vertical_routing_network_y:2.routing_node_up:20775 = _105_;
+ assign \vertical_routing_network_x:3.vertical_routing_network_y:2.routing_node_up:20777 = _106_;
+ assign \vertical_routing_network_x:3.vertical_routing_network_y:2.routing_node_down:22238 = _109_;
+ assign \vertical_routing_network_x:3.vertical_routing_network_y:2.routing_node_down:22240 = _110_;
+ assign \vertical_routing_network_x:3.vertical_routing_network_y:3.routing_node_up:22250 = _111_;
+ assign \vertical_routing_network_x:3.vertical_routing_network_y:3.routing_node_up:22252 = _112_;
+ assign \vertical_routing_network_x:3.vertical_routing_network_y:3.routing_node_down:23713 = _115_;
+ assign \vertical_routing_network_x:3.vertical_routing_network_y:3.routing_node_down:23715 = _116_;
+ assign \vertical_routing_network_x:3.vertical_routing_network_y:4.routing_node_up:23725 = _117_;
+ assign \vertical_routing_network_x:3.vertical_routing_network_y:4.routing_node_up:23727 = _118_;
+ assign \vertical_routing_network_x:3.vertical_routing_network_y:4.routing_node_down:25188 = _121_;
+ assign \vertical_routing_network_x:3.vertical_routing_network_y:4.routing_node_down:25190 = _122_;
+ assign \vertical_routing_network_x:3.vertical_routing_network_y:5.routing_node_up:25200 = _123_;
+ assign \vertical_routing_network_x:3.vertical_routing_network_y:5.routing_node_up:25202 = _124_;
+ assign \vertical_routing_network_x:3.vertical_routing_network_y:5.routing_node_down:26663 = _127_;
+ assign \vertical_routing_network_x:3.vertical_routing_network_y:5.routing_node_down:26665 = _128_;
+ assign \vertical_routing_network_x:3.vertical_routing_network_y:6.routing_node_up:26675 = _129_;
+ assign \vertical_routing_network_x:3.vertical_routing_network_y:6.routing_node_up:26677 = _130_;
+ assign \vertical_routing_network_x:3.vertical_routing_network_y:6.routing_node_down:28138 = _133_;
+ assign \vertical_routing_network_x:3.vertical_routing_network_y:6.routing_node_down:28140 = _134_;
+ assign \vertical_routing_network_x:3.vertical_routing_network_y:7.routing_node_up:28150 = _135_;
+ assign \vertical_routing_network_x:3.vertical_routing_network_y:7.routing_node_up:28152 = _136_;
+ assign \vertical_routing_network_x:3.vertical_routing_network_y:7.routing_node_down:29613 = _139_;
+ assign \vertical_routing_network_x:3.vertical_routing_network_y:7.routing_node_down:29615 = _140_;
+ assign \horizontal_routing_network_x:1.horizontal_routing_network_y:1.routing_node_left:31081 = _143_;
+ assign \horizontal_routing_network_x:1.horizontal_routing_network_y:1.routing_node_left:31083 = _144_;
+ assign \horizontal_routing_network_x:1.horizontal_routing_network_y:1.routing_node_right:31091 = _145_;
+ assign \horizontal_routing_network_x:1.horizontal_routing_network_y:1.routing_node_right:31093 = _146_;
+ assign \horizontal_routing_network_x:1.horizontal_routing_network_y:2.routing_node_left:32223 = _147_;
+ assign \horizontal_routing_network_x:1.horizontal_routing_network_y:2.routing_node_left:32225 = _148_;
+ assign \horizontal_routing_network_x:1.horizontal_routing_network_y:2.routing_node_right:32233 = _149_;
+ assign \horizontal_routing_network_x:1.horizontal_routing_network_y:2.routing_node_right:32235 = _150_;
+ assign \horizontal_routing_network_x:1.horizontal_routing_network_y:3.routing_node_left:33365 = _151_;
+ assign \horizontal_routing_network_x:1.horizontal_routing_network_y:3.routing_node_left:33367 = _152_;
+ assign \horizontal_routing_network_x:1.horizontal_routing_network_y:3.routing_node_right:33375 = _153_;
+ assign \horizontal_routing_network_x:1.horizontal_routing_network_y:3.routing_node_right:33377 = _154_;
+ assign \horizontal_routing_network_x:1.horizontal_routing_network_y:4.routing_node_left:34507 = _155_;
+ assign \horizontal_routing_network_x:1.horizontal_routing_network_y:4.routing_node_left:34509 = _156_;
+ assign \horizontal_routing_network_x:1.horizontal_routing_network_y:4.routing_node_right:34517 = _157_;
+ assign \horizontal_routing_network_x:1.horizontal_routing_network_y:4.routing_node_right:34519 = _158_;
+ assign \horizontal_routing_network_x:1.horizontal_routing_network_y:5.routing_node_left:35649 = _159_;
+ assign \horizontal_routing_network_x:1.horizontal_routing_network_y:5.routing_node_left:35651 = _160_;
+ assign \horizontal_routing_network_x:1.horizontal_routing_network_y:5.routing_node_right:35659 = _161_;
+ assign \horizontal_routing_network_x:1.horizontal_routing_network_y:5.routing_node_right:35661 = _162_;
+ assign \horizontal_routing_network_x:1.horizontal_routing_network_y:6.routing_node_left:36791 = _163_;
+ assign \horizontal_routing_network_x:1.horizontal_routing_network_y:6.routing_node_left:36793 = _164_;
+ assign \horizontal_routing_network_x:1.horizontal_routing_network_y:6.routing_node_right:36801 = _165_;
+ assign \horizontal_routing_network_x:1.horizontal_routing_network_y:6.routing_node_right:36803 = _166_;
+ assign \horizontal_routing_network_x:1.horizontal_routing_network_y:7.routing_node_left:37933 = _167_;
+ assign \horizontal_routing_network_x:1.horizontal_routing_network_y:7.routing_node_left:37935 = _168_;
+ assign \horizontal_routing_network_x:1.horizontal_routing_network_y:7.routing_node_right:37943 = _169_;
+ assign \horizontal_routing_network_x:1.horizontal_routing_network_y:7.routing_node_right:37945 = _170_;
+ assign \horizontal_routing_network_x:1.horizontal_routing_network_y:8.routing_node_left:37955 = _171_;
+ assign \horizontal_routing_network_x:1.horizontal_routing_network_y:8.routing_node_left:37957 = _172_;
+ assign \horizontal_routing_network_x:1.horizontal_routing_network_y:8.routing_node_right:39418 = _175_;
+ assign \horizontal_routing_network_x:1.horizontal_routing_network_y:8.routing_node_right:39420 = _176_;
+ assign \horizontal_routing_network_x:2.horizontal_routing_network_y:1.routing_node_left:40886 = _179_;
+ assign \horizontal_routing_network_x:2.horizontal_routing_network_y:1.routing_node_left:40888 = _180_;
+ assign \horizontal_routing_network_x:2.horizontal_routing_network_y:1.routing_node_right:40896 = _181_;
+ assign \horizontal_routing_network_x:2.horizontal_routing_network_y:1.routing_node_right:40898 = _182_;
+ assign \horizontal_routing_network_x:2.horizontal_routing_network_y:2.routing_node_left:42028 = _183_;
+ assign \horizontal_routing_network_x:2.horizontal_routing_network_y:2.routing_node_left:42030 = _184_;
+ assign \horizontal_routing_network_x:2.horizontal_routing_network_y:2.routing_node_right:42038 = _185_;
+ assign \horizontal_routing_network_x:2.horizontal_routing_network_y:2.routing_node_right:42040 = _186_;
+ assign \horizontal_routing_network_x:2.horizontal_routing_network_y:3.routing_node_left:43170 = _187_;
+ assign \horizontal_routing_network_x:2.horizontal_routing_network_y:3.routing_node_left:43172 = _188_;
+ assign \horizontal_routing_network_x:2.horizontal_routing_network_y:3.routing_node_right:43180 = _189_;
+ assign \horizontal_routing_network_x:2.horizontal_routing_network_y:3.routing_node_right:43182 = _190_;
+ assign \horizontal_routing_network_x:2.horizontal_routing_network_y:4.routing_node_left:44312 = _191_;
+ assign \horizontal_routing_network_x:2.horizontal_routing_network_y:4.routing_node_left:44314 = _192_;
+ assign \horizontal_routing_network_x:2.horizontal_routing_network_y:4.routing_node_right:44322 = _193_;
+ assign \horizontal_routing_network_x:2.horizontal_routing_network_y:4.routing_node_right:44324 = _194_;
+ assign \horizontal_routing_network_x:2.horizontal_routing_network_y:5.routing_node_left:45454 = _195_;
+ assign \horizontal_routing_network_x:2.horizontal_routing_network_y:5.routing_node_left:45456 = _196_;
+ assign \horizontal_routing_network_x:2.horizontal_routing_network_y:5.routing_node_right:45464 = _197_;
+ assign \horizontal_routing_network_x:2.horizontal_routing_network_y:5.routing_node_right:45466 = _198_;
+ assign \horizontal_routing_network_x:2.horizontal_routing_network_y:6.routing_node_left:46596 = _199_;
+ assign \horizontal_routing_network_x:2.horizontal_routing_network_y:6.routing_node_left:46598 = _200_;
+ assign \horizontal_routing_network_x:2.horizontal_routing_network_y:6.routing_node_right:46606 = _201_;
+ assign \horizontal_routing_network_x:2.horizontal_routing_network_y:6.routing_node_right:46608 = _202_;
+ assign \horizontal_routing_network_x:2.horizontal_routing_network_y:7.routing_node_left:47738 = _203_;
+ assign \horizontal_routing_network_x:2.horizontal_routing_network_y:7.routing_node_left:47740 = _204_;
+ assign \horizontal_routing_network_x:2.horizontal_routing_network_y:7.routing_node_right:47748 = _205_;
+ assign \horizontal_routing_network_x:2.horizontal_routing_network_y:7.routing_node_right:47750 = _206_;
+ assign \horizontal_routing_network_x:2.horizontal_routing_network_y:8.routing_node_left:47760 = _207_;
+ assign \horizontal_routing_network_x:2.horizontal_routing_network_y:8.routing_node_left:47762 = _208_;
+ assign \horizontal_routing_network_x:2.horizontal_routing_network_y:8.routing_node_right:49223 = _211_;
+ assign \horizontal_routing_network_x:2.horizontal_routing_network_y:8.routing_node_right:49225 = _212_;
+ assign config_block_o = { block_cfg_shift_chain[0], block_cfg_shift_chain[8] };
+ assign config_vrnode_o = { vrnode_cfg_shift_chain[8], vrnode_cfg_shift_chain[17], vrnode_cfg_shift_chain[26], vrnode_cfg_shift_chain[35], vrnode_cfg_shift_chain[44], vrnode_cfg_shift_chain[53], vrnode_cfg_shift_chain[62] };
+ assign config_hrnode_o = { hrnode_cfg_shift_chain[18], hrnode_cfg_shift_chain[37] };
+ assign outputs_o = { _178_, _142_, _138_, _132_, _126_, _120_, _114_, _108_, _102_, _210_, _174_, _066_, _060_, _054_, _048_, _042_, _036_, _030_ };
+endmodule
+
+module fpga_io_mux(config_clk_i, config_ena_i, config_shift_i, route_i, config_shift_o, pins_o);
+ wire _00_;
+ wire _01_;
+ wire _02_;
+ wire _03_;
+ wire _04_;
+ wire _05_;
+ wire _06_;
+ wire _07_;
+ wire _08_;
+ wire _09_;
+ wire _10_;
+ wire _11_;
+ wire _12_;
+ wire _13_;
+ wire _14_;
+ wire _15_;
+ wire [8:0] config_chain;
+ input config_clk_i;
+ wire config_clk_i;
+ input config_ena_i;
+ wire config_ena_i;
+ input config_shift_i;
+ wire config_shift_i;
+ output config_shift_o;
+ wire config_shift_o;
+ output [7:0] pins_o;
+ wire [7:0] pins_o;
+ input [31:0] route_i;
+ wire [31:0] route_i;
+ fpga_routing_mux_wcfg_4_2_18446744073709551615 \muxes:1.io_mux (
+ .config_clk_i(config_clk_i),
+ .config_ena_i(config_ena_i),
+ .config_shift_i(config_chain[8]),
+ .config_shift_o(_00_),
+ .route_i({ route_i[24], route_i[16], route_i[8], route_i[0] }),
+ .route_o(_01_)
+ );
+ fpga_routing_mux_wcfg_4_2_18446744073709551615 \muxes:2.io_mux (
+ .config_clk_i(config_clk_i),
+ .config_ena_i(config_ena_i),
+ .config_shift_i(config_chain[7]),
+ .config_shift_o(_02_),
+ .route_i({ route_i[25], route_i[17], route_i[9], route_i[1] }),
+ .route_o(_03_)
+ );
+ fpga_routing_mux_wcfg_4_2_18446744073709551615 \muxes:3.io_mux (
+ .config_clk_i(config_clk_i),
+ .config_ena_i(config_ena_i),
+ .config_shift_i(config_chain[6]),
+ .config_shift_o(_04_),
+ .route_i({ route_i[26], route_i[18], route_i[10], route_i[2] }),
+ .route_o(_05_)
+ );
+ fpga_routing_mux_wcfg_4_2_18446744073709551615 \muxes:4.io_mux (
+ .config_clk_i(config_clk_i),
+ .config_ena_i(config_ena_i),
+ .config_shift_i(config_chain[5]),
+ .config_shift_o(_06_),
+ .route_i({ route_i[27], route_i[19], route_i[11], route_i[3] }),
+ .route_o(_07_)
+ );
+ fpga_routing_mux_wcfg_4_2_18446744073709551615 \muxes:5.io_mux (
+ .config_clk_i(config_clk_i),
+ .config_ena_i(config_ena_i),
+ .config_shift_i(config_chain[4]),
+ .config_shift_o(_08_),
+ .route_i({ route_i[28], route_i[20], route_i[12], route_i[4] }),
+ .route_o(_09_)
+ );
+ fpga_routing_mux_wcfg_4_2_18446744073709551615 \muxes:6.io_mux (
+ .config_clk_i(config_clk_i),
+ .config_ena_i(config_ena_i),
+ .config_shift_i(config_chain[3]),
+ .config_shift_o(_10_),
+ .route_i({ route_i[29], route_i[21], route_i[13], route_i[5] }),
+ .route_o(_11_)
+ );
+ fpga_routing_mux_wcfg_4_2_18446744073709551615 \muxes:7.io_mux (
+ .config_clk_i(config_clk_i),
+ .config_ena_i(config_ena_i),
+ .config_shift_i(config_chain[2]),
+ .config_shift_o(_12_),
+ .route_i({ route_i[30], route_i[22], route_i[14], route_i[6] }),
+ .route_o(_13_)
+ );
+ fpga_routing_mux_wcfg_4_2_18446744073709551615 \muxes:8.io_mux (
+ .config_clk_i(config_clk_i),
+ .config_ena_i(config_ena_i),
+ .config_shift_i(config_chain[1]),
+ .config_shift_o(_14_),
+ .route_i({ route_i[31], route_i[23], route_i[15], route_i[7] }),
+ .route_o(_15_)
+ );
+ assign config_chain = { config_shift_i, _00_, _02_, _04_, _06_, _08_, _10_, _12_, _14_ };
+ assign config_shift_o = config_chain[0];
+ assign pins_o = { _15_, _13_, _11_, _09_, _07_, _05_, _03_, _01_ };
+endmodule
+
+module fpga_routing_mux_4_2_18446744073709551615(config_i, route_i, route_o);
+ wire _0_;
+ wire _1_;
+ wire _2_;
+ input [1:0] config_i;
+ wire [1:0] config_i;
+ input [3:0] route_i;
+ wire [3:0] route_i;
+ wire [3:0] route_int;
+ output route_o;
+ wire route_o;
+ assign _0_ = config_i[0] ? route_int[1] : route_int[0];
+ assign _1_ = config_i[0] ? route_int[3] : route_int[2];
+ assign _2_ = config_i[1] ? _1_ : _0_;
+ assign route_int = route_i;
+ assign route_o = _2_;
+endmodule
+
+module fpga_routing_mux_7_3_7(config_i, route_i, route_o);
+ wire _00_;
+ wire _01_;
+ wire _02_;
+ wire _03_;
+ wire _04_;
+ wire _05_;
+ wire _06_;
+ input [2:0] config_i;
+ wire [2:0] config_i;
+ input [6:0] route_i;
+ wire [6:0] route_i;
+ wire [7:0] route_int;
+ output route_o;
+ wire route_o;
+ assign _00_ = config_i[0] ? route_int[1] : route_int[0];
+ assign _01_ = config_i[0] ? route_int[5] : route_int[4];
+ assign _02_ = config_i[0] ? route_int[3] : route_int[2];
+ assign _03_ = config_i[0] ? route_int[7] : route_int[6];
+ assign _04_ = config_i[1] ? _02_ : _00_;
+ assign _05_ = config_i[1] ? _03_ : _01_;
+ assign _06_ = config_i[2] ? _05_ : _04_;
+ assign route_int = { 1'h0, route_i };
+ assign route_o = _06_;
+endmodule
+
+module fpga_routing_mux_wcfg_4_2_18446744073709551615(config_clk_i, config_ena_i, config_shift_i, route_i, config_shift_o, route_o);
+ wire _0_;
+ wire _1_;
+ wire [1:0] _2_;
+ input config_clk_i;
+ wire config_clk_i;
+ wire [1:0] config_data;
+ input config_ena_i;
+ wire config_ena_i;
+ input config_shift_i;
+ wire config_shift_i;
+ output config_shift_o;
+ wire config_shift_o;
+ input [3:0] route_i;
+ wire [3:0] route_i;
+ output route_o;
+ wire route_o;
+ fpga_cfg_shiftreg_2 config_register (
+ .config_clk_i(config_clk_i),
+ .config_ena_i(config_ena_i),
+ .config_o(_2_),
+ .config_shift_i(config_shift_i),
+ .config_shift_o(_1_)
+ );
+ fpga_routing_mux_4_2_18446744073709551615 mux (
+ .config_i(config_data),
+ .route_i(route_i),
+ .route_o(_0_)
+ );
+ assign config_data = _2_;
+ assign config_shift_o = _1_;
+ assign route_o = _0_;
+endmodule
+
+module fpga_routing_node(config_data_i, route_i, route_o);
+ wire _000_;
+ wire _001_;
+ wire _002_;
+ wire _003_;
+ wire _004_;
+ wire _005_;
+ wire _006_;
+ wire _007_;
+ wire _008_;
+ wire _009_;
+ wire _010_;
+ wire _011_;
+ wire _012_;
+ wire _013_;
+ wire _014_;
+ wire _015_;
+ wire _016_;
+ wire _017_;
+ wire _018_;
+ wire _019_;
+ wire _020_;
+ wire _021_;
+ wire _022_;
+ wire _023_;
+ wire _024_;
+ wire _025_;
+ wire _026_;
+ wire _027_;
+ wire _028_;
+ wire _029_;
+ wire _030_;
+ wire _031_;
+ wire _032_;
+ wire _033_;
+ wire _034_;
+ wire _035_;
+ wire _036_;
+ wire _037_;
+ wire _038_;
+ wire _039_;
+ wire _040_;
+ wire _041_;
+ wire _042_;
+ wire _043_;
+ wire _044_;
+ wire _045_;
+ wire _046_;
+ wire _047_;
+ wire _048_;
+ wire _049_;
+ wire _050_;
+ wire _051_;
+ wire _052_;
+ wire _053_;
+ wire _054_;
+ wire _055_;
+ wire _056_;
+ wire _057_;
+ wire _058_;
+ wire _059_;
+ wire _060_;
+ wire _061_;
+ wire _062_;
+ wire _063_;
+ wire _064_;
+ wire _065_;
+ wire _066_;
+ wire _067_;
+ wire _068_;
+ wire _069_;
+ wire _070_;
+ wire _071_;
+ wire _072_;
+ wire _073_;
+ wire _074_;
+ wire _075_;
+ wire _076_;
+ wire _077_;
+ wire _078_;
+ wire _079_;
+ wire _080_;
+ wire _081_;
+ wire _082_;
+ wire _083_;
+ wire _084_;
+ wire _085_;
+ wire _086_;
+ wire _087_;
+ wire _088_;
+ wire _089_;
+ wire _090_;
+ wire _091_;
+ wire _092_;
+ wire _093_;
+ wire _094_;
+ wire _095_;
+ wire _096_;
+ wire _097_;
+ wire _098_;
+ wire _099_;
+ wire _100_;
+ wire _101_;
+ wire _102_;
+ wire _103_;
+ wire _104_;
+ wire _105_;
+ wire _106_;
+ wire _107_;
+ wire _108_;
+ wire _109_;
+ wire _110_;
+ wire _111_;
+ wire _112_;
+ wire _113_;
+ wire _114_;
+ wire _115_;
+ wire _116_;
+ wire _117_;
+ wire _118_;
+ wire _119_;
+ wire _120_;
+ wire _121_;
+ wire _122_;
+ wire _123_;
+ wire _124_;
+ wire _125_;
+ wire _126_;
+ wire _127_;
+ wire _128_;
+ wire _129_;
+ wire _130_;
+ wire _131_;
+ wire _132_;
+ wire _133_;
+ wire _134_;
+ wire _135_;
+ wire _136_;
+ wire _137_;
+ wire _138_;
+ wire _139_;
+ wire _140_;
+ wire _141_;
+ wire _142_;
+ wire _143_;
+ wire _144_;
+ wire _145_;
+ wire _146_;
+ wire _147_;
+ wire _148_;
+ wire _149_;
+ wire _150_;
+ wire _151_;
+ wire _152_;
+ wire _153_;
+ wire _154_;
+ wire _155_;
+ wire _156_;
+ wire _157_;
+ wire _158_;
+ wire _159_;
+ wire _160_;
+ wire _161_;
+ wire _162_;
+ wire _163_;
+ wire _164_;
+ wire _165_;
+ wire _166_;
+ wire _167_;
+ wire _168_;
+ wire _169_;
+ wire _170_;
+ wire _171_;
+ wire _172_;
+ wire _173_;
+ wire _174_;
+ wire _175_;
+ wire [111:0] buffered_in;
+ wire [15:0] buffered_out0;
+ wire [15:0] buffered_out1;
+ input [47:0] config_data_i;
+ wire [47:0] config_data_i;
+ input [111:0] route_i;
+ wire [111:0] route_i;
+ wire [15:0] route_int;
+ output [15:0] route_o;
+ wire [15:0] route_o;
+ fpga_tech_buffer \muxes:1.bufs:1.rnode_in (
+ .i(route_i[105]),
+ .z(_000_)
+ );
+ fpga_tech_buffer \muxes:1.bufs:2.rnode_in (
+ .i(route_i[106]),
+ .z(_001_)
+ );
+ fpga_tech_buffer \muxes:1.bufs:3.rnode_in (
+ .i(route_i[107]),
+ .z(_002_)
+ );
+ fpga_tech_buffer \muxes:1.bufs:4.rnode_in (
+ .i(route_i[108]),
+ .z(_003_)
+ );
+ fpga_tech_buffer \muxes:1.bufs:5.rnode_in (
+ .i(route_i[109]),
+ .z(_004_)
+ );
+ fpga_tech_buffer \muxes:1.bufs:6.rnode_in (
+ .i(route_i[110]),
+ .z(_005_)
+ );
+ fpga_tech_buffer \muxes:1.bufs:7.rnode_in (
+ .i(route_i[111]),
+ .z(_006_)
+ );
+ fpga_tech_buffer \muxes:1.loop_breaker (
+ .i(buffered_out0[0]),
+ .z(_009_)
+ );
+ fpga_tech_buffer \muxes:1.rnode_tfinish (
+ .i(route_int[0]),
+ .z(_008_)
+ );
+ fpga_tech_buffer \muxes:1.rnode_tstart (
+ .i(buffered_out1[0]),
+ .z(_010_)
+ );
+ fpga_routing_mux_7_3_7 \muxes:1.routing_node_track (
+ .config_i(config_data_i[2:0]),
+ .route_i(buffered_in[111:105]),
+ .route_o(_007_)
+ );
+ fpga_tech_buffer \muxes:10.bufs:1.rnode_in (
+ .i(route_i[42]),
+ .z(_099_)
+ );
+ fpga_tech_buffer \muxes:10.bufs:2.rnode_in (
+ .i(route_i[43]),
+ .z(_100_)
+ );
+ fpga_tech_buffer \muxes:10.bufs:3.rnode_in (
+ .i(route_i[44]),
+ .z(_101_)
+ );
+ fpga_tech_buffer \muxes:10.bufs:4.rnode_in (
+ .i(route_i[45]),
+ .z(_102_)
+ );
+ fpga_tech_buffer \muxes:10.bufs:5.rnode_in (
+ .i(route_i[46]),
+ .z(_103_)
+ );
+ fpga_tech_buffer \muxes:10.bufs:6.rnode_in (
+ .i(route_i[47]),
+ .z(_104_)
+ );
+ fpga_tech_buffer \muxes:10.bufs:7.rnode_in (
+ .i(route_i[48]),
+ .z(_105_)
+ );
+ fpga_tech_buffer \muxes:10.loop_breaker (
+ .i(buffered_out0[9]),
+ .z(_108_)
+ );
+ fpga_tech_buffer \muxes:10.rnode_tfinish (
+ .i(route_int[9]),
+ .z(_107_)
+ );
+ fpga_tech_buffer \muxes:10.rnode_tstart (
+ .i(buffered_out1[9]),
+ .z(_109_)
+ );
+ fpga_routing_mux_7_3_7 \muxes:10.routing_node_track (
+ .config_i(config_data_i[29:27]),
+ .route_i(buffered_in[48:42]),
+ .route_o(_106_)
+ );
+ fpga_tech_buffer \muxes:11.bufs:1.rnode_in (
+ .i(route_i[35]),
+ .z(_110_)
+ );
+ fpga_tech_buffer \muxes:11.bufs:2.rnode_in (
+ .i(route_i[36]),
+ .z(_111_)
+ );
+ fpga_tech_buffer \muxes:11.bufs:3.rnode_in (
+ .i(route_i[37]),
+ .z(_112_)
+ );
+ fpga_tech_buffer \muxes:11.bufs:4.rnode_in (
+ .i(route_i[38]),
+ .z(_113_)
+ );
+ fpga_tech_buffer \muxes:11.bufs:5.rnode_in (
+ .i(route_i[39]),
+ .z(_114_)
+ );
+ fpga_tech_buffer \muxes:11.bufs:6.rnode_in (
+ .i(route_i[40]),
+ .z(_115_)
+ );
+ fpga_tech_buffer \muxes:11.bufs:7.rnode_in (
+ .i(route_i[41]),
+ .z(_116_)
+ );
+ fpga_tech_buffer \muxes:11.loop_breaker (
+ .i(buffered_out0[10]),
+ .z(_119_)
+ );
+ fpga_tech_buffer \muxes:11.rnode_tfinish (
+ .i(route_int[10]),
+ .z(_118_)
+ );
+ fpga_tech_buffer \muxes:11.rnode_tstart (
+ .i(buffered_out1[10]),
+ .z(_120_)
+ );
+ fpga_routing_mux_7_3_7 \muxes:11.routing_node_track (
+ .config_i(config_data_i[32:30]),
+ .route_i(buffered_in[41:35]),
+ .route_o(_117_)
+ );
+ fpga_tech_buffer \muxes:12.bufs:1.rnode_in (
+ .i(route_i[28]),
+ .z(_121_)
+ );
+ fpga_tech_buffer \muxes:12.bufs:2.rnode_in (
+ .i(route_i[29]),
+ .z(_122_)
+ );
+ fpga_tech_buffer \muxes:12.bufs:3.rnode_in (
+ .i(route_i[30]),
+ .z(_123_)
+ );
+ fpga_tech_buffer \muxes:12.bufs:4.rnode_in (
+ .i(route_i[31]),
+ .z(_124_)
+ );
+ fpga_tech_buffer \muxes:12.bufs:5.rnode_in (
+ .i(route_i[32]),
+ .z(_125_)
+ );
+ fpga_tech_buffer \muxes:12.bufs:6.rnode_in (
+ .i(route_i[33]),
+ .z(_126_)
+ );
+ fpga_tech_buffer \muxes:12.bufs:7.rnode_in (
+ .i(route_i[34]),
+ .z(_127_)
+ );
+ fpga_tech_buffer \muxes:12.loop_breaker (
+ .i(buffered_out0[11]),
+ .z(_130_)
+ );
+ fpga_tech_buffer \muxes:12.rnode_tfinish (
+ .i(route_int[11]),
+ .z(_129_)
+ );
+ fpga_tech_buffer \muxes:12.rnode_tstart (
+ .i(buffered_out1[11]),
+ .z(_131_)
+ );
+ fpga_routing_mux_7_3_7 \muxes:12.routing_node_track (
+ .config_i(config_data_i[35:33]),
+ .route_i(buffered_in[34:28]),
+ .route_o(_128_)
+ );
+ fpga_tech_buffer \muxes:13.bufs:1.rnode_in (
+ .i(route_i[21]),
+ .z(_132_)
+ );
+ fpga_tech_buffer \muxes:13.bufs:2.rnode_in (
+ .i(route_i[22]),
+ .z(_133_)
+ );
+ fpga_tech_buffer \muxes:13.bufs:3.rnode_in (
+ .i(route_i[23]),
+ .z(_134_)
+ );
+ fpga_tech_buffer \muxes:13.bufs:4.rnode_in (
+ .i(route_i[24]),
+ .z(_135_)
+ );
+ fpga_tech_buffer \muxes:13.bufs:5.rnode_in (
+ .i(route_i[25]),
+ .z(_136_)
+ );
+ fpga_tech_buffer \muxes:13.bufs:6.rnode_in (
+ .i(route_i[26]),
+ .z(_137_)
+ );
+ fpga_tech_buffer \muxes:13.bufs:7.rnode_in (
+ .i(route_i[27]),
+ .z(_138_)
+ );
+ fpga_tech_buffer \muxes:13.loop_breaker (
+ .i(buffered_out0[12]),
+ .z(_141_)
+ );
+ fpga_tech_buffer \muxes:13.rnode_tfinish (
+ .i(route_int[12]),
+ .z(_140_)
+ );
+ fpga_tech_buffer \muxes:13.rnode_tstart (
+ .i(buffered_out1[12]),
+ .z(_142_)
+ );
+ fpga_routing_mux_7_3_7 \muxes:13.routing_node_track (
+ .config_i(config_data_i[38:36]),
+ .route_i(buffered_in[27:21]),
+ .route_o(_139_)
+ );
+ fpga_tech_buffer \muxes:14.bufs:1.rnode_in (
+ .i(route_i[14]),
+ .z(_143_)
+ );
+ fpga_tech_buffer \muxes:14.bufs:2.rnode_in (
+ .i(route_i[15]),
+ .z(_144_)
+ );
+ fpga_tech_buffer \muxes:14.bufs:3.rnode_in (
+ .i(route_i[16]),
+ .z(_145_)
+ );
+ fpga_tech_buffer \muxes:14.bufs:4.rnode_in (
+ .i(route_i[17]),
+ .z(_146_)
+ );
+ fpga_tech_buffer \muxes:14.bufs:5.rnode_in (
+ .i(route_i[18]),
+ .z(_147_)
+ );
+ fpga_tech_buffer \muxes:14.bufs:6.rnode_in (
+ .i(route_i[19]),
+ .z(_148_)
+ );
+ fpga_tech_buffer \muxes:14.bufs:7.rnode_in (
+ .i(route_i[20]),
+ .z(_149_)
+ );
+ fpga_tech_buffer \muxes:14.loop_breaker (
+ .i(buffered_out0[13]),
+ .z(_152_)
+ );
+ fpga_tech_buffer \muxes:14.rnode_tfinish (
+ .i(route_int[13]),
+ .z(_151_)
+ );
+ fpga_tech_buffer \muxes:14.rnode_tstart (
+ .i(buffered_out1[13]),
+ .z(_153_)
+ );
+ fpga_routing_mux_7_3_7 \muxes:14.routing_node_track (
+ .config_i(config_data_i[41:39]),
+ .route_i(buffered_in[20:14]),
+ .route_o(_150_)
+ );
+ fpga_tech_buffer \muxes:15.bufs:1.rnode_in (
+ .i(route_i[7]),
+ .z(_154_)
+ );
+ fpga_tech_buffer \muxes:15.bufs:2.rnode_in (
+ .i(route_i[8]),
+ .z(_155_)
+ );
+ fpga_tech_buffer \muxes:15.bufs:3.rnode_in (
+ .i(route_i[9]),
+ .z(_156_)
+ );
+ fpga_tech_buffer \muxes:15.bufs:4.rnode_in (
+ .i(route_i[10]),
+ .z(_157_)
+ );
+ fpga_tech_buffer \muxes:15.bufs:5.rnode_in (
+ .i(route_i[11]),
+ .z(_158_)
+ );
+ fpga_tech_buffer \muxes:15.bufs:6.rnode_in (
+ .i(route_i[12]),
+ .z(_159_)
+ );
+ fpga_tech_buffer \muxes:15.bufs:7.rnode_in (
+ .i(route_i[13]),
+ .z(_160_)
+ );
+ fpga_tech_buffer \muxes:15.loop_breaker (
+ .i(buffered_out0[14]),
+ .z(_163_)
+ );
+ fpga_tech_buffer \muxes:15.rnode_tfinish (
+ .i(route_int[14]),
+ .z(_162_)
+ );
+ fpga_tech_buffer \muxes:15.rnode_tstart (
+ .i(buffered_out1[14]),
+ .z(_164_)
+ );
+ fpga_routing_mux_7_3_7 \muxes:15.routing_node_track (
+ .config_i(config_data_i[44:42]),
+ .route_i(buffered_in[13:7]),
+ .route_o(_161_)
+ );
+ fpga_tech_buffer \muxes:16.bufs:1.rnode_in (
+ .i(route_i[0]),
+ .z(_165_)
+ );
+ fpga_tech_buffer \muxes:16.bufs:2.rnode_in (
+ .i(route_i[1]),
+ .z(_166_)
+ );
+ fpga_tech_buffer \muxes:16.bufs:3.rnode_in (
+ .i(route_i[2]),
+ .z(_167_)
+ );
+ fpga_tech_buffer \muxes:16.bufs:4.rnode_in (
+ .i(route_i[3]),
+ .z(_168_)
+ );
+ fpga_tech_buffer \muxes:16.bufs:5.rnode_in (
+ .i(route_i[4]),
+ .z(_169_)
+ );
+ fpga_tech_buffer \muxes:16.bufs:6.rnode_in (
+ .i(route_i[5]),
+ .z(_170_)
+ );
+ fpga_tech_buffer \muxes:16.bufs:7.rnode_in (
+ .i(route_i[6]),
+ .z(_171_)
+ );
+ fpga_tech_buffer \muxes:16.loop_breaker (
+ .i(buffered_out0[15]),
+ .z(_174_)
+ );
+ fpga_tech_buffer \muxes:16.rnode_tfinish (
+ .i(route_int[15]),
+ .z(_173_)
+ );
+ fpga_tech_buffer \muxes:16.rnode_tstart (
+ .i(buffered_out1[15]),
+ .z(_175_)
+ );
+ fpga_routing_mux_7_3_7 \muxes:16.routing_node_track (
+ .config_i(config_data_i[47:45]),
+ .route_i(buffered_in[6:0]),
+ .route_o(_172_)
+ );
+ fpga_tech_buffer \muxes:2.bufs:1.rnode_in (
+ .i(route_i[98]),
+ .z(_011_)
+ );
+ fpga_tech_buffer \muxes:2.bufs:2.rnode_in (
+ .i(route_i[99]),
+ .z(_012_)
+ );
+ fpga_tech_buffer \muxes:2.bufs:3.rnode_in (
+ .i(route_i[100]),
+ .z(_013_)
+ );
+ fpga_tech_buffer \muxes:2.bufs:4.rnode_in (
+ .i(route_i[101]),
+ .z(_014_)
+ );
+ fpga_tech_buffer \muxes:2.bufs:5.rnode_in (
+ .i(route_i[102]),
+ .z(_015_)
+ );
+ fpga_tech_buffer \muxes:2.bufs:6.rnode_in (
+ .i(route_i[103]),
+ .z(_016_)
+ );
+ fpga_tech_buffer \muxes:2.bufs:7.rnode_in (
+ .i(route_i[104]),
+ .z(_017_)
+ );
+ fpga_tech_buffer \muxes:2.loop_breaker (
+ .i(buffered_out0[1]),
+ .z(_020_)
+ );
+ fpga_tech_buffer \muxes:2.rnode_tfinish (
+ .i(route_int[1]),
+ .z(_019_)
+ );
+ fpga_tech_buffer \muxes:2.rnode_tstart (
+ .i(buffered_out1[1]),
+ .z(_021_)
+ );
+ fpga_routing_mux_7_3_7 \muxes:2.routing_node_track (
+ .config_i(config_data_i[5:3]),
+ .route_i(buffered_in[104:98]),
+ .route_o(_018_)
+ );
+ fpga_tech_buffer \muxes:3.bufs:1.rnode_in (
+ .i(route_i[91]),
+ .z(_022_)
+ );
+ fpga_tech_buffer \muxes:3.bufs:2.rnode_in (
+ .i(route_i[92]),
+ .z(_023_)
+ );
+ fpga_tech_buffer \muxes:3.bufs:3.rnode_in (
+ .i(route_i[93]),
+ .z(_024_)
+ );
+ fpga_tech_buffer \muxes:3.bufs:4.rnode_in (
+ .i(route_i[94]),
+ .z(_025_)
+ );
+ fpga_tech_buffer \muxes:3.bufs:5.rnode_in (
+ .i(route_i[95]),
+ .z(_026_)
+ );
+ fpga_tech_buffer \muxes:3.bufs:6.rnode_in (
+ .i(route_i[96]),
+ .z(_027_)
+ );
+ fpga_tech_buffer \muxes:3.bufs:7.rnode_in (
+ .i(route_i[97]),
+ .z(_028_)
+ );
+ fpga_tech_buffer \muxes:3.loop_breaker (
+ .i(buffered_out0[2]),
+ .z(_031_)
+ );
+ fpga_tech_buffer \muxes:3.rnode_tfinish (
+ .i(route_int[2]),
+ .z(_030_)
+ );
+ fpga_tech_buffer \muxes:3.rnode_tstart (
+ .i(buffered_out1[2]),
+ .z(_032_)
+ );
+ fpga_routing_mux_7_3_7 \muxes:3.routing_node_track (
+ .config_i(config_data_i[8:6]),
+ .route_i(buffered_in[97:91]),
+ .route_o(_029_)
+ );
+ fpga_tech_buffer \muxes:4.bufs:1.rnode_in (
+ .i(route_i[84]),
+ .z(_033_)
+ );
+ fpga_tech_buffer \muxes:4.bufs:2.rnode_in (
+ .i(route_i[85]),
+ .z(_034_)
+ );
+ fpga_tech_buffer \muxes:4.bufs:3.rnode_in (
+ .i(route_i[86]),
+ .z(_035_)
+ );
+ fpga_tech_buffer \muxes:4.bufs:4.rnode_in (
+ .i(route_i[87]),
+ .z(_036_)
+ );
+ fpga_tech_buffer \muxes:4.bufs:5.rnode_in (
+ .i(route_i[88]),
+ .z(_037_)
+ );
+ fpga_tech_buffer \muxes:4.bufs:6.rnode_in (
+ .i(route_i[89]),
+ .z(_038_)
+ );
+ fpga_tech_buffer \muxes:4.bufs:7.rnode_in (
+ .i(route_i[90]),
+ .z(_039_)
+ );
+ fpga_tech_buffer \muxes:4.loop_breaker (
+ .i(buffered_out0[3]),
+ .z(_042_)
+ );
+ fpga_tech_buffer \muxes:4.rnode_tfinish (
+ .i(route_int[3]),
+ .z(_041_)
+ );
+ fpga_tech_buffer \muxes:4.rnode_tstart (
+ .i(buffered_out1[3]),
+ .z(_043_)
+ );
+ fpga_routing_mux_7_3_7 \muxes:4.routing_node_track (
+ .config_i(config_data_i[11:9]),
+ .route_i(buffered_in[90:84]),
+ .route_o(_040_)
+ );
+ fpga_tech_buffer \muxes:5.bufs:1.rnode_in (
+ .i(route_i[77]),
+ .z(_044_)
+ );
+ fpga_tech_buffer \muxes:5.bufs:2.rnode_in (
+ .i(route_i[78]),
+ .z(_045_)
+ );
+ fpga_tech_buffer \muxes:5.bufs:3.rnode_in (
+ .i(route_i[79]),
+ .z(_046_)
+ );
+ fpga_tech_buffer \muxes:5.bufs:4.rnode_in (
+ .i(route_i[80]),
+ .z(_047_)
+ );
+ fpga_tech_buffer \muxes:5.bufs:5.rnode_in (
+ .i(route_i[81]),
+ .z(_048_)
+ );
+ fpga_tech_buffer \muxes:5.bufs:6.rnode_in (
+ .i(route_i[82]),
+ .z(_049_)
+ );
+ fpga_tech_buffer \muxes:5.bufs:7.rnode_in (
+ .i(route_i[83]),
+ .z(_050_)
+ );
+ fpga_tech_buffer \muxes:5.loop_breaker (
+ .i(buffered_out0[4]),
+ .z(_053_)
+ );
+ fpga_tech_buffer \muxes:5.rnode_tfinish (
+ .i(route_int[4]),
+ .z(_052_)
+ );
+ fpga_tech_buffer \muxes:5.rnode_tstart (
+ .i(buffered_out1[4]),
+ .z(_054_)
+ );
+ fpga_routing_mux_7_3_7 \muxes:5.routing_node_track (
+ .config_i(config_data_i[14:12]),
+ .route_i(buffered_in[83:77]),
+ .route_o(_051_)
+ );
+ fpga_tech_buffer \muxes:6.bufs:1.rnode_in (
+ .i(route_i[70]),
+ .z(_055_)
+ );
+ fpga_tech_buffer \muxes:6.bufs:2.rnode_in (
+ .i(route_i[71]),
+ .z(_056_)
+ );
+ fpga_tech_buffer \muxes:6.bufs:3.rnode_in (
+ .i(route_i[72]),
+ .z(_057_)
+ );
+ fpga_tech_buffer \muxes:6.bufs:4.rnode_in (
+ .i(route_i[73]),
+ .z(_058_)
+ );
+ fpga_tech_buffer \muxes:6.bufs:5.rnode_in (
+ .i(route_i[74]),
+ .z(_059_)
+ );
+ fpga_tech_buffer \muxes:6.bufs:6.rnode_in (
+ .i(route_i[75]),
+ .z(_060_)
+ );
+ fpga_tech_buffer \muxes:6.bufs:7.rnode_in (
+ .i(route_i[76]),
+ .z(_061_)
+ );
+ fpga_tech_buffer \muxes:6.loop_breaker (
+ .i(buffered_out0[5]),
+ .z(_064_)
+ );
+ fpga_tech_buffer \muxes:6.rnode_tfinish (
+ .i(route_int[5]),
+ .z(_063_)
+ );
+ fpga_tech_buffer \muxes:6.rnode_tstart (
+ .i(buffered_out1[5]),
+ .z(_065_)
+ );
+ fpga_routing_mux_7_3_7 \muxes:6.routing_node_track (
+ .config_i(config_data_i[17:15]),
+ .route_i(buffered_in[76:70]),
+ .route_o(_062_)
+ );
+ fpga_tech_buffer \muxes:7.bufs:1.rnode_in (
+ .i(route_i[63]),
+ .z(_066_)
+ );
+ fpga_tech_buffer \muxes:7.bufs:2.rnode_in (
+ .i(route_i[64]),
+ .z(_067_)
+ );
+ fpga_tech_buffer \muxes:7.bufs:3.rnode_in (
+ .i(route_i[65]),
+ .z(_068_)
+ );
+ fpga_tech_buffer \muxes:7.bufs:4.rnode_in (
+ .i(route_i[66]),
+ .z(_069_)
+ );
+ fpga_tech_buffer \muxes:7.bufs:5.rnode_in (
+ .i(route_i[67]),
+ .z(_070_)
+ );
+ fpga_tech_buffer \muxes:7.bufs:6.rnode_in (
+ .i(route_i[68]),
+ .z(_071_)
+ );
+ fpga_tech_buffer \muxes:7.bufs:7.rnode_in (
+ .i(route_i[69]),
+ .z(_072_)
+ );
+ fpga_tech_buffer \muxes:7.loop_breaker (
+ .i(buffered_out0[6]),
+ .z(_075_)
+ );
+ fpga_tech_buffer \muxes:7.rnode_tfinish (
+ .i(route_int[6]),
+ .z(_074_)
+ );
+ fpga_tech_buffer \muxes:7.rnode_tstart (
+ .i(buffered_out1[6]),
+ .z(_076_)
+ );
+ fpga_routing_mux_7_3_7 \muxes:7.routing_node_track (
+ .config_i(config_data_i[20:18]),
+ .route_i(buffered_in[69:63]),
+ .route_o(_073_)
+ );
+ fpga_tech_buffer \muxes:8.bufs:1.rnode_in (
+ .i(route_i[56]),
+ .z(_077_)
+ );
+ fpga_tech_buffer \muxes:8.bufs:2.rnode_in (
+ .i(route_i[57]),
+ .z(_078_)
+ );
+ fpga_tech_buffer \muxes:8.bufs:3.rnode_in (
+ .i(route_i[58]),
+ .z(_079_)
+ );
+ fpga_tech_buffer \muxes:8.bufs:4.rnode_in (
+ .i(route_i[59]),
+ .z(_080_)
+ );
+ fpga_tech_buffer \muxes:8.bufs:5.rnode_in (
+ .i(route_i[60]),
+ .z(_081_)
+ );
+ fpga_tech_buffer \muxes:8.bufs:6.rnode_in (
+ .i(route_i[61]),
+ .z(_082_)
+ );
+ fpga_tech_buffer \muxes:8.bufs:7.rnode_in (
+ .i(route_i[62]),
+ .z(_083_)
+ );
+ fpga_tech_buffer \muxes:8.loop_breaker (
+ .i(buffered_out0[7]),
+ .z(_086_)
+ );
+ fpga_tech_buffer \muxes:8.rnode_tfinish (
+ .i(route_int[7]),
+ .z(_085_)
+ );
+ fpga_tech_buffer \muxes:8.rnode_tstart (
+ .i(buffered_out1[7]),
+ .z(_087_)
+ );
+ fpga_routing_mux_7_3_7 \muxes:8.routing_node_track (
+ .config_i(config_data_i[23:21]),
+ .route_i(buffered_in[62:56]),
+ .route_o(_084_)
+ );
+ fpga_tech_buffer \muxes:9.bufs:1.rnode_in (
+ .i(route_i[49]),
+ .z(_088_)
+ );
+ fpga_tech_buffer \muxes:9.bufs:2.rnode_in (
+ .i(route_i[50]),
+ .z(_089_)
+ );
+ fpga_tech_buffer \muxes:9.bufs:3.rnode_in (
+ .i(route_i[51]),
+ .z(_090_)
+ );
+ fpga_tech_buffer \muxes:9.bufs:4.rnode_in (
+ .i(route_i[52]),
+ .z(_091_)
+ );
+ fpga_tech_buffer \muxes:9.bufs:5.rnode_in (
+ .i(route_i[53]),
+ .z(_092_)
+ );
+ fpga_tech_buffer \muxes:9.bufs:6.rnode_in (
+ .i(route_i[54]),
+ .z(_093_)
+ );
+ fpga_tech_buffer \muxes:9.bufs:7.rnode_in (
+ .i(route_i[55]),
+ .z(_094_)
+ );
+ fpga_tech_buffer \muxes:9.loop_breaker (
+ .i(buffered_out0[8]),
+ .z(_097_)
+ );
+ fpga_tech_buffer \muxes:9.rnode_tfinish (
+ .i(route_int[8]),
+ .z(_096_)
+ );
+ fpga_tech_buffer \muxes:9.rnode_tstart (
+ .i(buffered_out1[8]),
+ .z(_098_)
+ );
+ fpga_routing_mux_7_3_7 \muxes:9.routing_node_track (
+ .config_i(config_data_i[26:24]),
+ .route_i(buffered_in[55:49]),
+ .route_o(_095_)
+ );
+ assign route_int = { _172_, _161_, _150_, _139_, _128_, _117_, _106_, _095_, _084_, _073_, _062_, _051_, _040_, _029_, _018_, _007_ };
+ assign buffered_in = { _006_, _005_, _004_, _003_, _002_, _001_, _000_, _017_, _016_, _015_, _014_, _013_, _012_, _011_, _028_, _027_, _026_, _025_, _024_, _023_, _022_, _039_, _038_, _037_, _036_, _035_, _034_, _033_, _050_, _049_, _048_, _047_, _046_, _045_, _044_, _061_, _060_, _059_, _058_, _057_, _056_, _055_, _072_, _071_, _070_, _069_, _068_, _067_, _066_, _083_, _082_, _081_, _080_, _079_, _078_, _077_, _094_, _093_, _092_, _091_, _090_, _089_, _088_, _105_, _104_, _103_, _102_, _101_, _100_, _099_, _116_, _115_, _114_, _113_, _112_, _111_, _110_, _127_, _126_, _125_, _124_, _123_, _122_, _121_, _138_, _137_, _136_, _135_, _134_, _133_, _132_, _149_, _148_, _147_, _146_, _145_, _144_, _143_, _160_, _159_, _158_, _157_, _156_, _155_, _154_, _171_, _170_, _169_, _168_, _167_, _166_, _165_ };
+ assign buffered_out0 = { _173_, _162_, _151_, _140_, _129_, _118_, _107_, _096_, _085_, _074_, _063_, _052_, _041_, _030_, _019_, _008_ };
+ assign buffered_out1 = { _174_, _163_, _152_, _141_, _130_, _119_, _108_, _097_, _086_, _075_, _064_, _053_, _042_, _031_, _020_, _009_ };
+ assign route_o = { _175_, _164_, _153_, _142_, _131_, _120_, _109_, _098_, _087_, _076_, _065_, _054_, _043_, _032_, _021_, _010_ };
+endmodule
+
+module fpga_routing_node_wcfg(config_clk_i, config_ena_i, config_shift_i, route_i, config_shift_o, route_o);
+ wire [15:0] _0_;
+ wire _1_;
+ wire [47:0] _2_;
+ input config_clk_i;
+ wire config_clk_i;
+ wire [47:0] config_data;
+ wire [47:0] config_data_gated;
+ input config_ena_i;
+ wire config_ena_i;
+ input config_shift_i;
+ wire config_shift_i;
+ output config_shift_o;
+ wire config_shift_o;
+ wire [15:0] \node:49485 ;
+ input [111:0] route_i;
+ wire [111:0] route_i;
+ output [15:0] route_o;
+ wire [15:0] route_o;
+ fpga_cfg_shiftreg_48 config_register (
+ .config_clk_i(config_clk_i),
+ .config_ena_i(config_ena_i),
+ .config_o(_2_),
+ .config_shift_i(config_shift_i),
+ .config_shift_o(_1_)
+ );
+ fpga_routing_node node (
+ .config_data_i(config_data_gated),
+ .route_i(route_i),
+ .route_o(_0_)
+ );
+ assign config_data = _2_;
+ assign config_data_gated = config_data;
+ assign \node:49485 = _0_;
+ assign config_shift_o = _1_;
+ assign route_o = \node:49485 ;
+endmodule
+
+module wb_arbiter_sync_6(wb_clk_i, wb_rst_i, \wb_i_up.stb_i , \wb_i_up.cyc_i , \wb_i_up.we_i , \wb_i_up.dat_i , \wb_i_up.adr_i , addr_map, wb_i_bottom, \wb_o_up.ack_o , \wb_o_up.dat_o , wb_o_bottom);
+ wire [32:0] _00_;
+ wire [32:0] _01_;
+ wire [32:0] _02_;
+ wire [32:0] _03_;
+ wire [66:0] _04_;
+ wire [66:0] _05_;
+ wire [66:0] _06_;
+ wire [66:0] _07_;
+ wire [32:0] _08_;
+ wire [32:0] _09_;
+ wire [32:0] _10_;
+ wire _11_;
+ wire _12_;
+ wire _13_;
+ wire _14_;
+ wire [2:0] _15_;
+ wire _16_;
+ wire [2:0] _17_;
+ wire _18_;
+ wire [2:0] _19_;
+ wire _20_;
+ wire [2:0] _21_;
+ wire _22_;
+ wire [2:0] _23_;
+ wire _24_;
+ wire [2:0] _25_;
+ wire [401:0] _26_;
+ wire _27_;
+ wire [2:0] _28_;
+ wire _29_;
+ wire [32:0] _30_;
+ wire [401:0] _31_;
+ wire _32_;
+ wire _33_;
+ wire [32:0] _34_;
+ wire [401:0] _35_;
+ wire _36_;
+ wire [2:0] _37_;
+ wire _38_;
+ wire [2:0] _39_;
+ reg [2:0] _40_ = 3'h0;
+ reg _41_;
+ reg [32:0] _42_;
+ reg [401:0] _43_;
+ wire _44_;
+ wire _45_;
+ wire _46_;
+ wire _47_;
+ wire _48_;
+ wire _49_;
+ wire _50_;
+ wire _51_;
+ wire _52_;
+ wire _53_;
+ wire _54_;
+ wire _55_;
+ wire [66:0] _56_;
+ wire [66:0] _57_;
+ wire [66:0] _58_;
+ wire [66:0] _59_;
+ wire [66:0] _60_;
+ wire [66:0] _61_;
+ wire [32:0] _62_;
+ wire [32:0] _63_;
+ wire [32:0] _64_;
+ wire _65_;
+ wire _66_;
+ wire _67_;
+ wire _68_;
+ wire _69_;
+ wire _70_;
+ wire _71_;
+ wire _72_;
+ wire _73_;
+ wire _74_;
+ wire _75_;
+ wire _76_;
+ wire [66:0] _77_;
+ wire [66:0] _78_;
+ input [191:0] addr_map;
+ wire [191:0] addr_map;
+ wire state;
+ wire [2:0] \sync.pn_buf ;
+ input wb_clk_i;
+ wire wb_clk_i;
+ input [197:0] wb_i_bottom;
+ wire [197:0] wb_i_bottom;
+ input [31:0] \wb_i_up.adr_i ;
+ wire [31:0] \wb_i_up.adr_i ;
+ input \wb_i_up.cyc_i ;
+ wire \wb_i_up.cyc_i ;
+ input [31:0] \wb_i_up.dat_i ;
+ wire [31:0] \wb_i_up.dat_i ;
+ input \wb_i_up.stb_i ;
+ wire \wb_i_up.stb_i ;
+ input \wb_i_up.we_i ;
+ wire \wb_i_up.we_i ;
+ output [401:0] wb_o_bottom;
+ wire [401:0] wb_o_bottom;
+ output \wb_o_up.ack_o ;
+ wire \wb_o_up.ack_o ;
+ output [31:0] \wb_o_up.dat_o ;
+ wire [31:0] \wb_o_up.dat_o ;
+ input wb_rst_i;
+ wire wb_rst_i;
+ assign _00_ = \sync.pn_buf [0] ? wb_i_bottom[65:33] : wb_i_bottom[32:0];
+ assign _01_ = \sync.pn_buf [0] ? wb_i_bottom[65:33] : wb_i_bottom[32:0];
+ assign _02_ = \sync.pn_buf [0] ? wb_i_bottom[131:99] : wb_i_bottom[98:66];
+ assign _03_ = \sync.pn_buf [0] ? wb_i_bottom[131:99] : wb_i_bottom[98:66];
+ assign _62_ = \sync.pn_buf [1] ? _02_ : _00_;
+ assign _08_ = \sync.pn_buf [1] ? _03_ : _01_;
+ assign _11_ = \wb_i_up.cyc_i & \wb_i_up.stb_i ;
+ assign _12_ = ~ _42_[0];
+ assign _13_ = _11_ & _12_;
+ assign _14_ = \wb_i_up.adr_i >= addr_map[31:0];
+ assign _15_ = _14_ ? 3'h0 : \sync.pn_buf ;
+ assign _16_ = \wb_i_up.adr_i >= addr_map[63:32];
+ assign _17_ = _16_ ? 3'h1 : _15_;
+ assign _18_ = \wb_i_up.adr_i >= addr_map[95:64];
+ assign _19_ = _18_ ? 3'h2 : _17_;
+ assign _20_ = \wb_i_up.adr_i >= addr_map[127:96];
+ assign _21_ = _20_ ? 3'h3 : _19_;
+ assign _22_ = \wb_i_up.adr_i >= addr_map[159:128];
+ assign _23_ = _22_ ? 3'h4 : _21_;
+ assign _24_ = \wb_i_up.adr_i >= addr_map[191:160];
+ assign _25_ = _24_ ? 3'h5 : _23_;
+ assign _26_ = _13_ ? { _61_, _60_, _59_, _58_, _57_, _56_ } : _43_;
+ assign _27_ = _13_ ? 1'h1 : state;
+ assign _28_ = _13_ ? _25_ : \sync.pn_buf ;
+ assign _29_ = state == 1'h0;
+ assign _30_ = _64_[0] ? { _10_[32:1], 1'h1 } : _42_;
+ assign _31_ = _64_[0] ? { _07_, _06_, _05_, _04_, _78_, _77_ } : _43_;
+ assign _32_ = _64_[0] ? 1'h0 : state;
+ assign _33_ = state == 1'h1;
+ function [32:0] \594 ;
+ input [32:0] a;
+ input [65:0] b;
+ input [1:0] s;
+ (* parallel_case *)
+ casez (s)
+ 2'b?1:
+ \594 = b[32:0];
+ 2'b1?:
+ \594 = b[65:33];
+ default:
+ \594 = a;
+ endcase
+ endfunction
+ assign _34_ = \594 (33'hxxxxxxxxx, { _30_, 33'h000000000 }, { _33_, _29_ });
+ function [401:0] \596 ;
+ input [401:0] a;
+ input [803:0] b;
+ input [1:0] s;
+ (* parallel_case *)
+ casez (s)
+ 2'b?1:
+ \596 = b[401:0];
+ 2'b1?:
+ \596 = b[803:402];
+ default:
+ \596 = a;
+ endcase
+ endfunction
+ assign _35_ = \596 (402'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx, { _31_, _26_ }, { _33_, _29_ });
+ function [0:0] \598 ;
+ input [0:0] a;
+ input [1:0] b;
+ input [1:0] s;
+ (* parallel_case *)
+ casez (s)
+ 2'b?1:
+ \598 = b[0:0];
+ 2'b1?:
+ \598 = b[1:1];
+ default:
+ \598 = a;
+ endcase
+ endfunction
+ assign _36_ = \598 (1'hx, { _32_, _27_ }, { _33_, _29_ });
+ function [2:0] \602 ;
+ input [2:0] a;
+ input [5:0] b;
+ input [1:0] s;
+ (* parallel_case *)
+ casez (s)
+ 2'b?1:
+ \602 = b[2:0];
+ 2'b1?:
+ \602 = b[5:3];
+ default:
+ \602 = a;
+ endcase
+ endfunction
+ assign _37_ = \602 (3'hx, { \sync.pn_buf , _28_ }, { _33_, _29_ });
+ assign _38_ = ~ wb_rst_i;
+ assign _39_ = _38_ ? _37_ : \sync.pn_buf ;
+ always @(posedge wb_clk_i)
+ _40_ <= _39_;
+ always @(posedge wb_clk_i, posedge wb_rst_i)
+ if (wb_rst_i) _41_ <= 1'h0;
+ else _41_ <= _36_;
+ always @(posedge wb_clk_i, posedge wb_rst_i)
+ if (wb_rst_i) _42_ <= 33'h000000000;
+ else _42_ <= _34_;
+ always @(posedge wb_clk_i, posedge wb_rst_i)
+ if (wb_rst_i) _43_ <= 402'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
+ else _43_ <= _35_;
+ assign _44_ = ~ _25_[2];
+ assign _45_ = ~ _25_[1];
+ assign _46_ = _44_ & _45_;
+ assign _47_ = _44_ & _25_[1];
+ assign _48_ = _25_[2] & _45_;
+ assign _49_ = ~ _25_[0];
+ assign _50_ = _46_ & _49_;
+ assign _51_ = _46_ & _25_[0];
+ assign _52_ = _47_ & _49_;
+ assign _53_ = _47_ & _25_[0];
+ assign _54_ = _48_ & _49_;
+ assign _55_ = _48_ & _25_[0];
+ assign _56_ = _50_ ? { \wb_i_up.adr_i , \wb_i_up.dat_i , \wb_i_up.we_i , \wb_i_up.cyc_i , \wb_i_up.stb_i } : _43_[66:0];
+ assign _57_ = _51_ ? { \wb_i_up.adr_i , \wb_i_up.dat_i , \wb_i_up.we_i , \wb_i_up.cyc_i , \wb_i_up.stb_i } : _43_[133:67];
+ assign _58_ = _52_ ? { \wb_i_up.adr_i , \wb_i_up.dat_i , \wb_i_up.we_i , \wb_i_up.cyc_i , \wb_i_up.stb_i } : _43_[200:134];
+ assign _59_ = _53_ ? { \wb_i_up.adr_i , \wb_i_up.dat_i , \wb_i_up.we_i , \wb_i_up.cyc_i , \wb_i_up.stb_i } : _43_[267:201];
+ assign _60_ = _54_ ? { \wb_i_up.adr_i , \wb_i_up.dat_i , \wb_i_up.we_i , \wb_i_up.cyc_i , \wb_i_up.stb_i } : _43_[334:268];
+ assign _61_ = _55_ ? { \wb_i_up.adr_i , \wb_i_up.dat_i , \wb_i_up.we_i , \wb_i_up.cyc_i , \wb_i_up.stb_i } : _43_[401:335];
+ assign _63_ = \sync.pn_buf [0] ? wb_i_bottom[197:165] : wb_i_bottom[164:132];
+ assign _64_ = \sync.pn_buf [2] ? _63_ : _62_;
+ assign _65_ = ~ \sync.pn_buf [2];
+ assign _66_ = ~ \sync.pn_buf [1];
+ assign _67_ = _65_ & _66_;
+ assign _68_ = _65_ & \sync.pn_buf [1];
+ assign _69_ = \sync.pn_buf [2] & _66_;
+ assign _70_ = ~ \sync.pn_buf [0];
+ assign _71_ = _67_ & _70_;
+ assign _72_ = _67_ & \sync.pn_buf [0];
+ assign _73_ = _68_ & _70_;
+ assign _74_ = _68_ & \sync.pn_buf [0];
+ assign _75_ = _69_ & _70_;
+ assign _76_ = _69_ & \sync.pn_buf [0];
+ assign _77_ = _71_ ? 67'h00000000000000000 : _43_[66:0];
+ assign _78_ = _72_ ? 67'h00000000000000000 : _43_[133:67];
+ assign _04_ = _73_ ? 67'h00000000000000000 : _43_[200:134];
+ assign _05_ = _74_ ? 67'h00000000000000000 : _43_[267:201];
+ assign _06_ = _75_ ? 67'h00000000000000000 : _43_[334:268];
+ assign _07_ = _76_ ? 67'h00000000000000000 : _43_[401:335];
+ assign _09_ = \sync.pn_buf [0] ? wb_i_bottom[197:165] : wb_i_bottom[164:132];
+ assign _10_ = \sync.pn_buf [2] ? _09_ : _08_;
+ assign state = _41_;
+ assign \sync.pn_buf = _40_;
+ assign \wb_o_up.ack_o = _42_[0];
+ assign \wb_o_up.dat_o = _42_[32:1];
+ assign wb_o_bottom = _43_;
+endmodule
+
+module wb_register32_14ace0e78520e59d309b4c0f3f681129bf7f2ebe(wb_clk_i, wb_rst_i, \wb_i.stb_i , \wb_i.cyc_i , \wb_i.we_i , \wb_i.dat_i , \wb_i.adr_i , reg_i, \wb_o.ack_o , \wb_o.dat_o , reg_o);
+ wire _0_;
+ wire _1_;
+ wire [31:0] _2_;
+ reg [31:0] _3_;
+ reg [32:0] _4_;
+ input [31:0] reg_i;
+ wire [31:0] reg_i;
+ output [31:0] reg_o;
+ wire [31:0] reg_o;
+ wire [31:0] reg_o_buf;
+ input wb_clk_i;
+ wire wb_clk_i;
+ input [31:0] \wb_i.adr_i ;
+ wire [31:0] \wb_i.adr_i ;
+ input \wb_i.cyc_i ;
+ wire \wb_i.cyc_i ;
+ input [31:0] \wb_i.dat_i ;
+ wire [31:0] \wb_i.dat_i ;
+ input \wb_i.stb_i ;
+ wire \wb_i.stb_i ;
+ input \wb_i.we_i ;
+ wire \wb_i.we_i ;
+ output \wb_o.ack_o ;
+ wire \wb_o.ack_o ;
+ output [31:0] \wb_o.dat_o ;
+ wire [31:0] \wb_o.dat_o ;
+ input wb_rst_i;
+ wire wb_rst_i;
+ assign _0_ = \wb_i.cyc_i & \wb_i.stb_i ;
+ assign _1_ = _0_ & \wb_i.we_i ;
+ assign _2_ = _1_ ? \wb_i.dat_i : reg_o_buf;
+ always @(posedge wb_clk_i, posedge wb_rst_i)
+ if (wb_rst_i) _3_ <= 32'd0;
+ else _3_ <= _2_;
+ always @(posedge wb_clk_i, posedge wb_rst_i)
+ if (wb_rst_i) _4_ <= 33'h000000000;
+ else _4_ <= { reg_i, 1'h1 };
+ assign reg_o_buf = _3_;
+ assign \wb_o.ack_o = _4_[0];
+ assign \wb_o.dat_o = _4_[32:1];
+ assign reg_o = reg_o_buf;
+endmodule
+
+module wb_register32_81b45b9a32734d4367912d54c45d3716474431dc(wb_clk_i, wb_rst_i, \wb_i.stb_i , \wb_i.cyc_i , \wb_i.we_i , \wb_i.dat_i , \wb_i.adr_i , reg_i, \wb_o.ack_o , \wb_o.dat_o , reg_o);
+ wire _0_;
+ wire _1_;
+ wire [31:0] _2_;
+ reg [31:0] _3_;
+ reg [32:0] _4_;
+ input [31:0] reg_i;
+ wire [31:0] reg_i;
+ output [31:0] reg_o;
+ wire [31:0] reg_o;
+ wire [31:0] reg_o_buf;
+ input wb_clk_i;
+ wire wb_clk_i;
+ input [31:0] \wb_i.adr_i ;
+ wire [31:0] \wb_i.adr_i ;
+ input \wb_i.cyc_i ;
+ wire \wb_i.cyc_i ;
+ input [31:0] \wb_i.dat_i ;
+ wire [31:0] \wb_i.dat_i ;
+ input \wb_i.stb_i ;
+ wire \wb_i.stb_i ;
+ input \wb_i.we_i ;
+ wire \wb_i.we_i ;
+ output \wb_o.ack_o ;
+ wire \wb_o.ack_o ;
+ output [31:0] \wb_o.dat_o ;
+ wire [31:0] \wb_o.dat_o ;
+ input wb_rst_i;
+ wire wb_rst_i;
+ assign _0_ = \wb_i.cyc_i & \wb_i.stb_i ;
+ assign _1_ = _0_ & \wb_i.we_i ;
+ assign _2_ = _1_ ? \wb_i.dat_i : reg_o_buf;
+ always @(posedge wb_clk_i, posedge wb_rst_i)
+ if (wb_rst_i) _3_ <= 32'd14;
+ else _3_ <= _2_;
+ always @(posedge wb_clk_i, posedge wb_rst_i)
+ if (wb_rst_i) _4_ <= 33'h000000000;
+ else _4_ <= { reg_o_buf, 1'h1 };
+ assign reg_o_buf = _3_;
+ assign \wb_o.ack_o = _4_[0];
+ assign \wb_o.dat_o = _4_[32:1];
+ assign reg_o = reg_o_buf;
+endmodule
+
+module wb_register32_91a7f356ca6ce41b6122bd41e60c1f2eb8f0f0e3(wb_clk_i, wb_rst_i, \wb_i.stb_i , \wb_i.cyc_i , \wb_i.we_i , \wb_i.dat_i , \wb_i.adr_i , reg_i, \wb_o.ack_o , \wb_o.dat_o , reg_o);
+ wire _0_;
+ wire _1_;
+ wire [31:0] _2_;
+ reg [31:0] _3_;
+ reg [32:0] _4_;
+ input [31:0] reg_i;
+ wire [31:0] reg_i;
+ output [31:0] reg_o;
+ wire [31:0] reg_o;
+ wire [31:0] reg_o_buf;
+ input wb_clk_i;
+ wire wb_clk_i;
+ input [31:0] \wb_i.adr_i ;
+ wire [31:0] \wb_i.adr_i ;
+ input \wb_i.cyc_i ;
+ wire \wb_i.cyc_i ;
+ input [31:0] \wb_i.dat_i ;
+ wire [31:0] \wb_i.dat_i ;
+ input \wb_i.stb_i ;
+ wire \wb_i.stb_i ;
+ input \wb_i.we_i ;
+ wire \wb_i.we_i ;
+ output \wb_o.ack_o ;
+ wire \wb_o.ack_o ;
+ output [31:0] \wb_o.dat_o ;
+ wire [31:0] \wb_o.dat_o ;
+ input wb_rst_i;
+ wire wb_rst_i;
+ assign _0_ = \wb_i.cyc_i & \wb_i.stb_i ;
+ assign _1_ = _0_ & \wb_i.we_i ;
+ assign _2_ = _1_ ? \wb_i.dat_i : reg_o_buf;
+ always @(posedge wb_clk_i, posedge wb_rst_i)
+ if (wb_rst_i) _3_ <= 32'd0;
+ else _3_ <= _2_;
+ always @(posedge wb_clk_i, posedge wb_rst_i)
+ if (wb_rst_i) _4_ <= 33'h000000000;
+ else _4_ <= { reg_o_buf, 1'h1 };
+ assign reg_o_buf = _3_;
+ assign \wb_o.ack_o = _4_[0];
+ assign \wb_o.dat_o = _4_[32:1];
+ assign reg_o = reg_o_buf;
+endmodule
diff --git a/verilog/rtl/defines.v b/verilog/rtl/defines.v
new file mode 100644
index 0000000..44a29a0
--- /dev/null
+++ b/verilog/rtl/defines.v
@@ -0,0 +1,66 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+`default_nettype none
+
+`ifndef __GLOBAL_DEFINE_H
+// Global parameters
+`define __GLOBAL_DEFINE_H
+
+`define MPRJ_IO_PADS_1 19 /* number of user GPIO pads on user1 side */
+`define MPRJ_IO_PADS_2 19 /* number of user GPIO pads on user2 side */
+`define MPRJ_IO_PADS (`MPRJ_IO_PADS_1 + `MPRJ_IO_PADS_2)
+
+`define MPRJ_PWR_PADS_1 2 /* vdda1, vccd1 enable/disable control */
+`define MPRJ_PWR_PADS_2 2 /* vdda2, vccd2 enable/disable control */
+`define MPRJ_PWR_PADS (`MPRJ_PWR_PADS_1 + `MPRJ_PWR_PADS_2)
+
+// Analog pads are only used by the "caravan" module and associated
+// modules such as user_analog_project_wrapper and chip_io_alt.
+
+`define ANALOG_PADS_1 5
+`define ANALOG_PADS_2 6
+
+`define ANALOG_PADS (`ANALOG_PADS_1 + `ANALOG_PADS_2)
+
+// Size of soc_mem_synth
+
+// Type and size of soc_mem
+// `define USE_OPENRAM
+`define USE_CUSTOM_DFFRAM
+// don't change the following without double checking addr widths
+`define MEM_WORDS 256
+
+// Number of columns in the custom memory; takes one of three values:
+// 1 column : 1 KB, 2 column: 2 KB, 4 column: 4KB
+`define DFFRAM_WSIZE 4
+`define DFFRAM_USE_LATCH 0
+
+// not really parameterized but just to easily keep track of the number
+// of ram_block across different modules
+`define RAM_BLOCKS 1
+
+// Clock divisor default value
+`define CLK_DIV 3'b010
+
+// GPIO control default mode and enable for most I/Os
+// Most I/Os set to be user input pins on startup.
+// NOTE: To be modified, with GPIOs 5 to 35 being set from a build-time-
+// programmable block.
+`define MGMT_INIT 1'b0
+`define OENB_INIT 1'b0
+`define DM_INIT 3'b001
+
+`endif // __GLOBAL_DEFINE_H
\ No newline at end of file
diff --git a/verilog/rtl/efuse_ctrl/efuse_array_fromvhdl.v b/verilog/rtl/efuse_ctrl/efuse_array_fromvhdl.v
new file mode 100644
index 0000000..1362633
--- /dev/null
+++ b/verilog/rtl/efuse_ctrl/efuse_array_fromvhdl.v
@@ -0,0 +1,16 @@
+/* Generated by Yosys 0.22 (git sha1 f109fa3d4, gcc 8.3.0-6 -fPIC -Os) */
+
+(* top = 1 *)
+module efuse_array(nPRESET, SENSE, PROG_ENA, SEL, DO);
+ output [7:0] DO;
+ wire [7:0] DO;
+ input [7:0] PROG_ENA;
+ wire [7:0] PROG_ENA;
+ input [127:0] SEL;
+ wire [127:0] SEL;
+ input SENSE;
+ wire SENSE;
+ input nPRESET;
+ wire nPRESET;
+ assign DO = PROG_ENA;
+endmodule
diff --git a/verilog/rtl/fpga_struct_block/fpga_struct_block_fromvhdl.v b/verilog/rtl/fpga_struct_block/fpga_struct_block_fromvhdl.v
new file mode 100644
index 0000000..8f5e281
--- /dev/null
+++ b/verilog/rtl/fpga_struct_block/fpga_struct_block_fromvhdl.v
@@ -0,0 +1,1366 @@
+/* Generated by Yosys 0.22 (git sha1 f109fa3d4, gcc 10.2.1-6 -fPIC -Os) */
+
+module fpga_cfg_shiftreg_2(config_clk_i, config_ena_i, config_shift_i, config_shift_o, config_o);
+ reg [1:0] _0_;
+ input config_clk_i;
+ wire config_clk_i;
+ wire [1:0] config_data;
+ input config_ena_i;
+ wire config_ena_i;
+ output [1:0] config_o;
+ wire [1:0] config_o;
+ input config_shift_i;
+ wire config_shift_i;
+ output config_shift_o;
+ wire config_shift_o;
+ always @(posedge config_clk_i)
+ _0_ <= { config_shift_i, config_data[1] };
+ assign config_data = _0_;
+ assign config_shift_o = config_data[0];
+ assign config_o = config_data;
+endmodule
+
+module fpga_cfg_shiftreg_264(config_clk_i, config_ena_i, config_shift_i, config_shift_o, config_o);
+ reg [263:0] _0_;
+ input config_clk_i;
+ wire config_clk_i;
+ wire [263:0] config_data;
+ input config_ena_i;
+ wire config_ena_i;
+ output [263:0] config_o;
+ wire [263:0] config_o;
+ input config_shift_i;
+ wire config_shift_i;
+ output config_shift_o;
+ wire config_shift_o;
+ always @(posedge config_clk_i)
+ _0_ <= { config_shift_i, config_data[263:1] };
+ assign config_data = _0_;
+ assign config_shift_o = config_data[0];
+ assign config_o = config_data;
+endmodule
+
+module fpga_logic_block(clk_i, glb_rstn_i, config_clk_i, config_ena_i, config_shift_i, inputs_i, config_shift_o, outputs_o);
+ wire _00_;
+ wire _01_;
+ wire _02_;
+ wire _03_;
+ wire _04_;
+ wire _05_;
+ wire _06_;
+ wire _07_;
+ wire _08_;
+ wire _09_;
+ wire _10_;
+ wire [263:0] _11_;
+ wire _12_;
+ wire _13_;
+ wire _14_;
+ wire _15_;
+ wire _16_;
+ wire _17_;
+ wire _18_;
+ wire _19_;
+ wire _20_;
+ wire _21_;
+ wire _22_;
+ wire _23_;
+ wire _24_;
+ wire _25_;
+ wire _26_;
+ wire _27_;
+ wire _28_;
+ wire _29_;
+ wire _30_;
+ wire _31_;
+ wire _32_;
+ wire _33_;
+ wire _34_;
+ wire _35_;
+ wire _36_;
+ wire _37_;
+ wire _38_;
+ wire _39_;
+ wire _40_;
+ wire _41_;
+ wire [31:0] cell_in;
+ wire [7:0] cell_out;
+ input clk_i;
+ wire clk_i;
+ input config_clk_i;
+ wire config_clk_i;
+ wire [263:0] config_data;
+ input config_ena_i;
+ wire config_ena_i;
+ wire [263:0] config_record;
+ input config_shift_i;
+ wire config_shift_i;
+ output config_shift_o;
+ wire config_shift_o;
+ input glb_rstn_i;
+ wire glb_rstn_i;
+ input [31:0] inputs_i;
+ wire [31:0] inputs_i;
+ output [7:0] outputs_o;
+ wire [7:0] outputs_o;
+ fpga_cfg_shiftreg_264 config_register (
+ .config_clk_i(config_clk_i),
+ .config_ena_i(config_ena_i),
+ .config_o(_11_),
+ .config_shift_i(config_shift_i),
+ .config_shift_o(_10_)
+ );
+ fpga_routing_mux_16_4_0 \crossbar:1.crossbar_mux (
+ .config_i(config_record[127:124]),
+ .route_i({ inputs_i[7:0], cell_out }),
+ .route_o(_20_)
+ );
+ fpga_routing_mux_16_4_2 \crossbar:10.crossbar_mux (
+ .config_i(config_record[91:88]),
+ .route_i({ inputs_i[15:8], cell_out }),
+ .route_o(_29_)
+ );
+ fpga_routing_mux_16_4_2 \crossbar:11.crossbar_mux (
+ .config_i(config_record[87:84]),
+ .route_i({ inputs_i[23:16], cell_out }),
+ .route_o(_30_)
+ );
+ fpga_routing_mux_16_4_2 \crossbar:12.crossbar_mux (
+ .config_i(config_record[83:80]),
+ .route_i({ inputs_i[31:24], cell_out }),
+ .route_o(_31_)
+ );
+ fpga_routing_mux_16_4_3 \crossbar:13.crossbar_mux (
+ .config_i(config_record[79:76]),
+ .route_i({ inputs_i[7:0], cell_out }),
+ .route_o(_32_)
+ );
+ fpga_routing_mux_16_4_3 \crossbar:14.crossbar_mux (
+ .config_i(config_record[75:72]),
+ .route_i({ inputs_i[15:8], cell_out }),
+ .route_o(_33_)
+ );
+ fpga_routing_mux_16_4_3 \crossbar:15.crossbar_mux (
+ .config_i(config_record[71:68]),
+ .route_i({ inputs_i[23:16], cell_out }),
+ .route_o(_34_)
+ );
+ fpga_routing_mux_16_4_3 \crossbar:16.crossbar_mux (
+ .config_i(config_record[67:64]),
+ .route_i({ inputs_i[31:24], cell_out }),
+ .route_o(_35_)
+ );
+ fpga_routing_mux_16_4_4 \crossbar:17.crossbar_mux (
+ .config_i(config_record[63:60]),
+ .route_i({ inputs_i[7:0], cell_out }),
+ .route_o(_36_)
+ );
+ fpga_routing_mux_16_4_4 \crossbar:18.crossbar_mux (
+ .config_i(config_record[59:56]),
+ .route_i({ inputs_i[15:8], cell_out }),
+ .route_o(_37_)
+ );
+ fpga_routing_mux_16_4_4 \crossbar:19.crossbar_mux (
+ .config_i(config_record[55:52]),
+ .route_i({ inputs_i[23:16], cell_out }),
+ .route_o(_38_)
+ );
+ fpga_routing_mux_16_4_0 \crossbar:2.crossbar_mux (
+ .config_i(config_record[123:120]),
+ .route_i({ inputs_i[15:8], cell_out }),
+ .route_o(_21_)
+ );
+ fpga_routing_mux_16_4_4 \crossbar:20.crossbar_mux (
+ .config_i(config_record[51:48]),
+ .route_i({ inputs_i[31:24], cell_out }),
+ .route_o(_39_)
+ );
+ fpga_routing_mux_16_4_5 \crossbar:21.crossbar_mux (
+ .config_i(config_record[47:44]),
+ .route_i({ inputs_i[7:0], cell_out }),
+ .route_o(_40_)
+ );
+ fpga_routing_mux_16_4_5 \crossbar:22.crossbar_mux (
+ .config_i(config_record[43:40]),
+ .route_i({ inputs_i[15:8], cell_out }),
+ .route_o(_41_)
+ );
+ fpga_routing_mux_16_4_5 \crossbar:23.crossbar_mux (
+ .config_i(config_record[39:36]),
+ .route_i({ inputs_i[23:16], cell_out }),
+ .route_o(_00_)
+ );
+ fpga_routing_mux_16_4_5 \crossbar:24.crossbar_mux (
+ .config_i(config_record[35:32]),
+ .route_i({ inputs_i[31:24], cell_out }),
+ .route_o(_01_)
+ );
+ fpga_routing_mux_16_4_6 \crossbar:25.crossbar_mux (
+ .config_i(config_record[31:28]),
+ .route_i({ inputs_i[7:0], cell_out }),
+ .route_o(_02_)
+ );
+ fpga_routing_mux_16_4_6 \crossbar:26.crossbar_mux (
+ .config_i(config_record[27:24]),
+ .route_i({ inputs_i[15:8], cell_out }),
+ .route_o(_03_)
+ );
+ fpga_routing_mux_16_4_6 \crossbar:27.crossbar_mux (
+ .config_i(config_record[23:20]),
+ .route_i({ inputs_i[23:16], cell_out }),
+ .route_o(_04_)
+ );
+ fpga_routing_mux_16_4_6 \crossbar:28.crossbar_mux (
+ .config_i(config_record[19:16]),
+ .route_i({ inputs_i[31:24], cell_out }),
+ .route_o(_05_)
+ );
+ fpga_routing_mux_16_4_7 \crossbar:29.crossbar_mux (
+ .config_i(config_record[15:12]),
+ .route_i({ inputs_i[7:0], cell_out }),
+ .route_o(_06_)
+ );
+ fpga_routing_mux_16_4_0 \crossbar:3.crossbar_mux (
+ .config_i(config_record[119:116]),
+ .route_i({ inputs_i[23:16], cell_out }),
+ .route_o(_22_)
+ );
+ fpga_routing_mux_16_4_7 \crossbar:30.crossbar_mux (
+ .config_i(config_record[11:8]),
+ .route_i({ inputs_i[15:8], cell_out }),
+ .route_o(_07_)
+ );
+ fpga_routing_mux_16_4_7 \crossbar:31.crossbar_mux (
+ .config_i(config_record[7:4]),
+ .route_i({ inputs_i[23:16], cell_out }),
+ .route_o(_08_)
+ );
+ fpga_routing_mux_16_4_7 \crossbar:32.crossbar_mux (
+ .config_i(config_record[3:0]),
+ .route_i({ inputs_i[31:24], cell_out }),
+ .route_o(_09_)
+ );
+ fpga_routing_mux_16_4_0 \crossbar:4.crossbar_mux (
+ .config_i(config_record[115:112]),
+ .route_i({ inputs_i[31:24], cell_out }),
+ .route_o(_23_)
+ );
+ fpga_routing_mux_16_4_1 \crossbar:5.crossbar_mux (
+ .config_i(config_record[111:108]),
+ .route_i({ inputs_i[7:0], cell_out }),
+ .route_o(_24_)
+ );
+ fpga_routing_mux_16_4_1 \crossbar:6.crossbar_mux (
+ .config_i(config_record[107:104]),
+ .route_i({ inputs_i[15:8], cell_out }),
+ .route_o(_25_)
+ );
+ fpga_routing_mux_16_4_1 \crossbar:7.crossbar_mux (
+ .config_i(config_record[103:100]),
+ .route_i({ inputs_i[23:16], cell_out }),
+ .route_o(_26_)
+ );
+ fpga_routing_mux_16_4_1 \crossbar:8.crossbar_mux (
+ .config_i(config_record[99:96]),
+ .route_i({ inputs_i[31:24], cell_out }),
+ .route_o(_27_)
+ );
+ fpga_routing_mux_16_4_2 \crossbar:9.crossbar_mux (
+ .config_i(config_record[95:92]),
+ .route_i({ inputs_i[7:0], cell_out }),
+ .route_o(_28_)
+ );
+ fpga_logic_cell \logic_cells:1.cell (
+ .clk_i(clk_i),
+ .\config_i.lut_config (config_record[262:247]),
+ .\config_i.mux_config (config_record[263]),
+ .glb_rstn_i(glb_rstn_i),
+ .logic_i(cell_in[31:28]),
+ .logic_o(_12_)
+ );
+ fpga_logic_cell \logic_cells:2.cell (
+ .clk_i(clk_i),
+ .\config_i.lut_config (config_record[245:230]),
+ .\config_i.mux_config (config_record[246]),
+ .glb_rstn_i(glb_rstn_i),
+ .logic_i(cell_in[27:24]),
+ .logic_o(_13_)
+ );
+ fpga_logic_cell \logic_cells:3.cell (
+ .clk_i(clk_i),
+ .\config_i.lut_config (config_record[228:213]),
+ .\config_i.mux_config (config_record[229]),
+ .glb_rstn_i(glb_rstn_i),
+ .logic_i(cell_in[23:20]),
+ .logic_o(_14_)
+ );
+ fpga_logic_cell \logic_cells:4.cell (
+ .clk_i(clk_i),
+ .\config_i.lut_config (config_record[211:196]),
+ .\config_i.mux_config (config_record[212]),
+ .glb_rstn_i(glb_rstn_i),
+ .logic_i(cell_in[19:16]),
+ .logic_o(_15_)
+ );
+ fpga_logic_cell \logic_cells:5.cell (
+ .clk_i(clk_i),
+ .\config_i.lut_config (config_record[194:179]),
+ .\config_i.mux_config (config_record[195]),
+ .glb_rstn_i(glb_rstn_i),
+ .logic_i(cell_in[15:12]),
+ .logic_o(_16_)
+ );
+ fpga_logic_cell \logic_cells:6.cell (
+ .clk_i(clk_i),
+ .\config_i.lut_config (config_record[177:162]),
+ .\config_i.mux_config (config_record[178]),
+ .glb_rstn_i(glb_rstn_i),
+ .logic_i(cell_in[11:8]),
+ .logic_o(_17_)
+ );
+ fpga_logic_cell \logic_cells:7.cell (
+ .clk_i(clk_i),
+ .\config_i.lut_config (config_record[160:145]),
+ .\config_i.mux_config (config_record[161]),
+ .glb_rstn_i(glb_rstn_i),
+ .logic_i(cell_in[7:4]),
+ .logic_o(_18_)
+ );
+ fpga_logic_cell \logic_cells:8.cell (
+ .clk_i(clk_i),
+ .\config_i.lut_config (config_record[143:128]),
+ .\config_i.mux_config (config_record[144]),
+ .glb_rstn_i(glb_rstn_i),
+ .logic_i(cell_in[3:0]),
+ .logic_o(_19_)
+ );
+ assign cell_in = { _23_, _22_, _21_, _20_, _27_, _26_, _25_, _24_, _31_, _30_, _29_, _28_, _35_, _34_, _33_, _32_, _39_, _38_, _37_, _36_, _01_, _00_, _41_, _40_, _05_, _04_, _03_, _02_, _09_, _08_, _07_, _06_ };
+ assign cell_out = { _19_, _18_, _17_, _16_, _15_, _14_, _13_, _12_ };
+ assign config_data = _11_;
+ assign config_record = { config_data[144:128], config_data[161:145], config_data[178:162], config_data[195:179], config_data[212:196], config_data[229:213], config_data[246:230], config_data[263:247], config_data[3:0], config_data[7:4], config_data[11:8], config_data[15:12], config_data[19:16], config_data[23:20], config_data[27:24], config_data[31:28], config_data[35:32], config_data[39:36], config_data[43:40], config_data[47:44], config_data[51:48], config_data[55:52], config_data[59:56], config_data[63:60], config_data[67:64], config_data[71:68], config_data[75:72], config_data[79:76], config_data[83:80], config_data[87:84], config_data[91:88], config_data[95:92], config_data[99:96], config_data[103:100], config_data[107:104], config_data[111:108], config_data[115:112], config_data[119:116], config_data[123:120], config_data[127:124] };
+ assign config_shift_o = _10_;
+ assign outputs_o = cell_out;
+endmodule
+
+module fpga_logic_cell(\config_i.lut_config , \config_i.mux_config , clk_i, glb_rstn_i, logic_i, logic_o);
+ wire _0_;
+ wire _1_;
+ wire _2_;
+ wire _3_;
+ wire _4_;
+ wire _5_;
+ wire _6_;
+ wire _7_;
+ input clk_i;
+ wire clk_i;
+ input [15:0] \config_i.lut_config ;
+ wire [15:0] \config_i.lut_config ;
+ input \config_i.mux_config ;
+ wire \config_i.mux_config ;
+ input glb_rstn_i;
+ wire glb_rstn_i;
+ input [3:0] logic_i;
+ wire [3:0] logic_i;
+ wire [3:0] logic_in_buf;
+ output logic_o;
+ wire logic_o;
+ wire lut_out;
+ wire register_out;
+ assign _6_ = ~ \config_i.mux_config ;
+ assign _7_ = _6_ ? lut_out : register_out;
+ fpga_tech_register cell_reg (
+ .clk_i(clk_i),
+ .config_i_rst_polarity(1'h0),
+ .config_i_rst_value(1'h0),
+ .data_i(lut_out),
+ .data_o(_5_),
+ .rstn_i(glb_rstn_i)
+ );
+ fpga_tech_buffer \in_bufs:1.cell_tstart (
+ .i(logic_i[0]),
+ .z(_0_)
+ );
+ fpga_tech_buffer \in_bufs:2.cell_tstart (
+ .i(logic_i[1]),
+ .z(_1_)
+ );
+ fpga_tech_buffer \in_bufs:3.cell_tstart (
+ .i(logic_i[2]),
+ .z(_2_)
+ );
+ fpga_tech_buffer \in_bufs:4.cell_tstart (
+ .i(logic_i[3]),
+ .z(_3_)
+ );
+ fpga_lut_4 lut (
+ .config_i(\config_i.lut_config ),
+ .glb_rstn_i(glb_rstn_i),
+ .logic_i(logic_in_buf),
+ .logic_o(_4_)
+ );
+ assign lut_out = _4_;
+ assign register_out = _5_;
+ assign logic_in_buf = { _3_, _2_, _1_, _0_ };
+ assign logic_o = _7_;
+endmodule
+
+module fpga_lut_1(glb_rstn_i, config_i, logic_i, logic_o);
+ wire _0_;
+ wire _1_;
+ wire _2_;
+ wire _3_;
+ wire _4_;
+ wire _5_;
+ wire _6_;
+ wire _7_;
+ wire _8_;
+ input [1:0] config_i;
+ wire [1:0] config_i;
+ input glb_rstn_i;
+ wire glb_rstn_i;
+ input logic_i;
+ wire logic_i;
+ output logic_o;
+ wire logic_o;
+ wire lut_out;
+ wire sublut0_out;
+ wire sublut1_out;
+ assign _0_ = ~ sublut0_out;
+ assign _1_ = ~ sublut1_out;
+ assign _2_ = _0_ & _1_;
+ assign _3_ = sublut0_out & sublut1_out;
+ assign _4_ = ~ logic_i;
+ assign _5_ = logic_i ? sublut1_out : 1'h0;
+ assign _6_ = _4_ ? sublut0_out : _5_;
+ assign _7_ = _3_ ? 1'h1 : _6_;
+ assign _8_ = _2_ ? 1'h0 : _7_;
+ assign lut_out = _8_;
+ assign sublut0_out = config_i[0];
+ assign sublut1_out = config_i[1];
+ assign logic_o = lut_out;
+endmodule
+
+module fpga_lut_2(glb_rstn_i, config_i, logic_i, logic_o);
+ wire _00_;
+ wire _01_;
+ wire _02_;
+ wire _03_;
+ wire _04_;
+ wire _05_;
+ wire _06_;
+ wire _07_;
+ wire _08_;
+ wire _09_;
+ wire _10_;
+ input [3:0] config_i;
+ wire [3:0] config_i;
+ input glb_rstn_i;
+ wire glb_rstn_i;
+ input [1:0] logic_i;
+ wire [1:0] logic_i;
+ output logic_o;
+ wire logic_o;
+ wire lut_out;
+ wire sublut0_out;
+ wire sublut1_out;
+ assign _02_ = ~ sublut0_out;
+ assign _03_ = ~ sublut1_out;
+ assign _04_ = _02_ & _03_;
+ assign _05_ = sublut0_out & sublut1_out;
+ assign _06_ = ~ logic_i[1];
+ assign _07_ = logic_i[1] ? sublut1_out : 1'h0;
+ assign _08_ = _06_ ? sublut0_out : _07_;
+ assign _09_ = _05_ ? 1'h1 : _08_;
+ assign _10_ = _04_ ? 1'h0 : _09_;
+ fpga_lut_1 \subluts.sublut0 (
+ .config_i(config_i[1:0]),
+ .glb_rstn_i(glb_rstn_i),
+ .logic_i(logic_i[0]),
+ .logic_o(_00_)
+ );
+ fpga_lut_1 \subluts.sublut1 (
+ .config_i(config_i[3:2]),
+ .glb_rstn_i(glb_rstn_i),
+ .logic_i(logic_i[0]),
+ .logic_o(_01_)
+ );
+ assign lut_out = _10_;
+ assign sublut0_out = _00_;
+ assign sublut1_out = _01_;
+ assign logic_o = lut_out;
+endmodule
+
+module fpga_lut_3(glb_rstn_i, config_i, logic_i, logic_o);
+ wire _00_;
+ wire _01_;
+ wire _02_;
+ wire _03_;
+ wire _04_;
+ wire _05_;
+ wire _06_;
+ wire _07_;
+ wire _08_;
+ wire _09_;
+ wire _10_;
+ input [7:0] config_i;
+ wire [7:0] config_i;
+ input glb_rstn_i;
+ wire glb_rstn_i;
+ input [2:0] logic_i;
+ wire [2:0] logic_i;
+ output logic_o;
+ wire logic_o;
+ wire lut_out;
+ wire sublut0_out;
+ wire sublut1_out;
+ assign _02_ = ~ sublut0_out;
+ assign _03_ = ~ sublut1_out;
+ assign _04_ = _02_ & _03_;
+ assign _05_ = sublut0_out & sublut1_out;
+ assign _06_ = ~ logic_i[2];
+ assign _07_ = logic_i[2] ? sublut1_out : 1'h0;
+ assign _08_ = _06_ ? sublut0_out : _07_;
+ assign _09_ = _05_ ? 1'h1 : _08_;
+ assign _10_ = _04_ ? 1'h0 : _09_;
+ fpga_lut_2 \subluts.sublut0 (
+ .config_i(config_i[3:0]),
+ .glb_rstn_i(glb_rstn_i),
+ .logic_i(logic_i[1:0]),
+ .logic_o(_00_)
+ );
+ fpga_lut_2 \subluts.sublut1 (
+ .config_i(config_i[7:4]),
+ .glb_rstn_i(glb_rstn_i),
+ .logic_i(logic_i[1:0]),
+ .logic_o(_01_)
+ );
+ assign lut_out = _10_;
+ assign sublut0_out = _00_;
+ assign sublut1_out = _01_;
+ assign logic_o = lut_out;
+endmodule
+
+module fpga_lut_4(glb_rstn_i, config_i, logic_i, logic_o);
+ wire _00_;
+ wire _01_;
+ wire _02_;
+ wire _03_;
+ wire _04_;
+ wire _05_;
+ wire _06_;
+ wire _07_;
+ wire _08_;
+ wire _09_;
+ wire _10_;
+ wire _11_;
+ wire _12_;
+ wire _13_;
+ wire buffered_out0;
+ wire buffered_out1;
+ input [15:0] config_i;
+ wire [15:0] config_i;
+ input glb_rstn_i;
+ wire glb_rstn_i;
+ input [3:0] logic_i;
+ wire [3:0] logic_i;
+ output logic_o;
+ wire logic_o;
+ wire lut_out;
+ wire sublut0_out;
+ wire sublut1_out;
+ assign _02_ = ~ sublut0_out;
+ assign _03_ = ~ sublut1_out;
+ assign _04_ = _02_ & _03_;
+ assign _05_ = sublut0_out & sublut1_out;
+ assign _06_ = ~ logic_i[3];
+ assign _07_ = logic_i[3] ? sublut1_out : 1'h0;
+ assign _08_ = _06_ ? sublut0_out : _07_;
+ assign _09_ = _05_ ? 1'h1 : _08_;
+ assign _10_ = _04_ ? 1'h0 : _09_;
+ fpga_tech_buffer \breaker.loop_breaker (
+ .i(buffered_out0),
+ .z(_12_)
+ );
+ fpga_tech_buffer \breaker.lut_tfinish (
+ .i(lut_out),
+ .z(_11_)
+ );
+ fpga_tech_buffer \breaker.lut_tstart (
+ .i(buffered_out1),
+ .z(_13_)
+ );
+ fpga_lut_3 \subluts.sublut0 (
+ .config_i(config_i[7:0]),
+ .glb_rstn_i(glb_rstn_i),
+ .logic_i(logic_i[2:0]),
+ .logic_o(_00_)
+ );
+ fpga_lut_3 \subluts.sublut1 (
+ .config_i(config_i[15:8]),
+ .glb_rstn_i(glb_rstn_i),
+ .logic_i(logic_i[2:0]),
+ .logic_o(_01_)
+ );
+ assign lut_out = _10_;
+ assign sublut0_out = _00_;
+ assign sublut1_out = _01_;
+ assign buffered_out0 = _11_;
+ assign buffered_out1 = _12_;
+ assign logic_o = _13_;
+endmodule
+
+module fpga_routing_mux_16_4_0(config_i, route_i, route_o);
+ wire _00_;
+ wire _01_;
+ wire _02_;
+ wire _03_;
+ wire _04_;
+ wire _05_;
+ wire _06_;
+ wire _07_;
+ wire _08_;
+ wire _09_;
+ wire _10_;
+ wire _11_;
+ wire _12_;
+ wire _13_;
+ wire _14_;
+ input [3:0] config_i;
+ wire [3:0] config_i;
+ input [15:0] route_i;
+ wire [15:0] route_i;
+ wire [15:0] route_int;
+ output route_o;
+ wire route_o;
+ assign _00_ = config_i[0] ? route_int[1] : route_int[0];
+ assign _01_ = config_i[0] ? route_int[5] : route_int[4];
+ assign _02_ = config_i[0] ? route_int[9] : route_int[8];
+ assign _03_ = config_i[0] ? route_int[13] : route_int[12];
+ assign _04_ = config_i[2] ? _11_ : _10_;
+ assign _05_ = config_i[0] ? route_int[3] : route_int[2];
+ assign _06_ = config_i[0] ? route_int[7] : route_int[6];
+ assign _07_ = config_i[0] ? route_int[11] : route_int[10];
+ assign _08_ = config_i[0] ? route_int[15] : route_int[14];
+ assign _09_ = config_i[2] ? _13_ : _12_;
+ assign _10_ = config_i[1] ? _05_ : _00_;
+ assign _11_ = config_i[1] ? _06_ : _01_;
+ assign _12_ = config_i[1] ? _07_ : _02_;
+ assign _13_ = config_i[1] ? _08_ : _03_;
+ assign _14_ = config_i[3] ? _09_ : _04_;
+ assign route_int = { route_i[15:1], 1'h0 };
+ assign route_o = _14_;
+endmodule
+
+module fpga_routing_mux_16_4_1(config_i, route_i, route_o);
+ wire _00_;
+ wire _01_;
+ wire _02_;
+ wire _03_;
+ wire _04_;
+ wire _05_;
+ wire _06_;
+ wire _07_;
+ wire _08_;
+ wire _09_;
+ wire _10_;
+ wire _11_;
+ wire _12_;
+ wire _13_;
+ wire _14_;
+ input [3:0] config_i;
+ wire [3:0] config_i;
+ input [15:0] route_i;
+ wire [15:0] route_i;
+ wire [15:0] route_int;
+ output route_o;
+ wire route_o;
+ assign _00_ = config_i[0] ? route_int[1] : route_int[0];
+ assign _01_ = config_i[0] ? route_int[5] : route_int[4];
+ assign _02_ = config_i[0] ? route_int[9] : route_int[8];
+ assign _03_ = config_i[0] ? route_int[13] : route_int[12];
+ assign _04_ = config_i[2] ? _11_ : _10_;
+ assign _05_ = config_i[0] ? route_int[3] : route_int[2];
+ assign _06_ = config_i[0] ? route_int[7] : route_int[6];
+ assign _07_ = config_i[0] ? route_int[11] : route_int[10];
+ assign _08_ = config_i[0] ? route_int[15] : route_int[14];
+ assign _09_ = config_i[2] ? _13_ : _12_;
+ assign _10_ = config_i[1] ? _05_ : _00_;
+ assign _11_ = config_i[1] ? _06_ : _01_;
+ assign _12_ = config_i[1] ? _07_ : _02_;
+ assign _13_ = config_i[1] ? _08_ : _03_;
+ assign _14_ = config_i[3] ? _09_ : _04_;
+ assign route_int = { route_i[15:2], 1'h0, route_i[0] };
+ assign route_o = _14_;
+endmodule
+
+module fpga_routing_mux_16_4_2(config_i, route_i, route_o);
+ wire _00_;
+ wire _01_;
+ wire _02_;
+ wire _03_;
+ wire _04_;
+ wire _05_;
+ wire _06_;
+ wire _07_;
+ wire _08_;
+ wire _09_;
+ wire _10_;
+ wire _11_;
+ wire _12_;
+ wire _13_;
+ wire _14_;
+ input [3:0] config_i;
+ wire [3:0] config_i;
+ input [15:0] route_i;
+ wire [15:0] route_i;
+ wire [15:0] route_int;
+ output route_o;
+ wire route_o;
+ assign _00_ = config_i[0] ? route_int[1] : route_int[0];
+ assign _01_ = config_i[0] ? route_int[5] : route_int[4];
+ assign _02_ = config_i[0] ? route_int[9] : route_int[8];
+ assign _03_ = config_i[0] ? route_int[13] : route_int[12];
+ assign _04_ = config_i[2] ? _11_ : _10_;
+ assign _05_ = config_i[0] ? route_int[3] : route_int[2];
+ assign _06_ = config_i[0] ? route_int[7] : route_int[6];
+ assign _07_ = config_i[0] ? route_int[11] : route_int[10];
+ assign _08_ = config_i[0] ? route_int[15] : route_int[14];
+ assign _09_ = config_i[2] ? _13_ : _12_;
+ assign _10_ = config_i[1] ? _05_ : _00_;
+ assign _11_ = config_i[1] ? _06_ : _01_;
+ assign _12_ = config_i[1] ? _07_ : _02_;
+ assign _13_ = config_i[1] ? _08_ : _03_;
+ assign _14_ = config_i[3] ? _09_ : _04_;
+ assign route_int = { route_i[15:3], 1'h0, route_i[1:0] };
+ assign route_o = _14_;
+endmodule
+
+module fpga_routing_mux_16_4_3(config_i, route_i, route_o);
+ wire _00_;
+ wire _01_;
+ wire _02_;
+ wire _03_;
+ wire _04_;
+ wire _05_;
+ wire _06_;
+ wire _07_;
+ wire _08_;
+ wire _09_;
+ wire _10_;
+ wire _11_;
+ wire _12_;
+ wire _13_;
+ wire _14_;
+ input [3:0] config_i;
+ wire [3:0] config_i;
+ input [15:0] route_i;
+ wire [15:0] route_i;
+ wire [15:0] route_int;
+ output route_o;
+ wire route_o;
+ assign _00_ = config_i[0] ? route_int[1] : route_int[0];
+ assign _01_ = config_i[0] ? route_int[5] : route_int[4];
+ assign _02_ = config_i[0] ? route_int[9] : route_int[8];
+ assign _03_ = config_i[0] ? route_int[13] : route_int[12];
+ assign _04_ = config_i[2] ? _11_ : _10_;
+ assign _05_ = config_i[0] ? route_int[3] : route_int[2];
+ assign _06_ = config_i[0] ? route_int[7] : route_int[6];
+ assign _07_ = config_i[0] ? route_int[11] : route_int[10];
+ assign _08_ = config_i[0] ? route_int[15] : route_int[14];
+ assign _09_ = config_i[2] ? _13_ : _12_;
+ assign _10_ = config_i[1] ? _05_ : _00_;
+ assign _11_ = config_i[1] ? _06_ : _01_;
+ assign _12_ = config_i[1] ? _07_ : _02_;
+ assign _13_ = config_i[1] ? _08_ : _03_;
+ assign _14_ = config_i[3] ? _09_ : _04_;
+ assign route_int = { route_i[15:4], 1'h0, route_i[2:0] };
+ assign route_o = _14_;
+endmodule
+
+module fpga_routing_mux_16_4_4(config_i, route_i, route_o);
+ wire _00_;
+ wire _01_;
+ wire _02_;
+ wire _03_;
+ wire _04_;
+ wire _05_;
+ wire _06_;
+ wire _07_;
+ wire _08_;
+ wire _09_;
+ wire _10_;
+ wire _11_;
+ wire _12_;
+ wire _13_;
+ wire _14_;
+ input [3:0] config_i;
+ wire [3:0] config_i;
+ input [15:0] route_i;
+ wire [15:0] route_i;
+ wire [15:0] route_int;
+ output route_o;
+ wire route_o;
+ assign _00_ = config_i[0] ? route_int[1] : route_int[0];
+ assign _01_ = config_i[0] ? route_int[5] : route_int[4];
+ assign _02_ = config_i[0] ? route_int[9] : route_int[8];
+ assign _03_ = config_i[0] ? route_int[13] : route_int[12];
+ assign _04_ = config_i[2] ? _11_ : _10_;
+ assign _05_ = config_i[0] ? route_int[3] : route_int[2];
+ assign _06_ = config_i[0] ? route_int[7] : route_int[6];
+ assign _07_ = config_i[0] ? route_int[11] : route_int[10];
+ assign _08_ = config_i[0] ? route_int[15] : route_int[14];
+ assign _09_ = config_i[2] ? _13_ : _12_;
+ assign _10_ = config_i[1] ? _05_ : _00_;
+ assign _11_ = config_i[1] ? _06_ : _01_;
+ assign _12_ = config_i[1] ? _07_ : _02_;
+ assign _13_ = config_i[1] ? _08_ : _03_;
+ assign _14_ = config_i[3] ? _09_ : _04_;
+ assign route_int = { route_i[15:5], 1'h0, route_i[3:0] };
+ assign route_o = _14_;
+endmodule
+
+module fpga_routing_mux_16_4_5(config_i, route_i, route_o);
+ wire _00_;
+ wire _01_;
+ wire _02_;
+ wire _03_;
+ wire _04_;
+ wire _05_;
+ wire _06_;
+ wire _07_;
+ wire _08_;
+ wire _09_;
+ wire _10_;
+ wire _11_;
+ wire _12_;
+ wire _13_;
+ wire _14_;
+ input [3:0] config_i;
+ wire [3:0] config_i;
+ input [15:0] route_i;
+ wire [15:0] route_i;
+ wire [15:0] route_int;
+ output route_o;
+ wire route_o;
+ assign _00_ = config_i[0] ? route_int[1] : route_int[0];
+ assign _01_ = config_i[0] ? route_int[5] : route_int[4];
+ assign _02_ = config_i[0] ? route_int[9] : route_int[8];
+ assign _03_ = config_i[0] ? route_int[13] : route_int[12];
+ assign _04_ = config_i[2] ? _11_ : _10_;
+ assign _05_ = config_i[0] ? route_int[3] : route_int[2];
+ assign _06_ = config_i[0] ? route_int[7] : route_int[6];
+ assign _07_ = config_i[0] ? route_int[11] : route_int[10];
+ assign _08_ = config_i[0] ? route_int[15] : route_int[14];
+ assign _09_ = config_i[2] ? _13_ : _12_;
+ assign _10_ = config_i[1] ? _05_ : _00_;
+ assign _11_ = config_i[1] ? _06_ : _01_;
+ assign _12_ = config_i[1] ? _07_ : _02_;
+ assign _13_ = config_i[1] ? _08_ : _03_;
+ assign _14_ = config_i[3] ? _09_ : _04_;
+ assign route_int = { route_i[15:6], 1'h0, route_i[4:0] };
+ assign route_o = _14_;
+endmodule
+
+module fpga_routing_mux_16_4_6(config_i, route_i, route_o);
+ wire _00_;
+ wire _01_;
+ wire _02_;
+ wire _03_;
+ wire _04_;
+ wire _05_;
+ wire _06_;
+ wire _07_;
+ wire _08_;
+ wire _09_;
+ wire _10_;
+ wire _11_;
+ wire _12_;
+ wire _13_;
+ wire _14_;
+ input [3:0] config_i;
+ wire [3:0] config_i;
+ input [15:0] route_i;
+ wire [15:0] route_i;
+ wire [15:0] route_int;
+ output route_o;
+ wire route_o;
+ assign _00_ = config_i[0] ? route_int[1] : route_int[0];
+ assign _01_ = config_i[0] ? route_int[5] : route_int[4];
+ assign _02_ = config_i[0] ? route_int[9] : route_int[8];
+ assign _03_ = config_i[0] ? route_int[13] : route_int[12];
+ assign _04_ = config_i[2] ? _11_ : _10_;
+ assign _05_ = config_i[0] ? route_int[3] : route_int[2];
+ assign _06_ = config_i[0] ? route_int[7] : route_int[6];
+ assign _07_ = config_i[0] ? route_int[11] : route_int[10];
+ assign _08_ = config_i[0] ? route_int[15] : route_int[14];
+ assign _09_ = config_i[2] ? _13_ : _12_;
+ assign _10_ = config_i[1] ? _05_ : _00_;
+ assign _11_ = config_i[1] ? _06_ : _01_;
+ assign _12_ = config_i[1] ? _07_ : _02_;
+ assign _13_ = config_i[1] ? _08_ : _03_;
+ assign _14_ = config_i[3] ? _09_ : _04_;
+ assign route_int = { route_i[15:7], 1'h0, route_i[5:0] };
+ assign route_o = _14_;
+endmodule
+
+module fpga_routing_mux_16_4_7(config_i, route_i, route_o);
+ wire _00_;
+ wire _01_;
+ wire _02_;
+ wire _03_;
+ wire _04_;
+ wire _05_;
+ wire _06_;
+ wire _07_;
+ wire _08_;
+ wire _09_;
+ wire _10_;
+ wire _11_;
+ wire _12_;
+ wire _13_;
+ wire _14_;
+ input [3:0] config_i;
+ wire [3:0] config_i;
+ input [15:0] route_i;
+ wire [15:0] route_i;
+ wire [15:0] route_int;
+ output route_o;
+ wire route_o;
+ assign _00_ = config_i[0] ? route_int[1] : route_int[0];
+ assign _01_ = config_i[0] ? route_int[5] : route_int[4];
+ assign _02_ = config_i[0] ? route_int[9] : route_int[8];
+ assign _03_ = config_i[0] ? route_int[13] : route_int[12];
+ assign _04_ = config_i[2] ? _11_ : _10_;
+ assign _05_ = config_i[0] ? route_int[3] : route_int[2];
+ assign _06_ = config_i[0] ? route_int[7] : route_int[6];
+ assign _07_ = config_i[0] ? route_int[11] : route_int[10];
+ assign _08_ = config_i[0] ? route_int[15] : route_int[14];
+ assign _09_ = config_i[2] ? _13_ : _12_;
+ assign _10_ = config_i[1] ? _05_ : _00_;
+ assign _11_ = config_i[1] ? _06_ : _01_;
+ assign _12_ = config_i[1] ? _07_ : _02_;
+ assign _13_ = config_i[1] ? _08_ : _03_;
+ assign _14_ = config_i[3] ? _09_ : _04_;
+ assign route_int = { route_i[15:8], 1'h0, route_i[6:0] };
+ assign route_o = _14_;
+endmodule
+
+module fpga_routing_mux_4_2_18446744073709551615(config_i, route_i, route_o);
+ wire _0_;
+ wire _1_;
+ wire _2_;
+ input [1:0] config_i;
+ wire [1:0] config_i;
+ input [3:0] route_i;
+ wire [3:0] route_i;
+ wire [3:0] route_int;
+ output route_o;
+ wire route_o;
+ assign _0_ = config_i[0] ? route_int[1] : route_int[0];
+ assign _1_ = config_i[0] ? route_int[3] : route_int[2];
+ assign _2_ = config_i[1] ? _1_ : _0_;
+ assign route_int = route_i;
+ assign route_o = _2_;
+endmodule
+
+module fpga_routing_mux_wcfg_4_2_18446744073709551615(config_clk_i, config_ena_i, config_shift_i, route_i, config_shift_o, route_o);
+ wire _0_;
+ wire _1_;
+ wire [1:0] _2_;
+ input config_clk_i;
+ wire config_clk_i;
+ wire [1:0] config_data;
+ input config_ena_i;
+ wire config_ena_i;
+ input config_shift_i;
+ wire config_shift_i;
+ output config_shift_o;
+ wire config_shift_o;
+ input [3:0] route_i;
+ wire [3:0] route_i;
+ output route_o;
+ wire route_o;
+ fpga_cfg_shiftreg_2 config_register (
+ .config_clk_i(config_clk_i),
+ .config_ena_i(config_ena_i),
+ .config_o(_2_),
+ .config_shift_i(config_shift_i),
+ .config_shift_o(_1_)
+ );
+ fpga_routing_mux_4_2_18446744073709551615 mux (
+ .config_i(config_data),
+ .route_i(route_i),
+ .route_o(_0_)
+ );
+ assign config_data = _2_;
+ assign config_shift_o = _1_;
+ assign route_o = _0_;
+endmodule
+
+(* top = 1 *)
+module fpga_struct_block(clk_i, glb_rstn_i, config_clk_i, config_ena_i, config_shift_i, inputs_up_i, inputs_right_i, inputs_down_i, inputs_left_i, config_shift_o, outputs_o);
+ wire _00_;
+ wire _01_;
+ wire _02_;
+ wire _03_;
+ wire _04_;
+ wire _05_;
+ wire _06_;
+ wire _07_;
+ wire _08_;
+ wire _09_;
+ wire _10_;
+ wire _11_;
+ wire _12_;
+ wire _13_;
+ wire _14_;
+ wire _15_;
+ wire _16_;
+ wire _17_;
+ wire _18_;
+ wire _19_;
+ wire _20_;
+ wire _21_;
+ wire _22_;
+ wire _23_;
+ wire _24_;
+ wire _25_;
+ wire _26_;
+ wire _27_;
+ wire _28_;
+ wire _29_;
+ wire _30_;
+ wire _31_;
+ wire _32_;
+ wire _33_;
+ wire _34_;
+ wire _35_;
+ wire _36_;
+ wire _37_;
+ wire _38_;
+ wire _39_;
+ wire _40_;
+ wire _41_;
+ wire _42_;
+ wire _43_;
+ wire _44_;
+ wire _45_;
+ wire _46_;
+ wire _47_;
+ wire _48_;
+ wire _49_;
+ wire _50_;
+ wire _51_;
+ wire _52_;
+ wire _53_;
+ wire _54_;
+ wire _55_;
+ wire _56_;
+ wire _57_;
+ wire _58_;
+ wire _59_;
+ wire _60_;
+ wire _61_;
+ wire [7:0] _62_;
+ wire _63_;
+ wire _64_;
+ wire _65_;
+ wire [31:0] block_in;
+ wire [33:0] cfg_shift_chain;
+ input clk_i;
+ wire clk_i;
+ input config_clk_i;
+ wire config_clk_i;
+ input config_ena_i;
+ wire config_ena_i;
+ input config_shift_i;
+ wire config_shift_i;
+ output config_shift_o;
+ wire config_shift_o;
+ input glb_rstn_i;
+ wire glb_rstn_i;
+ input [31:0] inputs_down_i;
+ wire [31:0] inputs_down_i;
+ input [31:0] inputs_left_i;
+ wire [31:0] inputs_left_i;
+ input [31:0] inputs_right_i;
+ wire [31:0] inputs_right_i;
+ input [31:0] inputs_up_i;
+ wire [31:0] inputs_up_i;
+ wire \logic.logic_block:587 ;
+ wire [7:0] \logic.logic_block:588 ;
+ output [7:0] outputs_o;
+ wire [7:0] outputs_o;
+ fpga_logic_block \logic.logic_block (
+ .clk_i(clk_i),
+ .config_clk_i(config_clk_i),
+ .config_ena_i(config_ena_i),
+ .config_shift_i(cfg_shift_chain[0]),
+ .config_shift_o(_61_),
+ .glb_rstn_i(glb_rstn_i),
+ .inputs_i(block_in),
+ .outputs_o(_62_)
+ );
+ fpga_routing_mux_wcfg_4_2_18446744073709551615 \muxes_down:1.block_in_mux (
+ .config_clk_i(config_clk_i),
+ .config_ena_i(config_ena_i),
+ .config_shift_i(cfg_shift_chain[30]),
+ .config_shift_o(_26_),
+ .route_i({ inputs_down_i[24], inputs_down_i[16], inputs_down_i[8], inputs_down_i[0] }),
+ .route_o(_27_)
+ );
+ fpga_routing_mux_wcfg_4_2_18446744073709551615 \muxes_down:2.block_in_mux (
+ .config_clk_i(config_clk_i),
+ .config_ena_i(config_ena_i),
+ .config_shift_i(cfg_shift_chain[26]),
+ .config_shift_o(_28_),
+ .route_i({ inputs_down_i[25], inputs_down_i[17], inputs_down_i[9], inputs_down_i[1] }),
+ .route_o(_29_)
+ );
+ fpga_routing_mux_wcfg_4_2_18446744073709551615 \muxes_down:3.block_in_mux (
+ .config_clk_i(config_clk_i),
+ .config_ena_i(config_ena_i),
+ .config_shift_i(cfg_shift_chain[22]),
+ .config_shift_o(_30_),
+ .route_i({ inputs_down_i[26], inputs_down_i[18], inputs_down_i[10], inputs_down_i[2] }),
+ .route_o(_31_)
+ );
+ fpga_routing_mux_wcfg_4_2_18446744073709551615 \muxes_down:4.block_in_mux (
+ .config_clk_i(config_clk_i),
+ .config_ena_i(config_ena_i),
+ .config_shift_i(cfg_shift_chain[18]),
+ .config_shift_o(_32_),
+ .route_i({ inputs_down_i[27], inputs_down_i[19], inputs_down_i[11], inputs_down_i[3] }),
+ .route_o(_34_)
+ );
+ fpga_routing_mux_wcfg_4_2_18446744073709551615 \muxes_down:5.block_in_mux (
+ .config_clk_i(config_clk_i),
+ .config_ena_i(config_ena_i),
+ .config_shift_i(cfg_shift_chain[14]),
+ .config_shift_o(_35_),
+ .route_i({ inputs_down_i[28], inputs_down_i[20], inputs_down_i[12], inputs_down_i[4] }),
+ .route_o(_36_)
+ );
+ fpga_routing_mux_wcfg_4_2_18446744073709551615 \muxes_down:6.block_in_mux (
+ .config_clk_i(config_clk_i),
+ .config_ena_i(config_ena_i),
+ .config_shift_i(cfg_shift_chain[10]),
+ .config_shift_o(_37_),
+ .route_i({ inputs_down_i[29], inputs_down_i[21], inputs_down_i[13], inputs_down_i[5] }),
+ .route_o(_38_)
+ );
+ fpga_routing_mux_wcfg_4_2_18446744073709551615 \muxes_down:7.block_in_mux (
+ .config_clk_i(config_clk_i),
+ .config_ena_i(config_ena_i),
+ .config_shift_i(cfg_shift_chain[6]),
+ .config_shift_o(_39_),
+ .route_i({ inputs_down_i[30], inputs_down_i[22], inputs_down_i[14], inputs_down_i[6] }),
+ .route_o(_40_)
+ );
+ fpga_routing_mux_wcfg_4_2_18446744073709551615 \muxes_down:8.block_in_mux (
+ .config_clk_i(config_clk_i),
+ .config_ena_i(config_ena_i),
+ .config_shift_i(cfg_shift_chain[2]),
+ .config_shift_o(_41_),
+ .route_i({ inputs_down_i[31], inputs_down_i[23], inputs_down_i[15], inputs_down_i[7] }),
+ .route_o(_42_)
+ );
+ fpga_routing_mux_wcfg_4_2_18446744073709551615 \muxes_left:1.block_in_mux (
+ .config_clk_i(config_clk_i),
+ .config_ena_i(config_ena_i),
+ .config_shift_i(cfg_shift_chain[29]),
+ .config_shift_o(_43_),
+ .route_i({ inputs_left_i[24], inputs_left_i[16], inputs_left_i[8], inputs_left_i[0] }),
+ .route_o(_45_)
+ );
+ fpga_routing_mux_wcfg_4_2_18446744073709551615 \muxes_left:2.block_in_mux (
+ .config_clk_i(config_clk_i),
+ .config_ena_i(config_ena_i),
+ .config_shift_i(cfg_shift_chain[25]),
+ .config_shift_o(_46_),
+ .route_i({ inputs_left_i[25], inputs_left_i[17], inputs_left_i[9], inputs_left_i[1] }),
+ .route_o(_47_)
+ );
+ fpga_routing_mux_wcfg_4_2_18446744073709551615 \muxes_left:3.block_in_mux (
+ .config_clk_i(config_clk_i),
+ .config_ena_i(config_ena_i),
+ .config_shift_i(cfg_shift_chain[21]),
+ .config_shift_o(_48_),
+ .route_i({ inputs_left_i[26], inputs_left_i[18], inputs_left_i[10], inputs_left_i[2] }),
+ .route_o(_49_)
+ );
+ fpga_routing_mux_wcfg_4_2_18446744073709551615 \muxes_left:4.block_in_mux (
+ .config_clk_i(config_clk_i),
+ .config_ena_i(config_ena_i),
+ .config_shift_i(cfg_shift_chain[17]),
+ .config_shift_o(_50_),
+ .route_i({ inputs_left_i[27], inputs_left_i[19], inputs_left_i[11], inputs_left_i[3] }),
+ .route_o(_51_)
+ );
+ fpga_routing_mux_wcfg_4_2_18446744073709551615 \muxes_left:5.block_in_mux (
+ .config_clk_i(config_clk_i),
+ .config_ena_i(config_ena_i),
+ .config_shift_i(cfg_shift_chain[13]),
+ .config_shift_o(_52_),
+ .route_i({ inputs_left_i[28], inputs_left_i[20], inputs_left_i[12], inputs_left_i[4] }),
+ .route_o(_53_)
+ );
+ fpga_routing_mux_wcfg_4_2_18446744073709551615 \muxes_left:6.block_in_mux (
+ .config_clk_i(config_clk_i),
+ .config_ena_i(config_ena_i),
+ .config_shift_i(cfg_shift_chain[9]),
+ .config_shift_o(_54_),
+ .route_i({ inputs_left_i[29], inputs_left_i[21], inputs_left_i[13], inputs_left_i[5] }),
+ .route_o(_56_)
+ );
+ fpga_routing_mux_wcfg_4_2_18446744073709551615 \muxes_left:7.block_in_mux (
+ .config_clk_i(config_clk_i),
+ .config_ena_i(config_ena_i),
+ .config_shift_i(cfg_shift_chain[5]),
+ .config_shift_o(_57_),
+ .route_i({ inputs_left_i[30], inputs_left_i[22], inputs_left_i[14], inputs_left_i[6] }),
+ .route_o(_58_)
+ );
+ fpga_routing_mux_wcfg_4_2_18446744073709551615 \muxes_left:8.block_in_mux (
+ .config_clk_i(config_clk_i),
+ .config_ena_i(config_ena_i),
+ .config_shift_i(cfg_shift_chain[1]),
+ .config_shift_o(_59_),
+ .route_i({ inputs_left_i[31], inputs_left_i[23], inputs_left_i[15], inputs_left_i[7] }),
+ .route_o(_60_)
+ );
+ fpga_routing_mux_wcfg_4_2_18446744073709551615 \muxes_right:1.block_in_mux (
+ .config_clk_i(config_clk_i),
+ .config_ena_i(config_ena_i),
+ .config_shift_i(cfg_shift_chain[31]),
+ .config_shift_o(_08_),
+ .route_i({ inputs_right_i[24], inputs_right_i[16], inputs_right_i[8], inputs_right_i[0] }),
+ .route_o(_09_)
+ );
+ fpga_routing_mux_wcfg_4_2_18446744073709551615 \muxes_right:2.block_in_mux (
+ .config_clk_i(config_clk_i),
+ .config_ena_i(config_ena_i),
+ .config_shift_i(cfg_shift_chain[27]),
+ .config_shift_o(_10_),
+ .route_i({ inputs_right_i[25], inputs_right_i[17], inputs_right_i[9], inputs_right_i[1] }),
+ .route_o(_12_)
+ );
+ fpga_routing_mux_wcfg_4_2_18446744073709551615 \muxes_right:3.block_in_mux (
+ .config_clk_i(config_clk_i),
+ .config_ena_i(config_ena_i),
+ .config_shift_i(cfg_shift_chain[23]),
+ .config_shift_o(_13_),
+ .route_i({ inputs_right_i[26], inputs_right_i[18], inputs_right_i[10], inputs_right_i[2] }),
+ .route_o(_14_)
+ );
+ fpga_routing_mux_wcfg_4_2_18446744073709551615 \muxes_right:4.block_in_mux (
+ .config_clk_i(config_clk_i),
+ .config_ena_i(config_ena_i),
+ .config_shift_i(cfg_shift_chain[19]),
+ .config_shift_o(_15_),
+ .route_i({ inputs_right_i[27], inputs_right_i[19], inputs_right_i[11], inputs_right_i[3] }),
+ .route_o(_16_)
+ );
+ fpga_routing_mux_wcfg_4_2_18446744073709551615 \muxes_right:5.block_in_mux (
+ .config_clk_i(config_clk_i),
+ .config_ena_i(config_ena_i),
+ .config_shift_i(cfg_shift_chain[15]),
+ .config_shift_o(_17_),
+ .route_i({ inputs_right_i[28], inputs_right_i[20], inputs_right_i[12], inputs_right_i[4] }),
+ .route_o(_18_)
+ );
+ fpga_routing_mux_wcfg_4_2_18446744073709551615 \muxes_right:6.block_in_mux (
+ .config_clk_i(config_clk_i),
+ .config_ena_i(config_ena_i),
+ .config_shift_i(cfg_shift_chain[11]),
+ .config_shift_o(_19_),
+ .route_i({ inputs_right_i[29], inputs_right_i[21], inputs_right_i[13], inputs_right_i[5] }),
+ .route_o(_20_)
+ );
+ fpga_routing_mux_wcfg_4_2_18446744073709551615 \muxes_right:7.block_in_mux (
+ .config_clk_i(config_clk_i),
+ .config_ena_i(config_ena_i),
+ .config_shift_i(cfg_shift_chain[7]),
+ .config_shift_o(_21_),
+ .route_i({ inputs_right_i[30], inputs_right_i[22], inputs_right_i[14], inputs_right_i[6] }),
+ .route_o(_23_)
+ );
+ fpga_routing_mux_wcfg_4_2_18446744073709551615 \muxes_right:8.block_in_mux (
+ .config_clk_i(config_clk_i),
+ .config_ena_i(config_ena_i),
+ .config_shift_i(cfg_shift_chain[3]),
+ .config_shift_o(_24_),
+ .route_i({ inputs_right_i[31], inputs_right_i[23], inputs_right_i[15], inputs_right_i[7] }),
+ .route_o(_25_)
+ );
+ fpga_routing_mux_wcfg_4_2_18446744073709551615 \muxes_up:1.block_in_mux (
+ .config_clk_i(config_clk_i),
+ .config_ena_i(config_ena_i),
+ .config_shift_i(cfg_shift_chain[32]),
+ .config_shift_o(_00_),
+ .route_i({ inputs_up_i[24], inputs_up_i[16], inputs_up_i[8], inputs_up_i[0] }),
+ .route_o(_11_)
+ );
+ fpga_routing_mux_wcfg_4_2_18446744073709551615 \muxes_up:2.block_in_mux (
+ .config_clk_i(config_clk_i),
+ .config_ena_i(config_ena_i),
+ .config_shift_i(cfg_shift_chain[28]),
+ .config_shift_o(_22_),
+ .route_i({ inputs_up_i[25], inputs_up_i[17], inputs_up_i[9], inputs_up_i[1] }),
+ .route_o(_33_)
+ );
+ fpga_routing_mux_wcfg_4_2_18446744073709551615 \muxes_up:3.block_in_mux (
+ .config_clk_i(config_clk_i),
+ .config_ena_i(config_ena_i),
+ .config_shift_i(cfg_shift_chain[24]),
+ .config_shift_o(_44_),
+ .route_i({ inputs_up_i[26], inputs_up_i[18], inputs_up_i[10], inputs_up_i[2] }),
+ .route_o(_55_)
+ );
+ fpga_routing_mux_wcfg_4_2_18446744073709551615 \muxes_up:4.block_in_mux (
+ .config_clk_i(config_clk_i),
+ .config_ena_i(config_ena_i),
+ .config_shift_i(cfg_shift_chain[20]),
+ .config_shift_o(_63_),
+ .route_i({ inputs_up_i[27], inputs_up_i[19], inputs_up_i[11], inputs_up_i[3] }),
+ .route_o(_64_)
+ );
+ fpga_routing_mux_wcfg_4_2_18446744073709551615 \muxes_up:5.block_in_mux (
+ .config_clk_i(config_clk_i),
+ .config_ena_i(config_ena_i),
+ .config_shift_i(cfg_shift_chain[16]),
+ .config_shift_o(_65_),
+ .route_i({ inputs_up_i[28], inputs_up_i[20], inputs_up_i[12], inputs_up_i[4] }),
+ .route_o(_01_)
+ );
+ fpga_routing_mux_wcfg_4_2_18446744073709551615 \muxes_up:6.block_in_mux (
+ .config_clk_i(config_clk_i),
+ .config_ena_i(config_ena_i),
+ .config_shift_i(cfg_shift_chain[12]),
+ .config_shift_o(_02_),
+ .route_i({ inputs_up_i[29], inputs_up_i[21], inputs_up_i[13], inputs_up_i[5] }),
+ .route_o(_03_)
+ );
+ fpga_routing_mux_wcfg_4_2_18446744073709551615 \muxes_up:7.block_in_mux (
+ .config_clk_i(config_clk_i),
+ .config_ena_i(config_ena_i),
+ .config_shift_i(cfg_shift_chain[8]),
+ .config_shift_o(_04_),
+ .route_i({ inputs_up_i[30], inputs_up_i[22], inputs_up_i[14], inputs_up_i[6] }),
+ .route_o(_05_)
+ );
+ fpga_routing_mux_wcfg_4_2_18446744073709551615 \muxes_up:8.block_in_mux (
+ .config_clk_i(config_clk_i),
+ .config_ena_i(config_ena_i),
+ .config_shift_i(cfg_shift_chain[4]),
+ .config_shift_o(_06_),
+ .route_i({ inputs_up_i[31], inputs_up_i[23], inputs_up_i[15], inputs_up_i[7] }),
+ .route_o(_07_)
+ );
+ assign cfg_shift_chain = { _00_, _08_, _26_, _43_, _22_, _10_, _28_, _46_, _44_, _13_, _30_, _48_, _63_, _15_, _32_, _50_, _65_, _17_, _35_, _52_, _02_, _19_, _37_, _54_, _04_, _21_, _39_, _57_, _06_, _24_, _41_, _59_, \logic.logic_block:587 , config_shift_i };
+ assign block_in = { _60_, _42_, _25_, _07_, _58_, _40_, _23_, _05_, _56_, _38_, _20_, _03_, _53_, _36_, _18_, _01_, _51_, _34_, _16_, _64_, _49_, _31_, _14_, _55_, _47_, _29_, _12_, _33_, _45_, _27_, _09_, _11_ };
+ assign \logic.logic_block:587 = _61_;
+ assign \logic.logic_block:588 = _62_;
+ assign config_shift_o = cfg_shift_chain[33];
+ assign outputs_o = \logic.logic_block:588 ;
+endmodule
diff --git a/verilog/rtl/fpga_struct_block/fpga_tech.v b/verilog/rtl/fpga_struct_block/fpga_tech.v
new file mode 100644
index 0000000..276d1c6
--- /dev/null
+++ b/verilog/rtl/fpga_struct_block/fpga_tech.v
@@ -0,0 +1,52 @@
+module gf180mcu_fd_sc_mcu7t5v0__dffrnq_1( CLK, D, RN, Q );
+input CLK, D, RN;
+output Q;
+endmodule
+
+module gf180mcu_fd_sc_mcu7t5v0__buf_1( I, Z );
+input I;
+output Z;
+endmodule
+
+module gf180mcu_fd_sc_mcu7t5v0__clkbuf_1( I, Z );
+input I;
+output Z;
+endmodule
+
+module fpga_tech_register
+ (input clk_i,
+ input rstn_i,
+ input config_i_rst_polarity,
+ input config_i_rst_value,
+ input data_i,
+ output data_o);
+
+ gf180mcu_fd_sc_mcu7t5v0__dffrnq_1 register (
+ .CLK(clk_i),
+ .D( data_i ),
+ .Q( data_o ),
+ .RN(rstn_i)
+ );
+endmodule
+
+
+module fpga_tech_buffer
+ (input i,
+ output z);
+ wire buf_X;
+ assign z = buf_X;
+
+ gf180mcu_fd_sc_mcu7t5v0__buf_1 tech_buf (
+ .I(i),
+ .Z(buf_X));
+endmodule
+
+
+module fpga_tech_clkbuffer
+ (input i,
+ output z);
+
+ gf180mcu_fd_sc_mcu7t5v0__clkbuf_1 tech_buf (
+ .I(i),
+ .Z(buf_X));
+endmodule
diff --git a/verilog/rtl/fpga_tech.v b/verilog/rtl/fpga_tech.v
new file mode 100644
index 0000000..c9031e2
--- /dev/null
+++ b/verilog/rtl/fpga_tech.v
@@ -0,0 +1,75 @@
+module gf180mcu_fd_sc_mcu7t5v0__dffrnq_1( CLK, D, RN, Q );
+input CLK, D, RN;
+output Q;
+endmodule
+
+module gf180mcu_fd_sc_mcu7t5v0__buf_1( I, Z );
+input I;
+output Z;
+endmodule
+
+module gf180mcu_fd_sc_mcu7t5v0__clkbuf_1( I, Z );
+input I;
+output Z;
+endmodule
+
+module fpga_tech_register
+ (input clk_i,
+ input rstn_i,
+ input config_i_rst_polarity,
+ input config_i_rst_value,
+ input data_i,
+ output data_o);
+
+ gf180mcu_fd_sc_mcu7t5v0__dffrnq_1 register (
+ .CLK(clk_i),
+ .D( data_i ),
+ .Q( data_o ),
+ .RN(rstn_i)
+ );
+endmodule
+
+
+module fpga_tech_buffer
+ (input i,
+ output z);
+ wire buf_X;
+ assign z = buf_X;
+
+ gf180mcu_fd_sc_mcu7t5v0__buf_1 tech_buf (
+ .I(i),
+ .Z(buf_X));
+endmodule
+
+
+module fpga_tech_clkbuffer
+ (input i,
+ output z);
+
+ gf180mcu_fd_sc_mcu7t5v0__clkbuf_1 tech_buf (
+ .I(i),
+ .Z(buf_X));
+endmodule
+
+
+module efuse_ctrl (wb_ack_o,
+ wb_clk_i,
+ wb_cyc_i,
+ wb_rst_i,
+ wb_sel_i,
+ wb_stb_i,
+ wb_we_i,
+ wb_adr_i,
+ wb_dat_i,
+ wb_dat_o);
+ output wb_ack_o;
+ input wb_clk_i;
+ input wb_cyc_i;
+ input wb_rst_i;
+ input wb_sel_i;
+ input wb_stb_i;
+ input wb_we_i;
+ input [9:0] wb_adr_i;
+ input [7:0] wb_dat_i;
+ output [7:0] wb_dat_o;
+endmodule
diff --git a/verilog/rtl/uprj_netlists.v b/verilog/rtl/uprj_netlists.v
new file mode 100644
index 0000000..5538307
--- /dev/null
+++ b/verilog/rtl/uprj_netlists.v
@@ -0,0 +1,27 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+// Include caravel global defines for the number of the user project IO pads
+`include "defines.v"
+`define USE_POWER_PINS
+
+`ifdef GL
+ // Assume default net type to be wire because GL netlists don't have the wire definitions
+ `default_nettype wire
+ `include "gl/user_project_wrapper.v"
+`else
+ `include "user_project_wrapper.v"
+ `include "ariel_fpga_top_fromvhdl.v"
+`endif
diff --git a/verilog/rtl/user_defines.v b/verilog/rtl/user_defines.v
new file mode 100644
index 0000000..91dad5d
--- /dev/null
+++ b/verilog/rtl/user_defines.v
@@ -0,0 +1,90 @@
+// SPDX-FileCopyrightText: 2022 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+`default_nettype none
+
+`ifndef __USER_DEFINES_H
+// User GPIO initial configuration parameters
+`define __USER_DEFINES_H
+
+// deliberately erroneous placeholder value; user required to config GPIO's to other
+`define GPIO_MODE_INVALID 13'hXXXX
+
+// Authoritive source of these MODE defs is: caravel/verilog/rtl/user_defines.v
+// Useful GPIO mode values. These match the names used in defs.h.
+//
+
+`define GPIO_MODE_MGMT_STD_INPUT_NOPULL 10'h007
+`define GPIO_MODE_MGMT_STD_INPUT_PULLDOWN 10'h047
+`define GPIO_MODE_MGMT_STD_INPUT_PULLUP 10'h087
+`define GPIO_MODE_MGMT_STD_OUTPUT 10'h00b
+`define GPIO_MODE_MGMT_STD_BIDIRECTIONAL 10'h009
+
+`define GPIO_MODE_USER_STD_INPUT_NOPULL 10'h006
+`define GPIO_MODE_USER_STD_INPUT_PULLDOWN 10'h046
+`define GPIO_MODE_USER_STD_INPUT_PULLUP 10'h086
+`define GPIO_MODE_USER_STD_OUTPUT 10'h00a
+`define GPIO_MODE_USER_STD_BIDIRECTIONAL 10'h008
+
+// The power-on configuration for GPIO 0 to 4 is fixed and cannot be
+// modified (allowing the SPI and debug to always be accessible unless
+// overridden by a flash program).
+
+// The values below can be any of the standard types defined above,
+// or they can be any 13-bit value if the user wants a non-standard
+// startup state for the GPIO. By default, every GPIO from 5 to 37
+// is set to power up as an input controlled by the management SoC.
+// Users may want to redefine these so that the user project powers
+// up in a state that can be used immediately without depending on
+// the management SoC to run a startup program to configure the GPIOs.
+
+`define USER_CONFIG_GPIO_5_INIT `GPIO_MODE_USER_STD_BIDIRECTIONAL
+`define USER_CONFIG_GPIO_6_INIT `GPIO_MODE_USER_STD_BIDIRECTIONAL
+`define USER_CONFIG_GPIO_7_INIT `GPIO_MODE_USER_STD_BIDIRECTIONAL
+`define USER_CONFIG_GPIO_8_INIT `GPIO_MODE_USER_STD_BIDIRECTIONAL
+`define USER_CONFIG_GPIO_9_INIT `GPIO_MODE_USER_STD_BIDIRECTIONAL
+`define USER_CONFIG_GPIO_10_INIT `GPIO_MODE_USER_STD_BIDIRECTIONAL
+`define USER_CONFIG_GPIO_11_INIT `GPIO_MODE_USER_STD_BIDIRECTIONAL
+`define USER_CONFIG_GPIO_12_INIT `GPIO_MODE_USER_STD_BIDIRECTIONAL
+`define USER_CONFIG_GPIO_13_INIT `GPIO_MODE_USER_STD_BIDIRECTIONAL
+
+// Configurations of GPIO 14 to 24 are used on caravel but not caravan.
+`define USER_CONFIG_GPIO_14_INIT `GPIO_MODE_USER_STD_BIDIRECTIONAL
+`define USER_CONFIG_GPIO_15_INIT `GPIO_MODE_USER_STD_BIDIRECTIONAL
+`define USER_CONFIG_GPIO_16_INIT `GPIO_MODE_USER_STD_BIDIRECTIONAL
+`define USER_CONFIG_GPIO_17_INIT `GPIO_MODE_USER_STD_BIDIRECTIONAL
+`define USER_CONFIG_GPIO_18_INIT `GPIO_MODE_USER_STD_BIDIRECTIONAL
+`define USER_CONFIG_GPIO_19_INIT `GPIO_MODE_USER_STD_BIDIRECTIONAL
+`define USER_CONFIG_GPIO_20_INIT `GPIO_MODE_USER_STD_BIDIRECTIONAL
+`define USER_CONFIG_GPIO_21_INIT `GPIO_MODE_USER_STD_BIDIRECTIONAL
+`define USER_CONFIG_GPIO_22_INIT `GPIO_MODE_USER_STD_BIDIRECTIONAL
+`define USER_CONFIG_GPIO_23_INIT `GPIO_MODE_USER_STD_BIDIRECTIONAL
+`define USER_CONFIG_GPIO_24_INIT `GPIO_MODE_USER_STD_BIDIRECTIONAL
+
+`define USER_CONFIG_GPIO_25_INIT `GPIO_MODE_USER_STD_BIDIRECTIONAL
+`define USER_CONFIG_GPIO_26_INIT `GPIO_MODE_USER_STD_BIDIRECTIONAL
+`define USER_CONFIG_GPIO_27_INIT `GPIO_MODE_USER_STD_BIDIRECTIONAL
+`define USER_CONFIG_GPIO_28_INIT `GPIO_MODE_USER_STD_BIDIRECTIONAL
+`define USER_CONFIG_GPIO_29_INIT `GPIO_MODE_USER_STD_BIDIRECTIONAL
+`define USER_CONFIG_GPIO_30_INIT `GPIO_MODE_USER_STD_BIDIRECTIONAL
+`define USER_CONFIG_GPIO_31_INIT `GPIO_MODE_USER_STD_BIDIRECTIONAL
+`define USER_CONFIG_GPIO_32_INIT `GPIO_MODE_USER_STD_BIDIRECTIONAL
+`define USER_CONFIG_GPIO_33_INIT `GPIO_MODE_USER_STD_BIDIRECTIONAL
+`define USER_CONFIG_GPIO_34_INIT `GPIO_MODE_USER_STD_BIDIRECTIONAL
+`define USER_CONFIG_GPIO_35_INIT `GPIO_MODE_USER_STD_BIDIRECTIONAL
+`define USER_CONFIG_GPIO_36_INIT `GPIO_MODE_USER_STD_BIDIRECTIONAL
+`define USER_CONFIG_GPIO_37_INIT `GPIO_MODE_USER_STD_BIDIRECTIONAL
+
+`endif // __USER_DEFINES_H
diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v
new file mode 100644
index 0000000..78058ac
--- /dev/null
+++ b/verilog/rtl/user_project_wrapper.v
@@ -0,0 +1,90 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+`default_nettype none
+`define MPRJ_IO_PADS 38
+/*
+ *-------------------------------------------------------------
+ *
+ * user_project_wrapper
+ *
+ * This wrapper enumerates all of the pins available to the
+ * user for the user project.
+ *
+ *-------------------------------------------------------------
+ */
+
+module user_project_wrapper #(
+ parameter BITS = 32
+)(
+`ifdef USE_POWER_PINS
+ inout vdd, // User area 5.0V supply
+ inout vss, // User area ground
+`endif
+
+ // Wishbone Slave ports (WB MI A)
+ input wb_clk_i,
+ input wb_rst_i,
+ input wbs_stb_i,
+ input wbs_cyc_i,
+ input wbs_we_i,
+ input [3:0] wbs_sel_i,
+ input [31:0] wbs_dat_i,
+ input [31:0] wbs_adr_i,
+ output wbs_ack_o,
+ output [31:0] wbs_dat_o,
+
+ // Logic Analyzer Signals
+ input [63:0] la_data_in,
+ output [63:0] la_data_out,
+ input [63:0] la_oenb,
+
+ // IOs
+ input [`MPRJ_IO_PADS-1:0] io_in,
+ output [`MPRJ_IO_PADS-1:0] io_out,
+ output [`MPRJ_IO_PADS-1:0] io_oeb,
+
+ // Independent clock (on independent integer divider)
+ input user_clock2,
+
+ // User maskable interrupt signals
+ output [2:0] user_irq
+);
+
+/*--------------------------------------*/
+/* User project is instantiated here */
+/*--------------------------------------*/
+
+ariel_fpga_top ariel_fpga_top_inst (
+ .wb_clk_i(wb_clk_i),
+ .wb_rst_i(wb_rst_i),
+ .wbs_stb_i(wbs_stb_i),
+ .wbs_cyc_i(wbs_cyc_i),
+ .wbs_we_i(wbs_we_i),
+ .wbs_dat_i(wbs_dat_i),
+ .wbs_adr_i(wbs_adr_i),
+ .wbs_ack_o(wbs_ack_o),
+ .wbs_dat_o(wbs_dat_o),
+ .la_data_in(la_data_in),
+ .la_data_out(la_data_out),
+ .la_oenb(la_oenb),
+ .io_in(io_in),
+ .io_out(io_out),
+ .io_oeb(io_oeb),
+ .user_clock2(user_clock2),
+ .user_irq(user_irq)
+ );
+
+endmodule // user_project_wrapper
