| /root/hyperram_controller/lib/user_proj_example.lib |
| /root/hyperram_controller/lib/user_project_wrapper.lib |
| /root/hyperram_controller/openlane/wrapped_wb_hyperram/config.tcl |
| /root/hyperram_controller/sdc/user_proj_example.sdc |
| /root/hyperram_controller/sdc/user_project_wrapper.sdc |
| /root/hyperram_controller/sdf/user_proj_example.sdf |
| /root/hyperram_controller/sdf/user_project_wrapper.sdf |
| /root/hyperram_controller/sdf/multicorner/nom/user_project_wrapper.ff.sdf |
| /root/hyperram_controller/sdf/multicorner/nom/user_project_wrapper.ss.sdf |
| /root/hyperram_controller/sdf/multicorner/nom/user_project_wrapper.tt.sdf |
| /root/hyperram_controller/spef/user_proj_example.spef |
| /root/hyperram_controller/spef/user_project_wrapper.spef |
| /root/hyperram_controller/spef/multicorner/user_project_wrapper.nom.spef |
| /root/hyperram_controller/verilog/includes/includes.gl+sdf.caravel_user_project |
| /root/hyperram_controller/verilog/includes/includes.gl.caravel_user_project |
| /root/hyperram_controller/verilog/includes/includes.rtl.caravel_user_project |
| /root/hyperram_controller/verilog/rtl/wrapped_wb_hyperram.v |
| /root/hyperram_controller/verilog/rtl/wb_hyperram/Makefile |
| /root/hyperram_controller/verilog/rtl/wb_hyperram/config.tcl |
| /root/hyperram_controller/verilog/rtl/wb_hyperram/sky130A_sky130_fd_sc_hd_config.tcl |
| /root/hyperram_controller/verilog/rtl/wb_hyperram/verible.rules |
| /root/hyperram_controller/verilog/rtl/wb_hyperram/wb_hyperram.gtkw |
| /root/hyperram_controller/verilog/rtl/wb_hyperram/picosoc/Makefile |
| /root/hyperram_controller/verilog/rtl/wb_hyperram/picosoc/firmware.c |
| /root/hyperram_controller/verilog/rtl/wb_hyperram/picosoc/ice40up5k_spram.v |
| /root/hyperram_controller/verilog/rtl/wb_hyperram/picosoc/picorv32.v |
| /root/hyperram_controller/verilog/rtl/wb_hyperram/picosoc/picosoc.v |
| /root/hyperram_controller/verilog/rtl/wb_hyperram/picosoc/sections.lds |
| /root/hyperram_controller/verilog/rtl/wb_hyperram/picosoc/simpleuart.v |
| /root/hyperram_controller/verilog/rtl/wb_hyperram/picosoc/spiflash.v |
| /root/hyperram_controller/verilog/rtl/wb_hyperram/picosoc/spimemio.v |
| /root/hyperram_controller/verilog/rtl/wb_hyperram/picosoc/start.s |
| /root/hyperram_controller/verilog/rtl/wb_hyperram/picosoc/upduino.pcf |
| /root/hyperram_controller/verilog/rtl/wb_hyperram/picosoc/upduino.sv |
| /root/hyperram_controller/verilog/rtl/wb_hyperram/picosoc/upduino_tb.v |
| /root/hyperram_controller/verilog/rtl/wb_hyperram/sby/hyperram.sby |
| /root/hyperram_controller/verilog/rtl/wb_hyperram/sby/register.sby |
| /root/hyperram_controller/verilog/rtl/wb_hyperram/sby/wb_hyperram.sby |
| /root/hyperram_controller/verilog/rtl/wb_hyperram/src/hyperram.sv |
| /root/hyperram_controller/verilog/rtl/wb_hyperram/src/register_rw.v |
| /root/hyperram_controller/verilog/rtl/wb_hyperram/src/wb_hyperram.sv |
| /root/hyperram_controller/verilog/rtl/wb_hyperram/test/dump_test_top.v |
| /root/hyperram_controller/verilog/rtl/wb_hyperram/test/test_top.v |
| /root/hyperram_controller/verilog/rtl/wb_hyperram/test/test_wb_hyperram.py |
| /root/hyperram_controller/verilog/rtl/wb_hyperram/test/wb_master.py |
| /root/hyperram_controller/verilog/rtl/wb_hyperram/test/s27kl0641/model/s27kl0641.mem |
| /root/hyperram_controller/verilog/rtl/wb_hyperram/test/s27kl0641/model/s27kl0641.v |
