| Luca Horn | 0db7050 | 2022-12-06 09:32:03 +0100 | [diff] [blame] | 1 | import cocotb |
| 2 | import random |
| 3 | from cocotb.clock import Clock |
| 4 | from cocotb.triggers import Timer, ClockCycles |
| 5 | |
| 6 | @cocotb.test() |
| 7 | async def test_cpu(dut): |
| 8 | dut._log.info("start") |
| 9 | |
| 10 | memory = [0] * 8192 |
| 11 | |
| 12 | with open("test.bin", mode='rb') as file: |
| 13 | for i in range(0, 8192): |
| 14 | a = file.read(1) |
| 15 | if len(a) > 0: |
| 16 | memory[i] = a[0] |
| 17 | |
| 18 | dut.sense.value = 0 |
| 19 | dut.dbus_in.value = 0 |
| 20 | dut.reset.value = 1 |
| 21 | clock = Clock(dut.clk, 1, units="us") |
| 22 | cocotb.start_soon(clock.start()) |
| 23 | await ClockCycles(dut.clk, 3) |
| 24 | dut.reset.value = 0 |
| 25 | |
| 26 | d_counter = 0 |
| 27 | c_counter = 0 |
| 28 | expected_io_out_d = [55, 66, 10] |
| 29 | expected_io_out_c = [12, 38, 33] |
| 30 | d_out_counter = 0 |
| 31 | c_out_counter = 0 |
| 32 | tt = 0 |
| 33 | while dut.as2650.halted == 0: |
| 34 | await Timer(0.25, units="us") |
| 35 | tt += 1 |
| 36 | dut.dbus_in.value = 0 |
| 37 | if dut.oeb.value == 0: |
| 38 | if dut.rw.value == 1 and dut.opreq.value == 1 and dut.wrp.value == 1: |
| 39 | if dut.m_io == 1: |
| 40 | memory[dut.adr.value] = dut.dbus_out.value |
| 41 | else: |
| 42 | if dut.wrp.value == 1: |
| 43 | if dut.d_c.value == 1: |
| 44 | assert dut.dbus_out.value == expected_io_out_d[d_out_counter] |
| 45 | if tt % 5 == 4: |
| 46 | d_out_counter += 1 |
| 47 | else: |
| 48 | assert dut.dbus_out.value == expected_io_out_c[c_out_counter] |
| 49 | if tt % 5 == 4: |
| 50 | c_out_counter += 1 |
| 51 | else: |
| 52 | if dut.rw.value == 0 and dut.opreq.value == 1: |
| 53 | if dut.m_io.value == 1: |
| 54 | dut.dbus_in.value = memory[dut.adr.value] |
| 55 | else: |
| 56 | if dut.d_c.value == 1: |
| 57 | dut.dbus_in.value = d_counter |
| 58 | if tt % 4 == 3: |
| 59 | d_counter += 1 |
| 60 | else: |
| 61 | dut.dbus_in.value = c_counter |
| 62 | if tt % 4 == 3: |
| 63 | c_counter += 2 |
| 64 | |
| 65 | assert memory[8191] == 0x16 |
| 66 | assert memory[8190] == 0xFF |
| 67 | assert memory[8189] == 0x16 |
| 68 | assert memory[8191-7] == 70 |
| 69 | assert memory[8191-8] == 3 |
| 70 | assert memory[8191-9] == 6 |
| 71 | assert memory[8191-10] == 66 |
| 72 | assert memory[8191-11] == 11 |
| 73 | assert memory[8191-12] == 0b01010101 |
| 74 | assert memory[8191-13] == 0b10001111 |
| 75 | assert memory[8191-14] == 24 |
| 76 | assert memory[8191-15] == 2 |
| 77 | assert memory[8191-16] == 1 |
| 78 | assert memory[8191-17] == 2 |
| 79 | assert memory[8191-18] == 2 |
| 80 | assert memory[8191-19] == 2 |
| 81 | assert memory[8191-20] == 1 |
| 82 | assert memory[8191-21] == 8 |
| 83 | assert memory[8191-22] == 0b11111101 |
| 84 | assert memory[8191-23] == 15 |
| 85 | assert memory[8191-24] == 0b11111101 |
| 86 | assert memory[8191-25] == 14 |
| 87 | assert memory[8191-26] == 10 |
| 88 | assert memory[8191-27] == 20 |
| 89 | assert memory[8191-28] == 6 |
| 90 | assert memory[8191-29] == 96 |
| 91 | assert memory[8191-30] == 0b10000111 |
| 92 | assert memory[8191-31] == 0b00001111 |
| 93 | assert memory[8191-32] == 0b00000111 |
| 94 | assert memory[8191-33] == 0b10000011 |
| 95 | assert memory[8191-34] == 0b00000001 |
| 96 | assert memory[8191-35] == 0b00000010 |
| 97 | assert memory[8191-36] == 0b00001001 |
| 98 | assert memory[8191-37] == 0 |
| 99 | assert memory[8191-38] == 0 |
| 100 | assert memory[8191-39] == 0b10000000 |
| 101 | assert memory[8191-40] == 0 |
| 102 | assert memory[8191-41] == 0b10000000 |
| 103 | assert memory[8191-42] == 55 |
| 104 | assert memory[8191-43] == 5 |
| 105 | assert memory[8191-44] == 4 |
| 106 | assert memory[8191-45] == 3 |
| 107 | assert memory[8191-46] == 103 |
| 108 | assert memory[8191-47] == 180 |
| 109 | assert memory[8191-48] == 0b01000000 |
| 110 | assert memory[8191-49] == 220 |
| 111 | assert memory[8191-50] == 5 |
| 112 | assert memory[8191-51] == 8 |
| 113 | assert memory[8191-52] == 5 |
| 114 | assert memory[8191-53] == 8 |
| 115 | assert memory[8191-54] == 0 |
| 116 | assert memory[8191-55] == 0b01000000 |
| 117 | assert memory[8191-56] == 0b10000000 |
| 118 | assert memory[8191-57] == 0b01000000 |
| 119 | assert memory[8191-58] == 0b10000000 |
| 120 | assert memory[8191-59] == 0 |
| 121 | assert memory[8191-60] == 1 |
| 122 | assert memory[8191-61] == 2 |
| 123 | assert memory[8191-62] == 3 |
| 124 | assert memory[8191-63] == 4 |
| 125 | assert memory[8191-64] == 5 |
| 126 | assert memory[8191-65] == 6 |
| 127 | assert memory[8191-66] == 16 |
| 128 | assert memory[8191-67] == 15 |
| 129 | assert memory[8191-68] == 7 |
| 130 | assert memory[8191-69] == 6 |
| 131 | assert memory[8191-70] == 40 |
| 132 | assert memory[8191-71] == 40 |
| Luca Horn | 475a75f | 2022-12-06 16:16:36 +0100 | [diff] [blame] | 133 | assert memory[8191-72] == 100 |
| 134 | assert memory[8191-73] == 200 |
