| Cocogoat | 511a562 | 2022-12-02 20:52:47 -0500 | [diff] [blame] | 1 | // SPDX-FileCopyrightText: 2020 Efabless Corporation |
| 2 | // |
| 3 | // Licensed under the Apache License, Version 2.0 (the "License"); |
| 4 | // you may not use this file except in compliance with the License. |
| 5 | // You may obtain a copy of the License at |
| 6 | // |
| 7 | // http://www.apache.org/licenses/LICENSE-2.0 |
| 8 | // |
| 9 | // Unless required by applicable law or agreed to in writing, software |
| 10 | // distributed under the License is distributed on an "AS IS" BASIS, |
| 11 | // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| 12 | // See the License for the specific language governing permissions and |
| 13 | // limitations under the License. |
| 14 | // SPDX-License-Identifier: Apache-2.0 |
| 15 | |
| 16 | `default_nettype none |
| 17 | |
| 18 | `ifndef __GLOBAL_DEFINE_H |
| 19 | // Global parameters |
| 20 | `define __GLOBAL_DEFINE_H |
| 21 | |
| 22 | `define MPRJ_IO_PADS_1 19 /* number of user GPIO pads on user1 side */ |
| 23 | `define MPRJ_IO_PADS_2 19 /* number of user GPIO pads on user2 side */ |
| 24 | `define MPRJ_IO_PADS (`MPRJ_IO_PADS_1 + `MPRJ_IO_PADS_2) |
| 25 | |
| 26 | `define MPRJ_PWR_PADS_1 2 /* vdda1, vccd1 enable/disable control */ |
| 27 | `define MPRJ_PWR_PADS_2 2 /* vdda2, vccd2 enable/disable control */ |
| 28 | `define MPRJ_PWR_PADS (`MPRJ_PWR_PADS_1 + `MPRJ_PWR_PADS_2) |
| 29 | |
| 30 | // Analog pads are only used by the "caravan" module and associated |
| 31 | // modules such as user_analog_project_wrapper and chip_io_alt. |
| 32 | |
| 33 | `define ANALOG_PADS_1 5 |
| 34 | `define ANALOG_PADS_2 6 |
| 35 | |
| 36 | `define ANALOG_PADS (`ANALOG_PADS_1 + `ANALOG_PADS_2) |
| 37 | |
| 38 | // Size of soc_mem_synth |
| 39 | |
| 40 | // Type and size of soc_mem |
| 41 | // `define USE_OPENRAM |
| 42 | `define USE_CUSTOM_DFFRAM |
| 43 | // don't change the following without double checking addr widths |
| 44 | `define MEM_WORDS 256 |
| 45 | |
| 46 | // Number of columns in the custom memory; takes one of three values: |
| 47 | // 1 column : 1 KB, 2 column: 2 KB, 4 column: 4KB |
| 48 | `define DFFRAM_WSIZE 4 |
| 49 | `define DFFRAM_USE_LATCH 0 |
| 50 | |
| 51 | // not really parameterized but just to easily keep track of the number |
| 52 | // of ram_block across different modules |
| 53 | `define RAM_BLOCKS 1 |
| 54 | |
| 55 | // Clock divisor default value |
| 56 | `define CLK_DIV 3'b010 |
| 57 | |
| 58 | // GPIO control default mode and enable for most I/Os |
| 59 | // Most I/Os set to be user input pins on startup. |
| 60 | // NOTE: To be modified, with GPIOs 5 to 35 being set from a build-time- |
| 61 | // programmable block. |
| 62 | `define MGMT_INIT 1'b0 |
| 63 | `define OENB_INIT 1'b0 |
| 64 | `define DM_INIT 3'b001 |
| 65 | |
| 66 | `endif // __GLOBAL_DEFINE_H |
