Merged Lanes

Merged Minx16 into UserProjectExample openlane scripts for CPU build flow. Simulated Dflop mem for ram macros. Macro ram to be included in near future
7 files changed
tree: faafc42b20112d4eb9843f6c54fd1c2a09f6563a
  1. .github/
  2. def/
  3. docs/
  4. gds/
  5. lef/
  6. mag/
  7. maglef/
  8. openlane/
  9. signoff/
  10. spi/
  11. verilog/
  12. .gitignore
  13. LICENSE
  14. Makefile
  15. README.md
README.md

Caravel User Project

License UPRJ_CI Caravel Build

:exclamation: Important Note

Refer to README for a quickstart of how to use caravel_user_project Refer to README for this sample project documentation.

:exclamation: Important MAKE!

This design uses design rules for the gf180mcuC PDK.

This project implements a 16 bit RISC themed processor for educational purposes.

Since the number of IO pins are limited the Address/Databus are merged into a single external bus.

More documentation to come in the following days!