)]}'
{
  "commit": "6e89603d8cc0439d0abb944aac1b841ce45182f2",
  "tree": "faafc42b20112d4eb9843f6c54fd1c2a09f6563a",
  "parents": [
    "52b43df305d38ae16c989835a0c3e70e9150dd84"
  ],
  "author": {
    "name": "Ryan Price",
    "email": "91754608+RyanMPrice@users.noreply.github.com",
    "time": "Wed Nov 16 14:20:43 2022 -0700"
  },
  "committer": {
    "name": "Ryan Price",
    "email": "91754608+RyanMPrice@users.noreply.github.com",
    "time": "Wed Nov 16 14:20:43 2022 -0700"
  },
  "message": "Merged Lanes\n\nMerged Minx16 into UserProjectExample openlane scripts for CPU build flow. Simulated Dflop mem for ram macros. Macro ram to be included in near future\n",
  "tree_diff": [
    {
      "type": "delete",
      "old_id": "055b66d4a697f7e6598e8d2a5f2a19b97341d0aa",
      "old_mode": 33188,
      "old_path": "openlane/user_Minx16/config.json",
      "new_id": "0000000000000000000000000000000000000000",
      "new_mode": 0,
      "new_path": "/dev/null"
    },
    {
      "type": "delete",
      "old_id": "d1567a83769c158308c3b0549b53ee2134b00c37",
      "old_mode": 33188,
      "old_path": "openlane/user_Minx16/macro.cfg",
      "new_id": "0000000000000000000000000000000000000000",
      "new_mode": 0,
      "new_path": "/dev/null"
    },
    {
      "type": "delete",
      "old_id": "603257af534d08fd9d295cf29b2dda86db24dd49",
      "old_mode": 33188,
      "old_path": "openlane/user_Minx16/pin_order.cfg",
      "new_id": "0000000000000000000000000000000000000000",
      "new_mode": 0,
      "new_path": "/dev/null"
    },
    {
      "type": "modify",
      "old_id": "370d74cd464b7befbc6c610f1f065b472187cb54",
      "old_mode": 33188,
      "old_path": "openlane/user_proj_example/config.json",
      "new_id": "dc0104c6f7a659df21d9628cdee01433932b87a5",
      "new_mode": 33188,
      "new_path": "openlane/user_proj_example/config.json"
    },
    {
      "type": "modify",
      "old_id": "2fda806ab62cbe43d3a6b2844e4bab975333e67b",
      "old_mode": 33188,
      "old_path": "openlane/user_proj_example/pin_order.cfg",
      "new_id": "c6f0dc8c4ef88e9aafe37ed25c8455162821d2ba",
      "new_mode": 33188,
      "new_path": "openlane/user_proj_example/pin_order.cfg"
    },
    {
      "type": "modify",
      "old_id": "0327be06e882962cebd6d36d18969238e0e0ef08",
      "old_mode": 33188,
      "old_path": "verilog/rtl/Minx16/scb.v",
      "new_id": "a6527190b81db03cd7ba60a3155514648da3d3d9",
      "new_mode": 33188,
      "new_path": "verilog/rtl/Minx16/scb.v"
    },
    {
      "type": "modify",
      "old_id": "95654f80637cc7c9b9f6fa31639ceace218817f1",
      "old_mode": 33188,
      "old_path": "verilog/rtl/user_proj_example.v",
      "new_id": "f07e702464e6fbffa930f91e5b675e220b3e23c9",
      "new_mode": 33188,
      "new_path": "verilog/rtl/user_proj_example.v"
    }
  ]
}