| { |
| "DESIGN_NAME": "Minx16Top", |
| "DESIGN_IS_CORE": 0, |
| "VERILOG_FILES": ["dir::../../verilog/rtl/defines.v", "dir::../../verilog/rtl/Minx16/*"], |
| "MACRO_PLACEMENT_CFG": "dir::macro.cfg", |
| "VERILOG_FILES_BLACKBOX": ["dir::../../verilog/rtl/gf180mcu_fd_ip_sram/gf180mcu_fd_ip_sram__sram512x8m8wm1.v"], |
| "EXTRA_LEFS": "dir::../../lef/gf180mcu_fd_ip_sram__sram512x8m8wm1.lef", |
| "EXTRA_GDS_FILES": "dir::../../gds/gf180mcu_fd_ip_sram__sram512x8m8wm1.gds", |
| "CLOCK_PERIOD": 100, |
| "CLOCK_PORT": "clk_i", |
| "CLOCK_NET": "Minx16Top.clk_i", |
| "FP_SIZING": "absolute", |
| "DIE_AREA": "0 0 2000 2000", |
| "FP_PIN_ORDER_CFG": "dir::pin_order.cfg", |
| "PL_BASIC_PLACEMENT": 0, |
| "PL_TARGET_DENSITY": 0.50, |
| "VDD_NETS": ["vccd1"], |
| "GND_NETS": ["vssd1"], |
| "DIODE_INSERTION_STRATEGY": 4, |
| "RUN_CVC": 1, |
| "pdk::sky130*": { |
| "FP_CORE_UTIL": 45, |
| "RT_MAX_LAYER": "met4", |
| "scl::sky130_fd_sc_hd": { |
| "CLOCK_PERIOD": 10 |
| }, |
| "scl::sky130_fd_sc_hdll": { |
| "CLOCK_PERIOD": 10 |
| }, |
| "scl::sky130_fd_sc_hs": { |
| "CLOCK_PERIOD": 8 |
| }, |
| "scl::sky130_fd_sc_ls": { |
| "CLOCK_PERIOD": 10, |
| "SYNTH_MAX_FANOUT": 5 |
| }, |
| "scl::sky130_fd_sc_ms": { |
| "CLOCK_PERIOD": 10 |
| } |
| }, |
| "pdk::gf180mcuC": { |
| "STD_CELL_LIBRARY": "gf180mcu_fd_sc_mcu7t5v0", |
| "CLOCK_PERIOD": 50.0, |
| "FP_CORE_UTIL": 40, |
| "RT_MAX_LAYER": "Metal4", |
| "SYNTH_MAX_FANOUT": 4, |
| "PL_TARGET_DENSITY": 0.45 |
| } |
| } |
