change VDD VSS
diff --git a/openlane/computer/config.tcl b/openlane/computer/config.tcl
index 2574945..a09ebb0 100644
--- a/openlane/computer/config.tcl
+++ b/openlane/computer/config.tcl
@@ -70,8 +70,8 @@
set ::env(FP_PIN_ORDER_CFG) $::env(DESIGN_DIR)/pin_order.cfg
-set ::env(VDD_NETS) [list {vccd1}]
-set ::env(GND_NETS) [list {vssd1}]
+set ::env(VDD_NETS) [list {vdd}]
+set ::env(GND_NETS) [list {vss}]
set ::env(DIODE_INSERTION_STRATEGY) 4
diff --git a/verilog/rtl/jacaranda-8/computer.v b/verilog/rtl/jacaranda-8/computer.v
index f22512f..82f4d94 100644
--- a/verilog/rtl/jacaranda-8/computer.v
+++ b/verilog/rtl/jacaranda-8/computer.v
@@ -16,8 +16,8 @@
module computer(
`ifdef USE_POWER_PINS
- inout vccd1, // User area 1 1.8V supply
- inout vssd1, // User area 1 digital ground
+ inout vdd, // User area 1 1.8V supply
+ inout vss, // User area 1 digital ground
`endif
input wb_clk_i,
input wb_rst_i,
diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v
index 1d44c90..9e57fb9 100644
--- a/verilog/rtl/user_project_wrapper.v
+++ b/verilog/rtl/user_project_wrapper.v
@@ -33,14 +33,8 @@
parameter BITS = 32
) (
`ifdef USE_POWER_PINS
- inout vdda1, // User area 1 3.3V supply
- inout vdda2, // User area 2 3.3V supply
- inout vssa1, // User area 1 analog ground
- inout vssa2, // User area 2 analog ground
- inout vccd1, // User area 1 1.8V supply
- inout vccd2, // User area 2 1.8v supply
- inout vssd1, // User area 1 digital ground
- inout vssd2, // User area 2 digital ground
+ inout vdd, // User area 5.0V supply
+ inout vss, // User area GND
`endif
// Wishbone Slave ports (WB MI A)
@@ -85,8 +79,8 @@
//user_proj_example mprj (
computer computer (
`ifdef USE_POWER_PINS
- .vccd1(vccd1), // User area 1 1.8V power
- .vssd1(vssd1), // User area 1 digital ground
+ .vdd(vdd), // User area 1 1.8V power
+ .vss(vss), // User area 1 digital ground
`endif
.wb_clk_i(wb_clk_i),
.wb_rst_i(wb_rst_i),
