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Caravel User Project

License UPRJ_CI Caravel Build

Jacaranda-8: 8bit CPU

Jacaranda-8 is educational ISA for home-build CPU beginners. This project implements the microarchitecture: CHARLATAN which is a simple implementation of Jacaranda-8 ISA.The following table shows the specifications of this CPU.

Jacaranda-8

itemvalue
microarchitectureCHARLATAN
data bus width8bit
instruction bus width8bit
memory address bus width8bit
architecture typeharvard architecture, RISC
number of general purpose register4
I/Omemory mapped
Interruptionenabled
Instruction typefield
reg-imm load/storeop[3:0] imm[3:0]
reg-reg movop[3:0] rd[1:0] rs[1:0]
reg-reg calop[3:0] rd[1:0] rs[1:0]
jump/branchop[3:0] mode[1:0] rs[1:0]
reg-mem load/storeop[3:0] rd[1:0] rs[1:0]
registerstype
pcprogram counter
flagcomparison flag
r0general purpose
r1general purpose
r2general purpose
r3general purpose/immediate load
NumberInstruction namemnemonic76543210pesudo code
0Movemov rd, rs0000rd_index[1]rd_index[0]rs_index[1]rs_index[0]rd[7:0] = rs[7:0], PC += 1
1Addadd rd, rs0001rd_index[1]rd_index[0]rs_index[1]rs_index[0]rd[7:0] = rd[7:0] + rs[7:0], PC += 1
2Substructsub rd, rs0010rd_index[1]rd_index[0]rs_index[1]rs_index[0]rd[7:0] = rd[7:0] - rs[7:0], PC += 1
3Andand rd, rs0011rd_index[1]rd_index[0]rs_index[1]rs_index[0]rd[7:0] = rd[7:0] & rs[7:0], PC += 1
4Oror rd, rs0100rd_index[1]rd_index[0]rs_index[1]rs_index[0]rd[7:0] = rd[7:0] | rs[7:0], PC += 1
5Notnot rd, rs0101rd_index[1]rd_index[0]rs_index[1]rs_index[0]rd[7:0] = !rs[7:0], PC += 1
6Shift Left Logicalsll rd, rs0110rd_index[1]rd_index[0]rs_index[1]rs_index[0]rd[7:0] = rd[7:0] << rs[7:0], PC += 1
7Shift Right Logicalsrl rd, rs0111rd_index[1]rd_index[0]rs_index[1]rs_index[0]rd[7:0] = rd[7:0] >> rs[7:0], PC += 1
8Shift Right Arithmeticsra rd, rs1000rd_index[1]rd_index[0]rs_index[1]rs_index[0]rd[7:0] = rd[7:0] >>> rs[7:0], PC += 1
9Comparecmp rd, rs1001rd_index[1]rd_index[0]rs_index[1]rs_index[0]flag = rd[7:0] == rs[7:0], PC += 1
10Jump equalje rs101000rs_index[1]rs_index[0]PC = flag ? rs[7:0] : PC += 1
11Jumpjmp rs101100rs_index[1]rs_index[0]PC = rs[7:0]
12Load Immediate Highldih imm1100imm[3]imm[2]imm[1]imm[0]imm_register[7:4] = imm[3:0], PC += 1
13Load Immediate Lowldil imm1101imm[3]imm[2]imm[1]imm[0]imm_register[3:0] = imm[3:0], PC += 1
14Loadld rd, rs1110rd_index[1]rd_index[0]rs_index[1]rs_index[0]rd[7:0] = mem[rs[7:0]], PC += 1
15Storest rd, rs1111rd_index[1]rd_index[0]rs_index[1]rs_index[0]mem[rs[7:0]] = rd[7:0], PC += 1
16Interrupt Returniret10110100PC = retaddr

project build guide

Jacaranda-8 programming guide

You can program your Jacaranda-8 machine code from the management SoC by Wishbone bus.

addressfunction
0x3000_0000IMEM_WRITE
0x3000_0004UART_CLK_FREQ

IMEM_WRITE

  • bits[7:0] for data that will be contained in the instruction memory.
  • bits[15:8] for address that indicates address in the instruction memory.

UART_CLK_FREQ

put board's clock frequency

Jacaranda MMapped I/O summary

addressdescriptionnote
255UART FLAG REGISTER 1(UFR1)
254UART FLAG REGISTER 2(UFR2)read only
253UART TX DATA(UTD)
252UART RX DATA(URD)read only
251GPIO OUT
250interrupt vector
249GPIO INread only