| commit | a65826831fd5a8f6654f06627d8dbd31257b0195 | [log] [tgz] |
|---|---|---|
| author | Cra2yPierr0t <uchiyama.kazuhide@gmail.com> | Fri Dec 02 17:31:45 2022 +0900 |
| committer | Cra2yPierr0t <uchiyama.kazuhide@gmail.com> | Fri Dec 02 17:31:45 2022 +0900 |
| tree | 2623c78ba59e18d4af97f89cf7f644a795309190 | |
| parent | b4001e0084a60f22ce9f5e13021c42b4da2cc67c [diff] |
update gl verilog
diff --git a/verilog/gl/user_project_wrapper.v b/verilog/gl/user_project_wrapper.v index fd51649..8d8de27 100644 --- a/verilog/gl/user_project_wrapper.v +++ b/verilog/gl/user_project_wrapper.v
@@ -54,9 +54,7 @@ input [3:0] wbs_sel_i; - computer computer (.vccd1(vccd1), - .vssd1(vssd1), - .wb_clk_i(wb_clk_i), + computer computer (.wb_clk_i(wb_clk_i), .wb_rst_i(wb_rst_i), .wbs_ack_o(wbs_ack_o), .wbs_cyc_i(wbs_cyc_i),