commit 53d0cdafad3264c9a12e30e93973c3d8b91b8e1d
author Cra2yPierr0t <uchiyama.kazuhide@gmail.com> Mon Dec 05 16:16:30 2022 +0900
committer Cra2yPierr0t <uchiyama.kazuhide@gmail.com> Mon Dec 05 16:16:30 2022 +0900
tree cef57cdde7125f9ea5952aee4cbf7b61fd6cbd5b
parent 81ea74dc998e9d4adcca563db6cdfdd7a1012ca1

fix la width

verilog/rtl/jacaranda-8/computer.v

diff --git a/verilog/rtl/jacaranda-8/computer.v b/verilog/rtl/jacaranda-8/computer.v
index 82f4d94..4811f9c 100644
--- a/verilog/rtl/jacaranda-8/computer.v
+++ b/verilog/rtl/jacaranda-8/computer.v
@@ -30,9 +30,9 @@
     output wbs_ack_o,
     output [31:0] wbs_dat_o,
 
-    input  [127:0] la_data_in,
-    output [127:0] la_data_out,
-    input  [127:0] la_oenb,
+    input  [63:0] la_data_in,
+    output [63:0] la_data_out,
+    input  [63:0] la_oenb,
 
     input  [`MPRJ_IO_PADS-1:0] io_in,
     output [`MPRJ_IO_PADS-1:0] io_out,