commit 3c1b8e03bc7c6d16d0bf6f97ff275f4c2e7a544e
author Cra2yPierr0t <uchiyama.kazuhide@gmail.com> Fri Dec 02 17:25:25 2022 +0900
committer Cra2yPierr0t <uchiyama.kazuhide@gmail.com> Fri Dec 02 17:25:25 2022 +0900
tree c711dd2cf9bb767222b1121a01e8e49db6e5b943
parent d18451f0ef0bad7d6fb3fe3bb4660508d85c7b4b

modosu UART baud logic

verilog/rtl/jacaranda-8/UART/UART.v

diff --git a/verilog/rtl/jacaranda-8/UART/UART.v b/verilog/rtl/jacaranda-8/UART/UART.v
index 5147b35..4605876 100644
--- a/verilog/rtl/jacaranda-8/UART/UART.v
+++ b/verilog/rtl/jacaranda-8/UART/UART.v
@@ -32,14 +32,12 @@
     input wire [31:0] clk_freq
 );
 
-    parameter BAUD_RATE = 9600;
-    parameter CLK_FREQ  = 250000;
+    parameter BAUD_RATE = 115200;
 
-    //wire [31:0] clk_count_bit;
+    wire [31:0] clk_count_bit;
     reg state;
 
-    //assign clk_count_bit = clk_freq / BAUD_RATE;
-    parameter CLK_COUNT = CLK_FREQ / BAUD_RATE;
+    assign clk_count_bit = clk_freq / BAUD_RATE;
 
     always @(negedge clk) begin
         if(reset) begin
@@ -62,7 +60,7 @@
         end
     end
 
-    tx tx1(clk, reset, tx_en, begin_flag, tx_data, tx, busy_flag, CLK_COUNT);
-    rx rx1(clk, reset, rx_en, rx, rx_data, receive_flag, CLK_COUNT);
+    tx tx1(clk, reset, tx_en, begin_flag, tx_data, tx, busy_flag, clk_count_bit);
+    rx rx1(clk, reset, rx_en, rx, rx_data, receive_flag, clk_count_bit);
     
 endmodule