commit 30958854878fc09748fc81511bcc42eadf90c1b2
author Cra2yPierr0t <uchiyama.kazuhide@gmail.com> Fri Dec 02 17:27:57 2022 +0900
committer Cra2yPierr0t <uchiyama.kazuhide@gmail.com> Fri Dec 02 17:27:57 2022 +0900
tree 69984ef5a7060eb39261a4e2aa2f472142e96bf1
parent 3c1b8e03bc7c6d16d0bf6f97ff275f4c2e7a544e

remove invalid var

openlane/user_project_wrapper/config.json

diff --git a/openlane/user_project_wrapper/config.json b/openlane/user_project_wrapper/config.json
index 81228c7..71db64e 100644
--- a/openlane/user_project_wrapper/config.json
+++ b/openlane/user_project_wrapper/config.json
@@ -5,7 +5,6 @@
     "CLOCK_PORT": "computer.wb_clk_i",
     "CLOCK_NET": "computer.wb_clk_i",
     "ROUTING_CORES": 16,
-    "FP_PDN_MACRO_HOOKS": "computer vccd1 vssd1 vccd1 vssd1",
     "MACRO_PLACEMENT_CFG": "dir::macro.cfg",
     "VERILOG_FILES_BLACKBOX": ["dir::../../verilog/rtl/defines.v", "dir::../../verilog/rtl/jacaranda-8/computer.v"],
     "EXTRA_LEFS": "dir::../../lef/computer.lef",